WO2024000325A1 - 像素电路、驱动方法和显示装置 - Google Patents

像素电路、驱动方法和显示装置 Download PDF

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Publication number
WO2024000325A1
WO2024000325A1 PCT/CN2022/102543 CN2022102543W WO2024000325A1 WO 2024000325 A1 WO2024000325 A1 WO 2024000325A1 CN 2022102543 W CN2022102543 W CN 2022102543W WO 2024000325 A1 WO2024000325 A1 WO 2024000325A1
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WIPO (PCT)
Prior art keywords
control
circuit
terminal
light
reset
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Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2022/102543
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English (en)
French (fr)
Inventor
承天一
李孟
杨中流
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
Original Assignee
BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by BOE Technology Group Co Ltd, Chengdu BOE Optoelectronics Technology Co Ltd filed Critical BOE Technology Group Co Ltd
Priority to PCT/CN2022/102543 priority Critical patent/WO2024000325A1/zh
Priority to CN202280002010.1A priority patent/CN117897761B/zh
Priority to US18/028,458 priority patent/US12236884B2/en
Publication of WO2024000325A1 publication Critical patent/WO2024000325A1/zh
Anticipated expiration legal-status Critical
Priority to US19/030,733 priority patent/US20250166571A1/en
Ceased legal-status Critical Current

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3258—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the voltage across the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0247—Flicker reduction other than flicker reduction circuits used for single beam cathode-ray tubes

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a pixel circuit, a driving method and a display device.
  • OLED Organic Light Emitting Diode
  • the threshold voltage of the driving transistor included in the pixel circuit drifts seriously, which is not conducive to improving hysteresis and affects the display effect.
  • an embodiment of the present disclosure provides a pixel circuit, including a light-emitting element, a driving circuit, an energy storage circuit, an initialization circuit and a compensation control circuit;
  • the display cycle of the pixel circuit includes a refresh frame and a hold frame;
  • the refresh frame and the holding frame respectively include a reset phase and a lighting phase set successively;
  • the energy storage circuit is electrically connected to the control end of the drive circuit and is used to store electrical energy
  • the compensation control circuit is electrically connected to the compensation control terminal, the control terminal of the drive circuit and the second terminal of the drive circuit respectively, and is used to control the compensation control signal under the control of the compensation control signal provided by the compensation control terminal.
  • the control end of the drive circuit is connected to the second end of the drive circuit;
  • the initialization circuit is electrically connected to the initial control terminal and the initial voltage terminal respectively, and the initialization circuit is electrically connected to the first terminal of the driving circuit and/or the second terminal of the driving circuit for use in the initialization process.
  • the initial voltage provided by the initial voltage terminal is controlled to be provided to the first part of the driving circuit. terminal and/or the second terminal of the driving circuit;
  • the second end of the driving circuit is electrically connected to the light-emitting element, and is used to drive the light-emitting element under the control of the potential of the control end of the driving circuit.
  • the driving transistor included in the driving circuit is a p-type transistor, and the initial voltage is a positive voltage.
  • the initialization circuit includes a first initialization sub-circuit; the initial control terminal includes a first initial control terminal, and the initial voltage terminal includes a first initial voltage terminal;
  • the first initialization sub-circuit is electrically connected to the first initial control terminal, the first initial voltage terminal and the second terminal of the drive circuit respectively, for providing the first initialization voltage at the first initial control terminal. Under the control of the initial control signal, in the refresh frame and the hold frame, at least in the reset phase, the first initial voltage provided by the first initial voltage terminal is written into the second terminal of the driving circuit .
  • the initialization circuit includes a second initialization sub-circuit; the initial control terminal includes a second initial control terminal, and the initial voltage terminal includes a second initial voltage terminal;
  • the second initialization sub-circuit is electrically connected to the second initial control terminal, the second initial voltage terminal and the first terminal of the drive circuit respectively, for second initial control provided at the second initial control terminal. Under the control of the signal, in the refresh frame and the hold frame, at least in the reset phase, the second initial voltage provided by the second initial voltage terminal is written into the first terminal of the driving circuit.
  • the initialization circuit includes a first initialization sub-circuit and a second initialization sub-circuit;
  • the initial control terminal includes a first initial control terminal and a second initial control terminal, and the initial voltage terminal includes a first initial voltage terminal. and the second initial voltage terminal;
  • the first initialization sub-circuit is electrically connected to the first initial control terminal, the first initial voltage terminal and the second terminal of the drive circuit respectively, for providing the first initialization voltage at the first initial control terminal. Under the control of the initial control signal, in the refresh frame and the hold frame, at least in the reset phase, the first initial voltage provided by the first initial voltage terminal is written into the second terminal of the driving circuit ;
  • the second initialization sub-circuit is electrically connected to the second initial control terminal, the second initial voltage terminal and the first terminal of the drive circuit respectively, for second initial control provided at the second initial control terminal. Under the control of the signal, in the refresh frame and the hold frame, at least in the reset phase, the second initial voltage provided by the second initial voltage terminal is written into the first terminal of the driving circuit.
  • the first initialization sub-circuit includes a first transistor
  • the control electrode of the first transistor is electrically connected to the first initial control terminal, the first electrode of the first transistor is electrically connected to the first initial voltage terminal, and the second electrode of the first transistor is electrically connected to the first initial control terminal.
  • the second terminal of the driving circuit is electrically connected.
  • the second initialization sub-circuit includes a second transistor
  • the control electrode of the second transistor is electrically connected to the second initial control terminal, the first electrode of the second transistor is electrically connected to the second initial voltage terminal, and the second electrode of the second transistor is electrically connected to the second initial control terminal.
  • the first end of the driving circuit is electrically connected.
  • the first initialization sub-circuit includes a first transistor
  • the second initialization sub-circuit includes a second transistor
  • the control electrode of the first transistor is electrically connected to the first initial control terminal, the first electrode of the first transistor is electrically connected to the first initial voltage terminal, and the second electrode of the first transistor is electrically connected to the first initial control terminal.
  • the second end of the driving circuit is electrically connected;
  • the control electrode of the second transistor is electrically connected to the second initial control terminal, the first electrode of the second transistor is electrically connected to the second initial voltage terminal, and the second electrode of the second transistor is electrically connected to the second initial control terminal.
  • the first end of the driving circuit is electrically connected.
  • the pixel circuit also includes a first light emission control circuit, a second light emission control circuit and a data writing circuit;
  • the first lighting control circuit is electrically connected to the first lighting control terminal, the power supply voltage terminal and the first terminal of the driving circuit respectively, for controlling the first lighting control signal provided by the first lighting control terminal. , controlling the connection between the power supply voltage terminal and the first terminal of the driving circuit;
  • the second light-emitting control circuit is electrically connected to the second light-emitting control terminal, the second terminal of the driving circuit and the first pole of the light-emitting element respectively, for providing the second light-emitting light at the second light-emitting control terminal.
  • the second terminal of the driving circuit Under the control of the control signal, the second terminal of the driving circuit is controlled to be connected to the first pole of the light-emitting element; the second pole of the light-emitting element is electrically connected to the first voltage terminal;
  • the data writing circuit is electrically connected to the writing control terminal, the data line and the first terminal of the driving circuit respectively, and is used to control the data under the control of the writing control signal provided by the writing control terminal.
  • the line is connected with the first end of the driving circuit.
  • the pixel circuit according to at least one embodiment of the present disclosure further includes a reset circuit
  • the reset circuit is electrically connected to the reset control terminal, the reset voltage terminal and the first pole of the light-emitting element respectively, and is used to control the reset voltage terminal to provide the reset voltage terminal under the control of the reset control signal provided by the reset control terminal.
  • the reset voltage is written to the first pole of the light-emitting element.
  • the compensation control circuit includes a third transistor, the first lighting control circuit includes a fourth transistor, the second lighting control circuit includes a fifth transistor, and the data writing circuit includes a sixth transistor, so
  • the drive circuit includes a drive transistor
  • the control electrode of the third transistor is electrically connected to the compensation control terminal, the first electrode of the third transistor is electrically connected to the control terminal of the drive circuit, and the second electrode of the third transistor is electrically connected to the drive circuit.
  • the second end of the circuit is electrically connected;
  • the control electrode of the fourth transistor is electrically connected to the first light-emitting control terminal, the first electrode of the fourth transistor is electrically connected to the power supply voltage terminal, and the second electrode of the fourth transistor is electrically connected to the driving The first end of the circuit is electrically connected;
  • the control electrode of the fifth transistor is electrically connected to the second light-emitting control terminal, the first electrode of the fifth transistor is electrically connected to the second terminal of the driving circuit, and the second electrode of the fifth transistor is electrically connected to The first electrode of the light-emitting element is electrically connected;
  • the control electrode of the sixth transistor is electrically connected to the write control terminal, the first electrode of the sixth transistor is electrically connected to the data line, and the second electrode of the sixth transistor is electrically connected to the first electrode of the drive circuit. terminal electrical connection;
  • the control electrode of the drive transistor is electrically connected to the control terminal of the drive circuit
  • the first electrode of the drive transistor is electrically connected to the first end of the drive circuit
  • the second electrode of the drive transistor is electrically connected to the drive circuit.
  • the second end of the circuit is electrically connected.
  • the third transistor is an oxide thin film transistor.
  • the reset circuit includes a seventh transistor
  • the control electrode of the seventh transistor is electrically connected to the reset control terminal, the first electrode of the seventh transistor is electrically connected to the reset voltage terminal, and the second electrode of the seventh transistor is electrically connected to the third terminal of the light-emitting element.
  • the seventh transistor is an oxide thin film transistor.
  • an embodiment of the present disclosure provides a driving method applied to the above-mentioned pixel circuit.
  • the display cycle of the pixel circuit includes a refresh frame and a hold frame; the refresh frame and the hold frame respectively include successive Set the reset phase and the lighting phase; the driving method includes:
  • the initialization circuit controls to provide the initial voltage provided by the initial voltage terminal to the initial control signal under the control of the initial control signal provided by the initial control terminal.
  • the initialization circuit includes a first initialization sub-circuit; the pixel circuit also includes a first light-emitting control circuit, a second light-emitting control circuit, a data writing circuit and a reset circuit; the refresh frame includes a sequentially set third An initialization phase, a first reset phase, a first charging phase, a first reset phase and a first lighting phase; the driving method includes:
  • the first initialization sub-circuit writes the first initial voltage provided by the first initial voltage terminal into the second terminal of the driving circuit under the control of the first initial control signal;
  • the compensation control circuit Under the control of the compensation control signal, the control terminal of the driving circuit is controlled to be connected to the second terminal of the driving circuit;
  • the reset circuit writes the reset voltage provided by the reset voltage terminal into the first pole of the light-emitting element under the control of the reset control signal
  • the second light-emitting control circuit writes the reset voltage provided by the reset voltage terminal into the first pole of the light-emitting element under the control of the second light-emitting control signal.
  • the second terminal of the driving circuit is controlled to be connected to the first pole of the light-emitting element;
  • the compensation control circuit controls the control terminal of the driving circuit and the third terminal of the driving circuit under the control of the compensation control signal. The two ends are connected;
  • the data writing circuit writes the data voltage provided by the data line into the first end of the driving circuit, and the compensation control circuit controls the control of the driving circuit under the control of the compensation control signal.
  • the terminal is connected to the second terminal of the driving circuit;
  • the first initialization sub-circuit writes the first initial voltage provided by the first initial voltage terminal into the second terminal of the driving circuit under the control of the first initial control signal;
  • the driving circuit The circuit controls the connection between the first end of the driving circuit and the second end of the driving circuit under the control of the potential of its control end;
  • the first light-emitting control circuit controls the connection between the power supply voltage terminal and the first terminal of the driving circuit under the control of the first light-emitting control signal;
  • the second light-emitting control circuit controls the connection between Under the control of the light-emitting control signal, the second terminal of the driving circuit is controlled to be connected to the first pole of the light-emitting element;
  • the driving circuit drives the light-emitting element to emit light under the control of the potential of its control terminal.
  • the initialization circuit includes a first initialization sub-circuit; the pixel circuit also includes a first light-emitting control circuit, a second light-emitting control circuit, a data writing circuit and a reset circuit; the holding frame includes a sequentially set third two initialization phases, a second reset phase, a second reset phase and a second lighting phase; the driving method includes:
  • the compensation control circuit controls the disconnection between the control terminal of the driving circuit and the second terminal of the driving circuit under the control of the compensation control signal
  • the first initialization sub-circuit writes the first initial voltage provided by the first initial voltage terminal into the second terminal of the driving circuit under the control of the first initial control signal;
  • the reset circuit In the second reset phase, the reset circuit writes the reset voltage provided by the reset voltage terminal into the first pole of the light-emitting element under the control of the reset control signal, and the second light-emitting control circuit writes the reset voltage provided by the reset voltage terminal into the first pole of the light-emitting element. , controlling the connection between the second end of the driving circuit and the first pole of the light-emitting element;
  • the first initialization sub-circuit writes the first initial voltage provided by the first initial voltage terminal into the second terminal of the driving circuit under the control of the first initial control signal;
  • the driving circuit The circuit controls the connection between the first end of the driving circuit and the second end of the driving circuit under the control of the potential of its control end;
  • the first light-emitting control circuit controls the connection between the power supply voltage end and the first end of the driving circuit under the control of the first light-emitting control signal;
  • the second light-emitting control circuit controls the second light-emitting control circuit in the second light-emitting stage.
  • the second terminal of the driving circuit is controlled to be connected to the first pole of the light-emitting element;
  • the driving circuit drives the light-emitting element to emit light under the control of the potential of its control terminal;
  • the holding frame also includes a holding setting phase arranged between the second reset phase and the second reset phase; the driving method further includes:
  • the data writing circuit writes the voltage signal provided by the data line into the first end of the driving circuit.
  • the initialization circuit includes a second initialization sub-circuit;
  • the pixel circuit also includes a first light-emitting control circuit, a second light-emitting control circuit, a data writing circuit and a reset circuit;
  • the refresh frame includes a sequentially set third An initialization phase, a first reset phase, a first charging phase, a first reset phase and a first lighting phase;
  • the driving method includes:
  • the second initialization sub-circuit writes the second initial voltage provided by the second initial voltage terminal into the first terminal of the driving circuit under the control of the second initial control signal;
  • the compensation control circuit Under the control of the compensation control signal, the control terminal of the driving circuit is controlled to be connected to the second terminal of the driving circuit;
  • the reset circuit writes the reset voltage provided by the reset voltage terminal into the first pole of the light-emitting element under the control of the reset control signal;
  • the second light-emitting control circuit writes the reset voltage provided by the reset voltage terminal into the first pole of the light-emitting element;
  • the compensation control circuit controls the control terminal of the driving circuit and the third terminal of the driving circuit under the control of the compensation control signal. The two ends are connected;
  • the data writing circuit writes the data voltage provided by the data line into the first end of the driving circuit, and the compensation control circuit controls the control of the driving circuit under the control of the compensation control signal.
  • the terminal is connected to the second terminal of the driving circuit;
  • the second initialization sub-circuit writes the second initial voltage provided by the second initial voltage terminal into the first terminal of the driving circuit under the control of the second initial control signal;
  • the driving circuit The circuit controls the connection between the first end of the driving circuit and the second end of the driving circuit under the control of the potential of its control end;
  • the first light-emitting control circuit controls the connection between the power supply voltage terminal and the first terminal of the driving circuit under the control of the first light-emitting control signal;
  • the second light-emitting control circuit controls the connection between Under the control of the light-emitting control signal, the second terminal of the driving circuit is controlled to be connected to the first pole of the light-emitting element;
  • the driving circuit drives the light-emitting element to emit light under the control of the potential of its control terminal.
  • the initialization circuit includes a second initialization sub-circuit;
  • the pixel circuit also includes a first light-emitting control circuit, a second light-emitting control circuit, a data writing circuit and a reset circuit;
  • the holding frame includes a sequentially set third two initialization phases, a second reset phase, a second reset phase and a second lighting phase;
  • the driving method includes:
  • the compensation control circuit controls the disconnection between the control terminal of the driving circuit and the second terminal of the driving circuit under the control of the compensation control signal
  • the second initialization sub-circuit writes the second initial voltage provided by the second initial voltage terminal into the first terminal of the driving circuit under the control of the second initial control signal;
  • the reset circuit writes the reset voltage provided by the reset voltage terminal into the first pole of the light-emitting element under the control of the reset control signal;
  • the second light-emitting control circuit writes the reset voltage provided by the reset voltage terminal into the first pole of the light-emitting element; , controlling the connection between the second end of the driving circuit and the first pole of the light-emitting element;
  • the second initialization sub-circuit writes the second initial voltage provided by the second initial voltage terminal into the first terminal of the driving circuit under the control of the second initial control signal;
  • the driving circuit The circuit controls the connection between the first end of the driving circuit and the second end of the driving circuit under the control of the potential of its control end;
  • the first light-emitting control circuit controls the connection between the power supply voltage end and the first end of the driving circuit under the control of the first light-emitting control signal;
  • the second light-emitting control circuit controls the second light-emitting control circuit in the second light-emitting stage.
  • the second terminal of the driving circuit is controlled to be connected to the first pole of the light-emitting element;
  • the driving circuit drives the light-emitting element to emit light under the control of the potential of its control terminal;
  • the holding frame also includes a holding setting phase arranged between the second reset phase and the second reset phase; the driving method further includes:
  • the data writing circuit writes the voltage signal provided by the data line into the first end of the driving circuit.
  • the initialization circuit includes a first initialization sub-circuit and a second initialization sub-circuit;
  • the pixel circuit also includes a first light-emitting control circuit, a second light-emitting control circuit and a data writing circuit;
  • the refresh frame includes successive The first reset stage, the first charging stage, the first reset stage and the first lighting stage are set;
  • the driving method includes:
  • the first initialization sub-circuit writes the first initial voltage provided by the first initial voltage terminal into the second terminal of the driving circuit under the control of the first initial control signal, and the compensation control The circuit controls the connection between the control end of the drive circuit and the second end of the drive circuit under the control of the compensation control signal;
  • the data writing circuit writes the data voltage provided by the data line into the first end of the driving circuit, and the compensation control circuit controls the control of the driving circuit under the control of the compensation control signal.
  • the terminal is connected to the second terminal of the driving circuit;
  • the second initialization sub-circuit writes the second initial voltage provided by the second initial voltage terminal into the first terminal of the driving circuit under the control of the second initial control signal, so
  • the driving circuit controls the connection between the first end of the driving circuit and the second end of the driving circuit under the control of the potential of its control end;
  • the first light-emitting control circuit controls the connection between the power supply voltage terminal and the first terminal of the driving circuit under the control of the first light-emitting control signal;
  • the second light-emitting control circuit controls the connection between Under the control of the light-emitting control signal, the second terminal of the driving circuit is controlled to be connected to the first pole of the light-emitting element;
  • the driving circuit drives the light-emitting element to emit light under the control of the potential of its control terminal.
  • the pixel circuit also includes a reset circuit; the driving method further includes:
  • the reset circuit writes the reset voltage provided by the reset voltage terminal into the first pole of the light-emitting element under the control of the reset control signal.
  • the initialization circuit includes a first initialization sub-circuit and a second initialization sub-circuit;
  • the pixel circuit also includes a first lighting control circuit, a second lighting control circuit and a data writing circuit;
  • the holding frame includes successive The second reset stage, the second reset stage and the second lighting stage are set;
  • the driving method includes:
  • the compensation control circuit controls the disconnection between the control terminal of the driving circuit and the second terminal of the driving circuit under the control of the compensation control signal
  • the first initialization sub-circuit writes the first initial voltage provided by the first initial voltage terminal into the second terminal of the driving circuit under the control of the first initial control signal;
  • the second initialization sub-circuit writes the second initial voltage provided by the second initial voltage terminal into the first terminal of the driving circuit under the control of the second initial control signal, so
  • the driving circuit controls the connection between the first end of the driving circuit and the second end of the driving circuit under the control of the potential of its control end;
  • the first light-emitting control circuit controls the connection between the power supply voltage end and the first end of the driving circuit under the control of the first light-emitting control signal; the second light-emitting control circuit controls the second light-emitting control circuit in the second light-emitting stage.
  • the second terminal of the driving circuit is controlled to be connected to the first pole of the light-emitting element; the driving circuit drives the light-emitting element to emit light under the control of the potential of its control terminal.
  • the pixel circuit also includes a reset circuit; the driving method further includes:
  • the reset circuit writes the reset voltage provided by the reset voltage terminal into the first pole of the light-emitting element under the control of the reset control signal.
  • the hold frame also includes a hold setting phase arranged between the second reset phase and the second reset phase;
  • the driving method also includes:
  • the data writing circuit writes the voltage signal provided by the data line into the first end of the driving circuit.
  • an embodiment of the present disclosure provides a display device including the above-mentioned pixel circuit.
  • Figure 1 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure
  • Figure 2 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure
  • Figure 3 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • Figure 4 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • Figure 5 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • Figure 6 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • Figure 7 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • Figure 8 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • Figure 9 is an operating timing diagram of at least one embodiment of the pixel circuit shown in Figure 8 of the present disclosure.
  • Figure 10A is a schematic diagram of the working state of at least one embodiment of the pixel circuit shown in Figure 8 of the present disclosure in the first initialization stage S11;
  • Figure 10B is a schematic diagram of the working state of at least one embodiment of the pixel circuit shown in Figure 8 of the present disclosure in the first reset stage S12;
  • Figure 10C is a schematic diagram of the working state of at least one embodiment of the pixel circuit shown in Figure 8 of the present disclosure in the first charging stage S13;
  • Figure 10D is a schematic diagram of the working state of at least one embodiment of the pixel circuit shown in Figure 8 of the present disclosure in the first reset stage S14;
  • Figure 10E is a schematic diagram of the working state of at least one embodiment of the pixel circuit shown in Figure 8 of the present disclosure in the first light emitting stage S15;
  • Figure 11 is an operating timing diagram of at least one embodiment of the pixel circuit shown in Figure 8 of the present disclosure.
  • Figure 12 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • Figure 13 is an operating timing diagram of at least one embodiment of the pixel circuit shown in Figure 11 of the present disclosure.
  • Figure 14A is a schematic diagram of the working state of at least one embodiment of the pixel circuit shown in Figure 12 of the present disclosure in the first initialization stage S11;
  • Figure 14B is a schematic diagram of the working state of at least one embodiment of the pixel circuit shown in Figure 12 of the present disclosure in the first reset stage S12;
  • Figure 14C is a schematic diagram of the working state of at least one embodiment of the pixel circuit shown in Figure 12 of the present disclosure in the first charging stage S13;
  • Figure 14D is a schematic diagram of the working state of at least one embodiment of the pixel circuit shown in Figure 12 of the present disclosure in the first reset stage S14;
  • Figure 14E is a schematic diagram of the working state of at least one embodiment of the pixel circuit shown in Figure 12 of the present disclosure in the first light emitting stage S15;
  • Figure 15 is an operating timing diagram of at least one embodiment of the pixel circuit shown in Figure 12 of the present disclosure.
  • Figure 16 is an operating timing diagram of at least one embodiment of the pixel circuit shown in Figure 12 of the present disclosure.
  • Figure 17 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • Figure 18 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • Figure 19 is an operating timing diagram of at least one embodiment of the pixel circuit shown in Figure 18 of the present disclosure.
  • Figure 20A is a schematic diagram of the working state of at least one embodiment of the pixel circuit shown in Figure 18 of the present disclosure in the first reset stage S12;
  • Figure 20B is a schematic diagram of the working state of at least one embodiment of the pixel circuit shown in Figure 18 of the present disclosure in the first charging stage S13;
  • Figure 20C is a schematic diagram of the working state of at least one embodiment of the pixel circuit shown in Figure 18 of the present disclosure in the first reset stage S14;
  • Figure 20D is a schematic diagram of the working state of at least one embodiment of the pixel circuit shown in Figure 18 of the present disclosure in the first light emitting stage S15;
  • Figure 21 is an operating timing diagram of at least one embodiment of the pixel circuit shown in Figure 18 of the present disclosure.
  • FIG. 22 is an operation timing diagram of at least one embodiment of the pixel circuit shown in FIG. 18 of the present disclosure.
  • the transistors used in all embodiments of the present disclosure may be transistors, thin film transistors, field effect transistors, or other devices with the same characteristics.
  • one pole is called the first pole and the other pole is called the second pole.
  • the control electrode when the transistor is a triode, the control electrode may be a base electrode, the first electrode may be a collector, and the second electrode may be an emitter; or, the control electrode may be a base electrode. pole, the first pole may be an emitter, and the second pole may be a collector.
  • the control electrode when the transistor is a thin film transistor or a field effect transistor, the control electrode may be a gate electrode, the first electrode may be a drain electrode, and the second electrode may be a source electrode; or, The control electrode may be a gate electrode, the first electrode may be a source electrode, and the second electrode may be a drain electrode.
  • the pixel circuit described in the embodiment of the present disclosure includes a light-emitting element, a drive circuit, an energy storage circuit, an initialization circuit and a compensation control circuit;
  • the display cycle of the pixel circuit includes a refresh frame and a hold frame;
  • the refresh frame and the hold frame They respectively include a reset phase and a lighting phase that are set successively;
  • the energy storage circuit is electrically connected to the control end of the drive circuit and is used to store electrical energy
  • the compensation control circuit is electrically connected to the compensation control terminal, the control terminal of the drive circuit and the second terminal of the drive circuit respectively, and is used to control the compensation control signal under the control of the compensation control signal provided by the compensation control terminal.
  • the control end of the drive circuit is connected to the second end of the drive circuit;
  • the initialization circuit is electrically connected to the initial control terminal and the initial voltage terminal respectively, and the initialization circuit is electrically connected to the first terminal of the driving circuit and/or the second terminal of the driving circuit for use in the initialization process.
  • the initial voltage provided by the initial voltage terminal is controlled to be provided to the first part of the driving circuit. terminal and/or the second terminal of the driving circuit;
  • the second end of the driving circuit is electrically connected to the light-emitting element, and is used to drive the light-emitting element under the control of the potential of the control end of the driving circuit.
  • the initialization circuit is controlled by the initial control signal to control the initial voltage in the refresh frame and the hold frame, at least in the reset phase.
  • the initial voltage provided by the terminal is provided to the first terminal of the driving circuit and/or the second terminal of the driving circuit to provide a bias voltage to the driving transistor included in the driving circuit, so that the driving transistor included in the driving circuit The transistor is in a biased state to improve hysteresis and improve display effects.
  • the pixel circuit described in the embodiment of the present disclosure can improve the flicker phenomenon during low-frequency display.
  • the embodiment of the present disclosure biases the drive transistor included in the drive circuit, so that during the reset phase in the hold frame , the potential of the source of the driving transistor and the potential of the drain of the driving transistor in the driving circuit are consistent with the refresh frame, which can improve the flicker phenomenon.
  • the driving transistor included in the driving circuit is a p-type transistor, and the initial voltage is a positive voltage.
  • the energy storage circuit may include a storage capacitor
  • the first end of the storage capacitor is electrically connected to the control end of the drive circuit, and the second end of the storage capacitor is electrically connected to the power supply voltage end.
  • the initialization circuit may include a first initialization sub-circuit; the initial control terminal includes a first initial control terminal, and the initial voltage terminal includes a first initial voltage terminal;
  • the first initialization sub-circuit is electrically connected to the first initial control terminal, the first initial voltage terminal and the second terminal of the drive circuit respectively, for providing the first initialization voltage at the first initial control terminal. Under the control of the initial control signal, in the refresh frame and the hold frame, at least in the reset phase, the first initial voltage provided by the first initial voltage terminal is written into the second terminal of the driving circuit .
  • the pixel circuit may include a light emitting element E0, a driving circuit 11, an energy storage circuit 12, an initialization circuit and a compensation control circuit 14;
  • the display cycle of the pixel circuit includes a refresh frame and a hold frame;
  • the refresh frame and the hold frame respectively include a reset phase and a lighting phase set successively;
  • the energy storage circuit 12 is electrically connected to the control terminal of the drive circuit and is used to store electrical energy
  • the compensation control circuit 14 is electrically connected to the compensation control terminal NG, the control terminal of the drive circuit 11 and the second terminal of the drive circuit 11 respectively, and is used to control the compensation control signal provided at the compensation control terminal NG. Next, control the connection between the control terminal of the driving circuit 11 and the second terminal of the driving circuit 11;
  • the initialization circuit includes a first initialization sub-circuit 131; the initial control terminal includes a first initial control terminal S1, and the initial voltage terminal includes a first initial voltage terminal I1;
  • the first initialization sub-circuit 131 is electrically connected to the first initial control terminal S1, the first initial voltage terminal I1 and the second terminal of the drive circuit 11 respectively, and is used to operate at the first initial control terminal Under the control of the first initial control signal provided by S1, in the refresh frame and the hold frame, at least in the reset phase, the first initial voltage provided by the first initial voltage terminal I1 is written into the
  • the second terminal of the drive circuit 11 is used to control the drive transistor included in the drive circuit 11 to be in a bias state;
  • the second end of the driving circuit 11 is electrically connected to the light-emitting element E0, and is used to drive the light-emitting element E0 under the control of the potential of the control end of the driving circuit 11.
  • the initialization circuit includes a second initialization sub-circuit; the initial control terminal includes a second initial control terminal, and the initial voltage terminal includes a second initial voltage terminal;
  • the second initialization sub-circuit is electrically connected to the second initial control terminal, the second initial voltage terminal and the first terminal of the drive circuit respectively, for second initial control provided at the second initial control terminal. Under the control of the signal, in the refresh frame and the hold frame, at least in the reset phase, the second initial voltage provided by the second initial voltage terminal is written into the first terminal of the driving circuit.
  • the pixel circuit may include a light emitting element E0, a driving circuit 11, an energy storage circuit 12, an initialization circuit and a compensation control circuit 14;
  • the display cycle of the pixel circuit includes a refresh frame and a hold frame;
  • the refresh frame and the hold frame respectively include a reset phase and a lighting phase set successively;
  • the energy storage circuit 12 is electrically connected to the control terminal of the drive circuit and is used to store electrical energy
  • the compensation control circuit 14 is electrically connected to the compensation control terminal NG, the control terminal of the drive circuit 11 and the second terminal of the drive circuit 11 respectively, and is used to control the compensation control signal provided at the compensation control terminal NG. Next, control the connection between the control terminal of the driving circuit 11 and the second terminal of the driving circuit 11;
  • the initialization circuit includes a second initialization sub-circuit 132; the initial control terminal includes a second initial control terminal S2, and the initial voltage terminal includes a second initial voltage terminal I2;
  • the second initialization sub-circuit 132 is electrically connected to the second initial control terminal S2, the second initial voltage terminal I2 and the first terminal of the drive circuit 11 respectively, and is used to provide a voltage at the second initial control terminal S2. Under the control of the second initial control signal, in the refresh frame and the hold frame, at least in the reset phase, the second initial voltage provided by the second initial voltage terminal I2 is written into the driving circuit The first end of 11 to control the driving transistor included in the driving circuit 11 to be in a bias state;
  • the second end of the driving circuit 11 is electrically connected to the light-emitting element E0, and is used to drive the light-emitting element E0 under the control of the potential of the control end of the driving circuit 11.
  • the initialization circuit includes a first initialization sub-circuit and a second initialization sub-circuit;
  • the initial control terminal includes a first initial control terminal and a second initial control terminal, and the initial voltage terminal includes a first initial voltage terminal and a second initial voltage terminal;
  • the first initialization sub-circuit is electrically connected to the first initial control terminal, the first initial voltage terminal and the second terminal of the drive circuit respectively, for providing the first initialization voltage at the first initial control terminal. Under the control of the initial control signal, in the refresh frame and the hold frame, at least in the reset phase, the first initial voltage provided by the first initial voltage terminal is written into the second terminal of the driving circuit ;
  • the second initialization sub-circuit is electrically connected to the second initial control terminal, the second initial voltage terminal and the first terminal of the drive circuit respectively, for second initial control provided at the second initial control terminal. Under the control of the signal, in the refresh frame and the hold frame, at least in the reset phase, the second initial voltage provided by the second initial voltage terminal is written into the first terminal of the driving circuit.
  • the pixel circuit may include a light emitting element E0, a driving circuit 11, an energy storage circuit 12, an initialization circuit and a compensation control circuit 14;
  • the display cycle of the pixel circuit includes a refresh frame and a hold frame;
  • the refresh frame and the hold frame respectively include a reset phase and a lighting phase set successively;
  • the energy storage circuit 12 is electrically connected to the control terminal of the drive circuit and is used to store electrical energy
  • the compensation control circuit 14 is electrically connected to the compensation control terminal NG, the control terminal of the drive circuit 11 and the second terminal of the drive circuit 11 respectively, and is used to control the compensation control signal provided at the compensation control terminal NG. Next, control the connection between the control terminal of the driving circuit 11 and the second terminal of the driving circuit 11;
  • the initialization circuit includes a first initialization sub-circuit 131 and a second initialization sub-circuit 132; the initial control terminal includes a first initial control terminal S1 and a second initial control terminal S2, and the initial voltage terminal includes a first initial voltage terminal I1 and the second initial voltage terminal I2;
  • the first initialization sub-circuit 131 is electrically connected to the first initial control terminal S1, the first initial voltage terminal I1 and the second terminal of the drive circuit respectively, and is used to operate the first initial control terminal S1 Under the control of the provided first initial control signal, in the refresh frame and the hold frame, at least in the reset phase, the first initial voltage provided by the first initial voltage terminal I1 is written into the driving the second terminal of circuit 11;
  • the second initialization sub-circuit is electrically connected to the second initial control terminal S2, the second initial voltage terminal I2 and the first terminal of the drive circuit 11, respectively, for providing the second initial control terminal S2.
  • the second initial voltage provided by the second initial voltage terminal I2 is written into the driving circuit 11 the first end of;
  • the second end of the driving circuit 11 is electrically connected to the light-emitting element E0, and is used to drive the light-emitting element E0 under the control of the potential of the control end of the driving circuit 11.
  • the first initialization sub-circuit includes a first transistor
  • the control electrode of the first transistor is electrically connected to the first initial control terminal, the first electrode of the first transistor is electrically connected to the first initial voltage terminal, and the second electrode of the first transistor is electrically connected to the first initial control terminal.
  • the second terminal of the driving circuit is electrically connected.
  • the second initialization sub-circuit includes a second transistor
  • the control electrode of the second transistor is electrically connected to the second initial control terminal, the first electrode of the second transistor is electrically connected to the second initial voltage terminal, and the second electrode of the second transistor is electrically connected to the second initial control terminal.
  • the first end of the driving circuit is electrically connected.
  • the first initialization sub-circuit includes a first transistor
  • the second initialization sub-circuit includes a second transistor
  • the control electrode of the first transistor is electrically connected to the first initial control terminal, the first electrode of the first transistor is electrically connected to the first initial voltage terminal, and the second electrode of the first transistor is electrically connected to the first initial control terminal.
  • the second end of the driving circuit is electrically connected;
  • the control electrode of the second transistor is electrically connected to the second initial control terminal, the first electrode of the second transistor is electrically connected to the second initial voltage terminal, and the second electrode of the second transistor is electrically connected to the second initial control terminal.
  • the first end of the driving circuit is electrically connected.
  • the pixel circuit further includes a first light emission control circuit, a second light emission control circuit and a data writing circuit;
  • the first lighting control circuit is electrically connected to the first lighting control terminal, the power supply voltage terminal and the first terminal of the driving circuit respectively, for controlling the first lighting control signal provided by the first lighting control terminal. , controlling the connection between the power supply voltage terminal and the first terminal of the driving circuit;
  • the second light-emitting control circuit is electrically connected to the second light-emitting control terminal, the second terminal of the driving circuit and the first pole of the light-emitting element respectively, for providing the second light-emitting light at the second light-emitting control terminal.
  • the second terminal of the driving circuit Under the control of the control signal, the second terminal of the driving circuit is controlled to be connected to the first pole of the light-emitting element; the second pole of the light-emitting element is electrically connected to the first voltage terminal;
  • the data writing circuit is electrically connected to the writing control terminal, the data line and the first terminal of the driving circuit respectively, and is used to control the data under the control of the writing control signal provided by the writing control terminal.
  • the line is connected with the first end of the driving circuit.
  • the first lighting control circuit and the second lighting control circuit are used for lighting control
  • the data writing circuit is used for writing data voltage
  • the pixel circuit further includes a reset circuit
  • the reset circuit is electrically connected to the reset control terminal, the reset voltage terminal and the first pole of the light-emitting element respectively, and is used to control the reset voltage terminal to provide the reset voltage terminal under the control of the reset control signal provided by the reset control terminal.
  • the reset voltage is written to the first pole of the light-emitting element.
  • the reset circuit under the control of the reset control signal, writes the reset voltage into the first pole of the light-emitting element to control the light-emitting element not to emit light and clear the first pole of the light-emitting element. residual charge.
  • the pixel circuit according to at least one embodiment of the present disclosure further includes a first light-emitting control circuit 41 , a second light-emitting control circuit 42 , Data writing circuit 43 and reset circuit 44;
  • the first lighting control circuit 41 is electrically connected to the first lighting control terminal E1, the power supply voltage terminal VDD and the first terminal of the driving circuit 11, respectively, for providing the first lighting at the first lighting control terminal E1. Under the control of the control signal, the power supply voltage terminal VDD is controlled to be connected to the first terminal of the driving circuit 11;
  • the second light-emitting control circuit 42 is electrically connected to the second light-emitting control terminal E2, the second terminal of the driving circuit 11 and the first pole of the light-emitting element E0 respectively, and is used to control the second light-emitting control terminal E2. Under the control of the provided second light-emitting control signal, the second terminal of the driving circuit 11 is controlled to be connected to the first pole of the light-emitting element E0; the second pole of the light-emitting element E0 is connected to the first voltage terminal V1 electrical connection;
  • the data writing circuit 43 is electrically connected to the writing control terminal S0, the data line D1 and the first end of the driving circuit 11 respectively, and is used to control the writing control signal provided by the writing control terminal S0. , controlling the communication between the data line D1 and the first end of the driving circuit 11;
  • the reset circuit 44 is electrically connected to the reset control terminal S3, the reset voltage terminal I3 and the first pole of the light-emitting element E0 respectively, and is used to control all the reset circuits under the control of the reset control signal provided by the reset control terminal S3.
  • the reset voltage provided by the reset voltage terminal I3 is written into the first pole of the light-emitting element E0.
  • the refresh frame includes a first initialization phase, a first reset phase, a first charging phase, a first reset phase and a first set in succession. luminous stage;
  • the first initialization sub-circuit 131 writes the first initial voltage Vi1 provided by the first initial voltage terminal I1 into the second terminal of the driving circuit 11 under the control of the first initial control signal;
  • the compensation control circuit 14 controls the connection between the control end of the driving circuit 11 and the second end of the driving circuit 11 under the control of the compensation control signal;
  • the reset circuit 44 writes the reset voltage Vi3 provided by the reset voltage terminal I3 into the first pole of the light-emitting element E0 under the control of the reset control signal, and the second light-emitting control circuit 42 Under the control of the light-emitting control signal, the second end of the driving circuit 11 is controlled to be connected to the first pole of the light-emitting element E0; the compensation control circuit 14, under the control of the compensation control signal, controls the connection between the second end of the driving circuit 11 and the first pole of the light-emitting element E0.
  • the control terminal is connected to the second terminal of the drive circuit 11;
  • the data writing circuit 43 writes the data voltage provided by the data line D1 into the first end of the driving circuit 11, and the compensation control circuit 14 controls the The control end of the drive circuit 11 is connected to the second end of the drive circuit 11;
  • the first initialization sub-circuit 131 writes the first initial voltage Vi1 provided by the first initial voltage terminal I1 into the second terminal of the driving circuit 11 under the control of the first initial control signal. ;
  • the drive circuit 11 controls the connection between the first end of the drive circuit 11 and the second end of the drive circuit 11 to control the drive transistor included in the drive circuit 11 in a biased state;
  • the first lighting control circuit 41 controls the connection between the power supply voltage terminal VDD and the first end of the driving circuit 11 under the control of the first lighting control signal; the second lighting control circuit 42 Under the control of the second light-emitting control signal, the second terminal of the driving circuit 11 is controlled to be connected to the first pole of the light-emitting element E0; the driving circuit 11 drives under the control of the potential of its control terminal.
  • the light-emitting element E0 emits light.
  • the holding frame includes a second initialization phase, a second reset phase, a second reset phase and a second light-emitting phase that are set successively;
  • the compensation control circuit 14 controls the disconnection between the control end of the driving circuit 11 and the second end of the driving circuit 11 under the control of the compensation control signal;
  • the first initialization sub-circuit 131 writes the first initial voltage Vi1 provided by the first initial voltage terminal I1 into the second terminal of the driving circuit 11 under the control of the first initial control signal;
  • the reset circuit 44 writes the reset voltage Vi3 provided by the reset voltage terminal I3 into the first pole of the light-emitting element E0 under the control of the reset control signal, and the second light-emitting control circuit 42 Under the control of the light-emitting control signal, the second terminal of the driving circuit 11 is controlled to be connected to the first pole of the light-emitting element E0;
  • the first initialization sub-circuit 131 writes the first initial voltage Vi1 provided by the first initial voltage terminal I1 into the second terminal of the driving circuit 11 under the control of the first initial control signal. ;
  • the drive circuit 11 controls the connection between the first end of the drive circuit 11 and the second end of the drive circuit 11 to control the drive transistor included in the drive circuit 11 in a biased state;
  • the first lighting control circuit 41 controls the connection between the power supply voltage terminal VDD and the first end of the driving circuit 11 under the control of the first lighting control signal; the second lighting control circuit 42 Under the control of the second light-emitting control signal, the second terminal of the driving circuit 11 is controlled to be connected to the first pole of the light-emitting element E0; the driving circuit 11 drives under the control of the potential of its control terminal.
  • the light-emitting element E0 emits light.
  • the hold frame may further include a hold set phase disposed between the second reset phase and the second reset phase;
  • the data writing circuit 43 writes the voltage signal provided by the data line D1 into the first end of the driving circuit 11.
  • the pixel circuit according to at least one embodiment of the present disclosure further includes a first light-emitting control circuit 41 , a second light-emitting control circuit 42 , Data writing circuit 43 and reset circuit 44;
  • the first lighting control circuit 41 is electrically connected to the first lighting control terminal E1, the power supply voltage terminal VDD and the first terminal of the driving circuit 11, respectively, for providing the first lighting at the first lighting control terminal E1. Under the control of the control signal, the power supply voltage terminal VDD is controlled to be connected to the first terminal of the driving circuit 11;
  • the second light-emitting control circuit 42 is electrically connected to the second light-emitting control terminal E2, the second terminal of the driving circuit 11 and the first pole of the light-emitting element E0 respectively, and is used to control the second light-emitting control terminal E2. Under the control of the provided second light-emitting control signal, the second terminal of the driving circuit 11 is controlled to be connected to the first pole of the light-emitting element E0; the second pole of the light-emitting element E0 is connected to the first voltage terminal V1 electrical connection;
  • the data writing circuit 43 is electrically connected to the writing control terminal S0, the data line D1 and the first end of the driving circuit 11 respectively, and is used to control the writing control signal provided by the writing control terminal S0. , controlling the communication between the data line D1 and the first end of the driving circuit 11;
  • the reset circuit 44 is electrically connected to the reset control terminal S3, the reset voltage terminal I3 and the first pole of the light-emitting element E0 respectively, and is used to control all the reset circuits under the control of the reset control signal provided by the reset control terminal S3.
  • the reset voltage provided by the reset voltage terminal I3 is written into the first pole of the light-emitting element E0.
  • the refresh frame includes a first initialization phase, a first reset phase, a first charging phase, a first reset phase and a first set in succession. luminous stage;
  • the second initialization sub-circuit 132 writes the second initial voltage Vi2 provided by the second initial voltage terminal I2 into the first terminal of the driving circuit 11 under the control of the second initial control signal;
  • the compensation control circuit 14 controls the connection between the control end of the driving circuit 11 and the second end of the driving circuit 11 under the control of the compensation control signal;
  • the reset circuit 44 writes the reset voltage Vi3 provided by the reset voltage terminal I3 into the first pole of the light-emitting element E0 under the control of the reset control signal;
  • the second light-emitting control circuit 42 writes the reset voltage Vi3 provided by the reset voltage terminal I3 into the first pole of the light-emitting element E0;
  • the second end of the driving circuit 11 is controlled to be connected to the first pole of the light-emitting element E0;
  • the compensation control circuit 14 under the control of the compensation control signal, controls the connection between the second end of the driving circuit 11 and the first pole of the light-emitting element E0.
  • the control terminal is connected to the second terminal of the drive circuit 11;
  • the data writing circuit 43 writes the data voltage Vdata provided by the data line D1 into the first end of the driving circuit 11, and the compensation control circuit 14 controls all the steps under the control of the compensation control signal.
  • the control terminal of the driving circuit 11 is connected to the second terminal of the driving circuit 11;
  • the second initialization sub-circuit 132 writes the second initial voltage Vi2 provided by the second initial voltage terminal i2 into the first terminal of the driving circuit 11 under the control of the second initial control signal. ; Under the control of the potential of its control end, the drive circuit 11 controls the connection between the first end of the drive circuit 11 and the second end of the drive circuit 11 to control the drive transistor included in the drive circuit 11 in a biased state;
  • the first lighting control circuit 41 controls the connection between the power supply voltage terminal VDD and the first end of the driving circuit 11 under the control of the first lighting control signal; the second lighting control circuit 42 Under the control of the second light-emitting control signal, the second terminal of the driving circuit 11 is controlled to be connected to the first pole of the light-emitting element E0; the driving circuit 11 drives under the control of the potential of its control terminal.
  • the light-emitting element E0 emits light.
  • the holding frame includes a second initialization stage, a second reset stage, a second reset stage and a second light-emitting stage that are set successively;
  • the compensation control circuit 14 controls the disconnection between the control end of the driving circuit 11 and the second end of the driving circuit 11 under the control of the compensation control signal;
  • the second initialization sub-circuit 132 writes the second initial voltage Vi2 provided by the second initial voltage terminal I2 into the first terminal of the driving circuit 11 under the control of the second initial control signal;
  • the reset circuit 44 writes the reset voltage Vi3 provided by the reset voltage terminal I3 into the first pole of the light-emitting element E0 under the control of the reset control signal;
  • the second light-emitting control circuit 42 writes the reset voltage Vi3 provided by the reset voltage terminal I3 into the first pole of the light-emitting element E0;
  • the second terminal of the driving circuit 11 is controlled to be connected to the first pole of the light-emitting element E0;
  • the second initialization sub-circuit 132 writes the second initial voltage Vi2 provided by the second initial voltage terminal I2 into the first terminal of the driving circuit 11 under the control of the second initial control signal. ;
  • the drive circuit 11 controls the connection between the first end of the drive circuit 11 and the second end of the drive circuit 11 to control the drive transistor included in the drive circuit 11 in a biased state;
  • the first lighting control circuit 41 controls the connection between the power supply voltage terminal VDD and the first end of the driving circuit 11 under the control of the first lighting control signal; the second lighting control circuit 42 Under the control of the second light-emitting control signal, the second terminal of the driving circuit 11 is controlled to be connected to the first pole of the light-emitting element E0; the driving circuit 11 drives under the control of the potential of its control terminal.
  • the light-emitting element E0 emits light.
  • the holding frame further includes a holding set stage disposed between the second reset stage and the second reset stage;
  • the data writing circuit 43 writes the voltage signal provided by the data line D1 into the first end of the driving circuit 11 .
  • the pixel circuit according to at least one embodiment of the present disclosure further includes a first light emission control circuit 41 , a second light emission control circuit 42 and Data writing circuit 43;
  • the first lighting control circuit 41 is electrically connected to the first lighting control terminal E1, the power supply voltage terminal VDD and the first terminal of the driving circuit 11, respectively, for providing the first lighting at the first lighting control terminal E1. Under the control of the control signal, the power supply voltage terminal VDD is controlled to be connected to the first terminal of the driving circuit 11;
  • the second light-emitting control circuit 42 is electrically connected to the second light-emitting control terminal E2, the second terminal of the driving circuit 11 and the first pole of the light-emitting element E0 respectively, and is used to control the second light-emitting control terminal E2. Under the control of the provided second light-emitting control signal, the second terminal of the driving circuit 11 is controlled to be connected to the first pole of the light-emitting element E0; the second pole of the light-emitting element E0 is connected to the first voltage terminal V1 electrical connection;
  • the data writing circuit 43 is electrically connected to the writing control terminal S0, the data line D1 and the first end of the driving circuit 11 respectively, and is used to control the writing control signal provided by the writing control terminal S0. , controlling the communication between the data line D1 and the first end of the driving circuit 11 .
  • the refresh frame includes a first reset phase, a first charging phase, a first reset phase and a first lighting phase that are set successively;
  • the first initialization sub-circuit 131 writes the first initial voltage Vi1 provided by the first initial voltage terminal I1 into the second terminal of the driving circuit 11 under the control of the first initial control signal.
  • the compensation control circuit 14 controls the connection between the control terminal of the driving circuit 11 and the second terminal of the driving circuit 11 under the control of the compensation control signal;
  • the data writing circuit 43 writes the data voltage Vdata provided by the data line D1 into the first end of the driving circuit 11, and the compensation control circuit 14 controls all the steps under the control of the compensation control signal.
  • the control terminal of the driving circuit 11 is connected to the second terminal of the driving circuit 11;
  • the second initialization sub-circuit 132 writes the second initial voltage Vi2 provided by the second initial voltage terminal I2 into the first terminal of the driving circuit 11 under the control of the second initial control signal.
  • the driving circuit 11 controls the communication between the first end of the driving circuit 11 and the second end of the driving circuit 11 under the control of the potential of its control end, so as to control the The drive transistor is in a biased state;
  • the first lighting control circuit 41 controls the connection between the power supply voltage terminal VDD and the first end of the driving circuit 11 under the control of the first lighting control signal; the second lighting control circuit 42 Under the control of the second light-emitting control signal, the second terminal of the driving circuit 11 is controlled to be connected to the first pole of the light-emitting element E0; the driving circuit 11 drives under the control of the potential of its control terminal.
  • the light-emitting element E0 emits light.
  • the holding frame includes a second initialization stage, a second reset stage, a second reset stage and a second light-emitting stage that are set successively;
  • the compensation control circuit 14 controls the disconnection between the control end of the driving circuit 11 and the second end of the driving circuit 11 under the control of the compensation control signal;
  • the first initialization sub-circuit 131 writes the first initial voltage Vi1 provided by the first initial voltage terminal I1 into the second terminal of the driving circuit 11 under the control of the first initial control signal. end;
  • the second initialization sub-circuit 132 writes the second initial voltage Vi2 provided by the second initial voltage terminal I2 into the first terminal of the driving circuit 11 under the control of the second initial control signal.
  • the driving circuit 11 controls the communication between the first end of the driving circuit 11 and the second end of the driving circuit 11 under the control of the potential of its control end, so as to control the The drive transistor is in a biased state;
  • the first lighting control circuit 41 controls the connection between the power supply voltage terminal VDD and the first end of the driving circuit 11 under the control of the first lighting control signal; the second lighting control circuit 42 Under the control of the second light-emitting control signal, the second terminal of the driving circuit 11 is controlled to be connected to the first pole of the light-emitting element E0; the driving circuit 11 drives under the control of the potential of its control terminal.
  • the light-emitting element E0 emits light.
  • the holding frame further includes a holding set stage disposed between the second reset stage and the second reset stage;
  • the data writing circuit 43 writes the voltage signal provided by the data line D1 into the first end of the driving circuit 11 .
  • the pixel circuit described in at least one embodiment of the present disclosure also includes a reset circuit 44;
  • the reset circuit 44 is electrically connected to the reset control terminal S3, the reset voltage terminal I3 and the first pole of the light-emitting element E0 respectively, and is used to control all the reset circuits under the control of the reset control signal provided by the reset control terminal S3.
  • the reset voltage provided by the reset voltage terminal I3 is written into the first pole of the light-emitting element E0.
  • the reset circuit 44 writes the reset voltage Vi3 provided by the reset voltage terminal I3 into the first pole of the light-emitting element E0 under the control of the reset control signal;
  • the reset circuit 44 writes the reset voltage Vi3 provided by the reset voltage terminal I3 into the first pole of the light-emitting element E0 under the control of the reset control signal.
  • the compensation control circuit includes a third transistor, the first lighting control circuit includes a fourth transistor, the second lighting control circuit includes a fifth transistor, and the data writing circuit includes a sixth transistor, so
  • the drive circuit includes a drive transistor
  • the control electrode of the third transistor is electrically connected to the compensation control terminal, the first electrode of the third transistor is electrically connected to the control terminal of the drive circuit, and the second electrode of the third transistor is electrically connected to the drive circuit.
  • the second end of the circuit is electrically connected;
  • the control electrode of the fourth transistor is electrically connected to the first light-emitting control terminal, the first electrode of the fourth transistor is electrically connected to the power supply voltage terminal, and the second electrode of the fourth transistor is electrically connected to the driving The first end of the circuit is electrically connected;
  • the control electrode of the fifth transistor is electrically connected to the second light-emitting control terminal, the first electrode of the fifth transistor is electrically connected to the second terminal of the driving circuit, and the second electrode of the fifth transistor is electrically connected to The first electrode of the light-emitting element is electrically connected;
  • the control electrode of the sixth transistor is electrically connected to the write control terminal, the first electrode of the sixth transistor is electrically connected to the data line, and the second electrode of the sixth transistor is electrically connected to the first electrode of the drive circuit. terminal electrical connection;
  • the control electrode of the drive transistor is electrically connected to the control terminal of the drive circuit
  • the first electrode of the drive transistor is electrically connected to the first end of the drive circuit
  • the second electrode of the drive transistor is electrically connected to the drive circuit.
  • the second end of the circuit is electrically connected.
  • the third transistor is an oxide thin film transistor.
  • the reset circuit includes a seventh transistor
  • the control electrode of the seventh transistor is electrically connected to the reset control terminal, the first electrode of the seventh transistor is electrically connected to the reset voltage terminal, and the second electrode of the seventh transistor is electrically connected to the third terminal of the light-emitting element.
  • the seventh transistor is an oxide thin film transistor.
  • the first initialization sub-circuit 131 includes a first transistor T1; the driving circuit 11 includes a driving transistor T0; the light emitting The component is an organic light-emitting diode O1; the energy storage circuit 12 includes a storage capacitor C1;
  • the gate of the first transistor T1 is electrically connected to the first initial control terminal S1, the source of the first transistor T1 is electrically connected to the first initial voltage terminal I1, and the drain of the first transistor T1
  • the pole is electrically connected to the drain of the driving transistor T0;
  • the compensation control circuit 14 includes a third transistor T3, the first lighting control circuit 41 includes a fourth transistor T4, the second lighting control circuit 42 includes a fifth transistor T5, and the data writing circuit 43 includes a sixth transistor.
  • the gate of the third transistor T3 is electrically connected to the compensation control terminal NG, the source of the third transistor T3 is electrically connected to the gate of the driving transistor T0, and the drain of the third transistor T3 is electrically connected to the compensation control terminal NG.
  • the drain of the driving transistor T0 is electrically connected;
  • the gate of the fourth transistor T4 is electrically connected to the first light emitting control terminal E1, the source of the fourth transistor T4 is electrically connected to the power supply voltage terminal VDD, and the drain of the fourth transistor T4 is electrically connected to the power supply voltage terminal VDD.
  • the source of the driving transistor T0 is electrically connected;
  • the gate of the fifth transistor T5 is electrically connected to the second light emitting control terminal E2, the source of the fifth transistor T5 is electrically connected to the drain of the driving transistor T0, and the drain of the fifth transistor T5
  • the electrode is electrically connected to the anode of the organic light-emitting diode O1;
  • the gate of the sixth transistor T6 is electrically connected to the write control terminal S0, the source of the sixth transistor T6 is electrically connected to the data line D1, and the drain of the sixth transistor T6 is electrically connected to the driving transistor.
  • the source of T0 is electrically connected;
  • the reset circuit includes a seventh transistor T7;
  • the gate of the seventh transistor T7 is electrically connected to the reset control terminal S3, the source of the seventh transistor T7 is electrically connected to the reset voltage terminal I3, and the drain of the seventh transistor T7 is electrically connected to the organic
  • the anode of the light-emitting diode O1 is electrically connected;
  • the cathode of the organic light-emitting diode O1 is electrically connected to the low voltage terminal VSS;
  • the first terminal of the storage capacitor C1 is electrically connected to the gate of the driving transistor T0, and the second terminal of the storage capacitor C1 is electrically connected to the power supply voltage terminal VDD.
  • T3 and T7 are oxide thin film transistors
  • T1, T4, T5, T6 and T0 are LTPS (low temperature polysilicon) thin film transistors
  • T3 and T7 are n-type transistors
  • T1, T4, T5, T6 and T0 are p-type transistors, but are not limited to this.
  • the refresh frame includes a first initialization phase S11, a first reset phase S12, and a first charging phase S13 set successively. , the first reset phase S14 and the first lighting phase S15;
  • E2 provides a high voltage signal
  • E1 provides a high voltage signal
  • S3 provides a low voltage signal
  • NG provides a high voltage signal
  • S1 provides a low voltage signal
  • S0 provides a high voltage signal
  • I1 provides the first initial voltage Vi1 , as shown in Figure 10A, T1 is turned on and T3 is turned on to write the first initial voltage Vi1 to the drain of T0 and the gate of T0 to initialize the drain voltage of T0 and the gate voltage of T0;
  • the first initial voltage Vi1 is a positive voltage.
  • Vi1 can be a 5V voltage signal, but is not limited to this;
  • E2 provides a low voltage signal
  • E1 provides a high voltage signal
  • S3 provides a high voltage signal
  • NG provides a high voltage signal
  • S1 provides a high voltage signal
  • S0 provides a high voltage signal
  • T7 Open I3 provides the reset voltage Vi3
  • T5 opens
  • T3 opens
  • T0 opens to write the reset voltage Vi3 to the anode of O1, the drain of T0, the gate of T0, and the source of T0 to control O1 not to emit light.
  • the reset voltage Vi3 may be a negative voltage, for example, Vi3 may be a -3V voltage signal, but is not limited to this;
  • E2 provides a high voltage signal
  • E1 provides a high voltage signal
  • S3 provides a low voltage signal
  • NG provides a high voltage signal
  • S1 provides a high voltage signal
  • S0 provides a low voltage signal
  • T6 Open D1 provides data voltage Vdata
  • T3 opens; at the beginning of the first charging phase S13, T0 is turned on, and the data voltage Vdata charges C1 through T6, T0 and T3 to increase the gate voltage of T0 until T0 is turned off.
  • the gate voltage of T0 is Vdata+Vth
  • Vth is the threshold voltage of T0;
  • E2 provides a high voltage signal
  • E1 provides a high voltage signal
  • S3 provides a low voltage signal
  • NG provides a low voltage signal
  • S1 provides a low voltage signal
  • S0 provides a high voltage signal
  • I1 provides the first initial voltage.
  • Vi1 as shown in Figure 10D, T1 is turned on, and T0 is turned on to reset the drain voltage of T0 and the source voltage of T0 to Vi1, so that T0 is in a bias state and improves the hysteresis phenomenon;
  • E2 provides a low voltage signal
  • E1 provides a low voltage signal
  • S3 provides a low voltage signal
  • NG provides a low voltage signal
  • S1 provides a high voltage signal
  • S0 provides a high voltage signal
  • the voltage value of the first initial voltage Vi1 may be greater than or equal to 4V and less than or equal to 7V
  • the voltage value of the reset voltage Vi3 may be greater than or equal to - 4V and less than or equal to -2V, but not limited to this.
  • the holding frame includes a second initialization phase S21, a second reset phase S22, and a retention setting phase S23 set successively. , the second reset phase S24 and the second lighting phase S25;
  • NG provides a low voltage signal
  • T3 is turned off to control the disconnection between the gate of T0 and the drain of T0 to maintain the gate voltage of T0;
  • E2 provides a high voltage signal
  • E1 provides a high voltage signal
  • S3 provides a low voltage signal
  • S1 provides a low voltage signal
  • S0 provides a high voltage signal
  • I1 provides the first initial voltage Vi1
  • T1 is turned on,
  • the first initial voltage Vi1 is written into the drain of T0 to initialize the drain voltage of T0;
  • the first initial voltage Vi1 is a positive voltage, for example, Vi1 can be a 5V voltage signal, but is not limited to this. ;
  • E2 provides a low voltage signal
  • E1 provides a high voltage signal
  • S3 provides a high voltage signal
  • S1 provides a high voltage signal
  • S0 provides a high voltage signal
  • T7 is turned on
  • I3 provides the reset voltage Vi3
  • T5 is turned on
  • the reset voltage Vi3 can be negative Voltage, for example, Vi3 can be a -3V voltage signal, but is not limited to this;
  • E2 provides a high voltage signal
  • E1 provides a high voltage signal
  • S3 provides a low voltage signal
  • S1 provides a high voltage signal
  • S0 provides a low voltage signal
  • T6 is turned on
  • D1 provides a voltage signal to the source of T0;
  • the voltage signal provided by D1 can be a positive voltage to set the source voltage of T0, thereby providing a bias voltage to the driving transistor T0, so that T0 is in a bias state to improve the magnetic field. stagnation phenomenon;
  • E2 provides a high voltage signal
  • E1 provides a high voltage signal
  • S3 provides a low voltage signal
  • S1 provides a low voltage signal
  • S0 provides a high voltage signal
  • I1 provides the first initial voltage Vi1
  • T1 is turned on
  • T0 Open to reset the drain voltage of T0 and the source voltage of T0 to Vi1, so that T0 is in a bias state and improve the hysteresis phenomenon
  • E2 provides a low-voltage signal
  • E1 provides a low-voltage signal
  • S3 provides a low-voltage signal
  • S1 provides a high-voltage signal
  • S0 provides a high-voltage signal
  • T4 and T5 are turned on, and T0 drives O1 to emit light.
  • the voltage signal provided by the data line D1 may be the data voltage Vdata
  • the data voltage Vdata is the data voltage provided by the data line D1 during the first charging phase
  • the voltage value range of the data voltage Vdata may be, for example, greater than or equal to 1V and less than or equal to 6.5V; or,
  • the voltage signal provided by the data line D1 may be a reset voltage signal, and the voltage value range of the reset voltage signal may be greater than or equal to 4.6V and less than or equal to 7V;
  • the display cycle includes a refresh frame and a hold frame.
  • the embodiment of the present disclosure The drive transistor included in the drive circuit is biased so that in the second reset phase in the hold frame, the potential of the source of the drive transistor and the potential of the drain of the drive transistor in the drive circuit are consistent with the refresh frame, which can improve flicker. Phenomenon.
  • the second initialization sub-circuit 132 includes a second transistor T2; the driving circuit 11 includes a driving transistor T0; the light emitting The component is an organic light-emitting diode O1; the energy storage circuit 12 includes a storage capacitor C1;
  • the gate of the second transistor T2 is electrically connected to the second initial control terminal S2, the source of the second transistor T2 is electrically connected to the second initial voltage terminal I2, and the drain of the second transistor T2
  • the pole is electrically connected to the source of the driving transistor T0;
  • the compensation control circuit 14 includes a third transistor T3, the first lighting control circuit 41 includes a fourth transistor T4, the second lighting control circuit 42 includes a fifth transistor T5, and the data writing circuit 43 includes a sixth transistor.
  • the gate of the third transistor T3 is electrically connected to the compensation control terminal NG, the source of the third transistor T3 is electrically connected to the gate of the driving transistor T0, and the drain of the third transistor T3 is electrically connected to the compensation control terminal NG.
  • the drain of the driving transistor T0 is electrically connected;
  • the gate of the fourth transistor T4 is electrically connected to the first light emitting control terminal E1, the source of the fourth transistor T4 is electrically connected to the power supply voltage terminal VDD, and the drain of the fourth transistor T4 is electrically connected to the power supply voltage terminal VDD.
  • the source of the driving transistor T0 is electrically connected;
  • the gate of the fifth transistor T5 is electrically connected to the second light emitting control terminal E2, the source of the fifth transistor T5 is electrically connected to the drain of the driving transistor T0, and the drain of the fifth transistor T5
  • the electrode is electrically connected to the anode of the organic light-emitting diode O1;
  • the gate of the sixth transistor T6 is electrically connected to the write control terminal S0, the source of the sixth transistor T6 is electrically connected to the data line D1, and the drain of the sixth transistor T6 is electrically connected to the driving transistor.
  • the source of T0 is electrically connected;
  • the reset circuit 44 includes a seventh transistor T7;
  • the gate of the seventh transistor T7 is electrically connected to the reset control terminal S3, the source of the seventh transistor T7 is electrically connected to the reset voltage terminal I3, and the drain of the seventh transistor T7 is electrically connected to the organic
  • the anode of the light-emitting diode O1 is electrically connected;
  • the cathode of the organic light-emitting diode O1 is electrically connected to the low voltage terminal VSS;
  • the first terminal of the storage capacitor C1 is electrically connected to the gate of the driving transistor T0, and the second terminal of the storage capacitor C1 is electrically connected to the power supply voltage terminal VDD.
  • T3 is an oxide thin film transistor
  • T2, T4, T5, T6, T7 and T0 are LTPS (low temperature polysilicon) thin film transistors
  • T3 is an n-type transistor
  • T2, T4, T5, T6, T7 and T0 are p-type transistors, but are not limited to this.
  • the refresh frame includes a first initialization phase S11, a first reset phase S12, a first charging phase S13, which are set successively.
  • E2 provides a high voltage signal
  • E1 provides a high voltage signal
  • S2 provides a low voltage signal
  • NG provides a high voltage signal
  • S3 provides a low voltage signal
  • S0 provides a high voltage signal
  • I2 provides the second initial voltage Vi2
  • I3 provides the reset voltage Vi3
  • Vi2 is a positive voltage
  • Vi3 is a negative voltage
  • Vi2 can be a 5V voltage signal
  • Vi3 can be a -3V voltage signal
  • T7 is turned on to write Vi3 to O1
  • the anode makes O1 not emit light and clears the residual charge of the anode of O1; T2 turns on, T0 turns on, and T3 turns on to initialize the source voltage of T0, the drain voltage of T0, and the gate voltage of T0;
  • E2 provides a low voltage signal
  • E1 provides a high voltage signal
  • S2 provides a high voltage signal
  • NG provides a high voltage signal
  • S3 provides a low voltage signal
  • S0 provides a high voltage signal
  • I3 provides the reset voltage Vi3; such as As shown in Figure 14B, T7 is turned on to write Vi3 to the anode of O1, so that O1 does not emit light and clears the residual charge on the anode of O1; T3 is turned on, and T0 is turned on to write Vi3 to the gate of T0 and the drain of T0. pole and the source of T0, so that T0 can be turned on at the beginning of the first charging stage S13;
  • E2 provides a high voltage signal
  • E1 provides a high voltage signal
  • S2 provides a high voltage signal
  • NG provides a high voltage signal
  • S3 provides a high voltage signal
  • S0 provides a low voltage signal
  • D1 provides the data voltage Vdata, such as As shown in Figure 14C, T6 is open and T3 is open;
  • T0 is turned on, and Vdata charges C1 through T6, T0 and T3 until T0 is turned off, at which time the gate voltage of T0 is Vdata+Vth;
  • E2 provides a high voltage signal
  • E1 provides a high voltage signal
  • S2 provides a low voltage signal
  • NG provides a low voltage signal
  • S3 provides a low voltage signal
  • S0 provides a high voltage signal
  • I2 provides the second initial voltage.
  • T2 is turned on, T0 is turned on, and T7 is turned on to write Vi2 to the source of T0 and the drain of T0 to reset the drain voltage of T0 and the source voltage of T0 to Vi2, So that T0 is in a bias state to improve the hysteresis phenomenon; write Vi3 to the anode of O1, control O1 not to emit light, and clear the residual charge of the anode of O1;
  • E2 provides a low voltage signal
  • E1 provides a low voltage signal
  • S2 provides a high voltage signal
  • NG provides a low voltage signal
  • S3 provides a high voltage signal
  • S0 provides a high voltage signal
  • the holding frame includes a second initialization stage S21, a second reset stage S22, a hold setting stage S23, and the second reset phase S24 and the second lighting phase S25;
  • NG provides a low voltage signal
  • T3 is turned off to control the disconnection between the gate of T0 and the drain of T0 to maintain the gate voltage of T0;
  • E2 provides a high voltage signal
  • E1 provides a high voltage signal
  • S2 provides a low voltage signal
  • S3 provides a low voltage signal
  • S0 provides a high voltage signal
  • I2 provides the second initial voltage Vi2
  • I3 provides the reset voltage Vi3
  • Vi2 is a positive voltage
  • Vi3 is a negative voltage
  • T7 is turned on to write Vi3 to the anode of O1, so that O1 does not emit light, and clears the anode of O1 Residual charge
  • T2 is turned on
  • T0 is turned on to initialize the source voltage of T0 and the drain voltage of T0;
  • E2 provides a low voltage signal
  • E1 provides a high voltage signal
  • S2 provides a high voltage signal
  • S3 provides a low voltage signal
  • S0 provides a high voltage signal
  • I3 provides the reset voltage Vi3
  • T7 is turned on to write Vi3 Enter the anode of O1 so that O1 does not emit light and clear the residual charge of the anode of O1
  • T0 is opened to write Vi3 to the drain of T0 and the source of T0;
  • E2 provides a high voltage signal
  • E1 provides a high voltage signal
  • S2 provides a high voltage signal
  • S3 provides a high voltage signal
  • S0 provides a low voltage signal
  • D1 provides a voltage signal
  • T6 is turned on
  • D1 provides a voltage signal to The source of T0;
  • the voltage signal provided by D1 can be a positive voltage to set the source voltage of T0, thereby providing a bias voltage to the driving transistor T0, so that T0 is in a bias state to improve the magnetic field. stagnation phenomenon;
  • E2 provides a high voltage signal
  • E1 provides a high voltage signal
  • S2 provides a low voltage signal
  • S3 provides a low voltage signal
  • S0 provides a high voltage signal
  • I2 provides the second initial voltage Vi2
  • T2 is turned on, and T0 Open
  • T7 opens to write Vi2 to the source of T0 and the drain of T0 to reset the drain voltage of T0 and the source voltage of T0 to Vi2, so that T0 is in a biased state and improves the hysteresis phenomenon ;
  • E2 provides a low-voltage signal
  • E1 provides a low-voltage signal
  • S2 provides a high-voltage signal
  • S3 provides a high-voltage signal
  • S0 provides a high-voltage signal
  • T4 and T5 are turned on, and T0 drives O1 to emit light.
  • the voltage signal provided by the data line D1 may be the data voltage Vdata
  • the data voltage Vdata is the data voltage provided by the data line D1 during the first charging phase
  • the voltage value range of the data voltage Vdata may be, for example, greater than or equal to 1V and less than or equal to 6.5V; or,
  • the voltage signal provided by the data line D1 may be a reset voltage signal, and the voltage value range of the reset voltage signal may be greater than or equal to 4.6V and less than or equal to 7V;
  • FIG. 16 is a second operating timing diagram of at least one embodiment of the pixel circuit shown in FIG. 12 of the present disclosure in holding a frame.
  • the voltage value of the second initial voltage Vi2 may be greater than or equal to 4V and less than or equal to 7V, and the voltage value of the reset voltage Vi3 may be greater than or equal to - 4V and less than or equal to -2V, but not limited to this.
  • the display cycle includes a refresh frame and a hold frame.
  • the embodiment of the present disclosure The drive transistor included in the drive circuit is biased so that in the second reset phase in the hold frame, the potential of the source of the drive transistor and the potential of the drain of the drive transistor in the drive circuit are consistent with the refresh frame, which can improve flicker. Phenomenon.
  • the first initialization sub-circuit 131 includes a first transistor T1; the second initialization sub-circuit 132 includes a second transistor T2 ;
  • the driving circuit 11 includes a driving transistor T0; the light-emitting element is an organic light-emitting diode O1; the energy storage circuit 12 includes a storage capacitor C1;
  • the gate of the first transistor T1 is electrically connected to the first initial control terminal S1, the source of the first transistor T1 is electrically connected to the first initial voltage terminal I1, and the drain of the first transistor T1
  • the pole is electrically connected to the drain of the driving transistor T0;
  • the gate of the second transistor T2 is electrically connected to the second initial control terminal S2, the source of the second transistor T2 is electrically connected to the second initial voltage terminal I2, and the drain of the second transistor T2
  • the pole is electrically connected to the source of the driving transistor T0;
  • the compensation control circuit 14 includes a third transistor T3, the first lighting control circuit 41 includes a fourth transistor T4, the second lighting control circuit 42 includes a fifth transistor T5, and the data writing circuit 43 includes a sixth transistor.
  • the gate of the third transistor T3 is electrically connected to the compensation control terminal NG, the source of the third transistor T3 is electrically connected to the gate of the driving transistor T0, and the drain of the third transistor T3 is electrically connected to the compensation control terminal NG.
  • the drain of the driving transistor T0 is electrically connected;
  • the gate of the fourth transistor T4 is electrically connected to the first light emitting control terminal E1, the source of the fourth transistor T4 is electrically connected to the power supply voltage terminal VDD, and the drain of the fourth transistor T4 is electrically connected to the power supply voltage terminal VDD.
  • the source of the driving transistor T0 is electrically connected;
  • the gate of the fifth transistor T5 is electrically connected to the second light emitting control terminal E2, the source of the fifth transistor T5 is electrically connected to the drain of the driving transistor T0, and the drain of the fifth transistor T5
  • the electrode is electrically connected to the anode of the organic light-emitting diode O1;
  • the gate of the sixth transistor T6 is electrically connected to the write control terminal S0, the source of the sixth transistor T6 is electrically connected to the data line D1, and the drain of the sixth transistor T6 is electrically connected to the driving transistor.
  • the source of T0 is electrically connected;
  • the cathode of the organic light-emitting diode O1 is electrically connected to the low voltage terminal VSS;
  • the first terminal of the storage capacitor C1 is electrically connected to the gate of the driving transistor T0, and the second terminal of the storage capacitor C1 is electrically connected to the power supply voltage terminal VDD.
  • T3 is an oxide thin film transistor
  • T1, T2, T4, T5, T6 and T0 are LTPS thin film transistors
  • T3 is an n-type transistor
  • T1, T2, T4, T5, T6 and T0 are p-type transistors, but are not limited to this.
  • the reset circuit 44 includes a seventh transistor T7;
  • the gate of the seventh transistor T7 is electrically connected to the reset control terminal S3, the source of the seventh transistor T7 is electrically connected to the reset voltage terminal I3, and the drain of the seventh transistor T7 is electrically connected to the organic
  • the anode of the light-emitting diode O1 is electrically connected.
  • T7 is an LTPS thin film transistor, and T7 is a p-type transistor, but is not limited to this.
  • the refresh frame includes a first reset phase S12, a first charging phase S13, and a first reset phase S14 that are set successively. and the first luminescence stage S15;
  • S1 provides a low voltage signal
  • S0 provides a high voltage signal
  • NG provides a high voltage signal
  • S3 provides a high voltage signal
  • E1 and E2 provide high voltage signals
  • I1 provides the first initial voltage Vi1, as shown in Figure 20A
  • T1 is turned on to write Vi1 to the drain of T0
  • T3 is turned on to write Vi1 to the gate of T0, so that T0 can be turned on at the beginning of the first charging phase S13
  • the first initial Voltage Vi1 is a negative voltage.
  • Vi1 can be a -3V voltage signal, but is not limited to this;
  • S1 provides a high voltage signal
  • S0 provides a low voltage signal
  • NG provides a high voltage signal
  • S3 provides a high voltage signal
  • E1 and E2 provide high voltage signals
  • D1 provides the data voltage Vdata, as shown in Figure 20B
  • T6 is turned on, and T3 is turned on to write Vdata to the source of T0;
  • T0 is turned on, and Vdata charges C1 through T6, T0 and T3 until T0 is turned off.
  • the gate voltage of T0 is Vdata+Vth, and Vth is the threshold voltage of T0;
  • S1 provides a high voltage signal
  • S0 provides a high voltage signal
  • NG provides a low voltage signal
  • S3 provides a low voltage signal
  • E1 and E2 provide high voltage signals
  • T2 is turned on
  • I2 Provide a second initial voltage Vi2
  • Vi2 is a positive voltage; for example, Vi2 can be a 5V voltage signal
  • T0 is turned on to reset the drain voltage of T0 and the source voltage of T0 to Vi2, so that T0 is in a bias state, Improve hysteresis
  • T7 is turned on, and I3 provides reset voltage Vi3 to control O1 not to emit light and clear the residual charge on the anode of O1
  • Vi3 is a negative voltage, for example, Vi3 can be a -3V voltage signal;
  • S1 provides a high voltage signal
  • S0 provides a high voltage signal
  • NG provides a low voltage signal
  • S3 provides a high voltage signal
  • E1 and E2 provide low voltage signals, as shown in Figure 20D
  • T4 and T5 are turned on, T0 drives O1 to emit light.
  • Vi1 can be greater than or equal to -4V and less than or equal to -2V
  • Vi2 can be greater than or equal to 4V and less than or equal to 7V
  • Vi3 can be greater than or equal to -4V and less than or equal to -. 2V, but not limited to this.
  • the holding frame includes a second reset phase S22, a second reset phase S24 and a second light emitting phase S25 that are set successively. ;
  • NG provides a low voltage signal
  • T3 is turned off, and the gate of T0 is controlled to be disconnected from the drain of T0 to maintain the gate voltage of T0;
  • S0 provides a high voltage signal
  • T6 is turned off, and stops writing the voltage signal provided by D1 to the source of T0;
  • S1 provides a low voltage signal
  • S0 provides a high voltage signal
  • S3 provides a high voltage signal
  • E1 and E2 provide high voltage signals
  • I1 provides the first initial voltage Vi1
  • T1 is turned on to write Vi1 to T0 the drain;
  • S1 provides a high voltage signal
  • S0 provides a high voltage signal
  • S3 provides a low voltage signal
  • E1 and E2 provide high voltage signals
  • T2 is turned on
  • I2 provides the second initial voltage Vi2
  • Vi2 is a positive voltage
  • Vi2 can be a 5V voltage signal
  • T0 is turned on to reset the drain voltage of T0 and the source voltage of T0 to Vi2, so that T0 is in a bias state to improve hysteresis
  • T7 is turned on, and I3 provides the reset voltage Vi3 is used to control O1 not to emit light and remove the residual charge on the anode of O1
  • Vi3 is a negative voltage, for example, Vi3 can be a -3V voltage signal;
  • S1 provides a high-voltage signal
  • S0 provides a high-voltage signal
  • S3 provides a high-voltage signal
  • E1 and E2 provide low-voltage signals
  • T4 and T5 are turned on, and T0 drives O1 to emit light.
  • the holding frame includes a second reset phase S22, a holding set phase S23, and a second reset phase S24 that are set successively. and the second luminescence stage S25;
  • NG provides a low voltage signal
  • T3 is turned off, and the gate of T0 is controlled to be disconnected from the drain of T0 to maintain the gate voltage of T0;
  • S1 provides a low voltage signal
  • S0 provides a high voltage signal
  • S3 provides a high voltage signal
  • E1 and E2 provide high voltage signals
  • I1 provides the first initial voltage Vi1
  • T1 is turned on to write Vi1 to T0 the drain;
  • S1 provides a high voltage signal
  • S0 provides a low voltage signal
  • S3 provides a high voltage signal
  • E1 and E2 provide high voltage signals
  • T6 is turned on
  • D1 provides a voltage signal
  • the voltage signal provided by D1 is written to T0 the source of
  • the voltage signal provided by D1 can be a positive voltage to set the source voltage of T0, thereby providing a bias voltage to the driving transistor T0, so that T0 is in a bias state to improve the magnetic field. stagnation phenomenon;
  • S1 provides a high voltage signal
  • S0 provides a high voltage signal
  • S3 provides a low voltage signal
  • E1 and E2 provide high voltage signals
  • T2 is turned on
  • I2 provides the second initial voltage Vi2
  • Vi2 is a positive voltage
  • Vi2 can be a 5V voltage signal
  • T0 is turned on to reset the drain voltage of T0 and the source voltage of T0 to Vi2, so that T0 is in a bias state to improve hysteresis
  • T7 is turned on, and I3 provides the reset voltage Vi3 is used to control O1 not to emit light and remove the residual charge on the anode of O1
  • Vi3 is a negative voltage, for example, Vi3 can be a -3V voltage signal;
  • S1 provides a high-voltage signal
  • S0 provides a high-voltage signal
  • S3 provides a high-voltage signal
  • E1 and E2 provide low-voltage signals
  • T4 and T5 are turned on, and T0 drives O1 to emit light.
  • the voltage signal provided by the data line D1 may be the data voltage Vdata
  • the data voltage Vdata is the data voltage provided by the data line D1 during the first charging phase
  • the voltage value range of the data voltage Vdata may be, for example, greater than or equal to 1V and less than or equal to 6.5V; or,
  • the voltage signal provided by the data line D1 may be a reset voltage signal, and the voltage value range of the reset voltage signal may be greater than or equal to 4.6V and less than or equal to 7V;
  • the display cycle includes a refresh frame and a hold frame.
  • the embodiment of the present disclosure The drive transistor included in the drive circuit is biased so that during the reset phase in the hold frame, the potential of the source of the drive transistor and the potential of the drain of the drive transistor in the drive circuit are consistent with the refresh frame, which can improve the flicker phenomenon.
  • the driving method described in the embodiment of the present disclosure is applied to the above-mentioned pixel circuit.
  • the display cycle of the pixel circuit includes a refresh frame and a hold frame; the refresh frame and the hold frame respectively include a reset phase and a light emitting phase set successively. stage; the driving method includes:
  • the initialization circuit controls to provide the initial voltage provided by the initial voltage terminal to the initial control signal under the control of the initial control signal provided by the initial control terminal.
  • the initialization circuit is controlled by the initial control signal to control the initial voltage terminal in the refresh frame and the hold frame, at least in the reset phase.
  • the provided initial voltage is provided to a first end of the drive circuit and/or a second end of the drive circuit to provide a bias voltage to a drive transistor included in the drive circuit, such that the drive transistor included in the drive circuit In the bias state, it can improve the hysteresis phenomenon and improve the display effect.
  • the initialization circuit includes a first initialization sub-circuit; the pixel circuit also includes a first light-emitting control circuit, a second light-emitting control circuit, a data writing circuit and a reset circuit; the refresh frame includes a sequentially set third An initialization phase, a first reset phase, a first charging phase, a first reset phase and a first lighting phase; the driving method according to at least one embodiment of the present disclosure includes:
  • the first initialization sub-circuit writes the first initial voltage provided by the first initial voltage terminal into the second terminal of the driving circuit under the control of the first initial control signal;
  • the compensation control circuit Under the control of the compensation control signal, the control end of the drive circuit is controlled to be connected to the second end of the drive circuit;
  • the reset circuit writes the reset voltage provided by the reset voltage terminal into the first pole of the light-emitting element under the control of the reset control signal
  • the second light-emitting control circuit writes the reset voltage provided by the reset voltage terminal into the first pole of the light-emitting element under the control of the second light-emitting control signal.
  • the second terminal of the driving circuit is controlled to be connected to the first pole of the light-emitting element;
  • the compensation control circuit controls the control terminal of the driving circuit and the third terminal of the driving circuit under the control of the compensation control signal. The two ends are connected;
  • the data writing circuit writes the data voltage provided by the data line into the first end of the driving circuit, and the compensation control circuit controls the control of the driving circuit under the control of the compensation control signal.
  • the terminal is connected to the second terminal of the driving circuit;
  • the first initialization sub-circuit writes the first initial voltage provided by the first initial voltage terminal into the second terminal of the driving circuit under the control of the first initial control signal;
  • the driving circuit The circuit controls the connection between the first end of the drive circuit and the second end of the drive circuit under the control of the potential of its control end to control the drive transistor included in the drive circuit to be in a biased state;
  • the first light-emitting control circuit controls the connection between the power supply voltage terminal and the first terminal of the driving circuit under the control of the first light-emitting control signal;
  • the second light-emitting control circuit controls the connection between Under the control of the light-emitting control signal, the second terminal of the driving circuit is controlled to be connected to the first pole of the light-emitting element;
  • the driving circuit drives the light-emitting element to emit light under the control of the potential of its control terminal.
  • the initialization circuit includes a first initialization sub-circuit; the pixel circuit also includes a first lighting control circuit, a second lighting control circuit, a data writing circuit and a reset circuit; the holding frame It includes a second initialization stage, a second reset stage, a second reset stage and a second lighting stage that are set successively; the driving method includes:
  • the compensation control circuit controls the disconnection between the control terminal of the driving circuit and the second terminal of the driving circuit under the control of the compensation control signal
  • the first initialization sub-circuit writes the first initial voltage provided by the first initial voltage terminal into the second terminal of the driving circuit under the control of the first initial control signal;
  • the reset circuit In the second reset phase, the reset circuit writes the reset voltage provided by the reset voltage terminal into the first pole of the light-emitting element under the control of the reset control signal, and the second light-emitting control circuit writes the reset voltage provided by the reset voltage terminal into the first pole of the light-emitting element. , controlling the connection between the second end of the driving circuit and the first pole of the light-emitting element;
  • the first initialization sub-circuit writes the first initial voltage provided by the first initial voltage terminal into the second terminal of the driving circuit under the control of the first initial control signal;
  • the driving circuit The circuit controls the connection between the first end of the drive circuit and the second end of the drive circuit under the control of the potential of its control end to control the drive transistor included in the drive circuit to be in a biased state;
  • the first light-emitting control circuit controls the connection between the power supply voltage end and the first end of the driving circuit under the control of the first light-emitting control signal; the second light-emitting control circuit controls the second light-emitting control circuit in the second light-emitting stage.
  • the second terminal of the driving circuit is controlled to be connected to the first pole of the light-emitting element; the driving circuit drives the light-emitting element to emit light under the control of the potential of its control terminal.
  • the hold frame further includes a hold setting phase disposed between the second reset phase and the second reset phase;
  • the driving method further includes:
  • the data writing circuit writes the voltage signal provided by the data line into the first end of the driving circuit.
  • the initialization circuit includes a second initialization sub-circuit;
  • the pixel circuit also includes a first light-emitting control circuit, a second light-emitting control circuit, a data writing circuit and a reset circuit;
  • the refresh frame includes a sequentially set third An initialization phase, a first reset phase, a first charging phase, a first reset phase and a first lighting phase;
  • the driving method according to at least one embodiment of the present disclosure includes:
  • the second initialization sub-circuit writes the second initial voltage provided by the second initial voltage terminal into the first terminal of the driving circuit under the control of the second initial control signal;
  • the compensation control circuit Under the control of the compensation control signal, the control terminal of the driving circuit is controlled to be connected to the second terminal of the driving circuit;
  • the reset circuit writes the reset voltage provided by the reset voltage terminal into the first pole of the light-emitting element under the control of the reset control signal;
  • the second light-emitting control circuit writes the reset voltage provided by the reset voltage terminal into the first pole of the light-emitting element;
  • the compensation control circuit controls the control terminal of the driving circuit and the third terminal of the driving circuit under the control of the compensation control signal. The two ends are connected;
  • the data writing circuit writes the data voltage provided by the data line into the first end of the driving circuit, and the compensation control circuit controls the control of the driving circuit under the control of the compensation control signal.
  • the terminal is connected to the second terminal of the driving circuit;
  • the second initialization sub-circuit writes the second initial voltage provided by the second initial voltage terminal into the first terminal of the driving circuit under the control of the second initial control signal;
  • the driving circuit The circuit controls the connection between the first end of the drive circuit and the second end of the drive circuit under the control of the potential of its control end to control the drive transistor included in the drive circuit to be in a biased state;
  • the first lighting control circuit controls the connection between the power supply voltage terminal and the first terminal of the driving circuit under the control of the first lighting control signal; the second lighting control circuit controls the connection between the first lighting stage and the first lighting stage.
  • the second terminal of the driving circuit Under the control of the light-emitting control signal, the second terminal of the driving circuit is controlled to be connected to the first pole of the light-emitting element; the driving circuit drives the light-emitting element to emit light under the control of the potential of its control terminal.
  • the initialization circuit includes a second initialization sub-circuit; the pixel circuit also includes a first lighting control circuit, a second lighting control circuit, a data writing circuit and a reset circuit; the holding frame It includes a second initialization stage, a second reset stage, a second reset stage and a second lighting stage that are set successively; the driving method includes:
  • the compensation control circuit controls the disconnection between the control terminal of the driving circuit and the second terminal of the driving circuit under the control of the compensation control signal
  • the second initialization sub-circuit writes the second initial voltage provided by the second initial voltage terminal into the first terminal of the driving circuit under the control of the second initial control signal;
  • the reset circuit writes the reset voltage provided by the reset voltage terminal into the first pole of the light-emitting element under the control of the reset control signal;
  • the second light-emitting control circuit writes the reset voltage provided by the reset voltage terminal into the first pole of the light-emitting element; , controlling the connection between the second end of the driving circuit and the first pole of the light-emitting element;
  • the second initialization sub-circuit writes the second initial voltage provided by the second initial voltage terminal into the first terminal of the driving circuit under the control of the second initial control signal;
  • the driving circuit Under the control of the potential of its control end, the circuit controls the connection between the first end of the drive circuit and the second end of the drive circuit to control the drive transistor included in the drive circuit to be in a biased state;
  • the first light-emitting control circuit controls the connection between the power supply voltage end and the first end of the driving circuit under the control of the first light-emitting control signal; the second light-emitting control circuit controls the second light-emitting control circuit in the second light-emitting stage.
  • the second terminal of the driving circuit is controlled to be connected to the first pole of the light-emitting element; the driving circuit drives the light-emitting element to emit light under the control of the potential of its control terminal.
  • the hold frame further includes a hold setting phase disposed between the second reset phase and the second reset phase;
  • the driving method further includes:
  • the data writing circuit writes the voltage signal provided by the data line into the first end of the driving circuit.
  • the initialization circuit includes a first initialization sub-circuit and a second initialization sub-circuit;
  • the pixel circuit also includes a first light-emitting control circuit, a second light-emitting control circuit and a data writing circuit;
  • the refresh frame includes successive The first reset stage, the first charging stage, the first reset stage and the first lighting stage are set;
  • the driving method according to at least one embodiment of the present disclosure includes:
  • the first initialization sub-circuit writes the first initial voltage provided by the first initial voltage terminal into the second terminal of the driving circuit under the control of the first initial control signal, and the compensation control The circuit controls the connection between the control end of the drive circuit and the second end of the drive circuit under the control of the compensation control signal;
  • the data writing circuit writes the data voltage provided by the data line into the first end of the driving circuit, and the compensation control circuit controls the control of the driving circuit under the control of the compensation control signal.
  • the terminal is connected to the second terminal of the driving circuit;
  • the second initialization sub-circuit writes the second initial voltage provided by the second initial voltage terminal into the first terminal of the driving circuit under the control of the second initial control signal, so
  • the drive circuit controls the connection between the first end of the drive circuit and the second end of the drive circuit under the control of the potential of its control end to control the drive transistor included in the drive circuit to be in a biased state;
  • the first light-emitting control circuit controls the connection between the power supply voltage terminal and the first terminal of the driving circuit under the control of the first light-emitting control signal;
  • the second light-emitting control circuit controls the connection between Under the control of the light-emitting control signal, the second terminal of the driving circuit is controlled to be connected to the first pole of the light-emitting element;
  • the driving circuit drives the light-emitting element to emit light under the control of the potential of its control terminal.
  • the pixel circuit further includes a reset circuit; the driving method further includes:
  • the reset circuit writes the reset voltage provided by the reset voltage terminal into the first pole of the light-emitting element under the control of the reset control signal.
  • the initialization circuit includes a first initialization sub-circuit and a second initialization sub-circuit;
  • the pixel circuit also includes a first lighting control circuit, a second lighting control circuit and a data writing circuit;
  • the holding frame includes successive The second initialization phase, the second reset phase, the second reset phase and the second lighting phase are set;
  • the driving method according to at least one embodiment of the present disclosure includes:
  • the compensation control circuit controls the disconnection between the control terminal of the driving circuit and the second terminal of the driving circuit under the control of the compensation control signal
  • the first initialization sub-circuit writes the first initial voltage provided by the first initial voltage terminal into the second terminal of the driving circuit under the control of the first initial control signal;
  • the second initialization sub-circuit writes the second initial voltage provided by the second initial voltage terminal into the first terminal of the driving circuit under the control of the second initial control signal, so
  • the drive circuit controls the connection between the first end of the drive circuit and the second end of the drive circuit under the control of the potential of its control end to control the drive transistor included in the drive circuit to be in a biased state;
  • the first light-emitting control circuit controls the connection between the power supply voltage end and the first end of the driving circuit under the control of the first light-emitting control signal; the second light-emitting control circuit controls the second light-emitting control circuit in the second light-emitting stage.
  • the second terminal of the driving circuit is controlled to be connected to the first pole of the light-emitting element; the driving circuit drives the light-emitting element to emit light under the control of the potential of its control terminal.
  • the pixel circuit further includes a reset circuit;
  • the driving method according to at least one embodiment of the present disclosure further includes:
  • the reset circuit writes the reset voltage provided by the reset voltage terminal into the first pole of the light-emitting element under the control of the reset control signal.
  • the hold frame further includes a hold setting phase disposed between the second reset phase and the second reset phase;
  • the driving method further includes:
  • the data writing circuit writes the voltage signal provided by the data line into the first end of the driving circuit.
  • the display device includes the above-mentioned pixel circuit.
  • the display device provided in the embodiment of the present disclosure can be any product or component with a display function such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, etc.

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Abstract

一种像素电路、驱动方法和显示装置。像素电路，包括发光元件（E0）、驱动电路（11）、储能电路（12）、初始化电路和补偿控制电路（14）；像素电路的显示周期包括刷新帧和保持帧；刷新帧和保持帧分别包括先后设置的重置阶段和发光阶段；初始化电路在初始控制信号的控制下，在刷新帧和保持帧，至少在重置阶段，控制将初始电压提供至驱动电路（11）的第一端和/或驱动电路（11）的第二端。

Description

像素电路、驱动方法和显示装置 技术领域
本公开涉及显示技术领域，尤其涉及一种像素电路、驱动方法和显示装置。
背景技术
近年来，随着智能显示技术的进步，有机发光显示器(Organic Light Emitting Diode，OLED)成为当今显示器研究领域的热点之一，随着显示面板的减薄化，边框变窄化，以及显示屏低频技术的发展，显示面板优化设计越来越严峻。
在相关技术中，像素电路包括的驱动晶体管的阈值电压漂移严重，不利于改善磁滞，影响显示效果。
发明内容
在一个方面中，本公开实施例提供了一种像素电路，包括发光元件、驱动电路、储能电路、初始化电路和补偿控制电路；所述像素电路的显示周期包括刷新帧和保持帧；所述刷新帧和所述保持帧分别包括先后设置的重置阶段和发光阶段；
所述储能电路与所述驱动电路的控制端电连接，用于储存电能；
所述补偿控制电路分别与补偿控制端、所述驱动电路的控制端和所述驱动电路的第二端电连接，用于在所述补偿控制端提供的补偿控制信号的控制下，控制所述驱动电路的控制端与所述驱动电路的第二端之间连通；
所述初始化电路分别与初始控制端和初始电压端电连接，所述初始化电路分别与所述驱动电路的第一端和/或所述驱动电路的第二端电连接，用于在所述初始控制端提供的初始控制信号的控制下，在所述刷新帧和所述保持帧，至少在所述重置阶段，控制将所述初始电压端提供的初始电压提供至所述驱动电路的第一端和/或所述驱动电路的第二端；
所述驱动电路的第二端与所述发光元件电连接，用于在所述驱动电路的 控制端的电位的控制下，驱动所述发光元件。
可选的，所述驱动电路包括的驱动晶体管为p型晶体管，所述初始电压为正电压。
可选的，所述初始化电路包括第一初始化子电路；所述初始控制端包括第一初始控制端，所述初始电压端包括第一初始电压端；
所述第一初始化子电路分别与所述第一初始控制端、所述第一初始电压端和所述驱动电路的第二端电连接，用于在所述第一初始控制端提供的第一初始控制信号的控制下，在所述刷新帧和所述保持帧，至少在所述重置阶段，将所述第一初始电压端提供的第一初始电压写入所述驱动电路的第二端。
可选的，所述初始化电路包括第二初始化子电路；所述初始控制端包括第二初始控制端，所述初始电压端包括第二初始电压端；
所述第二初始化子电路分别与所述第二初始控制端、第二初始电压端和所述驱动电路的第一端电连接，用于在所述第二初始控制端提供的第二初始控制信号的控制下，在所述刷新帧和所述保持帧，至少在所述重置阶段，将所述第二初始电压端提供的第二初始电压写入所述驱动电路的第一端。
可选的，所述初始化电路包括第一初始化子电路和第二初始化子电路；所述初始控制端包括第一初始控制端和第二初始控制端，所述初始电压端包括第一初始电压端和第二初始电压端；
所述第一初始化子电路分别与所述第一初始控制端、所述第一初始电压端和所述驱动电路的第二端电连接，用于在所述第一初始控制端提供的第一初始控制信号的控制下，在所述刷新帧和所述保持帧，至少在所述重置阶段，将所述第一初始电压端提供的第一初始电压写入所述驱动电路的第二端；
所述第二初始化子电路分别与所述第二初始控制端、第二初始电压端和所述驱动电路的第一端电连接，用于在所述第二初始控制端提供的第二初始控制信号的控制下，在所述刷新帧和所述保持帧，至少在所述重置阶段，将所述第二初始电压端提供的第二初始电压写入所述驱动电路的第一端。
可选的，所述第一初始化子电路包括第一晶体管；
所述第一晶体管的控制极与所述第一初始控制端电连接，所述第一晶体管的第一极与所述第一初始电压端电连接，所述第一晶体管的第二极与所述 驱动电路的第二端电连接。
可选的，所述第二初始化子电路包括第二晶体管；
所述第二晶体管的控制极与所述第二初始控制端电连接，所述第二晶体管的第一极与所述第二初始电压端电连接，所述第二晶体管的第二极与所述驱动电路的第一端电连接。
可选的，所述第一初始化子电路包括第一晶体管，所述第二初始化子电路包括第二晶体管；
所述第一晶体管的控制极与所述第一初始控制端电连接，所述第一晶体管的第一极与所述第一初始电压端电连接，所述第一晶体管的第二极与所述驱动电路的第二端电连接；
所述第二晶体管的控制极与所述第二初始控制端电连接，所述第二晶体管的第一极与所述第二初始电压端电连接，所述第二晶体管的第二极与所述驱动电路的第一端电连接。
可选的，本公开至少一实施例所述的像素电路还包括第一发光控制电路、第二发光控制电路和数据写入电路；
所述第一发光控制电路分别与第一发光控制端、电源电压端和所述驱动电路的第一端电连接，用于在所述第一发光控制端提供的第一发光控制信号的控制下，控制所述电源电压端与所述驱动电路的第一端之间连通；
所述第二发光控制电路分别与第二发光控制端、所述驱动电路的第二端和所述发光元件的第一极电连接，用于在所述第二发光控制端提供的第二发光控制信号的控制下，控制所述驱动电路的第二端与所述发光元件的第一极之间连通；所述发光元件的第二极与第一电压端电连接；
所述数据写入电路分别与写入控制端、数据线和所述驱动电路的第一端电连接，用于在所述写入控制端提供的写入控制信号的控制下，控制所述数据线与所述驱动电路的第一端之间连通。
可选的，本公开至少一实施例所述的像素电路还包括复位电路；
所述复位电路分别与复位控制端、复位电压端和所述发光元件的第一极电连接，用于在所述复位控制端提供的复位控制信号的控制下，控制将所述复位电压端提供的复位电压写入所述发光元件的第一极。
可选的，所述补偿控制电路包括第三晶体管，所述第一发光控制电路包括第四晶体管，所述第二发光控制电路包括第五晶体管，所述数据写入电路包括第六晶体管，所述驱动电路包括驱动晶体管；
所述第三晶体管的控制极与所述补偿控制端电连接，所述第三晶体管的第一极与所述驱动电路的控制端电连接，所述第三晶体管的第二极与所述驱动电路的第二端电连接；
所述第四晶体管的控制极与所述第一发光控制端电连接，所述第四晶体管的第一极与所述电源电压端电连接，所述第四晶体管的第二极与所述驱动电路的第一端电连接；
所述第五晶体管的控制极与所述第二发光控制端电连接，所述第五晶体管的第一极与所述驱动电路的第二端电连接，所述第五晶体管的第二极与所述发光元件的第一极电连接；
所述第六晶体管的控制极与写入控制端电连接，所述第六晶体管的第一极与所述数据线电连接，所述第六晶体管的第二极与所述驱动电路的第一端电连接；
所述驱动晶体管的控制极与所述驱动电路的控制端电连接，所述驱动晶体管的第一极与所述驱动电路的第一端电连接，所述驱动晶体管的第二极与所述驱动电路的第二端电连接。
可选的，所述第三晶体管为氧化物薄膜晶体管。
可选的，所述复位电路包括第七晶体管；
所述第七晶体管的控制极分别与复位控制端电连接，所述第七晶体管的第一极与所述复位电压端电连接，所述第七晶体管的第二极与所述发光元件的第一极电连接。
可选的，所述第七晶体管为氧化物薄膜晶体管。
在第二个方面中，本公开实施例提供一种驱动方法，应用于上述的像素电路，所述像素电路的显示周期包括刷新帧和保持帧；所述刷新帧和所述保持帧分别包括先后设置的重置阶段和发光阶段；所述驱动方法包括：
在所述刷新帧和所述保持帧，至少在所述重置阶段，初始化电路在所述初始控制端提供的初始控制信号的控制下，控制将所述初始电压端提供的初 始电压提供至所述驱动电路的第一端和/或所述驱动电路的第二端。
可选的，所述初始化电路包括第一初始化子电路；所述像素电路还包括第一发光控制电路、第二发光控制电路、数据写入电路和复位电路；所述刷新帧包括先后设置的第一初始化阶段、第一复位阶段、第一充电阶段、第一重置阶段和第一发光阶段；所述驱动方法包括：
在所述第一初始化阶段，所述第一初始化子电路在第一初始控制信号的控制下，将第一初始电压端提供的第一初始电压写入驱动电路的第二端；补偿控制电路在补偿控制信号的控制下，控制所述驱动电路的控制端与所述驱动电路的第二端之间连通；
在所述第一复位阶段，所述复位电路在复位控制信号的控制下，将复位电压端提供的复位电压写入发光元件的第一极，第二发光控制电路在第二发光控制信号的控制下，控制所述驱动电路的第二端与所述发光元件的第一极之间连通；补偿控制电路在补偿控制信号的控制下，控制所述驱动电路的控制端与所述驱动电路的第二端之间连通；
在所述第一充电阶段，所述数据写入电路将数据线提供的数据电压写入所述驱动电路的第一端，补偿控制电路在补偿控制信号的控制下，控制所述驱动电路的控制端与所述驱动电路的第二端之间连通；
在所述第一重置阶段，所述第一初始化子电路在第一初始控制信号的控制下，将第一初始电压端提供的第一初始电压写入驱动电路的第二端；所述驱动电路在其控制端的电位的控制下，控制所述驱动电路的第一端与所述驱动电路的第二端之间连通；
在第一发光阶段，所述第一发光控制电路在第一发光控制信号的控制下，控制电源电压端与所述驱动电路的第一端之间连通；所述第二发光控制电路在第二发光控制信号的控制下，控制所述驱动电路的第二端与所述发光元件的第一极之间连通；所述驱动电路在其控制端的电位的控制下，驱动所述发光元件发光。
可选的，所述初始化电路包括第一初始化子电路；所述像素电路还包括第一发光控制电路、第二发光控制电路、数据写入电路和复位电路；所述保持帧包括先后设置的第二初始化阶段、第二复位阶段、第二重置阶段和第二 发光阶段；所述驱动方法包括：
在所述保持帧，补偿控制电路在补偿控制信号的控制下，控制所述驱动电路的控制端与所述驱动电路的第二端之间断开；
在所述第二初始化阶段，所述第一初始化子电路在第一初始控制信号的控制下，将第一初始电压端提供的第一初始电压写入驱动电路的第二端；
在所述第二复位阶段，所述复位电路在复位控制信号的控制下，将复位电压端提供的复位电压写入发光元件的第一极，第二发光控制电路在第二发光控制信号的控制下，控制所述驱动电路的第二端与所述发光元件的第一极之间连通；
在所述第二重置阶段，所述第一初始化子电路在第一初始控制信号的控制下，将第一初始电压端提供的第一初始电压写入驱动电路的第二端；所述驱动电路在其控制端的电位的控制下，控制所述驱动电路的第一端与所述驱动电路的第二端之间连通；
在第二发光阶段，所述第一发光控制电路在第一发光控制信号的控制下，控制电源电压端与所述驱动电路的第一端之间连通；所述第二发光控制电路在第二发光控制信号的控制下，控制所述驱动电路的第二端与所述发光元件的第一极之间连通；所述驱动电路在其控制端的电位的控制下，驱动所述发光元件发光；
所述保持帧还包括设置于第二复位阶段和第二重置阶段之间的保持置位阶段；所述驱动方法还包括：
在所述保持置位阶段，所述数据写入电路将数据线提供的电压信号写入所述驱动电路的第一端。
可选的，所述初始化电路包括第二初始化子电路；所述像素电路还包括第一发光控制电路、第二发光控制电路、数据写入电路和复位电路；所述刷新帧包括先后设置的第一初始化阶段、第一复位阶段、第一充电阶段、第一重置阶段和第一发光阶段；所述驱动方法包括：
在所述第一初始化阶段，所述第二初始化子电路在第二初始控制信号的控制下，将第二初始电压端提供的第二初始电压写入驱动电路的第一端；补偿控制电路在补偿控制信号的控制下，控制所述驱动电路的控制端与所述驱 动电路的第二端之间连通；
在所述第一复位阶段，所述复位电路在复位控制信号的控制下，将复位电压端提供的复位电压写入发光元件的第一极；第二发光控制电路在第二发光控制信号的控制下，控制所述驱动电路的第二端与所述发光元件的第一极之间连通；补偿控制电路在补偿控制信号的控制下，控制所述驱动电路的控制端与所述驱动电路的第二端之间连通；
在所述第一充电阶段，所述数据写入电路将数据线提供的数据电压写入所述驱动电路的第一端，补偿控制电路在补偿控制信号的控制下，控制所述驱动电路的控制端与所述驱动电路的第二端之间连通；
在所述第一重置阶段，所述第二初始化子电路在第二初始控制信号的控制下，将第二初始电压端提供的第二初始电压写入驱动电路的第一端；所述驱动电路在其控制端的电位的控制下，控制所述驱动电路的第一端与所述驱动电路的第二端之间连通；
在第一发光阶段，所述第一发光控制电路在第一发光控制信号的控制下，控制电源电压端与所述驱动电路的第一端之间连通；所述第二发光控制电路在第二发光控制信号的控制下，控制所述驱动电路的第二端与所述发光元件的第一极之间连通；所述驱动电路在其控制端的电位的控制下，驱动所述发光元件发光。
可选的，所述初始化电路包括第二初始化子电路；所述像素电路还包括第一发光控制电路、第二发光控制电路、数据写入电路和复位电路；所述保持帧包括先后设置的第二初始化阶段、第二复位阶段、第二重置阶段和第二发光阶段；所述驱动方法包括：
在所述保持帧，补偿控制电路在补偿控制信号的控制下，控制所述驱动电路的控制端与所述驱动电路的第二端之间断开；
在所述第二初始化阶段，所述第二初始化子电路在第二初始控制信号的控制下，将第二初始电压端提供的第二初始电压写入驱动电路的第一端；
在所述第二复位阶段，所述复位电路在复位控制信号的控制下，将复位电压端提供的复位电压写入发光元件的第一极；第二发光控制电路在第二发光控制信号的控制下，控制所述驱动电路的第二端与所述发光元件的第一极 之间连通；
在所述第二重置阶段，所述第二初始化子电路在第二初始控制信号的控制下，将第二初始电压端提供的第二初始电压写入驱动电路的第一端；所述驱动电路在其控制端的电位的控制下，控制所述驱动电路的第一端与所述驱动电路的第二端之间连通；
在第二发光阶段，所述第一发光控制电路在第一发光控制信号的控制下，控制电源电压端与所述驱动电路的第一端之间连通；所述第二发光控制电路在第二发光控制信号的控制下，控制所述驱动电路的第二端与所述发光元件的第一极之间连通；所述驱动电路在其控制端的电位的控制下，驱动所述发光元件发光；
所述保持帧还包括设置于第二复位阶段和第二重置阶段之间的保持置位阶段；所述驱动方法还包括：
在所述保持置位阶段，所述数据写入电路将数据线提供的电压信号写入所述驱动电路的第一端。
可选的，所述初始化电路包括第一初始化子电路和第二初始化子电路；所述像素电路还包括第一发光控制电路、第二发光控制电路和数据写入电路；所述刷新帧包括先后设置的第一复位阶段、第一充电阶段、第一重置阶段和第一发光阶段；所述驱动方法包括：
在所述第一复位阶段，所述第一初始化子电路在第一初始控制信号的控制下，将第一初始电压端提供的第一初始电压写入所述驱动电路的第二端，补偿控制电路在补偿控制信号的控制下，控制所述驱动电路的控制端与所述驱动电路的第二端之间连通；
在所述第一充电阶段，所述数据写入电路将数据线提供的数据电压写入所述驱动电路的第一端，补偿控制电路在补偿控制信号的控制下，控制所述驱动电路的控制端与所述驱动电路的第二端之间连通；
在所述第一重置阶段，所述第二初始化子电路在第二初始控制信号的控制下，将第二初始电压端提供的第二初始电压写入所述驱动电路的第一端，所述驱动电路在其控制端的电位的控制下，控制所述驱动电路的第一端与所述驱动电路的第二端之间连通；
在第一发光阶段，所述第一发光控制电路在第一发光控制信号的控制下，控制电源电压端与所述驱动电路的第一端之间连通；所述第二发光控制电路在第二发光控制信号的控制下，控制所述驱动电路的第二端与所述发光元件的第一极之间连通；所述驱动电路在其控制端的电位的控制下，驱动所述发光元件发光。
可选的，所述像素电路还包括复位电路；所述驱动方法还包括：
在所述第一重置阶段，所述复位电路在复位控制信号的控制下，将复位电压端提供的复位电压写入发光元件的第一极。
可选的，所述初始化电路包括第一初始化子电路和第二初始化子电路；所述像素电路还包括第一发光控制电路、第二发光控制电路和数据写入电路；所述保持帧包括先后设置的第二复位阶段、第二重置阶段和第二发光阶段；所述驱动方法包括：
在所述保持帧，补偿控制电路在补偿控制信号的控制下，控制所述驱动电路的控制端与所述驱动电路的第二端之间断开；
在所述第二复位阶段，所述第一初始化子电路在第一初始控制信号的控制下，将第一初始电压端提供的第一初始电压写入所述驱动电路的第二端；
在所述第二重置阶段，所述第二初始化子电路在第二初始控制信号的控制下，将第二初始电压端提供的第二初始电压写入所述驱动电路的第一端，所述驱动电路在其控制端的电位的控制下，控制所述驱动电路的第一端与所述驱动电路的第二端之间连通；
在第二发光阶段，所述第一发光控制电路在第一发光控制信号的控制下，控制电源电压端与所述驱动电路的第一端之间连通；所述第二发光控制电路在第二发光控制信号的控制下，控制所述驱动电路的第二端与所述发光元件的第一极之间连通；所述驱动电路在其控制端的电位的控制下，驱动所述发光元件发光。
可选的，所述像素电路还包括复位电路；所述驱动方法还包括：
在所述第二重置阶段，所述复位电路在复位控制信号的控制下，将复位电压端提供的复位电压写入发光元件的第一极。
可选的，所述保持帧还包括设置于第二复位阶段和第二重置阶段之间的 保持置位阶段；所述驱动方法还包括：
在所述保持置位阶段，所述数据写入电路将数据线提供的电压信号写入所述驱动电路的第一端。
在第三个方面中，本公开实施例提供一种显示装置，包括上述的像素电路。
附图说明
图1是本公开至少一实施例所述的像素电路的结构图；
图2是本公开至少一实施例所述的像素电路的结构图；
图3是本公开至少一实施例所述的像素电路的结构图；
图4是本公开至少一实施例所述的像素电路的结构图；
图5是本公开至少一实施例所述的像素电路的结构图；
图6是本公开至少一实施例所述的像素电路的结构图；
图7是本公开至少一实施例所述的像素电路的结构图；
图8是本公开至少一实施例所述的像素电路的电路图；
图9是本公开图8所示的像素电路的至少一实施例的工作时序图；
图10A是本公开图8所示的像素电路的至少一实施例在第一初始化阶段S11的工作状态示意图；
图10B是本公开图8所示的像素电路的至少一实施例在第一复位阶段S12的工作状态示意图；
图10C是本公开图8所示的像素电路的至少一实施例在第一充电阶段S13的工作状态示意图；
图10D是本公开图8所示的像素电路的至少一实施例在第一重置阶段S14的工作状态示意图；
图10E是本公开图8所示的像素电路的至少一实施例在第一发光阶段S15的工作状态示意图；
图11是本公开图8所示的像素电路的至少一实施例的工作时序图；
图12是本公开至少一实施例所述的像素电路的电路图；
图13是本公开图11所示的像素电路的至少一实施例的工作时序图；
图14A是本公开图12所示的像素电路的至少一实施例在第一初始化阶段S11的工作状态示意图；
图14B是本公开图12所示的像素电路的至少一实施例在第一复位阶段S12的工作状态示意图；
图14C是本公开图12所示的像素电路的至少一实施例在第一充电阶段S13的工作状态示意图；
图14D是本公开图12所示的像素电路的至少一实施例在第一重置阶段S14的工作状态示意图；
图14E是本公开图12所示的像素电路的至少一实施例在第一发光阶段S15的工作状态示意图；
图15是本公开图12所示的像素电路的至少一实施例的工作时序图；
图16是本公开图12所示的像素电路的至少一实施例的工作时序图；
图17是本公开至少一实施例所述的像素电路的电路图；
图18是本公开至少一实施例所述的像素电路的电路图；
图19是本公开图18所示的像素电路的至少一实施例的工作时序图；
图20A是本公开图18所示的像素电路的至少一实施例在第一复位阶段S12的工作状态示意图；
图20B是本公开图18所示的像素电路的至少一实施例在第一充电阶段S13的工作状态示意图；
图20C是本公开图18所示的像素电路的至少一实施例在第一重置阶段S14的工作状态示意图；
图20D是本公开图18所示的像素电路的至少一实施例在第一发光阶段S15的工作状态示意图；
图21是本公开图18所示的像素电路的至少一实施例的工作时序图；
图22是本公开图18所示的像素电路的至少一实施例的工作时序图。
具体实施方式
下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而 不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。
本公开所有实施例中采用的晶体管均可以为三极管、薄膜晶体管或场效应管或其他特性相同的器件。在本公开实施例中，为区分晶体管除控制极之外的两极，将其中一极称为第一极，另一极称为第二极。
在实际操作时，当所述晶体管为三极管时，所述控制极可以为基极，所述第一极可以为集电极，所述第二极可以发射极；或者，所述控制极可以为基极，所述第一极可以为发射极，所述第二极可以集电极。
在实际操作时，当所述晶体管为薄膜晶体管或场效应管时，所述控制极可以为栅极，所述第一极可以为漏极，所述第二极可以为源极；或者，所述控制极可以为栅极，所述第一极可以为源极，所述第二极可以为漏极。
本公开实施例所述的像素电路包括发光元件、驱动电路、储能电路、初始化电路和补偿控制电路；所述像素电路的显示周期包括刷新帧和保持帧；所述刷新帧和所述保持帧分别包括先后设置的重置阶段和发光阶段；
所述储能电路与所述驱动电路的控制端电连接，用于储存电能；
所述补偿控制电路分别与补偿控制端、所述驱动电路的控制端和所述驱动电路的第二端电连接，用于在所述补偿控制端提供的补偿控制信号的控制下，控制所述驱动电路的控制端与所述驱动电路的第二端之间连通；
所述初始化电路分别与初始控制端和初始电压端电连接，所述初始化电路分别与所述驱动电路的第一端和/或所述驱动电路的第二端电连接，用于在所述初始控制端提供的初始控制信号的控制下，在所述刷新帧和所述保持帧，至少在所述重置阶段，控制将所述初始电压端提供的初始电压提供至所述驱动电路的第一端和/或所述驱动电路的第二端；
所述驱动电路的第二端与所述发光元件电连接，用于在所述驱动电路的控制端的电位的控制下，驱动所述发光元件。
本公开实施例所述的像素电路在工作时，所述初始化电路在初始控制信号的控制下，在所述刷新帧和所述保持帧，至少在所述重置阶段，控制将所述初始电压端提供的初始电压提供至所述驱动电路的第一端和/或所述驱动电路的第二端，以向所述驱动电路包括的驱动晶体管提供偏置电压，使得所 述驱动电路包括的驱动晶体管处于偏压状态，以能改善磁滞现象，提升显示效果。
本公开实施例所述的像素电路在低频显示时，能够改善Flicker(闪烁)现象。
由于在低频显示时，显示周期包括刷新帧和保持帧，在保持帧中的重置阶段，本公开实施例对所述驱动电路包括的驱动晶体管进行偏置，使得在保持帧中的重置阶段，驱动电路中的驱动晶体管的源极的电位和驱动晶体管的漏极的电位与刷新帧一致，能够改善闪烁现象。
在本公开至少一实施例中，所述驱动电路包括的驱动晶体管为p型晶体管，所述初始电压为正电压。
可选的，所述储能电路可以包括存储电容；
所述存储电容的第一端与所述驱动电路的控制端电连接，所述存储电容的第二端与电源电压端电连接。
在本公开至少一实施例中，所述初始化电路可以包括第一初始化子电路；所述初始控制端包括第一初始控制端，所述初始电压端包括第一初始电压端；
所述第一初始化子电路分别与所述第一初始控制端、所述第一初始电压端和所述驱动电路的第二端电连接，用于在所述第一初始控制端提供的第一初始控制信号的控制下，在所述刷新帧和所述保持帧，至少在所述重置阶段，将所述第一初始电压端提供的第一初始电压写入所述驱动电路的第二端。
如图1所示，本公开至少一实施例所述的像素电路可以包括发光元件E0、驱动电路11、储能电路12、初始化电路和补偿控制电路14；所述像素电路的显示周期包括刷新帧和保持帧；所述刷新帧和所述保持帧分别包括先后设置的重置阶段和发光阶段；
所述储能电路12与所述驱动电路的控制端电连接，用于储存电能；
所述补偿控制电路14分别与补偿控制端NG、所述驱动电路11的控制端和所述驱动电路11的第二端电连接，用于在所述补偿控制端NG提供的补偿控制信号的控制下，控制所述驱动电路11的控制端与所述驱动电路11的第二端之间连通；
所述初始化电路包括第一初始化子电路131；所述初始控制端包括第一 初始控制端S1，所述初始电压端包括第一初始电压端I1；
所述第一初始化子电路131分别与所述第一初始控制端S1、所述第一初始电压端I1和所述驱动电路11的第二端电连接，用于在所述第一初始控制端S1提供的第一初始控制信号的控制下，在所述刷新帧和所述保持帧，至少在所述重置阶段，将所述第一初始电压端I1提供的第一初始电压写入所述驱动电路11的第二端，以控制所述驱动电路11包括的驱动晶体管处于偏压状态；
所述驱动电路11的第二端与所述发光元件E0电连接，用于在所述驱动电路11的控制端的电位的控制下，驱动所述发光元件E0。
在本公开至少一实施例中，所述初始化电路包括第二初始化子电路；所述初始控制端包括第二初始控制端，所述初始电压端包括第二初始电压端；
所述第二初始化子电路分别与所述第二初始控制端、第二初始电压端和所述驱动电路的第一端电连接，用于在所述第二初始控制端提供的第二初始控制信号的控制下，在所述刷新帧和所述保持帧，至少在所述重置阶段，将所述第二初始电压端提供的第二初始电压写入所述驱动电路的第一端。
如图2所示，本公开至少一实施例所述的像素电路可以包括发光元件E0、驱动电路11、储能电路12、初始化电路和补偿控制电路14；所述像素电路的显示周期包括刷新帧和保持帧；所述刷新帧和所述保持帧分别包括先后设置的重置阶段和发光阶段；
所述储能电路12与所述驱动电路的控制端电连接，用于储存电能；
所述补偿控制电路14分别与补偿控制端NG、所述驱动电路11的控制端和所述驱动电路11的第二端电连接，用于在所述补偿控制端NG提供的补偿控制信号的控制下，控制所述驱动电路11的控制端与所述驱动电路11的第二端之间连通；
所述初始化电路包括第二初始化子电路132；所述初始控制端包括第二初始控制端S2，所述初始电压端包括第二初始电压端I2；
所述第二初始化子电路132分别与所述第二初始控制端S2、第二初始电压端I2和所述驱动电路11的第一端电连接，用于在所述第二初始控制端S2提供的第二初始控制信号的控制下，在所述刷新帧和所述保持帧，至少在所 述重置阶段，将所述第二初始电压端I2提供的第二初始电压写入所述驱动电路11的第一端，以控制所述驱动电路11包括的驱动晶体管处于偏压状态；
所述驱动电路11的第二端与所述发光元件E0电连接，用于在所述驱动电路11的控制端的电位的控制下，驱动所述发光元件E0。
在本公开至少一实施例中，所述初始化电路包括第一初始化子电路和第二初始化子电路；所述初始控制端包括第一初始控制端和第二初始控制端，所述初始电压端包括第一初始电压端和第二初始电压端；
所述第一初始化子电路分别与所述第一初始控制端、所述第一初始电压端和所述驱动电路的第二端电连接，用于在所述第一初始控制端提供的第一初始控制信号的控制下，在所述刷新帧和所述保持帧，至少在所述重置阶段，将所述第一初始电压端提供的第一初始电压写入所述驱动电路的第二端；
所述第二初始化子电路分别与所述第二初始控制端、第二初始电压端和所述驱动电路的第一端电连接，用于在所述第二初始控制端提供的第二初始控制信号的控制下，在所述刷新帧和所述保持帧，至少在所述重置阶段，将所述第二初始电压端提供的第二初始电压写入所述驱动电路的第一端。
如图3所示，本公开至少一实施例所述的像素电路可以包括发光元件E0、驱动电路11、储能电路12、初始化电路和补偿控制电路14；所述像素电路的显示周期包括刷新帧和保持帧；所述刷新帧和所述保持帧分别包括先后设置的重置阶段和发光阶段；
所述储能电路12与所述驱动电路的控制端电连接，用于储存电能；
所述补偿控制电路14分别与补偿控制端NG、所述驱动电路11的控制端和所述驱动电路11的第二端电连接，用于在所述补偿控制端NG提供的补偿控制信号的控制下，控制所述驱动电路11的控制端与所述驱动电路11的第二端之间连通；
所述初始化电路包括第一初始化子电路131和第二初始化子电路132；所述初始控制端包括第一初始控制端S1和第二初始控制端S2，所述初始电压端包括第一初始电压端I1和第二初始电压端I2；
所述第一初始化子电路131分别与所述第一初始控制端S1、所述第一初始电压端I1和所述驱动电路的第二端电连接，用于在所述第一初始控制端 S1提供的第一初始控制信号的控制下，在所述刷新帧和所述保持帧，至少在所述重置阶段，将所述第一初始电压端I1提供的第一初始电压写入所述驱动电路11的第二端；
所述第二初始化子电路分别与所述第二初始控制端S2、第二初始电压端I2和所述驱动电路11的第一端电连接，用于在所述第二初始控制端S2提供的第二初始控制信号的控制下，在所述刷新帧和所述保持帧，至少在所述重置阶段，将所述第二初始电压端I2提供的第二初始电压写入所述驱动电路11的第一端；
所述驱动电路11的第二端与所述发光元件E0电连接，用于在所述驱动电路11的控制端的电位的控制下，驱动所述发光元件E0。
可选的，所述第一初始化子电路包括第一晶体管；
所述第一晶体管的控制极与所述第一初始控制端电连接，所述第一晶体管的第一极与所述第一初始电压端电连接，所述第一晶体管的第二极与所述驱动电路的第二端电连接。
可选的，所述第二初始化子电路包括第二晶体管；
所述第二晶体管的控制极与所述第二初始控制端电连接，所述第二晶体管的第一极与所述第二初始电压端电连接，所述第二晶体管的第二极与所述驱动电路的第一端电连接。
可选的，所述第一初始化子电路包括第一晶体管，所述第二初始化子电路包括第二晶体管；
所述第一晶体管的控制极与所述第一初始控制端电连接，所述第一晶体管的第一极与所述第一初始电压端电连接，所述第一晶体管的第二极与所述驱动电路的第二端电连接；
所述第二晶体管的控制极与所述第二初始控制端电连接，所述第二晶体管的第一极与所述第二初始电压端电连接，所述第二晶体管的第二极与所述驱动电路的第一端电连接。
本公开至少一实施例所述的像素电路还包括第一发光控制电路、第二发光控制电路和数据写入电路；
所述第一发光控制电路分别与第一发光控制端、电源电压端和所述驱动 电路的第一端电连接，用于在所述第一发光控制端提供的第一发光控制信号的控制下，控制所述电源电压端与所述驱动电路的第一端之间连通；
所述第二发光控制电路分别与第二发光控制端、所述驱动电路的第二端和所述发光元件的第一极电连接，用于在所述第二发光控制端提供的第二发光控制信号的控制下，控制所述驱动电路的第二端与所述发光元件的第一极之间连通；所述发光元件的第二极与第一电压端电连接；
所述数据写入电路分别与写入控制端、数据线和所述驱动电路的第一端电连接，用于在所述写入控制端提供的写入控制信号的控制下，控制所述数据线与所述驱动电路的第一端之间连通。
在具体实施时，所述第一发光控制电路和所述第二发光控制电路用于进行发光控制，所述数据写入电路用于进行数据电压写入。
在本公开至少一实施例中，所述像素电路还包括复位电路；
所述复位电路分别与复位控制端、复位电压端和所述发光元件的第一极电连接，用于在所述复位控制端提供的复位控制信号的控制下，控制将所述复位电压端提供的复位电压写入所述发光元件的第一极。
在具体实施时，所述复位电路在复位控制信号的控制下，将复位电压写入所述发光元件的第一极，以控制所述发光元件不发光，并清除所述发光元件的第一极残留的电荷。
如图4所示，在图1所示的像素电路的至少一实施例的基础上，本公开至少一实施例所述的像素电路还包括第一发光控制电路41、第二发光控制电路42、数据写入电路43和复位电路44；
所述第一发光控制电路41分别与第一发光控制端E1、电源电压端VDD和所述驱动电路11的第一端电连接，用于在所述第一发光控制端E1提供的第一发光控制信号的控制下，控制所述电源电压端VDD与所述驱动电路11的第一端之间连通；
所述第二发光控制电路42分别与第二发光控制端E2、所述驱动电路11的第二端和所述发光元件E0的第一极电连接，用于在所述第二发光控制端E2提供的第二发光控制信号的控制下，控制所述驱动电路11的第二端与所述发光元件E0的第一极之间连通；所述发光元件E0的第二极与第一电压端 V1电连接；
所述数据写入电路43分别与写入控制端S0、数据线D1和所述驱动电路11的第一端电连接，用于在所述写入控制端S0提供的写入控制信号的控制下，控制所述数据线D1与所述驱动电路11的第一端之间连通；
所述复位电路44分别与复位控制端S3、复位电压端I3和所述发光元件E0的第一极电连接，用于在所述复位控制端S3提供的复位控制信号的控制下，控制将所述复位电压端I3提供的复位电压写入所述发光元件E0的第一极。
本公开如图4所示的像素电路的至少一实施例在工作时，所述刷新帧包括先后设置的第一初始化阶段、第一复位阶段、第一充电阶段、第一重置阶段和第一发光阶段；
在所述第一初始化阶段，所述第一初始化子电路131在第一初始控制信号的控制下，将第一初始电压端I1提供的第一初始电压Vi1写入驱动电路11的第二端；补偿控制电路14在补偿控制信号的控制下，控制所述驱动电路11的控制端与所述驱动电路11的第二端之间连通；
在所述第一复位阶段，所述复位电路44在复位控制信号的控制下，将复位电压端I3提供的复位电压Vi3写入发光元件E0的第一极，第二发光控制电路42在第二发光控制信号的控制下，控制所述驱动电路11的第二端与所述发光元件E0的第一极之间连通；补偿控制电路14在补偿控制信号的控制下，控制所述驱动电路11的控制端与所述驱动电路11的第二端之间连通；
在所述第一充电阶段，所述数据写入电路43将数据线D1提供的数据电压写入所述驱动电路11的第一端，补偿控制电路14在补偿控制信号的控制下，控制所述驱动电路11的控制端与所述驱动电路11的第二端之间连通；
在所述第一重置阶段，所述第一初始化子电路131在第一初始控制信号的控制下，将第一初始电压端I1提供的第一初始电压Vi1写入驱动电路11的第二端；所述驱动电路11在其控制端的电位的控制下，控制所述驱动电路11的第一端与所述驱动电路11的第二端之间连通，以控制所述驱动电路11包括的驱动晶体管处于偏压状态；
在第一发光阶段，所述第一发光控制电路41在第一发光控制信号的控制 下，控制电源电压端VDD与所述驱动电路11的第一端之间连通；所述第二发光控制电路42在第二发光控制信号的控制下，控制所述驱动电路11的第二端与所述发光元件E0的第一极之间连通；所述驱动电路11在其控制端的电位的控制下，驱动所述发光元件E0发光。
本公开如图4所示的像素电路的至少一实施例在工作时，所述保持帧包括先后设置的第二初始化阶段、第二复位阶段、第二重置阶段和第二发光阶段；
在所述保持帧，补偿控制电路14在补偿控制信号的控制下，控制所述驱动电路11的控制端与所述驱动电路11的第二端之间断开；
在所述第二初始化阶段，所述第一初始化子电路131在第一初始控制信号的控制下，将第一初始电压端I1提供的第一初始电压Vi1写入驱动电路11的第二端；
在所述第二复位阶段，所述复位电路44在复位控制信号的控制下，将复位电压端I3提供的复位电压Vi3写入发光元件E0的第一极，第二发光控制电路42在第二发光控制信号的控制下，控制所述驱动电路11的第二端与所述发光元件E0的第一极之间连通；
在所述第二重置阶段，所述第一初始化子电路131在第一初始控制信号的控制下，将第一初始电压端I1提供的第一初始电压Vi1写入驱动电路11的第二端；所述驱动电路11在其控制端的电位的控制下，控制所述驱动电路11的第一端与所述驱动电路11的第二端之间连通，以控制所述驱动电路11包括的驱动晶体管处于偏压状态；
在第二发光阶段，所述第一发光控制电路41在第一发光控制信号的控制下，控制电源电压端VDD与所述驱动电路11的第一端之间连通；所述第二发光控制电路42在第二发光控制信号的控制下，控制所述驱动电路11的第二端与所述发光元件E0的第一极之间连通；所述驱动电路11在其控制端的电位的控制下，驱动所述发光元件E0发光。
本公开如图4所示的像素电路的至少一实施例在工作时，所述保持帧还可以包括设置于第二复位阶段和第二重置阶段之间的保持置位阶段；
在所述保持置位阶段，所述数据写入电路43将数据线D1提供的电压信 号写入所述驱动电路11的第一端。
如图5所示，在图2所示的像素电路的至少一实施例的基础上，本公开至少一实施例所述的像素电路还包括第一发光控制电路41、第二发光控制电路42、数据写入电路43和复位电路44；
所述第一发光控制电路41分别与第一发光控制端E1、电源电压端VDD和所述驱动电路11的第一端电连接，用于在所述第一发光控制端E1提供的第一发光控制信号的控制下，控制所述电源电压端VDD与所述驱动电路11的第一端之间连通；
所述第二发光控制电路42分别与第二发光控制端E2、所述驱动电路11的第二端和所述发光元件E0的第一极电连接，用于在所述第二发光控制端E2提供的第二发光控制信号的控制下，控制所述驱动电路11的第二端与所述发光元件E0的第一极之间连通；所述发光元件E0的第二极与第一电压端V1电连接；
所述数据写入电路43分别与写入控制端S0、数据线D1和所述驱动电路11的第一端电连接，用于在所述写入控制端S0提供的写入控制信号的控制下，控制所述数据线D1与所述驱动电路11的第一端之间连通；
所述复位电路44分别与复位控制端S3、复位电压端I3和所述发光元件E0的第一极电连接，用于在所述复位控制端S3提供的复位控制信号的控制下，控制将所述复位电压端I3提供的复位电压写入所述发光元件E0的第一极。
本公开如图5所示的像素电路的至少一实施例在工作时，所述刷新帧包括先后设置的第一初始化阶段、第一复位阶段、第一充电阶段、第一重置阶段和第一发光阶段；
在所述第一初始化阶段，所述第二初始化子电路132在第二初始控制信号的控制下，将第二初始电压端I2提供的第二初始电压Vi2写入驱动电路11的第一端；补偿控制电路14在补偿控制信号的控制下，控制所述驱动电路11的控制端与所述驱动电路11的第二端之间连通；
在所述第一复位阶段，所述复位电路44在复位控制信号的控制下，将复位电压端I3提供的复位电压Vi3写入发光元件E0的第一极；第二发光控制 电路42在第二发光控制信号的控制下，控制所述驱动电路11的第二端与所述发光元件E0的第一极之间连通；补偿控制电路14在补偿控制信号的控制下，控制所述驱动电路11的控制端与所述驱动电路11的第二端之间连通；
在所述第一充电阶段，所述数据写入电路43将数据线D1提供的数据电压Vdata写入所述驱动电路11的第一端，补偿控制电路14在补偿控制信号的控制下，控制所述驱动电路11的控制端与所述驱动电路11的第二端之间连通；
在所述第一重置阶段，所述第二初始化子电路132在第二初始控制信号的控制下，将第二初始电压端i2提供的第二初始电压Vi2写入驱动电路11的第一端；所述驱动电路11在其控制端的电位的控制下，控制所述驱动电路11的第一端与所述驱动电路11的第二端之间连通，以控制所述驱动电路11包括的驱动晶体管处于偏压状态；
在第一发光阶段，所述第一发光控制电路41在第一发光控制信号的控制下，控制电源电压端VDD与所述驱动电路11的第一端之间连通；所述第二发光控制电路42在第二发光控制信号的控制下，控制所述驱动电路11的第二端与所述发光元件E0的第一极之间连通；所述驱动电路11在其控制端的电位的控制下，驱动所述发光元件E0发光。
本公开如图5所示的像素电路的至少一实施例在工作时，所述保持帧包括先后设置的第二初始化阶段、第二复位阶段、第二重置阶段和第二发光阶段；
在所述保持帧，补偿控制电路14在补偿控制信号的控制下，控制所述驱动电路11的控制端与所述驱动电路11的第二端之间断开；
在所述第二初始化阶段，所述第二初始化子电路132在第二初始控制信号的控制下，将第二初始电压端I2提供的第二初始电压Vi2写入驱动电路11的第一端；
在所述第二复位阶段，所述复位电路44在复位控制信号的控制下，将复位电压端I3提供的复位电压Vi3写入发光元件E0的第一极；第二发光控制电路42在第二发光控制信号的控制下，控制所述驱动电路11的第二端与所述发光元件E0的第一极之间连通；
在所述第二重置阶段，所述第二初始化子电路132在第二初始控制信号的控制下，将第二初始电压端I2提供的第二初始电压Vi2写入驱动电路11的第一端；所述驱动电路11在其控制端的电位的控制下，控制所述驱动电路11的第一端与所述驱动电路11的第二端之间连通，以控制所述驱动电路11包括的驱动晶体管处于偏压状态；
在第二发光阶段，所述第一发光控制电路41在第一发光控制信号的控制下，控制电源电压端VDD与所述驱动电路11的第一端之间连通；所述第二发光控制电路42在第二发光控制信号的控制下，控制所述驱动电路11的第二端与所述发光元件E0的第一极之间连通；所述驱动电路11在其控制端的电位的控制下，驱动所述发光元件E0发光。
本公开如图5所示的像素电路的至少一实施例在工作时，所述保持帧还包括设置于第二复位阶段和第二重置阶段之间的保持置位阶段；
在所述保持置位阶段，所述数据写入电路43将数据线D1提供的电压信号写入所述驱动电路11的第一端。
如图6所示，在图3所示的像素电路的至少一实施例的基础上，本公开至少一实施例所述的像素电路还包括第一发光控制电路41、第二发光控制电路42和数据写入电路43；
所述第一发光控制电路41分别与第一发光控制端E1、电源电压端VDD和所述驱动电路11的第一端电连接，用于在所述第一发光控制端E1提供的第一发光控制信号的控制下，控制所述电源电压端VDD与所述驱动电路11的第一端之间连通；
所述第二发光控制电路42分别与第二发光控制端E2、所述驱动电路11的第二端和所述发光元件E0的第一极电连接，用于在所述第二发光控制端E2提供的第二发光控制信号的控制下，控制所述驱动电路11的第二端与所述发光元件E0的第一极之间连通；所述发光元件E0的第二极与第一电压端V1电连接；
所述数据写入电路43分别与写入控制端S0、数据线D1和所述驱动电路11的第一端电连接，用于在所述写入控制端S0提供的写入控制信号的控制下，控制所述数据线D1与所述驱动电路11的第一端之间连通。
本公开如图6所示的像素电路的至少一实施例在工作时，所述刷新帧包括先后设置的第一复位阶段、第一充电阶段、第一重置阶段和第一发光阶段；
在所述第一复位阶段，所述第一初始化子电路131在第一初始控制信号的控制下，将第一初始电压端I1提供的第一初始电压Vi1写入所述驱动电路11的第二端，补偿控制电路14在补偿控制信号的控制下，控制所述驱动电路11的控制端与所述驱动电路11的第二端之间连通；
在所述第一充电阶段，所述数据写入电路43将数据线D1提供的数据电压Vdata写入所述驱动电路11的第一端，补偿控制电路14在补偿控制信号的控制下，控制所述驱动电路11的控制端与所述驱动电路11的第二端之间连通；
在所述第一重置阶段，所述第二初始化子电路132在第二初始控制信号的控制下，将第二初始电压端I2提供的第二初始电压Vi2写入所述驱动电路11的第一端，所述驱动电路11在其控制端的电位的控制下，控制所述驱动电路11的第一端与所述驱动电路11的第二端之间连通，以控制所述驱动电路11包括的驱动晶体管处于偏压状态；
在第一发光阶段，所述第一发光控制电路41在第一发光控制信号的控制下，控制电源电压端VDD与所述驱动电路11的第一端之间连通；所述第二发光控制电路42在第二发光控制信号的控制下，控制所述驱动电路11的第二端与所述发光元件E0的第一极之间连通；所述驱动电路11在其控制端的电位的控制下，驱动所述发光元件E0发光。
本公开如图6所示的像素电路的至少一实施例在工作时，所述保持帧包括先后设置的第二初始化阶段、第二复位阶段、第二重置阶段和第二发光阶段；
在所述保持帧，补偿控制电路14在补偿控制信号的控制下，控制所述驱动电路11的控制端与所述驱动电路11的第二端之间断开；
在所述第二复位阶段，所述第一初始化子电路131在第一初始控制信号的控制下，将第一初始电压端I1提供的第一初始电压Vi1写入所述驱动电路11的第二端；
在所述第二重置阶段，所述第二初始化子电路132在第二初始控制信号 的控制下，将第二初始电压端I2提供的第二初始电压Vi2写入所述驱动电路11的第一端，所述驱动电路11在其控制端的电位的控制下，控制所述驱动电路11的第一端与所述驱动电路11的第二端之间连通，以控制所述驱动电路11包括的驱动晶体管处于偏压状态；
在第二发光阶段，所述第一发光控制电路41在第一发光控制信号的控制下，控制电源电压端VDD与所述驱动电路11的第一端之间连通；所述第二发光控制电路42在第二发光控制信号的控制下，控制所述驱动电路11的第二端与所述发光元件E0的第一极之间连通；所述驱动电路11在其控制端的电位的控制下，驱动所述发光元件E0发光。
本公开如图6所示的像素电路的至少一实施例在工作时，所述保持帧还包括设置于第二复位阶段和第二重置阶段之间的保持置位阶段；
在所述保持置位阶段，所述数据写入电路43将数据线D1提供的电压信号写入所述驱动电路11的第一端。
如图7所示，在图6所示的像素电路的至少一实施例的基础上，本公开至少一实施例所述的像素电路还包括复位电路44；
所述复位电路44分别与复位控制端S3、复位电压端I3和所述发光元件E0的第一极电连接，用于在所述复位控制端S3提供的复位控制信号的控制下，控制将所述复位电压端I3提供的复位电压写入所述发光元件E0的第一极。
本公开如图7所示的像素电路的至少一实施例在工作时，
在所述第一重置阶段，所述复位电路44在复位控制信号的控制下，将复位电压端I3提供的复位电压Vi3写入发光元件E0的第一极；
在所述第二重置阶段，所述复位电路44在复位控制信号的控制下，将复位电压端I3提供的复位电压Vi3写入发光元件E0的第一极。
可选的，所述补偿控制电路包括第三晶体管，所述第一发光控制电路包括第四晶体管，所述第二发光控制电路包括第五晶体管，所述数据写入电路包括第六晶体管，所述驱动电路包括驱动晶体管；
所述第三晶体管的控制极与所述补偿控制端电连接，所述第三晶体管的第一极与所述驱动电路的控制端电连接，所述第三晶体管的第二极与所述驱 动电路的第二端电连接；
所述第四晶体管的控制极与所述第一发光控制端电连接，所述第四晶体管的第一极与所述电源电压端电连接，所述第四晶体管的第二极与所述驱动电路的第一端电连接；
所述第五晶体管的控制极与所述第二发光控制端电连接，所述第五晶体管的第一极与所述驱动电路的第二端电连接，所述第五晶体管的第二极与所述发光元件的第一极电连接；
所述第六晶体管的控制极与写入控制端电连接，所述第六晶体管的第一极与所述数据线电连接，所述第六晶体管的第二极与所述驱动电路的第一端电连接；
所述驱动晶体管的控制极与所述驱动电路的控制端电连接，所述驱动晶体管的第一极与所述驱动电路的第一端电连接，所述驱动晶体管的第二极与所述驱动电路的第二端电连接。
在本公开至少一实施例中，所述第三晶体管为氧化物薄膜晶体管。
可选的，所述复位电路包括第七晶体管；
所述第七晶体管的控制极分别与复位控制端电连接，所述第七晶体管的第一极与所述复位电压端电连接，所述第七晶体管的第二极与所述发光元件的第一极电连接。
在本公开至少一实施例中，所述第七晶体管为氧化物薄膜晶体管。
如图8所示，在图4所示的像素电路的至少一实施例的基础上，所述第一初始化子电路131包括第一晶体管T1；所述驱动电路11包括驱动晶体管T0；所述发光元件为有机发光二极管O1；所述储能电路12包括存储电容C1；
所述第一晶体管T1的栅极与所述第一初始控制端S1电连接，所述第一晶体管T1的源极与所述第一初始电压端I1电连接，所述第一晶体管T1的漏极与所述驱动晶体管T0的漏极电连接；
所述补偿控制电路14包括第三晶体管T3，所述第一发光控制电路41包括第四晶体管T4，所述第二发光控制电路42包括第五晶体管T5，所述数据写入电路43包括第六晶体管T6；
所述第三晶体管T3的栅极与所述补偿控制端NG电连接，所述第三晶体 管T3的源极与所述驱动晶体管T0的栅极电连接，所述第三晶体管T3的漏极与所述驱动晶体管T0的漏极电连接；
所述第四晶体管T4的栅极与所述第一发光控制端E1电连接，所述第四晶体管T4的源极与所述电源电压端VDD电连接，所述第四晶体管T4的漏极与所述驱动晶体管T0的源极电连接；
所述第五晶体管T5的栅极与所述第二发光控制端E2电连接，所述第五晶体管T5的源极与所述驱动晶体管T0的漏极电连接，所述第五晶体管T5的漏极与所述有机发光二极管O1的阳极电连接；
所述第六晶体管T6的栅极与写入控制端S0电连接，所述第六晶体管T6的源极与所述数据线D1电连接，所述第六晶体管T6的漏极与所述驱动晶体管T0的源极电连接；
所述复位电路包括第七晶体管T7；
所述第七晶体管T7的栅极分别与复位控制端S3电连接，所述第七晶体管T7的源极与所述复位电压端I3电连接，所述第七晶体管T7的漏极与所述有机发光二极管O1的阳极电连接；
所述有机发光二极管O1的阴极与低电压端VSS电连接；
所述存储电容C1的第一端与所述驱动晶体管T0的栅极电连接，所述存储电容C1的第二端与电源电压端VDD电连接。
在图8所示的像素电路的至少一实施例中，T3和T7为氧化物薄膜晶体管，T1、T4、T5、T6和T0为LTPS(低温多晶硅)薄膜晶体管，T3和T7为n型晶体管，T1、T4、T5、T6和T0为p型晶体管，但不以此为限。
如图9所示，本公开如图8所示的像素电路的至少一实施例在工作时，所述刷新帧包括先后设置的第一初始化阶段S11、第一复位阶段S12、第一充电阶段S13、第一重置阶段S14和第一发光阶段S15；
在第一初始化阶段S11，E2提供高电压信号，E1提供高电压信号，S3提供低电压信号，NG提供高电压信号，S1提供低电压信号，S0提供高电压信号，I1提供第一初始电压Vi1，如图10A所示，T1打开，T3打开，以将第一初始电压Vi1写入T0的漏极与T0的栅极，以对T0的漏极电压和T0的栅极电压进行初始化；所述第一初始电压Vi1为正电压，例如，Vi1可以为5V电 压信号，但不以此为限；
在第一复位阶段S12，E2提供低电压信号，E1提供高电压信号，S3提供高电压信号，NG提供高电压信号，S1提供高电压信号，S0提供高电压信号，如图10B所示，T7打开，I3提供复位电压Vi3，T5打开，T3打开，T0打开，以将所述复位电压Vi3写入O1的阳极、T0的漏极、T0的栅极和T0的源极，以控制O1不发光，并清除O1的阳极残留的电荷，并对T0的栅极电压、T0的源极电压和T0的漏极电压进行复位，并使得在所述第一充电阶段S13开始时，T0能够导通；所述复位电压Vi3可以为负电压，例如，Vi3可以为-3V电压信号，但不以此为限；
在第一充电阶段S13，E2提供高电压信号，E1提供高电压信号，S3提供低电压信号，NG提供高电压信号，S1提供高电压信号，S0提供低电压信号，如图10C所示，T6打开，D1提供数据电压Vdata；T3打开；在所述第一充电阶段S13开始时，T0导通，所述数据电压Vdata通过T6、T0和T3为C1充电，以提升T0的栅极电压，直至T0关断，此时T0的栅极电压为Vdata+Vth，Vth为T0的阈值电压；
在第一重置阶段S14，E2提供高电压信号，E1提供高电压信号，S3提供低电压信号，NG提供低电压信号，S1提供低电压信号，S0提供高电压信号，I1提供第一初始电压Vi1，如图10D所示，T1打开，T0打开，以将T0的漏极电压和T0的源极电压重置为Vi1，以使得T0处于偏压状态，改善磁滞现象；
在第一发光阶段S15，E2提供低电压信号，E1提供低电压信号，S3提供低电压信号，NG提供低电压信号，S1提供高电压信号，S0提供高电压信号，如图10E所示，T4和T5打开，T0驱动O1发光。
本公开如图8所示的像素电路的至少一实施例在工作时，所述第一初始电压Vi1的电压值可以大于等于4V而小于等于7V，所述复位电压Vi3的电压值可以大于等于-4V而小于等于-2V，但不以此为限。
如图11所示，本公开如图8所示的像素电路的至少一实施例在工作时，所述保持帧包括先后设置的第二初始化阶段S21、第二复位阶段S22、保持置位阶段S23、第二重置阶段S24和第二发光阶段S25；
在所述保持帧，NG提供低电压信号，T3关断，以控制T0的栅极与T0的漏极之间断开，以维持T0的栅极电压；
在所述第二初始化阶段S21，E2提供高电压信号，E1提供高电压信号，S3提供低电压信号，S1提供低电压信号，S0提供高电压信号，I1提供第一初始电压Vi1，T1打开，以将第一初始电压Vi1写入T0的漏极，以对T0的漏极电压进行初始化；所述第一初始电压Vi1为正电压，例如，Vi1可以为5V电压信号，但不以此为限；
在第二复位阶段S22，E2提供低电压信号，E1提供高电压信号，S3提供高电压信号，S1提供高电压信号，S0提供高电压信号，T7打开，I3提供复位电压Vi3，T5打开，以将所述复位电压Vi3写入O1的阳极和T0的漏极，以控制O1不发光，并清除O1的阳极残留的电荷，并对T0的漏极电压进行复位；所述复位电压Vi3可以为负电压，例如，Vi3可以为-3V电压信号，但不以此为限；
在保持置位阶段S23，E2提供高电压信号，E1提供高电压信号，S3提供低电压信号，S1提供高电压信号，S0提供低电压信号，T6打开，D1提供电压信号至T0的源极；
在所述保持置位阶段S23，D1提供的电压信号可以为正电压，以对T0的源极电压进行置位，从而向驱动晶体管T0提供偏置电压，使得T0处于偏压状态，以改善磁滞现象；
在第二重置阶段S24，E2提供高电压信号，E1提供高电压信号，S3提供低电压信号，S1提供低电压信号，S0提供高电压信号，I1提供第一初始电压Vi1，T1打开，T0打开，以将T0的漏极电压和T0的源极电压重置为Vi1，以使得T0处于偏压状态，改善磁滞现象；
在第二发光阶段S25，E2提供低电压信号，E1提供低电压信号，S3提供低电压信号，S1提供高电压信号，S0提供高电压信号，T4和T5打开，T0驱动O1发光。
在具体实施时，在所述保持重置阶段，所述数据线D1提供的电压信号可以为数据电压Vdata，所述数据电压Vdata为在第一充电阶段，所述数据线D1提供的数据电压，所述数据电压Vdata的电压值范围例如可以为大于等于 1V而小于等于6.5V；或者，
在保持重置阶段，所述数据线D1提供的电压信号可以为重置电压信号，所述重置电压信号的电压值范围可以为大于等于4.6V而小于等于7V；
但不以此为限。
本公开如图8所示的像素电路的至少一实施例在工作时，在低频显示时，显示周期包括刷新帧和保持帧，在保持帧中的第二重置阶段，本公开实施例对所述驱动电路包括的驱动晶体管进行偏置，使得在保持帧中的第二重置阶段，驱动电路中的驱动晶体管的源极的电位和驱动晶体管的漏极的电位与刷新帧一致，能够改善闪烁现象。
如图12所示，在图5所示的像素电路的至少一实施例的基础上，所述第二初始化子电路132包括第二晶体管T2；所述驱动电路11包括驱动晶体管T0；所述发光元件为有机发光二极管O1；所述储能电路12包括存储电容C1；
所述第二晶体管T2的栅极与所述第二初始控制端S2电连接，所述第二晶体管T2的源极与所述第二初始电压端I2电连接，所述第二晶体管T2的漏极与所述驱动晶体管T0的源极电连接；
所述补偿控制电路14包括第三晶体管T3，所述第一发光控制电路41包括第四晶体管T4，所述第二发光控制电路42包括第五晶体管T5，所述数据写入电路43包括第六晶体管T6；
所述第三晶体管T3的栅极与所述补偿控制端NG电连接，所述第三晶体管T3的源极与所述驱动晶体管T0的栅极电连接，所述第三晶体管T3的漏极与所述驱动晶体管T0的漏极电连接；
所述第四晶体管T4的栅极与所述第一发光控制端E1电连接，所述第四晶体管T4的源极与所述电源电压端VDD电连接，所述第四晶体管T4的漏极与所述驱动晶体管T0的源极电连接；
所述第五晶体管T5的栅极与所述第二发光控制端E2电连接，所述第五晶体管T5的源极与所述驱动晶体管T0的漏极电连接，所述第五晶体管T5的漏极与所述有机发光二极管O1的阳极电连接；
所述第六晶体管T6的栅极与写入控制端S0电连接，所述第六晶体管T6的源极与所述数据线D1电连接，所述第六晶体管T6的漏极与所述驱动晶体 管T0的源极电连接；
所述复位电路44包括第七晶体管T7；
所述第七晶体管T7的栅极分别与复位控制端S3电连接，所述第七晶体管T7的源极与所述复位电压端I3电连接，所述第七晶体管T7的漏极与所述有机发光二极管O1的阳极电连接；
所述有机发光二极管O1的阴极与低电压端VSS电连接；
所述存储电容C1的第一端与所述驱动晶体管T0的栅极电连接，所述存储电容C1的第二端与电源电压端VDD电连接。
在图12所示的像素电路的至少一实施例中，T3为氧化物薄膜晶体管，T2、T4、T5、T6、T7和T0为LTPS(低温多晶硅)薄膜晶体管，T3为n型晶体管，T2、T4、T5、T6、T7和T0为p型晶体管，但不以此为限。
如图13所示，本公开图12所示的像素电路的至少一实施例在工作时，所述刷新帧包括先后设置的第一初始化阶段S11、第一复位阶段S12、第一充电阶段S13、第一重置阶段S14和第一发光阶段S15；
在第一初始化阶段S11，E2提供高电压信号，E1提供高电压信号，S2提供低电压信号，NG提供高电压信号，S3提供低电压信号，S0提供高电压信号，I2提供第二初始电压Vi2，I3提供复位电压Vi3，Vi2为正电压，Vi3为负电压；例如，Vi2可以为5V电压信号，Vi3可以为-3V电压信号；如图14A所示，T7打开，以将Vi3写入O1的阳极，使得O1不发光，并清除O1的阳极残留的电荷；T2打开，T0打开，T3打开，以对T0的源极电压、T0的漏极电压和T0的栅极电压进行初始化；
在第一复位阶段S12，E2提供低电压信号，E1提供高电压信号，S2提供高电压信号，NG提供高电压信号，S3提供低电压信号，S0提供高电压信号，I3提供复位电压Vi3；如图14B所示，T7打开，以将Vi3写入O1的阳极，使得O1不发光，并清除O1的阳极残留的电荷；T3打开，T0打开，以将Vi3写入T0的栅极、T0的漏极和T0的源极，使得在第一充电阶段S13开始时，T0能够导通；
在第一充电阶段S13，E2提供高电压信号，E1提供高电压信号，S2提供高电压信号，NG提供高电压信号，S3提供高电压信号，S0提供低电压信号， D1提供数据电压Vdata，如图14C所示，T6打开，T3打开；
在所述第一充电阶段S13开始时，T0导通，Vdata通过T6、T0和T3为C1充电，直至T0关断，此时T0的栅极电压为Vdata+Vth；
在第一重置阶段S14，E2提供高电压信号，E1提供高电压信号，S2提供低电压信号，NG提供低电压信号，S3提供低电压信号，S0提供高电压信号，I2提供第二初始电压Vi2，如图14D所示，T2打开，T0打开，T7打开，以将Vi2写入T0的源极和T0的漏极，以将T0的漏极电压和T0的源极电压重置为Vi2，以使得T0处于偏压状态，改善磁滞现象；并将Vi3写入O1的阳极，控制O1不发光，并清除O1的阳极残留的电荷；
在第一发光阶段S15，E2提供低电压信号，E1提供低电压信号，S2提供高电压信号，NG提供低电压信号，S3提供高电压信号，S0提供高电压信号，如图14E所示，T4和T5打开，T0驱动O1发光。
如图15所示，本公开图12所示的像素电路的至少一实施例在工作时，所述保持帧包括先后设置的第二初始化阶段S21、第二复位阶段S22、保持置位阶段S23、第二重置阶段S24和第二发光阶段S25；
在所述保持帧，NG提供低电压信号，T3关断，以控制T0的栅极与T0的漏极之间断开，以维持T0的栅极电压；
在第二初始化阶段S21，E2提供高电压信号，E1提供高电压信号，S2提供低电压信号，S3提供低电压信号，S0提供高电压信号，I2提供第二初始电压Vi2，I3提供复位电压Vi3，Vi2为正电压，Vi3为负电压；例如，Vi2可以为5V电压信号，Vi3可以为-3V电压信号；T7打开，以将Vi3写入O1的阳极，使得O1不发光，并清除O1的阳极残留的电荷；T2打开，T0打开，以对T0的源极电压和T0的漏极电压进行初始化；
在第二复位阶段S22，E2提供低电压信号，E1提供高电压信号，S2提供高电压信号，S3提供低电压信号，S0提供高电压信号，I3提供复位电压Vi3；T7打开，以将Vi3写入O1的阳极，使得O1不发光，并清除O1的阳极残留的电荷；T0打开，以将Vi3写入T0的漏极和T0的源极；
在保持置位阶段S23，E2提供高电压信号，E1提供高电压信号，S2提供高电压信号，S3提供高电压信号，S0提供低电压信号，D1提供电压信号，T6 打开，D1提供电压信号至T0的源极；
在所述保持置位阶段S23，D1提供的电压信号可以为正电压，以对T0的源极电压进行置位，从而向驱动晶体管T0提供偏置电压，使得T0处于偏压状态，以改善磁滞现象；
在第二重置阶段S24，E2提供高电压信号，E1提供高电压信号，S2提供低电压信号，S3提供低电压信号，S0提供高电压信号，I2提供第二初始电压Vi2，T2打开，T0打开，T7打开，以将Vi2写入T0的源极和T0的漏极，以将T0的漏极电压和T0的源极电压重置为Vi2，以使得T0处于偏压状态，改善磁滞现象；并将Vi3写入O1的阳极，控制O1不发光，并清除O1的阳极残留的电荷；
在第二发光阶段S25，E2提供低电压信号，E1提供低电压信号，S2提供高电压信号，S3提供高电压信号，S0提供高电压信号，T4和T5打开，T0驱动O1发光。
在具体实施时，在所述保持重置阶段，所述数据线D1提供的电压信号可以为数据电压Vdata，所述数据电压Vdata为在第一充电阶段，所述数据线D1提供的数据电压，所述数据电压Vdata的电压值范围例如可以为大于等于1V而小于等于6.5V；或者，
在保持重置阶段，所述数据线D1提供的电压信号可以为重置电压信号，所述重置电压信号的电压值范围可以为大于等于4.6V而小于等于7V；
但不以此为限。
图16是本公开图12所示的像素电路的至少一实施例在保持帧的第二工作时序图。
图16与图15的区别在于：在保持帧，S0提供高电压信号，T6关断，停止将D1提供的电压信号写入T0的源极。
本公开如图12所示的像素电路的至少一实施例在工作时，所述第二初始电压Vi2的电压值可以大于等于4V而小于等于7V，所述复位电压Vi3的电压值可以大于等于-4V而小于等于-2V，但不以此为限。
本公开如图12所示的像素电路的至少一实施例在工作时，在低频显示时，显示周期包括刷新帧和保持帧，在保持帧中的第二重置阶段，本公开实施例 对所述驱动电路包括的驱动晶体管进行偏置，使得在保持帧中的第二重置阶段，驱动电路中的驱动晶体管的源极的电位和驱动晶体管的漏极的电位与刷新帧一致，能够改善闪烁现象。
如图17所示，在图6所示的像素电路的至少一实施例的基础上，所述第一初始化子电路131包括第一晶体管T1；所述第二初始化子电路132包括第二晶体管T2；所述驱动电路11包括驱动晶体管T0；所述发光元件为有机发光二极管O1；所述储能电路12包括存储电容C1；
所述第一晶体管T1的栅极与所述第一初始控制端S1电连接，所述第一晶体管T1的源极与所述第一初始电压端I1电连接，所述第一晶体管T1的漏极与所述驱动晶体管T0的漏极电连接；
所述第二晶体管T2的栅极与所述第二初始控制端S2电连接，所述第二晶体管T2的源极与所述第二初始电压端I2电连接，所述第二晶体管T2的漏极与所述驱动晶体管T0的源极电连接；
所述补偿控制电路14包括第三晶体管T3，所述第一发光控制电路41包括第四晶体管T4，所述第二发光控制电路42包括第五晶体管T5，所述数据写入电路43包括第六晶体管T6；
所述第三晶体管T3的栅极与所述补偿控制端NG电连接，所述第三晶体管T3的源极与所述驱动晶体管T0的栅极电连接，所述第三晶体管T3的漏极与所述驱动晶体管T0的漏极电连接；
所述第四晶体管T4的栅极与所述第一发光控制端E1电连接，所述第四晶体管T4的源极与所述电源电压端VDD电连接，所述第四晶体管T4的漏极与所述驱动晶体管T0的源极电连接；
所述第五晶体管T5的栅极与所述第二发光控制端E2电连接，所述第五晶体管T5的源极与所述驱动晶体管T0的漏极电连接，所述第五晶体管T5的漏极与所述有机发光二极管O1的阳极电连接；
所述第六晶体管T6的栅极与写入控制端S0电连接，所述第六晶体管T6的源极与所述数据线D1电连接，所述第六晶体管T6的漏极与所述驱动晶体管T0的源极电连接；
所述有机发光二极管O1的阴极与低电压端VSS电连接；
所述存储电容C1的第一端与所述驱动晶体管T0的栅极电连接，所述存储电容C1的第二端与电源电压端VDD电连接。
在图17所示的像素电路的至少一实施例的基础上，T3为氧化物薄膜晶体管，T1、T2、T4、T5、T6和T0为LTPS薄膜晶体管，T3为n型晶体管，T1、T2、T4、T5、T6和T0为p型晶体管，但不以此为限。
如图18所示，在图17所示的像素电路的至少一实施例的基础上，所述复位电路44包括第七晶体管T7；
所述第七晶体管T7的栅极分别与复位控制端S3电连接，所述第七晶体管T7的源极与所述复位电压端I3电连接，所述第七晶体管T7的漏极与所述有机发光二极管O1的阳极电连接。
在图18所示的像素电路的至少一实施例的基础上，T7为LTPS薄膜晶体管，T7为p型晶体管，但不以此为限。
如图19所示，本公开图18所示的像素电路的至少一实施例在工作时，所述刷新帧包括先后设置的第一复位阶段S12、第一充电阶段S13、第一重置阶段S14和第一发光阶段S15；
在第一复位阶段S12，S1提供低电压信号，S0提供高电压信号，NG提供高电压信号，S3提供高电压信号，E1和E2提供高电压信号，I1提供第一初始电压Vi1，如图20A所示，T1打开，以将Vi1写入T0的漏极，T3打开，以将Vi1写入T0的栅极，以使得在第一充电阶段S13开始时，T0能够导通；所述第一初始电压Vi1为负电压，例如，Vi1可以为-3V电压信号，但不以此为限；
在第一充电阶段S13，S1提供高电压信号，S0提供低电压信号，NG提供高电压信号，S3提供高电压信号，E1和E2提供高电压信号，D1提供数据电压Vdata，如图20B所示，T6打开，T3打开，以将Vdata写入T0的源极；
在所述第一充电阶段S13开始时，T0导通，Vdata通过T6、T0和T3为C1充电，直至T0关断，此时T0的栅极电压为Vdata+Vth，Vth为T0的阈值电压；
在第一重置阶段S14，S1提供高电压信号，S0提供高电压信号，NG提供低电压信号，S3提供低电压信号，E1和E2提供高电压信号，如图20C所示， T2打开，I2提供第二初始电压Vi2；Vi2为正电压；例如，Vi2可以为5V电压信号；T0打开，以将T0的漏极电压和T0的源极电压重置为Vi2，以使得T0处于偏压状态，改善磁滞现象；T7打开，I3提供复位电压Vi3，以控制O1不发光，并清除O1的阳极残留的电荷；Vi3为负电压，例如，Vi3可以为-3V电压信号；
在第一发光阶段S15，S1提供高电压信号，S0提供高电压信号，NG提供低电压信号，S3提供高电压信号，E1和E2提供低电压信号，如图20D所示，T4和T5打开，T0驱动O1发光。
本公开图18所示的像素电路的至少一实施例在工作时，Vi1可以大于等于-4V而小于等于-2V，Vi2可以大于等于4V而小于等于7V，Vi3可以大于等于-4V而小于等于-2V，但不以此为限。
如图21所示，本公开图18所示的像素电路的至少一实施例在工作时，所述保持帧包括先后设置的第二复位阶段S22、第二重置阶段S24和第二发光阶段S25；
在保持帧，NG提供低电压信号，T3关断，控制T0的栅极与T0的漏极之间断开，以维持T0的栅极电压；
在保持帧，S0提供高电压信号，T6关断，停止向T0的源极写入D1提供的电压信号；
在第二复位阶段S22，S1提供低电压信号，S0提供高电压信号，S3提供高电压信号，E1和E2提供高电压信号，I1提供第一初始电压Vi1，T1打开，以将Vi1写入T0的漏极；
在第二重置阶段S24，S1提供高电压信号，S0提供高电压信号，S3提供低电压信号，E1和E2提供高电压信号，T2打开，I2提供第二初始电压Vi2；Vi2为正电压；例如，Vi2可以为5V电压信号；T0打开，以将T0的漏极电压和T0的源极电压重置为Vi2，以使得T0处于偏压状态，改善磁滞现象；T7打开，I3提供复位电压Vi3，以控制O1不发光，并清除O1的阳极残留的电荷；Vi3为负电压，例如，Vi3可以为-3V电压信号；
在第二发光阶段S25，S1提供高电压信号，S0提供高电压信号，S3提供高电压信号，E1和E2提供低电压信号，T4和T5打开，T0驱动O1发光。
如图22所示，本公开图18所示的像素电路的至少一实施例在工作时，所述保持帧包括先后设置的第二复位阶段S22、保持置位阶段S23、第二重置阶段S24和第二发光阶段S25；
在保持帧，NG提供低电压信号，T3关断，控制T0的栅极与T0的漏极之间断开，以维持T0的栅极电压；
在第二复位阶段S22，S1提供低电压信号，S0提供高电压信号，S3提供高电压信号，E1和E2提供高电压信号，I1提供第一初始电压Vi1，T1打开，以将Vi1写入T0的漏极；
在保持置位阶段S23，S1提供高电压信号，S0提供低电压信号，S3提供高电压信号，E1和E2提供高电压信号，T6打开，D1提供电压信号，将D1提供的电压信号写入T0的源极，
在所述保持置位阶段S23，D1提供的电压信号可以为正电压，以对T0的源极电压进行置位，从而向驱动晶体管T0提供偏置电压，使得T0处于偏压状态，以改善磁滞现象；
在第二重置阶段S24，S1提供高电压信号，S0提供高电压信号，S3提供低电压信号，E1和E2提供高电压信号，T2打开，I2提供第二初始电压Vi2；Vi2为正电压；例如，Vi2可以为5V电压信号；T0打开，以将T0的漏极电压和T0的源极电压重置为Vi2，以使得T0处于偏压状态，改善磁滞现象；T7打开，I3提供复位电压Vi3，以控制O1不发光，并清除O1的阳极残留的电荷；Vi3为负电压，例如，Vi3可以为-3V电压信号；
在第二发光阶段S25，S1提供高电压信号，S0提供高电压信号，S3提供高电压信号，E1和E2提供低电压信号，T4和T5打开，T0驱动O1发光。
在具体实施时，在所述保持重置阶段，所述数据线D1提供的电压信号可以为数据电压Vdata，所述数据电压Vdata为在第一充电阶段，所述数据线D1提供的数据电压，所述数据电压Vdata的电压值范围例如可以为大于等于1V而小于等于6.5V；或者，
在保持重置阶段，所述数据线D1提供的电压信号可以为重置电压信号，所述重置电压信号的电压值范围可以为大于等于4.6V而小于等于7V；
但不以此为限。
本公开如图17所示的像素电路的至少一实施例在工作时，在低频显示时，显示周期包括刷新帧和保持帧，在保持帧中的第二重置阶段，本公开实施例对所述驱动电路包括的驱动晶体管进行偏置，使得在保持帧中的重置阶段，驱动电路中的驱动晶体管的源极的电位和驱动晶体管的漏极的电位与刷新帧一致，能够改善闪烁现象。
本公开实施例所述的驱动方法，应用于上述的像素电路，所述像素电路的显示周期包括刷新帧和保持帧；所述刷新帧和所述保持帧分别包括先后设置的重置阶段和发光阶段；所述驱动方法包括：
在所述刷新帧和所述保持帧，至少在所述重置阶段，初始化电路在所述初始控制端提供的初始控制信号的控制下，控制将所述初始电压端提供的初始电压提供至所述驱动电路的第一端和/或所述驱动电路的第二端。
在本公开实施例所述的驱动方法中，所述初始化电路在初始控制信号的控制下，在所述刷新帧和所述保持帧，至少在所述重置阶段，控制将所述初始电压端提供的初始电压提供至所述驱动电路的第一端和/或所述驱动电路的第二端，以向所述驱动电路包括的驱动晶体管提供偏置电压，使得所述驱动电路包括的驱动晶体管处于偏压状态，以能改善磁滞现象，提升显示效果。
可选的，所述初始化电路包括第一初始化子电路；所述像素电路还包括第一发光控制电路、第二发光控制电路、数据写入电路和复位电路；所述刷新帧包括先后设置的第一初始化阶段、第一复位阶段、第一充电阶段、第一重置阶段和第一发光阶段；本公开至少一实施例所述的驱动方法包括：
在所述第一初始化阶段，所述第一初始化子电路在第一初始控制信号的控制下，将第一初始电压端提供的第一初始电压写入驱动电路的第二端；补偿控制电路在补偿控制信号的控制下，控制所述驱动电路的控制端与所述驱动电路的第二端之间连通；
在所述第一复位阶段，所述复位电路在复位控制信号的控制下，将复位电压端提供的复位电压写入发光元件的第一极，第二发光控制电路在第二发光控制信号的控制下，控制所述驱动电路的第二端与所述发光元件的第一极之间连通；补偿控制电路在补偿控制信号的控制下，控制所述驱动电路的控制端与所述驱动电路的第二端之间连通；
在所述第一充电阶段，所述数据写入电路将数据线提供的数据电压写入所述驱动电路的第一端，补偿控制电路在补偿控制信号的控制下，控制所述驱动电路的控制端与所述驱动电路的第二端之间连通；
在所述第一重置阶段，所述第一初始化子电路在第一初始控制信号的控制下，将第一初始电压端提供的第一初始电压写入驱动电路的第二端；所述驱动电路在其控制端的电位的控制下，控制所述驱动电路的第一端与所述驱动电路的第二端之间连通，以控制所述驱动电路包括的驱动晶体管处于偏压状态；
在第一发光阶段，所述第一发光控制电路在第一发光控制信号的控制下，控制电源电压端与所述驱动电路的第一端之间连通；所述第二发光控制电路在第二发光控制信号的控制下，控制所述驱动电路的第二端与所述发光元件的第一极之间连通；所述驱动电路在其控制端的电位的控制下，驱动所述发光元件发光。
在本公开至少一实施例中，所述初始化电路包括第一初始化子电路；所述像素电路还包括第一发光控制电路、第二发光控制电路、数据写入电路和复位电路；所述保持帧包括先后设置的第二初始化阶段、第二复位阶段、第二重置阶段和第二发光阶段；所述驱动方法包括：
在所述保持帧，补偿控制电路在补偿控制信号的控制下，控制所述驱动电路的控制端与所述驱动电路的第二端之间断开；
在所述第二初始化阶段，所述第一初始化子电路在第一初始控制信号的控制下，将第一初始电压端提供的第一初始电压写入驱动电路的第二端；
在所述第二复位阶段，所述复位电路在复位控制信号的控制下，将复位电压端提供的复位电压写入发光元件的第一极，第二发光控制电路在第二发光控制信号的控制下，控制所述驱动电路的第二端与所述发光元件的第一极之间连通；
在所述第二重置阶段，所述第一初始化子电路在第一初始控制信号的控制下，将第一初始电压端提供的第一初始电压写入驱动电路的第二端；所述驱动电路在其控制端的电位的控制下，控制所述驱动电路的第一端与所述驱动电路的第二端之间连通，以控制所述驱动电路包括的驱动晶体管处于偏压 状态；
在第二发光阶段，所述第一发光控制电路在第一发光控制信号的控制下，控制电源电压端与所述驱动电路的第一端之间连通；所述第二发光控制电路在第二发光控制信号的控制下，控制所述驱动电路的第二端与所述发光元件的第一极之间连通；所述驱动电路在其控制端的电位的控制下，驱动所述发光元件发光。
在本公开至少一实施例中，所述保持帧还包括设置于第二复位阶段和第二重置阶段之间的保持置位阶段；所述驱动方法还包括：
在所述保持置位阶段，所述数据写入电路将数据线提供的电压信号写入所述驱动电路的第一端。
可选的，所述初始化电路包括第二初始化子电路；所述像素电路还包括第一发光控制电路、第二发光控制电路、数据写入电路和复位电路；所述刷新帧包括先后设置的第一初始化阶段、第一复位阶段、第一充电阶段、第一重置阶段和第一发光阶段；本公开至少一实施例所述的驱动方法包括：
在所述第一初始化阶段，所述第二初始化子电路在第二初始控制信号的控制下，将第二初始电压端提供的第二初始电压写入驱动电路的第一端；补偿控制电路在补偿控制信号的控制下，控制所述驱动电路的控制端与所述驱动电路的第二端之间连通；
在所述第一复位阶段，所述复位电路在复位控制信号的控制下，将复位电压端提供的复位电压写入发光元件的第一极；第二发光控制电路在第二发光控制信号的控制下，控制所述驱动电路的第二端与所述发光元件的第一极之间连通；补偿控制电路在补偿控制信号的控制下，控制所述驱动电路的控制端与所述驱动电路的第二端之间连通；
在所述第一充电阶段，所述数据写入电路将数据线提供的数据电压写入所述驱动电路的第一端，补偿控制电路在补偿控制信号的控制下，控制所述驱动电路的控制端与所述驱动电路的第二端之间连通；
在所述第一重置阶段，所述第二初始化子电路在第二初始控制信号的控制下，将第二初始电压端提供的第二初始电压写入驱动电路的第一端；所述驱动电路在其控制端的电位的控制下，控制所述驱动电路的第一端与所述驱 动电路的第二端之间连通，以控制所述驱动电路包括的驱动晶体管处于偏压状态；
在第一发光阶段，所述第一发光控制电路在第一发光控制信号的控制下，控制电源电压端与所述驱动电路的第一端之间连通；所述第二发光控制电路在第二发光控制信号的控制下，控制所述驱动电路的第二端与所述发光元件的第一极之间连通；所述驱动电路在其控制端的电位的控制下，驱动所述发光元件发光。
在本公开至少一实施例中，所述初始化电路包括第二初始化子电路；所述像素电路还包括第一发光控制电路、第二发光控制电路、数据写入电路和复位电路；所述保持帧包括先后设置的第二初始化阶段、第二复位阶段、第二重置阶段和第二发光阶段；所述驱动方法包括：
在所述保持帧，补偿控制电路在补偿控制信号的控制下，控制所述驱动电路的控制端与所述驱动电路的第二端之间断开；
在所述第二初始化阶段，所述第二初始化子电路在第二初始控制信号的控制下，将第二初始电压端提供的第二初始电压写入驱动电路的第一端；
在所述第二复位阶段，所述复位电路在复位控制信号的控制下，将复位电压端提供的复位电压写入发光元件的第一极；第二发光控制电路在第二发光控制信号的控制下，控制所述驱动电路的第二端与所述发光元件的第一极之间连通；
在所述第二重置阶段，所述第二初始化子电路在第二初始控制信号的控制下，将第二初始电压端提供的第二初始电压写入驱动电路的第一端；所述驱动电路在其控制端的电位的控制下，控制所述驱动电路的第一端与所述驱动电路的第二端之间连通，以控制所述驱动电路包括的驱动晶体管处于偏压状态；
在第二发光阶段，所述第一发光控制电路在第一发光控制信号的控制下，控制电源电压端与所述驱动电路的第一端之间连通；所述第二发光控制电路在第二发光控制信号的控制下，控制所述驱动电路的第二端与所述发光元件的第一极之间连通；所述驱动电路在其控制端的电位的控制下，驱动所述发光元件发光。
在本公开至少一实施例中，所述保持帧还包括设置于第二复位阶段和第二重置阶段之间的保持置位阶段；所述驱动方法还包括：
在所述保持置位阶段，所述数据写入电路将数据线提供的电压信号写入所述驱动电路的第一端。
可选的，所述初始化电路包括第一初始化子电路和第二初始化子电路；所述像素电路还包括第一发光控制电路、第二发光控制电路和数据写入电路；所述刷新帧包括先后设置的第一复位阶段、第一充电阶段、第一重置阶段和第一发光阶段；本公开至少一实施例所述的驱动方法包括：
在所述第一复位阶段，所述第一初始化子电路在第一初始控制信号的控制下，将第一初始电压端提供的第一初始电压写入所述驱动电路的第二端，补偿控制电路在补偿控制信号的控制下，控制所述驱动电路的控制端与所述驱动电路的第二端之间连通；
在所述第一充电阶段，所述数据写入电路将数据线提供的数据电压写入所述驱动电路的第一端，补偿控制电路在补偿控制信号的控制下，控制所述驱动电路的控制端与所述驱动电路的第二端之间连通；
在所述第一重置阶段，所述第二初始化子电路在第二初始控制信号的控制下，将第二初始电压端提供的第二初始电压写入所述驱动电路的第一端，所述驱动电路在其控制端的电位的控制下，控制所述驱动电路的第一端与所述驱动电路的第二端之间连通，以控制所述驱动电路包括的驱动晶体管处于偏压状态；
在第一发光阶段，所述第一发光控制电路在第一发光控制信号的控制下，控制电源电压端与所述驱动电路的第一端之间连通；所述第二发光控制电路在第二发光控制信号的控制下，控制所述驱动电路的第二端与所述发光元件的第一极之间连通；所述驱动电路在其控制端的电位的控制下，驱动所述发光元件发光。
在本公开至少一实施例中，所述像素电路还包括复位电路；所述驱动方法还包括：
在所述第一重置阶段，所述复位电路在复位控制信号的控制下，将复位电压端提供的复位电压写入发光元件的第一极。
可选的，所述初始化电路包括第一初始化子电路和第二初始化子电路；所述像素电路还包括第一发光控制电路、第二发光控制电路和数据写入电路；所述保持帧包括先后设置的第二初始化阶段、第二复位阶段、第二重置阶段和第二发光阶段；本公开至少一实施例所述的驱动方法包括：
在所述保持帧，补偿控制电路在补偿控制信号的控制下，控制所述驱动电路的控制端与所述驱动电路的第二端之间断开；
在所述第二复位阶段，所述第一初始化子电路在第一初始控制信号的控制下，将第一初始电压端提供的第一初始电压写入所述驱动电路的第二端；
在所述第二重置阶段，所述第二初始化子电路在第二初始控制信号的控制下，将第二初始电压端提供的第二初始电压写入所述驱动电路的第一端，所述驱动电路在其控制端的电位的控制下，控制所述驱动电路的第一端与所述驱动电路的第二端之间连通，以控制所述驱动电路包括的驱动晶体管处于偏压状态；
在第二发光阶段，所述第一发光控制电路在第一发光控制信号的控制下，控制电源电压端与所述驱动电路的第一端之间连通；所述第二发光控制电路在第二发光控制信号的控制下，控制所述驱动电路的第二端与所述发光元件的第一极之间连通；所述驱动电路在其控制端的电位的控制下，驱动所述发光元件发光。
可选的，所述像素电路还包括复位电路；本公开至少一实施例所述的驱动方法还包括：
在所述第二重置阶段，所述复位电路在复位控制信号的控制下，将复位电压端提供的复位电压写入发光元件的第一极。
在本公开至少一实施例中，所述保持帧还包括设置于第二复位阶段和第二重置阶段之间的保持置位阶段；所述驱动方法还包括：
在所述保持置位阶段，所述数据写入电路将数据线提供的电压信号写入所述驱动电路的第一端。
本公开实施例所述的显示装置包括上述的像素电路。
本公开实施例所提供的显示装置可以为手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
以上所述是本公开的优选实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本公开所述原理的前提下，还可以作出若干改进和润饰，这些改进和润饰也应视为本公开的保护范围。

Claims (25)

  1. 一种像素电路，包括发光元件、驱动电路、储能电路、初始化电路和补偿控制电路；所述像素电路的显示周期包括刷新帧和保持帧；所述刷新帧和所述保持帧分别包括先后设置的重置阶段和发光阶段；
    所述储能电路与所述驱动电路的控制端电连接，用于储存电能；
    所述补偿控制电路分别与补偿控制端、所述驱动电路的控制端和所述驱动电路的第二端电连接，用于在所述补偿控制端提供的补偿控制信号的控制下，控制所述驱动电路的控制端与所述驱动电路的第二端之间连通；
    所述初始化电路分别与初始控制端和初始电压端电连接，所述初始化电路分别与所述驱动电路的第一端和/或所述驱动电路的第二端电连接，用于在所述初始控制端提供的初始控制信号的控制下，在所述刷新帧和所述保持帧，至少在所述重置阶段，控制将所述初始电压端提供的初始电压提供至所述驱动电路的第一端和/或所述驱动电路的第二端；
    所述驱动电路的第二端与所述发光元件电连接，用于在所述驱动电路的控制端的电位的控制下，驱动所述发光元件。
  2. 如权利要求1所述的像素电路，其中，所述驱动电路包括的驱动晶体管为p型晶体管，所述初始电压为正电压。
  3. 如权利要求1所述的像素电路，其中，所述初始化电路包括第一初始化子电路；所述初始控制端包括第一初始控制端，所述初始电压端包括第一初始电压端；
    所述第一初始化子电路分别与所述第一初始控制端、所述第一初始电压端和所述驱动电路的第二端电连接，用于在所述第一初始控制端提供的第一初始控制信号的控制下，在所述刷新帧和所述保持帧，至少在所述重置阶段，将所述第一初始电压端提供的第一初始电压写入所述驱动电路的第二端。
  4. 如权利要求1所述的像素电路，其中，所述初始化电路包括第二初始化子电路；所述初始控制端包括第二初始控制端，所述初始电压端包括第二初始电压端；
    所述第二初始化子电路分别与所述第二初始控制端、第二初始电压端和 所述驱动电路的第一端电连接，用于在所述第二初始控制端提供的第二初始控制信号的控制下，在所述刷新帧和所述保持帧，至少在所述重置阶段，将所述第二初始电压端提供的第二初始电压写入所述驱动电路的第一端。
  5. 如权利要求1所述的像素电路，其中，所述初始化电路包括第一初始化子电路和第二初始化子电路；所述初始控制端包括第一初始控制端和第二初始控制端，所述初始电压端包括第一初始电压端和第二初始电压端；
    所述第一初始化子电路分别与所述第一初始控制端、所述第一初始电压端和所述驱动电路的第二端电连接，用于在所述第一初始控制端提供的第一初始控制信号的控制下，在所述刷新帧和所述保持帧，至少在所述重置阶段，将所述第一初始电压端提供的第一初始电压写入所述驱动电路的第二端；
    所述第二初始化子电路分别与所述第二初始控制端、第二初始电压端和所述驱动电路的第一端电连接，用于在所述第二初始控制端提供的第二初始控制信号的控制下，在所述刷新帧和所述保持帧，至少在所述重置阶段，将所述第二初始电压端提供的第二初始电压写入所述驱动电路的第一端。
  6. 如权利要求3所述的像素电路，其中，所述第一初始化子电路包括第一晶体管；
    所述第一晶体管的控制极与所述第一初始控制端电连接，所述第一晶体管的第一极与所述第一初始电压端电连接，所述第一晶体管的第二极与所述驱动电路的第二端电连接。
  7. 如权利要求4所述的像素电路，其中，所述第二初始化子电路包括第二晶体管；
    所述第二晶体管的控制极与所述第二初始控制端电连接，所述第二晶体管的第一极与所述第二初始电压端电连接，所述第二晶体管的第二极与所述驱动电路的第一端电连接。
  8. 如权利要求5所述的像素电路，其中，所述第一初始化子电路包括第一晶体管，所述第二初始化子电路包括第二晶体管；
    所述第一晶体管的控制极与所述第一初始控制端电连接，所述第一晶体管的第一极与所述第一初始电压端电连接，所述第一晶体管的第二极与所述驱动电路的第二端电连接；
    所述第二晶体管的控制极与所述第二初始控制端电连接，所述第二晶体管的第一极与所述第二初始电压端电连接，所述第二晶体管的第二极与所述驱动电路的第一端电连接。
  9. 如权利要求1至8中任一权利要求所述的像素电路，其中，还包括第一发光控制电路、第二发光控制电路和数据写入电路；
    所述第一发光控制电路分别与第一发光控制端、电源电压端和所述驱动电路的第一端电连接，用于在所述第一发光控制端提供的第一发光控制信号的控制下，控制所述电源电压端与所述驱动电路的第一端之间连通；
    所述第二发光控制电路分别与第二发光控制端、所述驱动电路的第二端和所述发光元件的第一极电连接，用于在所述第二发光控制端提供的第二发光控制信号的控制下，控制所述驱动电路的第二端与所述发光元件的第一极之间连通；所述发光元件的第二极与第一电压端电连接；
    所述数据写入电路分别与写入控制端、数据线和所述驱动电路的第一端电连接，用于在所述写入控制端提供的写入控制信号的控制下，控制所述数据线与所述驱动电路的第一端之间连通。
  10. 如权利要求9所述的像素电路，其中，还包括复位电路；
    所述复位电路分别与复位控制端、复位电压端和所述发光元件的第一极电连接，用于在所述复位控制端提供的复位控制信号的控制下，控制将所述复位电压端提供的复位电压写入所述发光元件的第一极。
  11. 如权利要求9所述的像素电路，其中，所述补偿控制电路包括第三晶体管，所述第一发光控制电路包括第四晶体管，所述第二发光控制电路包括第五晶体管，所述数据写入电路包括第六晶体管，所述驱动电路包括驱动晶体管；
    所述第三晶体管的控制极与所述补偿控制端电连接，所述第三晶体管的第一极与所述驱动电路的控制端电连接，所述第三晶体管的第二极与所述驱动电路的第二端电连接；
    所述第四晶体管的控制极与所述第一发光控制端电连接，所述第四晶体管的第一极与所述电源电压端电连接，所述第四晶体管的第二极与所述驱动电路的第一端电连接；
    所述第五晶体管的控制极与所述第二发光控制端电连接，所述第五晶体管的第一极与所述驱动电路的第二端电连接，所述第五晶体管的第二极与所述发光元件的第一极电连接；
    所述第六晶体管的控制极与写入控制端电连接，所述第六晶体管的第一极与所述数据线电连接，所述第六晶体管的第二极与所述驱动电路的第一端电连接；
    所述驱动晶体管的控制极与所述驱动电路的控制端电连接，所述驱动晶体管的第一极与所述驱动电路的第一端电连接，所述驱动晶体管的第二极与所述驱动电路的第二端电连接。
  12. 如权利要求11所述的像素电路，其中，所述第三晶体管为氧化物薄膜晶体管。
  13. 如权利要求10所述的像素电路，其中，所述复位电路包括第七晶体管；
    所述第七晶体管的控制极分别与复位控制端电连接，所述第七晶体管的第一极与所述复位电压端电连接，所述第七晶体管的第二极与所述发光元件的第一极电连接。
  14. 如权利要求13所述的像素电路，其中，所述第七晶体管为氧化物薄膜晶体管。
  15. 一种驱动方法，应用于如权利要求1至14中任一权利要求所述的像素电路，所述像素电路的显示周期包括刷新帧和保持帧；所述刷新帧和所述保持帧分别包括先后设置的重置阶段和发光阶段；所述驱动方法包括：
    在所述刷新帧和所述保持帧，至少在所述重置阶段，初始化电路在所述初始控制端提供的初始控制信号的控制下，控制将所述初始电压端提供的初始电压提供至所述驱动电路的第一端和/或所述驱动电路的第二端。
  16. 如权利要求15所述的驱动方法，其中，所述初始化电路包括第一初始化子电路；所述像素电路还包括第一发光控制电路、第二发光控制电路、数据写入电路和复位电路；所述刷新帧包括先后设置的第一初始化阶段、第一复位阶段、第一充电阶段、第一重置阶段和第一发光阶段；所述驱动方法包括：
    在所述第一初始化阶段，所述第一初始化子电路在第一初始控制信号的控制下，将第一初始电压端提供的第一初始电压写入驱动电路的第二端；补偿控制电路在补偿控制信号的控制下，控制所述驱动电路的控制端与所述驱动电路的第二端之间连通；
    在所述第一复位阶段，所述复位电路在复位控制信号的控制下，将复位电压端提供的复位电压写入发光元件的第一极，第二发光控制电路在第二发光控制信号的控制下，控制所述驱动电路的第二端与所述发光元件的第一极之间连通；补偿控制电路在补偿控制信号的控制下，控制所述驱动电路的控制端与所述驱动电路的第二端之间连通；
    在所述第一充电阶段，所述数据写入电路将数据线提供的数据电压写入所述驱动电路的第一端，补偿控制电路在补偿控制信号的控制下，控制所述驱动电路的控制端与所述驱动电路的第二端之间连通；
    在所述第一重置阶段，所述第一初始化子电路在第一初始控制信号的控制下，将第一初始电压端提供的第一初始电压写入驱动电路的第二端；所述驱动电路在其控制端的电位的控制下，控制所述驱动电路的第一端与所述驱动电路的第二端之间连通；
    在第一发光阶段，所述第一发光控制电路在第一发光控制信号的控制下，控制电源电压端与所述驱动电路的第一端之间连通；所述第二发光控制电路在第二发光控制信号的控制下，控制所述驱动电路的第二端与所述发光元件的第一极之间连通；所述驱动电路在其控制端的电位的控制下，驱动所述发光元件发光。
  17. 如权利要求15所述的驱动方法，其中，所述初始化电路包括第一初始化子电路；所述像素电路还包括第一发光控制电路、第二发光控制电路、数据写入电路和复位电路；所述保持帧包括先后设置的第二初始化阶段、第二复位阶段、第二重置阶段和第二发光阶段；所述驱动方法包括：
    在所述保持帧，补偿控制电路在补偿控制信号的控制下，控制所述驱动电路的控制端与所述驱动电路的第二端之间断开；
    在所述第二初始化阶段，所述第一初始化子电路在第一初始控制信号的控制下，将第一初始电压端提供的第一初始电压写入驱动电路的第二端；
    在所述第二复位阶段，所述复位电路在复位控制信号的控制下，将复位电压端提供的复位电压写入发光元件的第一极，第二发光控制电路在第二发光控制信号的控制下，控制所述驱动电路的第二端与所述发光元件的第一极之间连通；
    在所述第二重置阶段，所述第一初始化子电路在第一初始控制信号的控制下，将第一初始电压端提供的第一初始电压写入驱动电路的第二端；所述驱动电路在其控制端的电位的控制下，控制所述驱动电路的第一端与所述驱动电路的第二端之间连通；
    在第二发光阶段，所述第一发光控制电路在第一发光控制信号的控制下，控制电源电压端与所述驱动电路的第一端之间连通；所述第二发光控制电路在第二发光控制信号的控制下，控制所述驱动电路的第二端与所述发光元件的第一极之间连通；所述驱动电路在其控制端的电位的控制下，驱动所述发光元件发光；
    所述保持帧还包括设置于第二复位阶段和第二重置阶段之间的保持置位阶段；所述驱动方法还包括：
    在所述保持置位阶段，所述数据写入电路将数据线提供的电压信号写入所述驱动电路的第一端。
  18. 如权利要求15所述的驱动方法，其中，所述初始化电路包括第二初始化子电路；所述像素电路还包括第一发光控制电路、第二发光控制电路、数据写入电路和复位电路；所述刷新帧包括先后设置的第一初始化阶段、第一复位阶段、第一充电阶段、第一重置阶段和第一发光阶段；所述驱动方法包括：
    在所述第一初始化阶段，所述第二初始化子电路在第二初始控制信号的控制下，将第二初始电压端提供的第二初始电压写入驱动电路的第一端；补偿控制电路在补偿控制信号的控制下，控制所述驱动电路的控制端与所述驱动电路的第二端之间连通；
    在所述第一复位阶段，所述复位电路在复位控制信号的控制下，将复位电压端提供的复位电压写入发光元件的第一极；第二发光控制电路在第二发光控制信号的控制下，控制所述驱动电路的第二端与所述发光元件的第一极 之间连通；补偿控制电路在补偿控制信号的控制下，控制所述驱动电路的控制端与所述驱动电路的第二端之间连通；
    在所述第一充电阶段，所述数据写入电路将数据线提供的数据电压写入所述驱动电路的第一端，补偿控制电路在补偿控制信号的控制下，控制所述驱动电路的控制端与所述驱动电路的第二端之间连通；
    在所述第一重置阶段，所述第二初始化子电路在第二初始控制信号的控制下，将第二初始电压端提供的第二初始电压写入驱动电路的第一端；所述驱动电路在其控制端的电位的控制下，控制所述驱动电路的第一端与所述驱动电路的第二端之间连通；
    在第一发光阶段，所述第一发光控制电路在第一发光控制信号的控制下，控制电源电压端与所述驱动电路的第一端之间连通；所述第二发光控制电路在第二发光控制信号的控制下，控制所述驱动电路的第二端与所述发光元件的第一极之间连通；所述驱动电路在其控制端的电位的控制下，驱动所述发光元件发光。
  19. 如权利要求15所述的驱动方法，其中，所述初始化电路包括第二初始化子电路；所述像素电路还包括第一发光控制电路、第二发光控制电路、数据写入电路和复位电路；所述保持帧包括先后设置的第二初始化阶段、第二复位阶段、第二重置阶段和第二发光阶段；所述驱动方法包括：
    在所述保持帧，补偿控制电路在补偿控制信号的控制下，控制所述驱动电路的控制端与所述驱动电路的第二端之间断开；
    在所述第二初始化阶段，所述第二初始化子电路在第二初始控制信号的控制下，将第二初始电压端提供的第二初始电压写入驱动电路的第一端；
    在所述第二复位阶段，所述复位电路在复位控制信号的控制下，将复位电压端提供的复位电压写入发光元件的第一极；第二发光控制电路在第二发光控制信号的控制下，控制所述驱动电路的第二端与所述发光元件的第一极之间连通；
    在所述第二重置阶段，所述第二初始化子电路在第二初始控制信号的控制下，将第二初始电压端提供的第二初始电压写入驱动电路的第一端；所述驱动电路在其控制端的电位的控制下，控制所述驱动电路的第一端与所述驱 动电路的第二端之间连通；
    在第二发光阶段，所述第一发光控制电路在第一发光控制信号的控制下，控制电源电压端与所述驱动电路的第一端之间连通；所述第二发光控制电路在第二发光控制信号的控制下，控制所述驱动电路的第二端与所述发光元件的第一极之间连通；所述驱动电路在其控制端的电位的控制下，驱动所述发光元件发光；
    所述保持帧还包括设置于第二复位阶段和第二重置阶段之间的保持置位阶段；所述驱动方法还包括：
    在所述保持置位阶段，所述数据写入电路将数据线提供的电压信号写入所述驱动电路的第一端。
  20. 如权利要求15所述的驱动方法，其中，所述初始化电路包括第一初始化子电路和第二初始化子电路；所述像素电路还包括第一发光控制电路、第二发光控制电路和数据写入电路；所述刷新帧包括先后设置的第一复位阶段、第一充电阶段、第一重置阶段和第一发光阶段；所述驱动方法包括：
    在所述第一复位阶段，所述第一初始化子电路在第一初始控制信号的控制下，将第一初始电压端提供的第一初始电压写入所述驱动电路的第二端，补偿控制电路在补偿控制信号的控制下，控制所述驱动电路的控制端与所述驱动电路的第二端之间连通；
    在所述第一充电阶段，所述数据写入电路将数据线提供的数据电压写入所述驱动电路的第一端，补偿控制电路在补偿控制信号的控制下，控制所述驱动电路的控制端与所述驱动电路的第二端之间连通；
    在所述第一重置阶段，所述第二初始化子电路在第二初始控制信号的控制下，将第二初始电压端提供的第二初始电压写入所述驱动电路的第一端，所述驱动电路在其控制端的电位的控制下，控制所述驱动电路的第一端与所述驱动电路的第二端之间连通；
    在第一发光阶段，所述第一发光控制电路在第一发光控制信号的控制下，控制电源电压端与所述驱动电路的第一端之间连通；所述第二发光控制电路在第二发光控制信号的控制下，控制所述驱动电路的第二端与所述发光元件的第一极之间连通；所述驱动电路在其控制端的电位的控制下，驱动所述发 光元件发光。
  21. 如权利要求20所述的驱动方法，其中，所述像素电路还包括复位电路；所述驱动方法还包括：
    在所述第一重置阶段，所述复位电路在复位控制信号的控制下，将复位电压端提供的复位电压写入发光元件的第一极。
  22. 如权利要求15所述的驱动方法，其中，所述初始化电路包括第一初始化子电路和第二初始化子电路；所述像素电路还包括第一发光控制电路、第二发光控制电路和数据写入电路；所述保持帧包括先后设置的第二复位阶段、第二重置阶段和第二发光阶段；所述驱动方法包括：
    在所述保持帧，补偿控制电路在补偿控制信号的控制下，控制所述驱动电路的控制端与所述驱动电路的第二端之间断开；
    在所述第二复位阶段，所述第一初始化子电路在第一初始控制信号的控制下，将第一初始电压端提供的第一初始电压写入所述驱动电路的第二端；
    在所述第二重置阶段，所述第二初始化子电路在第二初始控制信号的控制下，将第二初始电压端提供的第二初始电压写入所述驱动电路的第一端，所述驱动电路在其控制端的电位的控制下，控制所述驱动电路的第一端与所述驱动电路的第二端之间连通；
    在第二发光阶段，所述第一发光控制电路在第一发光控制信号的控制下，控制电源电压端与所述驱动电路的第一端之间连通；所述第二发光控制电路在第二发光控制信号的控制下，控制所述驱动电路的第二端与所述发光元件的第一极之间连通；所述驱动电路在其控制端的电位的控制下，驱动所述发光元件发光。
  23. 如权利要求22所述的驱动方法，其中，所述像素电路还包括复位电路；所述驱动方法还包括：
    在所述第二重置阶段，所述复位电路在复位控制信号的控制下，将复位电压端提供的复位电压写入发光元件的第一极。
  24. 如权利要求22所述的驱动方法，其中，所述保持帧还包括设置于第二复位阶段和第二重置阶段之间的保持置位阶段；所述驱动方法还包括：
    在所述保持置位阶段，所述数据写入电路将数据线提供的电压信号写入 所述驱动电路的第一端。
  25. 一种显示装置，包括如权利要求1至14中任一权利要求所述的像素电路。
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