WO2023286662A1 - 積層セラミックコンデンサ - Google Patents

積層セラミックコンデンサ Download PDF

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Publication number
WO2023286662A1
WO2023286662A1 PCT/JP2022/026744 JP2022026744W WO2023286662A1 WO 2023286662 A1 WO2023286662 A1 WO 2023286662A1 JP 2022026744 W JP2022026744 W JP 2022026744W WO 2023286662 A1 WO2023286662 A1 WO 2023286662A1
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Prior art keywords
holes
internal electrode
ceramic capacitor
layer
multilayer ceramic
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PCT/JP2022/026744
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English (en)
French (fr)
Japanese (ja)
Inventor
良太 阿蘓
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Murata Manufacturing Co Ltd
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Murata Manufacturing Co Ltd
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Priority to CN202280046403.2A priority Critical patent/CN117716457A/zh
Priority to JP2023535259A priority patent/JPWO2023286662A1/ja
Publication of WO2023286662A1 publication Critical patent/WO2023286662A1/ja
Priority to US18/527,434 priority patent/US12437921B2/en
Anticipated expiration legal-status Critical
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/002—Details
    • H01G4/018—Dielectrics
    • H01G4/06—Solid dielectrics
    • H01G4/08—Inorganic dielectrics
    • H01G4/12—Ceramic dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/002—Details
    • H01G4/005—Electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/002—Details
    • H01G4/005—Electrodes
    • H01G4/008—Selection of materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/002—Details
    • H01G4/005—Electrodes
    • H01G4/008—Selection of materials
    • H01G4/0085—Fried electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/002—Details
    • H01G4/005—Electrodes
    • H01G4/012—Form of non-self-supporting electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/002—Details
    • H01G4/018—Dielectrics
    • H01G4/06—Solid dielectrics
    • H01G4/08—Inorganic dielectrics
    • H01G4/12—Ceramic dielectrics
    • H01G4/1209—Ceramic dielectrics characterised by the ceramic dielectric material
    • H01G4/1218—Ceramic dielectrics characterised by the ceramic dielectric material based on titanium oxides or titanates
    • H01G4/1227—Ceramic dielectrics characterised by the ceramic dielectric material based on titanium oxides or titanates based on alkaline earth titanates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/002—Details
    • H01G4/228—Terminals
    • H01G4/232—Terminals electrically connecting two or more layers of a stacked or rolled capacitor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/30—Stacked capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/002—Details
    • H01G4/228—Terminals
    • H01G4/232—Terminals electrically connecting two or more layers of a stacked or rolled capacitor
    • H01G4/2325—Terminals electrically connecting two or more layers of a stacked or rolled capacitor characterised by the material of the terminals

Definitions

  • the present invention relates to a multilayer ceramic capacitor.
  • a multilayer ceramic capacitor is known in which a plurality of dielectric layers made of a ceramic material and a plurality of internal electrode layers are laminated. Further miniaturization, higher capacity, and improved reliability are required for such multilayer ceramic capacitors. Therefore, attempts have been made to reduce the thickness of the dielectric layers, to reduce the thickness of the internal electrode layers, and to increase the number of these layers laminated.
  • Patent Document 1 discloses a problem that short-circuit failure occurs between internal electrode layers when dielectric layers are thinned. Patent Document 1 discloses an invention that solves this problem and suppresses deterioration in reliability by including a conductive layer between internal electrode layers.
  • the internal electrode layers are thinned, a plurality of through holes are formed in the internal electrode layers. If through holes are formed in the internal electrode layers, the life, ie reliability, of the multilayer ceramic capacitor may be reduced.
  • An object of the present invention is to provide a multilayer ceramic capacitor that suppresses deterioration in reliability.
  • the inventors of the present application have obtained new knowledge that the life of a multilayer ceramic capacitor depends on the component of the dielectric that fills the through-holes of the internal electrode layers. Specifically, when an insulating substance originating from the dielectric layer segregates in the dielectric filled in the through hole, the concentration of the electric field is suppressed. Decrease is suppressed.
  • a multilayer ceramic capacitor according to the present invention is a multilayer ceramic capacitor in which a plurality of dielectric layers made of a ceramic material and a plurality of internal electrode layers are laminated, wherein each of the plurality of internal electrode layers has a plurality of through-holes. A portion of the dielectric layer is filled in the plurality of through holes, and Si derived from the dielectric layer is segregated.
  • FIG. 1 is a perspective view showing a laminated ceramic capacitor according to this embodiment
  • FIG. FIG. 2 is a sectional view (LT section) taken along the line II-II of the multilayer ceramic capacitor shown in FIG. 1
  • FIG. 2 is a sectional view (WT section) taken along line III-III of the multilayer ceramic capacitor shown in FIG. 1
  • FIG. 3 is a sectional view (LW section) taken along line IV-IV of the multilayer ceramic capacitor shown in FIG. 2
  • FIG. 3 is a cross-sectional view (LW cross section) taken along line V-V of the multilayer ceramic capacitor shown in FIG. 2 ;
  • FIG. 2 is an enlarged view of the internal electrode layers of the multilayer ceramic capacitor according to the present embodiment, viewed from the stacking direction; It is an example of a captured image of an internal electrode layer captured using SEM-EDX. It is an example of the Si component image in FIG. 7A. It is an example of the Mg component image in FIG. 7A.
  • FIG. 3 is an enlarged view of internal electrode layers of a multilayer ceramic capacitor of a comparative example, viewed from the stacking direction;
  • FIG. 4 is a perspective view showing a laminated ceramic capacitor according to Modification 1 of the present embodiment;
  • FIG. 10 is an LW cross-sectional view of the laminate in the multilayer ceramic capacitor shown in FIG. 9, and is an LW cross-sectional view including first internal electrode layers corresponding to FIG.
  • FIG. 10 is an LW cross-sectional view of the laminate in the multilayer ceramic capacitor shown in FIG. 9, and is an LW cross-sectional view including second internal electrode layers corresponding to FIG. 5;
  • FIG. 13 is an LW cross-sectional view of the laminate in the multilayer ceramic capacitor shown in FIG. 12, and is an LW cross-sectional view including second internal electrode layers corresponding to FIG. 5.
  • FIG. 10 is an LW cross-sectional view of the laminate in the multilayer ceramic capacitor shown in FIG. 9, and is an LW cross-sectional view including second internal electrode layers corresponding to FIG. 5;
  • FIG. 1 is a perspective view showing a laminated ceramic capacitor according to the present embodiment
  • FIG. 2 is a sectional view taken along line II-II of the laminated ceramic capacitor shown in FIG. 1, and FIG. It is the III-III line sectional view of a capacitor
  • 4 is a sectional view taken along line IV-IV of the laminated ceramic capacitor shown in FIG. 2
  • FIG. 5 is a sectional view taken along line VV of the laminated ceramic capacitor shown in FIG.
  • a laminated ceramic capacitor 1 shown in FIGS. 1 to 5 includes a laminated body 10 and external electrodes 40 .
  • the X direction is the length direction L of the multilayer ceramic capacitor 1 and the multilayer body 10
  • the Y direction is the width direction W of the multilayer ceramic capacitor 1 and the multilayer body 10
  • the Z direction is the lamination of the multilayer ceramic capacitor 1 and the multilayer body 10.
  • direction T. 2 is also called the LT section
  • the section shown in FIG. 3 is also called the WT section.
  • the cross section shown in FIGS. 4 and 5 is also called an LW cross section.
  • length direction L, width direction W, and stacking direction T are not necessarily orthogonal to each other, and may intersect each other.
  • the laminate 10 has a substantially rectangular parallelepiped shape, and includes a first main surface TS1 and a second main surface TS2 facing in the lamination direction T, and a first side surface WS1 and a second side surface WS2 facing in the width direction W. , a first end surface LS1 and a second end surface LS2 facing each other in the length direction L. As shown in FIG.
  • a corner is a portion where three surfaces of the laminate 10 intersect, and a ridge is a portion where two surfaces of the laminate 10 intersect.
  • the laminate 10 has a plurality of dielectric layers 20 and a plurality of internal electrode layers 30 laminated in the lamination direction T. As shown in FIGS. Moreover, the laminate 10 has an inner layer portion 100, and a first outer layer portion 101 and a second outer layer portion 102 which are arranged to sandwich the inner layer portion 100 in the stacking direction T. As shown in FIG.
  • the inner layer section 100 includes a portion of the multiple dielectric layers 20 and multiple internal electrode layers 30 .
  • a plurality of internal electrode layers 30 are arranged facing each other with the dielectric layers 20 interposed therebetween.
  • the inner layer portion 100 is a portion that generates capacitance and substantially functions as a capacitor.
  • the first outer layer portion 101 is arranged on the first main surface TS1 side of the laminate 10, and the second outer layer portion 102 is arranged on the second main surface TS2 side of the laminate 10. More specifically, the first outer layer portion 101 is arranged between the internal electrode layer 30 closest to the first main surface TS1 among the plurality of internal electrode layers 30 and the first main surface TS1. , the second outer layer portion 102 is arranged between the internal electrode layer 30 closest to the second main surface TS2 among the plurality of internal electrode layers 30 and the second main surface TS2.
  • the first outer layer portion 101 and the second outer layer portion 102 do not include the internal electrode layer 30, and include portions of the plurality of dielectric layers 20 other than the portion for the inner layer portion 100, respectively.
  • the first outer layer portion 101 and the second outer layer portion 102 are portions that function as protective layers for the inner layer portion 100 .
  • the laminate 10 has a first side outer layer portion 111 and a second side outer layer portion 112 that sandwich the internal electrode layer 30 in the width direction W.
  • the first side outer layer portion 111 is positioned on the first side surface WS1 side of the laminate 10, and the second side outer layer portion 112 is positioned on the second side surface WS2 side of the laminate 10.
  • the first side outer layer portion 111 is positioned between the end of the internal electrode layer 30 on the side of the first side surface WS1 and the first side surface WS1, and serves as the second side outer layer.
  • the portion 112 is located between the end of the internal electrode layer 30 on the second side surface WS2 side and the second side surface WS2.
  • the first side outer layer portion 111 and the second side outer layer portion 112 do not include the internal electrode layers 30 and include only the plurality of dielectric layers 20 .
  • the first side outer layer portion 111 and the second side outer layer portion 112 are portions that function as protective layers for the internal electrode layers 30 .
  • the first side outer layer portion 111 and the second side outer layer portion 112 are also referred to as W gaps or side gaps.
  • the material of the dielectric layer 20 for example, a dielectric ceramic containing BaTiO 3 , CaTiO 3 , SrTiO 3 , CaZrO 3 or the like as a main component can be used.
  • a Mn compound, an Fe compound, a Cr compound, a Co compound, a Ni compound, or the like may be added as an accessory component.
  • the material of the dielectric layer 20 may contain Si as an auxiliary component, or may contain Mg as an auxiliary component.
  • the thickness of the dielectric layer 20 is not particularly limited, and may be, for example, from 0.2 ⁇ m to 1.0 ⁇ m, preferably from 0.3 ⁇ m to 0.5 ⁇ m.
  • the number of dielectric layers 20 is not particularly limited, and may be, for example, 15 or more and 700 or less.
  • the number of dielectric layers 20 is the total number of dielectric layers in the inner layer portion and the number of dielectric layers in the outer layer portion.
  • the multiple internal electrode layers 30 include multiple first internal electrode layers 31 and multiple second internal electrode layers 32 .
  • the plurality of first internal electrode layers 31 and the plurality of second internal electrode layers 32 are alternately arranged in the stacking direction T of the stack 10 .
  • the first internal electrode layer 31 includes a counter electrode portion 311 and a lead electrode portion 312
  • the second internal electrode layer 32 includes a counter electrode portion 321 and a lead electrode portion 322 .
  • the counter electrode portion 311 and the counter electrode portion 321 face each other in the stacking direction T of the laminate 10 with the dielectric layer 20 interposed therebetween.
  • the shape of the counter electrode portion 311 and the counter electrode portion 321 is not particularly limited, and may be, for example, a substantially rectangular shape.
  • the counter electrode portion 311 and the counter electrode portion 321 are portions that generate capacitance and substantially function as capacitors.
  • the extraction electrode portion 312 extends from the counter electrode portion 311 toward the first end surface LS1 of the laminate 10 and is exposed at the first end surface LS1.
  • the extraction electrode portion 322 extends from the counter electrode portion 321 toward the second end surface LS2 of the laminate 10 and is exposed at the second end surface LS2.
  • the shape of the extraction electrode portion 312 and the extraction electrode portion 322 is not particularly limited, and may be, for example, a substantially rectangular shape.
  • the first internal electrode layer 31 and the second internal electrode layer 32 contain metal Ni as a main component.
  • the first internal electrode layer 31 and the second internal electrode layer 32 are formed of metals such as Cu, Ag, Pd, or Au, or alloys containing at least one of these metals, such as Ag—Pd alloys. , may be included as a main component, or may be included as a component other than the main component. Further, Sn may be dissolved in a part of the first internal electrode layers 31 and a part of the second internal electrode layers 32 .
  • the first internal electrode layer 31 and the second internal electrode layer 32 may contain dielectric particles having the same composition as the ceramic contained in the dielectric layer 20 as a component other than the main component.
  • the metal of the main component is defined as the metal component with the highest weight percentage.
  • the thickness of the first internal electrode layer 31 and the second internal electrode layer 32 is not particularly limited, and may be, for example, 0.2 ⁇ m or more and 2.0 ⁇ m or less.
  • the number of first internal electrode layers 31 and second internal electrode layers 32 is not particularly limited, and may be, for example, 15 or more and 700 or less.
  • the dimensions of the laminate 10 described above are not particularly limited.
  • the thickness T1 in the direction T may be 0.05 mm or more and 32 mm or less, preferably the length L1 in the length direction L is 0.1 mm or more and 1.2 mm or less, and the width W1 in the width direction W is 0. .1 mm or more and 0.7 mm or less, the thickness T1 in the stacking direction T is 0.1 mm or more and 0.7 mm or less, and more preferably the length L1 in the length direction L is 0.2 mm or more and 0.5 mm or less.
  • the width W1 in the width direction W is 0.1 mm or more and 0.3 mm or less
  • the thickness T1 in the stacking direction T is 0.1 mm or more and 0.3 mm or less.
  • the thickness of the first outer layer portion 101 and the second outer layer portion 102 of the laminate 10 is not particularly limited, and may be 0.2 ⁇ m or more and 40 ⁇ m or less, preferably 0.5 ⁇ m or more and 20 ⁇ m or less. be.
  • the external electrode 40 includes a first external electrode 41 and a second external electrode 42 .
  • the first external electrode 41 is arranged on the first end face LS1 of the laminate 10 and connected to the first internal electrode layer 31 .
  • the first external electrode 41 may extend from the first end surface LS1 to part of the first main surface TS1 and part of the second main surface TS2. Also, the first external electrode 41 may extend from the first end surface LS1 to a portion of the first side surface WS1 and a portion of the second side surface WS2.
  • the second external electrode 42 is arranged on the second end face LS2 of the laminate 10 and connected to the second internal electrode layer 32 .
  • the second external electrode 42 may extend from the second end surface LS2 to a portion of the first main surface TS1 and a portion of the second main surface TS2. Also, the second external electrode 42 may extend from the second end surface LS2 to a portion of the first side surface WS1 and a portion of the second side surface WS2.
  • the first external electrode 41 has a first underlying electrode layer 415 and a first plating layer 416
  • the second external electrode 42 has a second underlying electrode layer 425 and a second plating layer 426.
  • the first base electrode layer 415 and the second base electrode layer 425 may be fired layers containing metal and glass.
  • glass include glass components containing at least one selected from B, Si, Ba, Mg, Al, Li, and the like.
  • borosilicate glass can be used.
  • the metal contains Cu as a main component.
  • the metal may contain at least one selected from metals such as Ni, Ag, Pd, or Au, or alloys such as Ag—Pd alloys as a main component, or may contain as a component other than the main component. It's okay.
  • the sintered layer is a layer obtained by applying a conductive paste containing metal and glass to the laminate by a dip method and then sintering it.
  • the firing may be performed after firing the internal electrode layers, or may be performed simultaneously with the firing of the internal electrode layers. Also, the fired layer may be a plurality of layers.
  • the first base electrode layer 415 and the second base electrode layer 425 may be resin layers containing conductive particles and thermosetting resin.
  • the resin layer may be formed on the fired layer described above, or may be formed directly on the laminate without forming the fired layer.
  • the resin layer is a layer obtained by applying a conductive paste containing conductive particles and a thermosetting resin to the laminate by a coating method and firing the layer.
  • the firing may be performed after firing the internal electrode layers, or may be performed simultaneously with the firing of the internal electrode layers.
  • the resin layer may be a plurality of layers.
  • each layer of the first base electrode layer 415 and the second base electrode layer 425 as the fired layer or resin layer is not particularly limited, and may be 1 ⁇ m or more and 10 ⁇ m or less.
  • the first base electrode layer 415 and the second base electrode layer 425 may be thin film layers of 1 ⁇ m or less formed by a thin film forming method such as a sputtering method or a vapor deposition method and having metal particles deposited thereon.
  • the first plating layer 416 covers at least part of the first base electrode layer 415
  • the second plating layer 426 covers at least part of the second base electrode layer 425 .
  • the first plating layer 416 and the second plating layer 426 contain at least one selected from metals such as Cu, Ni, Ag, Pd, and Au, and alloys such as Ag—Pd alloys, for example.
  • Each of the first plating layer 416 and the second plating layer 426 may be formed of multiple layers.
  • a two-layer structure of Ni plating and Sn plating is preferred.
  • the Ni plating layer can prevent the base electrode layer from being eroded by solder when mounting the ceramic electronic component, and the Sn plating layer improves the wettability of the solder when mounting the ceramic electronic component. , can be easily implemented.
  • each layer of the first plating layer 416 and the second plating layer 426 is not particularly limited, and may be 1 ⁇ m or more and 10 ⁇ m or less.
  • FIG. 6 is an enlarged view of the internal electrode layers viewed from the stacking direction.
  • each of the internal electrode layers 30, that is, the first internal electrode layers 31 and the second internal electrode layers 32 has a plurality of through holes 30H.
  • These through holes 30H have a high degree of circularity.
  • the average circularity of the plurality of through holes 30H is 0.6 or more. As a result, it is possible to suppress the concentration of the electric field in the through hole 30 ⁇ /b>H, and suppress the deterioration of the life of the multilayer ceramic capacitor 1 , that is, the reliability.
  • a method for obtaining the average circularity of the through-holes 30H of the internal electrode layer 30 is not particularly limited, but the following example can be given.
  • the dielectric layers 20 are electrolytically stripped from desired internal electrode layers 30 in the vicinity of the center in the stacking direction T of the stack 10 .
  • the peeling part in the lamination direction T of the laminated body 10 is not limited to this.
  • a metallurgical microscope for example, a 100-fold objective lens, three fields of view each having a size of, for example, 30 ⁇ m ⁇ 30 ⁇ m are imaged in the vicinity of the in-plane center of the desired internal electrode layer 30 .
  • the image pick-up location in the plane of the internal electrode layer 30 and the size of the field of view are not limited to these.
  • the captured image is subjected to binarization image processing of the area where the internal electrode layer 30 exists and the area where the internal electrode layer 30 does not exist, that is, the area of the internal electrode layer 30 and the area of the through hole 30H.
  • the circularity of each through-hole 30H is calculated from the above formula, the circularity of all the through-holes 30H is averaged for each field of view, and the circularity of the three fields of view is averaged to obtain the average circularity. demand.
  • the average circularity of the through-holes 30H in the desired three fields of view of the internal electrode layer 30 is taken as the average circularity of the through-holes 30H of the plurality of internal electrode layers 30 of the multilayer ceramic capacitor 1 .
  • the ratio of the through holes 30H having a circularity of 0.6 or more is preferably 60% or more. More preferably, among the plurality of through holes 30H, the ratio of the through holes 30H having a degree of circularity of 0.6 or more is 70% or more. As a result, it is possible to further suppress the concentration of the electric field in the through hole 30H, and to further suppress the deterioration of the life of the multilayer ceramic capacitor 1, that is, the reliability.
  • a method for obtaining the ratio of the through holes 30H of the internal electrode layer 30 is not particularly limited, but the following example can be given. - As described above, in the binarized image, the circularity of each through-hole 30H is calculated from the above equation. - Calculate the ratio of the number of through-holes 30H having a degree of circularity of 0.6 or more to the number of all through-holes 30H in the three fields of view described above. In other words, the ratio of the through-holes 30H in the three fields of view of the desired internal electrode layer 30 is the ratio of the through-holes 30H of the plurality of internal electrode layers 30 of the multilayer ceramic capacitor 1 .
  • FIG. 7A is an example of a captured image of an internal electrode layer captured using SEM-EDX
  • FIG. 7B is an example of a Si component image in FIG. 7A
  • FIG. 7C is an example of a Mg component image in FIG. 7A. is.
  • a part of the adjacent dielectric layer 20 is filled in each of the through holes 30H of the internal electrode layers 30 .
  • Si derived from the dielectric layer 20 is segregated in the through hole 30H.
  • the insulation resistance in the through hole 30H can be increased. As a result, it is possible to suppress the concentration of the electric field in the through hole 30 ⁇ /b>H, and suppress the deterioration of the life of the multilayer ceramic capacitor 1 , that is, the reliability.
  • Si is preferably segregated near the edge of the through-hole 30H.
  • the Si concentration at the edge of the through-hole 30H is preferably higher than the Si concentration at the center of the through-hole 30H.
  • the insulation resistance can be enhanced in the vicinity of the edge of the through-hole 30H where electric field concentration tends to occur.
  • Mg derived from the dielectric layer 20 may be segregated in the through holes 30H.
  • the through-holes 30H in which Si is segregated among the plurality of through-holes 30H may include through-holes in which Mg derived from the dielectric layer 20 is further segregated.
  • the ratio of the through holes 30H in which Mg is further segregated is preferably 20% or less. Details will be described later.
  • the method of obtaining the ratio of the through-holes 30H in which Si and Mg are segregated is not particularly limited.
  • An example using (SEM) or transmission electron microscopy (TEM) is given below.
  • the dielectric layers 20 are electrolytically stripped from the desired internal electrode layers 30 in the vicinity of the center in the stacking direction T of the stack 10 .
  • the peeling part in the lamination direction T of the laminated body 10 is not limited to this.
  • three fields of view each having a size of, for example, 30 ⁇ m ⁇ 30 ⁇ m are imaged in the vicinity of the in-plane center of the desired internal electrode layer 30 .
  • the image pick-up location in the plane of the internal electrode layer 30 and the size of the field of view are not limited to these.
  • - Calculate the number of through-holes 30H in which Si is segregated in the captured image.
  • the number of through holes 30H in which Si is segregated such as regions R1 and R2 is calculated.
  • - Calculate the number of through-holes 30H in which Si is segregated and Mg is further segregated in the captured image.
  • the number of through-holes 30H in which Si is segregated and Mg is also segregated is calculated as in region R1.
  • the ratio of the number of through holes 30H in which Mg is further segregated to the number of through holes 30H in which Si is segregated is calculated.
  • the ratio of the through-holes 30H in the three fields of view of the desired internal electrode layer 30 is the ratio of the through-holes 30H of the plurality of internal electrode layers 30 of the multilayer ceramic capacitor 1 .
  • a dielectric sheet for the dielectric layers 20 and a conductive paste for the internal electrode layers 30 are prepared.
  • Dielectric sheets and conductive pastes contain binders and solvents. Known materials can be used as the binder and solvent.
  • an internal electrode pattern is formed on the dielectric sheet by printing a conductive paste on the dielectric sheet, for example, in a predetermined pattern.
  • a method for forming the internal electrode pattern screen printing, gravure printing, or the like can be used.
  • a predetermined number of dielectric sheets for the second outer layer portion 102 on which the internal electrode pattern is not printed are laminated.
  • Dielectric sheets for the inner layer section 100 on which the internal electrode pattern is printed are successively laminated thereon.
  • a predetermined number of dielectric sheets for the first outer layer section 101 on which the internal electrode pattern is not printed are laminated thereon. Thereby, a laminated sheet is produced.
  • the laminated sheet is pressed in the lamination direction by means of isostatic pressing or the like to produce a laminated block.
  • the laminated block is cut into a predetermined size to cut out laminated chips. At this time, the corners and ridges of the laminated chips are rounded by barrel polishing or the like.
  • the laminated chip is fired to produce the laminated body 10 .
  • the firing temperature is preferably 900° C. or more and 1400° C. or less, although it depends on the materials of the dielectric and internal electrodes.
  • the dielectric may be sintered after the internal electrodes are sintered.
  • the internal electrode layer 30 has a plurality of through holes 30H, the through holes 30H are partially filled with the dielectric layer 20, and Si derived from the dielectric layer 20 segregates.
  • Si segregates in the dielectric filled in the through hole 30H the softening point of this dielectric can be increased. Thereby, it is possible to suppress the formation of a large through hole 30H in the internal electrode. Also, the circularity of the through-holes 30H can be increased.
  • Mg derived from the dielectric layer 20 is segregated in the through-hole 30H, but among the through-holes where Si is segregated, the ratio of the through-holes where Mg is further segregated is 20% or less. and preferred.
  • Mg dissolves in Si the above-mentioned effect of increasing the softening point of the dielectric by Si is reduced. Therefore, it is preferable that the segregation of Mg in the through holes 30H is equal to or less than a predetermined amount.
  • Mg is an element added to the dielectric layer 20 to promote the grain growth of the ceramic, and the larger the grain size of the ceramic, the higher the dielectric constant can be secured. Therefore, when Mg segregates in the dielectric in the through holes 30H, the through holes 30H of the internal electrode layers 30 are widened. Therefore, it is preferable that the segregation of Mg in the through holes 30H is equal to or less than a predetermined amount. Thereby, it is possible to suppress the through holes 30H of the internal electrode layers 30 from becoming large.
  • the first end surface LS1 of the laminate 10 is a conductive paste, which is an electrode material for the underlying electrode layer
  • the first underlying electrode layer 415 is formed on the first end surface LS1.
  • a second base electrode layer 425 is formed on the second end face LS2.
  • the firing temperature is preferably 600° C. or higher and 900° C. or lower.
  • the first base electrode layer 415 and the second base electrode layer 415 which are resin layers, are formed by applying a conductive paste containing conductive particles and a thermosetting resin by a coating method and baking the paste.
  • the layer 425 may be formed, or the first base electrode layer 415 and the second base electrode layer 425 which are thin films may be formed by a thin film formation method such as a sputtering method or an evaporation method.
  • a first plated layer 416 is formed on the surface of the first base electrode layer 415 to form the first external electrode 41, and a second plated layer 426 is formed on the surface of the second base electrode layer 425. Then, the second external electrodes 42 are formed.
  • the laminated ceramic capacitor 1 described above is obtained.
  • the inventors of the present application obtained new knowledge as a result of extensive studies that the life of the multilayer ceramic capacitor 1 depends on the circularity of the through-holes 30H of the internal electrode layers 30 .
  • the life, ie reliability, of the multilayer ceramic capacitor is reduced.
  • the circularity of the through-hole 30H is high, that is, when the shape of the through-hole 30H does not have steep unevenness, concentration of the electric field is suppressed. A decrease in the life of the capacitor 1, that is, the reliability, is suppressed.
  • the average circularity of the through holes 30H of the internal electrode layers 30 is 0.6 or more. As a result, it is possible to suppress the concentration of the electric field in the through hole 30 ⁇ /b>H, and suppress the deterioration of the life of the multilayer ceramic capacitor 1 , that is, the reliability.
  • the ratio of the through holes 30H having a circularity of 0.6 or more may be 60% or more. Furthermore, among the plurality of through holes 30H of the internal electrode layer 30, the ratio of the through holes 30H having a circularity of 0.6 or more may be 70% or more. As a result, it is possible to further suppress the concentration of the electric field in the through hole 30H, and to further suppress the deterioration of the life of the multilayer ceramic capacitor 1, that is, the reliability.
  • the inventors of the present application have obtained a new finding that the life of the multilayer ceramic capacitor 1 depends on the component of the dielectric material filled in the through holes 30H of the internal electrode layers 30. Specifically, as shown in FIGS. 7A and 7B, when an insulating substance derived from the dielectric layer 20 segregates in the dielectric filled in the through hole 30H, the concentration of the electric field is suppressed. , the deterioration of the life, that is, the reliability, of the multilayer ceramic capacitor 1 is suppressed.
  • the through holes 30H of the internal electrode layers 30 are partially filled with the dielectric layers 20, and the Si derived from the dielectric layers 20 Segregated.
  • the insulation resistance in the through hole 30H can be increased.
  • the Si concentration at the edge of the through hole 30H of the internal electrode layer 30 may be higher than the Si concentration at the center of the through hole 30H.
  • the insulation resistance can be enhanced in the vicinity of the edge of the through-hole 30H where electric field concentration tends to occur.
  • the dielectric may be sintered after the internal electrodes are sintered.
  • the softening point of the dielectric can be increased. Thereby, it is possible to suppress the formation of a large through hole 30H in the internal electrode. Also, the circularity of the through-holes 30H can be increased.
  • the through holes 30H of the internal electrode layers 30, Mg derived from the dielectric layers 20 is further segregated.
  • the through holes 30H in which Si is segregated, and the through holes 30H in which Mg is further segregated. may be 20% or less.
  • Mg dissolves in Si the above-mentioned effect of increasing the softening point of the dielectric by Si is reduced. Therefore, it is preferable that the segregation of Mg in the through holes 30H is equal to or less than a predetermined amount.
  • Mg is an element added to the dielectric layer 20 to promote the grain growth of the ceramic, and the larger the grain size of the ceramic, the higher the dielectric constant can be secured. Therefore, when Mg segregates in the dielectric in the through holes 30H, the through holes 30H of the internal electrode layers 30 are widened. Therefore, it is preferable that the segregation of Mg in the through holes 30H is equal to or less than a predetermined amount. Thereby, it is possible to suppress the through holes 30H of the internal electrode layers 30 from becoming large.
  • the present invention is not limited to the above-described embodiments, and various modifications and variations are possible.
  • the laminated ceramic capacitor 1 in which the external electrodes 40 are formed on the end faces LS1 and LS2 of the laminated body 10 is illustrated.
  • the features of the present invention are not limited to this, and can be applied to, for example, a laminated ceramic capacitor in which external electrodes are formed on the side surfaces WS1 and WS2 of the laminated body 10.
  • the two-terminal type multilayer ceramic capacitor 1 having two external electrodes is exemplified.
  • the features of the present invention are not limited to this, and can also be applied to multi-terminal multilayer ceramic capacitors having three or more external electrodes.
  • Examples of such multi-terminal type laminated ceramic capacitors include laminated ceramic capacitors that reduce equivalent series inductance (ESL).
  • ESL equivalent series inductance
  • two modified examples of a three-terminal type laminated ceramic capacitor and an eight-terminal type laminated ceramic capacitor will be exemplified below.
  • Modification 1 9 is a perspective view showing a laminated ceramic capacitor according to Modification 1 of the present embodiment
  • FIG. 10 is an LW cross-sectional view of the laminate in the laminated ceramic capacitor shown in FIG. 11 is an LW cross-sectional view of a laminate in the multilayer ceramic capacitor shown in FIG. 9, and is an LW cross-sectional view including a second internal electrode layer corresponding to FIG. is.
  • a laminated ceramic capacitor 1 of Modification 1 shown in FIGS. 9 to 11 is a three-terminal type laminated ceramic capacitor that reduces ESL.
  • the multilayer ceramic capacitor 1 of Modification 1 is the multilayer ceramic capacitor 1 shown in FIGS. An external electrode 44 is provided.
  • the first external electrode 41 is arranged on the first end surface LS1 of the laminate 10, and the second external electrode 42 is arranged on the second end surface LS2 of the laminate 10.
  • the third external electrode 43 is arranged on the first side surface WS1 of the laminate 10, and the fourth external electrode 44 is arranged on the second side surface WS2 of the laminate 10. As shown in FIG.
  • the first internal electrode layer 31 is exposed at the first end surface LS1 and the second end surface LS2 of the laminate 10 and connected to the first external electrode 41 and the second external electrode 42 . Further, the second internal electrode layer 32 is exposed on the first side surface WS1 and the second side surface WS2 of the laminate 10, and is connected to the third external electrode 43 and the fourth external electrode 44. .
  • Modification 2 12 is a perspective view showing a laminated ceramic capacitor according to Modification 2 of the present embodiment
  • FIG. 13 is an LW cross-sectional view of the laminate in the laminated ceramic capacitor shown in FIG. 14 is an LW cross-sectional view of a laminate in the multilayer ceramic capacitor shown in FIG. 12, and is an LW cross-sectional view including a second internal electrode layer corresponding to FIG. is.
  • the laminated ceramic capacitor 1 of Modification 2 shown in FIGS. 12 to 14 is an 8-terminal type laminated ceramic capacitor that reduces ESL.
  • the multilayer ceramic capacitor 1 of Modification 2 is the multilayer ceramic capacitor 1 shown in FIGS.
  • An external electrode 44 , a fifth external electrode 45 , a sixth external electrode 46 , a seventh external electrode 47 and an eighth external electrode 48 are provided.
  • the first external electrode 41, the seventh external electrode 47, the third external electrode 43 and the eighth external electrode 48 are arranged on the first side surface WS1 of the laminate 10 from the first end surface LS1 to the second end surface. They are arranged in this order toward LS2. Further, the fifth external electrode 45, the third external electrode 43, the sixth external electrode 46 and the fourth external electrode 44 are arranged on the second side surface WS2 of the laminate 10 from the first end surface LS1 to the second external electrode 44. are arranged in this order toward the end face LS2 of .
  • the first internal electrode layer 31 is exposed on the first side surface WS1 and the second side surface WS2 of the laminate 10, and the first external electrode 41, the second external electrode 42 and the third external electrode 43 are formed. and the fourth external electrode 44 . Further, the second internal electrode layer 32 is exposed on the first side surface WS1 and the second side surface WS2 of the laminate 10, and the fifth external electrode 45, the sixth external electrode 46, the seventh external electrode It is connected to the electrode 47 and the eighth external electrode 48 .
  • the laminated ceramic capacitors of this embodiment shown in FIGS. 1 to 5 were produced as Examples 1 to 17, and the laminated ceramic capacitors of Comparative Examples 1 to 6 were produced.
  • BT is Ba and Ti
  • BCT is Ba, Ti and Ca
  • CZ Ca and Zr, a perovskite-type compound.
  • Abundance ratio of 4 or more and less than 1.0, 1.0 or more, and further 3.0 or more, and through-holes in which Mg is further segregated in the through-holes in which Si is segregated among the through-holes of the internal electrode layer The abundance ratio of is shown in Table 2.
  • a method of calculating the average circularity of the through-holes is the same as the example described above. i.e. electrolytically stripping the dielectric layer from the desired internal electrode layer in the vicinity of the center in the stacking direction of the laminate, Using a metallurgical microscope and a 100x objective lens, three fields of view with a size of 30 ⁇ m ⁇ 30 ⁇ m are imaged near the center of the desired internal electrode layer, -Binary image processing is performed on the captured image for the area of the internal electrode layer and the area of the through hole, ⁇ In the binarized image, the circularity of each through-hole was calculated from the above formula, the circularity of all through-holes was averaged for each field of view, and the circularity of the three fields of view was averaged to obtain the average circularity. .
  • the calculation method of the existence ratio for each degree of circularity of the through-holes is the same as the example described above. i.e. ⁇ As described above, in the binarized image, the circularity of each through-hole is calculated from the above formula, - Calculate the ratio of the number of through-holes for each degree of circularity with respect to all the numbers of through-holes in the three fields of view described above.
  • the calculation method of the existence ratio of the through-holes in which Mg is further segregated to the through-holes in which Si is segregated among the through-holes of the internal electrode layer is the same as the example described above. i.e. - As described above, the dielectric layers are electrolytically stripped from desired internal electrode layers in the vicinity of the center in the stacking direction of the stack, ⁇ As described above, using SEM-EDX, three fields of view with a size of 30 ⁇ m ⁇ 30 ⁇ m are imaged near the center of the desired internal electrode layer, ⁇ Calculate 20 through-holes in which Si is segregated in the captured image, - Calculate the number of through-holes in which Mg is further segregated in the 20 through-holes in which Si is segregated in the captured image, - Calculate the ratio of the number of through-holes further segregated with Mg to the 20 through-holes with segregated Si in the three fields of view described above.
  • HALT Highly Accelerated Limit Test
  • HALT is a test that applies stress such as temperature and vibration exceeding specifications to the test object to clarify the operation limit and / or destruction limit, in other words, the operating margin and / or destruction margin for the specification, so-called accelerated test and / or destructive testing.
  • HALT makes it possible to test margins to specifications, ie reliability, in a short period of time.
  • the HALT conditions are as follows. Temperature 150°C, Voltage 30V
  • Table 2 shows the three-level judgment based on the time to failure (Mean Time To Failure: MTTF) as the HALT evaluation results.
  • MTTF time to failure
  • the insulation resistance between terminals was 100 k ⁇ or less.
  • ⁇ indicates that the MTTF is 10 hours or more
  • ⁇ indicates that the MTTF is 5 hours or more and less than 10 hours
  • x indicates that the MTTF is less than 5 hours.

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