WO2023284287A1 - 半导体结构及其形成方法 - Google Patents

半导体结构及其形成方法 Download PDF

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Publication number
WO2023284287A1
WO2023284287A1 PCT/CN2022/074554 CN2022074554W WO2023284287A1 WO 2023284287 A1 WO2023284287 A1 WO 2023284287A1 CN 2022074554 W CN2022074554 W CN 2022074554W WO 2023284287 A1 WO2023284287 A1 WO 2023284287A1
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electrical contact
gate structure
doped region
contact layer
sidewall
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PCT/CN2022/074554
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English (en)
French (fr)
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李宗翰
廖君玮
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长鑫存储技术有限公司
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Priority to US18/152,205 priority Critical patent/US20230163179A1/en
Publication of WO2023284287A1 publication Critical patent/WO2023284287A1/zh

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    • H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
    • H01L29/4941—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with a barrier layer between the silicon and the metal or metal silicide upper layer, e.g. Silicide/TiN/Polysilicon
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    • H10B12/05—Making the transistor

Definitions

  • the present disclosure relates to, but is not limited to, a semiconductor structure and method of forming the same.
  • Dynamic Random Access Memory is a semiconductor storage device commonly used in computers, consisting of many repeated storage units. Each memory cell usually includes a capacitor and a transistor. The gate of the transistor is connected to the word line, the drain is connected to the bit line, and the source is connected to the capacitor. The voltage signal on the word line can control the opening or closing of the transistor, and then through the bit line Read the data information stored in the capacitor, or write the data information into the capacitor through the bit line for storage.
  • the present disclosure provides a semiconductor structure and a method for forming the same.
  • a first aspect of the present disclosure provides a semiconductor structure, including: a substrate; a gate structure located on the substrate; a plurality of doped regions located in the substrate and located on the substrate Both sides of the gate structure; the doped region includes a first doped region and a second doped region, and the concentration of doped ions in the first doped region is greater than the concentration of doped ions in the second doped region ; the first doped region is away from the sidewall of the gate structure; an electrical contact layer, the electrical contact layer is in contact with the first doped region away from the sidewall of the gate structure, and the The top surface of the electrical contact layer is higher than the surface of the substrate; a dielectric layer is filled between the electrical contact layer and the gate structure.
  • a second aspect of the present disclosure provides a method for forming a semiconductor structure, including: providing a substrate and a gate structure, the gate structure being located on the substrate; performing ion implantation on the substrate to A plurality of doped regions are formed in the bottom, and the doped regions are located on both sides of the gate structure; the doped regions include a first doped region and a second doped region, and the first doped region is doped with The concentration of hetero ions is greater than the concentration of dopant ions in the second doped region; the first doped region is far away from the sidewall of the gate structure; part of the substrate is removed to form a trench, and the trench Exposing the first doped region away from the sidewall of the gate structure; forming an electrical contact layer, the electrical contact layer filling the trench, and the first doped region away from the gate The side walls of the structure are in contact, the top surface of the electrical contact layer is higher than the surface of the substrate; a dielectric layer is formed, and the dielectric layer is filled between the electrical contact layer
  • Fig. 1 is a structural schematic diagram of a semiconductor structure
  • FIG. 2 is a schematic structural diagram of a semiconductor structure provided by an embodiment of the present disclosure
  • FIG. 3 is another structural schematic diagram of a semiconductor structure provided by an embodiment of the present disclosure.
  • FIG. 4 is another structural schematic diagram of a semiconductor structure provided by an embodiment of the present disclosure.
  • FIG. 5 is a schematic top view of a semiconductor structure provided by an embodiment of the present disclosure.
  • FIG. 6 is another schematic top view of a semiconductor structure provided by an embodiment of the present disclosure.
  • FIG. 7 is a schematic structural diagram of a substrate and a gate structure provided in a method for forming a semiconductor structure provided by another embodiment of the present disclosure
  • FIG. 8 is a schematic structural diagram after forming a dielectric layer in the structure shown in FIG. 7;
  • FIG. 9 is a schematic structural view after forming grooves in the structure shown in FIG. 8;
  • FIG. 10 is a schematic structural view after forming an electrical contact layer in the structure shown in FIG. 9;
  • FIG. 11 is a schematic structural diagram after forming an initial electrical contact layer during the process of forming an electrical contact layer and a dielectric layer provided by another embodiment of the present disclosure
  • FIG. 12 is a schematic structural view of the structure shown in FIG. 11 after part of the initial electrical contact layer located on the sidewall of the gate structure is removed;
  • FIG. 13 is a schematic structural view of the structure shown in FIG. 12 after the grooves are filled to form a second dielectric layer.
  • FIG. 1 is a schematic structural diagram of a semiconductor structure.
  • a semiconductor structure includes: a substrate 100; a gate structure 120, the gate structure 120 is located on the substrate 100, the gate structure 120 includes a gate oxide layer 121 and a gate 122; a plurality of doped regions 110, located in the substrate 100 and on both sides of the gate structure 120; the doped region 110 includes a first doped region 111, a second doped region 112 and a third doped region 113, the first doped region 111
  • the concentration of doping ions is greater than the concentration of doping ions in the second doping region 112 and the concentration of doping ions in the third doping region 113; the second doping region 112 is formed in the third doping region 113, and the first
  • the doped region 111 is formed in the second doped region 112, and the first doped region 111, the second doped region 112 and the third doped region 113 are flush with the surface of the substrate 100; the electrical contact layer 130, the electrical contact The layer 130 is located on the upper surface of the doped region 110
  • the doped region 110 can be used as the source or drain of the semiconductor structure. It can be obtained from the above that the doped region 110 has a gradient doping distribution, and the closer to the surface of the substrate 100, the greater the doping concentration. The region with a higher doping concentration is slightly away from the gate structure 120, but the distance between the gate structure 120 and the region with a higher doping concentration in the source and drain regions is still small.
  • the gate structure 120 When the gate structure 120 is turned on, the gate structure 120 is in the An enhanced electric field is generated in the region, and the enhanced electric field still affects the dopant ions in the doped region, so that the doped region 110 leaks current under the influence of the strong electric field, which only makes the concentration of doped ions in the doped region 110 present a simple gradient distribution
  • the improvement of device performance cannot meet the requirements of further shrinking device size, and the leakage phenomenon in the source and drain regions is still serious; Closer, it is also easy to short the gate structure 120 and the electrical contact layer 130 .
  • the implementation of the present disclosure provides a semiconductor structure, the concentration of dopant ions in the first doped region is greater than the concentration of dopant ions in the second doped region, and the first doped region is far away from the sidewall of the gate structure, ensuring most of the The dopant ions are far away from the gate structure.
  • the gate structure When the gate structure is turned on, the gate structure generates an enhanced electric field in the region. Since most of the dopant ions are far away from the gate structure, the enhanced electric field will not affect the dopant ions in the source and drain regions.
  • the electrical contact layer is in contact with the side wall of the first doped region away from the gate structure, the electrical contact layer and the side wall of the gate structure are in contact with each other.
  • the distance between the gate structure is relatively long, which effectively avoids the contact short circuit between the gate structure and the electrical contact layer, and is conducive to improving the reliability of the semiconductor structure.
  • FIG. 2 is a schematic structural diagram of a semiconductor structure provided by an embodiment of the present disclosure.
  • the semiconductor structure provided in this embodiment includes: a substrate 200; a gate structure 220, the gate structure 220 is located on the substrate 200; a plurality of doped regions 210 are located in the substrate 200, and are located in the gate structure 220 on both sides; the doped region 210 includes a first doped region 211 and a second doped region 212, the concentration of doped ions in the first doped region 211 is greater than the concentration of doped ions in the second doped region 212; the first The doped region 211 is away from the sidewall of the gate structure 220; the electrical contact layer 230, the electrical contact layer 230 is in contact with the sidewall of the first doped region 211 away from the gate structure 220, and the top surface of the electrical contact layer 230 is higher than The surface of the substrate 200 ; the dielectric layer 240 , the dielectric layer 240 is filled between the electrical contact layer 230 and the gate structure 220 .
  • the material of the substrate 200 is a semiconductor material.
  • the material of the substrate 200 is silicon.
  • the substrate may also be a germanium substrate, a silicon germanium substrate, a silicon carbide substrate or a silicon-on-insulator substrate.
  • the gate structure 220 includes a gate oxide layer 221 , a first gate conductive layer 222 , a gate barrier layer 223 and a gate second conductive layer 224 stacked in sequence.
  • the material of the gate oxide layer 221 is an insulating material, such as silicon dioxide, silicon carbide or silicon nitride, which is used to isolate the gate conductive layer from the doped region 210 .
  • the first conductive layer 222 of the gate has low resistance, and its material may be polysilicon, so as to reduce the contact resistance.
  • the gate barrier layer 223 is used to block the mutual diffusion of the gate first conductive layer 222 and the gate second conductive layer 224, and is also used to increase the adhesion between the gate first conductive layer 222 and the gate second conductive layer 224 , the material of which can be titanium nitride or tantalum nitride; the material of the second conductive layer 224 of the gate can be tungsten.
  • the material of the second conductive layer of the gate may also be other metal materials such as gold or silver.
  • the gate structure 220 further includes an isolation structure 225 located on surfaces of the gate oxide layer 221 , the first gate conductive layer 222 , the gate barrier layer 223 and the second gate conductive layer 224 .
  • the isolation structure 225 is a single-layer structure, and the material of the isolation structure 225 is silicon nitride, which mainly plays the role of isolation and insulation.
  • the isolation structure may also be a multi-layer structure.
  • the isolation structure 225 has greater hardness and density, which can improve the effect of isolation, so as to avoid electrical connection between the gate structure 220 and other conductive structures formed subsequently, thereby avoiding problems such as short circuit or electric leakage.
  • the isolation structure 225 has better corrosion resistance, so it can avoid being damaged during the cleaning process.
  • the doped region 210 can be an N-type doped region or a P-type doped region; in this embodiment, the doped region 210 is an N-type doped region, and the doped region 210 is doped with N-type ions, and the substrate 200 Doped with P-type ions. In other embodiments, the doped region is a P-type doped region, the doped region is doped with P-type ions, and the substrate is doped with N-type ions.
  • the doped region 210 on one side of the gate structure 220 acts as a source, and the doped region 210 on the other side of the gate structure 220 acts as a drain.
  • the doped region 210 includes a first doped region 211 and a second doped region 212 .
  • the concentration of doping ions in the first doping region 211 is greater than the concentration of doping ions in the second doping region 212, and the first doping region 211 is far away from the sidewall of the gate structure 220, most of the doping The ions are far away from the gate structure 220.
  • the gate structure 220 When the subsequent gate structure 220 is turned on, the gate structure 220 generates an enhanced electric field in the region. Since most of the dopant ions are far away from the gate structure 220, the enhanced electric field will not affect the doped region 210.
  • Doping ions is beneficial to avoid the risk of leakage current in the doped region 210 under the influence of a strong electric field, and improve the performance of the semiconductor structure.
  • the doped region 210 further includes a third doped region 213, and the concentration of doped ions in the third doped region 213 is lower than the concentration of doped ions in the second doped region 212.
  • the first doped region 211 is formed in the second doped region 212, and the sidewall of the second doped region 212 away from the gate structure 220 is aligned with the sidewall of the first doped region 211 away from the gate structure 220. flat.
  • the second doped region 212 is formed in the third doped region 213, and the third doped region 213 is far away from the sidewall of the gate structure 220 and the second doped region 212 is far away from the sidewall of the gate structure 220.
  • the side walls are flush.
  • a third doped region with a lower doping concentration can be formed in the entire doped region 210 first. impurity region 213, and then dope the predetermined region multiple times in order to form a doped region with a higher doping concentration. In the process of forming the entire doped region 210, there is no need to worry about mutual contamination between different doped regions. question.
  • FIG. 3 is another structural schematic diagram of a semiconductor structure provided by an embodiment of the present disclosure.
  • the second doped region 212 and the first doped region 211 are sequentially arranged along a direction away from the sidewall of the gate structure 220; it can be understood that the third doped region 213 is located at the first The side of the second doped region 212 is away from the first doped region 211 .
  • the first doped region 211 with the highest doping concentration close to the sidewall of the gate structure 220 also has a larger distance from the gate structure 220 , further avoiding the problem of leakage current in the doped region 210 .
  • the material of the electrical contact layer 230 is polysilicon doped with tungsten metal or the like.
  • the electrical contact layer 230 is in contact with the sidewall of the first doped region 211 away from the gate structure 220, the distance between the electrical contact layer 230 and the gate structure 220 is relatively long, so that the subsequent contact between the gate structure 220 and the electrical contact layer 230
  • the dielectric layer 240 formed therebetween has a relatively large thickness, which can effectively avoid contact short circuit between the gate structure 220 and the electrical contact layer 230 , and is beneficial to improve the reliability of the semiconductor structure.
  • the electrical contact layer 230 includes a first electrical contact layer 231 and a second electrical contact layer 232, the first electrical contact layer 231 is in contact with the sidewall of the first doped region 211 away from the gate structure 220; the second electrical contact layer 232 is located On the first electrical contact layer 231 , in a direction perpendicular to the sidewall of the gate structure 220 , the distance between the second electrical contact layer 232 and the gate structure 220 is greater than the distance between the first electrical contact layer 231 and the gate structure 220 .
  • the second electrical contact layer 232 is directly opposite to the gate structure 220 in the electrical contact layer 230, and the distance between the second electrical contact layer 232 and the gate structure 220 is greater than that between the first electrical contact layer 231 and the gate structure 220. The distance ensures that the electrical contact layer 230 facing the gate structure 220 is far away, which is beneficial to avoid the risk of a short circuit between the gate structure 220 and the electrical contact layer 230 .
  • the top surface of the first electrical contact layer 231 is not higher than the surface of the substrate 200;
  • the sidewalls of the gate structure 220 are flush with each other, and the width of the second electrical contact layer 232 is smaller than the width of the first electrical contact layer 231 in a direction perpendicular to the sidewall of the gate structure 220 .
  • the side of the electrical contact layer 230 away from the gate structure 220 is a flat surface, which simplifies the morphology of the semiconductor structure, and on this basis maximizes the distance between the electrical contact layer 230 and the gate structure 220 .
  • the material of the first electrical contact layer 231 is the same as that of the second electrical contact layer 232 .
  • the material of the first electrical contact layer 231 is the same as that of the second electrical contact layer 232, which is beneficial to simplify the formation steps of the entire electrical contact layer 230.
  • the initial electrical contact layer is etched. By removing part of the initial electrical contact layer, the first electrical contact layer 231 and the second electrical contact layer 232 can be formed.
  • the material of the first electrical contact layer and the material of the second electrical contact layer may also be different, for example, the material of the first electrical contact layer is doped polysilicon, and the material of the second electrical contact layer is tungsten metal;
  • the first electrical contact layer is in contact with the doped region, and the contact resistance between the doped polysilicon and the doped region is small, which is beneficial to improve the electrical conduction effect of the electrical contact layer and the doped region.
  • FIG. 4 is another structural schematic diagram of a semiconductor structure provided by an embodiment of the present disclosure.
  • the width of the electrical contact layer 230 is constant in a direction perpendicular to the surface of the substrate 200 . That is to say, the electrical contact layer 230 is a whole, so that when a certain distance is ensured between the electrical contact layer 230 and the gate structure 220 , the structure of the electrical contact layer 230 is simple, which simplifies the formation process.
  • the first electrical contact layer 231 is in contact with the entire sidewall of the first doped region 211 away from the gate structure 220 .
  • the first electrical contact layer may also only be in contact with a portion of the sidewall of the first doped region away from the gate structure.
  • the electrical contact layer 230 and the doped region 210 have a larger contact area, and the larger the contact area, the smaller the contact resistance between the electrical contact layer 230 and the doped region 210, which is conducive to improving the contact between the electrical contact layer 230 and the doped region.
  • the conductive effect of the region 210 improves the performance of the semiconductor structure.
  • FIG. 5 is a schematic top view of a semiconductor structure provided by an embodiment of the present disclosure.
  • the length of the second electrical contact layer 232 is equal to the length of the first electrical contact layer 231 (refer to FIG. 2); In this way, both ends of the first electrical contact layer 231 and the second electrical contact layer 232 are aligned, and the appearance of the entire electrical contact layer 230 (refer to FIG. 2 ) is relatively flat, which simplifies the formation steps.
  • FIG. 6 is another schematic top view of the semiconductor structure provided by an embodiment of the present disclosure.
  • the length of the second electrical contact layer 232 is smaller than the length of the first electrical contact layer 231 in the extending direction of the sidewall of the doped region 210 (refer to FIG. 2 ).
  • the length of the second electrical contact layer 232 is relatively small, while ensuring that the contact area between the entire electrical contact layer 230 and the first doped region 211 remains unchanged. , the material of the entire electrical contact layer 230 is saved, which is beneficial to reducing the volume of the entire semiconductor structure.
  • the electrical contact layer 230 may also include: a metal-semiconductor compound layer, the resistivity of the material of the metal-semiconductor compound layer is greater than the resistivity of the material of the first doped region 211, and the metal-semiconductor compound layer and the first doped The region 211 is in contact away from the sidewall of the gate structure 220 .
  • the material of the metal-semiconductor compound layer can be titanium nitride, silicon nitride, etc.; the metal-semiconductor compound layer is used to block the interdiffusion between the electrical contact layer 230 and the doped region 210, and is also used to increase the size of the electrical contact layer 230 and the doped region. 210 adhesion.
  • the material of the dielectric layer 240 may be insulating materials such as silicon oxide, silicon carbide, and silicon nitride.
  • the material of the dielectric layer 240 is an insulating material, and the dielectric layer 240 located between the gate structure 220 and the electrical contact layer 230 can effectively prevent the electrical connection between the gate structure 220 and the electrical contact layer 230 .
  • the dielectric layer 240 includes a first dielectric layer 241 and a second dielectric layer 242 arranged in sequence along the direction away from the sidewall of the gate structure 220;
  • the doped region 211 is flush with the sidewall away from the gate structure 220 ;
  • the second dielectric layer 242 is located between the first dielectric layer 241 and the second electrical contact layer 232 .
  • the sidewall of the first dielectric layer 241 away from the gate structure 220 is flush with the sidewall of the first doped region 211 away from the gate structure 220, that is, the first dielectric layer 241 covers the upper surface of the doped region 210, which can ensure that When the second electrical contact layer 232 is formed, it will not affect the doped region 210 .
  • the concentration of doped ions in the first doped region 211 is greater than the concentration of doped ions in the second doped region 212, and the first doped region 211 is far away from the sidewall of the gate structure 220, ensuring most of the The doped ions are far away from the gate structure 220.
  • the gate structure 220 When the gate structure 220 is turned on, the gate structure 220 generates an enhanced electric field in the region. Since most of the doped ions are far away from the gate structure 220, the enhanced electric field will not affect the doped region 210.
  • the doping ions are beneficial to avoid the risk of leakage current in the doped region 210 under the influence of a strong electric field, and improve the performance of the semiconductor structure;
  • the walls are in contact with each other, so the distance between the electrical contact layer 230 and the gate structure 220 is relatively long, which effectively avoids the contact short circuit between the gate structure 220 and the electrical contact layer 230, and is conducive to improving the reliability of the semiconductor structure.
  • Another embodiment of the present disclosure provides a method for forming a semiconductor structure.
  • the method for forming a semiconductor structure can form the semiconductor structure provided in the previous embodiment.
  • the method for forming a semiconductor structure provided by another embodiment of the present disclosure will be described below with reference to the accompanying drawings. Describe in detail.
  • FIG. 7 to 13 are structural schematic diagrams corresponding to each step in the method for forming a semiconductor structure provided by another embodiment of the present disclosure.
  • a substrate 300 and a gate structure 320 are provided, and the gate structure 320 is located on the substrate 300 .
  • the material of the substrate 300 is a semiconductor material.
  • the material of the substrate 300 is silicon.
  • the substrate may also be a germanium substrate, a silicon germanium substrate, a silicon carbide substrate or a silicon-on-insulator substrate.
  • the gate structure 320 includes a gate oxide layer 321 , a first gate conductive layer 322 , a gate barrier layer 323 and a gate second conductive layer 324 stacked in sequence.
  • the material of the gate oxide layer 321 is silicon oxide or a high dielectric material, and the high dielectric material may include one or more of HfO2, HfSiO, HfSiON, HfAlO, HfZrO, Al2O3, TaO2 and the like.
  • the high dielectric material refers to a material with a relative dielectric constant greater than that of silicon oxide, that is, a high-k material.
  • the gate first conductive layer 322 has low resistance, and its material may be polysilicon.
  • the gate barrier layer 323 is used to block the interdiffusion of the gate first conductive layer 322 and the gate second conductive layer 324, and is also used to increase the adhesion between the gate first conductive layer 322 and the gate second conductive layer 324 , the material of which can be titanium nitride or tantalum nitride; the material of the second conductive layer 324 of the gate can be tungsten.
  • the material of the first conductive layer of the gate may also be other metal materials such as gold or silver.
  • the gate structure 320 further includes an isolation structure 325 located on the surfaces of the gate oxide layer 321 , the first gate conductive layer 322 , the gate barrier layer 323 and the second gate conductive layer 324 .
  • the isolation structure 325 is a single-layer structure, and the material of the isolation structure 325 is silicon nitride, which mainly plays the role of isolation and insulation.
  • the isolation structure may also be a multi-layer structure.
  • the isolation structure 325 has greater hardness and density, which can improve the effect of isolation, so as to avoid electrical connection between the gate structure 320 and other conductive structures formed subsequently, thereby avoiding problems such as short circuit or electric leakage.
  • the isolation structure 325 has better corrosion resistance, so that it can avoid being damaged during the cleaning process.
  • the doped regions 310 are located on both sides of the gate structure 320; the doped regions 310 include a first doped region 311 and a second doped region In the region 312 , the concentration of doping ions in the first doping region 311 is greater than the concentration of doping ions in the second doping region 312 ; the first doping region 311 is far away from the sidewall of the gate structure 320 .
  • the doped region 310 can be an N-type doped region or a P-type doped region; in this embodiment, the doped region 310 is an N-type doped region, and the doped region 310 is doped with N-type ions, and the substrate 300 Doped with P-type ions. In other embodiments, the doped region is a P-type doped region, the doped region is doped with P-type ions, and the substrate is doped with N-type ions.
  • the doped region 310 on one side of the gate structure 320 acts as a source, and the doped region 310 on the other side of the gate structure 320 acts as a drain.
  • the doped region 310 includes a first doped region 311 and a second doped region 312 .
  • the concentration of doping ions in the first doping region 311 is greater than the concentration of doping ions in the second doping region 312, and the first doping region 311 is far away from the sidewall of the gate structure 320, most of the doping The ions are far away from the gate structure 320.
  • the gate structure 320 When the subsequent gate structure 320 is turned on, the gate structure 320 generates an enhanced electric field in the region. Since most of the dopant ions are far away from the gate structure 320, the enhanced electric field will not affect the doped region 310.
  • Doping ions is beneficial to avoid the risk of leakage current in the doped region 310 under the influence of a strong electric field, and improve the performance of the semiconductor structure.
  • the formed doped region 310 further includes a third doped region 313 , and the concentration of doped ions in the third doped region 313 is lower than the concentration of doped ions in the second doped region 312 .
  • the first doped region 311 is formed in the second doped region 312, and the sidewall of the second doped region 312 away from the gate structure 320 is aligned with the sidewall of the first doped region 311 away from the gate structure 320. flat.
  • the second doped region 312 is formed in the third doped region 313, and the third doped region 313 is far away from the sidewall of the gate structure 320 and the second doped region 312 is far away from the sidewall of the gate structure 320.
  • the side walls are flush.
  • a third doped region with a lower doping concentration can be formed in the entire doped region 310 first.
  • the initial dielectric layer 343 covers the surface of the gate structure 320 and the surface of the substrate 300. In the direction perpendicular to the sidewall of the gate structure 320, the The thickness is equal to the width of the top surface of the doped region 310 .
  • the thickness of the initial dielectric layer 343 located on the sidewall of the gate structure 320 is equal to the width of the top surface of the doped region 310 , and the impact of the etching process on the doped region 310 can be avoided when part of the initial dielectric layer 343 is subsequently removed.
  • the initial dielectric layer 343 is formed by an atomic deposition process. In other embodiments, a chemical vapor deposition process may also be used to form the initial dielectric layer.
  • a mask layer 350 is formed on the upper surface of the initial dielectric layer 343 located on the upper surface of the gate structure 320 , and the mask layer 350 is a mask for subsequent removal of part of the initial mask layer 350 .
  • a dielectric layer 340 is formed, and the dielectric layer 340 is filled between the subsequently formed electrical contact layer and the gate structure 320 .
  • forming the dielectric layer 340 may be: etching part of the initial dielectric layer 343 (refer to FIG. 7 ) to expose the surface of the substrate 300 , and the remaining initial dielectric layer 343 is used as the dielectric layer 340 .
  • a wet etching process is used to remove part of the initial dielectric layer 343 .
  • the formed sidewall of the dielectric layer 340 away from the gate structure 320 is flush with the sidewall of the first doped region 311 away from the gate structure 320 . In this way, when the substrate 300 is subsequently etched using the dielectric layer 340 and the mask layer 350 as a mask, the formed trench will just expose the sidewall of the first doped region 311 away from the gate structure 320 .
  • part of the substrate 300 is removed to form a trench 360 , and the trench 360 exposes the sidewall of the first doped region 311 away from the gate structure 320 .
  • a wet etching process is used to remove part of the substrate 300 to form the trench 360 .
  • a dry etching process may also be used.
  • the trench 360 exposes the sidewall of the first doped region 311 , and the subsequent formation of an electrical contact layer filling the trench 360 can contact the region with the highest concentration in the doped region 310 , which is beneficial to improve the contact performance.
  • an electrical contact layer 330 is formed.
  • the electrical contact layer 330 fills the trench 360 (see FIG. 9 ) and is in contact with the sidewall of the first doped region 311 away from the gate structure 320 .
  • the top of the electrical contact layer 330 The surface is higher than the surface of the substrate 300 .
  • the electrical contact layer 330 may be formed as follows: the electrical contact layer 330 fills the trench 360 and is located on the sidewall of the dielectric layer 340, and the electrical contact layer 330 has the same width in the direction perpendicular to the surface of the substrate 300 .
  • the structure of the electrical contact layer 330 is simple, which simplifies the formation process.
  • the step of forming the electrical contact layer 330 and the dielectric layer 340 includes:
  • a first dielectric layer 341 is formed on the surface of the gate structure 320 , the first dielectric layer 341 is away from the sidewall of the gate structure 320 and the first doped region 311 is away from the gate structure 320
  • an initial electrical contact layer 333 is formed, the initial electrical contact layer 333 fills the trench 360, and the initial electrical contact layer 333 is located on one side of the gate structure 320 .
  • the initial electrical contact layer 333 (referring to FIG. 11 ) that is partly located on the sidewall of the gate structure 320 is removed, and the remaining initial electrical contact layer 333 is used as the electrical contact layer 330, the sidewall of the electrical contact layer 330 and the gate structure 320 A groove 370 is enclosed.
  • the electrical contact layer 330 includes a first electrical contact layer 331 and a second electrical contact layer 332, the first electrical contact layer 331 is in contact with the sidewall of the first doped region 311 away from the gate structure 320; the second electrical contact layer 332 is located on the first electrical contact layer 331. In the direction perpendicular to the sidewall of the gate structure 320, the distance between the second electrical contact layer 332 and the gate structure 320 is greater than that between the first electrical contact layer 331 and the gate structure 320. distance.
  • the second electrical contact layer 332 is directly opposite to the gate structure 320 in the electrical contact layer 330, and the distance between the second electrical contact layer 332 and the gate structure 320 is greater than that between the first electrical contact layer 331 and the gate structure 320.
  • the distance ensures that the electrical contact layer 330 facing the gate structure 320 is far away, which is beneficial to avoid the risk of a short circuit between the gate structure 320 and the electrical contact layer 330 .
  • the groove 370 (see FIG. 12 ) is filled to form a second dielectric layer 342 , and the first dielectric layer 341 and the second dielectric layer 342 constitute a dielectric layer 340 .
  • the sidewall of the first dielectric layer 341 away from the gate structure 320 is flush with the sidewall of the first doped region 311 away from the gate structure 320, that is, the first dielectric layer 341 covers the upper surface of the doped region 310, which can ensure that When the second electrical contact layer 332 is formed, it will not affect the doped region 310 .
  • the concentration of doped ions in the first doped region 311 is greater than the concentration of doped ions in the second doped region 312, and the first doped region 311 is far away from the sidewall of the gate structure 320, It is ensured that most of the dopant ions are far away from the gate structure 320.
  • the gate structure 320 When the gate structure 320 is turned on, the gate structure 320 generates an enhanced electric field in the region.
  • the enhanced electric field will not Affecting the doping ions in the doped region 310 is beneficial to avoid the risk of leakage current in the doped region 310 under the influence of a strong electric field and improve the performance of the semiconductor structure; and since the electrical contact layer 330 and the first doped region 311 are far away from the gate
  • the sidewalls of the electrode structure 320 are in contact, so the distance between the electrical contact layer 330 and the gate structure 320 is relatively long, which effectively avoids the contact short circuit between the gate structure 320 and the electrical contact layer 330, and is beneficial to improving the reliability of the semiconductor structure.

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Abstract

本公开提供一种半导体结构及其形成方法，半导体结构包括：衬底；栅极结构，栅极结构位于衬底上；多个掺杂区，位于衬底内，且位于栅极结构的两侧；掺杂区包括第一掺杂区和第二掺杂区，第一掺杂区掺杂离子的浓度大于第二掺杂区掺杂离子的浓度；第一掺杂区远离栅极结构的侧壁；电接触层，电接触层与第一掺杂区远离栅极结构的侧壁相接触，且电接触层的顶面高于衬底的表面；介质层，介质层填充于电接触层和栅极结构之间。

Description

半导体结构及其形成方法
本公开要求在2021年07月13日提交中国专利局、申请号为202110790428.0、发明名称为“半导体结构及其形成方法”的中国专利申请的优先权，其全部内容通过引用结合在本公开中。
技术领域
本公开涉及但不限于一种半导体结构及其形成方法。
背景技术
动态随机存取存储器(Dynamic Random Access Memory，DRAM)是计算机中常用的半导体存储器件，由许多重复的存储单元组成。每个存储单元通常包括电容器和晶体管，晶体管的栅极与字线相连、漏极与位线相连、源极与电容器相连，字线上的电压信号能够控制晶体管的打开或关闭，进而通过位线读取存储在电容器中的数据信息，或者通过位线将数据信息写入到电容器中进行存储。
随着集成电路技术的快速发展，集成电路中器件的密集度越来越高，半导体器件的特征尺寸不断减小，特别是有效栅长(effective gate length)的缩短，短沟道效应(Short-channel effects)导致的源漏区漏电问题，对器件可靠性提出了挑战。
发明内容
以下是对本公开详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
本公开提供一种半导体结构及其形成方法。
本公开的第一方面提供一种半导体结构，包括：衬底；栅极结构，所述栅极结构位于所述衬底上；多个掺杂区，位于所述衬底内，且位于所述栅极结构的两侧；所述掺杂区包括第一掺杂区和第二掺杂区，所述第一掺杂区掺杂离子的浓度大于所述第二掺杂区掺杂离子的浓度；所述 第一掺杂区远离所述栅极结构的侧壁；电接触层，所述电接触层与所述第一掺杂区远离所述栅极结构的侧壁相接触，且所述电接触层的顶面高于所述衬底的表面；介质层，所述介质层填充于所述电接触层和所述栅极结构之间。
本公开的第二方面提供一种半导体结构的形成方法，包括：提供衬底和栅极结构，所述栅极结构位于所述衬底上；对所述衬底进行离子注入以在所述衬底内形成多个掺杂区，所述掺杂区位于所述栅极结构的两侧；所述掺杂区包括第一掺杂区和第二掺杂区，所述第一掺杂区掺杂离子的浓度大于所述第二掺杂区掺杂离子的浓度；所述第一掺杂区远离所述栅极结构的侧壁；去除部分所述衬底，形成沟槽，所述沟槽暴露出所述第一掺杂区远离所述栅极结构的侧壁；形成电接触层，所述电接触层填充满所述沟槽，且与所述第一掺杂区远离所述栅极结构的侧壁相接触，所述电接触层的顶面高于所述衬底的表面；形成介质层，所述介质层填充于所述电接触层和所述栅极结构之间。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图说明
并入到说明书中并且构成说明书的一部分的附图示出了本公开的实施例，并且与描述一起用于解释本公开实施例的原理。在这些附图中，类似的附图标记用于表示类似的要素。下面描述中的附图是本公开的一些实施例，而不是全部实施例。对于本领域技术人员来讲，在不付出创造性劳动的前提下，可以根据这些附图获得其他的附图。
图1为一种半导体结构的结构示意图；
图2为本公开一实施例提供的半导体结构的一种结构示意图；
图3为本公开一实施例提供的半导体结构的另一种结构示意图；
图4为本公开一实施例提供的半导体结构的再一种结构示意图；
图5为本公开一实施例提供的半导体结构的一种俯视结构示意图；
图6为本公开一实施例提供的半导体结构的又一种俯视结构示意图；
图7为本公开另一实施例提供的半导体结构的形成方法中提供的衬底和栅极结构的结构示意图；
图8为图7所示出的结构中形成介质层后的结构示意图；
图9为图8所示出的结构中形成沟槽后的结构示意图；
图10为图9所示出的结构中形成电接触层后的结构示意图；
图11为本公开另一实施例提供的在形成电接触层和介质层的过程中形成初始电接触层后的结构示意图；
图12为图11所示出的结构中去除部分位于栅极结构侧壁的初始电接触层后的结构示意图；
图13为图12所示出的结构中填充凹槽形成第二介质层后的结构示意图。
具体实施方式
下面将结合本公开实施例中的附图，对公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。需要说明的是，在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互任意组合。
由背景技术可知，现有技术的半导体结构的可靠性不足。
图1为一种半导体结构的结构示意图。
参考图1，一种半导体结构，包括：衬底100；栅极结构120，栅极结构120位于衬底100上，栅极结构120包括栅极氧化层121和栅极122；多个掺杂区110，位于衬底100内，且位于栅极结构120的两侧；掺杂区110包括第一掺杂区111、第二掺杂区112以及第三掺杂区113，第一掺杂区111掺杂离子的浓度大于第二掺杂区112掺杂离子的浓度和第三掺杂区113的掺杂离子的浓度；第二掺杂区112形成于第三掺杂区113之中，第一掺杂区111形成于第二掺杂区112之中，第一掺杂区111、第二掺杂区112和第三掺杂区113靠近衬底100表面齐平；电接触层130，电接触层130位于掺杂区110的上表面，与第一掺杂区111相接触。
其中，掺杂区110可以作为半导体结构的源极或漏极，由上述可以得到的是，掺杂区110为梯度式的掺杂分布，越靠近衬底100表面的区域掺杂浓 度越大，使得掺杂浓度较大的区域稍微远离了栅极结构120，但是栅极结构120与源漏区掺杂浓度较大的区域距离还是较小，栅极结构120导通时，栅极结构120在区域中产生增强电场，增强电场还是会影掺杂区的掺杂离子，使得掺杂区110在强电场的影响下漏电流，这种仅使得掺杂区110掺杂离子浓度呈简单的梯度分布的方式，对器件性能的改善并不能满足器件尺寸进一步缩小的要求，源漏区漏电现象依然严重；而且由于后续形成的电接触层130位于掺杂区110上表面，与栅极结构120的距离较近，也容易使得栅极结构120和电接触层130短路。
本公开实施提供一种半导体结构，第一掺杂区掺杂离子的浓度大于第二掺杂区掺杂离子的浓度，且第一掺杂区远离栅极结构的侧壁，保证了大部分的掺杂离子远离栅极结构，栅极结构导通时，栅极结构在区域中产生增强电场，由于大部分的掺杂离子远离栅极结构，增强电场不会影响源漏区的掺杂离子，有利于避免掺杂区在强电场的影响下有漏电流的风险，提高半导体结构的性能；而且由于电接触层与第一掺杂区远离栅极结构的侧壁相接触，所以电接触层与栅极结构的距离较远，有效避免了栅极结构和电接触层接触短路的情况，有利于提高半导体结构的可靠性。
图2为本公开一实施例提供的半导体结构的一种结构示意图。
参考图2，本实施例提供的半导体结构包括：衬底200；栅极结构220，栅极结构220位于衬底200上；多个掺杂区210，位于衬底200内，且位于栅极结构220的两侧；掺杂区210包括第一掺杂区211和第二掺杂区212，第一掺杂区211掺杂离子的浓度大于第二掺杂区212掺杂离子的浓度；第一掺杂区211远离栅极结构220的侧壁；电接触层230，电接触层230与第一掺杂区211远离栅极结构220的侧壁相接触，且电接触层230的顶面高于衬底200的表面；介质层240，介质层240填充于电接触层230和栅极结构220之间。
衬底200的材料为半导体材料。本实施例中，衬底200的材料为硅。在其他实施例中，衬底也可以为锗基底、锗硅基底、碳化硅基底或者绝缘体上的硅基底。
本实施例中，栅极结构220包括依次堆叠的栅极氧化层221、栅极第一导电层222、栅极阻挡层223和栅极第二导电层224。
栅极氧化层221的材料为绝缘材料，比如可以为二氧化硅、碳化硅或氮化硅，用于将栅极导电层与掺杂区210隔离。
本实施例中，栅极第一导电层222具有较低的电阻，其材料可以为多晶硅，以降低接触电阻。栅极阻挡层223用于阻挡栅极第一导电层222与栅极第二导电层224的互扩散，还用于增大栅极第一导电层222和栅极第二导电层224的黏附性，其材料可以为氮化钛或氮化钽；栅极第二导电层224的材料可以为钨。在其他实施例中，栅极第二导电层的材料也可以为金或者银等其他金属材料。
栅极结构220还包括隔离结构225，隔离结构225位于栅极氧化层221、栅极第一导电层222、栅极阻挡层223和栅极第二导电层224的表面。
在本实施例中，隔离结构225为单层结构，隔离结构225的材料为氮化硅，主要起隔离绝缘的作用。在其他实施例中，隔离结构也可以为多层结构。隔离结构225具有较大的硬度和致密度，能够提高隔离的效果，以避免栅极结构220与后续形成的其他导电结构发生电连接，从而避免产生短路或漏电等问题。另外，隔离结构225具有较好的抗腐蚀能力，如此，可以避免在清洗过程中受到损伤。
掺杂区210可以为N型掺杂区或P型掺杂区；在本实施例中，掺杂区210为N型掺杂区，掺杂区210内掺杂有N型离子，衬底200掺杂有P型离子。在其他实施例中，掺杂区为P型掺杂区，掺杂区掺杂有P型离子，衬底掺杂有N型离子。
位于栅极结构220一侧的掺杂区210作为源极，位于栅极结构220另一侧的掺杂区210作为漏极。
本实施例中，掺杂区210包括第一掺杂区211和第二掺杂区212。其中，由于第一掺杂区211掺杂离子的浓度大于第二掺杂区212掺杂离子的浓度，且第一掺杂区211远离栅极结构220的侧壁，保证了大部分的掺杂离子远离栅极结构220，后续栅极结构220导通时，栅极结构220在区域中产生增强电场，由于大部分的掺杂离子远离栅极结构220，增强电场不会影响掺杂区210的掺杂离子，有利于避免掺杂区210在强电场的影响下有漏电流的风险，提高半导体结构的性能。
本实施例中，掺杂区210还包括第三掺杂区213，第三掺杂区213掺杂 离子的浓度小于第二掺杂区212掺杂离子的浓度。
其中，第一掺杂区211形成于第二掺杂区212之中，且第二掺杂区212远离栅极结构220的侧壁和第一掺杂区211远离栅极结构220的侧壁齐平。可以理解的是，第二掺杂区212形成于第三掺杂区213之中，且第三掺杂区213远离栅极结构220的侧壁和第二掺杂区212远离栅极结构220的侧壁齐平。
形成此结构的掺杂区210，在保证掺杂区210内大部分的掺杂离子远离栅极结构220的基础上，可以先在整个掺杂区210内形成掺杂浓度较低的第三掺杂区213，再依次对预设区域进行多次掺杂，以形成掺杂浓度更高的掺杂区域，在形成整个掺杂区210的过程中，不用担心不同掺杂区域之间相互污染的问题。
图3为本公开一实施例提供的半导体结构的另一种结构示意图。
参考图3，在其他实施例中，第二掺杂区212和第一掺杂区211依次沿远离栅极结构220侧壁的方向排布；可以理解的是，第三掺杂区213位于第二掺杂区212远离第一掺杂区211的一侧。如此设置，掺杂浓度最大的第一掺杂区211靠近栅极结构220的侧壁于栅极结构220也具有较大的距离，进一步避免了掺杂区210漏电流的问题。
继续参考图2，电接触层230的材料为钨金属掺杂多晶硅等。
由于电接触层230与第一掺杂区211远离栅极结构220的侧壁相接触，所以电接触层230与栅极结构220的距离较远，这样后续在栅极结构220和电接触层230之间形成的介质层240具有较大的厚度，能够有效避免栅极结构220和电接触层230接触短路的情况，有利于提高半导体结构的可靠性。
电接触层230包括第一电接触层231和第二电接触层232，第一电接触层231与第一掺杂区211远离栅极结构220的侧壁相接触；第二电接触层232位于第一电接触层231上，在垂直于栅极结构220侧壁的方向上，第二电接触层232与栅极结构220的距离，大于第一电接触层231与栅极结构220的距离。
可以得到电接触层230中与栅极结构220正对的为第二电接触层232，而第二电接触层232与栅极结构220的距离大于第一电接触层231与栅极结构220的距离，保证了与栅极结构220正对的电接触层230距离较远，有利 于避免栅极结构220和电接触层230短路的风险。
在本实施例中，第一电接触层231的顶面不高于衬底200的表面；第二电接触层232远离栅极结构220的侧壁与第一电接触层231远离栅极结构220的侧壁齐平，在垂直于栅极结构220侧壁的方向上，第二电接触层232的宽度小于第一电接触层231的宽度。
这样，电接触层230远离栅极结构220的一侧为一个平整的面，简化了半导体结构的形貌，并且在此基础上最大化电接触层230和栅极结构220之间的距离。
本实施例中，第一电接触层231的材料和第二电接触层232的材料相同。第一电接触层231的材料和第二电接触层232的材料相同，有利于简化整个电接触层230的形成步骤，在形成整个初始电接触层之后，对初始电接触层进行刻蚀处理，去除部分初始电接触层，即可以形成第一电接触层231和第二电接触层232。
在其他实施例中，第一电接触层的材料和第二电接触层的材料也可以不同，例如第一电接触层的材料是掺杂多晶硅，第二电接触层的材料是钨金属；由于第一电接触层与掺杂区接触，掺杂多晶硅和掺杂区的接触电阻较小，有利于提高电接触层和掺杂区具有更好的导电效果。
图4为本公开一实施例提供的半导体结构的再一种结构示意图。
参考图4，在其他实施例中，电接触层230的宽度在垂直于衬底200表面的方向上不变。也即，电接触层230为一个整体，如此设置，在保证了电接触层230与栅极结构220之间具有一定的距离的情况下，电接触层230的结构简单，简化了形成工艺。
继续参考图2，在本实施例中，第一电接触层231与第一掺杂区211远离栅极结构220的整个侧壁相接触。在其他实施例中，第一电接触层也可以只与第一掺杂区远离栅极结构的部分侧壁接触。
这样，电接触层230与掺杂区210具有较大的接触面积，接触面积越大，电接触层230与掺杂区210之间的接触电阻越小，有利于提高电接触层230和掺杂区210的导电效果，进而提高半导体结构的性能。
图5为本公开一实施例提供的半导体结构的一种俯视结构示意图。
参考图5，在本实施例中，在掺杂区210(参考图2)侧壁的延伸方向上， 第二电接触层232的长度等于第一电接触层231(参考图2)的长度；这样，第一电接触层231和第二电接触层232的两端对齐，整个电接触层230(参考图2)的形貌较为平整，简化了形成步骤。
图6为本公开一实施例提供的半导体结构的又一种俯视结构示意图。
参考图6，在其他实施例中，在掺杂区210(参考图2)侧壁的延伸方向上，第二电接触层232的长度小于第一电接触层231的长度。
由于与第一掺杂区211接触的为第一电接触层231，所以第二电接触层232的长度较小，在保证整个电接触层230与第一掺杂区211接触面积不变的同时，节省了整个电接触层230的材料，有利于减小整个半导体结构的体积。
本实施例中，电接触层230还可以包括：金属半导体化合物层，金属半导体化合物层的材料的电阻率大于第一掺杂区211的材料的电阻率，且金属半导体化合物层与第一掺杂区211远离栅极结构220的侧壁相接触。
金属半导体化合物层的材料可以为氮化钛、氮化硅等；金属半导体化合物层用于阻挡电接触层230与掺杂区210的互扩散，还用于增大电接触层230和掺杂区210的黏附性。
继续参考图2，本实施例中，介质层240的材料可以为氧化硅、碳化硅、氮化硅等绝缘材料。
介质层240的材料为绝缘材料，位于栅极结构220和电接触层230之间的介质层240可以有效避免栅极结构220和电接触层230电连接。
本实施例中，介质层240包括沿远离栅极结构220侧壁方向依次排布的第一介质层241和第二介质层242；第一介质层241远离栅极结构220的侧壁与第一掺杂区211远离栅极结构220的侧壁齐平；第二介质层242位于第一介质层241和第二电接触层232之间。
第一介质层241远离栅极结构220的侧壁与第一掺杂区211远离栅极结构220的侧壁齐平，也即第一介质层241覆盖掺杂区210的上表面，可以保证在形成第二电接触层232的时候，不会对掺杂区210产生影响。
本实施例中，第一掺杂区211掺杂离子的浓度大于第二掺杂区212掺杂离子的浓度，且第一掺杂区211远离栅极结构220的侧壁，保证了大部分的掺杂离子远离栅极结构220，栅极结构220导通时，栅极结构220在区域中 产生增强电场，由于大部分的掺杂离子远离栅极结构220，增强电场不会影响掺杂区210的掺杂离子，有利于避免掺杂区210在强电场的影响下有漏电流的风险，提高半导体结构的性能；而且由于电接触层230与第一掺杂区211远离栅极结构220的侧壁相接触，所以电接触层230与栅极结构220的距离较远，有效避免了栅极结构220和电接触层230接触短路的情况，有利于提高半导体结构的可靠性。
本公开另一实施例提供一种半导体结构的形成方法，该半导体结构的形成方法可以形成上一实施例提供的半导体结构，以下将结合附图对本公开另一实施例提供的半导体结构的形成方法进行详细说明。
图7～图13为本公开另一实施例提供的半导体结构的形成方法中各步骤对应的结构示意图。
参考图7，提供衬底300和栅极结构320，栅极结构320位于衬底300上。
衬底300的材料为半导体材料。本实施例中，衬底300的材料为硅。在其他实施例中，衬底也可以为锗基底、锗硅基底、碳化硅基底或者绝缘体上的硅基底。
本实施例中，栅极结构320包括依次堆叠的栅极氧化层321、栅极第一导电层322、栅极阻挡层323和栅极第二导电层324。
栅极氧化层321的材料为氧化硅或高介电材料，高介电材料可以包括HfO2、HfSiO、HfSiON、HfAlO、HfZrO、Al2O3、TaO2等其中一种或多种材料。其中，高介电材料指的是相对介电常数大于氧化硅相对介电常数的材料，即高k材料。
本实施例中，栅极第一导电层322具有较低的电阻，其材料可以为多晶硅。栅极阻挡层323用于阻挡栅极第一导电层322与栅极第二导电层324的互扩散，还用于增大栅极第一导电层322和栅极第二导电层324的黏附性，其材料可以为氮化钛或氮化钽；栅极第二导电层324的材料可以为钨。在其他实施例中，栅极第一导电层的材料也可以为金或者银等其他金属材料。
栅极结构320还包括隔离结构325，隔离结构325位于栅极氧化层321、栅极第一导电层322、栅极阻挡层323和栅极第二导电层324的表面。
在本实施例中，隔离结构325为单层结构，隔离结构325的材料为氮化硅，主要起隔离绝缘的作用。在其他实施例中，隔离结构也可以为多层结构。 隔离结构325具有较大的硬度和致密度，能够提高隔离的效果，以避免栅极结构320与后续形成的其他导电结构发生电连接，从而避免产生短路或漏电等问题。另外，隔离结构325具有较好的抗腐蚀能力，如此，可以避免在清洗过程中受到损伤。
对衬底300进行离子注入以在衬底300内形成多个掺杂区310，掺杂区310位于栅极结构320的两侧；掺杂区310包括第一掺杂区311和第二掺杂区312，第一掺杂区311掺杂离子的浓度大于第二掺杂区312掺杂离子的浓度；第一掺杂区311远离栅极结构320的侧壁。
掺杂区310可以为N型掺杂区或P型掺杂区；在本实施例中，掺杂区310为N型掺杂区，掺杂区310内掺杂有N型离子，衬底300掺杂有P型离子。在其他实施例中，掺杂区为P型掺杂区，掺杂区掺杂有P型离子，衬底掺杂有N型离子。
位于栅极结构320一侧的掺杂区310作为源极，位于栅极结构320另一侧的掺杂区310作为漏极。
本实施例中，掺杂区310包括第一掺杂区311和第二掺杂区312。其中，由于第一掺杂区311掺杂离子的浓度大于第二掺杂区312掺杂离子的浓度，且第一掺杂区311远离栅极结构320的侧壁，保证了大部分的掺杂离子远离栅极结构320，后续栅极结构320导通时，栅极结构320在区域中产生增强电场，由于大部分的掺杂离子远离栅极结构320，增强电场不会影响掺杂区310的掺杂离子，有利于避免掺杂区310在强电场的影响下有漏电流的风险，提高半导体结构的性能。
本实施例中，形成的掺杂区310还包括第三掺杂区313，第三掺杂区313掺杂离子的浓度小于第二掺杂区312掺杂离子的浓度。
其中，第一掺杂区311形成于第二掺杂区312之中，且第二掺杂区312远离栅极结构320的侧壁和第一掺杂区311远离栅极结构320的侧壁齐平。可以理解的是，第二掺杂区312形成于第三掺杂区313之中，且第三掺杂区313远离栅极结构320的侧壁和第二掺杂区312远离栅极结构320的侧壁齐平。
形成此结构的掺杂区310，在保证掺杂区310内大部分的掺杂离子远离栅极结构320的基础上，可以先在整个掺杂区310内形成掺杂浓度较低的第 三掺杂区313，再依次对预设区域进行多次掺杂，以形成掺杂浓度更高的掺杂区域，在形成整个掺杂区310的过程中，不用担心不同掺杂区域之间相互污染的问题。
形成初始介质层343，初始介质层343覆盖栅极结构320的表面和衬底300的表面，在垂直于栅极结构320侧壁的方向上，位于栅极结构320侧壁的初始介质层343的厚度等于掺杂区310顶面的宽度。
位于栅极结构320侧壁的初始介质层343的厚度等于掺杂区310顶面的宽度，在后续去除部分初始介质层343的时候，可以避免刻蚀工艺对掺杂区310的影响。
本实施例中，采用原子沉积工艺形成初始介质层343。在其他实施例中，也可以采用化学气相沉积工艺形成初始介质层。
在位于栅极结构320上表面的初始介质层343上表面形成掩膜层350，掩膜层350为后续去除部分初始掩膜层350的掩膜。
参考图8，形成介质层340，介质层340填充于后续形成的电接触层和栅极结构320之间。
在本实施例中，形成介质层340可以为：刻蚀部分初始介质层343(参考图7)，暴露出衬底300表面，剩余的初始介质层343作为介质层340。
本实施例中，采用湿法刻蚀工艺，去除部分初始介质层343。
形成的介质层340远离栅极结构320的侧壁与第一掺杂区311远离栅极结构320的侧壁齐平。这样，在后续以介质层340和掩膜层350为掩膜刻蚀衬底300时，形成的沟槽会正好暴露出第一掺杂区311远离栅极结构320的侧壁。
参考图9，去除部分衬底300，形成沟槽360，沟槽360暴露出第一掺杂区311远离栅极结构320的侧壁。
本实施例中，采用湿法刻蚀工艺去除部分衬底300，形成沟槽360。在其他实施例中，也可以采用干法刻蚀工艺。沟槽360暴露出第一掺杂区311的侧壁，后续形成填充沟槽360的电接触层就可以和掺杂区310内浓度最大的区域接触，有利于提高接触性能。
参考图10，形成电接触层330，电接触层330填充满沟槽360(参考图9)，且与第一掺杂区311远离栅极结构320的侧壁相接触，电接触层330的顶面 高于衬底300的表面。
在本实施例中，形成的电接触层330可以为：电接触层330填充沟槽360且位于介质层340的侧壁，在垂直于衬底300表面的方向上，电接触层330的宽度相同。
如此设置，在保证了电接触层330与栅极结构320之间具有一定的距离的情况下，电接触层330的结构简单，简化了形成工艺。
在另一个例子中，形成电接触层330和介质层340的步骤包括：
参考图11，在形成栅极结构320之后，在栅极结构320表面形成第一介质层341，第一介质层341远离栅极结构320的侧壁与第一掺杂区311远离栅极结构320的侧壁齐平；在形成沟槽360(参考图9)之后，形成初始电接触层333，初始电接触层333填充满沟槽360，且初始电接触层333位于栅极结构320的一侧。
参考图12，去除部分位于栅极结构320侧壁的初始电接触层333(参考图11)，剩余的初始电接触层333作为电接触层330，电接触层330和栅极结构320的侧壁围成凹槽370。
其中，电接触层330包括第一电接触层331和第二电接触层332，第一电接触层331与第一掺杂区311远离栅极结构320的侧壁相接触；第二电接触层332位于第一电接触层331上，在垂直于栅极结构320侧壁的方向上，第二电接触层332与栅极结构320的距离，大于第一电接触层331与栅极结构320的距离。
可以得到电接触层330中与栅极结构320正对的为第二电接触层332，而第二电接触层332与栅极结构320的距离大于第一电接触层331与栅极结构320的距离，保证了与栅极结构320正对的电接触层330距离较远，有利于避免栅极结构320和电接触层330短路的风险。
参考图13，填充凹槽370(参考图12)，形成第二介质层342，第一介质层341和第二介质层342构成介质层340。
第一介质层341远离栅极结构320的侧壁与第一掺杂区311远离栅极结构320的侧壁齐平，也即第一介质层341覆盖掺杂区310的上表面，可以保证在形成第二电接触层332的时候，不会对掺杂区310产生影响。
本实施例中，形成的半导体结构，第一掺杂区311掺杂离子的浓度大于 第二掺杂区312掺杂离子的浓度，且第一掺杂区311远离栅极结构320的侧壁，保证了大部分的掺杂离子远离栅极结构320，栅极结构320导通时，栅极结构320在区域中产生增强电场，由于大部分的掺杂离子远离栅极结构320，增强电场不会影响掺杂区310的掺杂离子，有利于避免掺杂区310在强电场的影响下有漏电流的风险，提高半导体结构的性能；而且由于电接触层330与第一掺杂区311远离栅极结构320的侧壁相接触，所以电接触层330与栅极结构320的距离较远，有效避免了栅极结构320和电接触层330接触短路的情况，有利于提高半导体结构的可靠性。
本说明书中各实施例或实施方式采用递进的方式描述，每个实施例重点说明的都是与其他实施例的不同之处，各个实施例之间相同相似部分相互参见即可。
在本说明书的描述中，参考术语“实施例”、“示例性的实施例”、“一些实施方式”、“示意性实施方式”、“示例”等的描述意指结合实施方式或示例描述的具体特征、结构、材料或者特点包含于本公开的至少一个实施方式或示例中。
在本说明书中，对上述术语的示意性表述不一定指的是相同的实施方式或示例。而且，描述的具体特征、结构、材料或者特点可以在任何的一个或多个实施方式或示例中以合适的方式结合。
在本公开的描述中，需要说明的是，术语“中心”、“上”、“下”、“左”、“右”、“竖直”、“水平”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本公开和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。
可以理解的是，本公开所使用的术语“第一”、“第二”等可在本公开中用于描述各种结构，但这些结构不受这些术语的限制。这些术语仅用于将第一个结构与另一个结构区分。
在一个或多个附图中，相同的元件采用类似的附图标记来表示。为了清楚起见，附图中的多个部分没有按比例绘制。此外，可能未示出某些公知的部分。为了简明起见，可以在一幅图中描述经过数个步骤后获得的结构。在下文中描述了本公开的许多特定的细节，例如器件的结构、材料、尺寸、处 理工艺和技术，以便更清楚地理解本公开。但正如本领域技术人员能够理解的那样，可以不按照这些特定的细节来实现本公开。
最后应说明的是：以上各实施例仅用以说明本公开的技术方案，而非对其限制；尽管参照前述各实施例对本公开进行了详细的说明，本领域技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本公开各实施例技术方案的范围。

Claims (15)

  1. 一种半导体结构，包括：
    衬底；
    栅极结构，所述栅极结构位于所述衬底上；
    多个掺杂区，位于所述衬底内，且位于所述栅极结构的两侧；
    所述掺杂区包括第一掺杂区和第二掺杂区，所述第一掺杂区掺杂离子的浓度大于所述第二掺杂区掺杂离子的浓度；所述第一掺杂区远离所述栅极结构的侧壁；
    电接触层，所述电接触层与所述第一掺杂区远离所述栅极结构的侧壁相接触，且所述电接触层的顶面高于所述衬底的表面；
    介质层，所述介质层填充于所述电接触层和所述栅极结构之间。
  2. 根据权利要求1所述的半导体结构，其中，所述电接触层包括第一电接触层和第二电接触层，所述第一电接触层与所述第一掺杂区远离所述栅极结构的侧壁相接触；
    所述第二电接触层位于所述第一电接触层上，在垂直于所述栅极结构侧壁的方向上，所述第二电接触层与所述栅极结构的距离，大于所述第一电接触层与所述栅极结构的距离。
  3. 根据权利要求2所述的半导体结构，其中，所述第一电接触层的顶面不高于所述衬底的表面；
    所述第二电接触层远离所述栅极结构的侧壁与所述第一电接触层远离所述栅极结构的侧壁齐平，在垂直于所述栅极结构侧壁的方向上，所述第二电接触层的宽度小于所述第一电接触层的宽度。
  4. 根据权利要求2所述的半导体结构，其中，所述第一电接触层与所述第一掺杂区远离所述栅极结构的整个侧壁相接触。
  5. 根据权利要求2所述的半导体结构，其中，在所述掺杂区侧壁的延伸方向上，所述第二电接触层的长度小于等于所述第一电接触层的长度。
  6. 根据权利要求2所述的半导体结构，其中，所述第一电接触层的材料和所述第二电接触层的材料相同。
  7. 根据权利要求2所述的半导体结构，其中，所述介质层包括沿远离所 述栅极结构侧壁方向依次排布的第一介质层和第二介质层；
    所述第一介质层远离所述栅极结构的侧壁与所述第一掺杂区远离所述栅极结构的侧壁齐平；
    所述第二介质层位于所述第一介质层和所述第二电接触层之间。
  8. 根据权利要求1所述的半导体结构，其中，所述电接触层的宽度在垂直于所述衬底表面的方向上不变。
  9. 根据权利要求1所述的半导体结构，其中，所述第二掺杂区和所述第一掺杂区依次沿远离所述栅极结构侧壁的方向排布。
  10. 根据权利要求1所述的半导体结构，其中，所述第一掺杂区形成于所述第二掺杂区之中，且所述第二掺杂区远离所述栅极结构的侧壁和所述第一掺杂区远离所述栅极结构的侧壁齐平。
  11. 根据权利要求1所述的半导体结构，所述电接触层还包括：金属半导体化合物层，所述金属半导体化合物层的材料的电阻率大于所述第一掺杂区的材料的电阻率，且所述金属半导体化合物层与所述第一掺杂区远离所述栅极结构的侧壁相接触。
  12. 一种半导体结构的形成方法，包括：
    提供衬底和栅极结构，所述栅极结构位于所述衬底上；
    对所述衬底进行离子注入以在所述衬底内形成多个掺杂区，所述掺杂区位于所述栅极结构的两侧；
    所述掺杂区包括第一掺杂区和第二掺杂区，所述第一掺杂区掺杂离子的浓度大于所述第二掺杂区掺杂离子的浓度；所述第一掺杂区远离所述栅极结构的侧壁；
    去除部分所述衬底，形成沟槽，所述沟槽暴露出所述第一掺杂区远离所述栅极结构的侧壁；
    形成电接触层，所述电接触层填充满所述沟槽，且与所述第一掺杂区远离所述栅极结构的侧壁相接触，所述电接触层的顶面高于所述衬底的表面；
    形成介质层，所述介质层填充于所述电接触层和所述栅极结构之间。
  13. 根据权利要求12所述的半导体结构的形成方法，其中，形成所述电接触层和所述介质层的步骤包括：在形成所述栅极结构之后，在所述栅极结构表面形成所述介质层，所述介质层远离所述栅极结构的侧壁与所述第一掺 杂区远离所述栅极结构的侧壁齐平；
    在形成所述沟槽之后，形成所述电接触层，所述电接触层填充所述沟槽且位于所述介质层的侧壁，在垂直于所述衬底表面的方向上，所述电接触层的宽度相同。
  14. 根据权利要求13所述的半导体结构的形成方法，其中，形成所述介质层的步骤包括：形成初始介质层，所述初始介质层覆盖所述栅极结构的表面和所述衬底的表面，在垂直于所述栅极结构侧壁的方向上，位于所述栅极结构侧壁的所述初始介质层的厚度等于所述掺杂区顶面的宽度；
    在刻蚀所述衬底之前，刻蚀部分所述初始介质层，暴露出所述衬底表面，剩余的所述初始介质层作为所述介质层。
  15. 根据权利要求12所述的半导体结构的形成方法，其中，形成所述电接触层和所述介质层的步骤包括：在形成所述栅极结构之后，在所述栅极结构表面形成第一介质层，所述第一介质层远离所述栅极结构的侧壁与所述第一掺杂区远离所述栅极结构的侧壁齐平；
    在形成所述沟槽之后，形成初始电接触层，所述初始电接触层填充满所述沟槽，且所述初始电接触层位于所述栅极结构的一侧；
    去除部分位于所述栅极结构侧壁的所述初始电接触层，剩余的所述初始电接触层作为所述电接触层，所述电接触层和所述栅极结构的侧壁围成凹槽；
    填充所述凹槽，形成第二介质层，所述第一介质层和所述第二介质层构成所述介质层。
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