WO2024021180A1 - 半导体结构和半导体结构的制造方法 - Google Patents

半导体结构和半导体结构的制造方法 Download PDF

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WO2024021180A1
WO2024021180A1 PCT/CN2022/112183 CN2022112183W WO2024021180A1 WO 2024021180 A1 WO2024021180 A1 WO 2024021180A1 CN 2022112183 W CN2022112183 W CN 2022112183W WO 2024021180 A1 WO2024021180 A1 WO 2024021180A1
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Prior art keywords
word line
conductive layer
line conductive
hole
semiconductor structure
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PCT/CN2022/112183
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English (en)
French (fr)
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文浚硕
张思
金若兰
张世明
李延龙
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长鑫存储技术有限公司
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Priority to US18/168,513 priority Critical patent/US20240038862A1/en
Publication of WO2024021180A1 publication Critical patent/WO2024021180A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices

Definitions

  • the present disclosure belongs to the field of semiconductors, and specifically relates to a manufacturing method of a semiconductor structure and a semiconductor structure.
  • DRAM Dynamic Random Access Memory
  • DRAM Dynamic Random Access Memory
  • the main working principle of DRAM is to use the amount of charge stored in the capacitor to represent whether a stored binary bit (bit) is 1 or 0.
  • DRAM includes an array area and a peripheral area. There are memory cells in the array area and peripheral circuits in the peripheral area. The peripheral circuits can control the reading and writing process of the memory cells.
  • Embodiments of the present disclosure provide a manufacturing method of a semiconductor structure and a semiconductor structure, which are at least conducive to simplifying the process steps of the semiconductor structure, thereby reducing production costs.
  • embodiments of the present disclosure provide a method of manufacturing a semiconductor structure, wherein the method of manufacturing a semiconductor structure includes: providing a substrate with an active layer in the substrate of the peripheral region; and in the array A word line trench is formed in the substrate of the region; a word line is formed in the word line trench, and the word line includes a first word line conductive layer and a second word line conductive layer that are stacked; the first word line
  • the top of the conductive layer has a protruding portion, and the protruding portion protrudes in a direction in which the first word line conductive layer points to the second word line conductive layer; an isolation layer covering the base is formed; and a through-hole is formed at the same time.
  • another aspect of the present disclosure provides a semiconductor structure.
  • the semiconductor structure includes: a substrate, an active layer is provided in the substrate of the peripheral region; and characters are formed in the substrate of the array region.
  • the word line includes a stacked first word line conductive layer and a second word line conductive layer; the top of the first word line conductive layer has a protruding portion, and the protruding portion extends along the first word line conductive layer.
  • the word line conductive layer protrudes in the direction of the second word line conductive layer; an isolation layer covers the base, a first contact structure and a second contact structure are formed in the isolation layer, and the first contact structure is The active layer is connected, and the second contact structure is connected to the word line.
  • a protruding portion protruding upward is formed on the top of the first word line conductive layer, and the protruding portion can reduce the distance between the top surface of the first word line conductive layer and the active layer.
  • the height difference of the top surface within the substrate enables the process steps of the first through hole and the second through hole to be integrated, thereby reducing production costs.
  • Figure 1 shows a schematic top view of an array region of a semiconductor structure provided by an embodiment of the present disclosure
  • FIGS. 2-20 illustrate structural schematic diagrams corresponding to each step in a method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure.
  • DRAM has many process steps and higher production costs. Analysis found that the main reason is that: a first through hole needs to be formed in the peripheral area of the DRAM to expose the active layer and form a contact structure; a second through hole needs to be formed in the array area of the DRAM to expose the first word line conductive layer and form a contact structure.
  • the first word line conductive layer is deeper in the substrate than the active layer. If the first through hole and the second through hole are formed at the same time, the active layer will be over-etched, or the first word line conductive layer will not be exposed, thereby reducing the performance of the semiconductor structure. Therefore, the first through hole and the second through hole are usually formed in different process steps, resulting in higher production costs.
  • Embodiments of the present disclosure provide a method for manufacturing a semiconductor structure, which includes: forming a protrusion on the top of a first word line conductive layer, and etching an isolation layer to form a second through hole exposing the protrusion. That is, the protruding portion protrudes upward, which can reduce the depth difference between the first word line conductive layer and the active layer in the substrate, so that the process steps of the first through hole and the second through hole can be integrated, thereby reducing production costs.
  • FIGS. 1 to 20 an embodiment of the present disclosure provides a method of manufacturing a semiconductor structure. It should be noted that, in order to facilitate description and clearly illustrate the steps of the method of manufacturing a semiconductor structure, FIGS. 1 to 20 are all Schematic diagram of the partial structure of a semiconductor structure. The manufacturing method of the semiconductor structure will be described in detail below with reference to the accompanying drawings.
  • Figure 1 shows the array area of the finally formed semiconductor structure.
  • the semiconductor structure includes a first direction X and a second direction Y.
  • the first direction X is the extension direction of the word line 2
  • the second direction Y is The arrangement direction of the word lines 2 is a direction perpendicular to the sidewalls of the word line trenches 4 (refer to FIG. 2).
  • the first direction X and the second direction Y are perpendicular to each other and parallel to the surface of the substrate 1 .
  • Figure 2 is a cross-sectional view of the semiconductor structure in the A-A1 direction shown in Figure 1.
  • a substrate 1 is provided, and a word line trench 4 is formed in the substrate 1 in the array area.
  • the substrate 1 of the array area includes: a first insulating structure 12, a second insulating structure 13 and a plurality of mutually separated active areas 11.
  • the first insulating structure 12 may be silicon nitride
  • the second insulating structure 13 may be silicon oxide.
  • the material of the active region 11 may be silicon or germanium.
  • the active region 11 may include a source-drain region 111 and a channel region 112.
  • the source-drain region 111 is located above the channel region 112, and the source-drain region 111 is located on both sides of the top of the word line trench 4.
  • the channel region 112 is located above the word line trench 4. below the line trench 4 and on both sides of the bottom of the word line trench 4.
  • the source-drain region 111 includes a source electrode and a drain electrode, and the source electrode and the drain electrode are located on different sides of the word line trench 4 respectively.
  • the source-drain region 111 and the channel region 112 may have opposite types of doping ions.
  • the channel region 112 may have P-type doping ions
  • the source-drain region 111 may have N-type doping ions.
  • the method of forming the word line trench 4 in the substrate 1 includes using a dry etching process to remove part of the first insulating structure 12 and part of the active region 11 .
  • the word line trenches 4 extend in the first direction X; there are multiple word line trenches 4 , and the plurality of word line trenches 4 are arranged in the second direction Y.
  • the first direction X part of the word line trench 4 is buried in the first insulation structure 12
  • part of the word line trench 4 is buried in the active area 11 .
  • the depth of the word line trench 4 buried in the active region 11 is smaller than the depth of the word line trench 4 buried in the first insulation structure 12 .
  • a dielectric layer 3 is formed in the word line trench 4 .
  • an atomic layer deposition process, an in-situ water vapor generation process, or other methods can be used to form a conformally covered high dielectric layer on the inner wall of the word line trench 4 .
  • the dielectric constant material is used as the dielectric layer 3.
  • the high dielectric constant material can reduce the gate leakage current.
  • the high dielectric constant material can be zirconium oxide, aluminum oxide, silicon oxide, silicon nitride, hafnium oxide or niobium oxide.
  • a first barrier layer 21 is formed in the word line trench 4 , and the first barrier layer 21 also covers the surface of the dielectric layer 3 .
  • the material of the first barrier layer 21 may include metal nitride, such as titanium nitride, titanium nitride or tungsten nitride.
  • the first barrier layer 21 can block the diffusion of metal atoms in the subsequently formed first word line conductive layer 22 into the dielectric layer 3 , thereby improving the reliability of the semiconductor structure.
  • the first barrier layer 21 may have a higher work function; accordingly, the doping dose of the channel region 112 may be reduced, thereby reducing the junction leakage current, thereby improving the retention time of the DRAM. .
  • an initial first word line conductive layer 220 is formed in the word line trench 4 .
  • a chemical vapor deposition process is used to form the initial first word line conductive layer 220 that fills the word line trench 4 .
  • a first etching process is performed so that the upper surface of the initial first word line conductive layer 220 is lower than the upper surface of the substrate 1 , that is, the height of the initial first word line conductive layer 220 in the word line trench 4 is reduced.
  • the initial first word line conductive layer 220 after the first etching process has a relatively flat top surface.
  • the top surface of the initial first word line conductive layer 220 after the first etching process may be higher than the bottom surface of the source and drain regions 111 .
  • the material of the initial first word line conductive layer 220 may be a low-resistance metal, such as tungsten and titanium. Low-resistance metals can increase the operating speed of semiconductor structures and reduce power consumption.
  • a second etching process is performed to form the top of the initial first word line conductive layer 220 as the protruding portion 22 a, and the remaining initial first word line conductive layer 220 serves as the first word line conductive layer 22 .
  • the protruding portion 22a can be used to increase the height of the first word line conductive layer 22, and can also be used to increase the volume of the first word line conductive layer 22, thereby reducing the resistance of the first word line conductive layer 22; and the protruding portion 22a
  • the sidewalls can provide spatial locations for the subsequently formed second word line conductive layer 24 .
  • the top end of the protruding part 22a may be higher than the bottom surface of the source and drain region 111, and the bottom end of the protruding part 22a may be flush with or lower than the bottom surface of the source and drain region 111.
  • the initial first word line conductive layer 220 has opposite sides arranged in the second direction Y, and the initial first word line conductive layer 220 located on the opposite sides is etched, so that in the middle position of the word line trench 4 A protruding portion 22 a protruding upward is formed, that is, the top end of the protruding portion 22 a is spaced apart from the sidewalls of the word line trench 4 .
  • the etching width on the opposite sides may be the same, that is, the distance between the top of the protrusion 22 a and the two opposite side walls of the word line trench 4 is the same. In this way, it is beneficial to improve the uniformity of the semiconductor structure and make the manufacturing process simpler.
  • the initial first word line conductive layer 220 on the side close to the word line trench 4 is etched, that is, the top of the protrusion 22 a is in contact with the word line trench 4 .
  • the protruding portion 22 a is in contact with one side of the word line trench 4 and is spaced apart from the other side of the word line trench 4 .
  • the protruding portion 22a may be in contact with the side of the word line trench 4 close to the source electrode, and be spaced apart from the side of the word line trench 4 close to the drain electrode.
  • the extending direction of the protruding portion 22 a is the same as the extending direction of the word line trench 4 and is parallel to the upper surface of the substrate 1 , and the lengths of the protruding portion 22 a and the word line trench 4 in the extending direction are the same. That is to say, by etching one or both sides of the entire initial first word line conductive layer 220 along the first direction X, the elongated protruding portion 22 a can be formed. In this way, there is no need to form a separate mask, and the production process can be simplified.
  • the protruding portion 22 a can also be in the shape of a block and is located at the edge of the active area 11 adjacent to the word line 2 .
  • the protruding portion 22 a may be disposed opposite the source and drain regions 111 , and the first word line conductive layer 22 below the protruding portion 22 a may be disposed opposite the channel region 112 .
  • the first word line conductive layer 22 may have a high work function, thereby increasing the work function difference between the first word line conductive layer 22 and the channel region 112 .
  • This work function difference can form an electric field between the first word line conductive layer 22 and the channel region 112.
  • This electric field can enhance the effect of the word line threshold voltage, that is, improve the utilization of the word line voltage. In other words, this electric field can make the word line threshold voltage lower, thereby reducing power consumption.
  • the protruding portion 22a can reduce the overlapping area of the first word line conductive layer 22 and the source and drain regions 111, thereby reducing the gate-induced drain leakage current (GIDL, gate) caused by the high work function of the first word line conductive layer 22. -induced drain leakage).
  • GIDL gate-induced drain leakage current
  • the thickness of the protruding portion 22a in the direction perpendicular to the upper surface of the substrate 1 is greater than 20 nm.
  • the thickness of the protruding portion 22 a is within the above range, the height of the first word line conductive layer 22 can be greatly increased to reduce the height difference between the first word line conductive layer 22 and the active layer 14 in the peripheral area.
  • the thickness of the protruding portion 22 a may be less than 40 nm, thereby ensuring that the first word line conductive layer 22 has a larger volume while reducing the overlapping area of the first word line conductive layer 22 and the source and drain regions 111 .
  • the top surface of the protruding portion 22 a is a curved surface.
  • the arc surface may have a smaller curvature, that is, the flatness of the top surface may be increased to increase the top surface area of the protruding portion 22 a exposed by the second through hole 72 formed subsequently.
  • the top surface of protrusion 22a is planar. That is, the top surface of the protruding portion 22a may have a uniform height, which can facilitate the subsequent formation of the second through hole 72 to expose the entire top surface of the protruding portion 22a, thereby increasing the distance between the subsequently formed second contact structure 82 and the first
  • the contact area of the word line conductive layer 22 is to reduce the contact resistance.
  • a second barrier layer 23 with conformal coverage is formed on the top surface of the first word line conductive layer 22 .
  • the second barrier layer 23 can prevent the metal atoms of the first word line conductive layer 22 from diffusing toward the subsequently formed second word line conductive layer 24, thereby improving the performance of the semiconductor structure.
  • a material such as tungsten nitride, titanium nitride or oxide is deposited on the top surface of the first word line conductive layer 22 as the second barrier layer 23; alternatively, nitrogen ion implantation can be directly performed on the top surface of the first conductive layer 22.
  • the second barrier layer 23 is formed.
  • a second word line conductive layer 24 is formed on the first word line conductive layer 22 , and the second word line conductive layer 24 at least covers part of the second barrier layer 23 .
  • a chemical vapor deposition process is used to deposit polysilicon on the first word line conductive layer 22 as the initial second word line conductive layer 24, and the initial second word line conductive layer 24 fills the word line trench 4; for the initial second word line conductive layer 24, The word line conductive layer 24 is etched back so that the upper surface of the initial second word line conductive layer 24 is lower than the upper surface of the substrate 1 , and the remaining initial second word line conductive layer 24 serves as the second word line conductive layer 24 .
  • the polysilicon may have doped ions to reduce the resistance of the second word line conductive layer 24 and reduce the contact resistance between the second word line conductive layer 24 and the first word line conductive layer 22 .
  • polysilicon may have N-type doping ions in it.
  • the work function of the second word line conductive layer 24 is smaller than the work function of the first word line conductive layer 22 .
  • the work function of the second word line conductive layer 24 may also be smaller than the first barrier layer 21 and the first barrier layer 21 .
  • the second word line conductive layer 24 and the source/drain region 111 have an overlapping area in the direction perpendicular to the surface of the substrate 1 .
  • the lower work function of the second word line conductive layer 24 can reduce the gate-induced drain leakage current, thereby avoiding affecting the DRAM.
  • the retention time (Retention Time) and the write recovery time (Write Recovery Time) are improved, thereby improving the performance of the semiconductor structure.
  • the top surface of the second word line conductive layer 24 may be higher than the top surface of the protruding portion 22 a.
  • the top surface of the second word line conductive layer 24 may be flush with the top surface of the protruding portion 22 a.
  • the top surface of the second word line conductive layer 24 may be lower than the top surface of the protrusion 22 a. That is, as long as the second word line conductive layer 24 can be located at least on the sidewall of the protruding portion 22a. That is, the second word line conductive layer 24 is located between the protruding portion 22 a and the sidewall of the word line trench 4 .
  • the second word line conductive layer 24 , the first word line conductive layer 22 , the first barrier layer 21 and the second barrier layer 23 together constitute the word line 2 .
  • the word line 2 is a buried word line 2, and the word line 2, the dielectric layer 3 and the active area 11 constitute a non-planar transistor.
  • the first barrier layer 21 and the second barrier layer 23 may not be formed. Therefore, the first word line conductive layer 22 and the second word line conductive layer 24 may constitute the word line 2 .
  • the thickness of the second barrier layer 23 and the first barrier layer 21 may be less than the thickness of the first word line conductive layer 22 in the direction perpendicular to the sidewalls of the word line trench 4, so that the thickness of the first word line can be
  • the conductive layer 22 provides more space to reduce the overall resistance of the word line 2 .
  • the word line 2 can be formed in the word line trench 4.
  • the word line 2 includes a stacked first word line conductive layer 22 and a second word line conductive layer 24;
  • the top of the first word line conductive layer 22 has a protruding portion 22 a , and the protruding portion 22 a protrudes in a direction from the first word line conductive layer 22 to the second word line conductive layer 24 .
  • Figures 10 and 11 both show the array area, and Figure 10 is a schematic cross-sectional view in the A-A1 direction shown in Figure 1, and Figure 11 is a schematic cross-sectional view in the B-B1 direction shown in Figure 1.
  • Figure 12 is a schematic cross-sectional view of the peripheral area. Referring to Figures 10-12, an isolation layer 5 covering the substrate 1 is formed. The isolation layer 5 in the array area also fills the word line trench 4 and covers the word line 2; the isolation layer 5 in the peripheral area covers the active layer 14. The isolation layer 5 can protect the word line 2 and the active layer 14 .
  • the isolation layer 5 in the array area may have a single-layer structure.
  • the isolation layer 5 in the array area may be silicon nitride or silicon oxynitride.
  • the isolation layer 5 in the peripheral area may include a first isolation layer 51 , a second isolation layer 52 and a third isolation layer 53 arranged in a stack.
  • the first isolation layer 51 and the third isolation layer 53 are made of the same material, and are different from the second isolation layer 52 .
  • the material of the first isolation layer 51 and the third isolation layer 53 may be silicon nitride
  • the material of the second isolation layer 51 may be silicon oxide.
  • the isolation layer 5 in the array area and the peripheral area may both have a single-layer structure or both have a multi-layer structure, which is beneficial to simplifying the production process.
  • the process before forming the isolation layer 5 , the process further includes: forming a gate structure 6 on the active layer 14 ; and the isolation layer 5 covers the gate structure 6 .
  • the active layer 14 and the gate structure 6 may constitute a transistor.
  • Figure 13 is a schematic cross-sectional view of the semiconductor structure in the B-B1 direction shown in Figure 1.
  • Figure 14 shows a partial top perspective view of the array area, and Figure 14 only shows the first word line conductive layer 22, the light Resist layer 73 and second through hole 72;
  • Figure 15 is a schematic cross-sectional view of the peripheral area; with reference to Figures 13-15, the first through hole 71 and the second through hole 72 are formed simultaneously through the isolation layer 5.
  • the first through hole 71 exposes the active layer 14, and the second through hole 72 exposes the protruding portion 22a.
  • a photoresist layer 73 is formed on the isolation layer 5, and the photoresist layer 73 is subjected to photolithography processing to simultaneously form a first opening and a second opening, the first opening is located in the peripheral area, and the second opening is located in the array area. .
  • the first through hole 71 is directly opposite to the first opening formed subsequently, and the second through hole 72 is directly opposite to the second opening. That is, the positions of the first through hole 71 and the second through hole 72 can be defined simultaneously through one photolithography process, without the need to use two photolithography processes to respectively define the positions of the first through hole 71 and the second through hole 72.
  • the isolation layer 5 is simultaneously etched along the first opening and the second opening to form the first through hole 71 and the second through hole 72 .
  • the protruding portion 22 a can increase the height of the first word line conductive layer 22 , thereby reducing the height difference between the top surface of the first word line conductive layer 22 and the top surface of the active layer 14 in the peripheral area.
  • the burial depths of the first word line conductive layer 22 and the active layer 14 in the substrate 1 are closer, so that an etching process can be used to simultaneously etch the isolation layer 5 in the peripheral area and the array area to simultaneously form the first Through hole 71 and second through hole 72, and an etching process can make the first through hole 71 and second through hole 72 reach a preset depth, thereby avoiding over-etching of the active layer 14 or failure to expose the third through hole.
  • a problem with the word line conductive layer 22 Therefore, there is no need to use two etching processes to etch the isolation layer 5 in the peripheral area and the array area respectively, which is beneficial to simplifying the process steps and reducing production costs.
  • the top surface of the second word line conductive layer 24 is flush with or higher than the top surface of the protruding portion 22 a, part of the second word line conductive layer needs to be removed during the formation of the second through hole 72 layer 24, thereby exposing the protruding portion 22a, so that the subsequently formed second contact structure 82 can be directly electrically connected to the second word line conductive layer 24; if the top surface of the second conductive layer 24 is lower than the top of the protruding portion 22a surface, the isolation layer 5 located on the top surface of the protrusion 22a can be directly removed without removing the second word line conductive layer 24.
  • part of the top end of the protruding portion 22 a may be removed during the formation of the second through hole 72 .
  • the top surface of the protruding portion 22a is arc-shaped, the top surface of the protruding portion 22a can be transformed from an arc surface to a flat surface after the etching process.
  • selective etching may be performed to retain the entire protruding portion 22a, that is, the top surface of the protruding portion 22a remains an arc surface. This will be described in detail later in conjunction with the positional relationship between the protruding portion 22a and the second contact structure 82.
  • the second through hole 72 may be located at an edge of the array area.
  • the second through hole 72 has a first width L1 in the extending direction of the word line trench 4 , that is, the first width L1 is the width in the first direction X.
  • the second through hole 72 has a second width L2 in a direction perpendicular to the sidewall of the word line trench 4, that is, the second width is the width in the second direction Y, and the first width L1 is greater than the second width L2. It should be noted that in the second direction Y, the top end of the protruding portion 22 a only occupies part of the spatial position of the word line trench 4 .
  • the contact width between the first word line conductive layer 22 and the subsequently formed second contact structure 82 in the second direction Y is small. Therefore, the first word line conductive layer 22 and the second contact structure 82 can be appropriately increased.
  • the contact width in the first direction X is to increase the width of the second through hole 72 in the first direction X, thereby increasing the contact area between the first word line conductor layer 22 and the second contact structure 82 .
  • the difference between the first width L1 and the second width L2 is greater than 10 nm.
  • the difference in width between the two is maintained within the above range, it is beneficial for the subsequently formed second contact structure 82 and the first word line conductive layer 22 to obtain a suitable contact area, thereby reducing the contact resistance.
  • the difference between the first width L1 and the second width L2 may be less than 50 nm to prevent the second contact structure 82 from occupying the spatial position of other structures in the first direction X.
  • the width of the second through hole 72 is greater than or equal to the width of the protruding portion 22a. That is, the top surface area of the protruding portion 22a exposed by the second through hole 72 is increased in the second direction Y, thereby increasing the contact area between the subsequently formed second contact structure 82 and the protruding portion 22a; in addition, It is beneficial to increase the volume of the second contact structure 82 to reduce the resistance of the second contact structure 82 .
  • the second width L2 of the second through hole 72 may also be equal to the width of the word line trench 4 , that is, the second through hole 72 exposes the sidewalls of the word line trench 4 , so that the second contact structure 82 is in the third
  • the width in the two directions Y is equal to the width of the word line trench 4 .
  • first through holes 71 there are at least two first through holes 71 , and two of the first through holes 71 are located on both sides of the gate structure 6 . That is, the first through hole 71 can expose the source and drain electrodes on both sides of the gate structure 6 .
  • the manufacturing method further includes: forming a first contact structure 81 filling the first through hole 71 and a second contact structure 82 filling the second through hole 72 , the first contact structure 81 being connected to the active layer 14 , the second contact structure 82 is connected to the word line 2 . That is, the first contact structure 81 can lead out the active layer 14 in the substrate 1 , and the second contact structure 82 can lead out the word line 2 in the substrate 1 .
  • an initial contact structure is formed in the first through hole 71 and the second through hole 72 and on the surface of the isolation layer 5, and the initial contact structure is planarized to remove the initial contact structure located on the surface of the isolation layer 5.
  • the remaining initial contact structure in one through hole 71 serves as the first contact structure 81
  • the remaining initial contact structure in the second through hole 72 serves as the second contact structure 82 .
  • the material of the initial contact structure may be low-resistance metal such as copper, tungsten, titanium, etc.
  • the material of the initial contact structure may also be the same as the material of the first word line conductive layer 22 .
  • the second contact structure 82 is directly connected to both the first word line conductive layer 22 and the second word line conductive layer 24 .
  • the reason why the second contact structure 82 is not indirectly electrically connected to the first word line conductive layer 22 through the second word line conductive layer 24 is that the resistance of the first word line conductive layer 22 is less than the resistance of the second word line conductive layer 24.
  • the work function of the first word line conductive layer 22 is greater than the work function of the second word line conductive layer 24.
  • the second contact structure 82 is directly connected to the first word line conductive layer 22, which can reduce the contact resistance and strengthen the first word line conductive layer. 22 and the channel region 112, thereby improving the gate control capability.
  • Figures 17-19 show several different positional relationships between the second contact structure 82 and the protruding portion 22a. Specifically, referring to FIGS. 17 and 18 , the protruding portion 22 a is in direct contact with the second contact structure 82 , and the second barrier layer 23 between the two has been removed during the process of forming the second through hole 72 , thereby facilitating Reduce the contact resistance between the two.
  • the protruding portion 22 a is in planar contact with the second contact structure 82 . In other words, part of the top end of the protruding portion 22 a can be removed during the process of forming the second through hole 72 .
  • the protruding portion 22 a is in arcuate contact with the second contact structure 82 , which is beneficial to increasing the contact area between the two and reducing the contact resistance. That is to say, in the process of forming the second through hole 72, an etchant with a high selectivity ratio is used, so that the protruding portion 22a is not etched.
  • the protruding portion 22a and the second contact structure 82 also have a second barrier layer 23.
  • the protruding portion 22a and the second contact structure 82 are in arc surface contact, and the contact area is large. Contact resistance is low.
  • each word line 2 is connected to a second contact structure 82 , and the second contact structures 82 connected to adjacent word lines 2 may be arranged in a staggered manner. That is, the word line 2 has two opposite ends in the first direction X, and the second contact structures 82 connected to adjacent word lines 2 are located at different ends of the word line 2 . Therefore, a word line 2 can be spaced between adjacent second contact structures 82 at the same end, thereby increasing the spacing between adjacent second contact structures 82 and thereby reducing the parasitic capacitance between adjacent second contact structures 82 , to increase the operating speed of semiconductor structures.
  • adjacent second contact structures 82 at the same end may be staggered from each other, that is, they are not in a direct relationship in the second direction Y. It can be understood that the smaller the facing area, the smaller the parasitic capacitance. In this way, the width of the second contact structure 82 in the first direction X can be appropriately increased, thereby increasing the contact area between the second contact structure 82 and the first word line conductive layer 22 . That is to say, even if the width of the second contact structure 82 in the first direction No large parasitic capacitance is generated between the structures 82 .
  • the protruding portion 22a is formed on the top of the first word line conductive layer 22 to increase the height of the top surface of the first word line conductive layer 22, thereby reducing the height of the first word line conductive layer 22.
  • the height difference between the top surface and the top surface of the peripheral area In this way, it is convenient to subsequently form the first through hole 71 and the second through hole 72 at the same time, thereby simplifying the production process and reducing the production cost.
  • the protruding portion 22a can reduce the overlapping area of the first word line conductive layer 22 and the source-drain region 111, thereby reducing the gate-induced drain leakage current, thereby preventing the leakage current from adversely affecting the storage time and write recovery time of the DRAM. .
  • embodiments of the present disclosure also provide a semiconductor structure, which can be manufactured using the manufacturing method provided in the foregoing embodiments.
  • a semiconductor structure which can be manufactured using the manufacturing method provided in the foregoing embodiments.
  • the semiconductor structure includes a peripheral area and an array area.
  • the semiconductor structure includes: a substrate 1.
  • the substrate 1 in the peripheral area has an active layer 14; a word line 2 is formed in the substrate 1 in the array area.
  • the word line 2 includes a stacked first word.
  • the line conductive layer 22 and the second word line conductive layer 24; the top of the first word line conductive layer 22 has a protruding portion 22a, and the protruding portion 22a points along the first word line conductive layer 22 to the second word line conductive layer 24.
  • the direction protrudes; the isolation layer 5 covering the substrate 1 is formed with a first contact structure 81 and a second contact structure 82 in the isolation layer 5.
  • the first contact structure 81 is connected to the active layer 14, and the second contact structure 82 is connected to the word line. 2 connected.
  • the protruding portion 22 a can reduce the height difference between the top surface of the first word line conductive layer 22 and the top surface of the active layer 14 in the peripheral area, thereby facilitating the simultaneous formation of the first contact structure 81 and the second contact structure 82 .
  • the second contact structure 82 may be in contact with the word line trench 4 , that is, in the second direction Y, the width of the second contact structure 82 may be equal to the width of the word line trench 4 . In this way, it is beneficial to increase the volume of the second contact structure 82 and reduce the resistance of the second contact structure 82.
  • the projected area of the second word line conductive layer 24 on the substrate 1 is located on the protruding portion 22 a on the substrate 1 On both sides of the projection area; the second contact structure 82 is in contact with both the first word line conductive layer 22 and the second word line conductive layer 24 . That is, both sides of the top of the protruding portion 22 a are spaced apart from the word line trench 4 , and the second word line conductive layer 24 may be located in the gap between both sides of the protruding portion 22 a and the word line trench 4 .

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Abstract

本公开实施例涉及半导体领域，提供一种半导体结构的制造方法和半导体结构，所述半导体结构包括外围区和阵列区，制造方法包括：提供基底，所述外围区的基底内具有有源层；在所述阵列区的所述基底内形成字线沟槽；在所述字线沟槽中字线，所述字线包括层叠设置的第一字线导电层和第二字线导电层；所述第一字线导电层的顶部具有凸出部，且所述凸出部沿所述第一字线导电层指向所述第二字线导电层的方向凸出；形成覆盖所述基底的隔离层；同时形成贯穿所述隔离层的第一通孔和第二通孔，所述第一通孔露出所述有源层，所述第二通孔露出所述凸出部。本公开实施例至少可以简化生产工艺。

Description

半导体结构和半导体结构的制造方法
交叉引用
本申请引用于2022年7月28日递交的名称为“半导体结构和半导体结构的制造方法”的第202210900085.3号中国专利申请，其通过引用被全部并入本申请。
技术领域
本公开属于半导体领域，具体涉及一种半导体结构的制造方法和半导体结构。
背景技术
半导体结构中的动态随机存取存储器(Dynamic Random Access Memory，简称DRAM)是一种广泛应用于计算机系统的半导体存储器。DRAM的主要作用原理是利用电容内存储电荷的多寡来代表一个其存储的二进制比特(bit)是1还是0。DRAM包括阵列区和外围区，阵列区内具有存储单元，外围区内具有外围电路，外围电路能够控制存储单元的读写过程。
然而，形成DRAM的工艺步骤较多，生产成本较高。
发明内容
本公开实施例提供一种半导体结构的制造方法和半导体结构，至少有利于简化半导体结构的工艺步骤，从而降低生产成本。
根据本公开一些实施例，本公开实施例一方面提供一种半导体结构的制造方法，其中，半导体结构的制造方法包括：提供基底，所述外围区的基底内具有有源层；在所述阵列区的所述基底内形成字线沟槽；在所述字线沟槽中字线，所述字线包括层叠设置的第一字线导电层和第二字线导电层；所述第一字线导电层的顶部具有凸出部，且所述凸出部沿所述第一字线导电层指向所述第二字线导电层的方向凸出；形成覆盖所述基底的隔离层；同时形成贯穿所述隔离层的第一通孔和第二通孔，所述第一通孔露出所述有源层，所述第二通孔露出所述凸出部。
根据本公开一些实施例，本公开实施例另一方面提供一种半导体结构，所述半导体结构包括：基底，所述外围区的基底内具有有源层；所述阵列区的基底内形成有字线，所述字线包括层叠设置的第一字线导电层和第二字线导电层；所述第一字线导电层的顶部具有凸出部，且所述凸出部沿所述第一字线导电层指向所述第二字线导电层的方向凸出；覆盖所述基底的隔离层，所述隔离层中形成有第一接触结构以及第二接触结构，所述第一接触结构所述有源层相连，所述第二接触结构与所述字线相连。
本公开实施例提供的技术方案至少具有以下优点：在第一字线导电层的顶部形成向上凸出的凸出部，凸出部可以减小第一字线导电层的顶面与有源层的顶面在基底内的高度差，从而能够集成第一通孔和第二通孔的工艺步骤，进而降低生产成本。
附图说明
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合本公开的实施例，并与说明书一起用于解释本公开的原理。显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1示出了本公开一实施例提供的半导体结构的阵列区的俯视示意图；
图2-图20示出了本公开一实施例提供的半导体结构的制造方法中各步骤对应的结构示意图。
具体实施方式
DRAM的工艺步骤较多，生产成本较高。经分析发现，主要原因在于：DRAM的外围区内需要形成第一通孔，以露出有源层并形成接触结构；DRAM的阵列区内需要形成第二通孔，以露出第一字线导电层并形成接触结构。然而，相比于有源层，第一字线导电层在基底内的深度更深。若同时形成第一通孔和第二通孔，则会对有源层造成过刻蚀，或者无法露出第一字线导电层，从而降低半导体结构的性能。因此，第一通孔和第二通孔通常在不同的工艺步骤中形成，生产成本较高。
本公开实施例提供一种半导体结构的制造方法，包括：在第一字线导电层的顶部形成凸出部，刻蚀隔离层以形成露出凸出部的第二通孔。即，凸出部向上凸出，可以减小第一字线导电层与有源层在基底内的深度差，从而能够集成第一通孔和第二通孔的工艺步骤，进而降低生产成本。
下面将结合附图对本公开的各实施例进行详细的阐述。然而，本领域 的普通技术人员可以理解，在本公开各实施例中，为了使读者更好地理解本公开实施例而提出了许多技术细节。但是，即使没有这些技术细节和基于以下各实施例的种种变化和修改，也可以实现本公开实施例所要求保护的技术方案。
如图1-图20所示，本公开一实施例提供一种半导体结构的制造方法，需要说明的是，为了便于描述以及清晰地示意出半导体结构制作方法的步骤，图1至图20均为半导体结构的局部结构示意图。以下将结合附图对半导体结构的制造方法进行详细说明。
图1示出了最终形成的半导体结构的阵列区，参考图1，半导体结构结构内包括第一方向X和第二方向Y，第一方向X为字线2的延伸方向，第二方向Y为字线2的排列方向，即垂直于字线沟槽4(参考图2)侧壁的方向。第一方向X与第二方向Y垂直，且二者平行于基底1表面。
图2为半导体结构在图1所示的A-A1方向上的剖面图，参考图2，提供基底1，在阵列区的基底1内形成字线沟槽4。具体地，阵列区的基底1包括：第一绝缘结构12、第二绝缘结构13和多个相互分立的有源区11。示例地，第一绝缘结构12可以为氮化硅，第二绝缘结构13可以为氧化硅。有源区11的材料可以为硅或锗。有源区11可以包括源漏区111和沟道区112，源漏区111位于沟道区112的上方，且源漏区111位于字线沟槽4顶部的两侧，沟道区112位于字线沟槽4的下方以及字线沟槽4底部的两侧。源漏区111包括源极和漏极，且源极和漏极分别位于字线沟槽4的不同侧。源漏区111和沟道区112中可以具有相反类型的掺杂离子，比如，沟道区112内具有P型掺杂离子，源漏区111内具有N型掺杂离子。
在基底1中形成字线沟槽4的方法包括：采用干法刻蚀工艺去除部分第一绝缘结构12和部分有源区11。示例地，结合参考图1-图2，字线沟槽4在第一方向X上延伸；字线沟槽4为多个，且多个字线沟槽4在第二方向Y排列。在第一方向X上，部分字线沟槽4埋入第一绝缘结构12内，部分字线沟槽4埋入有源区11内。埋入有源区11内的字线沟槽4的深度，小于埋入第一绝缘结构12内的字线沟槽4的深度。
继续参考图2，在字线沟槽4中形成介质层3，示例地，可以采用原子层沉积工艺、原位水汽生成工艺等方法在字线沟槽4的内壁上形成保形覆盖的高介电常数材料以作为介质层3，高介电常数材料能够降低栅极漏电流，高介电常数材料可以为氧化锆、氧化铝、氧化硅、氮化硅、氧化铪或氧化铌等。
参考图3，在字线沟槽4中形成第一阻挡层21，第一阻挡层21还覆盖介质层3的表面。示例地，第一阻挡层21的材料可以包括金属氮化物，比如氮化钛、氮化坦或氮化钨。第一阻挡层21能够阻挡后续形成的第一字线导电层22中的金属原子扩散至介质层3中，从而提高半导体结构的可靠性。
在一些实施例中，第一阻挡层21可以具有较高的功函数；相应地， 可以减少沟道区112的掺杂剂量，从而可以降低结泄漏电流，进而提高DRAM的保存时间(retention time)。
继续参考图3，在字线沟槽4中形成初始第一字线导电层220。示例地，采用化学气相沉积工艺形成填充满字线沟槽4的初始第一字线导电层220。此后，进行第一刻蚀处理，以使初始第一字线导电层220的上表面低于基底1的上表面，即降低初始第一字线导电层220在字线沟槽4中的高度。第一刻蚀处理后的初始第一字线导电层220具有相对平坦的顶面。示例地，第一刻蚀处理后的初始第一字线导电层220的顶面可以高于源漏区111的底面。
示例地，初始第一字线导电层220的材料可以为低电阻金属，比如钨、钛。低电阻金属可以提高半导体结构的运行速率，并且降低功耗。
参考图4-图5，第二刻蚀处理，以将初始第一字线导电层220的顶部形成为凸出部22a，剩余的初始第一字线导电层220作为第一字线导电层22。凸出部22a能够用于增加第一字线导电层22的高度，还能够用于增加第一字线导电层22的体积，从而降低第一字线导电层22的电阻；且凸出部22a的侧壁周围能够为后续形成的第二字线导电层24提供空间位置。凸出部22a的顶端可以高于源漏区111的底面，凸出部22a的底端可以平齐于或低于源漏区111的底面。
示例地，初始第一字线导电层220具有在第二方向Y上排列的相对两侧，刻蚀位于相对两侧的初始第一字线导电层220，从而在字线沟槽4的中间位置形成了朝上凸出的凸出部22a，即凸出部22a的顶端与字线沟槽4的侧壁间隔设置。此外，相对两侧的刻蚀宽度可以相同，也就是说，凸出部22a的顶端与字线沟槽4相对的两个侧壁的距离相同。如此，有利于提高半导体结构的均一性，并且制造工艺更为简单。
在另一些实施例中，参考图5，刻蚀靠近字线沟槽4一侧的初始第一字线导电层220，即，凸出部22a的顶端与字线沟槽4相接触。换言之，凸出部22a与字线沟槽4的一侧相接触，并与字线沟槽4的另一侧相间隔。举例而言，凸出部22a可以与字线沟槽4靠近源极的一侧相接触，并与字线沟槽4靠近漏极的一侧相间隔。
需要说明的是，凸出部22a的延伸方向与字线沟槽4的延伸方向相同且平行于基底1的上表面，且凸出部22a和字线沟槽4在延伸方向上的长度相同。也就是说，沿着第一方向X刻蚀整条初始第一字线导电层220的一侧或两侧，可以形成长条状的凸出部22a。如此，无需形成单独的掩膜，可以简化生产工艺。在另一些实施例中，凸出部22a还可以为块状，且位于有源区11与字线2相邻的边缘位置。
参考图4-图5，凸出部22a可以与源漏区111相对设置，凸出部22a以下的第一字线导电层22可以与沟道区112相对设置。需要说明的是，第一字线导电层22可以具有高功函数，从而增大第一字线导电层22与沟道区112的功函数差。此功函数差能够在第一字线导电层22与沟道区112之间形 成一个电场，该电场可以增强字线阈值电压的作用，即提高字线电压的利用率。换言之，该电场可以让字线阈值电压更低，从而降低功耗。此外，凸出部22a可以减小第一字线导电层22与源漏区111的重叠面积，从而降低第一字线导电层22的高功函数引起的栅诱导漏极泄漏电流(GIDL，gate-induced drain leakage)。
在第一字线导电层22指向第二字线导电层24的方向上，凸出部22a在垂直基底1的上表面方向上的厚度大于20nm。在凸出部22a的厚度处于上述范围时，能够较大程度地增加第一字线导电层22的高度，以降低第一字线导电层22与外围区的有源层14的高度差。在一些实施例中，凸出部22a的厚度可以小于40nm，从而能够在保证第一字线导电层22具有较大体积的同时，降低第一字线导电层22与源漏区111的重叠面积。
在一些实施例中，参考图4，凸出部22a的顶面为弧面。示例地，该弧面可以具有较小的弯曲弧度，即增加顶面的平整程度，以增大后续形成的第二通孔72露出的凸出部22a的顶面面积。
在一些实施例中，参考图5，凸出部22a的顶面为平面。即，凸出部22a的顶面可以具有均一的高度，从而能够便于后续形成的第二通孔72将整个凸出部22a的顶面露出，进而增加后续形成的第二接触结构82与第一字线导电层22的接触面积，以降低接触电阻。
参考图6，在第一字线导电层22顶面形成保形覆盖的第二阻挡层23。第二阻挡层23能够避免第一字线导电层22的金属原子朝向后续形成的第二字线导电层24扩散，从而提高半导体结构的性能。示例地，在第一字线导电层22顶面沉积氮化钨、氮化钛或氧化物等材料作为第二阻挡层23；或者，可以直接对第一导电层22的顶面进行氮离子注入从而形成第二阻挡层23。
参考图7-图9，在第一字线导电层22层上形成第二字线导电层24，第二字线导电层24至少覆盖部分第二阻挡层23。示例地，采用化学气相沉积工艺在第一字线导电层22上沉积多晶硅以作为初始第二字线导电层24，初始第二字线导电层24填充满字线沟槽4；对初始第二字线导电层24进行回刻，以使初始第二字线导电层24的上表面低于基底1的上表面，剩余的初始第二字线导电层24作为第二字线导电层24。多晶硅中可以具有掺杂离子以降低第二字线导电层24的电阻，且降低第二字线导电层24与第一字线导电层22的接触电阻。示例地，多晶硅中可以具有N型掺杂离子。
在一些实施例中，第二字线导电层24的功函数小于第一字线导电层22的功函数，此外，第二字线导电层24的功函数还可以小于第一阻挡层21和第二阻挡层23的功函数。第二字线导电层24与源漏区111在垂直于基底1表面的方向上具有重叠区，第二字线导电层24较低的功函数能够降低栅诱导漏极泄漏电流，从而避免影响DRAM的保存时间(Retention Time)和写恢复时间(Write Recovery Time)，进而提高半导体结构的性能。
具体地，参考图7，第二字线导电层24的顶面可以高于凸出部22a的顶面。参考图8，第二字线导电层24的顶面可以与凸出部22a的顶面齐平。 参考图9，第二字线导电层24的顶面可以低于凸出部22a的顶面。也就是说，只要能够使得第二字线导电层24至少位于凸出部22a的侧壁即可。即第二字线导电层24位于凸出部22a与字线沟槽4的侧壁之间。
需要说明的是，第二字线导电层24、第一字线导电层22、第一阻挡层21和第二阻挡层23共同构成字线2。字线2为埋入式字线2，字线2、介质层3和有源区11构成了非平面的晶体管。在另一些实施例中，也可以不形成第一阻挡层21和第二阻挡层23，因此，第一字线导电层22和第二字线导电层24可以构成字线2。
在一些实施例中，第二阻挡层23、第一阻挡层21的厚度可以小于第一字线导电层22在垂直字线沟槽4的侧壁方向上的厚度，从而可以为第一字线导电层22提供更多的空间，以降低字线2的总电阻。
至此，基于图2-图9所示的工艺步骤，可以在字线沟槽4中形成字线2，字线2包括层叠设置的第一字线导电层22和第二字线导电层24；第一字线导电层22的顶部具有凸出部22a，且凸出部22a沿第一字线导电层22指向第二字线导电层24的方向凸出。
图10和图11均示出了阵列区，且图10为图1所示的A-A1方向上的剖面示意图，图11为图1所示的B-B1方向上的剖面示意图。图12为外围区的剖面示意图，参考图10-图12，形成覆盖基底1的隔离层5。阵列区的隔离层5还填充在字线沟槽4中，并覆盖字线2；外围区的隔离层5覆盖有源层14。隔离层5能够保护字线2和有源层14。
具体地，参考图10和图11，阵列区的隔离层5可以为单层结构，比如，阵列区的隔离层5可以为氮化硅或氮氧化硅。参考图12，外围区的隔离层5可以包括层叠设置的第一隔离层51、第二隔离层52和第三隔离层53。第一隔离层51和第三隔离层53的材料相同，且与第二隔离层52的材料不同。示例地，第一隔离层51和第三隔离层53的材料可以为氮化硅，第二隔离层51的材料可以为氧化硅。在另一些实施例中，阵列区和外围区的隔离层5可以均为单层结构或均为多层结构，从而有利于简化生产工艺。
在一些实施例中，参考图12，在形成隔离层5前还包括：在有源层14上形成栅极结构6；隔离层5覆盖栅极结构6。换言之，有源层14与栅极结构6可以构成晶体管。
图13为半导体结构在图1所示的B-B1方向上的剖面示意图，图14示出了阵列区的局部俯向透视图，且图14仅示出了第一字线导电层22、光刻胶层73和第二通孔72；图15为外围区的剖面示意图；参考图13-图15，同时形成贯穿隔离层5的第一通孔71和第二通孔72，第一通孔71露出有源层14，第二通孔72露出凸出部22a。
具体地，在隔离层5上形成光刻胶层73，对光刻胶层73进行光刻处理，以同时形成第一开口和第二开口，第一开口位于外围区，第二开口位于阵列区。第一通孔71与后续形成的第一开口正对，第二通孔72与第二开口正对。即，可以通过一次光刻处理同时定义出第一通孔71和第二通孔72的 位置，而无需采用两次光刻处理分别定义第一通孔71和第二通孔72的位置。
继续参考图13-图15，同时沿第一开口和第二开口刻蚀隔离层5，以形成第一通孔71和第二通孔72。需要说明的是，凸出部22a能够增加第一字线导电层22的高度，从而使得第一字线导电层22的顶面与外围区的有源层14的顶面的高度差减小。即第一字线导电层22和有源层14在基底1内的埋入深度更为接近，从而可以采用一道刻蚀工艺同时刻蚀外围区和阵列区的隔离层5，以同时形成第一通孔71和第二通孔72，且一道刻蚀工艺可以使得第一通孔71和第二通孔72均达到预设的深度，而避免对有源层14造成过刻蚀或者无法露出第一字线导电层22的问题。因此，无需采用两道刻蚀工艺分别刻蚀外围区和阵列区的隔离层5，从而有利于简化工艺步骤，降低生产成本。
需要说明的是，若第二字线导电层24的顶面齐平于或高于凸出部22a的顶面，则在形成第二通孔72的过程中还需要去除部分第二字线导电层24，从而露出凸出部22a，以使得后续形成的第二接触结构82能够直接与第二字线导电层24电连接；若第二导电层24的顶面低于凸出部22a的顶面，可以直接去除位于凸出部22a顶面的隔离层5，而无需再去除第二字线导电层24。
此外，在形成第二通孔72的过程中还可以去除凸出部22a的部分顶端。换言之，若凸出部22a的顶面为弧形，经刻蚀工艺后，凸出部22a的顶面可以由弧面转变为平面。或者，也可以进行选择性刻蚀，而保留整个凸出部22a，即凸出部22a的顶面仍保持为弧面。后续将结合凸出部22a与第二接触结构82的位置关系对此进行详细说明。
参考图13-图14，第二通孔72可以位于阵列区的边缘位置。第二通孔72在字线沟槽4的延伸方向上具有第一宽度L1，即第一宽度L1为第一方向X上的宽度。第二通孔72在垂直于字线沟槽4侧壁的方向上具有第二宽度L2，即第二宽度为第二方向Y上的宽度，第一宽度L1大于第二宽度L2。需要说明的是，在第二方向Y上，凸出部22a的顶端只占据了字线沟槽4的部分空间位置。也就是说，第一字线导电层22与后续形成的第二接触结构82在第二方向Y上的接触宽度较小，因此，可以适当增加第一字线导电层22与第二接触结构82在第一方向X上的接触宽度，即增加第二通孔72在第一方向X上宽度，从而增大第一字线导线层22与第二接触结构82的接触面积。
示例地，第一宽度L1与第二宽度L2之差大于10nm。当二者宽度之差保持在上述范围时，有利于使得后续形成的第二接触结构82与第一字线导电层22获得合适的接触面积，从而降低接触电阻。此外，第一宽度L1与第二宽度L2之差还可以小于50nm，以避免第二接触结构82在第一方向X上挤占其他结构的空间位置。
在垂直于字线沟槽4侧壁的方向上，第二通孔72的宽度大于或等于凸出部22a的宽度。即，在第二方向Y上增大第二通孔72所暴露的凸出部22a的顶面面积，从而增大后续形成的第二接触结构82与凸出部22a的接触 面积；此外，还有利于增大第二接触结构82的体积，以降低第二接触结构82的电阻。举例而言，第二通孔72的第二宽度L2还可以等于字线沟槽4的宽度，即第二通孔72露出字线沟槽4的侧壁，从而使得第二接触结构82在第二方向Y上的宽度等于字线沟槽4的宽度。
参考图15，第一通孔71至少为两个，且其中两个第一通孔71位于栅极结构6的两侧。即第一通孔71可以露出栅极结构6两侧的源漏极。
参考图16-图20，制造方法还包括：形成填充第一通孔71的第一接触结构81以及填充第二通孔72的第二接触结构82，第一接触结构81与有源层14相连，第二接触结构82与字线2相连。即，第一接触结构81能够将基底1内的有源层14引出，第二接触结构82能够将基底1内的字线2引出。
示例地，在第一通孔71和第二通孔72中，以及隔离层5的表面形成初始接触结构，对初始接触结构进行平坦化处理，以去除位于隔离层5表面的初始接触结构，第一通孔71中剩余的初始接触结构作为第一接触结构81，第二通孔72中剩余的初始接触结构作为第二接触结构82。初始接触结构的材料可以为铜、钨、钛等低电阻金属，此外，初始接触结构的材料还可以与第一字线导电层22的材料相同。
在一些实施例中，参考图16-图19，第二接触结构82与第一字线导电层22和第二字线导电层24均直接相连。第二接触结构82不是通过第二字线导电层24与第一字线导电层22间接电连接的原因在于：第一字线导电层22的电阻小于第二字线导电层24的电阻，第一字线导电层22的功函数大于第二字线导电层24的功函数，第二接触结构82直接与第一字线导电层22相连可以降低接触电阻，且能够加强第一字线导电层22与沟道区112之间形成的电场，从而提高栅控能力。
图17-图19示出了第二接触结构82与凸出部22a几种不同的位置关系。具体地，参考图17-图18，凸出部22a与第二接触结构82直接接触，二者之间的第二阻挡层23在形成第二通孔72的过程中已经被去除，从而有利于降低二者的接触电阻。
参考图17，凸出部22a与第二接触结构82为平面接触，换言之，可以在形成第二通孔72的过程中去除凸出部22a的部分顶端。
参考图18，凸出部22a与第二接触结构82为弧面接触，从而有利于增大二者之间的接触面积，以降低接触电阻。也就是说，在形成第二通孔72的过程中，采用了高选择比的刻蚀剂，从而使得凸出部22a不被刻蚀。
在另一些实施例中，参考图19，凸出部22a与第二接触结构82还具有第二阻挡层23，此外，凸出部22a与第二接触结构82为弧面接触，接触面积大，接触电阻较低。
参考图1，每条字线2都与一个第二接触结构82相连，且与相邻字线2相连的第二接触结构82可以交错设置。即，字线2在第一方向X上具有相对的两端，与相邻字线2相连的第二接触结构82位于字线2的不同端。 因此，在同一端的相邻第二接触结构82之间可间隔一条字线2，从而增加了相邻第二接触结构82的间距，进而能够降低相邻第二接触结构82的之间的寄生电容，以提高半导体结构的运行速率。
此外，在同一端的相邻第二接触结构82可相互错开，即二者在第二方向Y上并不是正对关系。可以理解的是，正对面积越小，寄生电容越小。如此，可以适当增加第二接触结构82在第一方向X上的宽度，从而增加第二接触结构82与第一字线导电层22的接触面积。也就是说，即使第二接触结构82的在第一方向X上的宽度较大，但由于相邻第二接触结构82的间距较大，且正对面积较小，因此，相邻第二接触结构82之间不会产生较大的寄生电容。
综上所述，本公开实施例在第一字线导电层22的顶部形成凸出部22a，以增大第一字线导电层22顶面的高度，从而缩小第一字线导电层22的顶面与外围区的顶面的高度差。如此，便于后续在同时形成第一通孔71和第二通孔72，以简化生产工艺，降低生产成本。此外，凸出部22a能够减小第一字线导电层22与源漏区111的重叠面积，进而降低栅诱导漏极泄漏电流，从而避免泄露电流对DRAM的保存时间和写恢复时间产生不良影响。
如图16-图20所示，本公开实施例还提供一种半导体结构，该半导体结构可以采用前述实施例提供的制造方法进行制造。有关该半导体结构的详细说明可参考前述实施例。
半导体结构包括外围区和阵列区，半导体结构包括：基底1，外围区的基底1内具有有源层14；阵列区的基底1内形成有字线2，字线2包括层叠设置的第一字线导电层22和第二字线导电层24；第一字线导电层22的顶部具有凸出部22a，且凸出部22a沿第一字线导电层22指向第二字线导电层24的方向凸出；覆盖基底1的隔离层5，隔离层5中形成有第一接触结构81以及第二接触结构82，第一接触结构81与有源层14相连，第二接触结构82与字线2相连。
即，凸出部22a可以降低第一字线导电层22的顶面与外围区的有源层14的顶面的高度差，从而便于同时形成第一接触结构81和第二接触结构82。
示例地，第二接触结构82可以与字线沟槽4相接触，即在第二方向Y上，第二接触结构82的宽度可以等于字线沟槽4的宽度。如此，有利于 增大第二接触结构82的体积，降低第二接触结构82的电阻。
在一些实施例中，参考图17-图19，在第二接触结构82在基底1上的投影区域内，第二字线导电层24在基底1上的投影区域位于凸出部22a在基底1上的投影区域的两侧；第二接触结构82与第一字线导电层22及第二字线导电层24均接触。即，凸出部22a的顶端的两侧与字线沟槽4间隔设置，第二字线导电层24可以位于凸出部22a的两侧与字线沟槽4之间的间隙中。如此，有利于减小第二字线导电层24与源漏区111的接触面积，进而降低栅诱导漏极泄漏电流。在本说明书的描述中，参考术语“一些实施例”、“示例地”等的描述意指结合该实施例或示例描述的具体特征、结构、材料或者特点包含于本公开的至少一个实施例或示例中。在本说明书中，对上述术语的示意性表述不必须针对的是相同的实施例或示例。而且，描述的具体特征、结构、材料或者特点可以在任一个或多个实施例或示例中以合适的方式结合。此外，在不相互矛盾的情况下，本领域的技术人员可以将本说明书中描述的不同实施例或示例以及不同实施例或示例的特征进行结合和组合。
尽管上面已经示出和描述了本公开的实施例，可以理解的是，上述实施例是示例性的，不能理解为对本公开的限制，本领域的普通技术人员在本公开的范围内可以对上述实施例进行变化、修改、替换和变型，故但凡依本公开的权利要求和说明书所做的变化或修饰，皆应属于本公开专利涵盖的范围之内。

Claims (17)

  1. 一种半导体结构的制造方法，所述半导体结构包括外围区和阵列区，包括：
    提供基底，所述外围区的基底内具有有源层；
    在所述阵列区的所述基底内形成字线沟槽；
    在所述字线沟槽中字线，所述字线包括层叠设置的第一字线导电层和第二字线导电层；所述第一字线导电层的顶部具有凸出部，且所述凸出部沿所述第一字线导电层指向所述第二字线导电层的方向凸出；
    形成覆盖所述基底的隔离层；
    同时形成贯穿所述隔离层的第一通孔和第二通孔，所述第一通孔露出所述有源层，所述第二通孔露出所述凸出部。
  2. 根据权利要求1所述的半导体结构的制造方法，其中，所述同时形成贯穿所述隔离层的第一通孔和第二通孔包括：
    在所述隔离层上形成光刻胶层，对所述光刻胶层进行光刻处理，以同时形成第一开口和第二开口，所述第一开口位于所述外围区，所述第二开口位于所述阵列区；
    同时沿所述第一开口和所述第二开口刻蚀所述隔离层，以形成所述第一通孔和所述第二通孔，所述第一通孔与所述第一开口正对，所述第二通孔与所述第二开口正对。
  3. 根据权利要求1所述的半导体结构的制造方法，其中，
    形成所述第一字线导电层的步骤包括：形成填充满所述字线沟槽的初始第一字线导电层；
    第一刻蚀处理，以使所述初始第一字线导电层的上表面低于所述基底的上表面；
    第二刻蚀处理，以将所述初始第一字线导电层的顶部形成为所述凸出部，剩余的所述初始第一字线导电层作为所述第一字线导电层。
  4. 根据权利要求1所述的半导体结构的制造方法，其中，所述凸出部的顶端与所述字线沟槽的侧壁间隔设置。
  5. 根据权利要求4所述的半导体结构的制造方法，其中，所述凸出部的顶端与所述字线沟槽相对的两个侧壁的距离相同。
  6. 根据权利要求4所述的半导体结构的制造方法，其中，所述凸出部与所述字线沟槽相接触。
  7. 根据权利要求1所述的半导体结构的制造方法，其中，所述凸出部的延伸方向与所述字线沟槽的延伸方向相同且平行于所述基底的上表面，且所述凸出部和所述字线沟槽在延伸方向上的长度相同。
  8. 根据权利要求1所述的半导体结构的制造方法，其中，所述第二通孔在所述字线沟槽的延伸方向上具有第一宽度，所述第二通孔在垂直于所述字线沟槽侧壁的方向上具有第二宽度，所述第一宽度大于所述第二宽度。
  9. 根据权利要求8所述的半导体结构的制造方法，其中，所述第一宽度与所述第二宽度之差大于10nm。
  10. 根据权利要求1所述的半导体结构的制造方法，其中，在所述第一字线导电层指向所述第二字线导电层的方向上，所述凸出部的厚度大于20nm。
  11. 根据权利要求1所述的半导体结构的制造方法，其中，所述凸出部的顶面为平面；
    或者，所述凸出部的顶面为弧面。
  12. 根据权利要求1所述的半导体结构的制造方法，其中，所述第一字线导电层的功函数大于所述第二字线导电层的功函数。
  13. 根据权利要求1所述的半导体结构的制造方法，其中，在垂直于所述字线沟槽侧壁的方向上，所述第二通孔的宽度大于或等于所述凸出部的宽度。
  14. 根据权利要求1所述的半导体结构的制造方法，其中，还包括：形成填充所述第一通孔的第一接触结构以及填充所述第二通孔的第二接触结构，所述第一接触结构与所述有源层相连，所述第二接触结构与所述字线相连。
  15. 根据权利要求1所述的半导体结构的制造方法，其中，在形成所述隔离层前还包括：在所述有源层上形成栅极结构；
    所述隔离层覆盖所述栅极结构；所述第一通孔至少为两个，且其中两个所述第一通孔位于所述栅极结构的两侧。
  16. 一种半导体结构，所述半导体结构包括外围区和阵列区，所述半导体结构包括：
    基底，所述外围区的基底内具有有源层；
    所述阵列区的基底内形成有字线，所述字线包括层叠设置的第一字线导电层和第二字线导电层；所述第一字线导电层的顶部具有凸出部，且所述凸出部沿所述第一字线导电层指向所述第二字线导电层的方向凸出；
    覆盖所述基底的隔离层，所述隔离层中形成有第一接触结构以及第二接触结构，所述第一接触结构与所述有源层相连，所述第二接触结构与所述字线相连。
  17. 根据权利要求16所述的半导体结构，其中，在所述第二接触结构在所述基底上的投影区域内，所述第二字线导电层在所述基底上的投影区域位于所述凸出部在所述基底上的投影区域的两侧；所述第二接触结构与所述第一字线导电层及所述第二字线导电层均接触。
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