WO2023284170A1 - 一种制作GaN芯片的方法及GaN芯片 - Google Patents

一种制作GaN芯片的方法及GaN芯片 Download PDF

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WO2023284170A1
WO2023284170A1 PCT/CN2021/127517 CN2021127517W WO2023284170A1 WO 2023284170 A1 WO2023284170 A1 WO 2023284170A1 CN 2021127517 W CN2021127517 W CN 2021127517W WO 2023284170 A1 WO2023284170 A1 WO 2023284170A1
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sacrificial layer
gan
layer
temporary carrier
growing
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PCT/CN2021/127517
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English (en)
French (fr)
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郭芬
苏康
周朗
李拓
满宏涛
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苏州浪潮智能科技有限公司
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Priority to US18/268,949 priority Critical patent/US11908689B2/en
Publication of WO2023284170A1 publication Critical patent/WO2023284170A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/185—Joining of semiconductor bodies for junction formation
    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
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    • H01L21/02538—Group 13/15 materials
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    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/7688—Filling of holes, grooves or trenches, e.g. vias, with conductive material by deposition over sacrificial masking layer, e.g. lift-off
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/7806—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices involving the separation of the active layers from a substrate
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02378—Silicon carbide
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02455—Group 13/15 materials
    • H01L21/02458—Nitrides
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02494—Structure
    • H01L21/02496—Layer structure
    • H01L21/02505—Layer structure consisting of more than two layers
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68318—Auxiliary support including means facilitating the separation of a device or wafer from the auxiliary support
    • H—ELECTRICITY
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    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68381—Details of chemical or physical process used for separating the auxiliary support from a device or wafer
    • H01L2221/68386—Separation by peeling

Definitions

  • the present application relates to the semiconductor field, and more specifically, refers to a method, system, computer equipment and readable medium for fabricating a GaN chip.
  • GaN Gallium Nitride
  • GaN materials have excellent characteristics such as large band gap, high electron saturation rate, high critical breakdown electric field and strong radiation resistance. Therefore, high electron mobility transistors (HEMT) based on GaN materials are widely used.
  • HEMT high electron mobility transistors
  • GaN HEMT devices have excellent power output capability, but the output power density of conventional GaN-based microwave power devices can only reach -5W/mm. Studies have shown that the actual output capability of GaN-based microwave power devices is mainly limited by the self-heating effect.
  • GaN heterostructures are usually grown on substrates such as sapphire, silicon carbide (SiC) or Si. Among them, since SiC has high thermal conductivity, which is about 10 times that of sapphire, SiC with high thermal conductivity is used as the substrate.
  • the substrate or heat sink of high-frequency and high-power GaN-based devices will be one of the best solutions to reduce the self-heating effect of GaN-based high-power devices and solve the problem of rapid power density decline with the increase of total power and frequency.
  • the lattice mismatch between the SiC substrate and GaN is relatively small, which can effectively improve the crystal quality of the grown GaN material.
  • the price of semi-insulating SiC substrate is very high.
  • the original substrate of the GaN heterostructure on the SiC substrate can be removed by lift-off technology, and then the GaN heterostructure can be transferred to other target substrates with relatively low cost and high thermal conductivity.
  • the crystal quality of the SiC substrate is less affected, and the reuse of the SiC substrate can be realized to overcome the problem of high cost of the SiC substrate.
  • LLO Laser Lift-Off
  • Smart-Cut Smart-Cut
  • Controlled Spalling and Epitaxial Lift-Off
  • ELO Epitaxial Lift-Off
  • LLO is usually used to lift off the GaN film on the sapphire substrate. Since the process requires excimer laser, the process is relatively complicated and the cost is high.
  • Smart-Cut technology uses ion implantation to generate an ion damage layer under the donor wafer; then, the acceptor wafer is combined with the donor wafer; finally, the film separation is achieved at the ion damage layer through stress regulation technology, the most mature of Smart-Cut
  • An application is the preparation of silicon-on-insulator (SOI) wafers.
  • SOI silicon-on-insulator
  • Smart-Cut puts forward high requirements for wafer bonding.
  • Controllable exfoliation technology grows a stress-inducing layer on a separated film, and the stress-inducing layer is subjected to tensile stress.
  • the tape on the stress-inducing layer By pulling the tape on the stress-inducing layer, the film is peeled off from a heterogeneous or homogeneous substrate.
  • Si, Ge , GaAs and GaN films are peeled from the original substrate, but due to the difficulty of stress control, this method is difficult to achieve large-area, high-flatness materials and devices.
  • the purpose of the embodiment of the present application is to propose a method, system, computer equipment and computer-readable storage medium for fabricating a GaN chip.
  • This application introduces a "sandwich" structure sacrificial layer between the GaN functional material and the SiC substrate , the GaN device is stripped from the SiC substrate and transplanted to other high thermal conductivity substrates to realize the perfect transfer of the GaN device, thereby reducing the difficulty of the heterogeneous integration process of the GaN device, expanding the application range of the GaN device, and improving the GaN device
  • the flexibility of heterogeneous integration has a great impact on improving the performance of RF power devices, improving device thermal management, and manufacturing flexible electronic devices.
  • an aspect of the embodiment of the present application provides a method for manufacturing a GaN chip, including the following steps: growing a Nb 2 N sacrificial layer on the original substrate, and growing a GaN insert on the Nb 2 N sacrificial layer layer; growing a Ta 2 N sacrificial layer on the GaN insertion layer, and growing a semiconductor layer on the Ta 2 N sacrificial layer to form a GaN wafer; bonding, and removing the Nb 2 N sacrificial layer and the Ta 2 N sacrificial layer; and transferring the remaining material after removing the Nb 2 N sacrificial layer and the Ta 2 N sacrificial layer to a target substrate , and removing the temporary mount from the remaining material to form a GaN chip.
  • the growing the Nb 2 N sacrificial layer on the original substrate includes: forming a Nb 2 N sacrificial layer with a thickness of 0 to 50 nm on the original substrate.
  • the growing a Ta 2 N sacrificial layer on the GaN insertion layer includes: forming a Ta 2 N sacrificial layer with a thickness of 0 to 50 nm on the GaN insertion layer.
  • the bonding of the GaN wafer and the first surface of the temporary carrier includes: coating an adhesive material on the first surface of the temporary carrier, placing the temporary carrier Bake on a hot plate and then cool the temporary slides.
  • the coating of the adhesive material on the first side of the temporary carrier includes: coating the adhesive material on the first side of the temporary carrier by a spin coating method, and controlling the rotation speed to 1200 to 3000 rpm, control the time to 30 to 60 seconds.
  • placing the temporary slide on a hot plate for baking includes: controlling the temperature of the hot plate to 120° C., and baking for 3 minutes; and controlling the temperature of the hot plate to 180° C., and baking for 4 minutes. minute.
  • the bonding the GaN wafer and the first surface of the temporary carrier includes: controlling the bonding temperature to 200 to 350° C., and controlling the bonding pressure to 1000 to 2000N.
  • the removing the Nb 2 N sacrificial layer and the Ta 2 N sacrificial layer includes: removing the Nb 2 N sacrificial layer by etching with hydrochloric acid and hydrofluoric acid at a volume ratio of 1:1. layer and the Ta 2 N sacrificial layer.
  • the transfer of the remaining material after removing the Nb 2 N sacrificial layer and the Ta 2 N sacrificial layer to the target substrate includes: using nitrogen or oxygen gas to treat the remaining material and the target substrate.
  • the substrate is activated, and the activated target substrate is aligned and attached to the remaining material, and annealing is performed.
  • Another aspect of the embodiments of the present application provides a chip manufactured by using the above method.
  • the application has the following beneficial technical effects: by introducing a "sandwich” structure sacrificial layer between the GaN functional material and the SiC substrate, the GaN device is peeled off from the SiC substrate and transplanted to other high thermal conductivity substrates to realize a GaN device
  • the perfect transfer of GaN devices thereby reducing the difficulty of GaN device heterogeneous integration process, expanding the application range of GaN devices, improving the flexibility of GaN device heterogeneous integration, and improving the performance of RF power devices, improving device thermal management, flexible electronic device manufacturing and other fields have a significant impact.
  • FIG. 1 is a schematic diagram of an embodiment of a method for making a GaN chip provided by the present application
  • Fig. 2 is a schematic diagram of the hardware structure of an embodiment of a computer device for making a GaN chip provided by the present application;
  • FIG. 3 is a schematic diagram of an embodiment of a computer storage medium for making a GaN chip provided by the present application.
  • FIG. 1 is a schematic diagram of an embodiment of a method for fabricating a GaN chip provided by the present application. As shown in Figure 1, the embodiment of the present application includes the following steps:
  • the GaN device is peeled off from the SiC substrate and transplanted onto other high thermal conductivity substrates, Realize the perfect transfer of GaN devices, thereby reducing the difficulty of GaN device heterogeneous integration process, expanding the application range of GaN devices, improving the flexibility of GaN device heterogeneous integration, and improving the performance of RF power devices, improving device thermal management, flexible electronic devices Manufacturing and other fields have a significant impact.
  • a Nb 2 N sacrificial layer is grown on the original substrate, and a GaN insertion layer is grown on the Nb 2 N sacrificial layer.
  • the growing the Nb 2 N sacrificial layer on the original substrate includes: forming a Nb 2 N sacrificial layer with a thickness of 0 to 50 nm on the original substrate.
  • SiC silicon carbide
  • the original substrate is not limited to SiC, and may also be GaN, Sapphire (sapphire), Diamond (diamond), Ga2O 3 (gallium trioxide) and AlN (aluminum nitride), etc.
  • a sacrificial layer with a sandwich structure is grown by thin film deposition, and a layer of Nb 2 N sacrificial layer with ⁇ phase is grown on the substrate by adjusting the growth process, controlling the growth temperature, the dose ratio of Nb atoms and N atoms, and the Nb 2 N
  • the sacrificial layer growth thickness is 0 to 50 nm.
  • a GaN insertion layer is grown on the Nb 2 N sacrificial layer, and the thickness of the GaN insertion layer is 0 to 200 nm.
  • a Ta 2 N sacrificial layer is grown on the GaN insertion layer, and a semiconductor layer is grown on the Ta 2 N sacrificial layer to form a GaN wafer.
  • the growing a Ta 2 N sacrificial layer on the GaN insertion layer includes: forming a Ta 2 N sacrificial layer with a thickness of 0 to 50 nm on the GaN insertion layer.
  • a Ta 2 N sacrificial layer with hexagonal crystal structure symmetry is grown on the GaN insertion layer by thin film deposition, and the growth thickness of the Ta 2 N sacrificial layer is 0 to 50 nm.
  • a semiconductor layer is grown on the Ta 2 N sacrificial layer.
  • the bonding of the GaN wafer and the first surface of the temporary carrier includes: coating an adhesive material on the first surface of the temporary carrier, placing the temporary carrier Bake on a hot plate, and then cool the temporary slide, eg, wait for the temporary slide to cool at room temperature.
  • Apply a temporary adhesive material on the front of the temporary carrier as a bonding material place the temporary carrier face up on a hot plate and bake it. After the temporary carrier is naturally cooled at room temperature, place the SiC-based GaN wafer and Temporary slides are bonded face-to-face.
  • the coating of the adhesive material on the first side of the temporary carrier includes: coating the adhesive material on the first side of the temporary carrier by a spin coating method, and controlling the rotation speed to 1200 to 3000 rpm, control the time to 30 to 60 seconds.
  • the coating of the temporary bonding material adopts the method of spin coating, the rotation speed is 1200rpm/min to 3000rpm/min, and the time is 30 to 60s.
  • placing the temporary slide on a hot plate for baking includes: controlling the temperature of the hot plate to 120° C., and baking for 3 minutes; and controlling the temperature of the hot plate to 180° C., and baking for 4 minutes. minute.
  • a two-step baking method was adopted, the first step of baking time was 3 minutes, the temperature of the hot plate was 120°C; the second step of baking time was 4 minutes, and the temperature of the hot plate was 180°C.
  • the bonding the GaN wafer and the first surface of the temporary carrier includes: controlling the bonding temperature to 200 to 350° C., and controlling the bonding pressure to 1000 to 2000N. After the temporary carrier is naturally cooled at room temperature, the SiC-based GaN wafer and the temporary carrier are bonded face-to-face. The bonding temperature is 200 to 350°C and the bonding pressure is 1000 to 2000N.
  • the bonding of the GaN wafer and the first surface of the temporary carrier includes: after the temporary carrier is naturally cooled at room temperature, the SiC-based GaN wafer and the temporary carrier face each other , so that the SiC-based GaN wafer and the carrier are overlapped as much as possible, fixed with a fixture and placed in a bonding machine for bonding, using a wafer bonding machine for wafer bonding, the bonding temperature is 150 to 200 ° C, bonding The time is 5 to 10 minutes, and the pressure is 0.1MPa.
  • the removing the Nb 2 N sacrificial layer and the Ta 2 N sacrificial layer includes: removing the Nb 2 N sacrificial layer by etching with hydrochloric acid and hydrofluoric acid at a volume ratio of 1:1. layer and the Ta 2 N sacrificial layer.
  • the sacrificial layer of the Nb 2 N/GaN/Ta 2 N sandwich structure is removed by using hydrochloric acid and hydrofluoric acid with a volume ratio of 1:1 and selective wet chemical etching, and the SiC substrate is separated from the GaN material after etching.
  • the removing the Nb 2 N sacrificial layer and the Ta 2 N sacrificial layer includes: removing the Nb 2 N/Ta 2 N stacked sacrificial layer with nitric acid and reactive non-plasma gas XeF 2 Except; the Nb 2 N/GaN/Ta 2 N sandwich structure sacrificial layer grown on the original substrate includes but not limited to metal-organic chemical vapor deposition, molecular beam epitaxy, sputtering, atomic layer deposition and pulsed laser deposition, most It is best to directly carry out in-situ growth of III-V epitaxial materials after depositing the Nb 2 N sacrificial layer to avoid pollution; the semiconductor layer can be a GaN HEMT structure, or a GaN MOSFET, GaN Finfet structure, etc.
  • the transfer of the remaining material after removing the Nb 2 N sacrificial layer and the Ta 2 N sacrificial layer to the target substrate includes: using nitrogen or oxygen gas to treat the remaining material and the target substrate.
  • the substrate is activated, and the activated target substrate is aligned and attached to the remaining material, and annealing is performed.
  • the GaN material is transferred to the target substrate by direct bonding. Direct bonding is to use gas to perform plasma activation on the target substrate and the back of the GaN material.
  • the gas used is N 2 or O 2 , the gas flow rate is 50 to 200 sccm, and the activation time is 10 to 60 s.
  • the target substrate is Align and bond with the GaN material, and perform annealing treatment at a temperature of 150 to 200°C for 2 hours. Soak the GaN wafer in the temporary bonding material removal solution, and the GaN wafer will be automatically separated from the temporary carrier after the temporary bonding material is completely dissolved by the removal solution.
  • This application provides a technology to improve the heat dissipation of GaN chips to grow semiconductor epitaxial material structures.
  • This structure uses a Nb 2 N/GaN/Ta 2 N sandwich structure sacrificial layer, due to the similar lattice matching of Nb 2 N, Ta 2 N and GaN .
  • the GaN insertion layer in the sandwich structure is mainly used to alleviate the lattice mismatch between the SiC substrate and the upper GaN buffer layer, so the use of the Nb 2 N/GaN/Ta 2 N sandwich structure sacrificial layer can improve the crystal quality of the epitaxial GaN material ;
  • the Ta 2 N ultra-thin film has high surface coverage and good uniformity, which can make the back surface roughness of the stripped GaN material lower, and the back side of the stripped GaN material does not need additional polishing treatment, and is easy to transfer to the target substrate Above; the Nb 2 N/GaN/Ta 2 N sandwich structure sacrificial layer can make the sacrificial layer easier to peel off by wet etching, and make the SiC substrate reusable after simple surface treatment; Nb 2 N/GaN/Ta 2 The growth of N sandwich structure sacrificial layer is compatible with III-N growth temperature; Nb 2 N/GaN/Ta 2 N sandwich structure sacrificial layer has selective
  • Nb 2 N and Ta 2 N have similar crystal structures with SiC, GaN and AlN, Nb 2 N and Ta 2 N thin films can be grown on SiC, Nb 2 N/GaN/Ta 2 N sandwich structure sacrificial layer can be compared with The heterogeneous integration of III-N devices will not affect the material quality and electrical properties of the subsequent III-N layer.
  • the research work confirmed that AlN and GaN heterostructures with high crystallinity and electrical quality can be grown on Nb 2 N/GaN thin layers almost the same as directly grown on GaN thin films.
  • This application introduces the Nb 2 N/GaN/Ta 2 N sandwich structure sacrificial layer, and adopts a simple treatment process that can complete the transfer of III-N devices after the completion of the previous treatment and quality screening.
  • the finished III-N device can be completely separated from its substrate.
  • the second aspect of the embodiments of the present application proposes a chip manufactured by any one of the above methods.
  • the above method will not be repeated here.
  • the third aspect of the embodiment of the present application proposes a system for manufacturing GaN chips, including: a first sacrificial module configured to grow a Nb 2 N sacrificial layer on the original substrate, and A GaN insertion layer is grown on the Nb 2 N sacrificial layer; a second sacrificial module is configured to grow a Ta 2 N sacrificial layer on the GaN insertion layer, and grow a semiconductor layer on the Ta 2 N sacrificial layer to form a GaN round a sheet; a removal module configured to bond the GaN wafer to the first side of the temporary carrier, and remove the Nb 2 N sacrificial layer and the Ta 2 N sacrificial layer; and an execution module, It is configured to transfer the remaining material after removing the Nb 2 N sacrificial layer and the Ta 2 N sacrificial layer to a target substrate, and remove the temporary carrier from the remaining material to form a GaN chip.
  • the removal module is configured to: apply an adhesive material to the first side of the temporary slide, place the temporary slide on a hot plate to bake, and then remove the Temporary slide cooling.
  • the removal module is configured to: apply an adhesive material to the first surface of the temporary carrier by spin coating, and control the rotation speed to 1200 to 3000 rpm, and control the time to for 30 to 60 seconds.
  • the removal module is configured to: control the temperature of the hot plate to 120° C. and bake for 3 minutes; and control the temperature of the hot plate to 180° C. and bake for 4 minutes.
  • the removal module is configured to: control the bonding temperature at 200 to 350° C., and control the bonding pressure at 1000 to 2000 N.
  • the removal module is configured to: use hydrochloric acid and hydrofluoric acid with a volume ratio of 1:1 to etch and remove the Nb 2 N sacrificial layer and the Ta 2 N sacrificial layer.
  • the execution module is configured to: activate the remaining material and the target substrate with nitrogen or oxygen, and align and attach the activated target substrate to the remaining material , and annealed.
  • the fourth aspect of the embodiments of the present application proposes a computer device, including: at least one processor; and a memory, the memory stores computer instructions that can run on the processor, and the instructions are executed by the processor to The following steps are implemented: S1, growing a Nb 2 N sacrificial layer on the original substrate, and growing a GaN insertion layer on the Nb 2 N sacrificial layer; S2, growing a Ta 2 N sacrificial layer on the GaN insertion layer, and growing a semiconductor layer on the Ta 2 N sacrificial layer to form a GaN wafer; S3, bonding the GaN wafer to the first surface of the temporary carrier, and removing the Nb 2 N sacrificial layer and the the Ta 2 N sacrificial layer; and S4, transferring the remaining material after removing the Nb 2 N sacrificial layer and the Ta 2 N sacrificial layer to a target substrate, and removing the temporary wafer to form a GaN chip.
  • the bonding of the GaN wafer and the first surface of the temporary carrier includes: coating an adhesive material on the first surface of the temporary carrier, placing the temporary carrier Bake on a hot plate and then cool the temporary slides.
  • the coating of the adhesive material on the first side of the temporary carrier includes: coating the adhesive material on the first side of the temporary carrier by a spin coating method, and controlling the rotation speed to 1200 to 3000 rpm, control the time to 30 to 60 seconds.
  • placing the temporary slide on a hot plate for baking includes: controlling the temperature of the hot plate to 120° C., and baking for 3 minutes; and controlling the temperature of the hot plate to 180° C., and baking for 4 minutes. minute.
  • the bonding the GaN wafer and the first surface of the temporary carrier includes: controlling the bonding temperature to 200 to 350° C., and controlling the bonding pressure to 1000 to 2000N.
  • the removing the Nb 2 N sacrificial layer and the Ta 2 N sacrificial layer includes: removing the Nb 2 N sacrificial layer by etching with hydrochloric acid and hydrofluoric acid at a volume ratio of 1:1. layer and the Ta 2 N sacrificial layer.
  • the transfer of the remaining material after removing the Nb 2 N sacrificial layer and the Ta 2 N sacrificial layer to the target substrate includes: using nitrogen or oxygen gas to treat the remaining material and the target substrate.
  • the substrate is activated, and the activated target substrate is aligned and attached to the remaining material, and annealing is performed.
  • FIG. 2 it is a schematic diagram of the hardware structure of an embodiment of the above-mentioned computer equipment for making GaN chips provided by the present application.
  • the device includes a processor 201 and a memory 202 , and may further include: an input device 203 and an output device 204 .
  • the processor 201, the memory 202, the input device 203, and the output device 204 may be connected through a bus or in other ways. In FIG. 2, connection through a bus is taken as an example.
  • the memory 202 can be used to store non-volatile software programs, non-volatile computer-executable programs and modules, as in the method for making a GaN chip in the embodiment of the present application.
  • the processor 201 executes various functional applications and data processing of the server by running non-volatile software programs, instructions and modules stored in the memory 202, that is, implements the method for fabricating a GaN chip in the above method embodiment.
  • the memory 202 may include a program storage area and a data storage area, wherein the program storage area may store an operating system and an application program required by at least one function; the data storage area may store data created according to the method of making a GaN chip, and the like.
  • the memory 202 may include a high-speed random access memory, and may also include a non-volatile memory, such as at least one magnetic disk storage device, flash memory device, or other non-volatile solid-state storage devices.
  • the memory 202 may optionally include memories that are remotely located relative to the processor 201, and these remote memories may be connected to the local module through a network. Examples of the aforementioned networks include, but are not limited to, the Internet, intranets, local area networks, mobile communication networks, and combinations thereof.
  • the input device 203 can receive input information such as user name and password.
  • the output device 204 may include a display device such as a display screen.
  • One or more program instructions/modules corresponding to the method for fabricating a GaN chip are stored in the memory 202, and when executed by the processor 201, the method for fabricating a GaN chip in any of the above method embodiments is executed.
  • Any one embodiment of the computer equipment implementing the above-mentioned method for fabricating a GaN chip can achieve the same or similar effects as any of the above-mentioned method embodiments corresponding thereto.
  • the present application also provides a computer-readable storage medium, and the computer-readable storage medium stores a computer program for executing the above method when executed by a processor.
  • FIG. 3 it is a schematic diagram of an embodiment of the above-mentioned computer storage medium for making GaN chips provided in this application.
  • the computer readable storage medium 3 stores a computer program 31 for executing a method for fabricating a GaN chip when executed by a processor.
  • the method for making a GaN chip comprises the following steps: growing a Nb 2 N sacrificial layer on an original substrate, and growing a GaN insertion layer on the Nb 2 N sacrificial layer; growing a Ta 2 N sacrificial layer on the GaN insertion layer, and growing a semiconductor layer on the Ta 2 N sacrificial layer to form a GaN wafer; bonding the GaN wafer to the first surface of the temporary carrier, and removing the Nb 2 N sacrificial layer and the Ta 2 N sacrificial layer; and transferring the remaining material after removing the Nb 2 N sacrificial layer and the Ta 2 N sacrificial layer to a target substrate, and removing the temporary carrier from the remaining material to GaN chips are formed.
  • the growing the Nb 2 N sacrificial layer on the original substrate includes: forming a Nb 2 N sacrificial layer with a thickness of 0 to 50 nm on the original substrate.
  • the growing a Ta 2 N sacrificial layer on the GaN insertion layer includes: forming a Ta 2 N sacrificial layer with a thickness of 0 to 50 nm on the GaN insertion layer.
  • the bonding of the GaN wafer and the first surface of the temporary carrier includes: coating an adhesive material on the first surface of the temporary carrier, placing the temporary carrier Bake on a hot plate and then cool the temporary slides.
  • the coating of the adhesive material on the first side of the temporary carrier includes: coating the adhesive material on the first side of the temporary carrier by a spin coating method, and controlling the rotation speed to 1200 to 3000 rpm, control the time to 30 to 60 seconds.
  • placing the temporary slide on a hot plate for baking includes: controlling the temperature of the hot plate to 120° C., and baking for 3 minutes; and controlling the temperature of the hot plate to 180° C., and baking for 4 minutes. minute.
  • the bonding the GaN wafer and the first surface of the temporary carrier includes: controlling the bonding temperature to 200 to 350°C, and controlling the bonding pressure to 1000 to 2000N.
  • the removing the Nb 2 N sacrificial layer and the Ta 2 N sacrificial layer includes: removing the Nb 2 N sacrificial layer by etching with hydrochloric acid and hydrofluoric acid at a volume ratio of 1:1. layer and the Ta 2 N sacrificial layer.
  • the transfer of the remaining material after removing the Nb 2 N sacrificial layer and the Ta 2 N sacrificial layer to the target substrate includes: using nitrogen or oxygen gas to treat the remaining material and the target substrate.
  • the substrate is activated, and the activated target substrate is aligned and attached to the remaining material, and annealing is performed.
  • the program of the method for making a GaN chip can be stored in a computer-readable
  • the program may include the processes of the embodiments of the above-mentioned methods.
  • the storage medium of the program may be a magnetic disk, an optical disk, a read-only memory (ROM) or a random access memory (RAM), and the like.
  • the storage medium may be a read-only memory, a magnetic disk or an optical disk, and the like.

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Abstract

本申请公开了一种制作GaN芯片的方法、系统、设备和存储介质，方法包括：在原始衬底上生长Nb 2N牺牲层，并在Nb 2N牺牲层上生长GaN插入层；在GaN插入层上生长Ta 2N牺牲层，并在Ta 2N牺牲层上生长半导体层以形成GaN圆片；将GaN圆片和临时载片的第一面进行键合，并移除Nb 2N牺牲层和Ta 2N牺牲层；以及将移除Nb 2N牺牲层和Ta 2N牺牲层后的剩余材料转移到目标衬底，并从剩余材料中移除临时载片以形成GaN芯片。本申请通过引入两层牺牲层，采取简单处理工艺即能够在完成前道处理和质量筛查后完成器件的转移，通过嵌入两层牺牲层，制造完毕的器件能够完整的从其衬底上分离，提高了GaN器件异质集成的灵活性。

Description

一种制作GaN芯片的方法及GaN芯片
本申请要求在2021年07月15日提交中国专利局、申请号为202110798912.8、发明名称为“一种制作GaN芯片的方法及GaN芯片”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及半导体领域，更具体地，特别是指一种制作GaN芯片的方法、系统、计算机设备及可读介质。
背景技术
进入21世纪，电子工业以及信息产业发展迅猛，半导体材料与器件作为发展的重要催化剂，正快速推动人类进入信息技术时代。而微电子器件的发展与半导体材料的进步密不可分，从以Ge(锗)、Si(硅)为代表的第一代半导体材料到以GaAs(砷化镓)、InP(磷化铟)为代表的第二代半导体材料都为器件的发展作出了巨大的贡献。氮化镓(GaN)作为第三代半导体材料的代表，自诞生以来就备受青睐，成为了全球半导体研究的焦点。GaN材料具备禁带宽度大、电子饱和速率高、临界击穿电场高和抗辐射能力强等优异特征，因此，基于GaN材料的高电子迁移率晶体管(high electron mobility transistor，HEMT)，被广泛应用于新一代高功率、高频率的固态微波功率器件制造，这对卫星通讯、军事雷达、第五代移动通信(5th Generation Moblie Networks，简称5G)等领域发展具有重要意义。
理论上，GaN HEMT器件具备优异的功率输出能力，但目前常规GaN基微波功率器件的输出功率密度仅能达到-5W/mm。研究表明，GaN基微波功率器件的实际输出能力主要受限于自热效应。目前，GaN异质结构通常都是在蓝宝石、碳化硅(SiC)或Si等衬底上生长获得，其中，由于SiC具 有高的热导率，约是蓝宝石的10倍，采用高热导率SiC作为高频、大功率GaN基器件的衬底或热沉，对于降低GaN基大功率器件的自加热效应，解决随总功率增加、频率提高出现的功率密度迅速下降问题将是很好的方案之一。另一方面，SiC衬底与GaN的晶格失配相对较小，可以有效提高生长的GaN材料的晶体质量。但是由于半绝缘SiC衬底相对于另外两种常用的GaN材料外延衬底，即蓝宝石衬底和Si衬底，半绝缘SiC衬底的价格非常高。为了降低成本，可以采用剥离技术移除SiC衬底上GaN异质结构的原始衬底，再将GaN异质结构转移至其他成本相对较低的高热导率的目标衬底上，如果剥离过程对SiC衬底的晶体质量影响较小，便可实现SiC衬底的重复利用，克服SiC衬底成本高的问题。
剥离技术可将薄膜从原始晶圆转移到另一个晶圆上。目前，主流的剥离技术包括激光剥离(Laser Lift-Off，LLO)、智能剥离(Smart-Cut)、可控剥离(Controlled Spalling)和外延层剥离(Epitaxial Lift-Off，ELO)等。LLO通常用于剥离蓝宝石衬底上的GaN薄膜，由于工艺过程需要用到准分子激光，因此，工艺较为复杂，成本较高。Smart-Cut技术利用离子注入在施主晶圆下方产生离子损伤层；然后，受主晶圆与施主晶圆结合；最后，通过应力调控技术在离子损伤层处实现薄膜分离，Smart-Cut最成熟的应用是制备绝缘体上硅(SOI)晶片。Smart-Cut中薄膜转移的成功与否的关键，取决于施主与受主晶圆的键合质量，因此，Smart-Cut对晶圆键合提出了很高的要求。可控剥落技术通过在分离的薄膜上生长应力诱导层，应力诱导层受到拉伸应力作用，通过拉扯应力诱导层上的胶带，从异质或同质基底上剥离薄膜，已成功实现Si、Ge、GaAs和GaN薄膜从原始衬底的剥离，但是由于应力调控难度较大，该方法很难实现大面积、高平整度材料及器件的剥离。
申请内容
有鉴于此，本申请实施例的目的在于提出一种制作GaN芯片的方法、系统、计算机设备及计算机可读存储介质，本申请通过在GaN功能材料和 SiC衬底间引入“三明治”结构牺牲层，将GaN器件从SiC衬底上剥离，并移植到其他高热导率衬底上，实现GaN器件的完美转移，从而降低GaN器件异质集成工艺难度，拓展GaN器件的应用范围，提高了GaN器件异质集成的灵活性，对于提高射频功率器件性能、改善器件热管理、柔性电子器件制造等领域具有重大影响意义。
基于上述目的，本申请实施例的一方面提供了一种制作GaN芯片的方法，包括如下步骤：在原始衬底上生长Nb 2N牺牲层，并在所述Nb 2N牺牲层上生长GaN插入层；在所述GaN插入层上生长Ta 2N牺牲层，并在所述Ta 2N牺牲层上生长半导体层以形成GaN圆片；将所述GaN圆片和临时载片的第一面进行键合，并移除所述Nb 2N牺牲层和所述Ta 2N牺牲层；以及将移除所述Nb 2N牺牲层和所述Ta 2N牺牲层后的剩余材料转移到目标衬底，并从所述剩余材料中移除所述临时载片以形成GaN芯片。
在一些实施方式中，所述在原始衬底上生长Nb 2N牺牲层包括：在所述原始衬底上制作0至50nm厚度的Nb 2N牺牲层。
在一些实施方式中，所述在所述GaN插入层上生长Ta 2N牺牲层包括：在所述GaN插入层上制作0至50nm厚度的Ta 2N牺牲层。
在一些实施方式中，所述将所述GaN圆片和临时载片的第一面进行键合包括：在所述临时载片的第一面涂敷粘合材料，将所述临时载片放置在热板上烘烤，并随后将所述临时载片冷却。
在一些实施方式中，所述在所述临时载片的第一面涂敷粘合材料包括：采用旋涂法对所述临时载片的第一面涂覆粘合材料，并将转速控制为1200至3000转/分钟，将时间控制为30至60秒。
在一些实施方式中，所述将所述临时载片放置在热板上烘烤包括：将热板温度控制为120℃，烘烤3分钟；以及将热板温度控制为180℃，烘烤4分钟。
在一些实施方式中，所述将所述GaN圆片和临时载片的第一面进行键合包括：将键合温度控制为200至350℃，键合压力控制为1000至2000N。
在一些实施方式中，所述移除所述Nb 2N牺牲层和所述Ta 2N牺牲层包括：使用体积比为1：1的盐酸和氢氟酸刻蚀移除所述Nb 2N牺牲层和所述Ta 2N牺牲层。
在一些实施方式中，所述将移除所述Nb 2N牺牲层和所述Ta 2N牺牲层后的剩余材料转移到目标衬底包括：采用氮气或氧气对所述剩余材料和所述目标衬底进行激活，将激活后的所述目标衬底与所述剩余材料对准贴合，并进行退火处理。
本申请实施例的另一方面，提供了一种使用如上方法制作的芯片。
本申请具有以下有益技术效果：通过在GaN功能材料和SiC衬底间引入“三明治”结构牺牲层，将GaN器件从SiC衬底上剥离，并移植到其他高热导率衬底上，实现GaN器件的完美转移，从而降低GaN器件异质集成工艺难度，拓展GaN器件的应用范围，提高了GaN器件异质集成的灵活性，对于提高射频功率器件性能、改善器件热管理、柔性电子器件制造等领域具有重大影响意义。
附图说明
为了更清楚地说明本申请实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的实施例。
图1为本申请提供的制作GaN芯片的方法的实施例的示意图；
图2本申请提供的制作GaN芯片的计算机设备的实施例的硬件结构示意图；
图3为本申请提供的制作GaN芯片的计算机存储介质的实施例的示意图。
具体实施方式
为使本申请的目的、技术方案和优点更加清楚明白，以下结合具体实施例，并参照附图，对本申请实施例进一步详细说明。
需要说明的是，本申请实施例中所有使用“第一”和“第二”的表述均是为了区分两个相同名称非相同的实体或者非相同的参量，可见“第一”“第二”仅为了表述的方便，不应理解为对本申请实施例的限定，后续实施例对此不再一一说明。
本申请实施例的第一个方面，提出了一种制作GaN芯片的方法的实施例。图1示出的是本申请提供的制作GaN芯片的方法的实施例的示意图。如图1所示，本申请实施例包括如下步骤：
S1、在原始衬底上生长Nb 2N牺牲层，并在所述Nb 2N牺牲层上生长GaN插入层；
S2、在所述GaN插入层上生长Ta 2N牺牲层，并在所述Ta 2N牺牲层上生长半导体层以形成GaN圆片；
S3、将所述GaN圆片和临时载片的第一面进行键合，并移除所述Nb 2N牺牲层和所述Ta 2N牺牲层；以及
S4、将移除所述Nb 2N牺牲层和所述Ta 2N牺牲层后的剩余材料转移到目标衬底，并从所述剩余材料中移除所述临时载片以形成GaN芯片。
本申请实施例通过在GaN功能材料和SiC衬底间引入Nb 2N/GaN/Ta 2N三明治结构牺牲层，将GaN器件从SiC衬底上剥离，并移植到其他高热导率衬底上，实现GaN器件的完美转移，从而降低GaN器件异质集成工艺难度，拓展GaN器件的应用范围，提高了GaN器件异质集成的灵活性，对于提高射频功率器件性能、改善器件热管理、柔性电子器件制造等领域具有重大影响意义。
在原始衬底上生长Nb 2N牺牲层，并在所述Nb 2N牺牲层上生长GaN插入层。在一些实施方式中，所述在原始衬底上生长Nb 2N牺牲层包括：在所述原始衬底上制作0至50nm厚度的Nb 2N牺牲层。本申请实施例选择具有六方晶体结构对称性的SiC(碳化硅)材料作为原始衬底，当然，原始衬 底不限于SiC，还可以为GaN、Sapphire(蓝宝石)、Diamond(钻石)、Ga 2O 3(三氧化二镓)和AlN(氮化铝)等。采用薄膜沉积法生长三明治结构牺牲层，通过调控生长工艺，控制生长温度、Nb原子与N原子通入剂量比，在衬底上生长一层具有β相的Nb 2N牺牲层，该Nb 2N牺牲层生长厚度为0至50nm。在Nb 2N牺牲层上生长GaN插入层，该GaN插入层的厚度为0至200nm。
在所述GaN插入层上生长Ta 2N牺牲层，并在所述Ta 2N牺牲层上生长半导体层以形成GaN圆片。在一些实施方式中，所述在所述GaN插入层上生长Ta 2N牺牲层包括：在所述GaN插入层上制作0至50nm厚度的Ta 2N牺牲层。采用薄膜沉积在GaN插入层上生长具有六方晶体结构对称性的Ta 2N牺牲层，该Ta 2N牺牲层生长厚度为0至50nm。在Ta 2N牺牲层上生长半导体层。
将所述GaN圆片和临时载片的第一面进行键合，并移除所述Nb 2N牺牲层和所述Ta 2N牺牲层。
在一些实施方式中，所述将所述GaN圆片和临时载片的第一面进行键合包括：在所述临时载片的第一面涂敷粘合材料，将所述临时载片放置在热板上烘烤，并随后将所述临时载片冷却，例如等待所述临时载片在室温下冷却。在临时载片的正面涂敷临时粘合材料作为键合材料，将临时载片正面朝上放在热板上烘烤，待临时载片在室温下自然冷却后，将SiC基GaN圆片和临时载片正面相对进行键合。
在一些实施方式中，所述在所述临时载片的第一面涂敷粘合材料包括：采用旋涂法对所述临时载片的第一面涂覆粘合材料，并将转速控制为1200至3000转/分钟，将时间控制为30至60秒。临时键合材料的涂敷采用旋涂方法，转速1200rpm/min至3000rpm/min，时间为30至60s。
在一些实施方式中，所述将所述临时载片放置在热板上烘烤包括：将热板温度控制为120℃，烘烤3分钟；以及将热板温度控制为180℃，烘烤4分钟。采用两步烘烤法，第一步烘烤时间为3min，热板温度为120℃；第二步烘烤时间为4min，热板温度为180℃。
在一些实施方式中，所述将所述GaN圆片和临时载片的第一面进行键合包括：将键合温度控制为200至350℃，键合压力控制为1000至2000N。待临时载片在室温下自然冷却后，将SiC基GaN圆片和临时载片正面相对进行键合，键合温度为200至350℃，键合压力1000至2000N。
在一些实施方式中，所述将所述GaN圆片和临时载片的第一面进行键合包括：待临时载片在室温下自然冷却后，将SiC基GaN圆片和临时载片正面相对，使SiC基GaN圆片和载片尽量完全重叠，用夹具固定好放入键合机进行键合，利用晶圆键合机进行圆片键合，键合温度为150至200℃，键合时间5至10min，压力为0.1MPa。
在一些实施方式中，所述移除所述Nb 2N牺牲层和所述Ta 2N牺牲层包括：使用体积比为1：1的盐酸和氢氟酸刻蚀移除所述Nb 2N牺牲层和所述Ta 2N牺牲层。使用体积比为1：1的盐酸和氢氟酸并采用选择性湿法化学刻蚀移除Nb 2N/GaN/Ta 2N三明治结构牺牲层，刻蚀后SiC衬底与GaN材料分离。
在一些实施方式中，所述移除所述Nb 2N牺牲层和所述Ta 2N牺牲层包括：采用硝酸、反应性非等离子气体XeF 2对Nb 2N/Ta 2N堆叠牺牲层进行移除；在原始衬底上生长的Nb 2N/GaN/Ta 2N三明治结构牺牲层包括但不局限于金属有机物化学气相沉积法、分子束外延、溅射、原子层沉积和脉冲激光沉积，最好是在沉积完Nb 2N牺牲层直接进行Ⅲ-Ⅴ外延材料的原位生长，避免造成污染；其中半导体层可以为GaN HEMT结构，也可以为GaN MOSFET、GaN Finfet结构等。
将移除所述Nb 2N牺牲层和所述Ta 2N牺牲层后的剩余材料转移到目标衬底，并从所述剩余材料中移除所述临时载片以形成GaN芯片。
在一些实施方式中，所述将移除所述Nb 2N牺牲层和所述Ta 2N牺牲层后的剩余材料转移到目标衬底包括：采用氮气或氧气对所述剩余材料和所述目标衬底进行激活，将激活后的所述目标衬底与所述剩余材料对准贴合，并进行退火处理。采用直接键合的方法将GaN材料转移到目标衬底。直接键合为采用气体对目标衬底和GaN材料的背面进行等离子体激活，所用气 体为N 2或O 2，气体流量为50至200sccm，激活时间为10至60s，激活结束后将目标衬底与GaN材料对准贴合，并进行退火处理，所用温度为150至200℃，时间为2h。将GaN圆片浸泡在临时键合材料去除液中，待临时键合材料被去除液全部溶解后GaN圆片将与临时载片自动分离。
本申请提供一种提高GaN芯片散热的技术来生长半导体外延材料结构，此结构采用Nb 2N/GaN/Ta 2N三明治结构牺牲层，由于Nb 2N、Ta 2N与GaN相近的晶格匹配。三明治结构中的GaN插入层主要用于缓解SiC衬底与上层GaN缓冲层之间的晶格失配，所以采用Nb 2N/GaN/Ta 2N三明治结构牺牲层可以提高外延GaN材料的晶体质量；Ta 2N超薄膜的表面覆盖率高，均匀性好，可使剥离后的GaN材料背面表面粗糙度更低，剥离后的GaN材料的背面不需要进行额外抛光处理，易于转移到目标衬底上；采用Nb 2N/GaN/Ta 2N三明治结构牺牲层可以使牺牲层更易于湿法腐蚀剥离，而且使SiC衬底经过简单的表面处理就可以重复利用；Nb 2N/GaN/Ta 2N三明治结构牺牲层的生长与Ⅲ-N生长温度兼容；Nb 2N/GaN/Ta 2N三明治结构牺牲层在SiC上有可选择性刻蚀特性，通过体积比为1：1的盐酸和氢氟酸的选择性湿法化学刻蚀或反应性非等离子气体XeF 2对Nb 2N/GaN/Ta 2N三明治结构牺牲层进行移除，而且在这个过程中，不会对GaN、AlN和大多数通用金属和电介质造成刻蚀。然后将GaN材料转移到目标衬底，实现SiC衬底的重复利用，提高GaN芯片散热效率。
Nb 2N和Ta 2N与SiC、GaN和AlN具有相似的晶体结构，Nb 2N和Ta 2N薄膜可以实现在SiC上的生长，Nb 2N/GaN/Ta 2N三明治结构牺牲层能够与Ⅲ-N器件异质集成，又不会影响后续Ⅲ-N层的材料质量和电性能。研究工作证实，带有高结晶度和电气质量的AlN和GaN异质结构能够生长在Nb 2N/GaN薄层上，与直接生长在GaN薄膜上几乎相同。本申请引入Nb 2N/GaN/Ta 2N三明治结构牺牲层，采取简单的处理工艺即能够在完成前道处理和质量筛查后完成Ⅲ-N器件的转移，通过嵌入薄Nb 2N/GaN/Ta 2N三明治结构牺牲层，制造完毕的Ⅲ-N器件能够完整从其衬底上完全分离。
需要特别指出的是，上述制作GaN芯片的方法的各个实施例中的各个 步骤均可以相互交叉、替换、增加、删减，因此，这些合理的排列组合变换之于制作GaN芯片的方法也应当属于本申请的保护范围，并且不应将本申请的保护范围局限在实施例之上。
基于上述目的，本申请实施例的第二个方面，提出了一种使用如上任意一种方法制作的芯片。为了说明书的简洁，在此不再赘述上述方法。
基于上述目的，本申请实施例的第三个方面，提出了一种制作GaN芯片的系统，包括：第一牺牲模块，配置用于在原始衬底上生长Nb 2N牺牲层，并在所述Nb 2N牺牲层上生长GaN插入层；第二牺牲模块，配置用于在所述GaN插入层上生长Ta 2N牺牲层，并在所述Ta 2N牺牲层上生长半导体层以形成GaN圆片；移除模块，配置用于将所述GaN圆片和临时载片的第一面进行键合，并移除所述Nb 2N牺牲层和所述Ta 2N牺牲层；以及执行模块，配置用于将移除所述Nb 2N牺牲层和所述Ta 2N牺牲层后的剩余材料转移到目标衬底，并从所述剩余材料中移除所述临时载片以形成GaN芯片。
在一些实施方式中，所述移除模块配置用于：在所述临时载片的第一面涂敷粘合材料，将所述临时载片放置在热板上烘烤，并随后将所述临时载片冷却。
在一些实施方式中，所述移除模块配置用于：采用旋涂法对所述临时载片的第一面涂覆粘合材料，并将转速控制为1200至3000转/分钟，将时间控制为30至60秒。
在一些实施方式中，所述移除模块配置用于：将热板温度控制为120℃，烘烤3分钟；以及将热板温度控制为180℃，烘烤4分钟。
在一些实施方式中，所述移除模块配置用于：将键合温度控制为200至350℃，键合压力控制为1000至2000N。
在一些实施方式中，所述移除模块配置用于：使用体积比为1：1的盐酸和氢氟酸刻蚀移除所述Nb 2N牺牲层和所述Ta 2N牺牲层。
在一些实施方式中，所述执行模块配置用于：采用氮气或氧气对所述剩余材料和所述目标衬底进行激活，将激活后的所述目标衬底与所述剩余 材料对准贴合，并进行退火处理。
基于上述目的，本申请实施例的第四个方面，提出了一种计算机设备，包括：至少一个处理器；以及存储器，存储器存储有可在处理器上运行的计算机指令，指令由处理器执行以实现如下步骤：S1、在原始衬底上生长Nb 2N牺牲层，并在所述Nb 2N牺牲层上生长GaN插入层；S2、在所述GaN插入层上生长Ta 2N牺牲层，并在所述Ta 2N牺牲层上生长半导体层以形成GaN圆片；S3、将所述GaN圆片和临时载片的第一面进行键合，并移除所述Nb 2N牺牲层和所述Ta 2N牺牲层；以及S4、将移除所述Nb 2N牺牲层和所述Ta 2N牺牲层后的剩余材料转移到目标衬底，并从所述剩余材料中移除所述临时载片以形成GaN芯片。
在一些实施方式中，所述将所述GaN圆片和临时载片的第一面进行键合包括：在所述临时载片的第一面涂敷粘合材料，将所述临时载片放置在热板上烘烤，并随后将所述临时载片冷却。
在一些实施方式中，所述在所述临时载片的第一面涂敷粘合材料包括：采用旋涂法对所述临时载片的第一面涂覆粘合材料，并将转速控制为1200至3000转/分钟，将时间控制为30至60秒。
在一些实施方式中，所述将所述临时载片放置在热板上烘烤包括：将热板温度控制为120℃，烘烤3分钟；以及将热板温度控制为180℃，烘烤4分钟。
在一些实施方式中，所述将所述GaN圆片和临时载片的第一面进行键合包括：将键合温度控制为200至350℃，键合压力控制为1000至2000N。
在一些实施方式中，所述移除所述Nb 2N牺牲层和所述Ta 2N牺牲层包括：使用体积比为1：1的盐酸和氢氟酸刻蚀移除所述Nb 2N牺牲层和所述Ta 2N牺牲层。
在一些实施方式中，所述将移除所述Nb 2N牺牲层和所述Ta 2N牺牲层后的剩余材料转移到目标衬底包括：采用氮气或氧气对所述剩余材料和所述目标衬底进行激活，将激活后的所述目标衬底与所述剩余材料对准贴合， 并进行退火处理。
如图2所示，为本申请提供的上述制作GaN芯片的计算机设备的一个实施例的硬件结构示意图。
以如图2所示的装置为例，在该装置中包括一个处理器201以及一个存储器202，并还可以包括：输入装置203和输出装置204。
处理器201、存储器202、输入装置203和输出装置204可以通过总线或者其他方式连接，图2中以通过总线连接为例。
存储器202作为一种非易失性计算机可读存储介质，可用于存储非易失性软件程序、非易失性计算机可执行程序以及模块，如本申请实施例中的制作GaN芯片的方法对应的程序指令/模块。处理器201通过运行存储在存储器202中的非易失性软件程序、指令以及模块，从而执行服务器的各种功能应用以及数据处理，即实现上述方法实施例的制作GaN芯片的方法。
存储器202可以包括存储程序区和存储数据区，其中，存储程序区可存储操作系统、至少一个功能所需要的应用程序；存储数据区可存储根据制作GaN芯片的方法的使用所创建的数据等。此外，存储器202可以包括高速随机存取存储器，还可以包括非易失性存储器，例如至少一个磁盘存储器件、闪存器件、或其他非易失性固态存储器件。在一些实施例中，存储器202可选包括相对于处理器201远程设置的存储器，这些远程存储器可以通过网络连接至本地模块。上述网络的实例包括但不限于互联网、企业内部网、局域网、移动通信网及其组合。
输入装置203可接收输入的用户名和密码等信息。输出装置204可包括显示屏等显示设备。
一个或者多个制作GaN芯片的方法对应的程序指令/模块存储在存储器202中，当被处理器201执行时，执行上述任意方法实施例中的制作GaN芯片的方法。
执行上述制作GaN芯片的方法的计算机设备的任何一个实施例，可以达到与之对应的前述任意方法实施例相同或者相类似的效果。
本申请还提供了一种计算机可读存储介质，计算机可读存储介质存储有被处理器执行时执行如上方法的计算机程序。
如图3所示，为本申请提供的上述制作GaN芯片的计算机存储介质的一个实施例的示意图。以如图3所示的计算机存储介质为例，计算机可读存储介质3存储有被处理器执行时执行制作GaN芯片的方法的计算机程序31。
制作GaN芯片的方法包括如下步骤：在原始衬底上生长Nb 2N牺牲层，并在所述Nb 2N牺牲层上生长GaN插入层；在所述GaN插入层上生长Ta 2N牺牲层，并在所述Ta 2N牺牲层上生长半导体层以形成GaN圆片；将所述GaN圆片和临时载片的第一面进行键合，并移除所述Nb 2N牺牲层和所述Ta 2N牺牲层；以及将移除所述Nb 2N牺牲层和所述Ta 2N牺牲层后的剩余材料转移到目标衬底，并从所述剩余材料中移除所述临时载片以形成GaN芯片。
在一些实施方式中，所述在原始衬底上生长Nb 2N牺牲层包括：在所述原始衬底上制作0至50nm厚度的Nb 2N牺牲层。
在一些实施方式中，所述在所述GaN插入层上生长Ta 2N牺牲层包括：在所述GaN插入层上制作0至50nm厚度的Ta 2N牺牲层。
在一些实施方式中，所述将所述GaN圆片和临时载片的第一面进行键合包括：在所述临时载片的第一面涂敷粘合材料，将所述临时载片放置在热板上烘烤，并随后将所述临时载片冷却。
在一些实施方式中，所述在所述临时载片的第一面涂敷粘合材料包括：采用旋涂法对所述临时载片的第一面涂覆粘合材料，并将转速控制为1200至3000转/分钟，将时间控制为30至60秒。
在一些实施方式中，所述将所述临时载片放置在热板上烘烤包括：将热板温度控制为120℃，烘烤3分钟；以及将热板温度控制为180℃，烘烤4分钟。
在一些实施方式中，所述将所述GaN圆片和临时载片的第一面进行键 合包括：将键合温度控制为200至350℃，键合压力控制为1000至2000N。
在一些实施方式中，所述移除所述Nb 2N牺牲层和所述Ta 2N牺牲层包括：使用体积比为1：1的盐酸和氢氟酸刻蚀移除所述Nb 2N牺牲层和所述Ta 2N牺牲层。
在一些实施方式中，所述将移除所述Nb 2N牺牲层和所述Ta 2N牺牲层后的剩余材料转移到目标衬底包括：采用氮气或氧气对所述剩余材料和所述目标衬底进行激活，将激活后的所述目标衬底与所述剩余材料对准贴合，并进行退火处理。
最后需要说明的是，本领域普通技术人员可以理解实现上述实施例方法中的全部或部分流程，可以通过计算机程序来指令相关硬件来完成，制作GaN芯片的方法的程序可存储于一计算机可读取存储介质中，该程序在执行时，可包括如上述各方法的实施例的流程。其中，程序的存储介质可为磁碟、光盘、只读存储记忆体(ROM)或随机存储记忆体(RAM)等。上述计算机程序的实施例，可以达到与之对应的前述任意方法实施例相同或者相类似的效果。
以上是本申请公开的示例性实施例，但是应当注意，在不背离权利要求限定的本申请实施例公开的范围的前提下，可以进行多种改变和修改。根据这里描述的公开实施例的方法权利要求的功能、步骤和/或动作不需以任何特定顺序执行。此外，尽管本申请实施例公开的元素可以以个体形式描述或要求，但除非明确限制为单数，也可以理解为多个。
应当理解的是，在本文中使用的，除非上下文清楚地支持例外情况，单数形式“一个”旨在也包括复数形式。还应当理解的是，在本文中使用的“和/或”是指包括一个或者一个以上相关联地列出的项目的任意和所有可能组合。
上述本申请实施例公开实施例序号仅仅为了描述，不代表实施例的优劣。
本领域普通技术人员可以理解实现上述实施例的全部或部分步骤可以 通过硬件来完成，也可以通过程序来指令相关的硬件完成，程序可以存储于一种计算机可读存储介质中，上述提到的存储介质可以是只读存储器，磁盘或光盘等。
所属领域的普通技术人员应当理解：以上任何实施例的讨论仅为示例性的，并非旨在暗示本申请实施例公开的范围(包括权利要求)被限于这些例子；在本申请实施例的思路下，以上实施例或者不同实施例中的技术特征之间也可以进行组合，并存在如上的本申请实施例的不同方面的许多其它变化，为了简明它们没有在细节中提供。因此，凡在本申请实施例的精神和原则之内，所做的任何省略、修改、等同替换、改进等，均应包含在本申请实施例的保护范围之内。

Claims (10)

  1. 一种制作GaN芯片的方法，其特征在于，包括以下步骤：
    在原始衬底上生长Nb 2N牺牲层，并在所述Nb 2N牺牲层上生长GaN插入层；
    在所述GaN插入层上生长Ta 2N牺牲层，并在所述Ta 2N牺牲层上生长半导体层以形成GaN圆片；
    将所述GaN圆片和临时载片的第一面进行键合，并移除所述Nb 2N牺牲层和所述Ta 2N牺牲层；以及
    将移除所述Nb 2N牺牲层和所述Ta 2N牺牲层后的剩余材料转移到目标衬底，并从所述剩余材料中移除所述临时载片以形成GaN芯片。
  2. 根据权利要求1所述的方法，其特征在于，所述在原始衬底上生长Nb 2N牺牲层包括：
    在所述原始衬底上制作0至50nm厚度的Nb 2N牺牲层。
  3. 根据权利要求1所述的方法，其特征在于，所述在所述GaN插入层上生长Ta 2N牺牲层包括：
    在所述GaN插入层上制作0至50nm厚度的Ta 2N牺牲层。
  4. 根据权利要求1所述的方法，其特征在于，所述将所述GaN圆片和临时载片的第一面进行键合包括：
    在所述临时载片的第一面涂敷粘合材料，将所述临时载片放置在热板上烘烤，并随后将所述临时载片冷却。
  5. 根据权利要求4所述的方法，其特征在于，所述在所述临时载片的第一面涂敷粘合材料包括：
    采用旋涂法对所述临时载片的第一面涂覆粘合材料，并将转速控制为1200至3000转/分钟，将时间控制为30至60秒。
  6. 根据权利要求4所述的方法，其特征在于，所述将所述临时载片放置在热板上烘烤包括：
    将热板温度控制为120℃，烘烤3分钟；以及
    将热板温度控制为180℃，烘烤4分钟。
  7. 根据权利要求1所述的方法，其特征在于，所述将所述GaN圆片和临时载片的第一面进行键合包括：
    将键合温度控制为200至350℃，键合压力控制为1000至2000N。
  8. 根据权利要求1所述的方法，其特征在于，所述移除所述Nb 2N牺牲层和所述Ta 2N牺牲层包括：
    使用体积比为1：1的盐酸和氢氟酸刻蚀移除所述Nb 2N牺牲层和所述Ta 2N牺牲层。
  9. 根据权利要求1所述的方法，其特征在于，所述将移除所述Nb 2N牺牲层和所述Ta 2N牺牲层后的剩余材料转移到目标衬底包括：
    采用氮气或氧气对所述剩余材料和所述目标衬底进行激活，将激活后的所述目标衬底与所述剩余材料对准贴合，并进行退火处理。
  10. 一种芯片，其特征在于，使用如权利要求1至9中任一项权利要求所述的方法制成。
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