WO2023279717A1 - 阻变存储器件及其制备方法 - Google Patents

阻变存储器件及其制备方法 Download PDF

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Publication number
WO2023279717A1
WO2023279717A1 PCT/CN2022/076303 CN2022076303W WO2023279717A1 WO 2023279717 A1 WO2023279717 A1 WO 2023279717A1 CN 2022076303 W CN2022076303 W CN 2022076303W WO 2023279717 A1 WO2023279717 A1 WO 2023279717A1
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WIPO (PCT)
Prior art keywords
bit line
trench
gate
substrate
resistive
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PCT/CN2022/076303
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English (en)
French (fr)
Inventor
章纬
邓杰芳
王晓光
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长鑫存储技术有限公司
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Priority to US17/807,030 priority Critical patent/US20230008157A1/en
Publication of WO2023279717A1 publication Critical patent/WO2023279717A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/011—Manufacture or treatment of multistable switching devices
    • H10N70/061—Shaping switching materials
    • H10N70/066—Shaping switching materials by filling of openings, e.g. damascene method
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H10B63/30—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having three or more electrodes, e.g. transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/881—Switching materials
    • H10N70/883—Oxides or nitrides
    • H10N70/8833—Binary metal oxides, e.g. TaOx

Definitions

  • the embodiments of the present application relate to the technical field of integrated circuits, and in particular to a resistive memory device and a manufacturing method thereof.
  • a typical resistive memory device is composed of a planar transistor and a MIM (metal-insulator-metal) structure above the planar transistor.
  • the planar transistor and the MIM structure are prepared in different process steps. Due to the complicated process and large size, how to simplify the process flow of RRAM and form a small-sized RRAM structure has become an urgent problem to be solved.
  • Embodiments of the present application provide a resistive memory device and a manufacturing method thereof, which can optimize the process flow of the resistive memory device.
  • a method for preparing a resistive memory device comprising:
  • bit line trenches in the substrate
  • bit line trench filling the bit line trench to form a bit line structure
  • variable resistance structure includes a bit line structure and a resistive material layer.
  • the present application also provides a resistive memory device, including:
  • a bit line trench is opened in the substrate
  • the resistive material layer is located on the sidewall and bottom of the bit line trench
  • bit line structure is filled in the bit line trench
  • variable resistance structure includes a bit line structure and a resistive material layer.
  • the variable resistance structure includes a bit line structure and a resistive switching material layer, wherein the resistive switching material layer is located on the sidewall and bottom of the bit line trench, and the bit line structure is filled in the bit line trench In the groove, the bit line structure and the resistive material layer on the side wall of the bit line in the resistive memory device of the present application are used as a part of the variable resistance structure, and the variable resistance structure is formed while the bit line structure is formed, which simplifies the resistive memory device.
  • the process flow reduces the production cost, and at the same time reduces the size of the resistive memory device.
  • FIG. 1 is a schematic flow chart of a method for manufacturing a resistive memory device in an embodiment
  • FIG. 2 is a schematic cross-sectional view of a resistive memory device after forming a gate trench in an embodiment
  • FIG. 3 is a schematic cross-sectional view of a resistive memory device after forming a gate trench in another embodiment
  • FIG. 4 is a schematic cross-sectional view of a resistive memory device after forming a first dielectric layer in an embodiment corresponding to FIG. 2;
  • FIG. 5 is a schematic cross-sectional view of a resistive memory device after forming a gate structure in an embodiment corresponding to FIG. 4;
  • FIG. 6 is a schematic cross-sectional view of a resistive memory device after forming a second dielectric layer in an embodiment corresponding to FIG. 5;
  • FIG. 7 is a schematic diagram of an equivalent circuit of a resistive memory device in an embodiment corresponding to FIG. 6 .
  • first, second, etc. used in this application may be used to describe various elements herein, but these elements are not limited by these terms. These terms are only used to distinguish one element from another element.
  • a first client could be termed a second client, and, similarly, a second client could be termed a first client, without departing from the scope of the present application.
  • Both the first client and the second client are clients, but they are not the same client.
  • first and second are used for descriptive purposes only, and cannot be interpreted as indicating or implying relative importance or implicitly specifying the quantity of indicated technical features. Thus, the features defined as “first” and “second” may explicitly or implicitly include at least one of these features.
  • plural means at least two, such as two, three, etc., unless otherwise specifically defined.
  • severeal means at least one, such as one, two, etc., unless otherwise specifically defined.
  • Resistive Random Access Memory is a storage device with a non-charge storage mechanism. It has a metal-insulator-metal sandwich structure. Under specific voltage/current excitation, its resistance can be between high resistance and low resistance. It has the advantages of low write operation voltage, short write and erase time, long memory time, non-destructive read, multi-value storage, simple structure and high storage density, and is expected to replace DRAM, SRAM and Flash, etc. become a general purpose memory. However, compared with DRAM, the size of RRAM is larger, and the number of RRAMs per unit area is smaller. The size of a typical RRAM cell using two FinFETs is 0.07632 square microns.
  • FIG. 1 is a schematic flowchart of a method for manufacturing a resistive memory device in an embodiment.
  • FIG. 2 is a schematic cross-sectional view of a resistive memory device after forming a gate trench 110 in an embodiment.
  • a method for manufacturing a resistive memory device including:
  • a substrate 102 for forming a resistive memory device is provided.
  • the substrate 102 includes a substrate and different device regions formed on the substrate.
  • the substrate can be undoped single crystal silicon or single crystal silicon doped with impurities.
  • single crystal silicon is selected as the constituent material of the substrate.
  • a bit line trench 108 is formed at a predetermined position on the substrate 102 by using photolithography and etching processes well known to those skilled in the art.
  • any one of atomic layer deposition, molecular beam epitaxy, radio frequency magnetron sputtering, and chemical vapor deposition is used to form a resistive material layer 206 on the sidewall and bottom of the bit line trench 108.
  • the resistive material layer 206 will reversibly change between different resistance states, and the resistance states usually include two kinds of high resistance state and low resistance state.
  • the resistive switch material layer 206 may be a high-k material layer.
  • the resistive switch material layer 206 includes at least one of a hafnium oxide material layer or a tantalum oxide material layer.
  • a bit line structure 210 is formed by filling the bit line trench 108 , and the material of the bit line structure 210 may be titanium nitride material or metal tungsten material.
  • the bit line structure 210 on one side of the resistive material layer 206, the substrate 102 on the other side of the resistive material layer 206, and the resistive material layer 206 together constitute a variable resistance structure (MIM structure) in the resistive memory device. That is, the bit line structure 210 in the present application serves as an electrode in the MIM structure at the same time, and the resistive material layer 206 serves as a resistance switching layer in the MIM structure. Compared with the typical preparation process of separately forming the MIM structure, the process flow is simplified.
  • the variable resistance structure includes a bit line structure 210 and a resistive material layer 206, wherein the resistive material layer 206 is located on the sidewall and bottom of the bit line trench 108, and the bit line structure 210 is filled in the bit line trench In the groove 108, the bit line structure 210 and the resistive material layer 206 on the side wall of the bit line in the resistive memory device of the present application are used as a part of the variable resistance structure, and the variable resistance structure is formed at the same time as the bit line structure 210, which simplifies The process flow of the resistive memory device reduces the production cost, and at the same time reduces the size of the resistive memory device.
  • a shallow trench isolation structure 104 is formed in the substrate 102, and the shallow trench isolation structure 104 isolates active regions 106 arranged in an array in the substrate 102; formed in the substrate 102
  • gate trenches 110 are formed in the substrate 102, each gate trench 110 and a bit line trench 108 straddle the same active region 106, and divide the active region 106 into The source region 202 between the gate trench 110 and the STI structure 104 , and the drain region 204 between the gate trench 110 and the bit line trench 108 .
  • bit line trench 108 and the gate trench 110 are simultaneously formed in the substrate 102 by an etching process, and the gate trench 110 and the bit line trench 108 are simultaneously passed through in one active region 106, and the The active region 106 is divided into a source region 202 located between the STI structure 104 and the gate trench 110 and a drain region 204 located between the gate trench 110 and the bit line trench 108 . Subsequently, the source region 202 and the drain region 204 can be doped according to actual needs to obtain the source and drain of the transistor in the resistive memory device respectively.
  • a shallow trench isolation structure 104 is formed in the substrate 102, and the shallow trench isolation structure 104 isolates the active region 106 arranged in an array in the substrate 102; after the bit line trench 108 is formed in the substrate 102 It also includes: a step of forming gate trenches 110 in the substrate 102, each gate trench 110 and a bit line trench 108 span the same active region 106, and divide the active region 106 into The source region 202 between the trench 110 and the STI structure 104 , and the drain region 204 between the gate trench 110 and the bit line trench 108 .
  • a bit line trench 108 and a gate trench 110 are respectively formed in the substrate 102 through an etching process, and the gate trench 110 and the bit line trench 108 pass through one active region 106 at the same time, and the The active region 106 is divided into a source region 202 located between the STI structure 104 and the gate trench 110 and a drain region 204 located between the gate trench 110 and the bit line trench 108 . Subsequently, the source region 202 and the drain region 204 can be doped according to actual needs to obtain the source and drain of the transistor in the resistive memory device respectively.
  • the doping depth of the source and the drain along the X direction is less than or equal to the depth of the gate trench 110 and the bit line trench 108 .
  • the X direction refers to the upward direction from the substrate 102
  • the Y direction refers to the direction intersecting with the extending direction of the bit line trench 108 .
  • the bit line trench 108 and the gate trench 110 have the same depth in the X direction and the same width in the Y direction. At this time, they can be formed by lithography equipment with the same overlay error Bit line trench 108 and gate trench 110 . In other embodiments, the shape of the bit line trench 108 and the gate trench 110 are different. At this time, according to the process requirements, the bit line trench 108 and the gate trench are formed by lithography equipment with the same or different overlay errors. 110.
  • bit line trench 108 and the gate trench 110 straddle the same active region 106, the bit line trench 108 and the adjacent shallow trench isolation structure in the Y direction
  • active region 106 between 104 that is, when a gate trench 110 and a bit line trench 108 pass through an active region 106, the active region 106 is divided into the shallow trench isolation structure 104 and the gate
  • the width W1 along the Y direction of the part of the active region 106 located between the bit line trench 108 and the adjacent STI structure 104 is smaller than or equal to the width W2 along the Y direction of the source region 202 .
  • the preparation method of the resistive memory device in this application can be compatible with the preparation method of the DRAM device, that is, at least part of the photolithography plate of the DRAM device can be used to prepare the resistive memory device, so that the process flow of the resistive memory device is simplified and has
  • the density of DRAM devices reduces production costs and realizes the high-density array design of resistive memory devices.
  • the size of resistive memory devices can reach 0.004 square microns, which is nearly 19 times smaller.
  • FIG. 3 is a schematic cross-sectional view of a resistive memory device after forming a gate trench in another embodiment.
  • the bit line trench 108 and the gate trench 110 straddle the same active region 106 , they are in contact with the adjacent shallow trench isolation structure 104 in the Y direction, that is, an active
  • the active region 106 is divided into a source region 202 located between the shallow trench isolation structure 104 and the gate trench 110 and a source region 202 located between the shallow trench isolation structure 104 and the gate trench 110 .
  • There are two parts of the drain region 204 between the gate trench 110 and the bit line trench 108 With this arrangement, the size of the resistive memory device is further reduced.
  • variable resistance structure further includes a drain region 204 . That is, the substrate 102 on the other side of the resistive material layer 206 in the variable resistance structure refers to the drain electrode after doping. At this time, the drain electrode and the bit line structure 210 are respectively used as two electrodes of the variable resistance structure, located on the drain electrode. The resistive material layer 206 between the electrode and the bit line structure 210 serves as a resistance transition layer between two electrodes of the variable resistance structure.
  • bit line trenches 108 are formed in the shallow trench isolation structure 104 between the plurality of active regions 106 and adjacent active regions 106 . In other embodiments, the bit line trenches 108 are only formed in the plurality of active regions 106 .
  • FIG. 4 is a schematic cross-sectional view of the resistive memory device after forming the first dielectric layer 208 in an embodiment corresponding to FIG. 2 .
  • a first dielectric layer 208 is formed on the sidewall and bottom of the gate trench 110 .
  • after forming the resistive switch material layer 206 on the sidewall and bottom of the bit line trench 108 or before forming the resistive switch material layer 206 on the sidewall and bottom of the bit line trench 108 further includes: The step of forming the first dielectric layer 208 on the sidewall and bottom of 110 .
  • the active region 106 can be isolated from the gate structure 212 subsequently formed in the gate trench 110, wherein the active region 106 includes a source formed in the source region 202 and a drain formed in the drain.
  • the drain in pole region 204 is a source formed in the source region 202 and a drain formed in the drain.
  • the first dielectric layer 208 includes at least one of a hafnium oxide material layer, a silicon dioxide layer or a tantalum oxide material layer.
  • the first dielectric layer 208 is made of the same material as the resistive material layer 206 , for example, both are hafnium oxide material layers.
  • FIG. 5 is a schematic cross-sectional view of the resistive memory device after forming the gate structure 212 in an embodiment corresponding to FIG. 4 .
  • the gate trench 110 is filled to form the gate structure 212 .
  • after filling the bit line trench 108 to form the bit line structure 210 or before filling the bit line trench 108 to form the bit line structure 210 further includes: filling the gate trench 110 to form a gate structure 212 steps.
  • the material of the bit line structure 210 and the gate structure 212 includes at least one of titanium nitride material, metal titanium material, metal tungsten material and doped polysilicon material.
  • the material of the bit line structure 210 and the gate structure 212 is titanium nitride for an exemplary description.
  • the step of filling the gate trench 110 to form the gate structure 212 includes: the first step, through the deposition process, the bit line trench 108 and filling the gate trench 110 to form a titanium nitride material layer.
  • the second step is to etch and remove the excess titanium nitride material layer to obtain the bit line structure 210 composed of the remaining titanium nitride material layer in the bit line trench 108, and the remaining titanium nitride material layer in the gate trench 110
  • a gate structure 212 is formed, wherein the gate structure 212 also serves as a word line structure (WL) in the resistive memory device.
  • WL word line structure
  • the upper surface of the gate structure 212 is flush with the upper surface of the bit line structure 210 .
  • the upper surface of the bit line structure 210 is lower than the upper surface of the substrate 102 , that is, the bit line structure 210 is a buried bit line. In other embodiments, the upper surface of the bit line structure 210 is flush with the upper surface of the substrate 102 or the upper surface of the bit line structure 210 is higher than the upper surface of the substrate 102 .
  • FIG. 6 is a schematic cross-sectional view of the resistive memory device after forming the second dielectric layer 112 in an embodiment corresponding to FIG. 5 .
  • the manufacturing method of the resistive memory device further includes: forming a protection layer 214 on the bit line structure 210 and the gate structure 212 . Further, when the upper surface of the bit line structure 210 is lower than the upper surface of the substrate 102 , the upper surface of the protective layer 214 is flush with or higher than the upper surface of the substrate 102 .
  • the bit line trench 108 and the gate trench 110 are filled with a protective material, the upper surface of the protective material is higher than the upper surface of the substrate 102, and the protective material covers the active region 106 and the shallow trench on the isolation structure 104 .
  • etching removes the protective material above the surface of the substrate 102 .
  • a chemical planarization treatment is performed to obtain a protective layer 214 whose upper surface is made of remaining protective material and is flush with the upper surface of the substrate 102 .
  • the constituent materials of the protective layer 214 include one or more of oxides, nitrides, and oxynitrides, wherein the oxides include borophosphosilicate glass (BPSG), phosphosilicate glass (PSG), tetraethyl orthosilicate (TEOS), undoped silica glass (USG), spin-on-glass (SOG), high-density plasma (HDP) or spin-on-dielectric (SOD); nitrides include silicon nitride (SiN); oxynitrides include oxynitride Silicon (SiON).
  • oxides include borophosphosilicate glass (BPSG), phosphosilicate glass (PSG), tetraethyl orthosilicate (TEOS), undoped silica glass (USG), spin-on-glass (SOG), high-density plasma (HDP) or spin-on-dielectric (SOD); nitrides include silicon nitride (SiN);
  • the protective layer 214 on the bit line structure 210 and the gate structure 212 further includes: forming a second dielectric layer 112 on the substrate 102, the second dielectric layer 112 and the protective layer 214 contacts.
  • the constituent materials of the second dielectric layer 112 include one or more of oxides, nitrides, and oxynitrides, wherein the oxides include borophosphosilicate glass (BPSG), phosphosilicate glass (PSG), Ethyl silicate (TEOS), undoped silica glass (USG), spin-on-glass (SOG), high-density plasma (HDP), or spin-on-dielectric (SOD); nitrides including silicon nitride (SiN); nitride The oxide includes silicon oxynitride (SiON).
  • BPSG borophosphosilicate glass
  • PSG phosphosilicate glass
  • TEOS Ethyl silicate
  • USG spin-on-glass
  • HDP high-density plasma
  • SOD spin-on-dielectric
  • the oxide includes silicon oxynitride (SiON).
  • the second dielectric layer 112 is located on the upper surface of the substrate 102 .
  • the second dielectric layer 112 includes a silicon dioxide layer on the upper surface of the substrate 102 .
  • the second dielectric layer 112 also includes a silicon nitride layer on the upper surface of the silicon dioxide layer.
  • the second dielectric layer 112 is made of the same material as the protective layer 214 .
  • the second dielectric layer 112 can be formed simultaneously with the protective layer 214 or can be formed separately from the protective layer 214 .
  • the second dielectric layer 112 on the substrate 102 further includes:
  • a source lead-out structure 114 is formed on the source region 202 , the source lead-out structure 114 penetrates the second dielectric layer 112 and is in contact with the source region 202 .
  • a photoresist layer having a pattern of the source lead-out structure 114 is formed on the upper surface of the second dielectric layer 112; secondly, using the photoresist layer as a mask, the second dielectric layer 112 is etched to form a The lead-out groove of the dielectric layer 112, the lead-out groove exposes the source region 202 below the second dielectric layer 112, that is, the lead-out groove exposes the doped source in the source region 202; again, in the lead-out groove
  • the conductive material is filled to form the source lead-out structure 114 in contact with the source region 202 .
  • the conductive material forming the source lead-out structure 114 includes one or more of polysilicon, metal, conductive metal nitride, conductive metal oxide, and metal silicide, wherein the metal can be tungsten (W), Nickel (Ni) or titanium (Ti); conductive metal nitrides include titanium nitride (TiN); conductive metal oxides include iridium oxide (I rO 2 ); metal silicides include titanium silicide (TiSi).
  • the upper surface of the source lead-out structure 114 is higher than the upper surface of the second dielectric layer 112 .
  • the lower surface of the source extraction structure 114 is lower than the upper surface of the substrate 102 , and the lower surface of the source extraction structure 114 is not lower than the lower surface of the source.
  • the lower surface of the source extraction structure 114 is flush with the upper surface of the substrate 102 .
  • the source lead-out structure 114 on the source region 202 further includes:
  • a source metal line layer 116 is formed on the substrate 102 , the source metal line layer 116 is in contact with the source lead-out contact, and is used to lead the source to the upper surface of the resistive memory device.
  • FIG. 7 is a schematic diagram of an equivalent circuit of a resistive memory device in an embodiment corresponding to FIG. 6 . As shown in FIG. 7 , the arrowed curve in the figure indicates the flow direction of the current, the input end of the current is the source metal line layer 116 (SL), and the output end of the current is the bit line structure 210 (BL).
  • SL source metal line layer 116
  • BL bit line structure 210
  • the device includes a transistor 216 and a variable resistance structure 218, and the transistor 216 is composed of a source region 202, a gate structure 212 (that is, a word line structure WL, the gate structure 212 and the first dielectric layer 208 are jointly used as the gate of the transistor) and a drain
  • the variable resistance structure 218 is composed of the drain region 204 , the resistive material layer 206 between the drain region 204 and the bit line structure 210 , and the bit line structure 210 .
  • steps in the flow chart of FIG. 1 are displayed sequentially as indicated by the arrows, these steps are not necessarily executed sequentially in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order restriction on the execution of these steps, and these steps can be executed in other orders. Moreover, at least some of the steps in Fig. 1 may include multiple sub-steps or multiple stages, these sub-steps or stages are not necessarily executed at the same time, but may be executed at different times, the execution of these sub-steps or stages The order is not necessarily performed sequentially, but may be performed alternately or alternately with at least a part of other steps or sub-steps or stages of other steps.
  • the present application also provides a resistive memory device, including:
  • the base 102 specifically, the base 102 includes a substrate and different device regions formed on the substrate, the substrate can be undoped single crystal silicon, single crystal silicon doped with impurities, silicon on insulator (SOI) , silicon-on-insulator (SSOI), silicon-germanium-on-insulator (S-SiGeOI), silicon-germanium-on-insulator (SiGeOI), and germanium-on-insulator (GeOI), etc.
  • the constituent material of the substrate is selected from single crystal silicon;
  • Bit line trenches 108 are opened in the substrate 102;
  • the resistive material layer 206 is located on the sidewall and bottom of the bit line trench 108; under the action of an electrical signal such as an applied voltage or current, the resistive material layer 206 will undergo reversible transition between different resistance states, and the resistance state is usually Including high resistance state and low resistance state. It can be understood that the resistive switch material layer 206 may be a high-k material layer. In one embodiment, the resistive switch material layer 206 includes at least one of a hafnium oxide material layer or a tantalum oxide material layer.
  • the bit line structure 210 is filled in the bit line trench 108; the material of the bit line structure 210 may be titanium nitride material or metal tungsten material.
  • the bit line structure 210 on one side of the resistive material layer 206, the substrate 102 on the other side of the resistive material layer 206, and the resistive material layer 206 together constitute a variable resistance structure (MIM structure) in the resistive memory device. That is, the bit line structure 210 in the present application serves as an electrode in the MIM structure at the same time, and the resistive material layer 206 serves as a resistance switching layer in the MIM structure. Compared with the typical preparation process of separately forming the MIM structure, the process flow is simplified.
  • the variable resistance structure includes a bit line structure 210 and a resistive material layer 206, wherein the resistive material layer 206 is located on the sidewall and bottom of the bit line trench 108, and the bit line structure 210 is filled in the bit line trench In the groove 108, the bit line structure 210 and the resistive material layer 206 on the side wall of the bit line in the resistive memory device of the present application are used as a part of the variable resistance structure, and the variable resistance structure is formed at the same time as the bit line structure 210, which simplifies The process flow of the resistive memory device reduces the production cost, and at the same time reduces the size of the resistive memory device.
  • a shallow trench isolation structure 104 is formed in the substrate 102, and the shallow trench isolation structure 104 isolates an active region 106 arranged in an array in the substrate 102;
  • a resistive memory device also includes:
  • Gate trenches 110, each gate trench 110 and a bit line trench 108 span the same active region 106, and divide the active region 106 between the gate trench 110 and the shallow trench isolation structure 104 between the source region 202 and the drain region 204 between the gate trench 110 and the bit line trench 108; that is, the gate trench 110 and the bit line trench 108 pass through the same active region 106,
  • the active region 106 is divided into a source region 202 between the STI structure 104 and the gate trench 110 and a drain region 204 between the gate trench 110 and the bit line trench 108 .
  • the source region 202 and the drain region 204 can be doped according to actual needs to obtain the source and drain of the transistor in the resistive memory device respectively.
  • the doping depth of the source and the drain along the X direction is less than or equal to the depth of the gate trench 110 and the bit line trench 108 .
  • the X direction refers to the upward direction from the substrate 102
  • the Y direction refers to the direction intersecting with the extending direction of the bit line trench 108 .
  • the bit line trench 108 and the gate trench 110 have the same depth in the X direction and the same width in the Y direction. At this time, they can be formed by lithography equipment with the same overlay error Bit line trench 108 and gate trench 110 . In other embodiments, the shape of the bit line trench 108 and the gate trench 110 are different. At this time, according to the process requirements, the bit line trench 108 and the gate trench are formed by lithography equipment with the same or different overlay errors. 110.
  • bit line trench 108 and the gate trench 110 straddle the same active region 106, the bit line trench 108 and the adjacent shallow trench isolation structure in the Y direction
  • active region 106 between 104 that is, when a gate trench 110 and a bit line trench 108 pass through an active region 106, the active region 106 is divided into the shallow trench isolation structure 104 and the gate
  • the width W1 along the Y direction of the part of the active region 106 located between the bit line trench 108 and the adjacent STI structure 104 is smaller than or equal to the width W2 along the Y direction of the source region 202 .
  • the preparation method of the resistive memory device in this application can be compatible with the preparation method of the DRAM device, that is, at least part of the photolithography plate of the DRAM device can be used to prepare the resistive memory device, so that the process flow of the resistive memory device is simplified and has
  • the density of DRAM devices reduces production costs and realizes the high-density array design of resistive memory devices.
  • the size of resistive memory devices can reach 0.004 square microns, which is nearly 19 times smaller.
  • the bit line trench 108 and the gate trench 110 straddle the same active region 106 , they are in contact with the adjacent shallow trench isolation structure 104 in the Y direction, that is, an active
  • the active region 106 is divided into a source region 202 located between the shallow trench isolation structure 104 and the gate trench 110 and a source region 202 located between the shallow trench isolation structure 104 and the gate trench 110 .
  • variable resistance structure further includes a drain region 204 . That is, the substrate 102 on the other side of the resistive material layer 206 in the variable resistance structure refers to the drain electrode after doping. At this time, the drain electrode and the bit line structure 210 are respectively used as two electrodes of the variable resistance structure, located on the drain electrode. The resistive material layer 206 between the electrode and the bit line structure 210 serves as a resistance transition layer between two electrodes of the variable resistance structure.
  • bit line trenches 108 are formed in the shallow trench isolation structure 104 between the plurality of active regions 106 and adjacent active regions 106 . In other embodiments, the bit line trenches 108 are only formed in the plurality of active regions 106 .
  • the resistive memory device further includes:
  • the first dielectric layer 208 is located between the gate structure 212 and the sidewall of the gate trench 110 and between the gate structure 212 and the bottom of the gate trench 110 .
  • the active region 106 can be isolated from the gate structure 212 subsequently formed in the gate trench 110, wherein the active region 106 includes a source formed in the source region 202 and a drain formed in the drain.
  • the drain in pole region 204 is located between the gate structure 212 and the sidewall of the gate trench 110 and between the gate structure 212 and the bottom of the gate trench 110 .
  • the first dielectric layer 208 includes at least one of a hafnium oxide material layer, a silicon dioxide layer or a tantalum oxide material layer.
  • the first dielectric layer 208 is made of the same material as the resistive material layer 206 , for example, both are hafnium oxide material layers. Further, the first dielectric layer 208 and the resistive material layer 206 are formed simultaneously.
  • the resistive memory device further includes: a gate structure 212 filled in the gate trench 110 .
  • the gate structure 212 also serves as a word line structure (WL) in the resistive memory device.
  • the material of the bit line structure 210 and the gate structure 212 at least includes at least one of titanium nitride material, metal titanium material, metal tungsten material and doped polysilicon material.
  • the upper surface of the gate structure 212 is flush with the upper surface of the bit line structure 210 .
  • the upper surface of the bit line structure 210 is lower than the upper surface of the substrate 102 , that is, the bit line structure 210 is a buried bit line. In other embodiments, the upper surface of the bit line structure 210 is flush with the upper surface of the substrate 102 or the upper surface of the bit line structure 210 is higher than the upper surface of the substrate 102 .
  • the resistive memory device further includes: a protection layer 214 located on the bit line structure 210 and the gate structure 212 . Further, when the upper surface of the bit line structure 210 is lower than the upper surface of the substrate 102 , the upper surface of the protective layer 214 is flush with or higher than the upper surface of the substrate 102 .
  • the constituent materials of the protective layer 214 include one or more of oxides, nitrides, and oxynitrides, wherein the oxides include borophosphosilicate glass (BPSG), phosphosilicate glass (PSG), tetraethyl orthosilicate (TEOS), undoped silica glass (USG), spin-on-glass (SOG), high-density plasma (HDP) or spin-on-dielectric (SOD); nitrides include silicon nitride (SiN); oxynitrides include oxynitride Silicon (SiON).
  • oxides include borophosphosilicate glass (BPSG), phosphosilicate glass (PSG), tetraethyl orthosilicate (TEOS), undoped silica glass (USG), spin-on-glass (SOG), high-density plasma (HDP) or spin-on-dielectric (SOD); nitrides include silicon nitride (SiN);
  • the resistive memory device further includes:
  • the second dielectric layer 112 is located on the substrate 102 and is in contact with the passivation layer 214 .
  • the constituent materials of the second dielectric layer 112 include one or more of oxides, nitrides, and oxynitrides, wherein the oxides include borophosphosilicate glass (BPSG), phosphosilicate glass (PSG), Ethyl silicate (TEOS), undoped silica glass (USG), spin-on-glass (SOG), high-density plasma (HDP), or spin-on-dielectric (SOD); nitrides including silicon nitride (SiN); nitride The oxide includes silicon oxynitride (SiON).
  • the second dielectric layer 112 is located on the upper surface of the substrate 102 .
  • the second dielectric layer 112 includes a silicon dioxide layer on the upper surface of the substrate 102 .
  • the second dielectric layer 112 also includes a silicon nitride layer on the upper surface of the silicon dioxide layer.
  • the material of the second dielectric layer 112 is the same as that of the protection layer 214 .
  • the resistive memory device further includes: a source lead-out structure 114 located on the source region 202 , the source lead-out structure 114 penetrates the second dielectric layer 112 , and is connected to the source region 202 touch.
  • the conductive material forming the source lead-out structure 114 includes one or more of polysilicon, metal, conductive metal nitride, conductive metal oxide, and metal silicide, wherein the metal can be tungsten (W), Nickel (Ni) or titanium (Ti); conductive metal nitrides include titanium nitride (TiN); conductive metal oxides include iridium oxide (I rO 2 ); metal silicides include titanium silicide (TiSi).
  • the source extraction structure 114 is in contact with the doped source in the source region 202 .
  • the upper surface of the source lead-out structure 114 is higher than the upper surface of the second dielectric layer 112 .
  • the lower surface of the source extraction structure 114 is lower than the upper surface of the substrate 102 , and the lower surface of the source extraction structure 114 is not lower than the lower surface of the source.
  • the lower surface of the source extraction structure 114 is flush with the upper surface of the substrate 102 .
  • the resistive memory device further includes:
  • the source metal line layer 116 is located on the substrate 102 and is in contact with the source lead-out contact, and is used to lead the source to the upper surface of the resistive memory device.
  • FIG. 7 is a schematic diagram of an equivalent circuit of a resistive memory device in an embodiment corresponding to FIG. 6 . As shown in FIG. 7 , the arrowed curve in the figure indicates the flow direction of the current, the input end of the current is the source metal line layer 116 (SL), and the output end of the current is the bit line structure 210 (BL).
  • SL source metal line layer 116
  • BL bit line structure 210
  • the device includes a transistor 216 and a variable resistance structure 218, and the transistor 216 is composed of a source region 202, a gate structure 212 (that is, a word line structure WL, the gate structure 212 and the first dielectric layer 208 are jointly used as the gate of the transistor) and a drain
  • the variable resistance structure 218 is composed of the drain region 204 , the resistive material layer 206 between the drain region 204 and the bit line structure 210 , and the bit line structure 210 .
  • the resistive memory device is manufactured by using any one of the manufacturing methods for the resistive memory device described above.
  • the present application also provides a memory device, which includes the resistive memory device described in any one of the foregoing.

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Abstract

本申请实施例涉及一种阻变存储器件及其制备方法。该制备方法，包括：提供基底；于基底中形成位线沟槽；于位线沟槽的侧壁和底部形成阻变材料层；于位线沟槽中填充形成位线结构；其中，可变电阻结构包括位线结构、阻变材料层。本申请阻变存储器件中位线结构及位线侧壁的阻变材料层作为可变电阻结构的一部分，在形成位线结构的同时形成可变电阻结构，简化了阻变存储器件的工艺流程，降低了生产成本，同时减小了阻变存储器件的尺寸。

Description

阻变存储器件及其制备方法
本申请要求于2021年7月9日提交中国专利局，申请号为2021107797679，申请名称为“阻变存储器件及其制备方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请实施例涉及集成电路技术领域，特别是涉及一种阻变存储器件及其制备方法。
背景技术
典型的阻变式存储器件(RRAM)采是由平面晶体管和位于平面晶体管上方的MIM(金属-绝缘体-金属)结构构成，平面晶体管和MIM结构是在不同的工艺步骤中制备而成的，工艺流程复杂、尺寸较大，如何简化RRAM的工艺流程并形成小尺寸的RRAM结构成为亟需解决的问题。
发明内容
本申请实施例提供了一种阻变存储器件及其制备方法，可以优化阻变存储器件的工艺流程。
一种阻变存储器件的制备方法，包括：
提供基底；
于基底中形成位线沟槽；
于位线沟槽的侧壁和底部形成阻变材料层；
于位线沟槽中填充形成位线结构；
其中，可变电阻结构包括位线结构、阻变材料层。
本申请还提供一种阻变存储器件，包括：
基底；
位线沟槽，开设于基底中；
阻变材料层，位于位线沟槽的侧壁和底部；
位线结构，填充于位线沟槽中；
其中，可变电阻结构包括位线结构、阻变材料层。
上述阻变存储器件及其制备方法中，可变电阻结构包括位线结构和阻变材料层，其中，阻变材料层位于位线沟槽的侧壁和底部，位线结构填充于位线沟槽中，本申请阻变存储器件中位线结构及位线侧壁的阻变材料层作为可变电阻结构的一部分，在形成位线结构的同时形成可变电阻结构，简化了阻变存储器件的工艺流程，降低了生产成本，同时减小了阻变存储器件的尺寸。
附图说明
为了更清楚地说明本申请实施例或相关技术中的技术方案，下面将对实施例或相关技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为一实施例中阻变存储器件的制备方法的流程示意图；
图2为一实施例中形成栅极沟槽之后阻变存储器件的剖面示意图；
图3为另一实施例中形成栅极沟槽之后阻变存储器件的剖面示意图；
图4为图2对应的一实施例中形成第一介质层之后阻变存储器件的剖面示意图；
图5为图4对应的一实施例中形成栅极结构之后阻变存储器件的剖面示意图；
图6为图5对应的一实施例中形成第二介质层之后阻变存储器件的剖面示意图；
图7为图6对应的一实施例中阻变存储器件的等效电路示意图。
附图标记说明：
102、基底；104、浅沟槽隔离结构；106、有源区；108、位线沟槽；110、栅极沟槽；112、第二介质层；114、源极引出结构；116、源极金属线层；202、源极区；204、漏极区；206、阻变材料层；208、第一介质层；210、位线结构；212、栅极结构；214、保护层；216、晶体管；218、可变电阻结构。
具体实施方式
为了便于理解本申请实施例，下面将参照相关附图对本申请实施例进行更全面的描述。附图中给出了本申请实施例的首选实施例。但是，本申请实施例可以以许多不同的形式来实现，并不限于本文所描述的实施例。相反地，提供这些实施例的目的是使对本申请实施例的公开内容更加透彻全面。
除非另有定义，本文所使用的所有的技术和科学术语与属于本申请实施例的技术领域的技术人员通常理解的含义相同。本文中在本申请实施例的说明书中所使用的术语只是为了描述具体的实施例的目的，不是旨在于限制本申请实施例。本文所使用的术语“及/或”包括一个或多个相关的所列项目的任意的和所有的组合。
在本申请实施例的描述中，需要理解的是，术语“上”、“下”、“竖直”、“水平”、“内”、“外”等指示的方位或位置关系为基于附图所示的方法或位置关系，仅是为了便于描述本申请实施例和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请实施例的限制。
可以理解，本申请所使用的术语“第一”、“第二”等可在本文中用于描述各种元件，但这些元件不受这些术语限制。这些术语仅用于将第一个元件与另一个元件区分。举例来说，在不脱离本申请的范围的情况下，可以将第一客户端称为第二客户端，且类似地，可将第二客户端称为第一客户端。第一客户端和第二客户端两者都是客户端，但其不是同一客户端。
此外，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括至少一个该特征。在本申请的描述中，“多个”的含义是至少两个，例如两个，三个等，除非另有明确具体的限定。在本申请的描述中，“若干”的含义是至少一个，例如一个，两个等，除非另有明确具体的限定。
阻变存储器件(Resistive Random Access Memory,RRAM)是非电荷存储机制的存储器件，具有金属-绝缘体-金属的三明治结构，在特定的电压/电流激励下，其阻值可以在高阻态和低阻态之间相互转换，具有写入操作电压低、写入擦除时间短、记忆时间长、非破坏性读取、多值存储、结构简单以及存储密度高等优点，有望代替DRAM、SRAM和Flash等成为通用存储器。但是，与DRAM相比，RRAM的尺寸较大，单位面积内RRAM的数量较少，典型的使用两个FinFET的RRAM单元的尺寸为0.07632平方微米。
图1为一实施例中阻变存储器件的制备方法的流程示意图。图2为一实施例中形成栅极沟槽110之后阻变存储器件的剖面示意图。参见图1、图2，为解决上述问题，在本实施例中，提供一种阻变存储器件的制备方法，包括：
S102，提供基底102。
提供用于形成阻变存储器件的基底102，具体地，基底102包括衬底及形成在衬底上的不同器件区域，该衬底可以采用未掺杂的单晶硅、掺杂有杂质的单晶硅、绝缘体上硅 (SOI)、绝缘体上层叠硅(SSOI)、绝缘体上层叠锗化硅(S-SiGeOI)、绝缘体上锗化硅(SiGeOI)以及绝缘体上锗(GeOI)等。作为示例，在本实施例中，衬底的构成材料选用单晶硅。
S104，于基底102中形成位线沟槽108。
采用本领域技术人员熟知的光刻、刻蚀工艺，在基底102的预设位置形成位线沟槽108。
S106，于位线沟槽108的侧壁和底部形成阻变材料层206。
具体地，采用原子层沉积工艺、分子束外延工艺、射频磁控溅射工艺及化学气相沉积工艺中的任一种方式，在位线沟槽108的侧壁和底部形成阻变材料层206，在外加电压、电流等电信号的作用下阻变材料层206会在不同的电阻状态之间进行可逆的转变，电阻状态通常包括高阻态、低阻态两种。可以理解的是，阻变材料层206可以为高k材料层。在其中一个实施例中，阻变材料层206包括氧化铪材料层或氧化钽材料层中的至少一种。
S108，于位线沟槽108中填充形成位线结构210。
具体地，在位线沟槽108中填充形成位线结构210，位线结构210的材料可以为氮化钛材料或金属钨材料。此时，阻变材料层206一侧的位线结构210、阻变材料层206另一侧的基底102以及阻变材料层206共同构成阻变存储器件中的可变电阻结构(MIM结构)，即本申请中的位线结构210同时作为MIM结构中的一个电极，阻变材料层206作为MIM结构中的电阻转变层。与典型的单独形成MIM结构的制备工艺相比，简化了工艺流程。
上述阻变存储器件，可变电阻结构包括位线结构210和阻变材料层206，其中，阻变材料层206位于位线沟槽108的侧壁和底部，位线结构210填充于位线沟槽108中，本申请阻变存储器件中位线结构210及位线侧壁的阻变材料层206作为可变电阻结构的一部分，在形成位线结构210的同时形成可变电阻结构，简化了阻变存储器件的工艺流程，降低了生产成本，同时减小了阻变存储器件的尺寸。
如图2所示，在本实施例中，基底102内形成有浅沟槽隔离结构104，浅沟槽隔离结构104于基底102内隔离出阵列排布的有源区106；于基底102中形成位线沟槽108的同时，于基底102中形成栅极沟槽110，每一栅极沟槽110和一个位线沟槽108横跨同一有源区106，且将有源区106分为位于栅极沟槽110与浅沟槽隔离结构104之间的源极区202、位于栅极沟槽110与位线沟槽108之间的漏极区204。具体地，通过刻蚀工艺在基底102中同时形成位线沟槽108和栅极沟槽110，一个有源区106中同时有栅极沟槽110和位线沟槽108穿过，并将该有源区106分为位于浅沟槽隔离结构104与栅极沟槽110之间的源 极区202以及位于栅极沟槽110与位线沟槽108之间的漏极区204。后续可以根据实际需要对源极区202和漏极区204进行掺杂工艺，分别得到阻变存储器件中晶体管的源极和漏极。
在其他实施例中，基底102内形成有浅沟槽隔离结构104，浅沟槽隔离结构104于基底102内隔离出阵列排布的有源区106；于基底102中形成位线沟槽108后还包括：于基底102中形成栅极沟槽110的步骤，每一栅极沟槽110和一个位线沟槽108横跨同一有源区106，且将有源区106分为位于栅极沟槽110与浅沟槽隔离结构104之间的源极区202、位于栅极沟槽110与位线沟槽108之间的漏极区204。具体地，通过刻蚀工艺在基底102中分别形成位线沟槽108和栅极沟槽110，一个有源区106中同时有栅极沟槽110和位线沟槽108穿过，并将该有源区106分为位于浅沟槽隔离结构104与栅极沟槽110之间的源极区202以及位于栅极沟槽110与位线沟槽108之间的漏极区204。后续可以根据实际需要对源极区202和漏极区204进行掺杂工艺，分别得到阻变存储器件中晶体管的源极和漏极。
在其中一个实施例中，源极和漏极沿X方向的掺杂深度小于或等于栅极沟槽110及位线沟槽108的深度。其中，X方向指的是自基底102向上的方向，Y方向指的是与位线沟槽108延伸方向相交的方向。
继续参考图2，在其中一个实施例中，位线沟槽108、栅极沟槽110在X方向的深度和Y方向的宽度均相同，此时，可以通过套刻误差相同的光刻设备形成位线沟槽108和栅极沟槽110。在其他实施例中，位线沟槽108和栅极沟槽110的形貌不同，此时，根据工艺要求通过套刻误差相同或不同的光刻设备形成位线沟槽108和栅极沟槽110。
如图2所示，在其中一个实施例中，位线沟槽108与栅极沟槽110横跨同一有源区106的同时，在Y方向上位线沟槽108与相邻浅沟槽隔离结构104之间存在有源区106，即一个有源区106中同时有栅极沟槽110和位线沟槽108穿过时，将该有源区106分为位于浅沟槽隔离结构104与栅极沟槽110之间的源极区202、位于栅极沟槽110与位线沟槽108之间的漏极区204以及位于位线沟槽108和相邻浅沟槽隔离结构104之间的部分有源区106。进一步地，位于位线沟槽108和相邻浅沟槽隔离结构104之间的部分有源区106沿Y方向的宽度W1小于或等于源极区202沿Y方向的宽度W2。本申请中阻变存储器件的制备方法可以与DRAM器件的制备方法兼容，即至少可以使用DRAM器件的部分光刻版来制备阻变存储器件，使得阻变存储器件的工艺流程得到简化的同时具有DRAM器件的密度，降低了生产成本，实现了阻变存储器件高密度阵列设计，阻变存储器件尺寸可以达 到0.004平方微米，缩小了近19倍。
图3为另一实施例中形成栅极沟槽之后阻变存储器件的剖面示意图。参见图3，在本实施例中，位线沟槽108与栅极沟槽110横跨同一有源区106的同时，在Y方向上与相邻浅沟槽隔离结构104相接触，即一个有源区106中同时有栅极沟槽110和位线沟槽108穿过时，将该有源区106分为位于浅沟槽隔离结构104与栅极沟槽110之间的源极区202以及位于栅极沟槽110与位线沟槽108之间的漏极区204两部分。通过该设置，进一步缩小了阻变存储器件的尺寸。
在其中一个实施例中，可变电阻结构还包括漏极区204。即可变电阻结构中阻变材料层206另一侧的基底102指的是掺杂之后的漏极，此时，漏极、位线结构210分别作为可变电阻结构的两个电极，位于漏极和位线结构210之间的阻变材料层206作为可变电阻结构两个电极之间的电阻转变层。
在其中一个实施例中，位线沟槽108形成于多个有源区106及相邻有源区106之间的浅沟槽隔离结构104中。在其他实施例中，位线沟槽108仅形成于多个有源区106中。
图4为图2对应的一实施例中形成第一介质层208之后阻变存储器件的剖面示意图。如图4所示，在其中一个实施例中，于位线沟槽108的侧壁和底部形成阻变材料层206的同时，于栅极沟槽110的侧壁和底部形成第一介质层208。在其他实施例中，于位线沟槽108的侧壁和底部形成阻变材料层206之后或位线沟槽108的侧壁和底部形成阻变材料层206之前还包括：于栅极沟槽110的侧壁和底部形成第一介质层208的步骤。通过形成第一介质层208，可以隔离有源区106与后续形成于栅极沟槽110内的栅极结构212，其中有源区106包括形成在源极区202中的源极和形成在漏极区204中的漏极。
在其中一个实施例中，第一介质层208至少包括氧化铪材料层、二氧化硅层或氧化钽材料层中的至少一种。
在其中一个实施例中，第一介质层208与阻变材料层206的材料相同，例如均为氧化铪材料层。
图5为图4对应的一实施例中形成栅极结构212之后阻变存储器件的剖面示意图。如图5所示，在其中一个实施例中，于位线沟槽108中填充形成位线结构210的同时，于栅极沟槽110中填充形成栅极结构212。在其他实施例中，于位线沟槽108中填充形成位线结构210之后或于位线沟槽108中填充形成位线结构210之前还包括：于栅极沟槽110中填充形成栅极结构212的步骤。
在其中一个实施例中，位线结构210和栅极结构212的材料至少包括氮化钛材料、金 属钛材料、金属钨材料以及掺杂多晶硅材料中的至少一种。以下以位线结构210和栅极结构212的材料均为氮化钛进行示例性说明。
具体的，于位线沟槽108中填充形成位线结构210的同时，于栅极沟槽110中填充形成栅极结构212的步骤包括：第一步、通过淀积工艺在位线沟槽108和栅极沟槽110中填充形成氮化钛材料层。第二步、刻蚀去除多余的氮化钛材料层，得到由位线沟槽108中剩余氮化钛材料层构成的位线结构210，以及由栅极沟槽110中剩余氮化钛材料层构成的栅极结构212，其中，栅极结构212同时作为阻变存储器件中的字线结构(WL)。
在其中一个实施例中，栅极结构212的上表面与位线结构210的上表面相齐平。
如图5所示，在其中一个实施例中，位线结构210的上表面低于基底102的上表面，即位线结构210为埋入式位线。在其他实施例中，位线结构210的上表面与基底102的上表面相齐平或者位线结构210的上表面高于基底102的上表面。
图6为图5对应的一实施例中形成第二介质层112之后阻变存储器件的剖面示意图。参见图6，在其中一个实施例中，阻变存储器件的制备方法还包括：于位线结构210和栅极结构212上形成保护层214。进一步地，位线结构210的上表面低于基底102的上表面时，保护层214的上表面与基底102的上表面相齐平或高于基底102的上表面。具体地，首先，在位线沟槽108和栅极沟槽110中填满保护材料，保护材料的上表面高于基底102的上表面，且保护材料的覆盖在有源区106及浅沟槽隔离结构104上。其次，刻蚀去除高于基底102表面的保护材料。再次，进行化学平坦化处理，得到由剩余保护材料构成的上表面与基底102上表面齐平的保护层214。保护层214的构成材料包括氧化物、氮化物、氮氧化物中的一种或多种，其中，氧化物包括硼磷硅玻璃(BPSG)、磷硅玻璃(PSG)、正硅酸乙酯(TEOS)、未掺杂硅玻璃(USG)、旋涂玻璃(SOG)、高密度等离子体(HDP)或旋涂电介质(SOD)；氮化物包括氮化硅(SiN)；氮氧化物包括氮氧化硅(SiON)。
继续参考图6，在其中一个实施例中，于位线结构210和栅极结构212上形成保护层214之后还包括：于基底102上形成第二介质层112，第二介质层112与保护层214相接触。进一步地，第二介质层112的构成材料包括氧化物、氮化物、氮氧化物中的一种或多种，其中，氧化物包括硼磷硅玻璃(BPSG)、磷硅玻璃(PSG)、正硅酸乙酯(TEOS)、未掺杂硅玻璃(USG)、旋涂玻璃(SOG)、高密度等离子体(HDP)或旋涂电介质(SOD)；氮化物包括氮化硅(SiN)；氮氧化物包括氮氧化硅(SiON)。
在其中一个实施例中，第二介质层112位于基底102的上表面。典型地，第二介质层112包括位于基底102上表面的二氧化硅层。进一步地，第二介质层112还包括位于二氧 化硅层上表面的氮化硅层。
在其中一个实施例中，第二介质层112与保护层214的材料相同，此时，第二介质层112可以与保护层214同时形成，也可以与保护层214分开形成。
如图6所示，在其中一个实施例中，于基底102上形成第二介质层112之后还包括：
于源极区202上形成源极引出结构114，源极引出结构114贯穿第二介质层112，且与源极区202相接触。
具体地，首先，在第二介质层112的上表面形成具有源极引出结构114图案的光刻胶层；其次，以光刻胶层为掩膜，刻蚀第二介质层112形成贯穿第二介质层112的引出沟槽，所述引出沟槽露出第二介质层112下方的源极区202，即引出沟槽暴露出源极区202中掺杂的源极；再次，在引出沟槽中填充导电材料形成与源极区202相接触的源极引出结构114。进一步地，形成源极引出结构114的导电材料包括多晶硅、金属、导电性金属氮化物、导电性金属氧化物和金属硅化物中的一种或多种，其中，金属可以是钨(W)、镍(Ni)或钛(Ti)；导电性金属氮化物包括氮化钛(TiN)；导电性金属氧化物包括氧化铱(I rO 2)；金属硅化物包括硅化钛(TiSi)。
在其中一个实施例中，源极引出结构114的上表面高于第二介质层112的上表面。
在其中一个实施例中，源极引出结构114的下表面低于基底102的上表面，且源极引出结构114的下表面不低于源极的下表面。
在另一个实施例中，源极引出结构114的下表面与基底102的上表面相齐平。
如图6所示，在其中一个实施例中，于源极区202上形成源极引出结构114之后还包括：
于基底102上形成源极金属线层116，所述源极金属线层116与源极引出接触相接触，用于将源极引出到阻变存储器件的上表面。
图7为图6对应的一实施例中阻变存储器件的等效电路示意图。如图7所示，图中带箭头曲线标识电流的流动方向，电流的输入端为源极金属线层116(SL)，电流的输出端为位线结构210(BL)，其中，阻变存储器件包括晶体管216和可变电阻结构218，晶体管216是由源极区202、栅极结构212(即字线结构WL，栅极结构212和第一介质层208共同作为晶体管的栅极)以及漏极区204构成，可变电阻结构218由漏极区204、漏极区204与位线结构210之间的阻变材料层206、位线结构210构成。
应该理解的是，虽然图1的流程图中的各个步骤按照箭头的指示依次显示，但是这些步骤并不是必然按照箭头指示的顺序依次执行。除非本文中有明确的说明，这些步骤的执 行并没有严格的顺序限制，这些步骤可以以其它的顺序执行。而且，图1中的至少一部分步骤可以包括多个子步骤或者多个阶段，这些子步骤或者阶段并不必然是在同一时刻执行完成，而是可以在不同的时刻执行，这些子步骤或者阶段的执行顺序也不必然是依次进行，而是可以与其它步骤或者其它步骤的子步骤或者阶段的至少一部分轮流或者交替地执行。
如图2、图5所示，本申请还提供一种阻变存储器件，包括：
基底102，具体地，基底102包括衬底及形成在衬底上的不同器件区域，该衬底可以采用未掺杂的单晶硅、掺杂有杂质的单晶硅、绝缘体上硅(SOI)、绝缘体上层叠硅(SSOI)、绝缘体上层叠锗化硅(S-SiGeOI)、绝缘体上锗化硅(SiGeOI)以及绝缘体上锗(GeOI)等。作为示例，在本实施例中，衬底的构成材料选用单晶硅；
位线沟槽108，开设于基底102中；
阻变材料层206，位于位线沟槽108的侧壁和底部；在外加电压、电流等电信号的作用下阻变材料层206会在不同的电阻状态之间进行可逆的转变，电阻状态通常包括高阻态、低阻态两种。可以理解的是，阻变材料层206可以为高k材料层。在其中一个实施例中，阻变材料层206包括氧化铪材料层或氧化钽材料层中的至少一种。
位线结构210，填充于位线沟槽108中；位线结构210的材料可以为氮化钛材料或金属钨材料。此时，阻变材料层206一侧的位线结构210、阻变材料层206另一侧的基底102以及阻变材料层206共同构成阻变存储器件中的可变电阻结构(MIM结构)，即本申请中的位线结构210同时作为MIM结构中的一个电极，阻变材料层206作为MIM结构中的电阻转变层。与典型的单独形成MIM结构的制备工艺相比，简化了工艺流程。
上述阻变存储器件，可变电阻结构包括位线结构210和阻变材料层206，其中，阻变材料层206位于位线沟槽108的侧壁和底部，位线结构210填充于位线沟槽108中，本申请阻变存储器件中位线结构210及位线侧壁的阻变材料层206作为可变电阻结构的一部分，在形成位线结构210的同时形成可变电阻结构，简化了阻变存储器件的工艺流程，降低了生产成本，同时减小了阻变存储器件的尺寸。
如图2所示，在其中一个实施例中，基底102内形成有浅沟槽隔离结构104，浅沟槽隔离结构104于基底102内隔离出阵列排布的有源区106；阻变存储器件还包括：
栅极沟槽110，每一栅极沟槽110和一个位线沟槽108横跨同一有源区106，且将有源区106分为位于栅极沟槽110与浅沟槽隔离结构104之间的源极区202、位于栅极沟槽110与位线沟槽108之间的漏极区204；即一个有源区106中同时有栅极沟槽110和位线沟槽108穿过，将该有源区106分为位于浅沟槽隔离结构104与栅极沟槽110之间的源极 区202以及位于栅极沟槽110与位线沟槽108之间的漏极区204。后续可以根据实际需要对源极区202和漏极区204进行掺杂工艺，分别得到阻变存储器件中晶体管的源极和漏极。
在其中一个实施例中，源极和漏极沿X方向的掺杂深度小于或等于栅极沟槽110及位线沟槽108的深度。其中，X方向指的是自基底102向上的方向，Y方向指的是与位线沟槽108延伸方向相交的方向。
继续参考图2，在其中一个实施例中，位线沟槽108、栅极沟槽110在X方向的深度和Y方向的宽度均相同，此时，可以通过套刻误差相同的光刻设备形成位线沟槽108和栅极沟槽110。在其他实施例中，位线沟槽108和栅极沟槽110的形貌不同，此时，根据工艺要求通过套刻误差相同或不同的光刻设备形成位线沟槽108和栅极沟槽110。
如图2所示，在其中一个实施例中，位线沟槽108与栅极沟槽110横跨同一有源区106的同时，在Y方向上位线沟槽108与相邻浅沟槽隔离结构104之间存在有源区106，即一个有源区106中同时有栅极沟槽110和位线沟槽108穿过时，将该有源区106分为位于浅沟槽隔离结构104与栅极沟槽110之间的源极区202、位于栅极沟槽110与位线沟槽108之间的漏极区204以及位于位线沟槽108和相邻浅沟槽隔离结构104之间的部分有源区106。进一步地，位于位线沟槽108和相邻浅沟槽隔离结构104之间的部分有源区106沿Y方向的宽度W1小于或等于源极区202沿Y方向的宽度W2。本申请中阻变存储器件的制备方法可以与DRAM器件的制备方法兼容，即至少可以使用DRAM器件的部分光刻版来制备阻变存储器件，使得阻变存储器件的工艺流程得到简化的同时具有DRAM器件的密度，降低了生产成本，实现了阻变存储器件高密度阵列设计，阻变存储器件尺寸可以达到0.004平方微米，缩小了近19倍。
参见图3，在其他实施例中，位线沟槽108与栅极沟槽110横跨同一有源区106的同时，在Y方向上与相邻浅沟槽隔离结构104相接触，即一个有源区106中同时有栅极沟槽110和位线沟槽108穿过时，将该有源区106分为位于浅沟槽隔离结构104与栅极沟槽110之间的源极区202以及位于栅极沟槽110与位线沟槽108之间的漏极区204两部分。通过该设置，进一步缩小了阻变存储器件的尺寸。
在其中一个实施例中，可变电阻结构还包括漏极区204。即可变电阻结构中阻变材料层206另一侧的基底102指的是掺杂之后的漏极，此时，漏极、位线结构210分别作为可变电阻结构的两个电极，位于漏极和位线结构210之间的阻变材料层206作为可变电阻结构两个电极之间的电阻转变层。
在其中一个实施例中，位线沟槽108形成于多个有源区106及相邻有源区106之间的 浅沟槽隔离结构104中。在其他实施例中，位线沟槽108仅形成于多个有源区106中。
如图4所示，在其中一个实施例中，阻变存储器件还包括：
第一介质层208，位于栅极结构212与栅极沟槽110的侧壁及栅极结构212与栅极沟槽110的底部之间。通过形成第一介质层208，可以隔离有源区106与后续形成于栅极沟槽110内的栅极结构212，其中有源区106包括形成在源极区202中的源极和形成在漏极区204中的漏极。
在其中一个实施例中，第一介质层208至少包括氧化铪材料层、二氧化硅层或氧化钽材料层中的至少一种。
在其中一个实施例中，第一介质层208与阻变材料层206的材料相同，例如均为氧化铪材料层。进一步地，第一介质层208与阻变材料层206是同时形成的。
如图5所示，在其中一个实施例中，阻变存储器件还包括：栅极结构212，填充于栅极沟槽110中。其中，栅极结构212同时作为阻变存储器件中的字线结构(WL)。在其中一个实施例中，位线结构210和栅极结构212的材料至少包括氮化钛材料、金属钛材料、金属钨材料以及掺杂多晶硅材料中的至少一种。
在其中一个实施例中，栅极结构212的上表面与位线结构210的上表面相齐平。
如图5所示，在其中一个实施例中，位线结构210的上表面低于基底102的上表面，即位线结构210为埋入式位线。在其他实施例中，位线结构210的上表面与基底102的上表面相齐平或者位线结构210的上表面高于基底102的上表面。
如图6所示，在其中一个实施例中，阻变存储器件还包括：保护层214，位于位线结构210和栅极结构212上。进一步地，位线结构210的上表面低于基底102的上表面时，保护层214的上表面与基底102的上表面相齐平或高于基底102的上表面。保护层214的构成材料包括氧化物、氮化物、氮氧化物中的一种或多种，其中，氧化物包括硼磷硅玻璃(BPSG)、磷硅玻璃(PSG)、正硅酸乙酯(TEOS)、未掺杂硅玻璃(USG)、旋涂玻璃(SOG)、高密度等离子体(HDP)或旋涂电介质(SOD)；氮化物包括氮化硅(SiN)；氮氧化物包括氮氧化硅(SiON)。
继续参考图6，在其中一个实施例中，阻变存储器件还包括：
第二介质层112，位于基底102上，且与保护层214相接触。进一步地，第二介质层112的构成材料包括氧化物、氮化物、氮氧化物中的一种或多种，其中，氧化物包括硼磷硅玻璃(BPSG)、磷硅玻璃(PSG)、正硅酸乙酯(TEOS)、未掺杂硅玻璃(USG)、旋涂玻璃(SOG)、高密度等离子体(HDP)或旋涂电介质(SOD)；氮化物包括氮化硅(SiN)； 氮氧化物包括氮氧化硅(SiON)。
在其中一个实施例中，第二介质层112位于基底102的上表面。典型地，第二介质层112包括位于基底102上表面的二氧化硅层。进一步地，第二介质层112还包括位于二氧化硅层上表面的氮化硅层。
在其中一个实施例中，第二介质层112与保护层214的材料相同。
继续参考图6，在其中一个实施例中，阻变存储器件还包括：源极引出结构114，位于源极区202上，源极引出结构114贯穿第二介质层112，且与源极区202相接触。进一步地，形成源极引出结构114的导电材料包括多晶硅、金属、导电性金属氮化物、导电性金属氧化物和金属硅化物中的一种或多种，其中，金属可以是钨(W)、镍(Ni)或钛(Ti)；导电性金属氮化物包括氮化钛(TiN)；导电性金属氧化物包括氧化铱(I rO 2)；金属硅化物包括硅化钛(TiSi)。源极引出结构114与源极区202中掺杂的源极相接触。
在其中一个实施例中，源极引出结构114的上表面高于第二介质层112的上表面。
在其中一个实施例中，源极引出结构114的下表面低于基底102的上表面，且源极引出结构114的下表面不低于源极的下表面。
在另一个实施例中，源极引出结构114的下表面与基底102的上表面相齐平。
继续参考图6，在其中一个实施例中，阻变存储器件还包括：
源极金属线层116，位于基底102上，且与源极引出接触相接触，用于将源极引出到阻变存储器件的上表面。
图7为图6对应的一实施例中阻变存储器件的等效电路示意图。如图7所示，图中带箭头曲线标识电流的流动方向，电流的输入端为源极金属线层116(SL)，电流的输出端为位线结构210(BL)，其中，阻变存储器件包括晶体管216和可变电阻结构218，晶体管216是由源极区202、栅极结构212(即字线结构WL，栅极结构212和第一介质层208共同作为晶体管的栅极)以及漏极区204构成，可变电阻结构218由漏极区204、漏极区204与位线结构210之间的阻变材料层206、位线结构210构成。
在其中一个实施例中，阻变存储器件是采用上述任一项所述的阻变存储器件的制备方法制成的。
本申请还提供一种存储设备，所述存储设备包括上述任一项所述的阻变存储器件。
以上所述实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例中的各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。
以上所述实施例仅表达了本申请实施例的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对发明专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本申请实施例构思的前提下，还可以做出若干变形和改进，这些都属于本申请实施例的保护范围。因此，本申请实施例专利的保护范围应以所附权利要求为准。

Claims (18)

  1. 一种阻变存储器件的制备方法，包括：
    提供基底；
    于所述基底中形成位线沟槽；
    于所述位线沟槽的侧壁和底部形成阻变材料层；
    于所述位线沟槽中填充形成位线结构；
    其中，可变电阻结构包括所述位线结构、所述阻变材料层。
  2. 根据权利要求1所述的制备方法，其中，所述阻变材料层包括氧化铪材料层或氧化钽材料层中的至少一种。
  3. 根据权利要求1所述的制备方法，其中，所述位线结构的上表面低于所述基底的上表面。
  4. 根据权利要求1所述的制备方法，其中，所述基底内形成有浅沟槽隔离结构，所述浅沟槽隔离结构于所述基底内隔离出阵列排布的有源区；所述于所述基底中形成位线沟槽的同时，于所述基底中形成栅极沟槽，每一所述栅极沟槽和一个所述位线沟槽横跨同一所述有源区，且将所述有源区分为位于所述栅极沟槽与所述浅沟槽隔离结构之间的源极区、位于所述栅极沟槽与所述位线沟槽之间的漏极区。
  5. 根据权利要求4所述的制备方法，其中，所述可变电阻结构还包括所述漏极区。
  6. 根据权利要求4所述的制备方法，其中，所述于所述位线沟槽的侧壁和底部形成阻变材料层的同时，于所述栅极沟槽的侧壁和底部形成第一介质层。
  7. 根据权利要求6所述的制备方法，其中，所述第一介质层与所述阻变材料层的材料相同。
  8. 根据权利要求4所述的制备方法，其中，所述于所述位线沟槽中填充形成所述位线结构的同时，于所述栅极沟槽中填充形成栅极结构。
  9. 根据权利要求8所述的制备方法，其中，所述栅极结构的上表面与所述位线结构的上表面相齐平。
  10. 根据权利要求8所述的制备方法，还包括：
    于所述位线结构和所述栅极结构上形成保护层，所述保护层与所述基底的上表面相齐平；
    于所述基底上形成第二介质层，所述第二介质层与所述保护层相接触。
  11. 根据权利要求10所述的制备方法，还包括：所述于所述基底上形成第二介质层之 后，
    于源极区上形成源极引出结构，所述源极引出结构贯穿所述第二介质层，且与所述源极区相接触。
  12. 一种阻变存储器件，包括：
    基底；
    位线沟槽，开设于所述基底中；
    阻变材料层，位于所述位线沟槽的侧壁和底部；
    位线结构，填充于所述位线沟槽中；
    其中，可变电阻结构包括所述位线结构、所述阻变材料层。
  13. 根据权利要求12所述的阻变存储器件，其中，所述阻变材料层包括氧化铪材料层或氧化钽材料层中的至少一种。
  14. 根据权利要求12所述的阻变存储器件，其中，所述位线结构的上表面低于所述基底的上表面。
  15. 根据权利要求12所述的阻变存储器件，其中，所述基底内形成有浅沟槽隔离结构，所述浅沟槽隔离结构于所述基底内隔离出阵列排布的有源区；所述阻变存储器件还包括：
    栅极沟槽，每一所述栅极沟槽和一个所述位线沟槽横跨同一所述有源区，且将所述有源区分为位于所述栅极沟槽与所述浅沟槽隔离结构之间的源极区、位于所述栅极沟槽与所述位线沟槽之间的漏极区；
    栅极结构，填充于所述栅极沟槽中；
    其中，所述可变电阻结构还包括所述漏极区。
  16. 根据权利要求15所述的阻变存储器件，还包括：
    第一介质层，位于所述栅极结构与所述栅极沟槽的侧壁及所述栅极结构与所述栅极沟槽的底部之间。
  17. 根据权利要求16所述的阻变存储器件，其中，所述第一介质层与所述阻变材料层的材料相同。
  18. 根据权利要求15所述的阻变存储器件，还包括：
    保护层，位于所述位线结构和所述栅极结构上，所述保护层与所述基底的上表面相齐平；
    第二介质层，位于所述基底上，且与所述保护层相接触；
    源极引出结构，位于所述源极区上，所述源极引出结构贯穿所述第二介质层，且与所 述源极区相接触。
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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8395139B1 (en) * 2011-12-06 2013-03-12 Nanya Technology Corp. 1T1R resistive memory device and fabrication method thereof
CN108899309A (zh) * 2018-06-27 2018-11-27 长鑫存储技术有限公司 埋入式字线结构及其制作方法
US20200035915A1 (en) * 2018-07-24 2020-01-30 International Business Machines Corporation TIGHTLY INTEGRATED 1T1R ReRAM FOR PLANAR TECHNOLOGY
CN112397508A (zh) * 2019-08-15 2021-02-23 长鑫存储技术有限公司 存储器件、半导体结构及其制造方法
US20210167129A1 (en) * 2019-12-03 2021-06-03 International Business Machines Corporation Resistive random access memory integrated with vertical transport field effect transistors

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8395139B1 (en) * 2011-12-06 2013-03-12 Nanya Technology Corp. 1T1R resistive memory device and fabrication method thereof
CN108899309A (zh) * 2018-06-27 2018-11-27 长鑫存储技术有限公司 埋入式字线结构及其制作方法
US20200035915A1 (en) * 2018-07-24 2020-01-30 International Business Machines Corporation TIGHTLY INTEGRATED 1T1R ReRAM FOR PLANAR TECHNOLOGY
CN112397508A (zh) * 2019-08-15 2021-02-23 长鑫存储技术有限公司 存储器件、半导体结构及其制造方法
US20210167129A1 (en) * 2019-12-03 2021-06-03 International Business Machines Corporation Resistive random access memory integrated with vertical transport field effect transistors

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