WO2023274163A1 - 多通道信号合成电路及多通道信号合成方法 - Google Patents

多通道信号合成电路及多通道信号合成方法 Download PDF

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WO2023274163A1
WO2023274163A1 PCT/CN2022/101583 CN2022101583W WO2023274163A1 WO 2023274163 A1 WO2023274163 A1 WO 2023274163A1 CN 2022101583 W CN2022101583 W CN 2022101583W WO 2023274163 A1 WO2023274163 A1 WO 2023274163A1
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signal
phase
radio frequency
channel
circuit
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PCT/CN2022/101583
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English (en)
French (fr)
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欧杰
张勇
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中兴通讯股份有限公司
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Publication of WO2023274163A1 publication Critical patent/WO2023274163A1/zh

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/005—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission adapting radio receivers, transmitters andtransceivers for operation on two or more bands, i.e. frequency ranges
    • H04B1/0067—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission adapting radio receivers, transmitters andtransceivers for operation on two or more bands, i.e. frequency ranges with one or more circuit blocks in common for different bands
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
    • H03L7/0891—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses the up-down pulses controlling source and sink current generators, e.g. a charge pump
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/093—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using special filtering or amplification characteristics in the loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission

Definitions

  • the embodiments of the present application relate to the field of electronic circuits, and in particular to a multi-channel signal synthesis circuit and a multi-channel signal synthesis method.
  • the multi-channel synthesis technology used in 5G, microwave and millimeter wave frequency band communication equipment has strict requirements on the phase relationship between the signals of each channel. Through the precise adjustment of the phase relationship between the signals of each channel, the synthesis of signal power is realized. In traditional multi-channel synthesis technology, phase adjustment can be performed on the baseband path, radio frequency path, or local oscillator path of each channel.
  • the phase relationship adjustment between each radio frequency channel is realized to achieve signal synthesis.
  • Purpose That is, the phase adjustment of the signal is directly performed on the radio frequency signal path.
  • use a shared local oscillator circuit and divide the local oscillator signal into multiple channels, and give it to the frequency converter of each channel respectively.
  • a phase shifter is added after the local oscillator power division circuit to adjust the phase of the local oscillator signal on each local oscillator signal path, realize the adjustment of the phase relationship of the output radio frequency signal of each channel, and achieve the purpose of signal synthesis. Since the same local oscillator signal is sent to each channel through the power dividing circuit, the routing of the local oscillator signal of each channel has strict requirements, which limits the application in the single board. Or in multi-channel, the baseband circuit directly adjusts the phase of the output signal, and finally realizes the phase change between multiple channels, and realizes the signal output synthesis.
  • phase adjustment the adjustment range of the phase through the baseband circuit is limited, and the phase adjustment directly on the radio frequency path will cause signal loss, and the processing of the local oscillator signal output by the local oscillator circuit requires multiple high-performance microwave shifters. Phase device, the cost is higher.
  • An embodiment of the present application provides a multi-channel signal synthesis circuit, including: N signal channels with the same circuit structure, a multi-port combiner connected to the N signal channels, a control loop connected to the multi-port combiner, and The clock unit connected to the control loop, N is an integer greater than 1; the clock unit is used to output the local oscillator signal to each signal channel; wherein, the local oscillator signal is generated according to the reference signal after phase shifting; the signal channel is used to The vibration signal generates the radio frequency signal of this channel; the multi-port combiner is used to synthesize the radio frequency signals output by N signal channels into one radio frequency signal and then output it; the control loop is used to output the control to the clock unit according to the synthesized radio frequency signal The signal is used for the clock unit to adjust the phase that the reference signal needs to move according to the control signal.
  • An embodiment of the present application provides a multi-channel signal synthesis method, including: phase-shifting the reference signals generated by the clock source respectively; generating local oscillator signals according to the phase-shifted reference signals; combining the local oscillator signals and Each baseband signal corresponding to each local oscillator signal is mixed to generate each radio frequency signal; each radio frequency signal is synthesized, and one synthesized radio frequency signal is output; the synthesized radio frequency signal is obtained for adjusting the reference signal that needs to be moved phase.
  • FIG. 1 is a schematic diagram of a multi-channel signal synthesis circuit provided according to an embodiment of the present application
  • FIG. 2 is a schematic diagram of a clock unit provided according to an embodiment of the present application.
  • FIG. 3 is a schematic diagram of a multi-channel signal synthesis circuit provided according to another embodiment of the present application.
  • Fig. 4 is a schematic diagram of an application scenario provided according to an embodiment of the present application.
  • first and second in the embodiments of the present application are used for description purposes only, and cannot be understood as indicating or implying relative importance or implicitly indicating the quantity of indicated technical features. Thus, the features defined as “first” and “second” may explicitly or implicitly include at least one of these features.
  • the terms “including” and “having” and any variations thereof are intended to cover non-exclusive inclusion. For example, a system, product or equipment comprising a series of components or units is not limited to the listed components or units, but optionally also includes components or units not listed, or optionally also includes Other parts or units inherent in equipment.
  • “plurality” means at least two, such as two, three, etc., unless otherwise specifically defined.
  • One embodiment of the present application relates to a signal synthesis circuit. As shown in Figure 1, specifically include:
  • N signal channels 100 with the same circuit structure a multi-port combiner 200 connected to the N signal channels 100, a control loop 300 connected to the multi-port combiner 200, and a clock unit 400 connected to the control loop 300;
  • the clock unit 400 is used to output a local oscillator signal to each signal channel 100; wherein, the local oscillator signal is generated according to the phase-shifted reference signal;
  • the signal channel 100 is used to generate a radio frequency signal of the channel according to the baseband signal and the local oscillator signal;
  • a multi-port combiner 200 configured to synthesize the radio frequency signals output by the N signal channels 100 into one radio frequency signal and then output it;
  • the control loop 300 is used to output a control signal to the clock unit 400 according to the synthesized radio frequency signal, so that the clock unit 400 can adjust the phase of the reference signal to be moved according to the control signal.
  • This application adjusts the local oscillator signal by adding a phase shift function on the path generated by the local oscillator signal, indirectly affects the output signal of each channel by adjusting the local oscillator signal, and at the same time detects the output signal at the signal output port, and closes the adjustment result Feedback to the clock unit, and circularly optimize the phase adjustment results to realize the synthesis of multi-channel signals and achieve low-cost and high-quality multi-channel signal synthesis. It avoids the power or signal quality loss caused by directly inserting the phase shifting unit on the radio frequency path, greatly improves the effect of signal synthesis, and brings about a significant increase in the total signal power of the device and an increase in the transmission distance. Compared with a single After the local oscillator signal is generated, the cost of adjusting it through a power amplifier circuit and a high-performance phase shifting unit is significantly reduced.
  • the signal channel 100 is the structure for generating the main signal.
  • the radio frequency signal of this channel is generated according to the baseband signal and the local oscillator signal. Since the multi-channel signal synthesis technology requires that the phases between the channels are consistent, a better synthesis result can be obtained, that is, it is necessary for each channel A phase adjustment structure is set so that multiple channels can realize signal synthesis.
  • the clock unit 400 before the clock unit 400 outputs the local oscillator signal to each signal channel 100 to generate, the clock unit 400 has already adjusted the phase of the reference signal, that is, the phases of the output local oscillator signals have been matched so that the corresponding signal channels The condition that the phases of 100 are consistent enables the signals of each signal channel 100 to be synthesized with high quality.
  • each signal channel 100 can be implemented in a single board or structure, or multiple channels can be implemented in a single board or structure; the multi-port combiner 200 can be implemented in a microstrip line structure, and the microstrip line
  • the structural form is not limited, and it can also be realized in the form of a cavity structure.
  • the clock unit 400 includes: a clock source 420, a drive and distribution circuit 430 connected to the clock source 420, N phase shifting units 410 respectively connected to N output ports of the drive and distribution circuit 430, and N
  • the N phase-locked loop circuits 440 connected to the phase-shifting units 410 respectively, and the N phase-shifting units 410 correspond to the N phase-locked loop circuits 440 one by one;
  • the clock source 420 is used to provide a reference signal;
  • the driving and distribution circuit 430 It is used to transmit the reference signal to N phase shifting units 410 respectively;
  • N phase shifting units 410 are used to perform phase shift adjustment on the reference signal transmitted by the driving and distribution circuit 430, and transmit it to the corresponding phase locked loop circuit 440;
  • N phase-locked loop circuits 440 are configured to generate local oscillator signals based on the phase-shifted and adjusted reference signals.
  • the same clock source 420 is adopted, and a phase shift unit 410 is set between the drive and distribution circuit 430 and the phase-locked loop circuit 440, and the phase shift unit 410 can adjust the reference clock source 420 sent by the drive and distribution circuit 430.
  • the reference signal is the original signal used to generate the local oscillator signal
  • the phase-shift adjustment of the reference signal can also affect the phase of the local oscillator signal
  • the local oscillator signal participates in adjusting the output of each signal channel 100, that is to say, through the
  • the phase adjustment of the reference signal before generating the local oscillator signal can adjust the phase of each signal channel 100, so that each signal channel can realize the purpose of signal synthesis.
  • the phase shift unit 410 is set before the local oscillator signal is generated to reduce the performance requirements of the phase shift unit 410, and the adjustable The range is wide, and the cost and circuit complexity are reduced under the premise of ensuring that the phase requirements are met.
  • the clock source 420 can be a crystal, a clock circuit, or other clock signals, and the clock signal can come from the device or an external device;
  • the phase shift unit 410 can be implemented by a phase shifter device or a phase shift circuit , can also be realized by a time-delay line combination switch or a time-delay circuit, as long as the purpose and function of phase adjustment can be realized, and the device or device for realization is not limited.
  • the PLL circuit 440 includes: a phase detector 441, a charge pump 442 connected to the phase detector 441, a loop filter 443 connected to the charge pump 442, a voltage-controlled loop filter connected to the loop filter 443
  • An oscillator 444 , the voltage-controlled oscillator 444 is also connected to the phase detector 441 through a frequency divider 445 ; the voltage-controlled oscillator 444 is used to output local oscillator signals to the N signal channels 110 .
  • the clock unit including the phase-locked loop circuit 440 is shown in FIG. 2 .
  • control loop 300 is connected to N phase shifting units 410 respectively, and outputs control signals to the N phase shifting units 410 respectively.
  • the phase-locked loop circuit 440 processes the phase-shifted reference signal to generate a local oscillator signal, so as to achieve the purpose of adjusting the signal generation process on the signal channel 100 .
  • the phase-locked loop circuit 440 can be an independent circuit, or an integrated specific chip; or the phase-locked loop circuit 440 structure except the voltage-controlled oscillator 444 is an integrated chip or circuit, and the voltage-controlled oscillator 444 is A separate chip or separate circuit to reduce the complexity of the PLL chip.
  • control loop 300 includes: a detection module 310 connected to the multi-port combiner 200 and a CPU controller 320 connected to the detection module 310;
  • the final RF signal is converted into a data format or signal usable by the CPU controller 320 ;
  • the CPU controller 320 is configured to output a control signal to the clock unit 400 according to the data obtained from the detection module 310 .
  • the control loop 300 is used to detect whether the synthesized signal output by the multi-port combiner 200 satisfies the preset output condition. If not, the CPU controller 320 sends a control signal to the clock unit 400, and the signals of each signal channel 100 are processed. Phase adjustment to optimize the synthesis quality of the signal, and finally achieve the conditions of the preset synthesis signal.
  • the first end of the CPU controller 320 is connected to N phase shifting units 410, and the second end of the CPU controller is connected to the detection module 310; the CPU controller 320 outputs N control signals, and the N control signals are used to control the N phase shifting units 410 respectively.
  • the CPU controller 320 receives the signal data transmitted by the detection module 310, and judges whether the signal data satisfies the preset output condition, if not, then outputs a corresponding control signal to the phase shifting unit 410 based on the current output signal, and controls each phase shifting
  • the unit 410 needs to adjust the phase; each phase shifting unit 410 adjusts the reference signal sent by the clock source 420 to the phase-locked loop circuit 440 , and finally achieves the purpose of correcting the signal phase of the multi-channel signal channel 100 .
  • the detection module 310 includes: a coupler 311, a detection circuit 312 connected to the coupler 311; the coupler 311 is connected to the multiport combiner 200; the first end of the detection circuit 312 is connected to the coupler 311, and A second terminal of the circuit 312 is connected to a CPU controller 320 .
  • the coupler 311 is used to obtain the output signal from the multi-port combiner 200, and the signal is embodied as a power value, and the coupler 311 transmits the signal power value obtained from the multi-port combiner 200 to the detection circuit 312, and the detection circuit 312 converts the signal power value obtained from the coupler 311 into a voltage value available to the CPU controller 320 .
  • the detection module 310 is used to obtain the composite signal result of multiple channels from the multi-port combiner 200, and process it into a data value available to the CPU controller 320, for example, the detection circuit 312 processes it into a value that the CPU controller 320 can process voltage value.
  • the detection circuit 312 can be a specific detector chip, or a detection function circuit realized by a group of devices;
  • the coupler 311 can be a microstrip coupler integrated on a single board, and the form is not limited, and it can also be cavity coupler.
  • N signal channels 100 include: a baseband unit 101, a first filter 102 connected to the baseband unit 101, a variable gain amplifier 103 connected to the first filter 102, and a variable gain amplifier 103 connected
  • each module is not limited to be composed of one or more devices; it may also be realized by a combination of several functional devices, and only need to realize corresponding functions.
  • the related structures of the signal channel 100 and the control loop 300 are shown in the signal synthesis circuit, as shown in FIG. 3 .
  • the present application utilizes adding a phase shift unit 410 on the reference signal path for generating the local oscillator signal, through detection by the detector circuit at the synthesized port, feedback and adjustment of the phase change on the reference signal path, and indirectly realizes the adjustment of the high frequency and
  • the phase adjustment on the millimeter-wave signal path realizes the adjustment of the phase relationship between multi-channel signals, and finally achieves the purpose of power synthesis between channels.
  • each channel adopts the same structure circuit; each local oscillator signal between multiple signal channels 100 comes from the same clock source 420; the clock source 420 passes through the driving and distribution circuit 430 respectively To each phase-locked loop circuit 440 that generates local oscillator signals; there is a phase shift unit 410 between the drive and distribution circuit 430 and the phase-locked loop circuit 440 that generates local oscillator signals; the output ports of multiple signal channels 100 are connected to the multi-port On the combiner 200; the output port of the multi-port combiner 200 also has the detection module 310 of the control loop 300; the output signal data of the detection module 310 is given to the CPU controller 320, and the CPU controller 320 is synchronously connected to the moving parts of each signal channel 100 On the phase unit 410; the CPU controller 320 adjusts the phase of each signal channel 100 through the feedback of the detection module 310; when the phase relationship of each signal channel 100 satisfies a certain condition, superposition and synthesis are realized at the output port of
  • the reference signal is adjusted by adding a phase shift unit 410 on the path generated by the local oscillator signal, and the reference signal is used to generate the local oscillator signal, which indirectly affects the output of each signal channel 100 by adjusting the local oscillator signal, and at the same time in the multi-port combiner 200
  • the output port detects the output signal, and feedbacks the adjustment result to the phase shifting unit 410 in a closed loop, and circularly optimizes the phase adjustment result to realize the synthesis of multiple signals. It avoids the power loss or signal quality damage caused by directly inserting the phase shift unit 410 on the signal channel 100, greatly improves the effect of signal synthesis, and brings about a significant increase in the total signal power of the device and an increase in the transmission distance.
  • the cost of adjusting through a power amplifier circuit and a high-performance phase shifting unit after a single local oscillator signal is generated is significantly reduced.
  • phase-shifting unit 410 Since the reference signal is a low-frequency signal, adding a phase-shifting unit 410 to the low-frequency signal path indirectly achieves the purpose of adjusting the phase of high-frequency signals such as local oscillator signals, and avoids directly inserting the power introduced by the phase-shifting unit 410 into the signal channel 100 or The loss of signal quality reduces the combination loss caused by the phase error and greatly improves the effect of power combination.
  • the realization of the phase shift unit 410 on the low-frequency signal has a simple structure, high precision of phase adjustment, and a large range of phase adjustment, which is enough to compensate the phase difference introduced on the main signal channel 100 due to signal routing and signal paths, and realize multiple The phase alignment of the channel output port achieves the effect of signal synthesis.
  • This solution greatly reduces the problem of multi-channel synthesis on 5G, microwave, and millimeter-wave frequency band devices, and solves the bottleneck of multi-channel synthesis on high-frequency bands. It is a great supplement and improvement to the multi-channel synthesis method. Simultaneously, the structure is simple, the circuit is reliable and effective, and has great practical value.
  • Radio 1 and Radio 2 are communication transmission devices on two sites respectively.
  • Multi-channel synthesis technology it is possible to increase the transmission signal power level of communication equipment by synthesizing multi-channel signals, thereby increasing the transmission distance between two sites, and at the same time improving the system gain margin and the availability of transmission links.
  • One embodiment of the present application relates to a signal synthesis method. Specifically include:
  • the reference signals generated by the clock source are phase-shifted respectively; the local oscillator signals are generated according to the phase-shifted reference signals; the local oscillator signals are mixed with the baseband signals corresponding to the local oscillator signals to generate each radio frequency signal; synthesize each radio frequency signal, and output one synthesized radio frequency signal; obtain the synthesized radio frequency signal, and use it to adjust the phase of the reference signal that needs to be moved.
  • the synthesized radio frequency signal is obtained to adjust the phase of the reference signal that needs to be moved; wherein, the preset condition includes: executing according to a preset time period, executing at a preset time node, or at other preset Executed when the condition is triggered.
  • the user's instruction can also be accepted for activation.
  • the time period for phase adjustment by the control loop 300 for signal synthesis, the time node for adjustment, or other conditions for triggering phase adjustment are preset.
  • the phase shifting unit 410 will not receive the real-time adjustment signal, and the clock unit 400 will synthesize the signal according to the predetermined phase adjustment conditions; when the control loop 300 is triggered to work, the synthesized signal will be monitored in real time, And feedback adjusts the phase conditions of each phase shifting unit 410, optimizes the phase relationship of each signal, and improves the quality of the synthesized signal.

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  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
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  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Abstract

本申请实施例涉及电子电路领域，公开了一种多通道信号合成电路及多通道信号合成方法。具体包括：电路结构相同的N个信号通道100、与N个信号通道100连接的多端口合路器200、与多端口合路器200连接的控制回路300、与控制回路300连接的时钟单元400；时钟单元400用于向各信号通道100输出本振信号；信号通道100用于根据基带信号和本振信号生成本通道的射频信号；多端口合路器200，用于将N个信号通道100输出的射频信号合成为一路射频信号后输出；控制回路300用于根据合成后的射频信号，向时钟单元400输出控制信号，供时钟单元400根据控制信号调整参考信号需要移动的相位。

Description

多通道信号合成电路及多通道信号合成方法
交叉引用
本申请基于申请号为“202110721963.0”、申请日为2021年06月28日的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此以引入方式并入本申请。
技术领域
本申请实施例涉及电子电路领域，特别涉及一种多通道信号合成电路及多通道信号合成方法。
背景技术
目前5G、微波及毫米波频段通信设备上采用的多通道合成技术对各通道信号之间的相位关系有严格要求。通过对各通道信号之间的相位关系的精确调整，实现信号功率的合成。传统多通道合成技术中，可以在各通道的基带路径、射频路径、或者本振路径上进行相位调整。
如5G设备中，通过在波束赋型芯片中内部集成数控移相器，通过预校准和查找码表(Look up table，LUT)方式，实现各射频通道之间的相位关系调整，达到信号合成的目的。即是在射频信号路径上直接进行信号的相位调整。或者在多通道中，采用共用本振电路，通过对本振信号进行多路功分，分别给到各通道的变频器。同时在本振功分电路后增加移相器，调整各本振信号路径上本振信号的相位，实现各通道输出射频信号的相位关系的调整，达到信号合成的目的。由于同一本振信号通过功分电路给到各个通道，各通道本振信号的走线有严格要求，限制了单板中的应用。或者在多通道中，通过基带电路对输出信号直接进行相位调整，最终实现多通道之间的相位变化，实现信号输出合成。
然而，上述几种相位调整方法，通过基带电路对于相位的调整范围有限， 直接在射频路径上进行相位调整会造成信号损失，对本振电路输出的本振信号进行处理需要多个高性能的微波移相器，成本较高。
发明内容
本申请实施例提供了一种多通道信号合成电路，包括：电路结构相同的N个信号通道、与N个信号通道连接的多端口合路器、与多端口合路器连接的控制回路、与控制回路连接的时钟单元，N为大于1的整数；时钟单元用于向各信号通道输出本振信号；其中，本振信号根据移相后的参考信号生成；信号通道用于根据基带信号和本振信号生成本通道的射频信号；多端口合路器，用于将N个信号通道输出的射频信号合成为一路射频信号后输出；控制回路用于根据合成后的射频信号，向时钟单元输出控制信号，供时钟单元根据控制信号调整参考信号需要移动的相位。
本申请实施例提供了一种多通道信号合成方法，包括：将时钟源生成的参考信号分别进行移相处理；根据各移相后的参考信号分别生成各本振信号；将各本振信号和与各本振信号分别对应的各基带信号进行混频，生成各射频信号；将各射频信号进行合成，输出一路合成后的射频信号；获取合成后的射频信号，用于调整参考信号需要移动的相位。
附图说明
图1是根据本申请一个实施例提供的多通道信号合成电路的示意图；
图2是根据本申请一个实施例提供的时钟单元的示意图；
图3是根据本申请另一个实施例提供的多通道信号合成电路的示意图；
图4是根据本申请一个实施例提供的应用场景的示意图。
具体实施方式
为使本申请实施例的目的、技术方案和优点更加清楚，下面将结合附图对本申请的各实施例进行详细的阐述。然而，本领域的普通技术人员可以理解，在本申请各实施例中，为了使读者更好地理解本申请而提出了许多技术细节。但是，即使没有这些技术细节和基于以下各实施例的种种变化和修改，也可以 实现本申请所要求保护的技术方案。以下各个实施例的划分是为了描述方便，不应对本申请的具体实现方式构成任何限定，各个实施例在不矛盾的前提下可以相互结合相互引用。
本申请实施例中的术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括至少一个该特征。本申请的描述中，术语“包括”和“具有”以及它们任何变形，意图在于覆盖不排他的包含。例如包含了一系列部件或单元的系统、产品或设备没有限定于已列出的部件或单元，而是可选地还包括没有列出的部件或单元，或可选地还包括对于这些产品或设备固有的其它部件或单元。本申请的描述中，“多个”的含义是至少两个，例如两个，三个等，除非另有明确具体的限定。
本申请的一个实施方式涉及一种信号合成电路。如图1所示，具体包括：
电路结构相同的N个信号通道100、与N个信号通道100连接的多端口合路器200、与多端口合路器200连接的控制回路300、与控制回路300连接的时钟单元400；
时钟单元400用于向各信号通道100输出本振信号；其中，本振信号根据移相后的参考信号生成；
信号通道100用于根据基带信号和本振信号生成本通道的射频信号；
多端口合路器200，用于将N个信号通道100输出的射频信号合成为一路射频信号后输出；
控制回路300用于根据合成后的射频信号，向时钟单元400输出控制信号，供时钟单元400根据控制信号调整参考信号需要移动的相位。
本申请通过在本振信号生成的路径上增加移相功能操作用于调整本振信号，通过调整本振信号间接影响各通道的输出信号，并同时在信号输出端口检测输出信号，将调整结果闭环反馈到时钟单元中，循环优化相位调整结果，以实现多路信号的合成，达到低成本高质量的多通道信号合成。避免了在射频路径上直接插入移相单元导致的功率或信号质量损失，极大的改善了信号合成的效果，带来设备总信号功率的明显提升与传输距离的增加，同时相较于在单一本振信号生成后通过功放电路和高性能移相单元进行调整的成本明显降低。
下面对本实施方式的信号合成电路的实现细节进行具体的说明，以下内容仅为方便理解提供的实现细节，并非实施本方案的必须。
信号通道100为主要信号生成的结构，根据基带信号和本振信号生成本通道的射频信号，由于多通道信号合成技术需要各通道间相位一致才能得到较优的合成结果，即，需要对于各通道设置相位调整结构，使得多通道能够实现信号合成。在本实施方式中，在时钟单元400向各信号通道100输出本振信号生成之前，时钟单元400已经对参考信号进行了相位调整，即输出的各本振信号的相位已符合使得对应各信号通道100相位一致的条件，使得各信号通道100的信号能够进行高质量的合成。
另外，各信号通道100，可以分别在一个单板或结构内实现，也可以多个通道在一个单板或结构内实现；多端口合路器200，可以是微带线结构实现，微带线结构形式不限，也可以是腔体结构形式实现。
在一个例子中，时钟单元400，包括：时钟源420、与时钟源420连接的驱动及分发电路430、与驱动及分发电路430的N个输出端口分别连接的N个移相单元410、与N个移相单元410分别连接的N个锁相环电路440，N个移相单元410与N个锁相环电路440一一对应；时钟源420，用于提供参考信号；驱动及分发电路430，用于将参考信号分别传送至N个移相单元410；N个移相单元410，用于将驱动及分发电路430传送的参考信号进行移相调整，并传送至对应的锁相环电路440；N个锁相环电路440，用于基于移相调整后的参考信号生成本振信号。
其中，采用同一个时钟源420，并在驱动与分发电路430和锁相环电路440之间设置移相单元410，移相单元410能够调整与驱动与分发电路430相连的时钟源420发送的参考信号，参考信号是用于生成本振信号的原始信号，对参考信号进行移相调整，也能够影响本振信号的相位，同时本振信号参与调节各信号通道100的输出，也就是说通过对生成本振信号之前的参考信号的相位调整，能够调节各信号通道100的相位，使得各信号通道实现信号合成的目的。相较于一些例子中在本振信号生成后对本振信号进行移相处理，本实施方式中在本振信号生成前设置移相单元410，降低对移相单元410的性能需求，并且可调整的范围广，在保证满足相位需求的前提下减少成本和电路的复杂度。时 钟源420，可以是晶体，时钟电路，或者其它时钟信号，时钟信号可以来自于本设备，也可以来自于外部设备；移相单元410，可以是移相器器件实现，可以是移相电路实现，也可以是时延线组合开关或时延电路实现，实现相位调节的目的和功能即可，并不限制实现的装置或器件。
在一个例子中，锁相环电路440包括：鉴相器441、与鉴相器441连接的电荷泵442、与电荷泵442连接的环路滤波器443、与环路滤波器443连接的压控振荡器444，压控振荡器444还通过分频器445与鉴相器441连接；压控振荡器444，用于向N个信号通道110输出本振信号。包含所述锁相环电路440的时钟单元如图2所示。
在一个例子中，控制回路300分别与N个移相单元410连接，分别向N个移相单元410输出控制信号。
锁相环电路440处理移相后的参考信号用于生成本振信号，以实现调整信号通道100上的信号生成过程的目的。其中，锁相环电路440可以是独立电路，也可以是一个集成的具体芯片；或者是除压控振荡器444外的锁相环电路440结构为一个集成芯片或电路，压控振荡器444为一个独立的芯片或独立电路，以减少锁相环芯片的复杂程度。
在一个例子中，控制回路300包括：与多端口合路器200连接的检测模块310和与检测模块310连接的CPU控制器320；检测模块310，用于获取合成后的射频信号，并将合成后的射频信号转化为CPU控制器320可用的数据格式或信号；CPU控制器320，用于根据从检测模块310获取的数据，向时钟单元400输出控制信号。
控制回路300用于检测多端口合路器200输出的合成信号是否满足预设的输出条件，如若不满足，则通过CPU控制器320向时钟单元400发出控制信号，对各信号通道100的信号进行相位调整，以优化信号的合成质量，最终达到预设合成信号的条件。
在一个例子中，CPU控制器320的第一端连接至N个移相单元410，CPU控制器的第二端连接至检测模块310；CPU控制器320输出N路控制信号，N路控制信号用于分别控制N个移相单元410。
CPU控制器320接收检测模块310传送的信号数据，判断该信号数据是否 满足预设的输出条件，若不满足，则基于当前的输出信号向移相单元410输出相应的控制信号，控制各移相单元410需要调整的相位；各移相单元410调节时钟源420向锁相环电路440发送的参考信号，最终达到纠正多路信号通道100的信号相位的目的。
在一个例子中，检测模块310，包括：耦合器311，与耦合器311连接的检波电路312；耦合器311连接至多端口合路器200；检波电路312的第一端连接至耦合器311，检波电路312的第二端连接至CPU控制器320。
例如，耦合器311用于从多端口合路器200获取输出的信号，该信号体现为功率值，耦合器311将从多端口合路器200获取的信号功率值传送至检波电路312，检波电路312将从耦合器311获取的信号功率值转化为CPU控制器320可用的电压值。检测模块310用于从多端口合路器200获得多路通道的合成信号结果，并将其处理为CPU控制器320可用的数据值，例如，检波电路312将其处理为CPU控制器320能够处理的电压值。另外，检波电路312，可以是具体的检波器芯片，也可以是一组器件实现的检波功能电路；耦合器311，可以是集成在单板上的微带耦合器，形式不限，也可以是腔体耦合器。
在一个例子中，N个信号通道100，包括：基带单元101、与基带单元101连接的第一滤波器102，与第一滤波器102连接的可变增益放大器103，与可变增益放大器103连接的混频器104，与混频器104连接的第二滤波器105，与第二滤波器105连接的功率放大器106；功率放大器106与多端口合路器200相连；混频器104与时钟单元400相连，接收时钟单元400提供的本振信号。其中，各模块不限于一个或多个器件组成；也可以是几个功能器件的组合实现，实现对应功能即可。将信号通道100，控制回路300相关结构展示于信号合成电路，如图3所示。
在另一个例子中，本申请利用在生成本振信号的参考信号路径上增加移相单元410，通过合成端口的检波电路检测，反馈调整参考信号路径上的相位变化，间接实现了对高频及毫米波信号路径上的相位调整，从而实现了多通道信号之间的相位关系调整，最终达到通道间功率合成的目的。主要特征，例如：多个信号通道100，各通道之间采用相同架构电路；多个信号通道100之间的各个本振信号来源于同一个时钟源420；时钟源420通过驱动及分发电路430 分别给到各个生成本振信号的锁相环电路440；驱动及分发电路430和生成本振信号的锁相环电路440之间存在移相单元410；多个信号通道100的输出端口对接在多端口合路器200上；多端口合路器200输出端口还存在控制回路300的检测模块310；检测模块310输出信号数据给到CPU控制器320，CPU控制器320同步连接到各信号通道100的移相单元410上；CPU控制器320通过检测模块310的反馈，调整各信号通道100的相位；各信号通道100的相位关系满足一定条件时，在多端口合路器200输出端口处实现叠加合成。
通过在本振信号生成的路径上增加移相单元410调整参考信号，参考信号用于生成本振信号，通过调整本振信号间接影响各信号通道100的输出，并同时在多端口合路器200输出端口检测输出信号，将调整结果闭环反馈到移相单元410中，循环优化相位调整结果，以实现多路信号的合成。避免了在信号通道100上直接插入移相单元410导致的功率损失或信号质量损伤，极大的改善了信号合成的效果，带来设备总信号功率的明显提升与传输距离的增加，同时相较于在单一本振信号生成后通过功放电路和高性能移相单元进行调整的成本明显降低。
由于参考信号是低频信号，在低频信号路径上增加移相单元410，间接达到了调整本振信号等高频信号相位的目的，避免了在信号通道100上直接插入移相单元410引入的功率或信号质量损失，减少了相位误差带来的合成损耗，极大的改善了功率合成的效果。另外在低频信号上的移相单元410的实现，结构简单，相位调整的精度高，相位调整的范围大，足以补偿主信号通道100上由于信号走线及信号路径上引入的相位差，实现多通道输出端口的相位对齐，达到信号合成的效果。本方案极大的降低了5G，微波及毫米波等频段设备上的多通道合成的难题，解决了高频频段上多通道合成的瓶颈，是对多通道合成方法的一大补充和完善。同时实现结构简单，电路可靠有效，具有较大实用价值。
本申请可以用于微波/毫米波点对点通信场景中，如图4所示：Radio 1和Radio 2分别是两个站点上的通信传输设备。利用多通道合成技术，可以通过对多通道进行信号合成，提升通信设备的发射信号功率电平，进而增加两个站点之间的传输距离，同时提高系统增益余量和传输链路的可用度。
本申请的一个实施方式涉及一种信号合成方法。具体包括：
将时钟源生成的参考信号分别进行移相处理；根据各移相后的参考信号分别生成各本振信号；将各本振信号和与各本振信号分别对应的各基带信号进行混频，生成各射频信号；将各射频信号进行合成，输出一路合成后的射频信号；获取合成后的射频信号，用于调整所述参考信号需要移动的相位。
另外，在满足预设条件时，获取合成后的射频信号，用于调整参考信号需要移动的相位；其中，预设条件包括：根据预设时间周期执行、在预设时间节点执行或者在其他预设条件触发时执行。另外，也可接受用户的指令进行启动。
即，为了减少资源消耗，预先设定控制回路300对于信号合成进行相位调整的时间周期、进行调整的时间节点或其他触发相位调整的条件。在控制回路300不工作的时候，移相单元410不会收到实时的调整信号，时钟单元400会按照既定的相位调整条件进行信号合成；在控制回路300触发进行工作时，实时监测合成信号，并反馈调整各移相单元410的相位条件，优化各信号的相位关系，提升合成信号的质量。
此外，为了突出本申请的创新部分，本实施方式中并没有将与解决本申请所提出的技术问题关系不太密切的单元引入，但这并不表明本实施方式中不存在其它的单元。
本领域的普通技术人员可以理解，上述各实施方式是实现本申请的具体实施例，而在实际应用中，可以在形式上和细节上对其作各种改变，而不偏离本申请的精神和范围。

Claims (10)

  1. 一种多通道信号合成电路，包括：电路结构相同的N个信号通道、与所述N个信号通道连接的多端口合路器、与所述多端口合路器连接的控制回路、与所述控制回路连接的时钟单元，所述N为大于1的整数；
    所述时钟单元用于向各所述信号通道输出本振信号；其中，所述本振信号根据移相后的参考信号生成；
    所述信号通道用于根据基带信号和所述本振信号生成本通道的射频信号；
    所述多端口合路器，用于将所述N个信号通道输出的射频信号合成为一路射频信号后输出；
    所述控制回路用于根据合成后的射频信号，向所述时钟单元输出控制信号，供所述时钟单元根据所述控制信号调整所述参考信号需要移动的相位。
  2. 根据权利要求1所述的多通道信号合成电路，其中，所述时钟单元，包括：
    时钟源、与所述时钟源连接的驱动及分发电路、与所述驱动及分发电路的N个输出端口分别连接的N个移相单元、与所述N个移相单元分别连接的N个锁相环电路，所述N个移相单元与所述N个锁相环电路一一对应；
    所述时钟源，用于提供参考信号；
    所述驱动及分发电路，用于将所述参考信号分别传送至所述N个移相单元；
    所述N个移相单元，用于将所述驱动及分发电路传送的参考信号进行移相调整，并传送至对应的锁相环电路；
    所述N个锁相环电路，用于基于所述移相调整后的参考信号生成本振信号。
  3. 根据权利要求2所述的多通道信号合成电路，其中，所述锁相环电路，包括：
    鉴相器、与所述鉴相器连接的电荷泵、与所述电荷泵连接的环路滤波器、与所述环路滤波器连接的压控振荡器，所述压控振荡器还通过分频器与所述鉴相器连接；
    所述压控振荡器，用于向所述N个信号通道输出所述本振信号。
  4. 根据权利要求2或3所述的多通道信号合成电路，其中，所述控制回路分别与所述N个移相单元连接，分别向所述N个移相单元输出控制信号。
  5. 根据权利要求1至4中任一项所述的多通道信号合成电路，其中，所述控制回路，包括：
    与所述多端口合路器连接的检测模块和与所述检测模块连接的CPU控制器；
    所述检测模块，用于获取所述合成后的射频信号，并将所述合成后的射频信号转化为所述CPU控制器可用的数据格式或信号；
    所述CPU控制器，用于根据从所述检测模块获取的数据，向所述时钟单元输出控制信号。
  6. 根据权利要求5所述的多通道信号合成电路，其中，所述检测模块，包括：
    耦合器，与所述耦合器连接的检波电路；
    所述耦合器，与所述多端口合路器连接，用于获取所述合成后的射频信号；
    所述检波电路，用于将从所述耦合器获取的所述合成后的射频信号进行格式调整。
  7. 根据权利要求1至6中任一项所述的多通道信号合成电路，其中，所述电路结构相同的N个信号通道，包括：
    基带单元，与所述基带单元连接的第一滤波器，与所述第一滤波器连接的可变增益放大器，与所述可变增益放大器连接的混频器，与所述混频器连接的第二滤波器，与所述第二滤波器连接的功率放大器；
    所述功率放大器与所述多端口合路器相连；
    所述混频器与所述时钟单元相连，接收所述时钟单元提供的本振信号。
  8. 根据权利要求2至4中任一项所述的多通道信号合成电路，其中，所述移相单元包括：移相器或时延电路。
  9. 一种多通道信号合成方法，包括：
    将时钟源生成的参考信号分别进行移相处理；
    根据各移相后的参考信号分别生成各本振信号；
    将各所述本振信号和与所述各本振信号分别对应的各基带信号进行混频，生成各射频信号；
    将所述各射频信号进行合成，输出一路合成后的射频信号；
    获取所述合成后的射频信号，用于调整所述参考信号需要移动的相位。
  10. 根据权利要求9所述的多通道信号合成方法，其中，所述获取所述合成后的射频信号，用于调整所述参考信号需要移动的相位，包括：
    在满足预设条件时，所述获取所述合成后的射频信号，用于调整所述参考信号需要移动的相位；
    其中，所述预设条件包括：根据预设时间周期执行或在预设时间节点执行。
PCT/CN2022/101583 2021-06-28 2022-06-27 多通道信号合成电路及多通道信号合成方法 WO2023274163A1 (zh)

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