WO2020237690A1 - 一种相位同步装置、相位同步系统及收发装置 - Google Patents

一种相位同步装置、相位同步系统及收发装置 Download PDF

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Publication number
WO2020237690A1
WO2020237690A1 PCT/CN2019/089705 CN2019089705W WO2020237690A1 WO 2020237690 A1 WO2020237690 A1 WO 2020237690A1 CN 2019089705 W CN2019089705 W CN 2019089705W WO 2020237690 A1 WO2020237690 A1 WO 2020237690A1
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Prior art keywords
phase
local oscillator
locked loop
oscillator signal
signal
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PCT/CN2019/089705
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English (en)
French (fr)
Inventor
高鹏
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华为技术有限公司
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Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to EP19930633.3A priority Critical patent/EP3968523A4/en
Priority to PCT/CN2019/089705 priority patent/WO2020237690A1/zh
Priority to CN201980095431.1A priority patent/CN113678377A/zh
Publication of WO2020237690A1 publication Critical patent/WO2020237690A1/zh
Priority to US17/539,149 priority patent/US20220085821A1/en

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/22—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using more than one loop
    • H03L7/23—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using more than one loop with pulse counters or frequency dividers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/07—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop using several loops, e.g. for redundant clock signal generation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/087—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using at least two phase detectors or a frequency and phase detector in the loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
    • H03L7/197—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division
    • H03L7/1974—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division for fractional frequency division
    • H03L7/1976—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division for fractional frequency division using a phase accumulator for controlling the counter or frequency divider

Definitions

  • This application relates to the field of communication technology, and in particular to a phase synchronization device, a phase synchronization system, and a transceiver device.
  • multi-antenna technology is used as the core technology to improve system throughput and will be widely used.
  • FIG. 1 shows a radio frequency transceiver that supports multiple antenna technology.
  • the radio frequency transceiver integrates n radio frequency transceiver channels (CH1, CH2...CHn).
  • the circuits of each transceiver channel are basically the same, including a low-noise amplifier (LNA), a power amplifier (PA), and a phase shifter (PHS).
  • LNA low-noise amplifier
  • PA power amplifier
  • PHS phase shifter
  • the signals received by each ANT are amplified by LNA, and then undergo phase shifting operation through PHS.
  • PHS phase shifting operation
  • the received signal after the phase shift processing is synthesized into a signal through a power combiner (PC).
  • PC power combiner
  • DC down-converter
  • the baseband signal is converted to an intermediate frequency signal and then sent to the transmitter, and then transferred to the radio frequency carrier frequency after a second frequency conversion by an up-converter (UC). Then, the signal is divided into n channels through a power splitter (PS) and sent to n channels of radio frequency transceivers.
  • PS power splitter
  • the signals sent to each RF transceiver channel undergo PHS phase shift processing, and then send to ANT through PA, and radiate to free space through ANT.
  • the transmitted signals radiated by each ANT can be combined in space to form a larger transmission power in a specific spatial direction.
  • the system may use more antennas to further improve beamforming characteristics. Due to the constraints of cost, power consumption, and implementation complexity, the number of RF channels that can be provided on a single RF transceiver chip is limited, so a multi-chip splicing scheme is required to achieve the expansion of the antenna array.
  • Figure 2 shows an example of an antenna array expansion method. In this example, each chip independently supports a 2 ⁇ 2 antenna array (ANT1 ⁇ ANT4). A total of 4 identical chips (CHIP1 ⁇ CHIP4) are used. ) Is spliced into a 4 ⁇ 4 antenna array, which realizes antenna array expansion.
  • Figure 3 shows another implementation of the antenna array expansion. In this example, the implementation of the antenna array is decoupled from the chip, and the chip is connected to the antenna feed point through a radio frequency wire.
  • the radio frequency transceiver shown in FIG. 4 can be applied to a radio frequency system supporting multiple antenna technology.
  • the radio frequency transceiver shown in FIG. 4 includes two radio frequency transceiver chips, and n radio frequency transceiver channels are integrated in each chip.
  • chip 1 and chip 2 each use a phase locked loop (PLL) inside the chip to provide local oscillator signals for up and down conversion operations.
  • PLL phase locked loop
  • phase-locked loops of the two chips use the same reference clock signal (CLK_REF)
  • CLK_REF reference clock signal
  • the frequencies of the local oscillator signals generated by the two phase-locked loops are the same, but their phase relationship is difficult to keep consistent.
  • the phase difference of the respective local oscillator signals of the two chips will affect the relative phase relationship of the carrier frequencies of the antennas transmitted by the two chips, and then affect the beamforming performance of the multi-antenna system.
  • the embodiments of the present application provide a phase synchronization device, a phase synchronization system, and a transceiver device, which are used to provide a local oscillator signal with the same phase for each radio frequency transceiver chip in a multi-chip splicing solution.
  • an embodiment of the present application provides a phase synchronization system, including a first radio frequency transceiver chip and a second radio frequency transceiver chip.
  • the first radio frequency transceiver chip includes a first phase locked loop and a first control circuit.
  • the radio frequency transceiver chip includes a second phase locked loop.
  • the first phase-locked loop is used to generate the first local oscillator signal;
  • the second phase-locked loop is used to generate the second local oscillator signal;
  • the first control circuit is used to generate the first local oscillator signal and the second local oscillator signal.
  • the signal is phase-detected to obtain a first phase difference, and a first control signal is generated according to the first phase difference, and the first phase-locked loop is phase-controlled or the second phase-locked loop is phase-controlled by using the first control signal.
  • the first control circuit performs phase detection according to the first local oscillator signal and the second local oscillator signal to obtain the first phase difference, and generates the first control signal according to the first phase difference, using the first The control signal controls the phase of the first phase-locked loop or the second phase-locked loop.
  • the first phase difference may reflect the relative phase relationship between the first local oscillator signal and the second local oscillator signal.
  • the phase synchronization system provided in the first aspect can realize the local oscillator of two radio frequency transceiver chips.
  • the phase of the signal is synchronized. Specifically, when the first control signal is generated according to the first phase difference and the first control signal is used to control the first phase-locked loop, the phase of the first local oscillator signal generated by the first phase-locked loop can be the same as that of the second phase-locked loop.
  • phase of the generated second local oscillator signal remains the same; or, when the first control signal is generated according to the first phase difference and the first control signal is used to control the second phase-locked loop, the second phase-locked loop generated by the second phase-locked loop.
  • the phase of the local oscillator signal is consistent with the phase of the first local oscillator signal generated by the first phase-locked loop.
  • the first control circuit may include: a first phase detector for detecting the first phase difference according to the first local oscillator signal and the second local oscillator signal.
  • the first control circuit may include: a first phase controller for generating a first control signal according to a first phase difference, the first control signal for controlling the frequency division of the first phase-locked loop or the second phase-locked loop Control word.
  • the first phase-locked loop is specifically used to generate a first local oscillator signal based on the first reference clock signal; the second phase-locked loop is specifically used to generate a second local oscillator signal based on the first reference clock signal. Vibration signal.
  • the first phase-locked loop and the second phase-locked loop generate local oscillator signals based on the same reference clock signal, and the frequencies of the first local oscillator signal and the second local oscillator signal are the same. Then, the first local oscillator signal and the second local oscillator signal are local oscillator signals with the same frequency and phase.
  • the first phase-locked loop can adopt different implementation modes when generating the first local oscillator signal.
  • the first control circuit uses the first control signal to control the phase of the first phase-locked loop. Then, when the first phase-locked loop generates the first local oscillator signal, under the control of the first control signal, The first local oscillator signal is generated according to the first reference clock signal.
  • the first phase-locked loop when the first phase-locked loop generates the first local oscillator signal, it can be implemented in the following ways: generating the frequency division control word according to the first control signal; generating the first local oscillator according to the first reference clock signal and the frequency division control word signal.
  • the first control signal can change the frequency division control word of the first phase-locked loop, thereby changing the phase of the first local oscillator signal generated by the first phase-locked loop.
  • the first control circuit uses the first control signal to control the phase of the second phase-locked loop. Therefore, when the second phase-locked loop generates the second local oscillator signal, it can be controlled by the first control signal. , Generate a second local oscillator signal based on the first reference clock signal.
  • the phase synchronization system provided by the first aspect further includes: a third radio frequency transceiver chip, the third radio frequency transceiver chip includes a third phase-locked loop and a second control circuit; wherein, the third phase-locked loop is used to generate a third Local oscillator signal; the second control circuit is used to detect the second phase difference according to the third local oscillator signal and the first local oscillator signal, and generate the second control signal according to the second phase difference; the first phase-locked loop is generating the first In the case of the local oscillator signal, the first local oscillator signal can be generated according to the first reference clock signal under the control of the second control signal.
  • the phase synchronization system provided by the first aspect may further include a third radio frequency transceiver chip for generating a control signal for phase control of the first phase-locked loop.
  • the third radio frequency transceiver chip includes a third phase locked loop and a second control circuit.
  • the first phase-locked loop when the first phase-locked loop generates the first local oscillator signal, it can be implemented in the following ways: generating a frequency division control word according to the second control signal; according to the first reference clock signal and frequency division control The word generates the first local oscillator signal.
  • the second control signal can change the frequency division control word of the first phase-locked loop, thereby changing the phase of the first local oscillator signal generated by the first phase-locked loop.
  • the first phase-locked loop when the first phase-locked loop generates the first local oscillator signal, it generates the first local oscillator signal according to the first reference clock signal.
  • the first phase-locked loop can be used as a reference for calibration of other phase-locked loops, and the first phase-locked loop does not need to be generated according to the control signal when generating the local oscillator signal.
  • the first phase-locked loop includes: a third phase detector for detecting the phase difference between the first reference clock signal and the feedback clock signal; the loop controller is coupled with the third phase detector, Used for generating a third control signal according to the phase difference between the first reference clock signal and the feedback clock signal; a controlled oscillator, coupled with the loop controller, for generating the first local oscillator signal according to the third control signal; a modulator, Used to generate the frequency division control word according to the first control signal or the second control signal and the frequency control word; the third frequency divider, coupled with the controlled oscillator and the modulator, is used to divide the frequency according to the first local oscillator signal The control word generates a feedback clock signal and outputs it to the third phase detector.
  • the modulator in the phase-locked loop when the modulator in the phase-locked loop generates the frequency division control word, it is generated according to the frequency control word.
  • the first phase-locked loop when the first phase-locked loop generates the frequency division control word, it must be generated according to the control signal.
  • a logic circuit can be added to the phase-locked loop provided in the prior art to form the first phase-locked loop to realize this function.
  • the control signal is used to intervene the behavior of the modulator, so as to realize the function of adjusting the phase of the local oscillator signal output by the first phase-locked loop.
  • the first control circuit includes: a first driver for receiving the first local oscillator signal and outputting the driven first local oscillator signal to the second control circuit.
  • the first control circuit may further include: a first buffer for buffering the second local oscillator signal.
  • the local oscillator signal transmitted from other chips to this chip can be buffered through the buffer, and the local oscillator signal output by the phase-locked loop in this chip can be compared with other chips.
  • the local oscillator signal transmitted to this chip performs phase detection; similarly, when the local oscillator signal output by the phase-locked loop in this chip is output to other chips for phase detection, the lock in the chip can also be detected by the driver.
  • the local oscillator signal output by the phase loop is output to other chips, and the driver can be coupled with buffers in other chips to realize the transmission of the local oscillator signal.
  • the local oscillator signal can be transmitted between chips through a driver and a buffer.
  • the time delay on the transmission path will cause the phase of the local oscillator signal to change.
  • the first control circuit includes: a second phase detector for obtaining the third phase based on the third local oscillator signal and the first local oscillator signal. Difference, the second control circuit generates a second control signal according to the difference between the second phase difference and the third phase difference.
  • the second phase detector also detects the second phase difference according to the third local oscillator signal generated by the third phase-locked loop and the first local oscillator signal. Since the first phase-locked loop and the first control circuit are integrated in the first radio frequency transceiver chip, and the second control circuit and the third phase-locked loop are integrated in the third radio frequency transceiver chip, the second control circuit detects the second radio frequency transceiver chip. In the case of phase difference, the first local oscillator signal is detected after being transmitted from the first RF transceiver chip to the third RF transceiver chip. The second phase difference includes the first RF transceiver chip to the third RF transceiver chip.
  • phase difference includes the phase deviation caused by the transmission path from the third radio frequency transceiver chip to the first radio frequency transceiver chip. Therefore, when the second control circuit generates the second control signal according to the difference between the second phase difference and the third phase difference, the second phase difference and the third phase difference are made the difference, which can cancel the phase deviation caused by the transmission path.
  • the second radio frequency transceiver chip further includes: a third control circuit for obtaining a fourth phase difference according to the detection of the first local oscillator signal and the second local oscillator signal; the first control circuit is generating the first In the case of a control signal, it is specifically used to generate the first control signal according to the difference between the first phase difference and the fourth phase difference.
  • the third control circuit coupled with the second phase-locked loop, it can also perform phase detection based on the first local oscillator signal and the second local oscillator signal to obtain a fourth phase difference, and transmit the fourth phase difference To the first control circuit.
  • the first control circuit When the first control circuit generates the first control signal, it can generate the first control signal according to the difference between the first phase difference and the fourth phase difference.
  • the first control circuit detects the first radio frequency transceiver chip.
  • the second local oscillator signal is detected after being transmitted from the second RF transceiver chip to the first RF transceiver chip.
  • the first phase difference includes the second RF transceiver chip to the first RF transceiver chip.
  • the phase difference includes the phase deviation caused by the transmission path from the first radio frequency transceiver chip to the second radio frequency transceiver chip. Therefore, when the first control circuit generates the first control signal according to the difference between the first phase difference and the fourth phase difference, after the first phase difference and the fourth phase difference are made, the phase deviation caused by the transmission path can be offset.
  • the first control circuit may include: a second driver for receiving the first local oscillation signal and outputting the driven first local oscillation signal to the third control circuit.
  • the first control circuit may further include: a second buffer for buffering the third local oscillator signal.
  • the first control circuit performs phase detection on the first local oscillator signal and the second local oscillator signal to obtain a first phase difference, and the first phase difference can reflect the first local oscillator signal and the second local oscillator signal.
  • the first phase difference can have multiple meanings.
  • the first type is the phase difference between the first local oscillator signal and the second local oscillator signal
  • the first phase detector detects the first phase difference based on the first local oscillator signal and the second local oscillator signal, it can be specifically implemented in the following manner: the first phase detector compares the first local oscillator signal with the second local oscillator signal. The phase difference of the vibration signal is detected to obtain the first phase difference.
  • the first phase detector directly detects the phase difference between the first local oscillator signal and the second local oscillator signal, and can generate the first local oscillator signal according to the phase difference between the first local oscillator signal and the second local oscillator signal.
  • the control signal is used for phase control of the first phase-locked loop or the second phase-locked loop.
  • the second type is the first phase difference is the phase difference between the first local oscillator signal after frequency division and the second local oscillator signal after frequency division
  • the first control circuit further includes: a first frequency divider, which is coupled to the first phase-locked loop, and is used to divide the frequency of the first local oscillator signal; and the third control circuit further includes: a second The frequency divider, coupled with the second phase-locked loop, is used to divide the frequency of the second local oscillator signal.
  • the frequency division ratio of the second frequency divider and the first frequency divider is the same; the first control circuit is based on the first
  • the first control circuit divides the first local oscillator signal by the first frequency divider and the second frequency divider.
  • the phase difference of the second local oscillator signal is detected to obtain the first phase difference.
  • the subsequent phase detection and signal transmission work at a lower frequency.
  • the power consumption level will be significantly reduced.
  • the first radio frequency transceiver chip further includes a first digital interface
  • the second radio frequency transceiver chip further includes a second digital interface.
  • the provided phase synchronization system also includes a control chip; wherein the first digital interface is coupled with the first control circuit to receive and output the first control signal; the control chip is coupled with the first digital interface and the second digital interface to connect The first control signal output by the first digital interface is transmitted to the second digital interface; the second digital interface is coupled with the second phase-locked loop.
  • the first digital interface and the second digital interface may be general digital interfaces, and the general digital interface may be used as a common interface for signal transmission between chips.
  • this type of digital interface module is provided on the radio frequency transceiver chip, which serves as a general interface for the upper system to issue instructions to the radio frequency transceiver chip, or the upper system to collect status information from the radio frequency transceiver chip.
  • this interface can be directly multiplexed for cross-chip information transmission, without the need to add resources such as hardware pins.
  • control chip may be the main control chip in the system.
  • the main control chip carries the software and hardware functions of the upper system, and communicates instructions or data with the radio frequency transceiver chip through a universal digital interface.
  • the main control chip can be directly multiplexed for cross-chip information transmission.
  • the existing chips and interfaces can be reused to realize cross-chip information transmission, so as to realize the phase synchronization of the local oscillator signal.
  • the first radio frequency transceiver chip also includes: a fourth phase-locked loop for generating a fourth local oscillator signal; a fourth control circuit for generating a fourth local oscillator signal and the first local oscillator Signal detection obtains a fifth phase difference, and generates a fourth control signal according to the fifth phase difference, and uses the fourth control signal to perform phase control on the first phase-locked loop or the fourth phase-locked loop.
  • the first phase-locked loop can be used to provide a local oscillator signal for a part of the radio frequency channel in the first radio frequency transceiver chip
  • the fourth phase-locked loop can be used to provide a local oscillator signal for another part of the radio frequency channel in the first radio frequency transceiver chip .
  • the first phase-locked loop and the fourth phase-locked loop in the first radio frequency transceiver chip can output local oscillator signals with the same phase, so as to provide all radio frequency channels in the first radio frequency transceiver chip with the same phase local oscillator. Vibration signal.
  • the first radio frequency transceiver chip further includes: a plurality of first transmission channels, the first phase-locked loop is specifically used to provide the first local oscillator signal for the plurality of first transmission channels; the second radio frequency transceiver The machine chip also includes: a plurality of second transmission channels, the second phase-locked loop is specifically used to provide a second local oscillator signal for the plurality of second transmission channels; a plurality of first transmission channels and a plurality of second transmission channels are used for Support multiple input multiple output MIMO transmission.
  • the multiple first transmission channels in the first radio frequency transceiver chip are respectively coupled with multiple first antennas
  • the multiple second transmission channels in the second radio frequency transceiver chip are respectively coupled with multiple second antennas
  • Multiple first antennas and multiple second antennas form a MIMO antenna array
  • multiple first transmission channels and multiple second transmission channels are used to transmit signals of the same carrier frequency, or multiple first transmission channels and multiple The second transmission channels are used to receive signals of the same carrier frequency.
  • the signals transmitted in the first transmission channel and the second transmission channel may be 5G NR signals.
  • the first radio frequency transceiver chip further includes: a plurality of first transmission channels, the first phase-locked loop is specifically used to provide the first local oscillator signal for the plurality of first transmission channels; the second radio frequency transceiver The machine chip also includes: a plurality of second transmission channels, the second phase-locked loop is specifically used to provide a second local oscillator signal for the plurality of second transmission channels; a plurality of first transmission channels and a plurality of second transmission channels are used for Support phased array transmission.
  • the multiple first transmission channels in the first radio frequency transceiver chip are respectively coupled with multiple first antennas
  • the multiple second transmission channels in the second radio frequency transceiver chip are respectively coupled with multiple second antennas
  • Multiple first antennas and multiple second antennas form a phased array antenna array
  • multiple signals respectively transmitted by multiple first transmission channels and multiple signals respectively transmitted by multiple second transmission channels are used for beamforming.
  • the signals transmitted in the first transmission channel and the second transmission channel may be 5G NR signals.
  • an embodiment of the present application provides a phase synchronization device, which includes a first phase-locked loop and a first control circuit integrated in a first radio frequency transceiver chip.
  • the first phase-locked loop is used to generate the first local oscillator signal.
  • the first control circuit is used to detect the first phase difference according to the first local oscillator signal and the second local oscillator signal generated by the second phase-locked loop in the second radio frequency transceiver chip, and generate the first phase difference according to the first phase difference A control signal, and using the first control signal to perform phase control on the first phase-locked loop or perform phase control on the second phase-locked loop.
  • the first control circuit performs phase detection according to the first local oscillator signal and the second local oscillator signal to obtain the first phase difference, and generates the first control signal according to the first phase difference, using the first The control signal controls the phase of the first phase-locked loop or the second phase-locked loop.
  • the first phase difference may reflect the relative phase relationship between the first local oscillator signal and the second local oscillator signal.
  • the phase synchronization device provided in the second aspect can realize the local oscillator of two radio frequency transceiver chips.
  • the phase of the signal is synchronized. Specifically, when the first control signal is generated according to the first phase difference and the first control signal is used to control the first phase-locked loop, the phase of the first local oscillator signal generated by the first phase-locked loop can be the same as that of the second phase-locked loop.
  • phase of the generated second local oscillator signal remains the same; or, when the first control signal is generated according to the first phase difference and the first control signal is used to control the second phase-locked loop, the second phase-locked loop generated by the second phase-locked loop.
  • the phase of the local oscillator signal is consistent with the phase of the first local oscillator signal generated by the first phase-locked loop.
  • phase synchronization device provided in the second aspect can be understood as a phase locked loop and control circuit integrated in a certain radio frequency transceiver chip, or as a radio frequency transceiver chip.
  • the working principle and processing logic of the phase-locked loop and the control circuit are the same as the phase-locked loop and the control circuit provided in the first aspect.
  • the first control circuit may include: a first phase detector for detecting the first phase difference according to the first local oscillator signal and the second local oscillator signal.
  • the first control circuit may include: a first phase controller for generating a first control signal according to a first phase difference, the first control signal for controlling the frequency division of the first phase-locked loop or the second phase-locked loop Control word.
  • the first phase controller is any one of a proportional controller, an integral controller, and a proportional-integral controller.
  • the operations of detecting the first phase difference and generating the first control signal can be performed by the first phase detector and the first phase controller, respectively.
  • the first phase-locked loop is specifically configured to: generate a first local oscillator signal based on the first reference clock signal; the first reference clock signal is a reference clock signal based on the second phase-locked loop to generate the second local oscillator signal .
  • the first phase-locked loop and the second phase-locked loop generate local oscillator signals based on the same reference clock signal, and the frequencies of the first local oscillator signal and the second local oscillator signal are the same. Then, the first local oscillator signal and the second local oscillator signal are local oscillator signals with the same frequency and phase.
  • the first phase-locked loop is specifically configured to generate the first local oscillator signal according to the first reference clock signal under the control of the first control signal.
  • the first control signal can change the frequency division control word of the first phase-locked loop, thereby changing the phase of the first local oscillator signal generated by the first phase-locked loop.
  • the first phase-locked loop is specifically used to: under the control of the second control signal, generate the first local oscillator signal according to the first reference clock signal, and the second control signal is the second signal in the third radio frequency transceiver chip.
  • the control signal generated by the control circuit, the second control circuit is used to detect the second phase difference according to the third local oscillator signal generated by the third phase-locked loop in the third radio frequency transceiver chip and the first local oscillator signal, and according to the first The two phase difference generates a second control signal.
  • the first control signal generated by the first control circuit is output to the second phase-locked loop for phase control of the second phase-locked loop.
  • the third RF transceiver chip includes a third phase-locked loop and a second control circuit. Then, for the first phase-locked loop, the second control signal generated by the third RF transceiver chip can be used to control the first phase-locked loop.
  • the phase locked loop performs phase control. Specifically, the second control signal can change the frequency division control word of the first phase-locked loop, thereby changing the phase of the first local oscillator signal generated by the first phase-locked loop.
  • the first control circuit includes: a first driver for receiving the first local oscillator signal and outputting the driven first local oscillator signal to the second control circuit.
  • the first control circuit includes: a first buffer for buffering the second local oscillator signal.
  • the local oscillator signal transmitted from other chips to this chip can be buffered through the buffer, and the local oscillator signal output by the phase-locked loop in this chip can be compared with other chips.
  • the local oscillator signal transmitted to this chip performs phase detection; similarly, when the local oscillator signal output by the phase-locked loop in this chip is output to other chips for phase detection, the lock in the chip can also be detected by the driver.
  • the local oscillator signal output by the phase loop is output to other chips, and the driver can be coupled with buffers in other chips to realize the transmission of the local oscillator signal.
  • the first control circuit includes: a second phase detector for detecting a third phase difference based on the third local oscillator signal and the first local oscillator signal, and the third phase difference is used for the second
  • the control circuit generates a second control signal according to the difference between the second phase difference and the third phase difference.
  • the second phase detector also detects the second phase difference according to the third local oscillator signal generated by the third phase-locked loop and the first local oscillator signal. Since the first phase-locked loop and the first control circuit are integrated in the first radio frequency transceiver chip, and the second control circuit and the third phase-locked loop are integrated in the third radio frequency transceiver chip, the second control circuit detects the second radio frequency transceiver chip. In the case of phase difference, the first local oscillator signal is detected after being transmitted from the first RF transceiver chip to the third RF transceiver chip. The second phase difference includes the first RF transceiver chip to the third RF transceiver chip.
  • phase difference includes the phase deviation caused by the transmission path from the third radio frequency transceiver chip to the first radio frequency transceiver chip. Therefore, when the second control circuit generates the second control signal according to the difference between the second phase difference and the third phase difference, the second phase difference and the third phase difference are made the difference, which can cancel the phase deviation caused by the transmission path.
  • the first control circuit when the first control circuit generates the first control signal according to the first phase difference, the following method can be used: the first control circuit generates the first control signal according to the difference between the first phase difference and the fourth phase difference; The phase difference is detected by the third control circuit coupled with the second phase-locked loop in the second radio frequency transceiver chip according to the first local oscillator signal and the second local oscillator signal.
  • the third control circuit coupled with the second phase-locked loop, it can also perform phase detection based on the first local oscillator signal and the second local oscillator signal to obtain a fourth phase difference, and transmit the fourth phase difference To the first control circuit.
  • the first control circuit When the first control circuit generates the first control signal, it can generate the first control signal according to the difference between the first phase difference and the fourth phase difference.
  • the first control circuit detects the first radio frequency transceiver chip.
  • the second local oscillator signal is detected after being transmitted from the second RF transceiver chip to the first RF transceiver chip.
  • the first phase difference includes the second RF transceiver chip to the first RF transceiver chip.
  • the phase difference includes the phase deviation caused by the transmission path from the first radio frequency transceiver chip to the second radio frequency transceiver chip. Therefore, when the first control circuit generates the first control signal according to the difference between the first phase difference and the fourth phase difference, after the first phase difference and the fourth phase difference are made, the phase deviation caused by the transmission path can be offset.
  • the first control circuit includes: a second driver for receiving the first local oscillator signal and outputting the driven first local oscillator signal to the third control circuit.
  • the first control circuit also includes: a second buffer for buffering the third local oscillator signal.
  • the first control circuit when the first control circuit detects the first phase difference based on the first local oscillator signal and the second local oscillator signal, it can use the following method: the first control circuit compares the first local oscillator signal with the second local oscillator signal. The phase difference of the two local oscillator signals is detected to obtain the first phase difference.
  • the first phase detector directly detects the phase difference between the first local oscillator signal and the second local oscillator signal, and can generate the first local oscillator signal according to the phase difference between the first local oscillator signal and the second local oscillator signal.
  • the control signal is used for phase control of the first phase-locked loop or the second phase-locked loop.
  • the first control circuit further includes: a first frequency divider, coupled with the first phase-locked loop, for dividing the frequency of the first local oscillator signal; then, the first control circuit is When a local oscillator signal and a second local oscillator signal detect the first phase difference, they are specifically used for: the first control circuit divides the first local oscillator signal through the first frequency divider and passes through the third control circuit The phase difference of the second local oscillator signal divided by the second frequency divider is detected to obtain the first phase difference, and the second frequency divider has the same division frequency as the first frequency divider.
  • the subsequent phase detection and signal transmission work at a lower frequency.
  • the power consumption level will be significantly reduced.
  • the first phase-locked loop may include: a third phase detector for detecting the phase difference between the first reference clock signal and the feedback clock signal; a loop controller, coupled with the third phase detector, for detecting the phase difference between the first reference clock signal and the feedback clock signal; The phase difference between the reference clock signal and the feedback clock signal generates the third control signal; the controlled oscillator, coupled with the loop controller, is used to generate the first local oscillator signal according to the third control signal; the modulator is used to generate the first local oscillator signal according to the first The control signal or the second control signal and the frequency control word generate the frequency division control word; the third frequency divider, coupled with the controlled oscillator and the modulator, is used to generate the feedback clock according to the first local oscillator signal and the frequency division control word The signal is output to the third phase detector.
  • phase synchronization device provided in the second aspect, other phase-locked loops can also adopt the same structure, which will not be repeated here.
  • the phase synchronization device provided in the second aspect further includes: a first digital interface; wherein, the first digital interface is coupled with the first control circuit for receiving the first control signal and outputting to the control chip;
  • the control chip is coupled with the first digital interface and the second digital interface in the second radio frequency transceiver chip, and is used to transmit the first control signal output by the first digital interface to the second digital interface; the second digital interface and the second lock Phase loop coupling.
  • the existing chips and interfaces can be reused to realize cross-chip information transmission, so as to realize the phase synchronization of the local oscillator signal.
  • the first RF transceiver chip also includes: a fourth phase-locked loop for generating a fourth local oscillator signal; a fourth control circuit for The fifth phase difference is detected according to the fourth local oscillator signal and the first local oscillator signal, and a fourth control signal is generated according to the fifth phase difference, and the fourth control signal is used to phase control the first phase-locked loop or to Four phase-locked loops perform phase control.
  • the first phase-locked loop can be used to provide a local oscillator signal for a part of the radio frequency channel in the first radio frequency transceiver chip
  • the fourth phase-locked loop can be used to provide a local oscillator signal for another part of the radio frequency channel in the first radio frequency transceiver chip .
  • the first phase-locked loop can be used to provide local oscillator signals for a part of the radio frequency channels in the first radio frequency transceiver chip
  • the fourth phase-locked loop can be used to provide local oscillator signals for another part of the radio frequency channels in the first radio frequency transceiver chip. Vibration signal. Therefore, the first phase-locked loop and the fourth phase-locked loop in the first RF transceiver chip can output local oscillator signals with the same phase, thereby providing the local oscillator signals with the same phase for all the RF channels in the first RF transceiver chip .
  • the first radio frequency transceiver chip further includes: a plurality of first transmission channels, the first phase-locked loop is specifically used to provide the first local oscillator signal for the plurality of first transmission channels; the second radio frequency transceiver The machine chip also includes: a plurality of second transmission channels, the second phase-locked loop is specifically used to provide a second local oscillator signal for the plurality of second transmission channels; a plurality of first transmission channels and a plurality of second transmission channels are used for Support MIMO transmission.
  • the multiple first transmission channels in the first radio frequency transceiver chip are respectively coupled with multiple first antennas
  • the multiple second transmission channels in the second radio frequency transceiver chip are respectively coupled with multiple second antennas
  • Multiple first antennas and multiple second antennas form a MIMO antenna array
  • multiple first transmission channels and multiple second transmission channels are used to transmit signals of the same carrier frequency, or multiple first transmission channels and multiple The second transmission channels are used to receive signals of the same carrier frequency.
  • the signals transmitted in the first transmission channel and the second transmission channel may be 5G NR signals.
  • the first radio frequency transceiver chip further includes: a plurality of first transmission channels, the first phase-locked loop is specifically used to provide the first local oscillator signal for the plurality of first transmission channels; the second radio frequency transceiver The machine chip also includes: a plurality of second transmission channels, the second phase-locked loop is specifically used to provide a second local oscillator signal for the plurality of second transmission channels; a plurality of first transmission channels and a plurality of second transmission channels are used for Support phased array transmission.
  • the multiple first transmission channels in the first radio frequency transceiver chip are respectively coupled with multiple first antennas
  • the multiple second transmission channels in the second radio frequency transceiver chip are respectively coupled with multiple second antennas
  • Multiple first antennas and multiple second antennas form a phased array antenna array
  • multiple signals respectively transmitted by multiple first transmission channels and multiple signals respectively transmitted by multiple second transmission channels are used for beamforming.
  • the signals transmitted in the first transmission channel and the second transmission channel may be 5G NR signals.
  • an embodiment of the present application provides a transceiver device.
  • the transceiver includes the first radio frequency transceiver chip and the second radio frequency transceiver chip provided in the first aspect and any possible designs thereof.
  • the first radio frequency transceiver chip further includes: a plurality of first transmission channels, and the first phase locked loop in the first radio frequency transceiver chip is specifically configured to provide the first transmission channels for the plurality of first transmission channels.
  • the second radio frequency transceiver chip also includes: a plurality of second transmission channels, and the second phase-locked loop in the second radio frequency transceiver chip is specifically used to provide the plurality of second transmission channels
  • the second local oscillator signal; the multiple first transmission channels and the multiple second transmission channels are used to support MIMO transmission.
  • the multiple first transmission channels in the first radio frequency transceiver chip are respectively coupled with multiple first antennas
  • the multiple second transmission channels in the second radio frequency transceiver chip are respectively coupled with multiple second antennas
  • One first antenna and multiple second antennas form a MIMO antenna array
  • multiple first transmission channels and multiple second transmission channels are used to transmit signals of the same carrier frequency, or multiple first transmission channels and multiple second transmission channels Both transmission channels are used to receive signals of the same carrier frequency.
  • the signals transmitted in the first transmission channel and the second transmission channel may be 5G NR signals.
  • an embodiment of the present application provides a transceiver device.
  • the transceiver includes the first radio frequency transceiver chip and the second radio frequency transceiver chip provided in the first aspect and any possible designs thereof.
  • the first radio frequency transceiver chip further includes: a plurality of first transmission channels, and the first phase-locked loop in the first radio frequency transceiver chip is specifically used to provide the first local oscillator signal for the plurality of first transmission channels;
  • the radio frequency transceiver chip also includes: a plurality of second transmission channels, the second phase locked loop in the second radio frequency transceiver chip is specifically used to provide a second local oscillator signal for the plurality of second transmission channels; a plurality of first transmission channels And multiple second transmission channels to support phased array transmission.
  • the multiple first transmission channels in the first radio frequency transceiver chip are respectively coupled with multiple first antennas
  • the multiple second transmission channels in the second radio frequency transceiver chip are respectively coupled with multiple second antennas
  • a first antenna and a plurality of second antennas form a phased array antenna array
  • a plurality of signals respectively transmitted by a plurality of first transmission channels and a plurality of signals respectively transmitted by a plurality of second transmission channels are used for beamforming.
  • the signals transmitted in the first transmission channel and the second transmission channel may be 5G NR signals.
  • an embodiment of the present application provides a phase synchronization system.
  • the phase synchronization system includes N phase-locked loops and N control circuits corresponding to the N phase-locked loops, and N>1.
  • the i-th phase-locked loop of the N phase-locked loops is used to generate the first local oscillator signal, 1 ⁇ i ⁇ N;
  • the control circuit corresponding to the i-th phase-locked loop is used to control the first local oscillator signal and Phase detection is performed on the second local oscillator signal generated by the i+1th phase-locked loop to obtain the first phase difference, the first control signal is generated according to the first phase difference, and the i+1th phase-locked loop is performed using the first control signal Phase control.
  • an embodiment of the present application provides a phase synchronization system.
  • the phase synchronization system includes N phase-locked loops and N control circuits corresponding to the N phase-locked loops one-to-one, and N>1.
  • the i-th phase-locked loop of the N phase-locked loops is used to generate the first local oscillator signal, 1 ⁇ i ⁇ N;
  • the control circuit corresponding to the i-th phase-locked loop is used to control the first local oscillator signal and Phase detection is performed on the second local oscillator signal generated by the i+1th phase-locked loop to obtain the first phase difference, the first control signal is generated according to the first phase difference, and the i-th phase-locked loop is phase controlled by the first control signal .
  • phase synchronization device or phase synchronization system provided by the second and sixth aspects can be referred to the relevant description in the phase synchronization system provided by the first aspect. Repeat it again.
  • Fig. 1 is a schematic structural diagram of a radio frequency transceiver provided in the prior art
  • FIG. 2 is a schematic diagram of an implementation manner of antenna array expansion provided by the prior art
  • FIG. 3 is a schematic diagram of another implementation manner of antenna array expansion provided by the prior art.
  • FIG. 4 is a schematic structural diagram of a radio frequency system supporting multiple antenna technology provided by the prior art
  • FIG. 5 is a schematic structural diagram of a first radio frequency system provided by an embodiment of this application.
  • FIG. 6 is a schematic structural diagram of a second radio frequency system provided by an embodiment of this application.
  • FIG. 7 is a schematic structural diagram of a first phase synchronization system provided by an embodiment of this application.
  • FIG. 8 is a schematic structural diagram of a second phase synchronization system provided by an embodiment of this application.
  • FIG. 9 is a schematic structural diagram of a third phase synchronization system provided by an embodiment of this application.
  • FIG. 10 is a schematic structural diagram of a first phase-locked loop provided by an embodiment of the application.
  • FIG. 11 is a schematic structural diagram of another first phase-locked loop provided by an embodiment of the application.
  • FIG. 12 is a schematic structural diagram of a fourth phase synchronization system provided by an embodiment of this application.
  • FIG. 13 is a schematic structural diagram of a fifth phase synchronization system provided by an embodiment of this application.
  • FIG. 14 is a schematic structural diagram of a sixth phase synchronization system provided by an embodiment of this application.
  • FIG. 15 is a schematic structural diagram of a seventh phase synchronization system provided by an embodiment of this application.
  • FIG. 16 is a schematic structural diagram of a phase synchronization device provided by an embodiment of the application.
  • FIG. 17 is a schematic structural diagram of a transceiver device provided by an embodiment of the application.
  • the embodiment of the present application can be applied to an application scenario where multiple PLLs respectively provide local oscillator signals for each radio frequency transceiver in a multi-chip splicing solution, and the local oscillator signals need to maintain the same phase.
  • the radio frequency system shown in Fig. 5 includes two radio frequency transceiver chips, and n radio frequency transceiver channels are integrated in each chip.
  • Each RF transceiver channel includes LNA, PA and PHS.
  • PHS phase-shifting parameters
  • each chip also includes UC/DC for realizing up-conversion/down-conversion.
  • the signal received by each ANT is amplified by the LNA and then undergoes a phase shift operation through the PHS.
  • the received signal after the phase shift processing is synthesized into a signal by the PC.
  • the combined signal is moved to a lower carrier frequency through DC for processing.
  • the baseband signal is converted to an intermediate frequency signal and then sent to the chip, and after the second frequency conversion by UC, it is moved to the radio frequency carrier frequency.
  • the signal is divided into n channels through the PS and sent to the n channels of radio frequency transceiver channels.
  • the signals sent to each RF transceiver channel undergo PHS phase shift processing, and then send to ANT through PA, and radiate to free space through ANT.
  • the phase synchronization device provided by the embodiment of the present application provides a local oscillator signal for the up and down conversion operations in each chip, so that each chip uses the same phase when performing up and down conversion operations.
  • the local oscillator signal Therefore, the local oscillator signal will not affect the relative phase relationship between the ANTs, and the phase of each RF transceiver channel is only adjusted by the PHS, which can improve the beamforming performance of the system.
  • radio frequency system shown in FIG. 5 is only for illustration.
  • the radio frequency transceiver channel and UC/DC can also be integrated in two chips respectively.
  • this implementation method there are still application scenarios where multiple PLLs provide local oscillator signals with the same phase for each RF transceiver in the multi-chip splicing solution.
  • the embodiments of this application are also applicable to this application scenario.
  • a superheterodyne structure is taken as an example to describe the down-converter operation, that is, first, the signal is moved from the radio frequency carrier frequency f RF to the intermediate frequency f IF .
  • the intermediate frequency signal after the down-converter in Figure 5 needs to be moved to the baseband through another frequency conversion, and converted into a digital signal by ADC for further processing.
  • the downconverter can also be implemented based on structures such as zero intermediate frequency (ZIF) or low intermediate frequency (LIF).
  • the superheterodyne structure is taken as an example to describe the up-conversion operation, that is, the baseband signal is moved to the radio frequency f RF after two frequency-conversion operations.
  • the upconverter in Figure 5 completes the second frequency conversion, that is, moves the intermediate frequency signal to the radio frequency carrier frequency.
  • the up-conversion operation can also be realized with a zero-IF structure, that is, the baseband signal is directly transferred to the radio frequency carrier frequency through only one frequency conversion, or the up-conversion is realized based on a low-IF structure.
  • the antennas corresponding to each transceiver channel are included.
  • the antenna may be arranged on the chip silicon wafer, the chip packaging structure or the circuit board, which is not specifically limited in the embodiment of the present application.
  • the radio frequency system shown in Figure 6 includes two radio frequency transceiver chips, namely chip 1 and chip 2. Each chip integrates n receiving channels (RX1 ⁇ RXn) and m transmitting channels (TX1 ⁇ TXm). It can support the operation of a multi-antenna system including n receiving antennas and m transmitting antennas.
  • each receiving channel includes LNA, mixer (MIX), analog baseband processor (analog baseband, ABB) and analog-to-digital converter (analog-to-digital converter, ADC), etc.; each transmitting channel includes Digital-to-analog converter (DAC), ABB, modulator (MOD) and power amplifier (Amp), etc.
  • the phase synchronization device provided by the embodiment of the present application can provide the local oscillator signal of the same phase for the receiving channel in each chip, so that the local oscillator signal of each receiving channel will not affect The relative phase relationship between the receiving antennas; at the same time, the phase synchronization device provided by the embodiment of the present application can provide the local oscillator signal of the same phase for the transmission channel in each chip, so that the local oscillator signal of each transmission channel will not affect The relative phase relationship between transmitting antennas.
  • both the receiving channel and the transmitting channel adopt a zero intermediate frequency structure (ZIF), that is, the conversion between the baseband signal and the radio frequency signal is realized through one frequency conversion.
  • ZIF zero intermediate frequency structure
  • the up-down frequency conversion operation can also be implemented through secondary frequency conversion, which is not specifically limited in the embodiments of the present application.
  • the solution provided by the embodiment of the present application aims to provide each RF transceiver chip in the multi-chip splicing solution with a local oscillator signal with the same phase through the phase synchronization device and the phase synchronization system, and does not make any difference to the specific structure of the RF transceiver chip. limited.
  • the embodiment of the present application provides a phase synchronization system to provide a local oscillator signal with the same phase for each radio frequency transceiver chip in a multi-chip splicing solution.
  • the phase synchronization system 700 includes a first radio frequency transceiver chip and a second radio frequency transceiver chip.
  • the first radio frequency transceiver chip includes a first phase-locked loop 701 and a first control circuit 702, and the second radio frequency transceiver chip includes a second radio frequency transceiver chip.
  • the first phase-locked loop 701 is used to generate the first local oscillator signal; the second phase-locked loop 703 is used to generate the second local oscillator signal; the first control circuit 702 is used to generate the first local oscillator signal and the second local oscillator signal
  • the signal is phase-detected to obtain the first phase difference, and a first control signal is generated according to the first phase difference, and the first phase-locked loop 701 is phase-controlled or the second phase-locked loop 703 is phase-controlled by the first control signal.
  • the first phase-locked loop 701 and the second phase-locked loop 703 may generate the first local oscillator signal and the second local oscillator signal based on the same reference clock signal, respectively. That is, the first phase-locked loop 701 generates a first local oscillator signal according to the first reference clock signal, and the second phase-locked loop 703 generates a second local oscillator signal according to the first reference clock signal.
  • the frequencies of the first local oscillator signal and the second local oscillator signal are the same. Then, the first local oscillator signal and the second local oscillator signal are local oscillator signals with the same frequency and phase.
  • the first control circuit 702 performs phase detection according to the first local oscillator signal and the second local oscillator signal to obtain a first phase difference, and generates a first control signal according to the first phase difference, and uses the first control signal to
  • the first phase locked loop 701 or the second phase locked loop 703 performs phase control.
  • the first phase difference may reflect the relative phase relationship between the first local oscillator signal and the second local oscillator signal.
  • the phase of the first local oscillator signal generated by the first phase-locked loop 701 and the second lock remains the same; or, when the first control signal is generated according to the first phase difference and the first control signal is used to control the second phase-locked loop 703, the second phase-locked loop can be made
  • the phase of the second local oscillator signal generated by 703 is consistent with the phase of the first local oscillator signal generated by the first phase-locked loop 701.
  • the first phase locked loop 701 and the first control circuit 702 can be provided in each radio frequency transceiver chip to realize the local oscillator signals output by the two phase locked loops.
  • the phases of the local oscillator signals output by the phase-locked loop are the same, it is possible to realize that multiple radio frequency transceiver chips use local oscillator signals with the same phase.
  • the first control circuit 702 may include: a first phase detector (PD), which is configured to respond to the first local oscillator signal and the second local oscillator signal. The first phase difference is detected.
  • PD first phase detector
  • the first control circuit 702 may include: a first phase controller, configured to generate a first control signal according to a first phase difference, and the first control signal is used to control the first phase-locked loop or The frequency division control word of the second phase-locked loop (also called frequency division coefficient).
  • the operations of performing phase detection and generating the first control signal can be completed by two devices respectively.
  • the first phase detector in the first control circuit 702 can perform phase detection on the first local oscillator signal and the second local oscillator signal to obtain the first phase difference; then, the first phase detector in the first control circuit 702
  • the phase controller can generate the first control signal according to the first phase difference.
  • PD can be divided into analog PD and digital PD.
  • the output signal of the analog PD is an analog voltage or current signal representing the phase difference of the input signal
  • the output signal of the digital PD is a digital signal representing the phase difference of the input signal.
  • the digital PD can be implemented using a time-to-digital converter (TDC) circuit.
  • TDC time-to-digital converter
  • the main function of the phase controller is to process the output of the PD according to the design requirements of the control system, and output the required phase tuning value.
  • the design of the phase controller can be designed as a proportional controller, integral controller, proportional-integral controller or other types of controllers according to the system control scheme.
  • the phase controller can also be divided into an analog phase controller or a digital phase controller according to the type of signal processed.
  • the analog phase controller is mainly realized by resistors, capacitors, and operational amplifiers.
  • the digital phase controller adopts digital logic circuit or digital signal processor to realize.
  • the first control circuit 702 performs phase detection on the first local oscillator signal and the second local oscillator signal to obtain a first phase difference, which can reflect the first local oscillator signal and The relative phase relationship between the second local oscillator signals.
  • the first phase difference can have multiple meanings.
  • the first type is the phase difference between the first local oscillator signal and the second local oscillator signal
  • the first phase detector detects the first phase difference based on the first local oscillator signal and the second local oscillator signal, it can be specifically implemented in the following manner: the first phase detector compares the first local oscillator signal with the second local oscillator signal. The phase difference of the vibration signal is detected to obtain the first phase difference.
  • the first phase detector directly detects the phase difference between the first local oscillator signal and the second local oscillator signal, and can generate the first local oscillator signal according to the phase difference between the first local oscillator signal and the second local oscillator signal.
  • the control signal is used to perform phase control on the first phase locked loop 701 or the second phase locked loop 703.
  • the second type is the first phase difference is the phase difference between the first local oscillator signal after frequency division and the second local oscillator signal after frequency division
  • the first control circuit 702 further includes: a first frequency divider (FDIV), the first frequency divider is coupled with the first phase-locked loop 701, and is used to perform the first local oscillator signal Frequency division;
  • the second radio frequency transceiver chip also includes a second frequency divider for frequency division of the second local oscillator signal, the second frequency divider and the first frequency divider have the same division frequency.
  • the first phase detector detects the first phase difference according to the first local oscillator signal and the second local oscillator signal
  • the first phase detector pair is divided by the first frequency divider
  • the phase difference between the first local oscillator signal and the second local oscillator signal divided by the second frequency divider is detected to obtain the first phase difference.
  • the division frequency of the first frequency divider is M
  • the frequency of the first local oscillator signal is f LO_1
  • the phase of the first local oscillator signal is ⁇ LO_1
  • the amplitude modulation information of the first local oscillator signal is A LO_1
  • the first division The output signal of the frequency converter can be expressed as:
  • phase of the first local oscillator signal after frequency division by the frequency divider is:
  • the dividing frequency of the second frequency divider is M
  • the frequency of the second local oscillator signal is f LO_2
  • the phase of the second local oscillator signal is ⁇ LO_2
  • the amplitude modulation information of the second local oscillator signal is A LO_2
  • phase of the second local oscillator signal after frequency division by the frequency divider is:
  • the first phase difference can be expressed as:
  • the output of the first phase detector (that is, the first phase difference) can be expressed as:
  • K PD_1 is the conversion gain of the first phase detector.
  • the subsequent phase detection and signal transmission work at a lower frequency.
  • the power consumption level will be significantly reduced.
  • the RF signal usually uses the frequency band above 3GHz, and the frequency of the signal transmitted in the RF transceiver chip is higher. Detection and control will undoubtedly increase the power consumption of the chip.
  • FDIV can be used to divide the high-frequency signal, which can reduce the power consumption of the chip.
  • the RF signal frequency is usually above 20GHz, and there is also the problem of high power consumption of the above-mentioned chip. Therefore, FDIV can be used to divide the high-frequency signal, which can reduce the power of the chip. Consumption.
  • the first phase difference can also be the phase difference between the frequency-multiplied signal of the first local oscillator signal and the frequency-multiplied signal of the second local oscillator signal.
  • the control principle is the same as The above two methods are similar and can be referred to each other, so I will not repeat them here.
  • the first control signal generated by the first phase-locked loop can be used for phase control of the first phase-locked loop, and can also be used for phase control of the second phase-locked loop. That is to say, in the first implementation, the control signal generated in this chip is used to control the phase of the phase-locked loop in other chips; in the second implementation, the control signal generated in this chip is used to Control the phase of the phase-locked loop in this chip. For these two implementations, the signal direction in the system will be different. The two implementations are briefly introduced below.
  • each radio frequency transceiver chip includes a phase-locked loop and a control circuit coupled with it, and the phase-locked loop is used to provide a local oscillator signal for the radio frequency transceiver chip.
  • the phase-locked loop in the i-th radio frequency transceiver chip is called the i-th phase-locked loop
  • the control circuit in the i-th radio frequency transceiver chip is called the i-th control circuit, 1 ⁇ i ⁇ N.
  • the first control circuit uses the control signal generated by the above solution to control the phase of the second phase-locked loop, so that the second phase-locked loop
  • the phase of the generated local oscillator signal is the same as the phase of the local oscillator signal generated by the first phase-locked loop
  • the control signal generated by the second control circuit is used to control the phase of the third phase-locked loop so that the third lock
  • the phase of the local oscillator signal generated by the phase loop is the same as the phase of the local oscillator signal generated by the second phase-locked loop
  • the control signal generated by the i-th control circuit is used to control the phase of the i+1-th phase-locked loop.
  • the phase of the local oscillator signal generated by the i+1-th phase-locked loop is the same as the phase of the local oscillator signal generated by the i-th phase-locked loop.
  • the first phase-locked loop is used as the reference of other phase-locked loops.
  • the phase of the local oscillator signal of the other phase-locked loop is the same as that of the previous phase-locked loop.
  • the phase is synchronized.
  • the last phase-locked loop may not be provided with a control circuit.
  • the first phase-locked loop does not need to be generated according to the control signal when generating the local oscillator signal; or, the last phase-locked loop may be provided with a control circuit ,
  • the output control signal can be used to control the phase of the first phase-locked loop.
  • the first phase-locked loop can generate the local oscillator signal according to the control signal output by the last control circuit (as shown in Figure 8). Take this method as an example for illustration).
  • the N-1th control circuit adopts the control signal generated by the above scheme to control the phase of the N-1th phase-locked loop, so that the Nth -1
  • the phase of the local oscillator signal generated by the phase-locked loop is the same as the phase of the local oscillator signal generated by the Nth phase-locked loop
  • the control signal generated by the N-2th control circuit is used to phase-lock the N-2th
  • the loop performs phase control so that the phase of the local oscillator signal generated by the N-2th phase-locked loop is the same as the phase of the local oscillator signal generated by the N-1th phase-locked loop...
  • the control signal generated by the first control circuit is used To perform phase control on the first phase-locked loop, so that the phase of the local oscillator signal generated by the first phase-locked loop is the same as the phase of the local oscillator signal generated by the second phase-locked loop.
  • the Nth phase-locked loop is used as the reference of other phase-locked loops.
  • the control circuit may not be provided in the Nth phase-locked loop.
  • the Nth phase-locked loop does not need to be generated according to the control signal when generating the local oscillator signal; or, the Nth phase-locked loop can be set
  • the control circuit the output control signal can be used to control the phase of the Nth phase-locked loop.
  • the Nth phase-locked loop can generate the local oscillator signal according to the control signal output by the first phase-locked loop ( Figure 9 shows this method as an example).
  • both the first phase-locked loop 701 and the second phase-locked loop 703 can respectively generate the first local oscillator signal and the second local oscillator signal based on the first reference clock signal.
  • the first phase-locked loop 701 can adopt different implementations when generating the first local oscillator signal.
  • the first control circuit 702 uses the first control signal to control the phase of the first phase-locked loop 701. Then, when the first phase-locked loop 701 generates the first local oscillator signal, the first control signal Under the control of, the first local oscillator signal is generated according to the first reference clock signal.
  • the first phase-locked loop 701 when the first phase-locked loop 701 generates the first local oscillator signal, it can generate the frequency division control word according to the first control signal; then, the first local oscillator signal is generated according to the first reference clock signal and the frequency division control word.
  • the first control signal can change the frequency division control word of the first phase-locked loop 701, thereby changing the phase of the first local oscillator signal generated by the first phase-locked loop 701.
  • the first control circuit 702 uses the first control signal to control the phase of the second phase-locked loop 703. Therefore, when the second phase-locked loop 703 generates the second local oscillator signal, the first control signal Under the control of, the second local oscillator signal is generated based on the first reference clock signal.
  • the phase synchronization system 700 may also include a third radio frequency transceiver chip, and the third radio frequency transceiver chip includes a third phase-locked loop and a second control circuit; wherein, the third phase-locked loop is used to generate a third The local oscillator signal, the second control circuit is used to detect the second phase difference according to the third local oscillator signal and the first local oscillator signal, and generate the aforementioned second control signal according to the second phase difference for the first phase-locked loop 701 Used when generating the first local oscillator signal.
  • the phase synchronization system 700 may also include a third radio frequency transceiver chip for generating a control signal for controlling the phase of the first phase-locked loop.
  • the third radio frequency transceiver chip includes a third phase locked loop and a second control circuit.
  • the first phase-locked loop 701 when the first phase-locked loop 701 generates the first local oscillator signal, it can generate the frequency division control word according to the second control signal; then, the first local oscillator signal is generated according to the first reference clock signal and the frequency division control word.
  • the second control signal can change the frequency division control word of the first phase-locked loop 701, thereby changing the phase of the first local oscillator signal generated by the first phase-locked loop 701.
  • the first control circuit 702 uses the first control signal to control the phase of the second phase-locked loop 703. Then, when the first phase-locked loop 701 generates the first local oscillator signal, it can be based on the first reference clock The signal generates the first local oscillator signal without the control of the control signal.
  • the first phase-locked loop in the system It can be used as a reference for calibration of other phase-locked loops.
  • the first phase-locked loop does not need to be generated according to the control signal when it generates the local oscillator signal.
  • the last phase-locked loop in the system can be As a reference for calibration of other phase-locked loops, the last phase-locked loop may not be generated according to the control signal when generating the local oscillator signal. This is the situation described in the third implementation.
  • the three implementations of the first phase-locked loop 701 generating the first local oscillator signal are listed above.
  • the structure of the first phase-locked loop 701 is similar to the structure of the phase-locked loop in the prior art, but there are differences in signal processing methods. Specifically, referring to FIG.
  • the first phase-locked loop 701 includes: a third phase detector for detecting the phase difference between a reference clock signal and a feedback clock signal; a loop controller and a third phase detector Coupling, used to generate a third control signal according to the phase difference between the first reference clock signal and the feedback clock signal; a controlled oscillator (controllable oscillator, OSC), coupled with the loop controller, used to generate the third control signal according to the third control signal A local oscillator signal; a modulator, used to generate a frequency division control word according to the first control signal or the second control signal, and the frequency control word; a third frequency divider (frequency divider, DIV), and a controlled oscillator and modulation
  • the device is coupled to generate a feedback clock signal according to the first local oscillator signal and the frequency division control word to output to the third phase detector.
  • the phase-locked loop in the embodiments of the present application may be a phase-controllable phase-locked loop (PC-PLL), and the PC-PLL provides a mechanism for local oscillator phase tuning.
  • PC-PLL phase-controllable phase-locked loop
  • the phase difference between the local oscillator signals output by the two PC-PLLs is determined according to the output of the phase detector, and the phase controller generates a control signal according to the phase difference, and the control signal finally acts on the two PCs.
  • the phase of the local oscillator signal output by the PC-PLL is consistent with the phase of the local oscillator signal output by the other PC-PLL.
  • the difference between the PC-PLL and the phase-locked loop in the prior art is that in the prior art, when the modulator in the phase-locked loop generates the frequency division control word, it is generated according to the frequency control word. In the embodiment of the present application, when the PC-PLL generates the frequency division control word, it must be generated according to the control signal. Specifically, a logic circuit can be added to the phase-locked loop provided in the prior art to form a PC-PLL to realize this function. Intervene the behavior of the modulator through the control signal, thereby realizing the adjustment function of the phase of the local oscillator signal output by the PC-PLL.
  • the first phase locked loop 701 includes:
  • Phase detector phase dectector, PD
  • PD Phase dectector
  • E PD (t) K PD ⁇ [ ⁇ REF (t)- ⁇ DIV (t)]
  • the PD may be an analog PD or a digital PD.
  • the output of the analog PD is the voltage or current signal reflecting the phase difference of the input clock.
  • the phase-locked loop using the analog PD is called the analog phase-locked loop;
  • the output of the digital PD is the digital signal reflecting the phase difference of the input clock, and the lock of the digital PD is adopted.
  • the phase loop is called a digital phase locked loop.
  • the loop controller is also called a loop filter in a phase-locked loop system.
  • the common controller types include a proportional controller or a proportional-integral controller. Assuming the value of the output signal of the loop controller is V CTRL , taking a proportional-integral controller as an example, the output of the loop controller can be described as:
  • K I and K P are the proportional gain and integral gain of the proportional-integral controller respectively.
  • the loop controller can also be divided into an analog controller and a digital controller according to the type of signal processed.
  • the analog controller handles analog models such as voltage and current.
  • the controller is realized by components such as resistors, capacitors or operational amplifiers; the digital controller handles digital signals, and the controller is usually a digital logic circuit or a digital signal processor. achieve.
  • Controlled oscillator (controllable oscillator, OSC).
  • the output signal of the controlled oscillator is used as the local oscillator signal.
  • the frequency of the controlled oscillator is controlled by its input control signal VCTRL. Assuming that the value of VCTRL is V CTRL and the conversion gain of the controlled oscillator is K V , the output frequency of the controlled oscillator is:
  • the phases of the first local oscillator signal and the second local oscillator signal are compared and used as an index for determining phase synchronization.
  • the phase information of the local oscillator signal and the frequency information of the local oscillator signal theoretically have an integral relationship:
  • the controlled oscillator can also be divided into a voltage controlled/flow controlled oscillator and a numerically controlled oscillator according to the type of control signal.
  • the frequency control signal of the voltage-controlled/flow-controlled oscillator is a voltage or current signal; the frequency control signal of the numerically controlled oscillator is a digital signal.
  • Frequency divider frequency divider, DIV. This module divides the frequency of the local oscillator signal output by the controlled oscillator, and generates the feedback clock signal CLK_DIV for phase comparison with the reference clock signal. Assuming that the frequency division ratio of the frequency divider is N DIV , the relationship between the frequency of the feedback clock signal and the frequency of the local oscillator signal is:
  • phase of the feedback clock signal after frequency division and the phase of the local oscillator signal are also reduced according to the frequency division ratio.
  • Sigma-Delta modulator (sigma-delta modulator, SDM).
  • SDM Sigma-delta modulator
  • the frequency of the output local oscillator signal of the phase-locked loop is controlled by the frequency control word (FCW), assuming that the expected frequency of the local oscillator signal is f LO and the frequency of the reference clock CLK_REF is f REF ,
  • FCW frequency control word
  • the value of the frequency control word can be expressed as:
  • N FCW is an integer
  • the above-mentioned frequency control word will not be an integer.
  • a Sigma-Delta modulator is required to process the frequency division ratio data.
  • the Sigma-Delta modulator is a digital signal processing circuit. In a phase-locked loop system, its function is mainly to convert a non-integer frequency control word into an integer frequency division sequence that can be accepted by the frequency divider. Suppose the value of the frequency control word is expressed as:
  • N FCW N FCW_INTG + N FCW_FRAC
  • N FCW_INTG and N FCW_FRAC are the integer part and the decimal part of the frequency control word respectively.
  • N DIV is the frequency division control word output from the Sigma-Delta modulator to the frequency divider, that is, the aforementioned frequency division ratio N DIV .
  • the range of N DIV change is related to the type of Sigma-Delta modulator.
  • the frequency divider sees an integer frequency division ratio that changes within a certain range. But in a long time range, the average value of the frequency division ratio seen by the frequency divider is the expected frequency control word, namely:
  • first phase-locked loop 701 is also applicable to other phase-locked loops in the embodiment of the present application, so the specific structure of other phase-locked loops will not be described in detail in this application.
  • the first control circuit 702 may further include: a first driver for receiving the first local oscillator signal and outputting the driven first local oscillator signal to the second control circuit.
  • the first control circuit 702 may further include: a first buffer for buffering the second local oscillator signal.
  • the local oscillator signal transmitted from other chips to this chip can be buffered through the buffer, and then the local oscillator signal output by the phase-locked loop in this chip can be compared with other chips.
  • the local oscillator signal transmitted to this chip performs phase detection; similarly, when the local oscillator signal output by the phase-locked loop in this chip is output to other chips for phase detection, the phase lock in this chip can be locked through the driver
  • the local oscillator signal output by the ring is output to other chips, and the driver can be coupled with buffers in other chips to realize the transmission of the local oscillator signal between chips.
  • the first control circuit 702 can directly detect the phase difference between the first local oscillator signal and the second local oscillator signal to obtain the first phase difference, or the frequency-divided first The phase difference between a local oscillator signal and the frequency-divided second local oscillator signal is detected to obtain the first phase difference. Therefore, for the second implementation mode, the first driver in the first control circuit 702 is used to output the divided first local oscillator signal to the second control circuit, and the first buffer in the first control circuit 702 is used for Buffer the second local oscillator signal after frequency division.
  • the first control circuit 702 may include a first phase detector, a first phase controller, a first frequency divider, a first driver, and a first buffer.
  • the control circuit is applied to a phase synchronization system including three radio frequency transceiver chips, and the phase synchronization system can be as shown in FIG. 12.
  • each chip is equipped with a PC-PLL and a local oscillator phase controller (LO phase controller, LPC).
  • the PC-PLL can be regarded as a specific example of the first phase-locked loop 701
  • the LPC can be regarded as a specific example of the first control circuit 702.
  • PC-PLL is used to generate the local oscillator signal
  • FDIV in LPC is used to divide the frequency of the local oscillator signal generated by PC-PLL
  • PD1 is used to detect the frequency divided by chip 1 and chip 2.
  • CTRL is used to generate the control signal PH_TUNE according to the phase difference between the oscillator signals.
  • the control signal is used for the PC-PLL in chip 2 to generate the local oscillator signal, so that the local oscillator generated by the PC-PLL in chip 2 The signal is consistent with the phase of the local oscillator signal generated by the PC-PLL in chip 1.
  • composition and working principle of the PC-PLL and LPC in chip 2 and chip 3 are similar to those in chip 1, and will not be repeated here.
  • phase synchronization system shown in FIG. 12 only shows the connection relationship between the chips, and does not explicitly show the composition of the transceiver channels in the radio frequency transceiver chip.
  • the composition of the transceiver channel in the radio frequency transceiver chip is not specifically limited.
  • the number of radio frequency transceiver chips included in the phase synchronization system is not specifically limited in the embodiments of the present application.
  • the local oscillator signal can be transmitted between chips through a driver and a buffer.
  • the time delay on the transmission path will cause the phase of the local oscillator signal to change.
  • the factors that cause the phase change mainly include: (1) the driver that sends the local oscillator signal on the n+1th chip; (2) Buffers for receiving local oscillator signals on n chips; (3) Hardware routing of transmission paths between chips.
  • the phase change caused by the above factors can be collectively expressed as a parameter ⁇ PATH_n .
  • the first control circuit 702 may further include: a second phase detector, which is used to calculate the third local oscillator signal and the first local oscillator signal. The third phase difference is detected, and the second control circuit generates a second control signal according to the difference between the second phase difference and the third phase difference.
  • the first phase-locked loop 701 when the first phase-locked loop 701 generates the first local oscillator signal, it can generate the first local oscillator signal according to the first reference clock signal and the second control signal.
  • the second control signal is the control signal generated by the second control circuit, and the second control circuit is used to detect the second phase difference according to the third local oscillator signal generated by the third phase-locked loop and the first local oscillator signal, and according to The second phase difference generates a second control signal.
  • the second phase detector also detects the second phase difference based on the third local oscillator signal generated by the third phase-locked loop and the first local oscillator signal. . Since the first phase locked loop 701 and the first control circuit 702 are integrated in the first radio frequency transceiver chip, and the second control circuit and the third phase locked loop are integrated in the third radio frequency transceiver chip, then the second control circuit detects In the second phase difference, the first local oscillator signal is detected after being transmitted from the first RF transceiver chip to the third RF transceiver chip. The second phase difference includes the first RF transceiver chip to the third RF transceiver chip.
  • the phase deviation caused by the transmission path of the chip when the second phase detector detects the third phase difference, the third local oscillator signal is transmitted from the third RF transceiver chip to the first RF transceiver chip and then detected.
  • the third phase difference includes the phase deviation caused by the transmission path from the third radio frequency transceiver chip to the first radio frequency transceiver chip. Therefore, when the second control circuit generates the second control signal according to the difference between the second phase difference and the third phase difference, the second phase difference and the third phase difference are made the difference, which can cancel the phase deviation caused by the transmission path.
  • the second radio frequency transceiver chip may also include a third control circuit coupled with the second phase-locked loop 703, and the third control circuit may also perform phase detection based on the first local oscillator signal and the second local oscillator signal to obtain The fourth phase difference is transmitted to the first control circuit 702 in the first radio frequency transceiver chip.
  • the first control circuit 702 When the first control circuit 702 generates the first control signal, it can generate the first control signal according to the difference between the first phase difference and the fourth phase difference.
  • the first phase-locked loop 701 and the first control circuit 702 are integrated in the first radio frequency transceiver chip, and the second phase-locked loop 703 and the third control circuit are integrated in the second radio frequency transceiver chip, then the first control circuit When 702 detects the first phase difference, the second local oscillator signal is detected after being transmitted from the second radio frequency transceiver chip to the first radio frequency transceiver chip.
  • the first phase difference includes the second radio frequency transceiver chip to the first radio frequency The phase deviation caused by the transmission path of the transceiver chip; and the third control circuit detects the fourth phase difference by transmitting the first local oscillator signal from the first RF transceiver chip to the second RF transceiver chip and then detects Yes, the fourth phase difference includes the phase deviation caused by the transmission path from the first radio frequency transceiver chip to the second radio frequency transceiver chip. Therefore, when the first control circuit 702 generates the first control signal according to the difference between the first phase difference and the fourth phase difference, after the first phase difference and the fourth phase difference are made, the phase deviation caused by the transmission path can be offset.
  • bidirectional phase detection the manner in which two phase detectors respectively perform phase detection on the phase difference of certain two local oscillator signals is referred to as "bidirectional phase detection" for short.
  • the first control circuit 702 may further include a second driver for receiving the first local oscillator signal and outputting the driven first local oscillator signal to the third control circuit.
  • the third control circuit may further include a buffer for buffering the first local oscillator signal.
  • the first control circuit 702 may also include a second buffer for buffering the third local oscillator signal.
  • the second control circuit may further include a driver for driving the output of the third local oscillator signal.
  • each local oscillator signal when transmitted between chips, a driver and a buffer are passed on the transmission path.
  • the specifications of the driver and buffer in the system are the same, it can be considered that the phase deviation caused by each local oscillator signal is approximately the same when it is transmitted between chips. Therefore, when the control signal is generated according to the difference between the two phase differences (for example, the first control circuit 702 generates the first control signal according to the difference between the first phase difference and the fourth phase difference), the phase deviation caused by the transmission path can be cancelled.
  • a set of phase detectors can be added to each chip of the phase synchronization system shown in FIG. 12, as shown in FIG. 13, the The original phase detector in the LPC is marked as PD1, and the newly added phase detector is marked as PD2, so as to realize bidirectional phase detection.
  • LPC can comprehensively calculate the phase deviation of the local oscillator signals of the two chips based on the phase detection results in the two directions.
  • the working principle of two-way phase detection is based on the PD on two chips respectively detecting the phase deviation of the local oscillator signal in two directions:
  • Direction 1 Transfer the divided local oscillator signal from the n+1th chip to the nth chip.
  • the phase difference of the local oscillator signals on the two chips is detected by PD1 on the nth chip.
  • the output of PD1 on the nth chip is:
  • E PD1_n is the output result of PD1 on the nth chip
  • G PD1_n is the conversion gain of PD1 on the nth chip
  • ⁇ PATH1_n is the local oscillator signal transmission path from the n+ 1th chip to the nth chip The phase change introduced.
  • Direction 2 Transmit the divided local oscillator signal from the nth chip to the n+1th chip.
  • the phase difference of the local oscillator signals on the two chips is detected by PD2 on the n+1th chip.
  • the PD2 output on the n+ 1th chip is:
  • G PD2_n+1 is the conversion gain of PD2 on the n+ 1th chip.
  • the output result of PD2 on the n+1th chip is sent to the nth chip, and the difference between the output result of PD1 on the nth chip is performed again, and you can Get:
  • E PD_n E PD1_n -E PD2_n+1
  • phase error value after the above-mentioned difference processing is sent to the controller for further processing, and a control signal for controlling the phase of the PC-PLL on the n+1 chip is obtained.
  • the local oscillator signals of the two chips can be synchronized finally.
  • radio frequency transceiver chips are used in FIG. 13 to describe the implementation method of the above-mentioned "two-way phase detection". For the application of two chips or more chips, it can be deduced by analogy, which will not be repeated in the embodiment of this application.
  • the phase synchronization system 700 provided by the embodiment of the present application has been introduced above. It is not difficult to see that cross-chip information transmission is required when adopting the above scheme.
  • the first control signal generated by the first phase-locked loop 701 may need to be transmitted to the second phase-locked loop 703 for phase control of the second phase-locked loop 703; for another example, the second phase-locked loop 703 is coupled
  • the fourth phase difference detected by the third control circuit may need to be transmitted to the first control circuit 702 so as to be used when the first control circuit generates the first control signal.
  • the above-mentioned cross-chip information transmission can be realized through a dedicated signal channel. However, such dedicated signal channels often occupy more hardware resources and increase the complexity of the design.
  • control signals and digital interfaces in the system can also be multiplexed to realize cross-chip information transmission.
  • the first radio frequency transceiver chip also includes a first digital interface
  • the second radio frequency transceiver chip also includes a second digital interface
  • the phase synchronization system 700 also includes Control chip; wherein, the first digital interface is coupled with the first control circuit 702 for receiving and outputting the first control signal; the control chip is coupled with the first digital interface and the second digital interface for outputting the first digital interface The first control signal is transmitted to the second digital interface; the second digital interface is coupled with the second phase locked loop 703.
  • the first digital interface and the second digital interface may be a universal digital interface (digital interface, INTF), and the INTF may be used as a common interface for signal transmission between chips.
  • this type of digital interface module is provided on the radio frequency transceiver chip, which serves as a general interface for the upper system to issue instructions to the radio frequency transceiver chip, or the upper system to collect status information from the radio frequency transceiver chip.
  • this interface can be directly multiplexed for cross-chip information transmission, without the need to add resources such as hardware pins.
  • control chip may be a controller chip in the system.
  • the main control chip carries the software and hardware functions of the upper system, and communicates instructions or data with the radio frequency transceiver chip through a universal digital interface.
  • the main control chip can be directly multiplexed for cross-chip information transmission.
  • control chip can be regarded as a part of the same synchronization device 700, or can be regarded as an independent module independent of the same synchronization device 700 in the system.
  • the phase synchronization system may be as shown in FIG. 14.
  • the LPC module is implemented with a digital structure, that is, both PD1 and PD2 are digital phase detectors, and CTRL is a digital controller, so the signals transmitted between chips are all digital signals.
  • the data communication initiated by the main control chip includes (1) read the PH_CTRL signal output by the controller of the nth chip through the general digital interface of the nth chip, and then pass the nth The universal digital interface of +1 chip sends this signal as PH_TUNE to the PC-PLL module; (2) Through the universal digital interface of the n+1th chip, read the phase detector PD2 on the n+1th chip The output PH_ERR2 is then sent to the LPC as PH_ERR_IN through the universal digital interface of the nth chip.
  • the general digital interface between the main control chip and each radio frequency transceiver chip adopts a daisy chain topology.
  • the main control chip first sends instructions or data to the first chip through the universal digital interface of the first chip.
  • the digital interface of the first chip judges whether the instruction or data is sent to the current chip according to the received information. If it is judged that the received information is sent by the main control chip to the current chip, it will be processed on the first chip, otherwise the received instructions or data will be sent to the second chip through the universal digital interface on the first chip Universal digital interface.
  • the second chip is similarly processed and cascaded accordingly.
  • the advantage of the daisy chain topology is that the main control chip only needs a set of digital interfaces to communicate with multiple radio frequency transceiver chips. With the increase in the number of RF transceiver chips in the phase synchronization system, the interfaces can be cascaded sequentially without affecting the information transmission mechanism between the main control chip and the RF transceiver chip.
  • a star topology can also be used.
  • the main control chip and each RF transceiver chip have a set of proprietary universal digital interfaces. That is, the same number of digital interface modules as the RF transceiver chips need to be integrated on the main control chip.
  • the main control chip can directly transmit instructions or data to each radio frequency transceiver chip, and instructions or data do not need to be forwarded through the chip.
  • each radio frequency transceiver chip includes a phase-locked loop and a control circuit as an example.
  • multiple phase-locked loops and multiple corresponding control circuits can also be provided in each chip.
  • each RF transceiver chip can be integrated with multiple phase-locked loops, and each phase-locked loop is used to provide a local oscillator signal for the corresponding RF channel.
  • a control circuit may be configured for each of the multiple phase-locked loops, so as to realize the synchronization of the local oscillator signal of each radio frequency channel in the chip.
  • the first radio frequency transceiver chip may further include: a fourth phase-locked loop for generating a fourth local oscillator signal; a fourth control circuit for detecting the fourth local oscillator signal and the first local oscillator signal
  • the fifth phase difference is used to generate a fourth control signal according to the fifth phase difference
  • the fourth control signal is used to perform phase control on the first phase-locked loop or the fourth phase-locked loop.
  • the first phase-locked loop can be used to provide a local oscillator signal for a part of the radio frequency channel in the first radio frequency transceiver chip
  • the fourth phase-locked loop can be used to provide a local oscillator signal for another part of the radio frequency channel in the first radio frequency transceiver chip .
  • the first phase-locked loop and the fourth phase-locked loop in the first radio frequency transceiver chip can output local oscillator signals with the same phase, so as to provide all radio frequency channels in the first radio frequency transceiver chip with the same phase local oscillator. Vibration signal.
  • two phase-locked loops and two control circuits can be provided in a radio frequency transceiver chip, and each phase-locked loop is used to provide a local oscillator signal for its corresponding radio frequency channel.
  • the local oscillator signals output by the two phase-locked loop modules on the same chip adopt the above-mentioned "two-way phase detection” scheme, and are output through the first local oscillator phase controller (LPC1)
  • the phase control signal adjusts the phase of the second phase controllable phase-locked loop (PC-PLL2).
  • the phases of the local oscillator signals output by the two phase-locked loops on a single chip can be synchronized through the integrated feedback control loop on the chip.
  • a common digital interface is used between the two chips to transfer information between the chips, constructing a cross-chip feedback control loop.
  • the phase between the local oscillator signal output by the second PLL module on the first chip and the local oscillator signal output by the first PLL module on the second chip can be realized Synchronize.
  • phase synchronization of the local oscillator signal in the chip and the phase synchronization of the local oscillator signal between the chips, the phase synchronization of the local oscillator signal of all the radio frequency transceiver chips in the radio frequency system can be realized.
  • the number of chips included in the phase synchronization system and the number of phase-locked loops (and control circuits) included in each chip are examples.
  • the phase synchronization system includes The number of chips and the number of phase-locked loops (and control circuits) included in each chip can be set according to requirements, which are not specifically limited in the embodiment of the present application.
  • the first control circuit 702 performs phase detection according to the first local oscillator signal and the second local oscillator signal to obtain the first phase difference, and generates the first phase difference according to the first phase difference.
  • the control signal uses the first control signal to control the phase of the first phase-locked loop 701 or the second phase-locked loop 703.
  • the first phase difference may reflect the relative phase relationship between the first local oscillator signal and the second local oscillator signal.
  • the solution provided by the embodiment of this application can realize the localization of two radio frequency transceiver chips.
  • the phase of the vibration signal is synchronized.
  • the phase of the first local oscillator signal generated by the first phase-locked loop 701 and the second lock remains the same; or, when the first control signal is generated according to the first phase difference and the first control signal is used to control the second phase-locked loop 703, the second phase-locked loop can be made
  • the phase of the second local oscillator signal generated by 703 is consistent with the phase of the first local oscillator signal generated by the first phase-locked loop 701.
  • phase synchronization system 700 Through the above-mentioned phase synchronization system 700, the phase synchronization of local oscillator signals of multiple chips can be achieved.
  • the first radio frequency transceiver chip further includes: a plurality of first transmission channels, the first phase-locked loop is specifically used to provide a first local oscillator signal for the plurality of first transmission channels; the second radio frequency transceiver chip also includes : Multiple second transmission channels, the second phase-locked loop is specifically used to provide second local oscillator signals for multiple second transmission channels; multiple first transmission channels and multiple second transmission channels are used to support multiple input multiple Out (multiple-input multiple-output, MIMO) transmission.
  • MIMO multiple-input multiple-output
  • the signals transmitted in the first transmission channel and the second transmission channel may be 5G new radio (NR) signals.
  • NR 5G new radio
  • the first radio frequency transceiver chip further includes: a plurality of first transmission channels, the first phase-locked loop is specifically used to provide a first local oscillator signal for the plurality of first transmission channels; a second radio frequency transceiver
  • the machine chip also includes: a plurality of second transmission channels, the second phase-locked loop is specifically used to provide a second local oscillator signal for the plurality of second transmission channels; a plurality of first transmission channels and a plurality of second transmission channels are used for Support phased array transmission.
  • the signals transmitted in the first transmission channel and the second transmission channel may be 5G NR signals.
  • the phase synchronization device 1600 includes a first phase-locked loop 1601 and a first control circuit 1602 integrated in a first radio frequency transceiver chip; wherein,
  • the first phase locked loop 1601 is used to generate the first local oscillator signal.
  • the first control circuit 1602 is used to detect the first phase difference according to the first local oscillator signal and the second local oscillator signal generated by the second phase-locked loop in the second radio frequency transceiver chip, and generate the first phase difference according to the first phase difference The first control signal, and using the first control signal to perform phase control on the first phase-locked loop 1601 or perform phase control on the second phase-locked loop.
  • phase synchronization device 1600 shown in FIG. 16 can be understood as a phase-locked loop and control circuit integrated in a certain radio frequency transceiver chip to provide a local oscillator signal for the radio frequency transceiver chip.
  • the working principle and processing logic of the phase lock loop and the control circuit are the same as the phase lock loop and control circuit in the phase synchronization system 700.
  • the first control circuit 1602 may include: a first phase detector for detecting the first phase difference according to the first local oscillator signal and the second local oscillator signal.
  • the first control circuit 1602 may include: a first phase controller for generating a first control signal according to the first phase difference, and the first control signal is used for controlling the first phase-locked loop 1601 or the second phase-locked loop Frequency division control word.
  • the first phase controller is any one of a proportional controller, an integral controller, and a proportional-integral controller.
  • the first phase-locked loop 1601 is specifically configured to: generate a first local oscillator signal based on the first reference clock signal; the first reference clock signal is the reference clock on which the second phase-locked loop generates the second local oscillator signal signal.
  • the first phase-locked loop 1601 is specifically configured to: under the control of the first control signal, generate the first local oscillator signal according to the first reference clock signal.
  • the first phase-locked loop 1601 is specifically configured to: under the control of the second control signal, generate the first local oscillator signal according to the first reference clock signal, and the second control signal is the second signal in the third radio frequency transceiver chip.
  • the control signal generated by the second control circuit, the second control circuit is used to detect the second phase difference according to the third local oscillator signal and the first local oscillator signal generated by the third phase-locked loop in the third radio frequency transceiver chip, and according to The second phase difference generates a second control signal.
  • the first control circuit 1602 includes a first driver for receiving the first local oscillator signal and outputting the driven first local oscillator signal to the second control circuit.
  • the first control circuit 1602 includes: a first buffer for buffering the second local oscillator signal.
  • the first control circuit 1602 includes: a second phase detector for detecting a third phase difference based on the third local oscillator signal and the first local oscillator signal, and the third phase difference is used for the first
  • the second control circuit generates a second control signal according to the difference between the second phase difference and the third phase difference.
  • the first control circuit 1602 when the first control circuit 1602 generates the first control signal according to the first phase difference, the first control circuit 1602 can generate the first control signal according to the difference between the first phase difference and the fourth phase difference;
  • the four-phase difference is detected by the third control circuit in the second radio frequency transceiver chip coupled with the second phase-locked loop according to the first local oscillator signal and the second local oscillator signal.
  • the first control circuit 1602 includes: a second driver for receiving the first local oscillator signal and outputting the driven first local oscillator signal to the third control circuit.
  • the first control circuit 1602 also includes: a second buffer for buffering the third local oscillator signal.
  • the following method when the first control circuit 1602 detects the first phase difference according to the first local oscillator signal and the second local oscillator signal, the following method can be used: The phase difference with the second local oscillator signal is detected to obtain the first phase difference.
  • the first control circuit 1602 further includes: a first frequency divider, coupled with the first phase-locked loop 1601, and used to divide the frequency of the first local oscillator signal; then, the first control circuit 1602
  • the first control circuit 1602 When the first phase difference is detected according to the first local oscillator signal and the second local oscillator signal, it is specifically used for: the first control circuit 1602 divides the first local oscillator signal through the first frequency divider and passes through the third local oscillator signal. The phase difference of the second local oscillator signal divided by the second frequency divider in the control circuit is detected to obtain the first phase difference, and the second frequency divider has the same division frequency as the first frequency divider.
  • the first phase-locked loop 1601 may include: a third phase detector for detecting the phase difference between the first reference clock signal and the feedback clock signal; a loop controller, coupled with the third phase detector, for detecting the phase difference between the first reference clock signal and the feedback clock signal; The phase difference between a reference clock signal and a feedback clock signal generates a third control signal; a controlled oscillator, coupled with the loop controller, is used to generate the first local oscillator signal according to the third control signal; a modulator is used to generate the first local oscillator signal according to the A control signal or a second control signal and a frequency control word generate a frequency division control word; a third frequency divider, coupled with the controlled oscillator and a modulator, is used to generate feedback based on the first local oscillator signal and the frequency division control word The clock signal is output to the third phase detector.
  • the phase synchronization device 1600 further includes: a first digital interface; wherein, the first digital interface is coupled with the first control circuit 1602 for receiving the first control signal and outputting it to the control chip; the control chip and The first digital interface is coupled with the second digital interface in the second radio frequency transceiver chip, and is used to transmit the first control signal output by the first digital interface to the second digital interface; the second digital interface is coupled with the second phase-locked loop .
  • the first RF transceiver chip also includes: a fourth phase-locked loop for generating a fourth local oscillator signal; a fourth control circuit for The fifth phase difference is detected according to the fourth local oscillator signal and the first local oscillator signal, and a fourth control signal is generated according to the fifth phase difference, and the first phase-locked loop 1601 is phase controlled or adjusted by the fourth control signal.
  • the fourth phase-locked loop performs phase control.
  • the first phase-locked loop can be used to provide a local oscillator signal for a part of the radio frequency channel in the first radio frequency transceiver chip
  • the fourth phase-locked loop can be used to provide a local oscillator signal for another part of the radio frequency channel in the first radio frequency transceiver chip .
  • phase synchronization system 700 shown in FIG. 7 can be regarded as a radio frequency system adopting a multi-chip splicing scheme
  • phase synchronization device 1600 shown in FIG. 16 can be regarded as the phase synchronization system 700 shown in FIG. It is a device that provides a local oscillator signal for a radio frequency transceiver chip.
  • phase synchronization system 700 For the working principles, implementation methods, and technical effects that are not described in detail in the phase synchronization device 1600, please refer to the relevant description of the phase synchronization system 700, which will not be repeated here.
  • the first radio frequency transceiver chip further includes: a plurality of first transmission channels, the first phase-locked loop is specifically used to provide a first local oscillator signal for the plurality of first transmission channels; the second radio frequency transceiver chip also includes : Multiple second transmission channels, the second phase-locked loop is specifically used to provide second local oscillator signals for multiple second transmission channels; multiple first transmission channels and multiple second transmission channels are used to support MIMO transmission.
  • the signals transmitted in the first transmission channel and the second transmission channel may be 5G NR signals.
  • the first radio frequency transceiver chip further includes: a plurality of first transmission channels, the first phase-locked loop is specifically used to provide a first local oscillator signal for the plurality of first transmission channels; a second radio frequency transceiver
  • the machine chip also includes: a plurality of second transmission channels, the second phase-locked loop is specifically used to provide a second local oscillator signal for the plurality of second transmission channels; a plurality of first transmission channels and a plurality of second transmission channels are used for Support phased array transmission.
  • the signals transmitted in the first transmission channel and the second transmission channel may be 5G NR signals.
  • an embodiment of the present application also provides a transceiver device.
  • the transceiver device includes the first radio frequency transceiver chip and the second radio frequency transceiver chip described in the phase synchronization system 700.
  • the first radio frequency transceiver chip further includes: a plurality of first transmission channels, the first phase-locked loop is specifically used to provide a first local oscillator signal for the plurality of first transmission channels; the second radio frequency transceiver chip further includes: Two second transmission channels, the second phase-locked loop is specifically used to provide second local oscillator signals for multiple second transmission channels; multiple first transmission channels and multiple second transmission channels are used to support MIMO transmission or phase control Array transmission.
  • the signals transmitted in the first transmission channel and the second transmission channel may be 5G NR signals.

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Abstract

一种相位同步装置、相位同步系统及收发装置，用以为多芯片拼接方案中的每个射频收发机芯片提供相位一致的本振信号。相位同步系统包括：第一射频收发机芯片和第二射频收发机芯片，第一射频收发机芯片包括第一锁相环和第一控制电路，第二射频收发机芯片包括第二锁相环；其中，第一锁相环，用于产生第一本振信号；第二锁相环，用于产生第二本振信号；第一控制电路，用于根据第一本振信号以及第二本振信号检测得到第一相位差，并根据第一相位差产生第一控制信号，以及利用第一控制信号对第一锁相环进行相位控制或对第二锁相环进行相位控制。

Description

一种相位同步装置、相位同步系统及收发装置 技术领域
本申请涉及通信技术领域，尤其涉及一种相位同步装置、相位同步系统及收发装置。
背景技术
在第五代移动通信(5G)系统中，多天线技术被作为提升系统吞吐率的核心技术，将会得到广泛应用。
为支持多天线技术，无线终端的射频收发机需要提供多个收发通道。如图1所示为一种支持多天线技术的射频收发机。在该射频收发机中集成了n路射频收发通道(CH1、CH2…CHn)。各个收发通道电路构成基本相同，包括低噪声放大器(low-noise amplifier，LNA)、功率放大器(power amplifier，PA)以及移相器(phase shifter，PHS)等。通过为各个收发通道的PHS配置合理的移相参数，即可利用多个天线(antenna，ANT)实现波束成形(Beamforming)，获得在特定空间方向上的等效天线增益提升的效果。
在接收方向上，各个ANT接收的信号经过LNA放大后，经过PHS进行移相操作。通过配置各路PHS的移相参数，可以获得特定方向的等效天线增益提升。经过移相处理后的接收信号，通过功率合路器(power combiner，PC)合成为一路信号。合路之后的信号经过下变频器(down-converter，DC)搬移到更低的载频上进行处理。
在发射方向上，基带信号变频至中频信号后送入发射机，并经过上变频器(up-converter，UC)进行第二次变频后搬移至射频载频。然后，信号经过功率分路器(power splitter，PS)分成n路，分别送入n路射频收发通道中。送入各个射频收发通道中的信号经过PHS的移相处理，再通过PA发送至ANT，并通过ANT辐射到自由空间。通过给各路PHS配置合适的移相参数，即可使得各个ANT辐射的发射信号在空间上进行合成，在特定的空间方向上形成较大的发射功率。
在一些应用场景下，系统有可能使用到更多天线数目，用以进一步提升波束成形特性。受到成本、功耗、实现复杂度等限制，一颗射频收发机芯片上能够提供的射频通道数是有限的，因而需要采用多芯片拼接的方案，实现天线阵列的扩展。图2示出了一种天线阵列扩展方法的示例，在该示例中，每一颗芯片独立支持了2×2规模的天线阵列(ANT1～ANT4)，总共采用4颗同样的芯片(CHIP1～CHIP4)拼接成了一个4×4规模的天线阵列，实现了天线阵列扩展。图3示出了另一种天线阵列扩展的实现方式，在该示例中，天线阵列的实现与芯片解耦，芯片通过射频导线与天线馈点连接。
无论采用何种天线阵列扩展方式，都会涉及到多颗射频收发机芯片的并联使用。示例性地，图4所示的射频收发机可应用于支持多天线技术的射频系统。图4所示的射频收发机中包括两颗射频收发机芯片，每颗芯片中集成了n路射频收发通道。其中，芯片1和芯片2各自采用本芯片内部的锁相环(phase locked loop，PLL)给上、下变频操作提供本振信号。也就是说，两颗芯片的本振信号是各自独立的。由于两颗芯片的锁相环采用了相同的参考时钟信号(CLK_REF)，因此这两个锁相环产生的本振信号的频率是相同的，但是它们的相位关系很难保持一致。两颗芯片各自本振信号的相位差，将会影响两颗芯片各自对应天线发射信号载频的相对相位关系，进而影响到多天线系统的波束成形性能。
因此，在多天线系统中，当使用多个PLL分别为多芯片拼接方案中的每个射频收发机提供本振信号时，如何使得多个PLL输出的本振信号的相位一致，是一个亟需解决的问题。
发明内容
本申请实施例提供了一种相位同步装置、相位同步系统及收发装置，用以为多芯片拼接方案中的每个射频收发机芯片提供相位一致的本振信号。
第一方面，本申请实施例提供一种相位同步系统，包括第一射频收发机芯片和第二射频收发机芯片，第一射频收发机芯片包括第一锁相环和第一控制电路，第二射频收发机芯片包括第二锁相环。其中，第一锁相环，用于产生第一本振信号；第二锁相环，用于产生第二本振信号；第一控制电路，用于根据第一本振信号以及第二本振信号进行相位检测得到第一相位差，并根据第一相位差产生第一控制信号，以及利用第一控制信号对第一锁相环进行相位控制或对第二锁相环进行相位控制。
采用第一方面提供的相位同步系统，第一控制电路根据第一本振信号和第二本振信号进行相位检测得到第一相位差，并根据第一相位差产生第一控制信号，利用第一控制信号对第一锁相环或第二锁相环进行相位控制。其中，第一相位差可以反映第一本振信号和第二本振信号之间的相对相位关系。通过构建的这一反馈控制系统架构，可以达到第一相位控制器和第二相位控制器输出的本振信号的相位一致的目的，即在第一相位检测器的输出端可以看到第一相位差的数值趋于0。由于第一锁相环置于第一射频收发机芯片、第二锁相环置于第二射频收发机芯片，因而采用第一方面提供的相位同步系统可以实现两颗射频收发机芯片的本振信号的相位同步。具体地，根据第一相位差产生第一控制信号并利用第一控制信号去控制第一锁相环时，可以使得第一锁相环产生的第一本振信号的相位与第二锁相环产生的第二本振信号的相位保持一致；或者，根据第一相位差产生第一控制信号并利用第一控制信号去控制第二锁相环时，可以使得第二锁相环产生的第二本振信号的相位与第一锁相环产生的第一本振信号的相位保持一致。
具体地，第一控制电路可以包括：第一相位检测器，用于根据第一本振信号以及第二本振信号检测得到第一相位差。
具体地，第一控制电路可以包括：第一相位控制器，用于根据第一相位差产生第一控制信号，第一控制信号用于控制第一锁相环或第二锁相环的分频控制字。
在一种可能的设计中，第一锁相环具体用于：基于第一参考时钟信号产生第一本振信号；第二锁相环，具体用于：基于第一参考时钟信号产生第二本振信号。
采用上述方案，第一锁相环和第二锁相环基于同一参考时钟信号产生本振信号，则第一本振信号和第二本振信号的频率一致。那么，第一本振信号和第二本振信号即为频率和相位均相同的本振信号。
在第一方面提供的相位同步系统中，根据系统中的控制信号的走向，第一锁相环在产生第一本振信号时，可以采用不同的实现方式。
实现方式一
在实现方式一中，第一控制电路利用第一控制信号对第一锁相环进行相位控制，那么，第一锁相环在产生第一本振信号时，在第一控制信号的控制下，根据第一参考时钟信号产生第一本振信号。
具体地，第一锁相环在产生第一本振信号时，可以通过如下方式实现：根据第一控制 信号产生分频控制字；根据第一参考时钟信号和分频控制字产生第一本振信号。
采用上述方案，第一控制信号可以改变第一锁相环的分频控制字，从而改变第一锁相环产生的第一本振信号的相位。
实现方式二
在实现方式二中，第一控制电路利用第一控制信号对第二锁相环进行相位控制，因此，第二锁相环在产生第二本振信号时，可以在第一控制信号的控制下，基于第一参考时钟信号产生第二本振信号。
那么，第一方面提供的相位同步系统还包括：第三射频收发机芯片，第三射频收发机芯片包括第三锁相环和第二控制电路；其中，第三锁相环用于产生第三本振信号；第二控制电路用于根据第三本振信号以及第一本振信号检测得到第二相位差，并根据第二相位差产生第二控制信号；第一锁相环在产生第一本振信号时，可以在第二控制信号的控制下，根据第一参考时钟信号产生第一本振信号。
也就是说，第一控制电路产生的第一控制信号输出至第二锁相环，用于对第二锁相环进行相位控制。那么，对于第一锁相环来说，第一方面提供的相位同步系统中还可包含第三射频收发机芯片，用以产生对第一锁相环进行相位控制的控制信号。具体地，该第三射频收发机芯片包括第三锁相环和第二控制电路。
具体地，在实现方式二中，第一锁相环在产生第一本振信号时，可以通过如下方式实现：根据第二控制信号产生分频控制字；根据第一参考时钟信号和分频控制字产生第一本振信号。
采用上述方案，第二控制信号可以改变第一锁相环的分频控制字，从而改变第一锁相环产生的第一本振信号的相位。
实现方式三
在实现方式三中，第一锁相环在产生第一本振信号时，根据第一参考时钟信号产生第一本振信号。
采用上述方案，第一锁相环可以作为其他锁相环校准的基准，第一锁相环在产生本振信号时无需根据控制信号产生。
在一种可能的设计中，第一锁相环包括：第三相位检测器，用于检测第一参考时钟信号与反馈时钟信号的相位差；环路控制器，与第三相位检测器耦合，用于根据第一参考时钟信号与反馈时钟信号的相位差产生第三控制信号；受控振荡器，与环路控制器耦合，用于根据第三控制信号产生第一本振信号；调制器，用于根据第一控制信号或第二控制信号，以及频率控制字产生分频控制字；第三分频器，与受控振荡器和调制器耦合，用于根据第一本振信号和分频控制字产生反馈时钟信号输出至第三相位检测器。
现有技术中，锁相环中的调制器在产生分频控制字时，是根据频率控制字产生的。而在第一方面提供的相位同步系统中，第一锁相环在产生分频控制字时，还要根据控制信号产生。具体地，可以在现有技术中提供的锁相环中加入逻辑电路形成第一锁相环，以实现该功能。通过控制信号来干预调制器的行为，从而实现第一锁相环输出的本振信号的相位的调节功能。
在一种可能的设计中，第一控制电路包括：第一驱动器，用于接收第一本振信号并将驱动后的第一本振信号输出至第二控制电路。
进一步地，第一控制电路还可以包括：第一缓冲器，用于缓存第二本振信号。
采用上述方案，对于在芯片间传输的本振信号来说，可以通过缓冲器来缓存其他芯片传输到本芯片的本振信号，进而将本芯片中的锁相环输出的本振信号与其他芯片传输到本芯片的本振信号进行相位检测；同样地，在将本芯片中的锁相环输出的本振信号输出到其他芯片上用于相位检测时，也可以通过驱动器将本芯片中的锁相环输出的本振信号输出至其他芯片，该驱动器可以与其他芯片中的缓冲器耦合，实现本振信号的传输。
在第一方面提供的相位同步系统中，可以通过驱动器和缓冲器实现本振信号在芯片间传输。但是，本振信号在芯片间传输时，传输路径上的时延会引起本振信号的相位变化。
为了减小传输路径中引入的相位偏差，在一种可能的设计中，第一控制电路包括：第二相位检测器，用于根据第三本振信号和第一本振信号检测得到第三相位差，第二控制电路根据第二相位差与第三相位差之差，产生第二控制信号。
在第一控制电路中包括第二相位检测器的情况下，第二相位检测器同样根据第三锁相环产生的第三本振信号以及第一本振信号检测得到第二相位差。由于第一锁相环和第一控制电路集成在第一射频收发机芯片中，第二控制电路和第三锁相环集成在第三射频收发机芯片中，那么，第二控制电路检测第二相位差时，是将第一本振信号由第一射频收发机芯片传输至第三射频收发机芯片后检测的，第二相位差中包含第一射频收发机芯片至第三射频收发机芯片这一传输路径引起的相位偏差；而第二相位检测器在检测第三相位差时，是将第三本振信号由第三射频收发机芯片传输至第一射频收发机芯片后检测的，第三相位差中包含第三射频收发机芯片至第一射频收发机芯片这一传输路径引起的相位偏差。因此，第二控制电路根据第二相位差与第三相位差之差产生第二控制信号时，将第二相位差和第三相位差做差，可以抵消传输路径引起的相位偏差。
在一种可能的设计中，第二射频收发机芯片还包括：第三控制电路，用于根据第一本振信号和第二本振信号检测得到第四相位差；第一控制电路在产生第一控制信号时，具体用于：根据第一相位差与第四相位差之差，产生第一控制信号。
采用上述方案，对于与第二锁相环耦合的第三控制电路，其也可根据第一本振信号和第二本振信号进行相位检测，得到第四相位差，并将第四相位差传输至第一控制电路。第一控制电路在产生第一控制信号时，可以根据第一相位差与第四相位差之差，产生第一控制信号。
由于第一锁相环和第一控制电路集成在第一射频收发机芯片中，第二锁相环和第三控制电路集成在第二射频收发机芯片中，那么，第一控制电路检测第一相位差时，是将第二本振信号由第二射频收发机芯片传输至第一射频收发机芯片后检测的，第一相位差中包括第二射频收发机芯片到第一射频收发机芯片这一传输路径引起的相位偏差；而第三控制电路在检测第四相位差时，是将第一本振信号由第一射频收发机芯片传输至第二射频收发机芯片中后检测的，第四相位差中包括第一射频收发机芯片到第二射频收发机芯片这一传输路径引起的相位偏差。因此，第一控制电路根据第一相位差与第四相位差之差产生第一控制信号时，将第一相位差和第四相位差做差之后，可以抵消传输路径引起的相位偏差。
在一种可能的设计中，第一控制电路可以包括：第二驱动器，用于接收第一本振信号并将驱动后的第一本振信号输出至第三控制电路。同样地，第一控制电路还可以包括：第二缓冲器，用于缓存第三本振信号。
采用上述方案，每个本振信号在芯片间传输时，传输路径上均经过一个驱动器和一个缓冲器。在系统中的驱动器和缓冲器的规格相同的情况下，可以认为每个本振信号在芯片 间传输时所引起的相位偏差近似相同。因而在根据两个相位差之差产生控制信号(例如第一控制电路根据第一相位差与第四相位差之差产生第一控制信号)时，可以抵消传输路径引起的相位偏差。
在第一方面提供的相位同步系统中，第一控制电路对第一本振信号以及第二本振信号进行相位检测得到第一相位差，该第一相位差可以反映第一本振信号和第二本振信号之间的相对相位关系。具体实现时，第一相位差可以有多种含义。
第一种：第一相位差是第一本振信号和第二本振信号的相位差
那么，第一相位检测器在根据第一本振信号以及第二本振信号检测得到第一相位差时，具体可通过如下方式实现：第一相位检测器对第一本振信号与第二本振信号的相位差进行检测，得到第一相位差。
在第一种方式中，第一相位检测器直接对第一本振信号和第二本振信号的相位差进行检测，可以根据第一本振信号与第二本振信号的相位差产生第一控制信号，用于对第一锁相环或第二锁相环进行相位控制。
第二种：第一相位差是分频后的第一本振信号和分频后的第二本振信号的相位差
在第二种方式中，第一控制电路还包括：第一分频器，与第一锁相环耦合，用于对第一本振信号进行分频；第三控制电路，还包括：第二分频器，与第二锁相环耦合，用于对第二本振信号进行分频，第二分频器与第一分频器的分频比相同；第一控制电路在根据第一本振信号以及第二本振信号检测得到第一相位差时，具体用于：第一控制电路对经过第一分频器分频后的第一本振信号以及经过第二分频器分频后的第二本振信号的相位差进行检测，得到第一相位差。
在第二种方式中，本振信号经过分频处理后，后级相位检测以及信号传输都工作在较低的频率上，与前述第一种方式相比，功耗水平将会显著降低。
在一种可能的设计中，若第一控制信号输出至第二锁相环，第一射频收发机芯片还包括第一数字接口，第二射频收发机芯片还包括第二数字接口，第一方面提供的相位同步系统还包括控制芯片；其中，第一数字接口与第一控制电路耦合，用于接收第一控制信号并输出；控制芯片与第一数字接口和第二数字接口耦合，用于将第一数字接口输出的第一控制信号传输至第二数字接口；第二数字接口与第二锁相环耦合。
其中，第一数字接口和第二数字接口可以是通用数字接口，通用数字接口可以作为芯片间信号传输的公共接口。通常射频收发机芯片上提供有这一类数字接口模块，作为上层系统给射频收发机芯片下发指令，或者上层系统从射频收发机芯片收集状态信息的通用接口。本申请实施例中可以直接复用这个接口进行跨芯片的信息传输，不需要新增硬件管脚等资源。
其中，控制芯片可以是系统中的主控芯片。主控芯片承载了上层系统的软、硬件功能，并通过通用数字接口与射频收发机芯片进行指令或数据的通信。本申请实施例中可以直接复用主控芯片进行跨芯片的信息传输。
采用上述方案，可以复用现有芯片和接口实现跨芯片的信息传输，以实现本振信号的相位同步。
在一种可能的设计中，第一射频收发机芯片还包括：第四锁相环，用于产生第四本振信号；第四控制电路，用于根据第四本振信号以及第一本振信号检测得到第五相位差，并根据第五相位差产生第四控制信号，以及利用第四控制信号对第一锁相环进行相位控制或 对第四锁相环进行相位控制。
其中，第一锁相环可用于为第一射频收发机芯片中的一部分射频通道提供本振信号，第四锁相环可用于为第一射频收发机芯片中的另一部分射频通道提供本振信号。采用上述方案，第一射频收发机芯片中的第一锁相环和第四锁相环可以输出相位一致的本振信号，从而为第一射频收发机芯片内的所有射频通道提供相位一致的本振信号。
在一种可能的设计中，第一射频收发机芯片还包括：多个第一传输通道，第一锁相环具体用于为多个第一传输通道提供第一本振信号；第二射频收发机芯片还包括：多个第二传输通道，第二锁相环具体用于为多个第二传输通道提供第二本振信号；多个第一传输通道和多个第二传输通道，用于支持多入多出MIMO传输。
具体实现时，第一射频收发机芯片中的多个第一传输通道分别与多个第一天线耦合，第二射频收发机芯片中的多个第二传输通道分别与多个第二天线耦合；多个第一天线和多个第二天线组成MIMO天线阵列；多个第一传输通道和多个第二传输通道均用于发送同一载波频率的信号，或者，多个第一传输通道和多个第二传输通道均用于接收同一载波频率的信号。
其中，第一传输通道和第二传输通道中传输的信号可以是5G NR信号。
在一种可能的设计中，第一射频收发机芯片还包括：多个第一传输通道，第一锁相环具体用于为多个第一传输通道提供第一本振信号；第二射频收发机芯片还包括：多个第二传输通道，第二锁相环具体用于为多个第二传输通道提供第二本振信号；多个第一传输通道和多个第二传输通道，用于支持相控阵传输。
具体实现时，第一射频收发机芯片中的多个第一传输通道分别与多个第一天线耦合，第二射频收发机芯片中的多个第二传输通道分别与多个第二天线耦合；多个第一天线与多个第二天线组成相控阵天线阵列；多个第一传输通道分别传输的多个信号以及多个第二传输通道分别传输的多个信号用于波束赋形。
其中，第一传输通道和第二传输通道中传输的信号可以是5G NR信号。
第二方面，本申请实施例提供一种相位同步装置，该相位同步装置包括集成在第一射频收发机芯片中的第一锁相环和第一控制电路。其中，第一锁相环，用于产生第一本振信号。第一控制电路，用于根据第一本振信号以及由第二射频收发机芯片中的第二锁相环产生的第二本振信号检测得到第一相位差，并根据第一相位差产生第一控制信号，以及利用第一控制信号对第一锁相环进行相位控制或对第二锁相环进行相位控制。
采用第二方面提供的相位同步装置，第一控制电路根据第一本振信号和第二本振信号进行相位检测得到第一相位差，并根据第一相位差产生第一控制信号，利用第一控制信号对第一锁相环或第二锁相环进行相位控制。其中，第一相位差可以反映第一本振信号和第二本振信号之间的相对相位关系。通过构建的这一反馈控制系统架构，可以达到第一相位控制器和第二相位控制器输出的本振信号的相位一致的目的，即在第一相位检测器的输出端可以看到第一相位差的数值趋于0。由于第一锁相环置于第一射频收发机芯片、第二锁相环置于第二射频收发机芯片，因而采用第二方面提供的相位同步装置可以实现两颗射频收发机芯片的本振信号的相位同步。具体地，根据第一相位差产生第一控制信号并利用第一控制信号去控制第一锁相环时，可以使得第一锁相环产生的第一本振信号的相位与第二锁相环产生的第二本振信号的相位保持一致；或者，根据第一相位差产生第一控制信号并 利用第一控制信号去控制第二锁相环时，可以使得第二锁相环产生的第二本振信号的相位与第一锁相环产生的第一本振信号的相位保持一致。
需要说明的是，第二方面提供的相位同步装置可以理解为某一射频收发机芯片中集成的锁相环和控制电路，或者理解为一个射频收发机芯片。在相位同步装置，锁相环和控制电路的工作原理和处理逻辑与第一方面提供的锁相环和控制电路相同。
具体地，第一控制电路可以包括：第一相位检测器，用于根据第一本振信号以及第二本振信号检测得到第一相位差。
具体地，第一控制电路可以包括：第一相位控制器，用于根据第一相位差产生第一控制信号，第一控制信号用于控制第一锁相环或第二锁相环的分频控制字。
其中，第一相位控制器为比例控制器、积分控制器、比例-积分控制器中的任一种。
也就是说，在第二方面提供的相位同步装置中，检测第一相位差和产生第一控制信号的操作可以分别由第一相位检测器和第一相位控制器执行。
可选地，第一锁相环具体用于：基于第一参考时钟信号产生第一本振信号；第一参考时钟信号为第二锁相环产生第二本振信号时所基于的参考时钟信号。
采用上述方案，第一锁相环和第二锁相环基于同一参考时钟信号产生本振信号，则第一本振信号和第二本振信号的频率一致。那么，第一本振信号和第二本振信号即为频率和相位均相同的本振信号。
可选地，第一锁相环具体用于：在第一控制信号的控制下，根据第一参考时钟信号产生第一本振信号。
采用上述方案，第一控制信号可以改变第一锁相环的分频控制字，从而改变第一锁相环产生的第一本振信号的相位。
可选地，第一锁相环具体用于：在第二控制信号的控制下，根据第一参考时钟信号产生第一本振信号，第二控制信号为第三射频收发机芯片中的第二控制电路产生的控制信号，第二控制电路用于根据第三射频收发机芯片中的第三锁相环产生的第三本振信号以及第一本振信号检测得到第二相位差，并根据第二相位差产生第二控制信号。
采用上述方案，第一控制电路产生的第一控制信号输出至第二锁相环，用于对第二锁相环进行相位控制。此外，第三射频收发机芯片中包括第三锁相环和第二控制电路，那么，对于第一锁相环来说，第三射频收发机芯片产生的第二控制信号可以用于对第一锁相环进行相位控制。具体地，第二控制信号可以改变第一锁相环的分频控制字，从而改变第一锁相环产生的第一本振信号的相位。
进一步地，第一控制电路包括：第一驱动器，用于接收第一本振信号并将驱动后的第一本振信号输出至第二控制电路。
相应地，第一控制电路包括：第一缓冲器，用于缓存第二本振信号。
采用上述方案，对于在芯片间传输的本振信号来说，可以通过缓冲器来缓存其他芯片传输到本芯片的本振信号，进而将本芯片中的锁相环输出的本振信号与其他芯片传输到本芯片的本振信号进行相位检测；同样地，在将本芯片中的锁相环输出的本振信号输出到其他芯片上用于相位检测时，也可以通过驱动器将本芯片中的锁相环输出的本振信号输出至其他芯片，该驱动器可以与其他芯片中的缓冲器耦合，实现本振信号的传输。
在一种可能的实现方式中，第一控制电路包括：第二相位检测器，用于根据第三本振信号和第一本振信号检测得到第三相位差，第三相位差用于第二控制电路根据第二相位差 与第三相位差之差产生第二控制信号。
在第一控制电路中包括第二相位检测器的情况下，第二相位检测器同样根据第三锁相环产生的第三本振信号以及第一本振信号检测得到第二相位差。由于第一锁相环和第一控制电路集成在第一射频收发机芯片中，第二控制电路和第三锁相环集成在第三射频收发机芯片中，那么，第二控制电路检测第二相位差时，是将第一本振信号由第一射频收发机芯片传输至第三射频收发机芯片后检测的，第二相位差中包含第一射频收发机芯片至第三射频收发机芯片这一传输路径引起的相位偏差；而第二相位检测器在检测第三相位差时，是将第三本振信号由第三射频收发机芯片传输至第一射频收发机芯片后检测的，第三相位差中包含第三射频收发机芯片至第一射频收发机芯片这一传输路径引起的相位偏差。因此，第二控制电路根据第二相位差与第三相位差之差产生第二控制信号时，将第二相位差和第三相位差做差，可以抵消传输路径引起的相位偏差。
同样地，第一控制电路在根据第一相位差产生第一控制信号时，可以通过如下方式：第一控制电路根据第一相位差与第四相位差之差，产生第一控制信号；第四相位差由第二射频收发机芯片中与第二锁相环耦合的第三控制电路根据第一本振信号和第二本振信号检测得到。
采用上述方案，对于与第二锁相环耦合的第三控制电路，其也可根据第一本振信号和第二本振信号进行相位检测，得到第四相位差，并将第四相位差传输至第一控制电路。第一控制电路在产生第一控制信号时，可以根据第一相位差与第四相位差之差，产生第一控制信号。
由于第一锁相环和第一控制电路集成在第一射频收发机芯片中，第二锁相环和第三控制电路集成在第二射频收发机芯片中，那么，第一控制电路检测第一相位差时，是将第二本振信号由第二射频收发机芯片传输至第一射频收发机芯片后检测的，第一相位差中包括第二射频收发机芯片到第一射频收发机芯片这一传输路径引起的相位偏差；而第三控制电路在检测第四相位差时，是将第一本振信号由第一射频收发机芯片传输至第二射频收发机芯片中后检测的，第四相位差中包括第一射频收发机芯片到第二射频收发机芯片这一传输路径引起的相位偏差。因此，第一控制电路根据第一相位差与第四相位差之差产生第一控制信号时，将第一相位差和第四相位差做差之后，可以抵消传输路径引起的相位偏差。
此外，第一控制电路包括：第二驱动器，用于接收第一本振信号并将驱动后的第一本振信号输出至第三控制电路。第一控制电路还包括：第二缓冲器，用于缓存第三本振信号。
采用上述方案，每个本振信号在芯片间传输时，传输路径上均经过一个驱动器和一个缓冲器。在系统中的驱动器和缓冲器的规格相同的情况下，可以认为每个本振信号在芯片间传输时所引起的相位偏差近似相同。因而在根据两个相位差之差产生控制信号(例如第一控制电路根据第一相位差与第四相位差之差产生第一控制信号)时，可以抵消传输路径引起的相位偏差。
在第一种实现方式中，第一控制电路在根据第一本振信号以及第二本振信号检测得到第一相位差时，可通过如下方式：第一控制电路对第一本振信号与第二本振信号的相位差进行检测，得到第一相位差。
采用第一种实现方式，第一相位检测器直接对第一本振信号和第二本振信号的相位差进行检测，可以根据第一本振信号与第二本振信号的相位差产生第一控制信号，用于对第一锁相环或第二锁相环进行相位控制。
在第二种实现方式中，第一控制电路还包括：第一分频器，与第一锁相环耦合，用于对第一本振信号进行分频；那么，第一控制电路在根据第一本振信号以及第二本振信号检测得到第一相位差时，具体用于：第一控制电路对经过第一分频器分频后的第一本振信号以及经过第三控制电路中的第二分频器分频后的第二本振信号的相位差进行检测，得到第一相位差，第二分频器与第一分频器的分频率相同。
采用第二种实现方式，本振信号经过分频处理后，后级相位检测以及信号传输都工作在较低的频率上，与前述第一种方式相比，功耗水平将会显著降低。
此外，第一锁相环可以包括：第三相位检测器，用于检测第一参考时钟信号与反馈时钟信号的相位差；环路控制器，与第三相位检测器耦合，用于根据第一参考时钟信号与反馈时钟信号的相位差产生第三控制信号；受控振荡器，与环路控制器耦合，用于根据第三控制信号产生第一本振信号；调制器，用于根据第一控制信号或第二控制信号，以及频率控制字产生分频控制字；第三分频器，与受控振荡器和调制器耦合，用于根据第一本振信号和分频控制字产生反馈时钟信号输出至第三相位检测器。
采用上述方案，给出了一种第一锁相环的具体结构。在第二方面提供的相位同步装置中，其他锁相环也可以采用同样的结构，此处不再赘述。
为了实现信号的跨芯片传输，第二方面提供的相位同步装置还包括：第一数字接口；其中，第一数字接口与第一控制电路耦合，用于接收第一控制信号并输出至控制芯片；控制芯片与第一数字接口和第二射频收发机芯片中的第二数字接口耦合，用于将第一数字接口输出的第一控制信号传输至第二数字接口；第二数字接口与第二锁相环耦合。
采用上述方案，可以复用现有芯片和接口实现跨芯片的信息传输，以实现本振信号的相位同步。
此外，针对一颗射频收发机芯片中包含的射频通道数据较多的情况，第一射频收发机芯片还包括：第四锁相环，用于产生第四本振信号；第四控制电路，用于根据第四本振信号以及第一本振信号检测得到第五相位差，并根据第五相位差产生第四控制信号，以及利用第四控制信号对第一锁相环进行相位控制或对第四锁相环进行相位控制。
其中，第一锁相环可用于为第一射频收发机芯片中的一部分射频通道提供本振信号，第四锁相环可用于为第一射频收发机芯片中的另一部分射频通道提供本振信号。
采用上述方案，第一锁相环可用于为第一射频收发机芯片中的一部分射频通道提供本振信号，第四锁相环可用于为第一射频收发机芯片中的另一部分射频通道提供本振信号。因而，第一射频收发机芯片中的第一锁相环和第四锁相环可以输出相位一致的本振信号，从而为第一射频收发机芯片内的所有射频通道提供相位一致的本振信号。
在一种可能的设计中，第一射频收发机芯片还包括：多个第一传输通道，第一锁相环具体用于为多个第一传输通道提供第一本振信号；第二射频收发机芯片还包括：多个第二传输通道，第二锁相环具体用于为多个第二传输通道提供第二本振信号；多个第一传输通道和多个第二传输通道，用于支持MIMO传输。
具体实现时，第一射频收发机芯片中的多个第一传输通道分别与多个第一天线耦合，第二射频收发机芯片中的多个第二传输通道分别与多个第二天线耦合；多个第一天线和多个第二天线组成MIMO天线阵列；多个第一传输通道和多个第二传输通道均用于发送同一载波频率的信号，或者，多个第一传输通道和多个第二传输通道均用于接收同一载波频率的信号。
其中，第一传输通道和第二传输通道中传输的信号可以是5G NR信号。
在一种可能的设计中，第一射频收发机芯片还包括：多个第一传输通道，第一锁相环具体用于为多个第一传输通道提供第一本振信号；第二射频收发机芯片还包括：多个第二传输通道，第二锁相环具体用于为多个第二传输通道提供第二本振信号；多个第一传输通道和多个第二传输通道，用于支持相控阵传输。
具体实现时，第一射频收发机芯片中的多个第一传输通道分别与多个第一天线耦合，第二射频收发机芯片中的多个第二传输通道分别与多个第二天线耦合；多个第一天线与多个第二天线组成相控阵天线阵列；多个第一传输通道分别传输的多个信号以及多个第二传输通道分别传输的多个信号用于波束赋形。
其中，第一传输通道和第二传输通道中传输的信号可以是5G NR信号。
第三方面，本申请实施例提供一种收发装置，该收发机包括上述第一方面及其任一种可能的设计中提供的第一射频收发机芯片和第二射频收发机芯片。其中，第一射频收发机芯片还包括：多个第一传输通道，所述第一射频收发机芯片中的第一锁相环具体用于为所述多个第一传输通道提供所述第一本振信号；所述第二射频收发机芯片还包括：多个第二传输通道，所述第二射频收发机芯片中的第二锁相环具体用于为所述多个第二传输通道提供所述第二本振信号；所述多个第一传输通道和所述多个第二传输通道，用于支持MIMO传输。
具体地，第一射频收发机芯片中的多个第一传输通道分别与多个第一天线耦合，第二射频收发机芯片中的多个第二传输通道分别与多个第二天线耦合；多个第一天线和多个第二天线组成MIMO天线阵列；多个第一传输通道和多个第二传输通道均用于发送同一载波频率的信号，或者，多个第一传输通道和多个第二传输通道均用于接收同一载波频率的信号。
其中，第一传输通道和第二传输通道中传输的信号可以是5G NR信号。
第四方面，本申请实施例提供一种收发装置，该收发机包括上述第一方面及其任一种可能的设计中提供的第一射频收发机芯片和第二射频收发机芯片。其中，第一射频收发机芯片还包括：多个第一传输通道，第一射频收发机芯片中的第一锁相环具体用于为多个第一传输通道提供第一本振信号；第二射频收发机芯片还包括：多个第二传输通道，第二射频收发机芯片中的第二锁相环具体用于为多个第二传输通道提供第二本振信号；多个第一传输通道和多个第二传输通道，用于支持相控阵传输。
具体地，第一射频收发机芯片中的多个第一传输通道分别与多个第一天线耦合，第二射频收发机芯片中的多个第二传输通道分别与多个第二天线耦合；多个第一天线和多个第二天线组成相控阵天线阵列；多个第一传输通道分别传输的多个信号以及多个第二传输通道分别传输的多个信号用于波束赋形。
其中，第一传输通道和第二传输通道中传输的信号可以是5G NR信号。
第五方面，本申请实施例提供一种相位同步系统，该相位同步系统包括N个锁相环以及与N个锁相环一对应的N个控制电路，N＞1。其中，N个锁相环中的第i个锁相环用于产生第一本振信号，1≤i＜N；与第i个锁相环对应的控制电路用于对第一本振信号以及第 i+1个锁相环产生的第二本振信号进行相位检测得到第一相位差，根据第一相位差产生第一控制信号，利用第一控制信号对第i+1个锁相环进行相位控制。
第六方面，本申请实施例提供一种相位同步系统，该相位同步系统包括N个锁相环以及与N个锁相环一一对应的N个控制电路，N＞1。其中，N个锁相环中的第i个锁相环用于产生第一本振信号，1≤i＜N；与第i个锁相环对应的控制电路用于对第一本振信号以及第i+1个锁相环产生的第二本振信号进行相位检测得到第一相位差，根据第一相位差产生第一控制信号，利用第一控制信号对第i个锁相环进行相位控制。
需要说明的是，第二方面和第六方面提供的相位同步装置或相位同步系统中未详细描述的实现方式及其技术效果可以参见第一方面提供的相位同步系统中的相关描述，此处不再赘述。
附图说明
图1为现有技术提供的一种射频收发机的结构示意图；
图2为现有技术提供的一种天线阵列扩展的实现方式的示意图；
图3为现有技术提供的另一种天线阵列扩展的实现方式的示意图；
图4为现有技术提供的一种支持多天线技术的射频系统的结构示意图；
图5为本申请实施例提供的第一种射频系统的结构示意图；
图6为本申请实施例提供的第二种射频系统的结构示意图；
图7为本申请实施例提供的第一种相位同步系统的结构示意图；
图8为本申请实施例提供的第二种相位同步系统的结构示意图；
图9为本申请实施例提供的第三种相位同步系统的结构示意图；
图10为本申请实施例提供的一种第一锁相环的结构示意图；
图11为本申请实施例提供的另一种第一锁相环的结构示意图；
图12为本申请实施例提供的第四种相位同步系统的结构示意图；
图13为本申请实施例提供的第五种相位同步系统的结构示意图；
图14为本申请实施例提供的第六种相位同步系统的结构示意图；
图15为本申请实施例提供的第七种相位同步系统的结构示意图；
图16为本申请实施例提供的一种相位同步装置的结构示意图；
图17为本申请实施例提供的一种收发装置的结构示意图。
具体实施方式
下面，首先对本申请实施例的应用场景加以介绍。
本申请实施例可以应用于多个PLL分别为多芯片拼接方案中的每个射频收发机提供本振信号，且本振信号需保持相位一致的应用场景。
示例性地，本申请实施例可以应用于图5所示的射频系统中。图5所示的射频系统中包括两颗射频收发机芯片，每颗芯片中集成了n路射频收发通道。每路射频收发通道包括LNA、PA以及PHS。通过对各个收发通道的PHS配置合理的移相参数，即可通过多个天 线接收或发射信号的空间合成，形成特定空间方向上的等效天线增益的提升。此外，每颗芯片中还包括UC/DC，用于实现上变频/下变频。
具体地，在接收方向上，各个ANT接收的信号经过LNA放大后，经过PHS进行移相操作。经过移相处理后的接收信号，通过PC合成为一路信号。合路之后的信号经过DC搬移到更低的载频上进行处理。在发射方向上，基带信号变频至中频信号后送入芯片，并经过UC进行第二次变频后搬移至射频载频。然后，信号经过PS分成n路，分别送入n路射频收发通道中。送入各个射频收发通道中的信号经过PHS的移相处理，再通过PA发送至ANT，并通过ANT辐射到自由空间。
在图5所示的射频系统中，通过本申请实施例提供的相位同步装置为每颗芯片中的上、下变频操作提供本振信号，使得每颗芯片进行上、下变频操作时采用相位相同的本振信号。因此，本振信号不会影响ANT间的相对相位关系，每个射频收发通道的相位仅由PHS调节，因而可以提高系统的波束成形性能。
应理解，图5所示的射频系统仅为示意。在另一种实现方式中，射频收发通道和UC/DC也可以分别集成在两个芯片中。采用这种实现方式，仍存在多个PLL分别为多芯片拼接方案中的每个射频收发机提供相位一致的本振信号的应用场景。本申请实施例对此应用场景同样适用。
需要说明的是，在图5所示的射频系统中，以超外差结构为例描述下变频器操作，即先，将信号从射频载频f RF上搬移至中频f IF。经过图5中下变频器后的中频信号需要经过另外一次变频搬移到基带，并通过ADC转换成数字信号进行进一步处理。此外，下变频器也可以基于零中频(ZIF)或低中频(LIF)等结构来实现。
同样地，在图5所示的射频系统中，以超外差结构为例描述上变频操作，即基带信号经过两次变频操作后被搬移至射频频率f RF。图5中的上变频器完成的是第二次变频，即将中频信号搬移至射频载频。此外，上变频操作也可以采用零中频结构来实现，即仅通过一次变频，直接将基带信号搬移到射频载频，或者基于低中频结构来实现上转换。
上变频操作和下变频操作的具体方式对本申请实施例的方案不产生影响，采用现有技术中提供的上变频操作和下变频操作实现即可。因而在本申请实施例中不再对此做详细描述。
此外，在图5所示架构中，包含了各个收发通道对应的天线。实际应用中，天线可以设置在芯片硅片上、芯片封装结构上或者电路板上，本申请实施例对此不做具体限定。
示例性地，本申请实施例可以应用于图6所示的射频系统中。图6所示的射频系统中包括两颗射频收发机芯片，即芯片1和芯片2，每颗芯片中分别集成了n个接收通道(RX1～RXn)以及m个发射通道(TX1～TXm)，可以支持包括n个接收天线以及m个发射天线的多天线系统工作。其中，每个接收通道分别包括LNA、混频器(MIX)、模拟基带处理器(analog baseband，ABB)和模数转换器(analog-to-digital converter，ADC)等；每个发射通道分别包括数模转换器(digital-to-analog converter，DAC)、ABB、调制器(MOD)和功率放大器(Amp)等。
在图6所示的射频系统中，通过本申请实施例提供的相位同步装置，可以为每颗芯片中的接收通道提供相位相同的本振信号，使得每个接收通道的本振信号不会影响接收天线间的相对相位关系；同时，通过本申请实施例提供的相位同步装置，可以为每颗芯片中的 发射通道提供相位相同的本振信号，使得每个发射通道的本振信号不会影响发射天线间的相对相位关系。
需要说明的是，在图6所示的结构中，接收通道和发射通道都采用了零中频结构(ZIF)，即通过一次变频实现基带信号与射频信号之间的转换。实际应用中，上下变频操作也可以通过二次变频实现，本申请实施例中对此不做具体限定。
当然，以上列举的应用场景仅为示例，实际应用中，本申请实施例可以应用于多个锁相环输出本振信号、且本振信号需保持相位一致的其他应用场景。
此外，本申请实施例提供的方案旨在通过相位同步装置和相位同步系统为多芯片拼接方案中的每个射频收发机芯片提供相位一致的本振信号，对射频收发机芯片的具体结构不做限定。
本申请实施例提供一种相位同步系统，用以为多芯片拼接方案中的每个射频收发机芯片提供相位一致的本振信号。
需要说明的是，本申请实施例中，多个，是指两个或两个以上。另外，需要理解的是，在本申请的描述中，“第一”、“第二”等词汇，仅用于区分描述的目的，而不能理解为指示或暗示相对重要性，也不能理解为指示或暗示顺序。本申请中所提到的“耦合”，是指电学连接，具体可以包括直接连接或者间接连接两种方式。下面，对本申请实施例的应用场景加以简单介绍。
下面将结合附图对本申请实施例作进一步地详细描述。
参见图7，为本申请实施例提供的一种相位同步系统。相位同步系统700包括第一射频收发机芯片和第二射频收发机芯片，第一射频收发机芯片中包括第一锁相环701和第一控制电路702，第二射频收发机芯片中包括第二锁相环703。
其中，第一锁相环701用于产生第一本振信号；第二锁相环703用于产生第二本振信号；第一控制电路702用于根据第一本振信号以及第二本振信号进行相位检测得到第一相位差，并根据第一相位差产生第一控制信号，以及利用第一控制信号对第一锁相环701进行相位控制或对第二锁相环703进行相位控制。
具体实现时，第一锁相环701和第二锁相环703可以基于同一参考时钟信号，分别产生第一本振信号和第二本振信号。即，第一锁相环701根据第一参考时钟信号产生第一本振信号，第二锁相环703根据第一参考时钟信号产生第二本振信号。
若第一锁相环701和第二锁相环703基于同一参考时钟信号产生本振信号，则第一本振信号和第二本振信号的频率一致。那么，第一本振信号和第二本振信号即为频率和相位均相同的本振信号。
本申请实施例中，第一控制电路702根据第一本振信号和第二本振信号进行相位检测得到第一相位差，并根据第一相位差产生第一控制信号，利用第一控制信号对第一锁相环701或第二锁相环703进行相位控制。其中，第一相位差可以反映第一本振信号和第二本振信号之间的相对相位关系。通过构建的这一反馈控制系统架构，可以达到第一锁相环701和第二锁相环703输出的本振信号的相位一致的目的，即在第一相位检测器的输出端可以看到趋于零的第一相位差。具体地，根据第一相位差产生第一控制信号并利用第一控制信号去控制第一锁相环701时，可以使得第一锁相环701产生的第一本振信号的相位与第二锁相环703产生的第二本振信号的相位保持一致；或者，根据第一相位差产生第一控制信 号并利用第一控制信号去控制第二锁相环703时，可以使得第二锁相环703产生的第二本振信号的相位与第一锁相环701产生的第一本振信号的相位保持一致。
若相位同步系统700中包含多个射频收发机芯片，则可以通过在每个射频收发机芯片中设置第一锁相环701和第一控制电路702，实现两个锁相环输出的本振信号的相位一致；在锁相环输出的本振信号的相位两两一致的情况下，可以实现多个射频收发机芯片采用相位一致的本振信号。
具体地，本申请实施例中，仍以图7为例，第一控制电路702可以包括：第一相位检测器(phase detector，PD)，用于根据第一本振信号以及第二本振信号检测得到第一相位差。
具体地，本申请实施例中，第一控制电路702可以包括：第一相位控制器，用于根据第一相位差产生第一控制信号，该第一控制信号用于控制第一锁相环或第二锁相环的分频控制字(也可以称为分频系数)。
也就是说，第一控制电路702中，进行相位检测和产生第一控制信号的操作可以分别由两个器件完成。具体地，可以通过第一控制电路702中的第一相位检测器对第一本振信号和第二本振信号进行相位检测，得到第一相位差；然后，第一控制电路702中的第一相位控制器可根据第一相位差产生第一控制信号。
具体实现时，PD的实现方法可以有多种。根据PD输出信号的类型，PD可以分为模拟PD和数字PD两种。其中，模拟PD的输出信号为表征输入信号相位差值的模拟电压或者电流信号；数字PD的输出信号为表征输入信号相位差值的数字信号。数字PD可以采用时间-数字转换器(time-to-digital converter，TDC)电路来实现。
此外，本申请实施例中，相位控制器的主要功能是：根据控制系统的设计要求，对PD的输出进行处理，输出所需要的相位调谐值。相位控制器的设计可以根据系统控制方案，设计为比例控制器(proportional controller)、积分控制器(integral controller)、比例-积分控制器(proportional-integral controller)或者其他类型的控制器。与PD相对应地，相位控制器也可以根据处理信号的类型，区分为模拟相位控制器或者数字相位控制器。模拟相位控制器主要采用电阻、电容以及运算放大器等器件实现。数字相位控制器则采用数字逻辑电路或者数字信号处理器来实现。
如前所述，本申请实施例中，第一控制电路702对第一本振信号以及第二本振信号进行相位检测得到第一相位差，该第一相位差可以反映第一本振信号和第二本振信号之间的相对相位关系。具体实现时，第一相位差可以有多种含义。
第一种：第一相位差是第一本振信号和第二本振信号的相位差
那么，第一相位检测器在根据第一本振信号以及第二本振信号检测得到第一相位差时，具体可通过如下方式实现：第一相位检测器对第一本振信号与第二本振信号的相位差进行检测，得到第一相位差。
在第一种方式中，第一相位检测器直接对第一本振信号和第二本振信号的相位差进行检测，可以根据第一本振信号与第二本振信号的相位差产生第一控制信号，用于对第一锁相环701或第二锁相环703进行相位控制。
第二种：第一相位差是分频后的第一本振信号和分频后的第二本振信号的相位差
在第二种方式中，第一控制电路702还包括：第一分频器(frequency divider，FDIV)，第一分频器与第一锁相环701耦合，用于对第一本振信号进行分频；第二射频收发机芯片中还包括第二分频器，用于对第二本振信号进行分频，第二分频器与第一分频器的分频率相同。那么，第一相位检测器在根据第一本振信号以及第二本振信号检测得到第一相位差时，具体可通过如下方式实现：第一相位检测器对经过第一分频器分频后的第一本振信号以及经过第二分频器分频后的第二本振信号的相位差进行检测，得到第一相位差。假设第一分频器的分频率为M，第一本振信号的频率为f LO_1，第一本振信号的相位为θ LO_1，第一本振信号的调幅信息为A LO_1，则第一分频器的输出信号可以表示为：
Figure PCTCN2019089705-appb-000001
其中，经过分频器分频后的第一本振信号的相位为：
Figure PCTCN2019089705-appb-000002
同样地，假设第二分频器的分频率为M，第二本振信号的频率为f LO_2，第二本振信号的相位为θ LO_2，第二本振信号的调幅信息为A LO_2，则第二分频器的输出信号可以表示为：
Figure PCTCN2019089705-appb-000003
其中，经过分频器分频后的第二本振信号的相位为：
Figure PCTCN2019089705-appb-000004
那么，第一相位差可以表示为：
Figure PCTCN2019089705-appb-000005
进一步地，第一相位检测器的输出(即第一相位差)可以表示为：
Figure PCTCN2019089705-appb-000006
其中，K PD_1为第一相位检测器的转换增益。
在第二种方式中，本振信号经过分频处理后，后级相位检测以及信号传输都工作在较低的频率上，与前述第一种方式相比，功耗水平将会显著降低。例如，在对大规模多输入输出(massive multiple-input multiple-output，massive MIMO)天线系统中，RF信号通常采用3GHz以上频段，射频收发机芯片中传输信号的频率较高，采用高频信号进行检测和控制无疑会增加芯片的功耗，此时可采用FDIV对高频信号进行分频，从而可以降低芯片的功耗。再比如，在5G波束成形(beamforming)场景瞎，RF信号频率通常在20GHz以上，也存在上述芯片功耗较高的问题，因而可采用FDIV对高频信号进行分频，从而可以降低芯片的功耗。
需要说明的是，针对芯片中传输信号频率较低的场景，第一相位差还可以是第一本振信号的倍频信号和第二本振信号的倍频信号的相位差，其控制原理与上述两种方式类似，可以相互参考，这里不再赘述。
相位同步系统700中，第一锁相环产生的第一控制信号可以用于对第一锁相环进行相位控制，也可以用于对第二锁相环进行相位控制。也就是说，在第一种实现方式中，本芯片中产生的控制信号用于对其他芯片中的锁相环进行相位控制；在第二种实现方式中，本芯片中产生的控制信号用于对本芯片中的锁相环进行相位控制。对于这两种实现方式，系统中的信号走向会有所不同，下面对这两种实现方式进行简单介绍。
假设相位同步系统700中包含N个射频收发机芯片，每个射频收发机芯片中包括一个锁相环以及与之耦合的控制电路，该锁相环用于为该射频收发机芯片提供本振信号。为了 方便描述，将第i个射频收发机芯片中的锁相环称为第i个锁相环，将第i个射频收发机芯片中的控制电路称为第i个控制电路，1≤i＜N。
那么，如图8所示，在第一种可能的实现方式中，第一个控制电路采用如上方案产生的控制信号用于对第二个锁相环进行相位控制，使得第二个锁相环产生的本振信号的相位与第一个锁相环产生的本振信号的相位相同；第二个控制电路产生的控制信号用于对第三个锁相环进行相位控制，使得第三个锁相环产生的本振信号的相位与第二个锁相环产生的本振信号的相位相同……第i个控制电路产生的控制信号用于对第i+1个锁相环进行相位控制，使得第i+1个锁相环产生的本振信号的相位与第i个锁相环产生的本振信号的相位相同。
不难看出，在上述实现方式中，第一个锁相环作为其他锁相环的基准，通过控制电路的控制，其他锁相环的本振信号的相位与前一个锁相环的本振信号的相位同步。此外，最后一个锁相环中可以不设置控制电路，在这种情况下，第一个锁相环在产生本振信号时无需根据控制信号产生；或者，最后一个锁相环中可以设置控制电路，其输出的控制信号可以用于对第一个锁相环进行相位控制，此时第一个锁相环在产生本振信号时可以根据最后一个控制电路输出的控制信号产生(图8中以此方式为例进行示意)。
此外，如图9所示，在第二种可能的实现方式中，第N-1个控制电路采用如上方案产生的控制信号用于对第N-1个锁相环进行相位控制，使得第N-1个锁相环产生的本振信号的相位与第N个锁相环产生的本振信号的相位相同；第N-2个控制电路产生的控制信号用于对第N-2个锁相环进行相位控制，使得第N-2个锁相环产生的本振信号的相位与第N-1个锁相环产生的本振信号的相位相同……第一个控制电路产生的控制信号用于对第一个锁相环进行相位控制，使得第一个锁相环产生的本振信号的相位与第二个锁相环产生的本振信号的相位相同。
不难看出，在上述实现方式中，第N个锁相环作为其他锁相环的基准，通过每个射频收发机芯片中的控制电路的控制，该射频收发机芯片内的锁相环的本振信号的相位与后一个锁相环的本振信号的相位同步。此外，第N个锁相环中可以不设置控制电路，在这种情况下，第N个锁相环在产生本振信号时无需根据控制信号产生；或者，第N个锁相环中可以设置控制电路，其输出的控制信号可以用于对第N个锁相环进行相位控制，此时第N个锁相环在产生本振信号时可以根据第一个锁相环输出的控制信号产生(图9中以此方式为例进行示意)。
如前所述，第一锁相环701和第二锁相环703均可以基于第一参考时钟信号，分别产生第一本振信号和第二本振信号。根据系统中的控制信号的走向(例如在图8和图9的示例中，控制信号的走向不同)，第一锁相环701在产生第一本振信号时，可以采用不同的实现方式。
实现方式一
在实现方式一中，第一控制电路702利用第一控制信号对第一锁相环701进行相位控制，那么，第一锁相环701在产生第一本振信号时，可以在第一控制信号的控制下，根据第一参考时钟信号产生第一本振信号。
具体地，第一锁相环701在产生第一本振信号时，可以根据第一控制信号产生分频控制字；然后，根据第一参考时钟信号和分频控制字产生第一本振信号。
也就是说，第一控制信号可以改变第一锁相环701的分频控制字，从而改变第一锁相环701产生的第一本振信号的相位。
实现方式二
在实现方式二中，第一控制电路702利用第一控制信号对第二锁相环703进行相位控制，因此，第二锁相环703在产生第二本振信号时，可以在第一控制信号的控制下，基于第一参考时钟信号产生第二本振信号。
那么，对于第一锁相环701来说，第一锁相环701在产生第一本振信号时，可以在第二控制信号的控制下，根据第一参考时钟信号产生第一本振信号。也就是说，在相位同步系统700中还可以包括第三射频收发机芯片，第三射频收发机芯片包括第三锁相环和第二控制电路；其中，第三锁相环用于产生第三本振信号，第二控制电路用于根据第三本振信号以及第一本振信号检测得到第二相位差，并根据第二相位差产生上述第二控制信号，以供第一锁相环701在产生第一本振信号时使用。也就是说，第一控制电路701产生的第一控制信号输出至第二锁相环703，用于对第二锁相环703进行相位控制。那么，对于第一锁相环701来说，相位同步系统700中还可包含第三射频收发机芯片，用以产生对第一锁相环进行相位控制的控制信号。具体地，第三射频收发机芯片包括第三锁相环和第二控制电路。
具体地，第一锁相环701在产生第一本振信号时，可以根据第二控制信号产生分频控制字；然后，根据第一参考时钟信号和分频控制字产生第一本振信号。
也就是说，第二控制信号可以改变第一锁相环701的分频控制字，从而改变第一锁相环701产生的第一本振信号的相位。
实现方式三
在实现方式三中，第一控制电路702利用第一控制信号对第二锁相环703进行相位控制，那么，第一锁相环701在产生第一本振信号时，可以根据第一参考时钟信号产生第一本振信号，而无需控制信号的控制。
在前面对图8所示的射频系统的描述中曾提到，若控制电路产生的控制信号用于对其他芯片中的锁相环进行相位控制，那么，系统中的第一个锁相环可以作为其他锁相环校准的基准，第一个锁相环在产生本振信号时可以不根据控制信号产生。同样地，在对图9所示的射频系统的描述中曾提到，若控制电路产生的控制信号用于对本芯片中的锁相环进行相位控制，那么，系统中的最后一个锁相环可以作为其他锁相环校准的基准，最后一个锁相环在产生本振信号时可以不根据控制信号产生。实现方式三中描述的就是这样的情况。
以上列举了第一锁相环701产生第一本振信号的三种实现方式。本申请实施例中，第一锁相环701的结构与现有技术中锁相环的结构类似，但在信号处理方式上又有所差别。具体地，参见图10，第一锁相环701包括：第三相位检测器，用于检测参考时钟信号与反馈时钟信号的相位差；环路控制器(loop controller)，与第三相位检测器耦合，用于根据第一参考时钟信号与反馈时钟信号的相位差产生第三控制信号；受控振荡器(controllable oscillator，OSC)，与环路控制器耦合，用于根据第三控制信号产生第一本振信号；调制器，用于根据第一控制信号或第二控制信号，以及频率控制字产生分频控制字；第三分频器(frequency divider，DIV)，与受控振荡器和调制器耦合，用于根据第一本振信号和分频控制字产生反馈时钟信号输出至第三相位检测器。
本申请实施例中的锁相环可以为相位可控锁相环(phase controllable phase-locked loop，PC-PLL)，PC-PLL提供了本振相位调谐的机制。本申请实施例中，根据相位检测器的输出判断两个PC-PLL输出的本振信号之间的相位差，相位控制器根据该相位差产生控制信号，该控制信号最终作用到上述两个PC-PLL中的任一个PC-PLL上，使得该PC-PLL输出的本振信号的相位与另一PC-PLL输出的本振信号的相位一致。
PC-PLL与现有技术中的锁相环的不同之处在于：现有技术中，锁相环中的调制器在产生分频控制字时，是根据频率控制字产生的。而本申请实施例中，PC-PLL在产生分频控制字时，还要根据控制信号产生。具体地，可以在现有技术中提供的锁相环中加入逻辑电路形成PC-PLL，以实现该功能。通过控制信号来干预调制器的行为，从而实现PC-PLL输出的本振信号的相位的调节功能。
示例性地，第一锁相环701的一种可能的结构示意图可以如图11所示。图11所示的第一锁相环701可以视为图10所示的第一锁相环701的一种具体示例。参见图11，第一锁相环701包括：
1.相位检测器(phase dectector，PD)。用以检测参考时钟信号CLK_REF与反馈时钟信号CLK_DIV之间的相位差，并输出与两个时钟信号相位差相关的信号PD_OUT。假设参考时钟信号的相位为θ REF，反馈时钟信号的相位为θ DIV，且PD的转换增益为K PD，则PD输出信号PD_OUT的值为：
E PD(t)＝K PD·[θ REF(t)-θ DIV(t)]
根据该PD输出数据的类型，该PD可以是模拟PD或数字PD。模拟PD输出的为反映输入时钟相位差值的电压或电流信号，采用模拟PD的锁相环称为模拟锁相环；数字PD输出的为反映输入时钟相位差的数字信号，采用数字PD的锁相环称为数字锁相环。
2.环路控制器(loop controller，CTRL)，在锁相环系统中又可称为环路滤波器(loop filter)。在锁相环系统中，常见的控制器类型包括比例控制器(proportional controller)或者比例-积分控制器(proportional-integral controller)。假设环路控制器的输出信号的值为V CTRL，以比例-积分控制器为例，则环路控制器的输出可以描述为：
Figure PCTCN2019089705-appb-000007
上式中，K I与K P分别为比例-积分控制器的比例增益和积分增益。
与PD的类型相对应，环路控制器也可以按照处理信号的类型区别为模拟控制器和数字控制器。模拟控制器处理的是电压、电流等模拟型号，控制器实现由电阻、电容或者运算放大器等元器件构成；数字控制器处理的是数字信号，控制器通常由数字逻辑电路或者数字信号处理器来实现。
3.受控振荡器(controllable oscillator，OSC)。受控振荡器的输出信号被用作本振信号。受控振荡器的频率受到其输入控制信号VCTRL的控制，假设VCTRL的值为V CTRL，受控振荡器的转换增益为K V，则受控振荡器的输出频率为：
f LO(t)＝f 0+K V·V CTRL(t)
上式中，f 0记为控制值V CTRL＝0时的频率。
在本申请实施例中，第一本振信号和第二本振信号的相位被比较，并被用作判决相位同步的指标。其中，本振信号的相位信息与本振信号的频率信息理论上存在积分关系：
Figure PCTCN2019089705-appb-000008
与相位检测器和环路控制器相对应地，受控振荡器根据控制信号的类型也可分为压控/流控振荡器和数控振荡器。压控/流控振荡器的频率控制信号是电压或电流信号；数控振荡器的频率控制信号是数字信号。
4.分频器(frequency divider，DIV)。该模块对受控振荡器输出的本振信号进行分频操作，并产生与参考时钟信号进行相位比较的反馈时钟信号CLK_DIV。假设分频器的分频比为N DIV，则反馈时钟信号频率与本振信号频率之间的关系是：
Figure PCTCN2019089705-appb-000009
对于相位信息，同样存在如下关系：
Figure PCTCN2019089705-appb-000010
也就是说分频后的反馈时钟信号的相位与本振信号的相位之间同样按照分频比率进行缩小。
5.Sigma-Delta调制器(sigma-delta modulator，SDM)。Sigam-Delta调制器的作用是实现锁相环的小数分频功能。
根据锁相环的工作原理，锁相环输出本振信号的频率由频率控制字(frequency control word，FCW)控制，假设期望的本振信号频率为f LO，且参考时钟CLK_REF的频率是f REF，则频率控制字的值可表示为：
Figure PCTCN2019089705-appb-000011
如果N FCW为一个整数，则可以直接控制DIV的分频比来实现锁相环功能，这种工作模式下，
N DIV＝N FCW
实际应用中，通常上述频率控制字都不会是一个整数。在这种小数分频比的工作模式下，则需要Sigma-Delta调制器对分频比数据进行处理。Sigma-Delta调制器是一个数字信号处理电路，在锁相环系统中，其功能主要是将非整数的频率控制字转换成一个可被分频器接受的整数分频序列。假设频率控制字的数值表示为：
N FCW＝N FCW_INTG+N FCW_FRAC
上式中，N FCW_INTG和N FCW_FRAC分别为频率控制字的整数部分和小数部分。频率控制字经过Sigma-Delta调制器后，输出一系列变化范围在N FCW_INTG附近的整数序列，即：
N DIV∈N FCW_INTG+{…,-2,-1,0,1,2,…}
上式中N DIV是Sigma-Delta调制器输出到分频器的分频控制字，即前述分频比N DIV。N DIV变化的范围与Sigma-Delta调制器的类型有关。
不难看出，经过Sigma-Delta调制器处理后，分频器看到的是一个在一定范围内变化的整数分频比。但是在一个长时间范围来看，分频器看到的分频比的平均值就是期望的频率控制字，即：
N FCW＝MEAN{N DIV[i]}
需要说明的是，以上介绍的第一锁相环701的结构对本申请实施例中的其他锁相环同样适用，因此本申请中不再对其他锁相环的具体结构进行详细介绍。
此外，本申请实施例中，第一控制电路702还可以包括：第一驱动器，用于接收第一本振信号并将驱动后的第一本振信号输出至第二控制电路。
进一步地，第一控制电路702还可以包括：第一缓冲器，用于缓存第二本振信号。
也就是说，对于在芯片间传输的本振信号来说，可以通过缓冲器来缓存其他芯片传输到本芯片的本振信号，进而根据本芯片中的锁相环输出的本振信号与其他芯片传输到本芯片的本振信号进行相位检测；同样地，在将本芯片中的锁相环输出的本振信号输出到其他芯片上用于相位检测时，可以通过驱动器将本芯片中的锁相环输出的本振信号输出至其他芯片，该驱动器可以与其他芯片中的缓冲器耦合，实现本振信号在芯片之间的传输。
如前所述，本申请实施例中，第一控制电路702可以直接对第一本振信号和第二本振信号的相位差进行检测，得到第一相位差，也可以对分频后的第一本振信号和分频后的第二本振信号的相位差进行检测，得到第一相位差。因此，对于第二种实现方式，第一控制电路702中的第一驱动器用于将分频后的第一本振信号输出至第二控制电路，第一控制电路702中的第一缓冲器用于缓存分频后的第二本振信号。
结合以上介绍，在相位同步系统700中，第一控制电路702中可以包括第一相位检测器、第一相位控制器、第一分频器、第一驱动器和第一缓冲器。将该控制电路应用于包含三个射频收发机芯片的相位同步系统中，该相位同步系统可以如图12所示。
在图12所示的相位同步系统中，每个芯片中均设有一个PC-PLL和一个本振相位控制器(LO phase controller，LPC)。PC-PLL可以视为第一锁相环701的一个具体示例，LPC可以视为第一控制电路702的一个具体示例。
以芯片1为例，PC-PLL用于产生本振信号，LPC中的FDIV用于对PC-PLL产生的本振信号进行分频，PD1用于检测芯片1和芯片2中分频后的本振信号之间的相位差，CTRL用于根据该相位差产生控制信号PH_TUNE，该控制信号用于芯片2中的PC-PLL产生本振信号，从而使得芯片2中的PC-PLL产生的本振信号与芯片1中的PC-PLL产生的本振信号的相位一致。
此外，芯片2和芯片3中的PC-PLL和LPC的构成及工作原理与芯片1中类似，此处不再赘述。
需要说明的是，图12所示的相位同步系统中仅示出了芯片间的连接关系，并未明确示出射频收发机芯片中的收发通道的组成。本申请实施例中对射频收发机芯片中的收发通道的组成不做具体限定。此外，本申请实施例中对相位同步系统中包含的射频收发机芯片的数目也不做具体限定。
在本申请实施例提供的相位同步系统700中，可以通过驱动器和缓冲器实现本振信号在芯片间传输。但是，本振信号在芯片间传输时，传输路径上的时延会引起本振信号的相位变化。
在从第n+1颗芯片到第n颗芯片的本振信号传输路径上，造成相位变化的因素主要包括：(1)第n+1颗芯片上发送本振信号的驱动器；(2)第n颗芯片上接收本振信号的缓冲器；(3)芯片间传输路径硬件走线。本示例分析中，可将上述几种因素造成的相位变化集中表示为一个参数θ PATH_n。考虑传输路径上引入的相位变化后，第一相位检测器的输出为：
Figure PCTCN2019089705-appb-000012
从以上公式中可以看出，即使在反馈环路达到稳定的状态下，两颗芯片内的本振信号 也会存在由于芯片间本振信号传输引入的相位偏差M·θ PATH_n。
为了减小上述传输路径中引入的相位偏差，在一种可能的设计中，第一控制电路702中还可以包括：第二相位检测器，用于根据第三本振信号和第一本振信号检测得到第三相位差，第二控制电路根据第二相位差与第三相位差之差，产生第二控制信号。
如前所述，第一锁相环701在产生第一本振信号时，可以根据第一参考时钟信号和第二控制信号产生第一本振信号。其中，第二控制信号为第二控制电路产生的控制信号，第二控制电路用于根据第三锁相环产生的第三本振信号以及第一本振信号检测得到第二相位差，并根据第二相位差产生第二控制信号。
那么，在第一控制电路702中包括第二相位检测器的情况下，第二相位检测器同样根据第三锁相环产生的第三本振信号以及第一本振信号检测得到第二相位差。由于第一锁相环701和第一控制电路702集成在第一射频收发机芯片中，第二控制电路和第三锁相环集成在第三射频收发机芯片中，那么，第二控制电路检测第二相位差时，是将第一本振信号由第一射频收发机芯片传输至第三射频收发机芯片后检测的，第二相位差中包含第一射频收发机芯片至第三射频收发机芯片这一传输路径引起的相位偏差；而第二相位检测器在检测第三相位差时，是将第三本振信号由第三射频收发机芯片传输至第一射频收发机芯片后检测的，第三相位差中包含第三射频收发机芯片至第一射频收发机芯片这一传输路径引起的相位偏差。因此，第二控制电路根据第二相位差与第三相位差之差产生第二控制信号时，将第二相位差和第三相位差做差，可以抵消传输路径引起的相位偏差。
同样地，第二射频收发机芯片中还可以包括与第二锁相环703耦合的第三控制电路，第三控制电路也可根据第一本振信号和第二本振信号进行相位检测，得到第四相位差，并将第四相位差传输至第一射频收发机芯片中的第一控制电路702。第一控制电路702在产生第一控制信号时，可以根据第一相位差与第四相位差之差，产生第一控制信号。
由于第一锁相环701和第一控制电路702集成在第一射频收发机芯片中，第二锁相环703和第三控制电路集成在第二射频收发机芯片中，那么，第一控制电路702检测第一相位差时，是将第二本振信号由第二射频收发机芯片传输至第一射频收发机芯片后检测的，第一相位差中包括第二射频收发机芯片到第一射频收发机芯片这一传输路径引起的相位偏差；而第三控制电路在检测第四相位差时，是将第一本振信号由第一射频收发机芯片传输至第二射频收发机芯片中后检测的，第四相位差中包括第一射频收发机芯片到第二射频收发机芯片这一传输路径引起的相位偏差。因此，第一控制电路702根据第一相位差与第四相位差之差产生第一控制信号时，将第一相位差和第四相位差做差之后，可以抵消传输路径引起的相位偏差。
本申请实施例中，将两个相位检测器分别对某两个本振信号的相位差做相位检测的方式简称为“双向相位检测”。
在上述实现方式中，第一控制电路702中还可以包括第二驱动器，用于接收第一本振信号并将驱动后的第一本振信号输出至第三控制电路。适应性地，第三控制电路中还可以包括用于缓存第一本振信号的缓冲器。
此外，第一控制电路702中还可以包括用于缓存第三本振信号的第二缓冲器。适应性地，第二控制电路中还可以包括用于驱动第三本振信号输出的驱动器。
这样的话，每个本振信号在芯片间传输时，传输路径上均经过一个驱动器和一个缓冲器。在系统中的驱动器和缓冲器的规格相同的情况下，可以认为每个本振信号在芯片间传 输时所引起的相位偏差近似相同。因而在根据两个相位差之差产生控制信号(例如第一控制电路702根据第一相位差与第四相位差之差产生第一控制信号)时，可以抵消传输路径引起的相位偏差。
示例性地，为了实现上述“双向相位检测”方案，可以在图12所示的相位同步系统的每个芯片中新增一组相位检测器(PD2)，如图13所示，每个芯片的LPC中原有的相位检测器记为PD1，新增的相位检测器记为PD2，从而实现双向相位检测。LPC可以根据两个方向的相位检测结果，综合计算两颗芯片本振信号的相位偏差。
双向相位检测的工作原理，是基于两颗芯片上的PD分别检测两个方向上本振信号的相位偏差：
1.方向一：从第n+1颗芯片将分频后的本振信号传送到第n颗芯片。这个方向上，两颗芯片上本振信号的相位差通过第n颗芯片上的PD1检测。考虑本振信号传输路径上引入的相位偏差，第n颗芯片上的PD1输出为：
Figure PCTCN2019089705-appb-000013
上式中，E PD1_n为第n颗芯片上PD1的输出结果，G PD1_n为第n颗芯片上PD1的转换增益，θ PATH1_n为第n+1颗芯片到第n颗芯片本振信号传输路径上引入的相位变化。
2.方向2：从第n颗芯片将分频后的本振信号传送到第n+1颗芯片。这个方向上，两颗芯片上本振信号的相位差通过第n+1颗芯片上的PD2检测。假设从第n颗芯片传输到第n+1颗芯片路径上引入的相位误差为θ PATH2_n，则第n+1颗芯片上的PD2输出为：
Figure PCTCN2019089705-appb-000014
上式中，G PD2_n+1为第n+1颗芯片上PD2的转换增益。
根据上述双向相位检测的结果，将第n+1颗芯片上PD2的输出结果，送入到第n颗芯片上，并与第n颗芯片上PD1输出结果再进行一次求差值处理，即可得：
E PD_n＝E PD1_n-E PD2_n+1
由于构成射频系统的多颗芯片通常是采用同一型号的芯片，芯片上各个模块(包括各个芯片上的PD1与PD2，以及两个传输方向上的驱动器和缓冲器)设计相同。因此可以认为存在以下近似关系：
K PD1_n≈K PD2_n+1≈K PD
θ PATH1_n≈θ PATH2_n≈θ PATH
因此，可得到：
Figure PCTCN2019089705-appb-000015
将上述求差处理之后的相位误差值，送入控制器中进一步处理，并获得控制第n+1颗芯片上PC-PLL相位的控制信号。在反馈控制系统的作用下，最终可以实现两颗芯片本振信号的同步。
需要说明的是，图13中采用了三颗射频收发机芯片来描述上述“双向相位检测”的实现方法。对于两颗芯片或者更多数目芯片的应用，可以依此类推，本申请实施例中不再赘述。
以上对本申请实施例提供的相位同步系统700进行了介绍。不难看出，采用上述方案时需要进行跨芯片的信息传输。比如，第一锁相环701产生的第一控制信号可能需要传输至第二锁相环703，用以对第二锁相环703进行相位控制；再比如，与第二锁相环703耦 合的第三控制电路检测得到的第四相位差可能需要传输至第一控制电路702，以便第一控制电路产生第一控制信号时使用。在实际应用中，可以通过专门的信号通道实现上述跨芯片的信息传输。但是这类专用的信号通道往往会占用比较多的硬件资源，增加设计的复杂度。
本申请实施例中，还可以复用系统中的控制信号和数字接口，以实现跨芯片的信息传输。
在一种可能的设计中，在相位同步系统700中，第一射频收发机芯片中还包括第一数字接口，第二射频收发机芯片中还包括第二数字接口，相位同步系统700中还包括控制芯片；其中，第一数字接口与第一控制电路702耦合，用于接收第一控制信号并输出；控制芯片与第一数字接口和第二数字接口耦合，用于将第一数字接口输出的第一控制信号传输至第二数字接口；第二数字接口与第二锁相环703耦合。
其中，第一数字接口和第二数字接口可以是通用数字接口(digital interface，INTF)，INTF可以作为芯片间信号传输的公共接口。通常射频收发机芯片上提供有这一类数字接口模块，作为上层系统给射频收发机芯片下发指令，或者上层系统从射频收发机芯片收集状态信息的通用接口。本申请实施例中可以直接复用这个接口进行跨芯片的信息传输，不需要新增硬件管脚等资源。
其中，控制芯片可以是系统中的主控芯片(controller chip)。主控芯片承载了上层系统的软、硬件功能，并通过通用数字接口与射频收发机芯片进行指令或数据的通信。本申请实施例中可以直接复用主控芯片进行跨芯片的信息传输。
需要说明的是，本申请实施例中，控制芯片可以视为相同同步装置700的一部分，也可以视为系统中独立于相同同步装置700的一个独立模块。
以图13所示的相位同步系统为例，若该相位同步系统复用主控芯片和INTF进行跨芯片的信息传输，该相位同步系统可以如图14所示。其中，LPC模块采用数字结构实现，即PD1和PD2均为数字相位检测器，CTRL为数字控制器，因而在芯片间传输的信号都是数字信号。在图14所示的相位同步系统中，主控芯片发起的数据通信包括(1)通过第n颗芯片的通用数字接口，读取第n颗芯片的控制器输出的PH_CTRL信号，然后通过第n+1颗芯片的通用数字接口将这个信号作为PH_TUNE送入到PC-PLL模块中；(2)通过第n+1颗芯片的通用数字接口，读取第n+1颗芯片上相位检测器PD2输出的PH_ERR2，然后通过第n颗芯片的通用数字接口，将这个信号作为PH_ERR_IN送入到LPC中。
在图14所示的相位同步系统中，主控芯片与各个射频收发机芯片之间的通用数字接口采用了菊花链形式的拓扑结构。在此拓扑结构中，主控芯片先将指令或数据通过第1颗芯片的通用数字接口送入第1颗芯片。第1颗芯片的数字接口根据接收到的信息判断该指令或数据是否是发给当前芯片。如果判断接收到的信息是主控芯片发给当前芯片的，则在第1颗芯片上进行处理，否则将接收到的指令或数据通过第1颗芯片上的通用数字接口发送给第2颗芯片的通用数字接口。第2颗芯片做类似处理，并依此级联。菊花链拓扑结构的优势是：主控芯片只需要一组数字接口，就可以与多颗射频收发机芯片进行通信。随着相位同步系统中射频收发机芯片数目的增加，接口可以依次级联，不影响主控芯片与射频收发机芯片之间的信息传输机制。
除了上述菊花链拓扑结构外，还可以采用星型拓扑结构。在星型拓扑结构中，主控芯片与每一颗射频收发机芯片都有一组专有的通用数字接口。即在主控芯片上需要集成与射 频收发机芯片数目相同的数字接口模块。采用星型拓扑结构，主控芯片可以将指令或数据直接传输至每个射频收发机芯片，指令或数据无需通过芯片转发。
在前面的示例中，均是以每个射频收发机芯片中包含一个锁相环和一个控制电路为例进行示意的。实际应用中，每个芯片中也可以设置多个锁相环以及多个对应的控制电路。
随着芯片技术的发展，单颗射频收发机芯片的规模也在不断的扩大。在一颗芯片上集成的射频通道数逐步增加。因此，每颗射频收发机芯片上可以集成有多个锁相环，每个锁相环用于为对应的射频通道提供本振信号。在本申请实施例中，可以为多个锁相环中的每个锁相环均配置一个控制电路，从而实现芯片中每个射频通道的本振信号的同步。
也就是说，第一射频收发机芯片还可以包括：第四锁相环，用于产生第四本振信号；第四控制电路，用于根据第四本振信号以及第一本振信号检测得到第五相位差，并根据第五相位差产生第四控制信号，以及利用第四控制信号对第一锁相环进行相位控制或对第四锁相环进行相位控制。
其中，第一锁相环可用于为第一射频收发机芯片中的一部分射频通道提供本振信号，第四锁相环可用于为第一射频收发机芯片中的另一部分射频通道提供本振信号。采用上述方案，第一射频收发机芯片中的第一锁相环和第四锁相环可以输出相位一致的本振信号，从而为第一射频收发机芯片内的所有射频通道提供相位一致的本振信号。
示例性地，如图15所示，在一颗射频收发机芯片中可以设置两个锁相环和两个控制电路，每个锁相环用于为其对应的射频通道提供本振信号。
在图15所示的射频系统中，同一颗芯片上的两个锁相环模块各自输出的本振信号采用上述“双向相位检测”方案，并经过第1个本振相位控制器(LPC1)输出相位控制信号，对第2个相位可控锁相环(PC-PLL2)的相位进行调整。通过单颗芯片上集成的跨模块反馈控制环路，实现单颗芯片上两个锁相环输出本振信号的相位同步。
不难看出，在图15所示的方案中，单颗芯片上两个锁相环输出的本振信号的相位可以通过芯片上集成的反馈控制环路进行同步。两颗芯片之间采用通用数字接口在芯片间传递信息，构建了跨芯片的反馈控制环路。通过芯片间的反馈控制环路，可以实现第1颗芯片上第2个锁相环模块输出的本振信号与第2颗芯片上第1个锁相环模块输出的本振信号之间的相位同步。因此，结合芯片内本振信号的相位同步，以及芯片之间本振信号的相位同步，可以实现射频系统内所有射频收发机芯片的本振信号的相位同步。
需要说明的是，在本申请的各示例中，相位同步系统中包含的芯片数目以及每颗芯片包含的锁相环(以及控制电路)的数目均为示例，实际应用中，相位同步系统中包含的芯片数目以及每颗芯片包含的锁相环(以及控制电路)的数目可以依需求设定，本申请实施例对此不做具体限定。
综上，采用本申请实施例提供的相位同步系统700，第一控制电路702根据第一本振信号和第二本振信号进行相位检测得到第一相位差，并根据第一相位差产生第一控制信号，利用第一控制信号对第一锁相环701或第二锁相环703进行相位控制。其中，第一相位差可以反映第一本振信号和第二本振信号之间的相对相位关系。通过构建的这一反馈控制系统架构，可以达到第一锁相环701和第二锁相环703输出的本振信号的相位一致的目的，即在第一相位检测器的输出端可以看到趋于0的第一相位差。由于第一锁相环701置于第 一射频收发机芯片、第二锁相环703置于第二射频收发机芯片，因而采用本申请实施例提供的方案可以实现两颗射频收发机芯片的本振信号的相位同步。具体地，根据第一相位差产生第一控制信号并利用第一控制信号去控制第一锁相环701时，可以使得第一锁相环701产生的第一本振信号的相位与第二锁相环703产生的第二本振信号的相位保持一致；或者，根据第一相位差产生第一控制信号并利用第一控制信号去控制第二锁相环703时，可以使得第二锁相环703产生的第二本振信号的相位与第一锁相环701产生的第一本振信号的相位保持一致。
通过在上述相位同步系统700，可以实现多芯片的本振信号的相位同步。
实际应用中，第一射频收发机芯片还包括：多个第一传输通道，第一锁相环具体用于为多个第一传输通道提供第一本振信号；第二射频收发机芯片还包括：多个第二传输通道，第二锁相环具体用于为多个第二传输通道提供第二本振信号；多个第一传输通道和多个第二传输通道，用于支持多入多出(multiple-input multiple-output，MIMO)传输。
其中，第一传输通道和第二传输通道中传输的信号可以是5G新空口(new radio，NR)信号。
在另一种应用场景中，第一射频收发机芯片还包括：多个第一传输通道，第一锁相环具体用于为多个第一传输通道提供第一本振信号；第二射频收发机芯片还包括：多个第二传输通道，第二锁相环具体用于为多个第二传输通道提供第二本振信号；多个第一传输通道和多个第二传输通道，用于支持相控阵传输。
其中，第一传输通道和第二传输通道中传输的信号可以是5G NR信号。
基于同一发明构思，本申请实施例还提供一种相位同步装置。参见图16，该相位同步装置1600包括集成在第一射频收发机芯片中的第一锁相环1601和第一控制电路1602；其中，
第一锁相环1601，用于产生第一本振信号。
第一控制电路1602，用于根据第一本振信号以及由第二射频收发机芯片中的第二锁相环产生的第二本振信号检测得到第一相位差，并根据第一相位差产生第一控制信号，以及利用第一控制信号对第一锁相环1601进行相位控制或对第二锁相环进行相位控制。
需要说明的是，在图16所示的相位同步装置1600可以理解为某一射频收发机芯片中集成的锁相环和控制电路，用以为该射频收发机芯片提供本振信号。在相位同步装置1600中，锁相环和控制电路的工作原理和处理逻辑与相位同步系统700中的锁相环和控制电路相同。
具体地，第一控制电路1602可以包括：第一相位检测器，用于根据第一本振信号以及第二本振信号检测得到第一相位差。
具体地，第一控制电路1602可以包括：第一相位控制器，用于根据第一相位差产生第一控制信号，第一控制信号用于控制第一锁相环1601或第二锁相环的分频控制字。
其中，第一相位控制器为比例控制器、积分控制器、比例-积分控制器中的任一种。
可选地，第一锁相环1601具体用于：基于第一参考时钟信号产生第一本振信号；第一参考时钟信号为第二锁相环产生第二本振信号时所基于的参考时钟信号。
可选地，第一锁相环1601具体用于：在第一控制信号的控制下，根据第一参考时钟信号产生第一本振信号。
可选地，第一锁相环1601具体用于：在第二控制信号的控制下，根据第一参考时钟信号产生第一本振信号，第二控制信号为第三射频收发机芯片中的第二控制电路产生的控制信号，第二控制电路用于根据第三射频收发机芯片中的第三锁相环产生的第三本振信号以及第一本振信号检测得到第二相位差，并根据第二相位差产生第二控制信号。
进一步地，第一控制电路1602包括：第一驱动器，用于接收第一本振信号并将驱动后的第一本振信号输出至第二控制电路。
相应地，第一控制电路1602包括：第一缓冲器，用于缓存第二本振信号。
在一种可能的实现方式中，第一控制电路1602包括：第二相位检测器，用于根据第三本振信号和第一本振信号检测得到第三相位差，第三相位差用于第二控制电路根据第二相位差与第三相位差之差产生第二控制信号。
那么，第一控制电路1602在根据第一相位差产生第一控制信号时，可以通过如下方式：第一控制电路1602根据第一相位差与第四相位差之差，产生第一控制信号；第四相位差由第二射频收发机芯片中与第二锁相环耦合的第三控制电路根据第一本振信号和第二本振信号检测得到。
此外，第一控制电路1602包括：第二驱动器，用于接收第一本振信号并将驱动后的第一本振信号输出至第三控制电路。第一控制电路1602还包括：第二缓冲器，用于缓存第三本振信号。
在第一种实现方式中，第一控制电路1602在根据第一本振信号以及第二本振信号检测得到第一相位差时，可通过如下方式：第一控制电路1602对第一本振信号与第二本振信号的相位差进行检测，得到第一相位差。
在第二种实现方式中，第一控制电路1602还包括：第一分频器，与第一锁相环1601耦合，用于对第一本振信号进行分频；那么，第一控制电路1602在根据第一本振信号以及第二本振信号检测得到第一相位差时，具体用于：第一控制电路1602对经过第一分频器分频后的第一本振信号以及经过第三控制电路中的第二分频器分频后的第二本振信号的相位差进行检测，得到第一相位差，第二分频器与第一分频器的分频率相同。
此外，第一锁相环1601可以包括：第三相位检测器，用于检测第一参考时钟信号与反馈时钟信号的相位差；环路控制器，与第三相位检测器耦合，用于根据第一参考时钟信号与反馈时钟信号的相位差产生第三控制信号；受控振荡器，与环路控制器耦合，用于根据第三控制信号产生第一本振信号；调制器，用于根据第一控制信号或第二控制信号，以及频率控制字产生分频控制字；第三分频器，与受控振荡器和调制器耦合，用于根据第一本振信号和分频控制字产生反馈时钟信号输出至第三相位检测器。
为了实现信号的跨芯片传输，相位同步装置1600还包括：第一数字接口；其中，第一数字接口与第一控制电路1602耦合，用于接收第一控制信号并输出至控制芯片；控制芯片与第一数字接口和第二射频收发机芯片中的第二数字接口耦合，用于将第一数字接口输出的第一控制信号传输至第二数字接口；第二数字接口与第二锁相环耦合。
此外，针对一颗射频收发机芯片中包含的射频通道数据较多的情况，第一射频收发机芯片还包括：第四锁相环，用于产生第四本振信号；第四控制电路，用于根据第四本振信号以及第一本振信号检测得到第五相位差，并根据第五相位差产生第四控制信号，以及利用第四控制信号对第一锁相环1601进行相位控制或对第四锁相环进行相位控制。
其中，第一锁相环可用于为第一射频收发机芯片中的一部分射频通道提供本振信号， 第四锁相环可用于为第一射频收发机芯片中的另一部分射频通道提供本振信号。
需要说明的是，图7所示的相位同步系统700可以视为采用多芯片拼接方案的射频系统，图16所示的相位同步装置1600可以视为图7所示的相位同步系统700中、用于为某个射频收发机芯片提供本振信号的装置。相位同步装置1600中未详尽描述的工作原理、实现方式及技术效果，可以参见相位同步系统700的相关描述，此处不再赘述。
实际应用中，第一射频收发机芯片还包括：多个第一传输通道，第一锁相环具体用于为多个第一传输通道提供第一本振信号；第二射频收发机芯片还包括：多个第二传输通道，第二锁相环具体用于为多个第二传输通道提供第二本振信号；多个第一传输通道和多个第二传输通道，用于支持MIMO传输。
其中，第一传输通道和第二传输通道中传输的信号可以是5G NR信号。
在另一种应用场景中，第一射频收发机芯片还包括：多个第一传输通道，第一锁相环具体用于为多个第一传输通道提供第一本振信号；第二射频收发机芯片还包括：多个第二传输通道，第二锁相环具体用于为多个第二传输通道提供第二本振信号；多个第一传输通道和多个第二传输通道，用于支持相控阵传输。
其中，第一传输通道和第二传输通道中传输的信号可以是5G NR信号。
基于同一发明构思，本申请实施例还提供一种收发装置。参见图17，该收发装置包括相位同步系统700中所述的第一射频收发机芯片和第二射频收发机芯片。
其中，第一射频收发机芯片还包括：多个第一传输通道，第一锁相环具体用于为多个第一传输通道提供第一本振信号；第二射频收发机芯片还包括：多个第二传输通道，第二锁相环具体用于为多个第二传输通道提供第二本振信号；多个第一传输通道和多个第二传输通道，用于支持MIMO传输或相控阵传输。其中，第一传输通道和第二传输通道中传输的信号可以是5G NR信号。
显然，本领域的技术人员可以对本申请实施例进行各种改动和变型而不脱离本申请实施例的范围。这样，倘若本申请实施例的这些修改和变型属于本申请权利要求及其等同技术的范围之内，则本申请也意图包含这些改动和变型在内。

Claims (30)

  1. 一种相位同步系统，其特征在于，包括第一射频收发机芯片和第二射频收发机芯片，所述第一射频收发机芯片包括第一锁相环和第一控制电路，所述第二射频收发机芯片包括第二锁相环；其中，
    所述第一锁相环，用于产生第一本振信号；
    所述第二锁相环，用于产生第二本振信号；
    所述第一控制电路，用于根据所述第一本振信号以及所述第二本振信号检测得到第一相位差，并根据所述第一相位差产生第一控制信号，以及利用所述第一控制信号对所述第一锁相环进行相位控制或对所述第二锁相环进行相位控制。
  2. 如权利要求1所述的相位同步系统，其特征在于，所述第一控制电路包括：
    第一相位检测器，用于根据所述第一本振信号以及所述第二本振信号检测得到所述第一相位差。
  3. 如权利要求1或2所述的相位同步系统，其特征在于，所述第一控制电路包括：
    第一相位控制器，用于根据所述第一相位差产生所述第一控制信号，所述第一控制信号用于控制所述第一锁相环或所述第二锁相环的分频控制字。
  4. 如权利要求3所述的相位同步系统，其特征在于，所述第一相位控制器为比例控制器、积分控制器、比例-积分控制器中的任一种。
  5. 如权利要求1～4任一项所述的相位同步系统，其特征在于，所述第一锁相环，具体用于：
    基于第一参考时钟信号产生所述第一本振信号；
    所述第二锁相环，具体用于：
    基于所述第一参考时钟信号产生所述第二本振信号。
  6. 如权利要求5所述的相位同步系统，其特征在于，所述第一锁相环具体用于：
    在所述第一控制信号的控制下，根据所述第一参考时钟信号产生所述第一本振信号。
  7. 如权利要求5所述的相位同步系统，其特征在于，所述第二锁相环具体用于：
    在所述第一控制信号的控制下，根据所述第一参考时钟信号产生所述第二本振信号。
  8. 如权利要求7所述的相位同步系统，其特征在于，还包括：第三射频收发机芯片，所述第三射频收发机芯片包括第三锁相环和第二控制电路；其中，
    所述第三锁相环，用于产生第三本振信号；
    所述第二控制电路，用于根据所述第三本振信号以及所述第一本振信号检测得到第二相位差，并根据所述第二相位差产生所述第二控制信号；
    所述第一锁相环具体用于：
    在所述第二控制信号的控制下，根据所述第一参考时钟信号产生所述第一本振信号。
  9. 如权利要求8所述的相位同步系统，其特征在于，所述第一控制电路包括：
    第一驱动器，用于接收所述第一本振信号并将驱动后的所述第一本振信号输出至所述第二控制电路。
  10. 如权利要求1～9任一项所述的相位同步系统，其特征在于，所述第一控制电路包括：
    第一缓冲器，用于缓存所述第二本振信号。
  11. 如权利要求8～10任一项所述的相位同步系统，其特征在于，所述第一控制电路包括：
    第二相位检测器，用于根据所述第三本振信号和所述第一本振信号检测得到第三相位差，
    所述第二控制电路在产生第二控制信号时，具体用于：
    根据所述第二相位差与所述第三相位差之差产生所述第二控制信号。
  12. 如权利要求11所述的相位同步系统，其特征在于，所述第二射频收发机芯片还包括：
    第三控制电路，用于根据所述第一本振信号和所述第二本振信号检测得到第四相位差；
    所述第一控制电路在产生所述第一控制信号时，具体用于：
    根据所述第一相位差与所述第四相位差之差，产生所述第一控制信号。
  13. 如权利要求12所述的相位同步系统，其特征在于，所述第一控制电路包括：
    第二驱动器，用于接收所述第一本振信号并将驱动后的所述第一本振信号输出至所述第三控制电路。
  14. 如权利要求11～13任一项所述的相位同步系统，其特征在于，所述第一控制电路还包括：
    第二缓冲器，用于缓存所述第三本振信号。
  15. 如权利要求1～14任一项所述的相位同步系统，其特征在于，所述第一控制电路在根据所述第一本振信号以及所述第二本振信号检测得到所述第一相位差时，具体用于：
    所述第一控制电路对所述第一本振信号与所述第二本振信号的相位差进行检测，得到所述第一相位差。
  16. 如权利要求12～15任一项所述的相位同步系统，其特征在于，所述第一控制电路还包括：
    第一分频器，与所述第一锁相环耦合，用于对所述第一本振信号进行分频；
    所述第三控制电路，还包括：
    第二分频器，与所述第二锁相环耦合，用于对所述第二本振信号进行分频，所述第二分频器与所述第一分频器的分频比相同；
    所述第一控制电路在根据所述第一本振信号以及所述第二本振信号检测得到所述第一相位差时，具体用于：
    所述第一控制电路对经过所述第一分频器分频后的所述第一本振信号以及经过所述第二分频器分频后的所述第二本振信号的相位差进行检测，得到所述第一相位差。
  17. 如权利要求5～16任一项所述的相位同步系统，其特征在于，所述第一锁相环包括：
    第三相位检测器，用于检测所述第一参考时钟信号与反馈时钟信号的相位差；
    环路控制器，与所述第三相位检测器耦合，用于根据所述第一参考时钟信号与所述反馈时钟信号的相位差产生第三控制信号；
    受控振荡器，与所述环路控制器耦合，用于根据所述第三控制信号产生所述第一本振信号；
    调制器，用于根据所述第一控制信号或所述第二控制信号，以及所述频率控制字产生分频控制字；
    第三分频器，与所述受控振荡器和所述调制器耦合，用于根据所述第一本振信号和所述分频控制字产生所述反馈时钟信号输出至所述第三相位检测器。
  18. 如权利要求1～17任一项所述的相位同步系统，其特征在于，所述第一射频收发机芯片还包括第一数字接口，所述第二射频收发机芯片还包括第二数字接口，所述系统还包括控制芯片；
    其中，所述第一数字接口与所述第一控制电路耦合，用于接收所述第一控制信号并输出；所述控制芯片与所述第一数字接口和所述第二数字接口耦合，用于将所述第一数字接口输出的所述第一控制信号传输至所述第二数字接口；所述第二数字接口与所述第二锁相环耦合。
  19. 如权利要求1～18任一项所述的相位同步系统，其特征在于，所述第一射频收发机芯片还包括：
    第四锁相环，用于产生第四本振信号；
    第四控制电路，用于根据所述第四本振信号以及所述第一本振信号检测得到第五相位差，并根据所述第五相位差产生第四控制信号，以及利用所述第四控制信号对所述第一锁相环进行相位控制或对所述第四锁相环进行相位控制。
  20. 如权利要求1～19任一项所述的相位同步系统，其特征在于，所述第一射频收发机芯片还包括：多个第一传输通道，所述第一锁相环具体用于为所述多个第一传输通道提供所述第一本振信号；
    所述第二射频收发机芯片还包括：多个第二传输通道，所述第二锁相环具体用于为所述多个第二传输通道提供所述第二本振信号；
    所述多个第一传输通道和所述多个第二传输通道，用于支持多入多出MIMO传输。
  21. 如权利要求1～19任一项所述的相位同步系统，其特征在于，所述第一射频收发机芯片还包括：多个第一传输通道，所述第一锁相环具体用于为所述多个第一传输通道提供所述第一本振信号；
    所述第二射频收发机芯片还包括：多个第二传输通道，所述第二锁相环具体用于为所述多个第二传输通道提供所述第二本振信号；
    所述多个第一传输通道和所述多个第二传输通道，用于支持相控阵传输。
  22. 一种相位同步装置，其特征在于，集成在第一射频收发机芯片中的第一锁相环和第一控制电路；其中，
    所述第一锁相环，用于产生第一本振信号；
    所述第一控制电路，用于根据所述第一本振信号以及由第二射频收发机芯片中的第二锁相环产生的第二本振信号检测得到第一相位差，并根据所述第一相位差产生第一控制信号，以及利用所述第一控制信号对所述第一锁相环进行相位控制或对所述第二锁相环进行相位控制。
  23. 如权利要求22所述的相位同步装置，其特征在于，所述第一锁相环，具体用于：
    基于第一参考时钟信号产生所述第一本振信号；所述第一参考时钟信号为所述第二锁相环产生所述第二本振信号时所基于的参考时钟信号。
  24. 如权利要求22或23所述的相位同步装置，其特征在于，所述第一锁相环具体用于：
    在所述第一控制信号的控制下，根据所述第一参考时钟信号产生所述第一本振信号。
  25. 如权利要求22或23所述的相位同步装置，其特征在于，所述第一锁相环具体用于：
    在第二控制信号的控制下，根据所述第一参考时钟信号产生所述第一本振信号，所述第二控制信号为第三射频收发机芯片中的第二控制电路产生的控制信号，所述第二控制电路用于根据所述第三射频收发机芯片中的第三锁相环产生的第三本振信号以及所述第一本振信号检测得到第二相位差，并根据所述第二相位差产生所述第二控制信号。
  26. 如权利要求22～25任一项所述的相位同步装置，其特征在于，所述装置还包括：第一数字接口；
    其中，所述第一数字接口与所述第一控制电路耦合，用于接收所述第一控制信号并输出至控制芯片；所述控制芯片与所述第一数字接口和所述第二射频收发机芯片中的第二数字接口耦合，用于将所述第一数字接口输出的所述第一控制信号传输至所述第二数字接口；所述第二数字接口与所述第二锁相环耦合。
  27. 如权利要求22～26任一项所述的相位同步装置，其特征在于，所述第一射频收发机芯片还包括：多个第一传输通道，所述第一锁相环具体用于为所述多个第一传输通道提 供所述第一本振信号；
    所述第二射频收发机芯片还包括：多个第二传输通道，所述第二锁相环具体用于为所述多个第二传输通道提供所述第二本振信号；
    所述多个第一传输通道和所述多个第二传输通道，用于支持MIMO传输。
  28. 如权利要求22～26任一项所述的相位同步装置，其特征在于，所述第一射频收发机芯片还包括：多个第一传输通道，所述第一锁相环具体用于为所述多个第一传输通道提供所述第一本振信号；
    所述第二射频收发机芯片还包括：多个第二传输通道，所述第二锁相环具体用于为所述多个第二传输通道提供所述第二本振信号；
    所述多个第一传输通道和所述多个第二传输通道，用于支持相控阵传输。
  29. 一种收发装置，其特征在于，包括，如权利要求1～21任一项所述的第一射频收发机芯片和第二射频收发机芯片；所述第一射频收发机芯片还包括：多个第一传输通道，所述第一射频收发机芯片中的第一锁相环具体用于为所述多个第一传输通道提供所述第一本振信号；
    所述第二射频收发机芯片还包括：多个第二传输通道，所述第二射频收发机芯片中的第二锁相环具体用于为所述多个第二传输通道提供所述第二本振信号；
    所述多个第一传输通道和所述多个第二传输通道，用于支持MIMO传输。
  30. 一种收发装置，其特征在于，包括，如权利要求1～21任一项所述的第一射频收发机芯片和第二射频收发机芯片；所述第一射频收发机芯片还包括：多个第一传输通道，所述第一射频收发机芯片中的第一锁相环具体用于为所述多个第一传输通道提供所述第一本振信号；
    所述第二射频收发机芯片还包括：多个第二传输通道，所述第二射频收发机芯片中的第二锁相环具体用于为所述多个第二传输通道提供所述第二本振信号；
    所述多个第一传输通道和所述多个第二传输通道，用于支持相控阵传输。
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