WO2023272941A1 - 一种半导体结构及其形成方法 - Google Patents

一种半导体结构及其形成方法 Download PDF

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Publication number
WO2023272941A1
WO2023272941A1 PCT/CN2021/117197 CN2021117197W WO2023272941A1 WO 2023272941 A1 WO2023272941 A1 WO 2023272941A1 CN 2021117197 W CN2021117197 W CN 2021117197W WO 2023272941 A1 WO2023272941 A1 WO 2023272941A1
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metal layer
bonding
forming
groove
conductive via
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PCT/CN2021/117197
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English (en)
French (fr)
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庄凌艺
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长鑫存储技术有限公司
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Priority to EP21947874.0A priority Critical patent/EP4325551A1/en
Priority to US17/668,785 priority patent/US20230005868A1/en
Publication of WO2023272941A1 publication Critical patent/WO2023272941A1/zh

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Definitions

  • the present application relates to, but is not limited to, a semiconductor structure and a method for forming the same.
  • Three-dimensional integrated circuits can improve packaging density, circuit operating speed and realize new multi-functional devices and circuit systems.
  • various semiconductor manufacturers are working on researching three-dimensional integrated circuits.
  • bonding between wafers is involved.
  • bonding between wafers is mainly realized through copper-copper bonding.
  • An embodiment of the present application provides a semiconductor structure, including: a first substrate, and a first bonding structure and a first conductive via formed in the first substrate;
  • the first bonding structure includes a first A metal layer and a second metal layer having a melting point lower than that of the first metal layer, the first metal layer includes a first surface and a second surface oppositely arranged, the first surface of the first metal layer has a first A groove, the second metal layer is located in the first groove; the first conductive via is in contact with the second surface of the first metal layer, and the first conductive via coincides with a projection of the first groove in a direction perpendicular to the first surface of the first metal layer.
  • the embodiment of the present application also provides a method for forming a semiconductor structure, including: providing a first substrate; forming a first bonding structure and a first conductive via in the first substrate;
  • the first bonding structure includes a first metal layer and a second metal layer having a melting point lower than that of the first metal layer, and the forming of the first bonding structure includes: forming the first metal layer, the first metal a layer comprising a first surface and a second surface oppositely disposed; a first groove is formed on the first surface of the first metal layer; and the second metal layer is formed in the first groove;
  • the first conductive via is in contact with the second surface of the first metal layer, and the first conductive via and the first groove are perpendicular to the first metal layer.
  • the projections in the direction of the first surface coincide.
  • FIG. 1 is a schematic diagram of a semiconductor structure provided in the related art
  • FIG. 2 is a schematic diagram of a semiconductor structure provided in an embodiment of the present application.
  • FIG. 3 is a schematic diagram of a gap above the second metal layer provided by the embodiment of the present application.
  • Fig. 4 is a schematic diagram of the bonding of the first bonding structure and the second bonding structure provided by the embodiment of the present application;
  • FIG. 5 is a schematic diagram of a third metal layer having a concave first surface provided by an embodiment of the present application.
  • FIG. 6 is a schematic diagram of a third metal layer having a convex first surface according to an embodiment of the present application.
  • FIG. 7 is a flowchart of a method for forming a semiconductor structure provided in an embodiment of the present application.
  • FIG. 1 is a schematic diagram of a semiconductor structure provided by the related art.
  • the semiconductor structure includes a first substrate 11, a first bonding structure 12 formed in the first substrate 11, and a first bonding structure 12 formed in the first substrate 11.
  • the material of the first bonding structure 12 is copper
  • the material of the second bonding structure 22 is also copper
  • the first bonding structure 12 and the second bonding structure 22 form a copper-copper bond combine.
  • copper-copper bonding needs to be bonded to each other at a high temperature of 400°C, and the bonding temperature is high, which limits the selection of many material processes and may cause the disadvantage of shifting component characteristics.
  • copper-copper bonding requires high surface flatness, which increases the difficulty of manufacturing.
  • An embodiment of the present application provides a semiconductor structure, including: a first substrate, and a first bonding structure and a first conductive via formed in the first substrate;
  • the first bonding structure includes a first A metal layer and a second metal layer having a melting point lower than that of the first metal layer, the first metal layer includes a first surface and a second surface oppositely arranged, the first surface of the first metal layer has a first A groove, the second metal layer is located in the first groove; the first conductive via is in contact with the second surface of the first metal layer, and the first conductive via coincides with a projection of the first groove in a direction perpendicular to the first surface of the first metal layer.
  • the first bonding structure provided by the embodiment of the present application includes a second metal layer with a lower melting point. Compared with other bonding structures including only the first metal layer, the first bonding structure provided by the embodiment of the present application can Bonding takes place at low temperature. At the same time, the projections of the first conductive via and the first groove in the direction perpendicular to the first surface of the first metal layer coincide, and during bonding, the first conductive via Thermal expansion will push the second metal layer in the first groove to fuse with other bonding structures to form an intermetallic compound, so that even if there is a small gap between the first bonding structure and the other bonding structures , the first bonding structure can also be smoothly fused with the other bonding structures, reducing the requirement on the flatness of the bonding surface during bonding.
  • FIG. 2 is a schematic diagram of a semiconductor structure provided by an embodiment of the present application.
  • the semiconductor structure includes a first substrate 11, and a first bonding structure 12 and a first bonding structure formed in the first substrate 11.
  • the first bonding structure 12 includes a first metal layer 121 and a second metal layer 122, the melting point of the second metal layer 122 is lower than that of the first metal layer 121, and the first metal layer
  • the layer 121 includes a first surface 121a and a second surface 121b oppositely disposed, the first surface 121a includes a first groove 121c, and the second metal layer 122 is located in the first groove 121c;
  • the first The conductive via 13 is in contact with the second surface 121b of the first metal layer 121, and the first conductive via 13 and the first groove 121c are perpendicular to the first metal layer 121.
  • the projections in the direction of the first surface 121a coincide.
  • the projections of the first conductive via 13 and the first groove 121c in a direction perpendicular to the first surface 121a of the first metal layer 121 coincide, that is, the first A section of the conductive via 13 parallel to the first surface 121 a and a section of the first groove 121 c parallel to the first surface 121 a have the same shape and size. In this way, the thermal expansion thrust of the first conductive via 13 on the molten second metal layer 122 during bonding can be increased, thereby improving bonding reliability.
  • the first conductive via 13 and the first groove 121c are cylindrical, and the diameter of the first groove 121c is the same as that of the first conductive via 13 .
  • the first conductive via 13 includes but not limited to a through-silicon via (TSV), and the first conductive via 13 is used for transmitting electrical signals.
  • TSV through-silicon via
  • the material of the first conductive via 13 is the same as that of the first metal layer 121 .
  • the material of the first conductive via 13 includes but not limited to copper.
  • the material of the first substrate 11 may be silicon, germanium, gallium nitride, gallium arsenide, indium phosphide (InP), silicon-on-insulator (SOI), germanium-on-insulator (GeOI), etc., but not limited thereto. It can also be other materials that can be used as the substrate.
  • the first conductive via 13 includes but not limited to a through-silicon via (TSV), and the first conductive via 13 is used for transmitting electrical signals.
  • TSV through-silicon via
  • the first metal layer 121 includes but not limited to at least one material of copper or tungsten.
  • the second metal layer 122 includes but not limited to at least one material selected from bismuth, cadmium, tin, lead, dysprosium and indium.
  • the second metal layer 122 may completely fill the first groove 121c, or may partially fill the first groove 121c. As shown in FIG. 3, in one embodiment, the thickness of the second metal layer 122 is smaller than the depth of the first groove 121c, in other words, the second metal layer 122 does not completely fill the first groove. Groove 121c. In this way, a void not filled by the second metal layer 122 is left on the top of the first groove 121c, which can prevent the expansion of the first conductive via 13 from displacing the second metal layer 122 from The first groove 121c is extruded onto the first surface 121a of the first metal layer 121 .
  • the thickness of the second metal layer is not as thick as possible, and in some specific embodiments, the thickness of the second metal layer 122 should be less than 1 ⁇ m, such as 0.8 ⁇ m.
  • the bonding surface of the first bonding structure 12 refers to the surface of the first bonding structure 12 that is bonded and connected with other bonding structures during bonding. It can be understood that the surface for bonding includes the first surface 121a of the first metal layer and the surface of the second metal layer exposed from the first groove 121c. In one embodiment, the shape of the bonding surface of the first bonding structure 12 includes but not limited to a circle, an ellipse, or a rectangle.
  • the semiconductor structure further includes a second substrate 21, and a second bonding structure 22 formed in the second substrate 21, the second bonding structure 22 is connected to the first bond
  • the bonding structure 12 is bonded and connected, as shown in FIG. 4 .
  • the bonding surface of the second bonding structure 22 refers to the surface of the second bonding structure 22 that is bonded and connected with other bonding structures during bonding.
  • the projections of the bonding surface of the second bonding structure 22 and the bonding surface of the first bonding structure 12 coincide in the vertical direction.
  • the shape and size of the bonding surface of the second bonding structure 22 are the same as the shape and size of the bonding surface of the first bonding structure 12 .
  • the shape and size of the bonding surface of the second bonding structure 22 and the shape and size of the bonding surface of the first bonding structure 12 may also be different.
  • the second bonding structure 22 includes a third metal layer 221, the material of the third metal layer 221 is the same as that of the first metal layer 121; the third metal layer 221 includes a first surface oppositely disposed 221a and a second surface 221b, the first surface 221a of the third metal layer 221 is bonded to the first bonding structure 12 .
  • the semiconductor structure further includes a second conductive via 23, the second conductive via 23 is formed in the second substrate 21, and the second conductive via 23 is connected to the The second surface 221b of the third metal layer 221 is contact-connected.
  • the second bonding structure 22 includes a fourth metal layer 222 , and the material of the fourth metal layer 222 is the same as that of the second metal layer 122 .
  • the first surface 221a of the third metal layer 221 has a second groove 221c, and the fourth metal layer 222 is located in the second groove 221c.
  • the projections of the second conductive via 23 and the second groove 221c in a direction perpendicular to the first surface 221a of the third metal layer 221 coincide.
  • the second conductive via 23 expands when heated, which pushes the fourth metal layer 222 and the first bonding structure 12 to form an intermetallic compound, thereby improving the bonding strength.
  • the first surface 221 a of the third metal layer 221 is concave, as shown in FIG. 5 .
  • the concave shape includes but not limited to a spherical concave shape.
  • the first conductive via 13 expands when heated, pushing the melted second metal layer 122 and the third metal layer 221
  • the first surface 221a is fused to form an intermetallic compound, which increases the bonding strength.
  • the second metal layer 122 in the molten state has fluidity, it will fill the space formed by the indentation, and the bonding reliability will not be affected because the bonding surface is indented.
  • the depth of the concave should not be too large; in some embodiments, the maximum depth of the concave is between 1-5 nm.
  • the first surface 221 a of the third metal layer 221 is convex, as shown in FIG. 6 .
  • the convex shape includes but not limited to a spherical convex shape.
  • the bonding surface of the first bonding structure 12 bonded to the third metal layer 221 should be indented 1-5 nm into the first substrate to accommodate the third metal layer 221 of the first surface 221a that is convex.
  • the first surface 221a of the third metal layer 221 can be smoothly bonded to the first bonding structure 12 by being concave or convex.
  • the connection reduces the flatness requirements of the bonding surface during bonding.
  • the embodiment of the present application also provides a method for forming a semiconductor structure, as shown in FIG. 7, the method includes the following steps:
  • Step 701 providing a first substrate
  • Step 702 forming a first bonding structure and a first conductive via in the first substrate;
  • the first bonding structure includes a first metal layer and a second metal layer with a melting point lower than that of the first metal layer
  • the forming the first bonding structure includes: forming the first metal layer, the first metal layer includes a first surface and a second surface opposite to each other; on the first surface of the first metal layer forming a first groove; forming the second metal layer in the first groove; the first conductive via is in contact with the second surface of the first metal layer, and the first A conductive via hole coincides with a projection of the first groove in a direction perpendicular to the first surface of the first metal layer.
  • step 701 is performed to provide a first substrate 11, as shown in FIG. 8a.
  • the material of the first substrate 11 may be silicon, germanium, gallium nitride, gallium arsenide, indium phosphide (InP), silicon-on-insulator (SOI), germanium-on-insulator (GeOI), etc., but not limited thereto. It can also be other materials that can be used as the substrate.
  • step 702 is performed to form a first bonding structure 12 and a first conductive via 13 in the first substrate 11 , as shown in FIGS. 8 b - 8 d .
  • the first bonding structure 12 includes a first metal layer 121 and a second metal layer 122 having a melting point lower than that of the first metal layer 121, and the first metal layer 121 includes a first surface 121a and a second surface oppositely disposed.
  • a first groove 121c is formed on the first surface 121a of the first metal layer 121, and the second metal layer 122 is formed in the first groove 121c; the first conductive via 13 is in contact with the second surface 121b of the first metal layer 121, and the first conductive via 13 and the first groove 121c are perpendicular to the second surface 121b of the first metal layer 121.
  • the projections in the direction of a surface 121a coincide.
  • first bonding structure 12 and the first conductive via 13 show the formation process of the first bonding structure 12 and the first conductive via 13. It should be clear that this is only an example, and other method steps can also be used to form the first bonding. structure 12 and a first conductive via 13 .
  • a first metal layer 121 is formed in the first substrate 11, the first metal layer 121 includes a first surface 121a and a second surface 121b oppositely arranged, and the first surface 121a is separated from the The first substrate 11 is exposed for subsequent bonding.
  • a first groove 121c is formed on the first surface 121a, and a second metal layer 122 is formed in the first groove 121c.
  • the first metal layer 121 and the second metal layer 122 constitute a first bonding structure 12 .
  • the surface of the second metal layer 122 exposed from the first groove 121c is flush with the first surface 121a.
  • the surface of the second metal layer 122 exposed from the first groove 121c is indented by a certain distance toward the inside of the first substrate 11 compared with the first surface 121a, in other words, the thickness of the second metal layer 122 is smaller than the depth of the first groove 121c. In this way, the first conductive via 13 can be prevented from extruding the second metal layer 122 from the first groove 121c onto the first surface 121a of the first metal layer 121 when expanding. .
  • a first conductive via 13 is formed in the first substrate 11, the first conductive via 13 is in contact with the second surface 121b, and the first conductive via 13 and the The projections of the first groove 121c in a direction perpendicular to the first surface 121a of the first metal layer 121 coincide.
  • the first conductive via 13 expands when heated, which will push the second metal layer 122 to form an intermetallic compound with other bonding structures, thereby improving the bonding strength.
  • the first conductive via 13 includes but not limited to a through silicon via (TSV).
  • the method for forming the semiconductor structure further includes providing a second substrate 21; forming a second bonding structure 22 in the second substrate 21; combining the second bonding structure 22 with the The first bonding structure 12 is bonded and connected. As shown in Figures 8e-8g.
  • a second substrate 21 is provided, and the material of the second substrate 21 may be the same as or different from that of the first substrate 11 .
  • a second bonding structure 22 is formed in the second substrate 21 .
  • forming the second bonding structure 22 includes: forming a third metal layer 221, the material of the third metal layer 221 is the same as that of the first metal layer 121, and the third metal layer
  • the layer 221 includes a first surface 221a and a second surface 221b oppositely disposed.
  • the method further includes forming a second conductive via 23 in the second substrate 21 , the second conductive via 23 is connected to the second surface of the third metal layer 221 221b contact connection.
  • forming the second bonding structure 22 further includes: forming a second groove 221c on the first surface 221a of the third metal layer 221, and forming a second groove 221c on the second groove 221c A fourth metal layer 222 is formed therein, and the material of the fourth metal layer 222 is the same as that of the second metal layer 122 .
  • the second bonding structure 22 is bonded to the first bonding structure 12 .

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Abstract

本申请实施例提供了一种半导体结构，包括：第一衬底，以及形成在所述第一衬底内的第一键合结构和第一导电通孔；所述第一键合结构包括第一金属层和熔点小于所述第一金属层的第二金属层，所述第一金属层包括相对设置的第一表面和第二表面，所述第一金属层的所述第一表面具有第一凹槽，所述第二金属层位于所述第一凹槽内；所述第一导电通孔与所述第一金属层的所述第二表面接触连接，且所述第一导电通孔和所述第一凹槽在垂直于所述第一金属层的所述第一表面的方向上的投影重合。

Description

一种半导体结构及其形成方法
相关申请的交叉引用
本申请基于申请号为202110746106.6、申请日为2021年07月01日的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本申请作为参考。
技术领域
本申请涉及但不限于一种半导体结构及其形成方法。
背景技术
三维集成电路可以提高封装密度、电路工作速度及实现新型多功能器件及电路系统，目前各半导体厂商都在致力于研究三维集成电路。
在三维集成电路中，会涉及晶圆与晶圆之间的键合，现有技术中晶圆与晶圆之间的键合主要通过铜-铜键合来实现。
然而，现有技术中的铜-铜键合容易失效，且键合性能还有待提升。
发明内容
本申请实施例提供了一种半导体结构，包括：第一衬底，以及形成在所述第一衬底内的第一键合结构和第一导电通孔；所述第一键合结构包括第一金属层和熔点小于所述第一金属层的第二金属层，所述第一金属层包括相对设置的第一表面和第二表面，所述第一金属层的所述第一表面具有第一凹槽，所述第二金属层位于所述第一凹槽内；所述第一导电通孔与所述第一金属层的所述第二表面接触连接，且所述第一导电通孔和所述第一凹槽在垂直于所述第一金属层的所述第一表面的方向上的投影重合。
本申请实施例还提供了一种半导体结构的形成方法，包括：提供第一衬底；在所述第一衬底内形成第一键合结构和第一导电通孔；
所述第一键合结构包括第一金属层和熔点小于所述第一金属层的第二金属层，所述形成第一键合结构包括：形成所述第一金属层，所述第一金属层包括相对设置的第一表面和第二表面；在所述第一金属层的所述第一表面上形成第一凹槽；在所述第一凹槽内形成所述第二金属层；
所述第一导电通孔与所述第一金属层的所述第二表面接触连接，且所述第一导电通孔和所述第一凹槽在垂直于所述第一金属层的所述第一表面的方向上的投影重合。
附图说明
图1为相关技术中提供的半导体结构的示意图；
图2为本申请实施例提供的半导体结构的示意图；
图3为本申请实施例提供的第二金属层上方具有空隙的示意图；
图4为本申请实施例提供的第一键合结构和第二键合结构键合的示意图；
图5为本申请实施例提供的第三金属层具有内凹状的第一表面的示意图；
图6为本申请实施例提供的第三金属层具有外凸状的第一表面的示意图；
图7为本申请实施例提供的半导体结构的形成方法的流程框图；
图8a-8g为本申请实施例提供的半导体结构的形成方法的工艺流程图。
具体实施方式
下面将参照附图更详细地描述本申请公开的示例性实施方式。虽然附图中显示了本申请的示例性实施方式，然而应当理解，可以以各种形式实 现本申请，而不应被这里阐述的具体实施方式所限制。相反，提供这些实施方式是为了能够更透彻地理解本申请，并且能够将本申请公开的范围完整的传达给本领域的技术人员。
在下文的描述中，给出了大量具体的细节以便提供对本申请更为彻底的理解。然而，对于本领域技术人员而言显而易见的是，本申请可以无需一个或多个这些细节而得以实施。在其他的例子中，为了避免与本申请发生混淆，对于本领域公知的一些技术特征未进行描述；即，这里不描述实际实施例的全部特征，不详细描述公知的功能和结构。
在附图中，为了清楚，层、区、元件的尺寸以及其相对尺寸可能被夸大。自始至终相同附图标记表示相同的元件。
应当明白，当元件或层被称为“在……上”、“与……相邻”、“连接到”或“耦合到”其它元件或层时，其可以直接地在其它元件或层上、与之相邻、连接或耦合到其它元件或层，或者可以存在居间的元件或层。相反，当元件被称为“直接在……上”、“与……直接相邻”、“直接连接到”或“直接耦合到”其它元件或层时，则不存在居间的元件或层。应当明白，尽管可使用术语第一、第二、第三等描述各种元件、部件、区、层和/或部分，这些元件、部件、区、层和/或部分不应当被这些术语限制。这些术语仅仅用来区分一个元件、部件、区、层或部分与另一个元件、部件、区、层或部分。因此，在不脱离本申请教导之下，下面讨论的第一元件、部件、区、层或部分可表示为第二元件、部件、区、层或部分。而当讨论的第二元件、部件、区、层或部分时，并不表明本申请必然存在第一元件、部件、区、层或部分。
空间关系术语例如“在……下”、“在……下面”、“下面的”、“在……之下”、“在……之上”、“上面的”等，在这里可为了方便描述而被使用从而描述图中所示的一个元件或特征与其它元件或特征的关系。应当明白，除了图中所示的取向以外，空间关系术语意图还包括使用和操作中的器件的不 同取向。例如，如果附图中的器件翻转，然后，描述为“在其它元件下面”或“在其之下”或“在其下”元件或特征将取向为在其它元件或特征“上”。因此，示例性术语“在……下面”和“在……下”可包括上和下两个取向。器件可以另外地取向(旋转90度或其它取向)并且在此使用的空间描述语相应地被解释。
在此使用的术语的目的仅在于描述具体实施例并且不作为本申请的限制。在此使用时，单数形式的“一”、“一个”和“所述/该”也意图包括复数形式，除非上下文清楚指出另外的方式。还应明白术语“组成”和/或“包括”，当在该说明书中使用时，确定所述特征、整数、步骤、操作、元件和/或部件的存在，但不排除一个或更多其它的特征、整数、步骤、操作、元件、部件和/或组的存在或添加。在此使用时，术语“和/或”包括相关所列项目的任何及所有组合。
图1为相关技术提供的半导体结构的示意图，如图所示，所述半导体结构包括第一衬底11，形成在所述第一衬底11内的第一键合结构12，形成在所述第一衬底11内且与所述第一键合结构12连接的第一导电通孔13，第二衬底21，形成在所述第二衬底21内的第二键合结构22，形成在所述第二衬底21内且与所述第二键合结构22连接的第二导电通孔23。其中，所述第一键合结构12的材料是铜，所述第二键合结构22的材料也是铜，所述第一键合结构12和所述第二键合结构22构成铜-铜键合。
然而，铜-铜键合需要在400℃高温条件下进行相互键合，键合温度较高，限制了许多材料工艺的选择以及可能造成元件特性偏移的缺点。此外，铜-铜键合对表面平整度要求较高，增加了工艺制作难度。
基于此，提出了本申请实施例的以下技术方案。
本申请实施例提供了一种半导体结构，包括：第一衬底，以及形成在所述第一衬底内的第一键合结构和第一导电通孔；所述第一键合结构包括 第一金属层和熔点小于所述第一金属层的第二金属层，所述第一金属层包括相对设置的第一表面和第二表面，所述第一金属层的所述第一表面具有第一凹槽，所述第二金属层位于所述第一凹槽内；所述第一导电通孔与所述第一金属层的所述第二表面接触连接，且所述第一导电通孔和所述第一凹槽在垂直于所述第一金属层的所述第一表面的方向上的投影重合。
本申请实施例提供的第一键合结构包括熔点较低的第二金属层，与仅包括第一金属层的其他键合结构相比，本申请实施例提供的第一键合结构可以在更低温度下进行键合。同时，所述第一导电通孔和所述第一凹槽在垂直于所述第一金属层的所述第一表面的方向上的投影重合，在键合时，所述第一导电通孔受热膨胀，会推动所述第一凹槽内所述第二金属层与其他键合结构融合形成金属间化合物，从而即使所述第一键合结构与所述其他键合结构之间存在微小间隙，所述第一键合结构与所述其他键合结构之间也能顺利融合，降低了键合时对键合表面的平整度要求。
为使本申请的上述目的、特征和优点能够更加明显易懂，下面结合附图对本申请的具体实施方式做详细的说明。在详述本申请实施例时，为便于说明，示意图会不依一般比例作局部放大，而且所述示意图只是示例，其在此不应限制本申请的保护范围。
图2为本申请实施例提供的半导体结构的示意图，如图所示，所述半导体结构包括第一衬底11，以及形成在所述第一衬底11内的第一键合结构12和第一导电通孔13；所述第一键合结构12包括第一金属层121和第二金属层122，所述第二金属层122的熔点小于所述第一金属层121，所述第一金属层121包括相对设置的第一表面121a和第二表面121b，所述第一表面121a包括第一凹槽121c，所述第二金属层122位于所述第一凹槽121c内；所述第一导电通孔13与所述第一金属层121的所述第二表面121b接触连接，所述第一导电通孔13和所述第一凹槽121c在垂直于所述第一金 属层121的所述第一表面121a的方向上的投影重合。
需要说明的是，所述第一导电通孔13和所述第一凹槽121c在垂直于所述第一金属层121的所述第一表面121a的方向上的投影重合，即所述第一导电通孔13与所述第一表面121a平行的截面和所述第一凹槽121c与所述第一表面121a平行的截面具有相同的形状和尺寸。如此，可以增大键合时所述第一导电通孔13对熔融态的所述第二金属层122的热膨胀推力，提高键合可靠性。
在一具体的实施例中，所述第一导电通孔13和所述第一凹槽121c呈圆柱状，所述第一凹槽121c的直径与所述第一导电通孔13的直径相同。
所述第一导电通孔13包括但不限于硅通孔(TSV)，所述第一导电通孔13用于传递电信号。
在一具体实施例中，所述第一导电通孔13的材料与所述第一金属层121的材料的相同。
在一具体实施例中，所述第一导电通孔13的材料包括但不限于铜。所述第一衬底11的材料可以是硅、锗、氮化镓、砷化镓、磷化铟(InP)，绝缘体上硅(SOI)、绝缘体上锗(GeOI)等，但不限于此，还可以是其他可以作为衬底的材料。
所述第一导电通孔13包括但不限于硅通孔(TSV)，所述第一导电通孔13用于传递电信号。
在一实施例中，所述第一金属层121包括但不限于铜或钨中的至少一种材料。
在一实施例中，所述第二金属层122包括但不限于铋、镉、锡、铅、镝、铟中的至少一种材料。
所述第二金属层122可以完全填充第一凹槽121c，也可以部分填充所述第一凹槽121c。如图3所示，在一实施例中，所述第二金属层122的厚 度小于所述第一凹槽121c的深度，换言之，所述第二金属层122并未完全填充所述第一凹槽121c。如此，在所述第一凹槽121c的顶部留下未被所述第二金属层122填充的空隙，可以防止所述第一导电通孔13在膨胀时，将所述第二金属层122从所述第一凹槽121c挤出至所述第一金属层121的所述第一表面121a上。
可以理解的是，所述第二金属层的厚度并非越厚越好，在一些具体的实施例的中，所述第二金属层122的厚度应小于1μm，如0.8μm。
需要明确的是，所述第一键合结构12的键合用表面是指所述第一键合结构12在键合时与其他键合结构键合连接的表面。可以理解的，所述键合用表面包括所述第一金属层的所述第一表面121a以及所述第二金属层从所述第一凹槽121c暴露的表面。在一实施例中，所述第一键合结构12的键合用表面的形状包括但不限于圆形、椭圆形、或矩形。
在一实施例中，所述半导体结构还包括第二衬底21，以及形成所述第二衬底21内的第二键合结构22，所述第二键合结构22与所述第一键合结构12键合连接，如图4所示。
需要明确的是，所述第二键合结构22的键合用表面是指所述第二键合结构22在键合时与其他键合结构键合连接的表面。在一实施例中，所述第二键合结构22的键合用表面和所述第一键合结构12的键合用表面在垂直方向上的投影重合。换句话说，所述第二键合结构22的键合用表面的形状和大小与所述第一键合结构12的键合用表面的形状和大小相同。但不限于此，在其他的实施例中，所述第二键合结构22的键合用表面的形状和大小和所述第一键合结构12的键合用表面的形状和大小也可以不同。
所述第二键合结构22包括第三金属层221，所述第三金属层221的材料与所述第一金属层121的材料相同；所述第三金属层221包括相对设置的第一表面221a和第二表面221b，所述第三金属层221的所述第一表面 221a与所述第一键合结构12键合连接。
在一实施例中，所述半导体结构还包括第二导电通孔23，所述第二导电通孔23形成于所述第二衬底21内，且所述第二导电通孔23与所述第三金属层221的所述第二表面221b接触连接。
在一实施例中，所述第二键合结构22包括第四金属层222，所述第四金属层222的材料与所述第二金属层122的材料相同。所述第三金属层221的所述第一表面221a具有第二凹槽221c，所述第四金属层222位于所述第二凹槽221c内。
在一具体的实施例中，所述第二导电通孔23和所述第二凹槽221c在垂直于所述第三金属层221的所述第一表面221a的方向上的投影重合。如此，在键合时，所述第二导电通孔23受热膨胀，会推动所述第四金属层222与第一键合结构12形成金属间化合物，提高键合强度。
在一实施例中，所述第三金属层221的所述第一表面221a呈内凹状，如图5所示。在一具体的实施例中，所述内凹状包括但不限于球形的内凹状。
所述第三金属层221在与所述第一键合结构12键合时，所述第一导电通孔13受热膨胀，推动熔融的所述第二金属层122与所述第三金属层221的第一表面221a融合形成金属间化合物，增加了键合强度。同时，由于熔融状态下的第二金属层122具有流动性，其会将所述内凹形成的空间填满，不会因为键合用表面呈内凹状而影响键合的可靠性。
为了保证键合的可靠性，所述内凹的深度不宜过大；在一些实施例中，所述内凹的最大深度值在1-5nm之间。
在一实施例中，所述第三金属层221的所述第一表面221a呈外凸状，如图6所示。在一具体的实施例中，所述外凸状包括但不限于球形的外凸状。
相应的，与所述第三金属层221键合连接的所述第一键合结构12的键合用表面应向所述第一衬底内部缩进1-5nm，以容纳所述第三金属层221的所述呈外凸状的所述第一表面221a。
综上可知，由于低熔点金属的化合效应以及金属的热膨胀效应，所述第三金属层221的所述第一表面221a内凹或者外凸都能顺利与所述第一键合结构12键合连接，降低了键合时对键合表面的平整度要求。
本申请实施例还提供了一种半导体结构的形成方法，如图7所示，所述方法包括以下步骤：
步骤701、提供第一衬底；
步骤702、在所述第一衬底内形成第一键合结构和第一导电通孔；所述第一键合结构包括第一金属层和熔点小于所述第一金属层的第二金属层，所述形成第一键合结构包括：形成所述第一金属层，所述第一金属层包括相对设置的第一表面和第二表面；在所述第一金属层的所述第一表面上形成第一凹槽；在所述第一凹槽内形成所述第二金属层；所述第一导电通孔与所述第一金属层的所述第二表面接触连接，且所述第一导电通孔和所述第一凹槽在垂直于所述第一金属层的所述第一表面的方向上的投影重合。
下面，结合图8a-8g对本申请实施例的半导体结构的形成方法再做进一步详细的说明。
首先，执行步骤701，提供第一衬底11，如图8a所示。
所述第一衬底11的材料可以是硅、锗、氮化镓、砷化镓、磷化铟(InP)，绝缘体上硅(SOI)、绝缘体上锗(GeOI)等，但不限于此，还可以是其他可以作为衬底的材料。
其次，执行步骤702，在所述第一衬底11内形成第一键合结构12和第一导电通孔13，如图8b-8d所示。所述第一键合结构12包括第一金属层121和熔点小于所述第一金属层121的第二金属层122，所述第一金属层121包 括相对设置的第一表面121a和第二表面121b，所述第一金属层121的所述第一表面121a上形成有第一凹槽121c，所述第二金属层122形成在所述第一凹槽121c内；所述第一导电通孔13与所述第一金属层121的所述第二表面121b接触连接，且所述第一导电通孔13和所述第一凹槽121c在垂直于所述第一金属层121的所述第一表面121a的方向上的投影重合。
图8b-8d示出了第一键合结构12及第一导电通孔13的形成过程，需要明确的是，这仅是一种示例，还可以采用其他方法步骤来形成所述第一键合结构12及第一导电通孔13。
参见图8b，在所述第一衬底11内形成第一金属层121，所述第一金属层121包括相对设置的第一表面121a和第二表面121b，所述第一表面121a从所述第一衬底11被暴露，用于后续键合。
参见图8c，在所述第一表面121a上形成第一凹槽121c，在所述第一凹槽121c内形成第二金属层122。所述第一金属层121和所述第二金属层122构成第一键合结构12。
在一实施例中，所述第二金属层122的从所述第一凹槽121c暴露的表面与所述第一表面121a齐平。
在一实施例中，所述第二金属层122的从所述第一凹槽121c暴露的表面与所述第一表面121a相比朝所述第一衬底11的内部缩进一定距离，换句话说，所述第二金属层122的厚度小于所述第一凹槽121c的深度。如此，可以防止所述第一导电通孔13在膨胀时，将所述第二金属层122从所述第一凹槽121c挤出至所述第一金属层121的所述第一表面121a上。
参见图8d，在所述第一衬底11内形成第一导电通孔13，所述第一导电通孔13与所述第二表面121b接触连接，且所述第一导电通孔13和所述第一凹槽121c在垂直于所述第一金属层121的所述第一表面121a的方向上的投影重合。如此，在键合时，所述第一导电通孔13受热膨胀，会推动所 述第二金属层122与其他键合结构形成金属间化合物，提高键合强度。具体的，所述第一导电通孔13包括但不限于硅通孔(TSV)。
在一实施例中，所述半导体结构的形成方法还包括提供第二衬底21；在所述第二衬底21内形成第二键合结构22；将所述第二键合结构22与所述第一键合结构12键合连接。如图8e-8g所示。
参见图8e，提供第二衬底21，所述第二衬底21的材料与所述第一衬底11的材料可以相同，也可以不同。
参见图8f，在所述第二衬底21内形成第二键合结构22。在一实施例中，形成所述第二键合结构22包括：形成第三金属层221，所述第三金属层221的材料与所述第一金属层121的材料相同，所述第三金属层221包括相对设置的第一表面221a和第二表面221b。
在一实施例中，所述方法还包括在所述第二衬底21内形成第二导电通孔23，所述第二导电通孔23与所述第三金属层221的所述第二表面221b接触连接。
在一实施例中，形成所述第二键合结构22，还包括：在所述第三金属层221的所述第一表面221a上形成第二凹槽221c，在所述第二凹槽221c内形成第四金属层222，所述第四金属层222的材料与所述第二金属层122的材料相同。
参见图8g，将所述第二键合结构22与所述第一键合结构12键合连接。
以上所述，仅为本申请的较佳实施例而已，并非用于限定本申请的保护范围，凡在本申请的精神和原则之内所作的任何修改、等同替换和改进等，均应包含在本申请的保护范围之内。

Claims (18)

  1. 一种半导体结构，包括：第一衬底，以及形成在所述第一衬底内的第一键合结构和第一导电通孔；
    所述第一键合结构包括第一金属层和熔点小于所述第一金属层的第二金属层，所述第一金属层包括相对设置的第一表面和第二表面，所述第一金属层的所述第一表面具有第一凹槽，所述第二金属层位于所述第一凹槽内；
    所述第一导电通孔与所述第一金属层的所述第二表面接触连接，且所述第一导电通孔和所述第一凹槽在垂直于所述第一金属层的所述第一表面的方向上的投影重合。
  2. 根据权利要求1所述的半导体结构，其中，所述第二金属层的厚度小于所述第一凹槽的深度。
  3. 根据权利要求1所述的半导体结构，其中，所述第二金属层的厚度小于1μm，所述第二金属层包括铋、镉、锡、铅、镝、铟中的至少一种材料，所述第一金属层包括铜或钨中的至少一种材料，所述第一键合结构的键合用表面的形状包括圆形、椭圆形、或矩形。
  4. 根据权利要求1所述的半导体结构，所述半导体结构还包括第二衬底，以及形成在所述第二衬底内的第二键合结构；所述第二键合结构与所述第一键合结构键合连接。
  5. 根据权利要求4所述的半导体结构，其中，所述第一键合结构的键合用表面和所述第二键合结构的键合用表面的形状和面积相同。
  6. 根据权利要求4所述的半导体结构，其中，所述第二键合结构包括与所述第一金属层材料相同第三金属层，所述第三金属层包括相对设置的第一表面和第二表面，所述第三金属层的所述第一表面与所述第一键合结构键合连接。
  7. 根据权利要求6所述的半导体结构，所述半导体结构还包括第二导电通孔，所述第二导电通孔形成于所述第二衬底内，且所述第二导电通孔与所述第三金属层的所述第二表面接触连接。
  8. 根据权利要求6所述的半导体结构，其中，所述第二键合结构包括与所述第二金属层材料相同第四金属层；所述第三金属层的所述第一表面具有第二凹槽，所述第四金属层位于所述第二凹槽内。
  9. 根据权利要求8所述的半导体结构，其中，所述第二导电通孔和所述第二凹槽在垂直于所述第三金属层的所述第一表面的方向上的投影重合。
  10. 根据权利要求6所述的半导体结构，其中，所述第三金属层的所述第一表面呈内凹状，所述内凹的最大深度值在1-5nm之间。
  11. 根据权利要求6所述的半导体结构，其中，所述第三金属层的所述第一表面呈外凸状，所述外凸的最大高度值在1-5nm之间。
  12. 根据权利要求11所述的半导体结构，其中，所述第一键合结构的键合用表面向所述第一衬底缩进1-5nm，以容纳所述第三金属层的所述呈外凸状的所述第一表面。
  13. 一种半导体结构的形成方法，包括：提供第一衬底；在所述第一衬底内形成第一键合结构和第一导电通孔；
    所述第一键合结构包括第一金属层和熔点小于所述第一金属层的第二金属层，所述形成第一键合结构包括：形成所述第一金属层，所述第一金属层包括相对设置的第一表面和第二表面；在所述第一金属层的所述第一表面上形成第一凹槽；在所述第一凹槽内形成所述第二金属层；
    所述第一导电通孔与所述第一金属层的所述第二表面接触连接，且所述第一导电通孔和所述第一凹槽在垂直于所述第一金属层的所述第一表面的方向上的投影重合。
  14. 根据权利要求13所述的半导体结构的形成方法，所述方法还包括：提供第二衬底；在所述第二衬底内形成第二键合结构；将所述第二键合结构与所述第一键合结构键合连接。
  15. 根据权利要求14所述的半导体结构的形成方法，其中，形成所述第二键合结构，包括：形成第三金属层，所述第三金属层的材料与所述第一金属层的材料相同，所述第三金属层包括相对设置的第一表面和第二表面。
  16. 根据权利要求15所述的半导体结构的形成方法，其中，将所述第二键合结构与所述第一键合结构键合连接，包括：
    将所述第三金属层的所述第一表面与所述第一键合结构的键合用表面键合连接。
  17. 根据权利要求15所述的半导体结构的形成方法，所述方法还包括：在所述第二衬底内形成第二导电通孔，所述第二导电通孔与所述第三金属层的所述第二表面接触连接。
  18. 根据权利要求15所述的半导体结构的形成方法，其中，形成所述第二键合结构，还包括：在所述第三金属层的所述第一表面上形成第二凹槽，在所述第二凹槽内形成第四金属层，所述第四金属层的材料与所述第二金属层的材料相同。
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