WO2023245712A1 - 半导体结构及其制备方法 - Google Patents

半导体结构及其制备方法 Download PDF

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WO2023245712A1
WO2023245712A1 PCT/CN2022/102632 CN2022102632W WO2023245712A1 WO 2023245712 A1 WO2023245712 A1 WO 2023245712A1 CN 2022102632 W CN2022102632 W CN 2022102632W WO 2023245712 A1 WO2023245712 A1 WO 2023245712A1
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trench
oxide layer
semiconductor structure
thickness
substrate
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PCT/CN2022/102632
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English (en)
French (fr)
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杨健
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长鑫存储技术有限公司
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    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
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    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0638—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for preventing surface leakage due to surface inversion layer, e.g. with channel stopper
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices

Definitions

  • Embodiments of the present disclosure relate to the field of semiconductor technology, and in particular, to a semiconductor structure and a preparation method thereof.
  • Dynamic random access memory is generally composed of multiple memory cells. Each memory cell usually includes a capacitor and a transistor. The gate of the transistor is electrically connected to the word line (WL), and one of the source and drain of the transistor is connected to the bit line. Line (Bit Line, BL for short) electrical connection.
  • Line Bit Line, BL for short
  • BWL Buried Word Line
  • BWL buried Word Line
  • a gate trench is usually formed on the substrate, and then a gate oxide layer and a gate electrode are formed in the gate trench.
  • the above-mentioned semiconductor structure is prone to gate-induced drain leakage current (Gate Induced Drain). Leakage (GIDL) phenomenon, as well as the defect of low transistor turn-on sensitivity, reduce the yield of semiconductor structures.
  • GIDL gate-induced drain leakage current
  • embodiments of the present disclosure provide a semiconductor structure and a preparation method thereof, which are used to reduce the gate-induced drain leakage current while also improving the turn-on sensitivity of the transistor.
  • a first aspect of embodiments of the present disclosure provides a method of manufacturing a semiconductor structure, which includes:
  • the first trench is oxidized to form a first oxide layer on the sidewall of the first trench, and a second oxide layer is formed on the bottom of the first trench.
  • the thickness of the first oxide layer Greater than the thickness of the second oxide layer; the oxidation rate of the first initial doped region is less than the oxidation rate of the substrate.
  • oxidizing the first trench includes: oxidizing the substrate on the sidewalls of the first trench to form the first oxide layer, and oxidizing a portion of the bottom of the first trench.
  • the thickness of the first initial doping region forms the second oxide layer, and the unoxidized first initial doping region forms a first doping region.
  • oxidizing the first trench includes: oxidizing the substrate on the sidewall of the first trench to form the first oxide layer, and oxidizing all of the bottom of the first trench.
  • the first initial doped region forms the second oxide layer.
  • oxidizing the first trench includes: oxidizing the substrate on the sidewall of the first trench to form the first oxide layer, and oxidizing all of the bottom of the first trench.
  • the first initial doped region and part of the substrate at the bottom of the first trench form the second oxide layer.
  • a first dielectric layer is deposited on the inner surface of the first trench
  • the first trench is oxidized, and the thickness of the second oxide layer is greater than the deposition thickness of the first dielectric layer; the oxidation rate of the first initial doped region is less than the oxidation rate of the first dielectric layer. Oxidation rate.
  • oxidizing the first trench includes: oxidizing all of the first dielectric layer and part of the substrate located on the sidewalls of the first trench to form the first oxide layer, oxidizing the first dielectric layer located on the sidewalls of the first trench. The entire first dielectric layer and part of the first initial doping region on the bottom wall of the first trench form the second oxide layer.
  • the thickness of the first dielectric layer at the sidewall of the first trench and at the bottom of the first trench are the same.
  • forming the first initial doping region at the bottom of the first trench includes:
  • III-V group elements are implanted into the bottom of the first trench.
  • the implantation energy is 1KeV-3KeV.
  • the ratio of the thickness of the first oxide layer to the thickness of the second oxide layer is (1.5-4):1.
  • oxidizing the first trench includes:
  • the first trench is oxidized using an in-situ water vapor generation process.
  • the preparation method further includes: forming a gate structure in the first trench after performing an oxidation treatment on the first trench.
  • a top surface of the gate structure is lower than a top surface of the substrate, and an insulating layer is formed on the top surface of the gate structure.
  • the preparation method further includes: forming a second doped region and a third doped region in the substrate, so The second doped region and the third doped region are located on both sides of the first trench.
  • a first initial doping region is formed at the bottom of the first trench.
  • the first initial doping region is The impurity element will prolong the reduction rate of the first initial doped region, so that the oxidation rate of the first doped region is lower than the oxidation rate of the substrate, thereby making the thickness of the first oxide layer formed greater than the thickness of the second oxide layer.
  • GIDL Gate Induced Drain Leakage
  • the second aspect of the embodiments of the present disclosure provides a semiconductor structure, which is prepared by the method for preparing the semiconductor structure provided in the first aspect, and has the beneficial effects in the above embodiments.
  • This embodiment is here No more details will be given.
  • Figure 1 is a process flow diagram of a method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure
  • Figure 2 is a schematic structural diagram of forming a first photoresist layer in a method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure
  • Figure 3 is a schematic structural diagram of forming a first trench in a method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure
  • Figure 4 is a schematic structural diagram of forming a first initial doping region in a method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure
  • Figure 5 is a schematic diagram 1 of the structure after forming the first oxide layer and the second oxide layer in the method for preparing a semiconductor structure provided by an embodiment of the present disclosure
  • Figure 6 is a schematic diagram 2 of the structure after forming the first oxide layer and the second oxide layer in the method for preparing a semiconductor structure provided by an embodiment of the present disclosure
  • Figure 7 is a schematic diagram three of the structure after forming the first oxide layer and the second oxide layer in the method for preparing a semiconductor structure provided by an embodiment of the present disclosure
  • Figure 8 is a schematic structural diagram of forming a first dielectric layer in a method for preparing a semiconductor structure provided by an embodiment of the present disclosure
  • Figure 9 is a schematic diagram 4 of the structure after forming the first oxide layer and the second oxide layer in the method for preparing a semiconductor structure provided by an embodiment of the present disclosure
  • FIG. 10 is a schematic structural diagram of forming a gate structure and an insulating layer in a method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure.
  • 10 substrate; 11: first trench; 13: second doped region; 14: third doped region; 20: first photoresist layer; 21: first shielding portion; 22: second opening; 30: First initial doping region; 40: First oxide layer; 50: Second oxide layer; 60: First doping region; 70: First dielectric layer; 80: Gate structure; 90: Insulating layer; 100 : Barrier layer.
  • semiconductor structures usually have technical problems such as gate-induced drain leakage (Gate Induced Drain Leakage, referred to as GIDL) and low transistor turn-on sensitivity.
  • GIDL gate Induced Drain Leakage
  • embodiments of the present application provide a semiconductor structure and a preparation method thereof.
  • a semiconductor structure and a preparation method thereof By forming a first initial doping region at the bottom of the first trench, when the first trench is subsequently oxidized, the first The doping elements in the initial doping region will prolong the reduction rate of the first initial doping region, so that the oxidation rate of the first doping region is less than the oxidation rate of the substrate, thereby causing the thickness of the first oxide layer to be formed to be greater than the second oxidation rate.
  • the thickness of the layer can not only reduce the Gate Induced Drain Leakage (GIDL) of the semiconductor structure, but also improve the turn-on sensitivity of the semiconductor structure, thereby improving the yield of the semiconductor structure.
  • GIDL Gate Induced Drain Leakage
  • the semiconductor structure is a dynamic random access memory (DRAM) as an example for introduction below.
  • DRAM dynamic random access memory
  • this embodiment is not limited to this.
  • the semiconductor structure in this embodiment can also be other structures. .
  • a method for preparing a semiconductor structure provided by an embodiment of the present invention includes the following steps:
  • Step S100 Provide a substrate with a first trench in the substrate.
  • the substrate 10 may be made of a semiconductor material, which may be silicon, germanium, silicon germanium, silicon carbide, silicon on insulator (SOI) or germanium on insulator (Germanium on Insulator, GOI). One or more.
  • the substrate 10 includes multiple active areas (Active Areas, AA for short), and the multiple active areas are spaced apart.
  • a shallow trench isolation (Shallow Trench Isolation, STI for short) structure can be provided between multiple active areas, and the multiple active areas are separated by the shallow trench isolation structure to ensure that each The active areas are independent of each other.
  • a shallow trench is formed in the substrate through a patterning process, and an insulating material is filled in the shallow trench, thereby defining multiple active areas separated by shallow trench isolation structures on the substrate.
  • the patterning manufacturing process can be a self-aligned double patterning (Self-Aligned Double Patterning, referred to as SADP) process or a self-aligned quadruple patterning (Self-Aligned Quadruple Patterning, referred to as SAQP) process.
  • SADP Self-Aligned Double Patterning
  • SAQP Self-Aligned Quadruple Patterning
  • the insulating material may be silicon oxide.
  • first trenches 11 there are first trenches 11 in the substrate 10.
  • the number of the first trenches 11 may be multiple. Part of the first trenches 11 is located on the shallow trench isolation structure, and part of the first trenches 11 is located on the shallow trench isolation structure.
  • the first trench 11 located on the active area may be a gate trench, and a gate electrode is formed in the first trench 11 to form a buried gate structure.
  • only one first trench 11 passes through an active area, that is, the active area is divided into two parts on the left and right by the first trench 11, and one of the two parts is the first trench 11.
  • a contact area, and the other is a second contact area.
  • the left part is the first contact area
  • the first contact area is connected to the bit line
  • the right part is the second contact area
  • the second contact area is connected to the capacitor structure.
  • an active area has two first trenches passing through it, that is, the active area is divided into three parts: left, middle and right by the trenches, and the middle part of these three parts is one.
  • Contact area the parts located on both sides are a contact area.
  • the middle part is the first contact area
  • the first contact area is connected to the bit line
  • the left and right parts are both second contact areas
  • the second contact area is connected to the capacitor.
  • the first trench 11 can be formed by the following process: forming a first photoresist layer 20 on the substrate 10 , that is, coating can be used on the top surface of the substrate 10 A first photoresist layer 20 is formed on the substrate.
  • the first photoresist layer 20 is patterned so that a plurality of first shielding portions 21 are formed on the first photoresist layer 20 at intervals, and first openings 22 are formed between adjacent first shielding portions, that is, Part of the first photoresist layer 20 is removed by exposure, development or etching, and the remaining first photoresist layer forms a plurality of first shielding portions 21 .
  • dry etching or wet etching is used to remove part of the thickness of the substrate 10 exposed in the first opening 22 to form the first trench 11 in the substrate 10 .
  • first trenches 11 when the number of first trenches 11 is multiple, the plurality of first trenches 11 are spaced apart along the first direction. For example, one or two first trenches 11 are distributed in each active area. A trench. Wherein, the first direction may intersect an extending direction of the active area.
  • FIG. 3 only shows a schematic cross-sectional view of the first trench 11 .
  • Step S200 Form a first initial doping region at the bottom of the first trench.
  • an ion diffusion process or a plasma doping system can be used to form the first initial doping region 30 at the bottom of the first trench 11 .
  • a plasma doping process may be used to inject doping elements into the bottom of the first trench 11 so that the doping elements react with the substrate 10 exposed at the bottom of the first trench 11 to form the first initial doping.
  • the doping element may be any one or more of group III-V elements, including but not limited to one or more combinations of C, N, P, B, Ge, and Ga.
  • the doping element is any one of the five group elements.
  • the doping element may be an N element, and the N element reacts with the Si element in the substrate 10 to form SIN or SION.
  • the doping elements when there are multiple types of doping elements, the doping elements may be multiple elements from the same group of III-V elements, or the doping elements may be elements from different groups of III-V elements.
  • the doping elements may be C elements and N elements, and the C elements and N elements react with the Si element in the substrate 10 to form SICN.
  • the injection energy of the plasma doping process is less than 1KeV, the thickness of the first initial doping region 30 will be too small, making it difficult to perform the subsequent oxidation treatment on the bottom of the first trench 11. Ensure the thickness relationship between the first oxide layer and the second oxide layer formed subsequently. If the injection energy of the plasma doping process is greater than 3KeV, the production cost will increase. Therefore, the injection energy of the plasma doping process in this embodiment is 1KeV-3KeV, and the thickness range of the first initial doping region 30 is controlled to be 1nm-3nm, so as to better control the subsequent formation of the first oxide layer and the third oxide layer.
  • the thickness of the dioxide layer ensures the performance of the semiconductor structure. In addition, it can also prevent the formation of the first initial doping region 30 from being too thick, thereby reducing the production cost of preparing the semiconductor structure.
  • Step S300 Perform oxidation treatment on the first trench, form a first oxide layer on the sidewall of the first trench, and form a second oxide layer on the bottom of the first trench.
  • the thickness of the first oxide layer is greater than that of the second oxide layer.
  • thickness; the oxidation rate of the first initial doped region is less than the oxidation rate of the substrate.
  • the first oxide layer 40 and the second oxide layer 50 may serve as gate oxide layers.
  • the first trench 11 is oxidized using an in-situ steam generation process (ISSG) to form a continuous first oxide layer 40 and a second oxide layer 50.
  • the first oxide layer 40 and the second oxide layer 50 has a U-shaped structure and is located on the inner surface of the first trench.
  • the first oxide layer 40 can be formed by consuming part of the thickness of the substrate 10 located on the sidewall of the first trench 11.
  • Layer 50 may be formed by consuming at least part of the thickness of first initial doped region 30 located at the bottom wall of first trench 11 .
  • the thickness of the first oxide layer 40 is D1 in FIG. 5
  • the thickness of the second oxide layer 50 is D2 in FIG. 5
  • the thickness of the first trench sidewall part of the substrate is The thickness in 10 refers to the dimension along the direction perpendicular to the side wall of the first trench 11. Taking FIG. 5 as an example, it is D1.
  • the substrate 10 is heated to a temperature high enough to catalyze the reaction between the oxygen-containing gas and the hydrogen-containing gas to form oxygen radicals, which can effectively oxidize
  • the silicon in the substrate 10 and the silicon in the first initial doping region 30 are used to form the first oxide layer 40 and the second oxide layer 50.
  • the second oxide layer 50 can make the formed first oxide layer 40 and the second oxide layer 50 have better density, thereby making the formed semiconductor structure have better electrical properties.
  • the silicon in the first initial doping region 30 needs to be reduced to free radicals, and then react with oxygen free radicals to form silicon oxide.
  • the first initial doping region 30 needs to be The doping elements in the impurity region 30 will prolong the reduction rate of the first initial doping region 30, and therefore the rate at which silicon radicals are formed is also slower. In this way, the rate at which the first initial doping region 30 is oxidized is smaller than the rate at which the substrate is oxidized. The rate of oxidation, in turn, causes the thickness of the first oxide layer 40 to be formed to be greater than the thickness of the second oxide layer 50.
  • a gate oxide layer with thick sidewalls and a thin bottom can reduce gate-induced drain leakage of the semiconductor structure.
  • Current Gate Induced Drain Leakage, GIDL for short
  • GIDL Gate Induced Drain Leakage
  • a portion of the substrate 10 on the sidewall of the first trench 11 is oxidized to form the first oxide layer 40 , and a portion of the thickness of the first initial doping region at the bottom of the first trench 11 is oxidized. 30 to form the second oxide layer 50, and the unoxidized first initial doping region 30 forms the first doping region 60.
  • the first oxide layer 40 and the second oxide layer 50 can be formed by controlling the reaction temperature and reaction time in the in-situ water vapor generation process to control the oxidized thickness of the substrate 10 and the first initial doping region 30, respectively.
  • the thickness of the second oxide layer 50 is smaller than the thickness of the first initial doped region 30 , that is, the sum of the thickness of the second oxide layer 50 and the thickness of the first doped region 60 is equal to the initial formation of the first initial doped region. 30 are equal in thickness.
  • a portion of the substrate 10 on the sidewall of the first trench 11 is oxidized to form the first oxide layer 40 , and the entire first initial doping region 30 at the bottom of the first trench 11 is oxidized.
  • a second oxide layer 50 is formed.
  • this embodiment can increase the reaction time of the in-situ water vapor generation process so that all the first initial doping region 30 located at the bottom of the first trench 11 is Oxidation, so that the thickness of the second oxide layer 50 is equal to the thickness of the first initial doping region 30. It should be noted that within the same reaction time, since the oxidation rate of the substrate 10 is greater than that of the first initial doping region 30 The oxidation rate is such that the thickness of the oxidized substrate 10 is greater than the thickness of the first initial doping region 30 , thereby causing the thickness of the first oxide layer 40 to be greater than the thickness of the second oxide layer 50 .
  • the substrate 10 on the sidewall of the first trench 11 is oxidized to form the first oxide layer 40 , and all the first initial doping regions 30 at the bottom of the first trench 11 are oxidized. A portion of the substrate 10 at the bottom of the first trench 11 forms a second oxide layer 50 , and the thickness of the first initial doped region 30 is smaller than the thickness of the second oxide layer 50 .
  • this embodiment can continue to increase the reaction time of the in-situ water vapor generation process.
  • all the first initial doping regions located at the bottom of the first trench 11 can be
  • a portion of the thickness of the substrate 10 located at the bottom of the first trench 11 is also oxidized, so that the thickness of the second oxide layer 50 is greater than the original thickness of the first initial doping region 30 .
  • the second oxide layer 50 located below the dotted line is formed by consuming the substrate 10
  • the second oxide layer 50 located above the dotted line is formed by consuming the first initial doping region 30 .
  • the thickness of the first oxide layer 40 is greater than the thickness of the second oxide layer 50 .
  • the method for preparing the semiconductor structure further includes: depositing on the inner surface of the first trench 11 A first dielectric layer 70 is formed.
  • a first dielectric layer 70 with a uniform thickness can be formed on the sidewalls and bottom walls of the first trench 11 through an atomic layer deposition (ALD) process.
  • the formed first dielectric layer 70 has Higher step coverage.
  • the thickness of the first dielectric layer 70 is 3-5 nm.
  • the reaction temperature of the atomic layer deposition process can be adjusted, for example, the reaction temperature is 600° C. to 700° C., thus ensuring the formation of the first dielectric layer 70 with high step coverage.
  • the first initial dielectric layer can be formed in the first trench 11 by chemical vapor deposition (Chemical Vapor Deposition, CVD for short) or physical vapor deposition (Physical Vapor Deposition, PVD for short), and then patterning the first dielectric layer.
  • CVD chemical Vapor Deposition
  • PVD Physical Vapor Deposition
  • An initial dielectric layer, part of the first initial dielectric layer is removed, and the first initial dielectric layer located on the sidewalls and bottom walls of the first trench 11 is retained to form the first dielectric layer 70, and the first dielectric layer 70 is formed on the first dielectric layer 70.
  • the groove 11 is surrounded by a second groove 12 .
  • the first dielectric layer 70 may include silicide, such as silicon carbide or silicon germanium. It should be noted that the oxidation rate of the first initial doped region 30 is smaller than the oxidation rate of the first dielectric layer 70 . During the subsequent oxidation process, the first dielectric layer 70 is more easily oxidized than the first initial doped region 30 to ensure the thickness relationship between the subsequently formed first oxide layer and the second oxide layer.
  • the material of the first dielectric layer 70 also includes silicon oxide, so that it is easier to form a denser first oxide layer 40 later using the ISSG process to ensure the performance of the semiconductor structure.
  • the substrate 10 in the area between adjacent first trenches 11 is used to form the source/drain regions. If the thickness of the substrate 10 consumed in the ISSG process is too large, it will result in the remaining third If the size of the substrate 10 between the trenches 11 is too small, it will increase the difficulty of preparing the source/drain regions. Based on this, in this embodiment, a third layer of uniform thickness is formed on the inner wall of the first trench 11. A dielectric layer 70 can protect the substrate 10. On the one hand, it can reduce the difficulty of preparing the source/drain regions.
  • the thickness of the finally formed first oxide layer 40 on the sidewalls and the second oxide layer on the bottom can be adjusted by controlling the thickness of the deposited first dielectric layer 70 50 thickness, thus providing sufficient adjustment time for regulating the reaction temperature and reaction time in the ISSG process, so as to better control the thickness of the subsequent formation of the first oxide layer and the second oxide layer, which can also reduce the gate induction of the semiconductor structure Gate Induced Drain Leakage (GIDL) can also improve the turn-on sensitivity of the semiconductor structure, thereby improving the yield of the semiconductor structure.
  • GIDL Gate Induced Drain Leakage
  • the inner surface of the first trench 11 is oxidized to form a first oxide layer 40 and a second oxide layer 50 .
  • the thickness of the second oxide layer 50 is greater than that of the first dielectric layer. The deposition thickness of layer 70.
  • the entire first dielectric layer 70 located on the sidewall of the first trench 11 and the substrate 10 located on part of the sidewall of the first trench 11 are oxidized to form the first oxide layer 40 , and the first oxide layer 40 is oxidized on the sidewall of the second trench 12
  • the entire first dielectric layer 70 on the bottom wall and part of the first initial doping region 30 on the bottom wall of the first trench 11 form the second oxide layer 50, where the thickness of the oxidized substrate 10 is greater than that of the oxidized substrate 10. the thickness of the first initial doped region 30 to ensure that the thickness of the finally formed first oxide layer 40 is greater than the thickness of the second oxide layer 50 .
  • the thickness of the second oxide layer 50 is equal to the initial first doping region 30 .
  • the ratio of the thickness of the first oxide layer 40 to the thickness of the second oxide layer 50 is less than 1.5:1, which will cause the thickness of the first oxide layer 40 to be too small.
  • the thickness of the first oxide layer 40 The ability to store charges will decrease, and electrons or a small amount of carrier fluid generated by the subsequent formation of the gate structure will enter the drain through the first oxide layer 40, causing a high electric field effect on the drain and increasing the gate-induced drain leakage current. If the ratio of the thickness of the first oxide layer 40 to the second oxide layer 50 is greater than 4:1, the thickness of the first oxide layer 40 is too large, and the thickness of the second oxide layer 50 will be increased accordingly, thus reducing the Sensitivity of Semiconductor Structures.
  • the ratio of the thickness of the first oxide layer 40 to the thickness of the second oxide layer 50 in this embodiment is (1.5-4):1, so that the thickness of the first oxide layer 40 and the second oxide layer 50 can be reasonably adjusted.
  • the thickness can not only reduce the Gate Induced Drain Leakage (GIDL) of the semiconductor structure, but also improve the turn-on sensitivity of the semiconductor structure, thereby improving the yield of the semiconductor structure.
  • GIDL Gate Induced Drain Leakage
  • the method of preparing a semiconductor structure further includes: after the step of oxidizing the first trench, forming a gate structure 80 in the first trench 11 , that is, in the first trench 11 .
  • a gate structure 80 is formed in the area surrounded by the oxide layer 40 and the second oxide layer 50 .
  • a deposition process may be used to deposit a conductive material in the area surrounded by the first oxide layer 40 and the second oxide layer 50 , and the conductive material fills the area surrounded by the first oxide layer 40 and the second oxide layer 50 , and then , using an etching process to remove a certain thickness of conductive material, and the retained conductive material forms the gate structure 80 , so that the top surface of the gate structure 80 is lower than the top surface of the substrate 10 .
  • the conductive material may include tungsten or polysilicon.
  • the gate structure 80 may have a single-layer structure or may include a double-layer structure, which is not specifically limited in this embodiment.
  • a deposition process is used to form an insulating layer 90 on the top surface of the gate structure.
  • a chemical vapor deposition process or a physical vapor deposition process may be used to form an insulating layer 90 on the top surface of the gate structure 80 , and the insulating layer 90 may be used to implement subsequent formation of an insulating layer between other semiconductor devices (eg, capacitor structures) on the substrate. Insulation settings.
  • the material of the insulating layer 90 includes silicon nitride, but is not limited thereto.
  • the preparation method of the semiconductor structure before forming the gate structure 80 in the area surrounded by the first oxide layer 40 and the second oxide layer 50 , the preparation method of the semiconductor structure further includes: forming the first oxide layer 40 and the second oxide layer 50 A barrier layer 100 is formed on the substrate.
  • the top surface of the barrier layer 100 is lower than the top surface of the first oxide layer 40 . That is, the top surface of the barrier layer 100 is lower than the top surface of the substrate 10 . In this way, the barrier layer 100 can be used to block subsequent formation of The conductive material in the gate structure is diffused toward the substrate to improve the performance of the semiconductor structure.
  • the barrier layer 100 is made of titanium nitride, but is not limited thereto.
  • the method of preparing the semiconductor structure further includes: forming the second doped region 13 and the third doped region 14 in the substrate 10, The second doped region 13 and the third doped region 14 are located on both sides of the first trench 11 to facilitate electrical connection between the second doped region 13 and the third doped region 14 and the capacitor structure or bit line structure formed later.
  • a second photoresist layer (not shown in the figure) having a second opening may be formed on the substrate 10, the second opening being used to expose partial areas on both sides of the first trench, and then,
  • the ion diffusion process or plasma doping process (Plasma doping) is used to inject doping ions into the exposed area to form the second doping region 13 and the third doping region 14 in the substrate 10 , wherein the second doping region 13 and the third doping region 14 are formed in the substrate 10 .
  • One of the doped region 13 and the third doped region 14 serves as the source region, and the other serves as the drain region.
  • the type of doping ions in the second doping region 13 and the third doping region 14 may be P-type ions or N-type ions.
  • Embodiments of the present disclosure also provide a semiconductor structure.
  • the semiconductor structure is produced by the preparation method of the semiconductor structure in the above embodiments. Therefore, the semiconductor structure has the beneficial effects in the above embodiments. This embodiment will not elaborate further here. Repeat.

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Abstract

本公开实施例提供一种半导体结构及其制备方法，涉及半导体技术领域，用于解决半导体结构具有较大的栅极诱导漏极泄漏电流的技术问题，该方法包括提供具有第一沟槽的衬底；在第一沟槽的底部形成第一初始掺杂区；对第一沟槽进行氧化处理，在第一沟槽的侧壁形成第一氧化层，在第一沟槽的底部形成第二氧化层，第一氧化层的厚度大于第二氧化层的厚度。本公开中第一初始掺杂区的掺杂元素会延长第一初始掺杂区的还原速率，使得第一初始掺杂区被氧化速率小于衬底被氧化速率，进而使得形成的第一氧化层的厚度大于第二氧化层的厚度，如此，既可以降低半导体结构的栅极诱导漏极泄漏电流，也可以提高半导体结构的开启灵敏度，进而提高了半导体结构的良率。

Description

半导体结构及其制备方法
本申请要求于2022年06月24日提交中国专利局、申请号为202210726492.7、申请名称为“半导体结构及其制备方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本公开实施例涉及半导体技术领域，尤其涉及一种半导体结构及其制备方法。
背景技术
动态随机存储器一般由多个存储单元组成，每个存储单元通常包括电容器和晶体管，晶体管的栅极与字线(Word Line，简称WL)电连接，晶体管的源极和漏极中之一与位线(Bit Line，简称BL)电连接。为了提高动态随机存储器的集成度，相关技术中通常采用埋入式字线(Buried Word Line，简称BWL)，即，埋入式字线形成在衬底内，并与衬底的有源区相交，使得部分埋入式字线用于晶体管的栅极。
在形成晶体管时，通常是在衬底上形成栅极沟槽，之后在栅极沟槽内形成栅氧化层和栅极，然而上述的半导体结构容易出现栅极诱导漏极泄漏电流(Gate Induced Drain Leakage，简称GIDL)现象，以及晶体管开启灵敏度低的缺陷，降低半导体结构的良率。
发明内容
鉴于上述问题，本公开实施例提供一种半导体结构及其制备方法，用于在降低栅极诱导漏极泄漏电流的同时，也提高晶体管的开启灵敏度。
根据一些实施例，本公开实施例的第一方面提供一种半导体结构的制备方法，其包括：
提供衬底，所述衬底内具有第一沟槽；
在所述第一沟槽的底部形成第一初始掺杂区；
对所述第一沟槽进行氧化处理，在所述第一沟槽的侧壁形成第一氧化层，在所述第一沟槽的底部形成第二氧化层，所述第一氧化层的厚度大于所述第二氧化层的厚度；所述第一初始掺杂区的被氧化速率小于所述衬底的被氧化速率。
在一些实施例中，对所述第一沟槽进行氧化处理包括：氧化所述第一沟槽侧壁的所述衬底形成所述第一氧化层，氧化所述第一沟槽底部的部分厚度所述第一初始掺杂区形成所述第二氧化层，未被氧化的所述第一初始掺杂区形成第一掺杂区。
在一些实施例中，对所述第一沟槽进行氧化处理包括：氧化所述第一沟槽侧壁的衬底形成所述第一氧化层，氧化所述第一沟槽底部的全部所述第一初始掺杂区形成所述第二氧化层。
在一些实施例中，对所述第一沟槽进行氧化处理包括：氧化所述第一沟槽侧壁的衬底形成所述第一氧化层，氧化所述第一沟槽底部的全部所述第一初始掺杂区及第一沟槽底部的部分衬底形成所述第二氧化层。
在一些实施例中，形成所述第一初始掺杂区之后，在所述第一沟槽内表面沉积形成第一介质层；
对所述第一沟槽进行氧化处理，所述第二氧化层厚度大于所述第一介质层的沉积厚度；所述第一初始掺杂区的被氧化速率小于所述第一介质层的被氧化速率。
在一些实施例中，对所述第一沟槽进行氧化处理包括：氧化位于所述第一沟槽侧壁上的全部第一介质层和部分衬底形成所述第一氧化层，氧化位于所述第一沟槽的底壁上的全部所述第一介质层及部分所述第一初始掺杂区形成所述第二氧化层。
在一些实施例中，所述第一沟槽侧壁和所述第一沟槽底部的第一介质层厚度相同。
在一些实施例中，在所述第一沟槽的底部形成第一初始掺杂区包括：
向所述第一沟槽底部注入III-V族元素中的任意一种或多种。
在一些实施例中，所述注入能量为1KeV-3KeV。
在一些实施例中，所述第一氧化层的厚度与所述第二氧化层的厚度之比为(1.5-4)：1。
在一些实施例中，对所述第一沟槽进行氧化处理包括：
利用原位水汽生成工艺对第一沟槽进行氧化处理。
在一些实施例中，所述制备方法还包括：对所述第一沟槽进行氧化处理后，在所述第一沟槽内形成栅极结构。
在一些实施例中，所述栅极结构的顶面低于所述衬底的顶面，且在所述栅极结构的顶面上形成绝缘层。
在一些实施例中，在所述栅极结构的顶面上形成绝缘层的步骤之后，所述制备方法还包括：在所述衬底内形成第二掺杂区和第三掺杂区，所述第二掺杂区和所述第三掺杂区位于所述第一沟槽的两侧。
本公开实施例提供的半导体结构的制备方法具有如下优点：
本公开实施例所提供的半导体结构的制备方法中，通过在第一沟槽的底部形成第一初始掺杂区，在后续对第一沟槽进行氧化处理时，第一初始掺杂区的掺杂元素会延长第一初始掺杂区的还原速率，使得第一掺杂区被氧化速率小于衬底被氧化速率，进而使得形成的第一氧化层的厚度大于第二氧化层的厚度，如此，既可以降低半导体结构的栅极诱导漏极泄漏电流(Gate Induced Drain Leakage，简称GIDL)，也可以提高半导体结构的开启灵敏度，进而提高了半导体结构的良率。
根据一些实施例，本公开实施例的第二方面提供一种半导体结构，该半导体结构通过第一方面提供的半导体结构的制备方法制得，具有上述实施例中的有益效果，本实施例在此不再多加赘述。
除了上面所描述的本公开实施例解决的技术问题、构成技术方案的技术特征以及由这些技术方案的技术特征所带来的有益效果外，本公开实施例提供的半导体结构及其制备方法所能解决的其他技术问题、技术方案中包含的其他技术特征以及这些技术特征带来的有益效果，将在具体实施方式中作出进一步详细的说明。
附图说明
为了更清楚地说明本公开实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作一简单地介绍，显而易见地，下面描述中的附图是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本公开实施例提供的半导体结构的制备方法的工艺流程图；
图2为本公开实施例提供的半导体结构的制备方法中形成第一光刻胶层的结构示意图；
图3为本公开实施例提供的半导体结构的制备方法中形成第一沟槽的结构示意图；
图4为本公开实施例提供的半导体结构的制备方法中形成第一初始掺杂区的结构示意图；
图5为本公开实施例提供的半导体结构的制备方法中形成第一氧化层和第二氧化层后的结构示意图一；
图6为本公开实施例提供的半导体结构的制备方法中形成第一氧化层和第二氧化层后的结构示意图二；
图7为本公开实施例提供的半导体结构的制备方法中形成第一氧化层和第二氧化层后的结构示意图三；
图8为本公开实施例提供的半导体结构的制备方法中形成第一介质层的结构示意图；
图9为本公开实施例提供的半导体结构的制备方法中形成第一氧化层和第二氧化层后的结构示意图四；
图10为本公开实施例提供的半导体结构的制备方法中形成栅极结构和绝缘层的结构示意图。
附图标记：
10：衬底；11：第一沟槽；13：第二掺杂区；14：第三掺杂区；20：第一光刻胶层；21：第一遮挡部；22：第二开口；30：第一初始掺杂区；40：第一氧化层；50：第二氧化层；60：第一掺杂区；70：第一介质层；80：栅极结构；90：绝缘层；100：阻挡层。
具体实施方式
正如背景技术所述，半导体结构通常具有栅极诱导漏极泄露电流(Gate Induced Drain Leakage，简称GIDL)和晶体管开启灵敏度低的技术问题，经发明人研究发现，出现这种问题的主要问题的原因是：相关技术中的制备工艺难以在沟槽的内壁上形成低台阶覆盖的氧化层，即，难以形成底部 薄侧壁厚的氧化层。
针对上述技术问题，本申请实施例提供了一种半导体结构及其制备方法，通过在第一沟槽的底部形成第一初始掺杂区，在后续对第一沟槽进行氧化处理时，第一初始掺杂区的掺杂元素会延长第一初始掺杂区的还原速率，使得第一掺杂区被氧化速率小于衬底被氧化速率，进而使得形成的第一氧化层的厚度大于第二氧化层的厚度，如此，既可以降低半导体结构的栅极诱导漏极泄漏电流(Gate Induced Drain Leakage，简称GIDL)，也可以提高半导体结构的开启灵敏度，进而提高了半导体结构的良率。
为了使本公开实施例的上述目的、特征和优点能够更加明显易懂，下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本公开的一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有作出创造性劳动的前提下所获得的所有其它实施例，均属于本公开保护的范围。
本实施例对半导体结构不作限制，下面将以半导体结构为动态随机存储器(DRAM)为例进行介绍，但本实施例并不以此为限，本实施例中的半导体结构还可以为其他的结构。
请参考图1，本发明实施例提供的一种半导体结构的制备方法，包括如下的步骤：
步骤S100：提供衬底，衬底内具有第一沟槽。
衬底10可以由半导体材料制成，半导体材料可以为硅、锗、锗化硅、碳化硅、绝缘体上硅(Silicon on Insulator，简称SOI)或绝缘体上锗(Germanium on Insulator，简称GOI)中的一种或者多种。
衬底10包括有多个有源区(Active Area，简称AA)，多个有源区间隔设置。在一些可能的实施例中，多个有源区之间可以设置浅槽隔离(Shallow Trench Isolation，简称STI)结构，通过浅沟槽隔离结构将多个有源区之间隔开来，以保证各有源区之间彼此独立。
示例性的，通过图案化制作工艺在衬底内形成浅沟槽，并在浅沟槽内填充绝缘材料，从而在衬底上定义出多个由浅沟槽隔离结构分离的有源区。其中，图案化制作工艺可以为自对准双图形(Self-Aligned Double Patterning， 简称SADP)工艺或者自对准四重图形(Self-Aligned Quadruple Patterning，简称SAQP)工艺。其中，绝缘材料可以为氧化硅。
衬底10内具有第一沟槽11，第一沟槽11的个数可以为多个，其中，部分的第一沟槽11位于浅沟槽隔离结构上，部分的第一沟槽11位于有源区上，例如，位于有源区上的第一沟槽11可以为栅极沟槽，并在第一沟槽11内形成栅极，以形成埋栅结构。
在一些可能的实现方式中，一个有源区仅有一条第一沟槽11穿过，即有源区被第一沟槽11分为左右两个部分，这两个部分中的一个为第一接触区，另一个为第二接触区，例如，左边的部分为第一接触区，第一接触区连接位线，右边的部分为第二接触区，第二接触区连接电容结构。
在另一些可能的实现方式中，一个有源区有两条第一沟槽穿过，即有源区被沟槽分为左中右三个部分，这三个部分中位于中间的部分为一个接触区，位于两边的部分为一个接触区。例如，中间的部分为第一接触区，第一接触区连接位线，左右两个部分均为第二接触区，第二接触区连接电容。如此设置，以便于后续在一个有源区内形成两个晶体管，并使该两个晶体管共用一个源极区或者漏极区，如此，可以使两个晶体管排布更优化，占用面积更小，进而，可以提高半导体结构的集成度和半导体结构的存储密度。
示例性地，请参考图2，第一沟槽11可以采用如下的过程进行：在衬底10上形成第一光刻胶层20，即，可以采用涂覆的方式在衬底10的顶面上形成第一光刻胶层20。
图形化第一光刻胶层20，以使第一光刻胶层20上形成间隔设置的多个第一遮挡部21，且相邻的第一遮挡部之间形成第一开口22，即，采用曝光、显影或者刻蚀的方式，去除部分第一光刻胶层20，被保留的第一光刻胶层形成多个第一遮挡部21。
之后，采用干法刻蚀或者湿法刻蚀，去除暴露在第一开口22内的部分厚度的衬底10，以在衬底10内形成第一沟槽11。
需要说明的是，当第一沟槽11的个数为多个时，多个第一沟槽11沿第一方向间隔设置，示例性的，每个有源区内分布有一个或者两个第一沟槽。其中，第一方向可以与有源区的延伸方向相交。图3中仅是给出了一个第一沟槽11的截面示意图。
步骤S200：在第一沟槽的底部形成第一初始掺杂区。
请参考图4，在本实施例中，可以利用离子扩散工艺或者等离子体掺杂工艺(Plasma doping system)在第一沟槽11的底部形成第一初始掺杂区30。例如，可以利用等离子体掺杂工艺向第一沟槽11的底部注入掺杂元素，使得掺杂元素与暴露在第一沟槽11的底部的衬底10发生反应，以形成第一初始掺杂区30。其中，掺杂元素可以为III-V族元素中的任意一种或者是多种，包括但不限于C、N、P、B、Ge、Ga中的一种或多种组合。
在一示例中，当掺杂元素为五族元素中的任意一个。示例性地，该掺杂元素可以为N元素，N元素与衬底10中的Si元素发生反应，以形成SIN或者SION。
在另一示例中，当掺杂元素的种类多种时，掺杂元素可以为III-V族同一族元素中的多种，又或者，掺杂元素可以为III-V族不同一族元素中的多种，示例性地，该掺杂元素可以为C元素和N元素，C元素和N元素与衬底10中的Si元素发生反应，以形成SICN。
在一些可能的实施方式中，若是等离子体掺杂工艺的注入能量小于1KeV，会致使第一初始掺杂区30的厚度过小，这样在后续第一沟槽11的底部进行氧化处理时，难以保证后续形成的第一氧化层和第二氧化层的厚度关系。若是，等离子体掺杂工艺的注入能量大于3KeV，则会造成生产成本的提高。因此，本实施例中的等离子体掺杂工艺的注入能量为1KeV-3KeV，控制第一初始掺杂区30的厚度范围为1nm-3nm，以便于更好地控制后续形成第一氧化层和第二氧化层的厚度，保证半导体结构的性能，此外，还可以防止形成第一初始掺杂区30厚度过大，降低了制备半导体结构的生产成本。
步骤S300：对第一沟槽进行氧化处理，在第一沟槽的侧壁形成第一氧化层，在第一沟槽的底部形成第二氧化层，第一氧化层的厚度大于第二氧化层的厚度；第一初始掺杂区的被氧化速率小于衬底的被氧化速率。其制备方法的过程示意图可以参考图5至图7。
第一氧化层40和第二氧化层50可以用作栅氧化层。示例性地，利用原位水汽生成工艺(In-Situ Steam Generation,ISSG)对第一沟槽11进行氧化处理，以形成连续的第一氧化层40和第二氧化层50，第一氧化层40和第二氧化层50呈U型结构并位于第一沟槽内表面，其中，第一氧化层40 可以由消耗位于第一沟槽11侧壁的部分厚度的衬底10形成的，第二氧化层50可以由消耗位于第一沟槽11底壁的至少部分厚度的第一初始掺杂区30形成。
需要说明的是，以图5所示为例，第一氧化层40的厚度为图5中D1，第二氧化层50的厚度为图5中D2，第一沟槽侧壁部分厚度的衬底10中的厚度，是指沿垂直于第一沟槽11的侧壁方向的尺寸，以图5为例，即为D1。
在原位水汽生成工艺中，对衬底10进行加热并加热到足够高的温度，该温度足以催化含氧气体和含氢气体之间的反应以形成氧自由基，氧自由基可以有效地氧化衬底10中的硅和第一初始掺杂区30中的硅，以形成第一氧化层40和第二氧化层50，如此，既可以在较短的时间内形成的第一氧化层40和第二氧化层50，且能够使所形成的第一氧化层40和第二氧化层50具有较好的致密性，进而使得所形成半导体结构具有更好的电学性能。
鉴于，在形成第二氧化层50时，需要将第一初始掺杂区30中的硅还原成自由基，然后再与氧自由基发生反应，以形成硅的氧化物，但是，第一初始掺杂区30中的掺杂元素会延长第一初始掺杂区30的还原速率，因此，形成硅自由基的速率也较慢，如此，第一初始掺杂区30被氧化的速率小于衬底被氧化的速率，进而，使得形成的第一氧化层40的厚度大于第二氧化层50的厚度，如此，形成侧壁厚底部薄的栅氧化层，既可以降低半导体结构的栅极诱导漏极泄漏电流(Gate Induced Drain Leakage，简称GIDL)，也可以提高半导体结构的开启灵敏度，进而提高了半导体结构的良率。
继续参考图5，在一种可能的实施方式中，氧化第一沟槽11侧壁的部分衬底10形成第一氧化层40，氧化第一沟槽11底部的部分厚度第一初始掺杂区30形成第二氧化层50，未被氧化的第一初始掺杂区30形成第一掺杂区60。例如，可以通过控制原位水汽生成工艺中反应温度和反应时间，以控制衬底10和第一初始掺杂区30的被氧化的厚度，分别形成第一氧化层40和第二氧化层50，使得第二氧化层50的厚度小于第一初始掺杂区30的厚度，也就是说，第二氧化层50的厚度和第一掺杂区60的厚度之和与最初形成第一初始掺杂区30的厚度相等。
请参考图6，在一种可能的实施方式中，氧化第一沟槽11侧壁的部分衬底10形成第一氧化层40，氧化第一沟槽11底部的全部第一初始掺杂区 30形成第二氧化层50。
与仅氧化部分第一初始掺杂区30的技术方案相比，本实施例可以通过增加原位水汽生成工艺的反应时间，使得位于第一沟槽11底部的第一初始掺杂区30全部被氧化，使得第二氧化层50的厚度等于最初的第一初始掺杂区30都厚度，需要说明的是，在相同的反应时间内由于衬底10的被氧化速率大于第一初始掺杂区30的被氧化速率，被氧化的衬底10的厚度大于第一初始掺杂区30厚度，进而使得第一氧化层40的厚度大于第二氧化层50的厚度。
请参考图7，在一种可能的实施方式中，氧化第一沟槽11侧壁的衬底10形成第一氧化层40，氧化第一沟槽11底部的全部第一初始掺杂区30及第一沟槽11底部的部分衬底10形成第二氧化层50，第一初始掺杂区30厚度小于第二氧化层50厚度。
与全部氧化第一初始掺杂区30的技术方案相比，本实施例可以继续增加原位水汽生成工艺的反应时间，如此，可以使位于第一沟槽11底部的全部第一初始掺杂区30被氧化的基础上，还有位于第一沟槽11底部的部分厚度的衬底10被氧化，使得第二氧化层50的厚度大于最初的第一初始掺杂区30厚度。以图7所示的方位为例，位于虚线下方的第二氧化层50是通过消耗衬底10形成的，位于虚线上方的第二氧化层50是通过消耗第一初始掺杂区30形成的。
需要说明的是，在相同的反应时间内由于衬底10的被氧化速率大于第一初始掺杂区30的被氧化速率，使得第一氧化层40的厚度大于第二氧化层50的厚度。
请参考图8，在一些实施例中，在第一沟槽11的底部形成第一初始掺杂区30的步骤之后，半导体结构的制备方法还包括：在第一沟槽11的内表面上沉积形成第一介质层70。
在一示例中，可以通过原子层沉积(Atomic Layer Deposition，简称ALD)工艺的第一沟槽11的侧壁和底壁上形成厚度均匀的第一介质层70，所形成第一介质层70具有较高的台阶覆盖率。例如，第一介质层70的厚度为3-5nm。在本示例中，可以通过调控原子层沉积工艺的反应温度，例如，反应温度为600℃-700℃，如此，可以为高台阶覆盖率的第一介质层70的形成提供保障。
在另一示例中，可以通过化学气相沉积(Chemical Vapor Deposition，简称CVD)或者物理气相沉积(Physical Vapor Deposition，简称PVD)在第一沟槽11内形成第一初始介质层，之后，图形化第一初始介质层，去除部分第一初始介质层，保留位于第一沟槽11的侧壁和底壁上的第一初始介质层，以形成第一介质层70，第一介质层70在第一沟槽11内围成第二沟槽12。
在一示例中，第一介质层70可以包括硅化物，例如碳化硅或者锗化硅，需要说明的是，第一初始掺杂区30的被氧化速率小于第一介质层70的被氧化速率，在后续的氧化处理过程中第一介质层70相较于第一初始掺杂区30更容易被氧化，以保证后续形成的第一氧化层和第二氧化层的厚度关系。
在另一示例中，第一介质层70的材质还包括氧化硅，如此在后续利用ISSG工艺更容易形成较为致密的第一氧化层40，以保证半导体结构的性能。
在位于相邻的第一沟槽11之间的区域的衬底10用于形成源极/漏极区，若是，在ISSG工艺中消耗的衬底10的厚度过大，则会导致剩余的第一沟槽11之间的衬底10的尺寸过小，会增加源极/漏极区的制备难度，基于此，在本实施例中，通过第一沟槽11的内壁上形成厚度均匀的第一介质层70，可以对衬底10进行防护，一方面可以降低源极/漏极区的制备难度，另一方面，由于对第一沟槽内表面的氧化处理是先对第一介质层进行氧化处理，在对衬底或第一初始掺杂区进行氧化处理，可以通过控制沉积的第一介质层70的厚度调控最终形成的侧壁的第一氧化层40厚度和底部的第二氧化层50厚度，从而给调控ISSG工艺中的反应温度和反应时间提供足够的调整时间，以便于更好地控制后续形成第一氧化层和第二氧化层的厚度，既可以降低半导体结构的栅极诱导漏极泄漏电流(Gate Induced Drain Leakage，简称GIDL)，也可以提高半导体结构的开启灵敏度，进而提高了半导体结构的良率。
请参考图9，待形成第一介质层70之后，对第一沟槽11内表面进行氧化处理，以形成第一氧化层40和第二氧化层50，第二氧化层50厚度大于第一介质层70的沉积厚度。
示例性地，氧化位于第一沟槽11侧壁上的全部第一介质层70和位于第一沟槽11侧壁部分厚度的衬底10形成第一氧化层40，氧化位于第二沟 槽12的底壁上的全部第一介质层70及位于第一沟槽11底壁上的部分第一初始掺杂区30形成第二氧化层50，其中，被氧化的衬底10的厚度大于被氧化的第一初始掺杂区30的厚度，以保证最终形成的第一氧化层40的厚度大于第二氧化层50的厚度。
本实施例可以通过增加原位水汽生成工艺的反应时间，使得位于第一介质层70的底部的全部第一初始掺杂区30被氧化，如此，第二氧化层50的厚度等于最初的第一初始掺杂区30的厚度和第一介质层70的厚度之和，需要说明的是，在相同的反应时间内由于衬底10的被氧化速率大于第一初始掺杂区30的被氧化速率，被氧化的衬底10的厚度大于第一初始掺杂区30厚度，进而使得第一氧化层40的厚度大于第二氧化层50的厚度。
在一些实施例中，第一氧化层40的厚度与第二氧化层50的厚度之比小于1.5:1，则会造成第一氧化层40的厚度过小，相应地，第一氧化层40的储存电荷的能力会下降，后续形成栅极结构产生的电子或者少数的载流体会通过第一氧化层40进入漏极，造成漏极形成高电场效应，增大栅极诱导漏极泄漏电流。若是，第一氧化层40与第二氧化层50的厚度之比大于4：1，则第一氧化层40的厚度过大，相应地也会增加第二氧化层50的厚度，如此，会降低半导体结构的灵敏度。
基于此，本实施例中第一氧化层40的厚度与第二氧化层50的厚度之比为(1.5-4)：1，如此可以合理地调配第一氧化层40和第二氧化层50的厚度，既可以降低半导体结构的栅极诱导漏极泄漏电流(Gate Induced Drain Leakage，简称GIDL)，也可以提高半导体结构的开启灵敏度，进而提高了半导体结构的良率。
请参考图10，在一些实施例中，半导体结构的制备方法还包括：在对第一沟槽进行氧化处理的步骤之后，在第一沟槽11内形成栅极结构80，即，在第一氧化层40和第二氧化层50围成的区域内形成栅极结构80。
示例性地，可以利用沉积工艺在第一氧化层40和第二氧化层50围成的区域内沉积导电材料，导电材料填充满第一氧化层40和第二氧化层50围成的区域，之后，利用刻蚀工艺去除一定厚度的导电材料，被保留下来的导电材料构成栅极结构80，使得栅极结构80的顶面低于衬底10的顶面。其中，导电材料可以包括钨或者多晶硅。
需要说明的是，栅极结构80可以单层结构，也可以包括双层结构，本 实施例在此不做具体的限定。
之后，再利用沉积工艺在栅极结构的顶面形成绝缘层90。例如，可以利用化学气相沉积工艺或者物理气相沉积工艺在栅极结构80的顶面形成绝缘层90，利用绝缘层90来实现后续形成在衬底上其他半导体器件(例如，电容结构)之间的绝缘设置。其中，绝缘层90的材质包括氮化硅，但不仅限于此。
在一些实施例中，在第一氧化层40和第二氧化层50围成的区域内形成栅极结构80之前，半导体结构的制备方法还包括：在第一氧化层40和第二氧化层50上形成阻挡层100，阻挡层100的顶面低于第一氧化层40的顶面，即阻挡层100的顶面低于衬底10的顶面，如此，可以利用阻挡层100来阻挡后续形成的栅极结构中的导电材料向衬底扩散，以提高半导体结构的性能。
其中，阻挡层100的材质包括氮化钛，但不仅限于此。
在一些实施例中，在栅极结构的顶面上形成绝缘层的步骤之后，半导体结构的制备方法还包括：在衬底10内形成第二掺杂区13和第三掺杂区14，第二掺杂区13和第三掺杂区14位于第一沟槽11的两侧，以便于第二掺杂区13和第三掺杂区14与后续形成电容结构或者位线结构电连接。示例性地，可以在衬底10上形成具有第二开口的第二光刻胶层(图中未示出)，该第二开口用于暴露出第一沟槽两侧的部分区域，之后，利用离子扩散工艺或者等离子体掺杂工艺(Plasma doping)向被暴露出来的区域注入掺杂离子，以在衬底10内形成第二掺杂区13和第三掺杂区14，其中，第二掺杂区13和第三掺杂区14中一个作为源极区，另一个作为漏极区。
在本实施例中，第二掺杂区13和第三掺杂区14中掺杂离子的类型可以为P型离子，也可以为N型离子。
本公开实施例还提供了一种半导体结构，该半导体结构通过上述实施例中的半导体结构的制备方法制得，因此该半导体结构具有上述实施例中的有益效果，本实施例在此不再多加赘述。
本说明书中各实施例或实施方式采用递进的方式描述，每个实施例重点说明的都是与其他实施例的不同之处，各个实施例之间相同相似部分相互参见即可。
在本说明书的描述中，参考术语“一个实施方式”、“一些实施方式”、 “示意性实施方式”、“示例”、“具体示例”、或“一些示例”等的描述意指结合实施方式或示例描述的具体特征、结构、材料或者特点包含于本公开的至少一个实施方式或示例中。
在本说明书中，对上述术语的示意性表述不一定指的是相同的实施方式或示例。而且，描述的具体特征、结构、材料或者特点可以在任何的一个或多个实施方式或示例中以合适的方式结合。
最后应说明的是：以上各实施例仅用以说明本公开的技术方案，而非对其限制；尽管参照前述各实施例对本公开进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本公开各实施例技术方案的范围。

Claims (15)

  1. 一种半导体结构的制备方法，包括如下步骤：
    提供衬底，所述衬底内具有第一沟槽；
    在所述第一沟槽的底部形成第一初始掺杂区；
    对所述第一沟槽进行氧化处理，在所述第一沟槽的侧壁形成第一氧化层，在所述第一沟槽的底部形成第二氧化层，所述第一氧化层的厚度大于所述第二氧化层的厚度；所述第一初始掺杂区的被氧化速率小于所述衬底的被氧化速率。
  2. 根据权利要求1所述的半导体结构的制备方法，其中，对所述第一沟槽进行氧化处理包括：氧化所述第一沟槽侧壁的所述衬底形成所述第一氧化层，氧化所述第一沟槽底部的部分厚度所述第一初始掺杂区形成所述第二氧化层，未被氧化的所述第一初始掺杂区形成第一掺杂区。
  3. 根据权利要求1所述的半导体结构的制备方法，其中，对所述第一沟槽进行氧化处理包括：氧化所述第一沟槽侧壁的衬底形成所述第一氧化层，氧化所述第一沟槽底部的全部所述第一初始掺杂区形成所述第二氧化层。
  4. 根据权利要求3所述的半导体结构的制备方法，其中，对所述第一沟槽进行氧化处理包括：氧化所述第一沟槽侧壁的衬底形成所述第一氧化层，氧化所述第一沟槽底部的全部所述第一初始掺杂区及第一沟槽底部的部分衬底形成所述第二氧化层。
  5. 根据权利要求1所述的半导体结构的制备方法，其中，形成所述初始第一掺杂区之后，在位于有源区的第一沟槽内表面沉积形成第一介质层；
    对所述第一沟槽内表面进行氧化处理，所述第二氧化层厚度大于所述第一介质层的沉积厚度；所述第一初始掺杂区的被氧化速率小于所述第一介质层的被氧化速率。
  6. 根据权利要求5所述的半导体结构的制备方法，其中，对所述第一沟槽进行氧化处理包括：氧化位于所述第一沟槽侧壁上的全部第一介质层和部分衬底形成所述第一氧化层，氧化位于所述第一沟槽的底壁上的全部所述第一介质层及部分所述第一初始掺杂区形成所述第二氧化层。
  7. 根据权利要求5所述的半导体结构的制备方法，其中，所述第一沟 槽侧壁和所述第一沟槽底部的第一介质层厚度相同。
  8. 根据权利要求1所述的半导体结构的制备方法，其中，在所述第一沟槽的底部形成第一初始掺杂区包括：
    向所述第一沟槽底部注入III-V族元素中的任意一种或多种。
  9. 根据权利要求8所述的半导体结构的制备方法，其中，所述注入能量为1KeV-3KeV。
  10. 根据权利要求1-9任一项所述的半导体结构的制备方法，其中，所述第一氧化层的厚度与所述第二氧化层的厚度之比为(1.5-4)：1。
  11. 根据权利要求1-9任一项所述的半导体结构的制备方法，其中，对所述第一沟槽进行氧化处理包括：
    利用原位水汽生成工艺对第一沟槽进行氧化处理。
  12. 根据权利要求1-9任一项所述的半导体结构的制备方法，其中，所述制备方法还包括：
    对所述第一沟槽进行氧化处理后，在所述第一沟槽内形成栅极结构。
  13. 根据权利要求12所述的半导体结构的制备方法，其中，
    所述栅极结构的顶面低于所述衬底的顶面，且在所述栅极结构的顶面上形成绝缘层。
  14. 根据权利要求13所述的半导体结构的制备方法，其中，在所述栅极结构的顶面上形成绝缘层的步骤之后，所述制备方法还包括：
    在所述衬底内形成第二掺杂区和第三掺杂区，所述第二掺杂区和所述第三掺杂区位于所述第一沟槽的两侧。
  15. 一种半导体结构，所述半导体结构通过权利要求1所述的半导体结构的制备方法制得。
PCT/CN2022/102632 2022-06-24 2022-06-30 半导体结构及其制备方法 WO2023245712A1 (zh)

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CN108511518A (zh) * 2018-03-09 2018-09-07 睿力集成电路有限公司 晶体管及其形成方法、半导体器件
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CN111063722A (zh) * 2018-10-17 2020-04-24 长鑫存储技术有限公司 半导体结构及其制造方法

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CN105448802A (zh) * 2014-06-09 2016-03-30 中芯国际集成电路制造(上海)有限公司 一种浅沟道隔离结构的制作方法
US10217750B1 (en) * 2017-08-31 2019-02-26 United Microelectronics Corp. Buried word line structure and method of making the same
CN108511518A (zh) * 2018-03-09 2018-09-07 睿力集成电路有限公司 晶体管及其形成方法、半导体器件
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