WO2023245610A1 - 显示基板以及显示装置 - Google Patents

显示基板以及显示装置 Download PDF

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Publication number
WO2023245610A1
WO2023245610A1 PCT/CN2022/101070 CN2022101070W WO2023245610A1 WO 2023245610 A1 WO2023245610 A1 WO 2023245610A1 CN 2022101070 W CN2022101070 W CN 2022101070W WO 2023245610 A1 WO2023245610 A1 WO 2023245610A1
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WO
WIPO (PCT)
Prior art keywords
line
area
signal line
overlapping
lines
Prior art date
Application number
PCT/CN2022/101070
Other languages
English (en)
French (fr)
Inventor
李挺
张正东
臧鹏程
张亚东
廖政
赵泽
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to PCT/CN2022/101070 priority Critical patent/WO2023245610A1/zh
Priority to CN202280001900.0A priority patent/CN117642694A/zh
Publication of WO2023245610A1 publication Critical patent/WO2023245610A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters

Definitions

  • Embodiments of the present disclosure relate to a display substrate and a display device.
  • the display area is provided with an opening or the display area is shaped like a triangle.
  • Cameras, photosensitive devices, etc. can be installed in the above opening or outside the triangle-like display area. , so as to increase the screen-to-body ratio of the display while also having a smooth and beautiful appearance.
  • the present disclosure provides a display substrate and a display device.
  • the display substrate includes a base substrate, a plurality of sub-pixels located on the base substrate, a plurality of signal lines, and a plurality of signal line connection lines.
  • the base substrate includes a first area and a second area located around the first area; a plurality of sub-pixels are located in the first area and the second area, and the sub-pixels in the first area are arranged along a first direction.
  • the number is greater than the number of sub-pixels arranged along the first direction in the second area; a plurality of signal lines are located in the first area and the second area, and at least part of each signal line is along the Extending in the first direction, each signal line is electrically connected to a row of sub-pixels arranged along the first direction; a plurality of signal line connection lines are located in the second area, and the plurality of signal line connection lines are configured to connect with The signal lines located in the second area are electrically connected, and at least part of each signal line connection line extends along the first direction.
  • the display substrate also includes a plurality of overlapping traces located in the second area. The plurality of overlapping traces are spaced apart and located on different layers from the plurality of signal line connecting lines. At least one signal line connecting line
  • the orthographic projection on the base substrate is entirely within the orthographic projection of at least one overlapping trace on the base substrate.
  • the plurality of signal lines include at least one of a plurality of gate lines and a plurality of data lines.
  • the extending direction of the overlapping traces is the same as the extending direction of the signal line connecting lines, and the line width of the overlapping traces is greater than or equal to the line width of the signal line connecting lines. Width.
  • the plurality of overlapping traces are arranged in one-to-one correspondence with the plurality of signal line connection lines, and the orthographic projection of each signal line connection line on the substrate is completely located on The corresponding overlapping traces are within the orthographic projection on the base substrate, and the distance between adjacent overlapping traces is not less than 1.5 microns.
  • the signal line connecting line and the signal line electrically connected thereto are arranged on the same layer.
  • the overlapping trace is located on a side of the signal line connection line away from the base substrate.
  • the plurality of signal lines include a plurality of gate lines
  • the display substrate further includes: a plurality of data lines located on a side of the plurality of gate lines away from the base substrate, And at least part of each data line extends along a second direction that intersects the first direction.
  • the data line and the signal line connecting line do not overlap, and the overlapping wiring and the data line are arranged on the same layer; or, the overlapping wiring is located on The data line is away from the side of the base substrate.
  • the signal line connecting line and the signal line electrically connected thereto are located on different layers.
  • the plurality of signal lines include a plurality of gate lines
  • the display substrate further includes: a plurality of data lines located on a side of the plurality of gate lines away from the base substrate, And at least part of each data line extends along a second direction that intersects the first direction.
  • the data lines and the signal line connecting lines do not overlap, and the signal line connecting lines and the data lines are arranged on the same layer.
  • the overlapping wiring and the gate line are arranged in the same layer, or the overlapping wiring is located on a side of the signal line connection line away from the base substrate.
  • the overlapping traces include first overlapping traces and second overlapping traces respectively located on both sides of the signal line connection line in a direction perpendicular to the substrate. line; in a direction perpendicular to the base substrate, the first overlapping trace and the second overlapping trace overlap, and the orthographic projection of the signal line connection line on the base substrate Located within the orthographic projection of at least one of the first overlapping trace and the second overlapping trace on the substrate.
  • the plurality of signal lines include a plurality of gate lines
  • the display substrate further includes: a plurality of data lines located on a side of the plurality of gate lines away from the base substrate, And at least part of each data line extends along a second direction that intersects the first direction.
  • the sub-pixel includes a common electrode, located on a side of the data line away from the base substrate, in a direction perpendicular to the base substrate, the data line and the signal line connection line do not overlap, so The signal line connection line and the data line are arranged on the same layer, one of the first overlapping trace and the second overlapping trace is arranged on the same layer as the gate line, and the first overlapping trace The other one of the second overlapping traces is arranged on the same layer as the common electrode.
  • the display substrate includes a display area and a non-display area
  • the second area includes a part of the display area and a part of the non-display area
  • the signal line connection line located at least partially in the non-display area
  • the signal line connection line is electrically connected to the signal line located on at least one side of the signal line connection line in the first direction, and the signal line connection line is electrically connected to the signal line connection line.
  • At least one capacitance compensation structure is provided between the signal lines, and the capacitance compensation structure is located in the non-display area.
  • the capacitance compensation structure is connected to the signal lines and the signal line connection lines located on both sides of the structure. are electrically connected, and the second direction intersects the first direction.
  • the plurality of signal lines include a plurality of gate lines
  • the display substrate further includes: a plurality of data lines located on a side of the plurality of gate lines away from the base substrate, And at least part of each data line extends along a second direction, and the second direction intersects the first direction
  • the sub-pixel includes a common electrode located on a side of the data line away from the base substrate;
  • the first region the value of the capacitance generated between the gate line electrically connected to a row of sub-pixels and the data line overlapping it and the common electrode is the first capacitance value
  • the second region Within, the capacitance generated between the gate line electrically connected to a row of sub-pixels and the data line overlapping it and the common electrode, a signal line connection line electrically connected to the gate line and the overlapping data line
  • the total capacitance value of the capacitance generated between the overlapping traces and the capacitance on the capacitance compensation structure is a second capacitance value
  • the at least one signal line connection line extends along a portion of an edge of the second area away from the first area.
  • the non-display area within the second area includes a first sub-area and a second sub-area, and the second sub-area is located between the first sub-area and the display area.
  • the signal line connection line is located in the first sub-region
  • the capacitance compensation structure is located in the second sub-region.
  • the sub-pixel includes a common electrode located on a side of the signal line away from the base substrate.
  • the display substrate further includes a common electrode line located on the base substrate, the common electrode line is configured to be electrically connected to the common electrode, and the common electrode line is electrically connected to the overlapping wiring.
  • the part of the common electrode line located in the second area is arranged on the same layer as the overlapping trace, and the part of the common electrode line is located between the overlapping trace and the overlapping trace. Between the display areas, the overlapping wiring and the part of the common electrode line are integrally provided.
  • the portion of the common electrode line located in the second area and the overlapping wiring are located on different layers, and an insulation layer is provided between them, and the overlapping wiring passes through A via hole located in the insulating layer is electrically connected to the portion of the common electrode line.
  • the display substrate further includes a connection line, the extension direction of the connection line intersects the extension direction of the overlapping wiring.
  • the connection line is configured to electrically connect the overlapping wiring and the portion of the common electrode line located in the second area; the connecting line and the overlapping wiring are arranged in the same layer.
  • the display area in the second area includes two sub-display areas arranged along the first direction, and an interval is provided between the two sub-display areas so that the third sub-display area
  • the display substrate includes a frame sealing glue area located in the non-display area, the frame sealing glue area is configured to provide frame sealing glue
  • the signal line is connected The line includes a portion located between the two sub-display areas and located in the sealant area, and the signal line connecting line is configured to connect the signal lines respectively located in the two sub-display areas, and the third The two directions intersect the first direction.
  • the at least one signal line connection line extends along at least part of an edge of the notch.
  • An embodiment of the present disclosure provides a display device, including any of the above display substrates.
  • Figure 1 is a schematic plan view of a display substrate.
  • Figure 2 is a partially enlarged schematic diagram of the A1 area shown in Figure 1.
  • Figure 3 is a partially enlarged schematic diagram of the A2 area shown in Figure 2.
  • Figure 4 is a partial enlarged schematic diagram of the A3 area shown in Figure 2.
  • FIG. 5 is an overall outline view of a display substrate according to an embodiment of the present disclosure.
  • Figure 6 is a partial enlarged view of the B1 area shown in Figure 5.
  • Figures 7 and 8 are schematic diagrams of the structure shown in Figure 6.
  • Figure 9 is a partial enlarged view of the B2 area shown in Figure 6.
  • FIG. 10 is a schematic diagram of the layer where the gate lines in the area shown in FIG. 9 are located.
  • Figure 11 is a partial enlarged view of the B3 area shown in Figure 9.
  • Figure 12 is a partial enlarged view of the B5 area shown in Figure 10.
  • FIG. 13 is a schematic diagram of the layer where the data lines in the area shown in FIG. 11 are located.
  • Figure 14 is a partial enlarged view of the B4 area shown in Figure 9.
  • Figure 15 is a partial enlarged view of the B6 area shown in Figure 10.
  • FIG. 16 is a schematic diagram of the layer where the data lines in the area shown in FIG. 14 are located.
  • FIG. 17 is a diagram showing the relationship between capacitance values on gate lines in different areas of the display substrate shown in FIG. 1 and the display substrate shown in FIG. 5 .
  • Figure 18 is a partial cross-sectional structural diagram taken along line DD' shown in Figure 14.
  • Figure 19 is a partial cross-sectional structural schematic diagram taken along line DD' shown in Figure 14 in another example according to an embodiment of the present disclosure.
  • Figure 20 is a partial enlarged view of the B7 area shown in Figure 11.
  • Figure 21 is a partial enlarged view of the B8 area shown in Figure 11.
  • FIG. 22 is a schematic diagram of a partial structure of a display substrate according to another example of an embodiment of the present disclosure.
  • Figure 23 is a partial cross-sectional structural diagram taken along line EE' shown in Figure 22.
  • FIG. 24 is a partial planar structural diagram of a display substrate according to another example of an embodiment of the present disclosure.
  • 25 to 27 are schematic diagrams of different examples of partial cross-sectional structures taken along line FF' shown in FIG. 24 .
  • FIG. 28 is a schematic plan view of a display substrate according to another embodiment of the present disclosure.
  • FIG. 29 is a partial structural diagram of the region G1 shown in FIG. 28 .
  • Figure 30 is a partial cross-sectional structural diagram taken along line HH' shown in Figure 29.
  • FIG. 31 is a partial structural diagram of region G2 shown in FIG. 28 .
  • Figure 32 is a partial cross-sectional structural diagram taken along line II' shown in Figure 31.
  • Characteristics such as “parallel”, “perpendicular” and “identical” used in the embodiments of the present disclosure include “parallel”, “perpendicular”, “identical” and other characteristics in the strict sense, as well as “approximately parallel”, “approximately perpendicular”, “Substantially the same” and the like, including certain errors, mean what is acceptable for a particular value as determined by one of ordinary skill in the art, taking into account the errors in the measurement and associated with the measurement of the particular quantity (e.g., limitations of the measurement system). within the deviation range. For example, “approximately” can mean within one or more standard deviations, or within 10% or 5% of the stated value.
  • the component can be one or more, or it can be understood as at least one.
  • At least one means one or more, and “plurality” means at least two.
  • the “same layer arrangement” referred to in this disclosure refers to two (or more than two) structures formed by the same deposition process and patterned by the same patterning process. Their materials may be the same or different.
  • the “integrated structure” in this disclosure refers to two (or more than two) structures formed through the same deposition process and patterned through the same patterning process to form connected structures. Their materials can be the same. Or different.
  • Figure 1 is a schematic plan view of a display substrate
  • Figure 2 is a partial enlarged schematic view of the A1 region shown in Figure 1
  • Figure 3 is a partial enlarged schematic view of the A2 region shown in Figure 2
  • Figure 4 is a partial enlarged schematic view of the A3 region shown in Figure 2 Enlarge the diagram.
  • the display substrate 10 includes a special-shaped display area.
  • a notch 17 is provided on one side of the special-shaped display area.
  • a plurality of sub-pixels 12 located on the base substrate are provided in the special-shaped display area.
  • the display areas located on both sides of the notch 17 in the X direction may be the first display area and the second display area respectively, and the display areas located respectively in the first display area and
  • the gate lines 14 electrically connected to the sub-pixels 12 in the second display area and distributed in the same row are electrically connected through the gate line connecting lines 11.
  • the gate line connecting lines 11 and the gate lines 14 can be wirings arranged in the same layer, such as gate lines.
  • the connection line 11 and the gate line 14 may have an integrated structure.
  • the number of sub-pixels 12 in a row provided in the first display area and the second display area on both sides of the notch 17 in the X direction is smaller than that of one side of the notch 17 in the Y direction.
  • the number of sub-pixels 12 in a row provided in the display area (such as the third display area), the gate lines 14 electrically connected to the sub-pixels 12 in the same row in the first display area and the second display area, and the gate line connection lines 11 and other conductive layers
  • the capacitance value of the capacitance generated between the conductive layer (such as the conductive layer where the data line is located and the conductive layer where the common electrode is located) is C01.
  • the capacitance value is C02.
  • the gate line connecting line 11 and the sub-pixel 12 of the first display area or the second display area can be A capacitance compensation structure 16 is provided between them, and/or a plurality of covering strips 13 extending in the Y direction are provided on the side of the partial gate line connection line 11 located in the third display area close to the notch 17 away from the base substrate.
  • the inventor of the present application found that the ratio of the capacitance value C03 to the capacitance value C02 is less than 70%, which will cause low-grayscale whitening when the pattern is displayed in the first display area.
  • Embodiments of the present disclosure provide a display substrate and a display device.
  • the display substrate includes a base substrate, a plurality of sub-pixels located on the base substrate, a plurality of signal lines, and a plurality of signal line connection lines.
  • the base substrate includes a first area and a second area located around the first area; a plurality of sub-pixels are located in the first area and the second area, and the number of sub-pixels arranged along the first direction in the first area is greater than that along the first area in the second area.
  • the sub-pixels are electrically connected; a plurality of signal line connection lines are located in the second area, the plurality of signal line connection lines are configured to be electrically connected to the signal line located in the second area, and at least part of each signal line connection line is along the first direction.
  • the display substrate also includes a plurality of overlapping traces located in the second area. The plurality of overlapping traces are spaced apart and located on different layers from the plurality of signal line connecting lines.
  • the orthographic projection of at least one signal line connecting line on the substrate substrate Located entirely within the orthographic projection of at least one overlapping trace on the substrate substrate.
  • the sealing glue (seal) can be satisfied as much as possible.
  • the overlapping area of the signal line connection line and the overlapping wiring is increased, thereby reducing the resistive-capacitive load on the signal line in the second area of the special-shaped display substrate. (RC load) to maximize compensation to avoid uneven display of low grayscale images in special-shaped display substrates.
  • FIG. 5 is an overall outline view of a display substrate according to an embodiment of the present disclosure.
  • FIG. 6 is a partial enlarged view of the B1 region shown in FIG. 5 .
  • FIGS. 7 and 8 are schematic views of the structure shown in FIG. 6 .
  • the display substrate includes a base substrate 100 and a plurality of sub-pixels 200 , a plurality of signal lines 300 and a plurality of signal line connection lines 400 located on the base substrate 100 .
  • the base substrate 100 includes a first region 101 and a second region 102 located around the first region 101 .
  • the second area 102 may be located on one side of the first area 101 in a certain direction, such as the Y direction as shown in FIG. 1 , or may surround at least part of the first area 101 .
  • multiple sub-pixels 200 are located in the first area 101 and the second area 102.
  • the number of sub-pixels 200 arranged along the first direction in the first area 101 is greater than that along the first direction in the second area 102.
  • the number of arranged sub-pixels 200 For example, the number of a row of sub-pixels 200 or a column of sub-pixels 200 arranged along the first direction in the first area 101 is greater than the number of a row of sub-pixels 200 or a column of sub-pixels 200 arranged along the first direction in the second area 102 .
  • the first direction in the embodiment of the present disclosure is the X direction shown in the figure, and the first direction may be the row direction or the column direction.
  • the first direction is the extension direction of the signal line.
  • the arrangement direction of the first area 101 and the second area 102 intersects the first direction.
  • the figure schematically shows that the first region 101 and the second region 102 are arranged along the Y direction, and the Y direction may be the second direction.
  • one of the first direction and the second direction may be a row direction, and the other may be a column direction.
  • the first direction and the second direction can be interchanged, but the extension direction of the signal line located in the display area is parallel to the first direction.
  • the size of the second area 102 in the first direction is smaller than the size of the first area 101 in the first direction.
  • the maximum size of the second area 102 in the first direction is not larger than the size of the first area 101 in the first direction. Therefore, the number of sub-pixels 200 arranged along the first direction provided in the second area 102 is smaller than the number of sub-pixels 200 arranged along the first direction provided in the first area 101 .
  • the ratio of the number of sub-pixels 200 arranged along the first direction in the second area 102 to the number of sub-pixels 200 arranged along the first direction in the first area 101 may be 0.01 ⁇ 0.9.
  • the ratio of the number of sub-pixels 200 arranged along the first direction in the second area 102 to the number of sub-pixels 200 arranged in the first area 101 arranged along the first direction may be 0.05 ⁇ 0.8.
  • the ratio of the number of sub-pixels 200 arranged along the first direction in the second area 102 to the number of sub-pixels 200 arranged in the first area 101 arranged along the first direction may be 0.07 ⁇ 0.7.
  • the ratio of the number of sub-pixels 200 arranged along the first direction in the second area 102 to the number of sub-pixels 200 arranged along the first direction in the first area 101 may be 0.1 ⁇ 0.6.
  • the ratio of the number of sub-pixels 200 arranged along the first direction in the second area 102 to the number of sub-pixels 200 arranged in the first area 101 arranged along the first direction may be 0.2 ⁇ 0.5.
  • the ratio of the number of sub-pixels 200 arranged along the first direction in the second area 102 to the number of sub-pixels 200 arranged along the first direction in the first area 101 may be 0.25 ⁇ 0.4.
  • the ratio of the number of sub-pixels 200 arranged along the first direction in the second area 102 to the number of sub-pixels 200 arranged along the first direction in the first area 101 may be 0.35 ⁇ 0.45.
  • the part of the second area 102 away from the first area 101 includes a frame, and the size of the frame is set to be narrower.
  • the ratio of the size of the second area 102 in the first direction to the size of the first area 101 in the first direction may be 0.01 ⁇ 0.9.
  • the ratio of the size of the second region 102 in the first direction to the size of the first region 101 in the first direction may be 0.04 ⁇ 0.8.
  • the ratio of the size of the second area 102 in the first direction to the size of the first area 101 in the first direction may be 0.06 ⁇ 0.7.
  • the ratio of the size of the second region 102 in the first direction to the size of the first region 101 in the first direction may be 0.1 ⁇ 0.75.
  • the ratio of the size of the second region 102 in the first direction to the size of the first region 101 in the first direction may be 0.15 ⁇ 0.6.
  • the ratio of the size of the second region 102 in the first direction to the size of the first region 101 in the first direction may be 0.25 ⁇ 0.65.
  • the ratio of the size of the second region 102 in the first direction to the size of the first region 101 in the first direction may be 0.2 ⁇ 0.55.
  • the ratio of the size of the second area 102 in the first direction to the size of the first area 101 in the first direction may be 0.25 ⁇ 0.5.
  • the ratio of the size of the second region 102 in the first direction to the size of the first region 101 in the first direction may be 0.3 ⁇ 0.45.
  • the ratio of the size of the second region 102 in the first direction to the size of the first region 101 in the first direction may be 0.35 ⁇ 0.4.
  • the sub-pixels 200 located in the first area 101 are arranged in an array along the first direction and the second direction.
  • the sub-pixels 200 located in the second area 102 are arranged in an array along the first direction and the second direction.
  • the sub-pixel 200 located in the first area 101 includes a plurality of sub-pixel rows arranged along the second direction, and the sub-pixels in each sub-pixel row 200 are arranged along the first direction, and each sub-pixel row in at least part of the first area 101 includes the same number of sub-pixels 200 .
  • each sub-pixel row in the first area 101 includes the same number of sub-pixels 200 .
  • the first direction may be the column direction
  • the second direction may be the row direction.
  • the sub-pixels located in the second area 102 include a plurality of sub-pixel rows arranged along the second direction, the sub-pixels 200 in each sub-pixel row are arranged along the first direction, and the number of sub-pixels 200 in different sub-pixel rows may be Same or different.
  • the number of subpixels in any subpixel row in the second area 102 is smaller than the number of subpixels in any subpixel row in the first area 101 .
  • 5 to 8 schematically show that the second area 102 of the display substrate includes the notch 103 , at this time, each sub-pixel row in the second area 102 includes two parts located on both sides of the notch 103 .
  • a plurality of signal lines 300 are located in the first area 101 and the second area 102 , and at least part of each signal line 300 extends along the first direction.
  • a row of sub-pixels 200 or a column of sub-pixels 200 are electrically connected.
  • the signal line 300 includes at least one of a gate line and a data line.
  • the signal line 300 may be only a gate line, only a data line, or include a gate line and a data line.
  • the embodiment shown in FIGS. 5 to 8 schematically shows that the signal line 300 is a gate line.
  • the display substrate includes a display area 104 and a non-display area 105
  • the second area 102 includes a portion of the display area 104 and a portion of the non-display area 105 .
  • the display area 104 is an area for displaying an image
  • the non-display area 105 is an area for not displaying an image.
  • the non-display area 105 may include a border.
  • the display area 104 is distributed with sub-pixels for displaying images and signal lines (including gate lines and data lines) provided between adjacent sub-pixels.
  • the embodiment of the present disclosure schematically shows that the non-display area 105 can be located on one side of the display area 104 or surround the display area 104, but it is not limited thereto, and the display area can also surround the non-display area.
  • each gate line 300 located in the display area 104 in the first region 101 extends along the first direction, and the gate lines 300 located in the first region 101 are arranged along the second direction.
  • each gate line 300 located in the display area 104 in the second area 102 extends along the first direction, and the gate lines 300 located in the second area 102 are arranged along the second direction.
  • a plurality of signal line connection lines 400 are located in the second area 102 , and the plurality of signal line connection lines 400 are configured to be electrically connected to the signal line 300 located in the second area 102 , and each signal line At least part of the connection line 500 extends along the first direction.
  • at least part of the signal line connection line 400 is located in the non-display area 105 .
  • FIGS. 5 to 8 schematically show that the signal lines are gate lines, and the signal line connection lines are gate line connection lines that are electrically connected to the gate lines. But it is not limited to this.
  • the signal line connection line is a data line connection line that is electrically connected to the data line.
  • the display area 104 in the second area 102 includes two sub-display areas 1041 and 1042 arranged along the first direction, with a gap provided between the two sub-display areas 1041 and 1042
  • the above-mentioned notch 103 is formed at an edge of the second area 102 away from the first area 104 .
  • the two sub-display areas 1041 and 1042 on both sides of the notch 103 are symmetrically distributed.
  • the sub-pixels 200 in the two sub-display areas 1041 and 1042 on both sides of the notch 103 are symmetrically distributed with respect to the center line of the display area 104 extending along the Y direction.
  • the gate lines 300 in the two sub-display areas 1041 and 1043 on both sides of the notch 103 are symmetrically distributed with respect to the above-mentioned center line.
  • at least part of the signal line connection line 400 is symmetrically distributed with respect to the above-mentioned center line.
  • the display substrate includes a frame sealant region SR located in the non-display area 105 , and the frame sealant region SR is configured to provide a frame sealant (described later).
  • the signal line connection line 400 includes a portion located between the two sub-display areas 1041 and 1042 and located in the sealant area SR, and the signal line connection line 400 is configured to connect the gate lines respectively located in the two sub-display areas 1041 and 1042 300. For example, along the direction perpendicular to the base substrate, the signal line connection lines overlap with the frame sealant provided in the frame sealant area.
  • two parts of the gate lines 300 that are electrically connected to the sub-pixels 200 located on both sides of the notch 103 and located in the same row are electrically connected through a signal line connection line 400 .
  • the number of the two portions of gate lines 300 electrically connected to the sub-pixel rows located on both sides of the notch 103 is the same, and the number of the signal line connection lines 400 is the same as the number of the gate lines 300 located on one side of the notch 103 .
  • Figures 5 to 8 schematically show that two sub-display areas are arranged along the extension direction of the gate lines, but are not limited to this.
  • the two sub-display areas can also be arranged along the extension direction of the data lines, then they are located on both sides of the notch.
  • Two parts of data lines that are electrically connected to sub-pixels located in the same column are electrically connected through a signal line connection line.
  • the display substrate also includes a plurality of overlapping traces 500 located in the second area 102 .
  • the plurality of overlapping traces 500 are spaced apart and located on different layers from the plurality of signal line connecting lines 400 .
  • the orthographic projection of the signal line connection line 400 on the base substrate 100 is completely located within the orthographic projection of an overlapping trace 500 on the base substrate 100 .
  • the signal line may be a gate line, and the orthographic projection of the gate line connection line on the substrate that is electrically connected to at least one gate line in the second area is located within the orthographic projection of at least one overlapping trace on the substrate.
  • the signal line may be a data line, and the orthographic projection of the data line connection line on the substrate that is electrically connected to at least one data line in the second area is located within the orthographic projection of at least one overlapping trace on the substrate.
  • the orthographic projection of at least one signal line connection line 400 on the base substrate 100 is completely located within the orthographic projection of at least one overlapping trace 500 on the base substrate 100 .
  • the orthographic projection of at least part of the signal line connection line 400 on the base substrate 100 is completely located within the orthographic projection of the corresponding overlapping trace 500 on the base substrate 100.
  • each overlapping trace 500 and the overlapping signal line connection line 400 extend in the same direction. Since in the display substrate provided by the present disclosure, the signal line connecting lines and the overlapping traces are overlapped, in order to clearly reflect the position of the signal line connecting lines 400 and the connection relationship with the gate lines 300, Figure 8 omits the overlapping traces. Line 500.
  • the schematic gap between the overlapping traces 500 and the gate lines 300 shown in FIG. 7 indicates that the overlapping traces 500 and the gate lines 300 are not electrically connected.
  • the display substrate provided by the present disclosure, by arranging the orthographic projection of at least one signal line connection line on the substrate to be completely located within the orthographic projection of the overlapping wiring on the substrate, it is possible to satisfy the positive requirements of the frame sealing glue as much as possible.
  • the overlapping area of the signal line connection line and the overlapping trace is increased, thereby reducing the resistance-capacitance load ( RC load) to maximize compensation to avoid uneven display of low grayscale images in special-shaped display substrates.
  • the resistance and capacitance of each signal line are directly related to the delay time when the signal line voltage changes, thereby affecting the charging time of the sub-pixel and the charging of the sub-pixel.
  • the embodiment of the present disclosure compensates the resistance and capacitance of the signal line to compensate the RC load of each signal line to be consistent with the RC load of its adjacent signal line and all other signal lines, so that the delay time of these signal lines becomes consistent. If it is consistent, it will not affect the charging time and charging of the sub-pixels, thereby avoiding the unevenness (mura) caused by this problem.
  • the orthographic projection of the signal line connecting lines on the base substrate is set to be completely located on the overlapping traces.
  • the overlapping area S of the signal line connection lines and the overlapping traces can be increased, while other parameters remain unchanged, thereby achieving RC of the signal lines in the second area of the special-shaped display substrate. Maximize load compensation to avoid uneven display of low grayscale images in special-shaped display substrates.
  • the signal line connection line 400 extends along the edge of the notch 103 .
  • the edge of the notch 103 includes a straight edge and an arcuate edge extending along the Curved part.
  • the straight portion of the signal line connecting line 400 is parallel to the first direction.
  • the arc-shaped portion of the signal line connecting line 400 is electrically connected to the signal line 300 located in the second area 102.
  • the signal line connection line 400 may further include another straight line portion whose arcuate portion is away from the notch 103 and extends along the first direction, and the straight portion is connected to the gate line 300 .
  • a connection portion may be provided between the signal line connection line 400 and the signal line 300 to connect the signal line connection line 400 and the signal line 300 .
  • the extending direction of the overlapping traces 500 is the same as the extending direction of the signal line connection lines 400 .
  • the overlapping trace 500 also includes a straight portion that overlaps with the straight portion of the signal line connection line 400 , and an arc portion that overlaps with the signal line connection line 400 .
  • the line width of the overlapping trace 500 is greater than or equal to the line width of the signal line connection line 400 .
  • the line width of the overlapping trace 500 is greater than the line width of the signal line connection line 400 .
  • the line width of the overlapping trace 500 is equal to the line width of the signal line connection line 400 .
  • the line width of the signal line connection line 400 is not less than 2 microns.
  • the line width of the signal line connection line 400 may be 3 to 6 microns.
  • the line width of the signal line connection line 400 may be 4-5.5 microns.
  • the line width of the signal line connection line 400 may be 4.5-5 microns.
  • the distance between the signal line connecting lines 400 may be 1.5-6 microns.
  • the distance between the signal line connecting lines 400 may be 1.5-6 microns.
  • the distance between the signal line connection lines 400 may be 2 to 4 microns.
  • the distance between the signal line connection lines 400 may be 3 to 5 microns.
  • the single-sided line width of the overlapping trace 500 (ie, half the line width) is 0.5 to 2.5 microns larger than the single-sided line width of the signal line connection line 400 .
  • the line width of the overlapping trace 500 is 1 to 5 microns larger than the line width of the signal line connection line 400 .
  • the line width of the overlapping trace 500 is 1.5 to 4 microns larger than the line width of the signal line connection line 400 .
  • the line width of the overlapping trace 500 is 2 to 2.5 microns larger than the line width of the signal line connection line 400 .
  • the line width of the overlapping trace 500 is 2.2 to 3 microns larger than the line width of the signal line connection line 400 .
  • the process requirements for the overlapping wiring and the signal line connecting line in the production process can be reduced, even if the overlapping wiring There is a certain relative displacement between the traces and the signal line connecting lines, and the orthographic projection of the signal line connecting lines on the substrate is still completely within the orthographic projection of the overlapping traces on the substrate.
  • multiple overlapping traces 500 are arranged in one-to-one correspondence with multiple signal line connection lines 400 , and each signal line connection line 400 is located on the front side of the substrate 100 .
  • the projection is completely located within the orthographic projection of the corresponding overlapping traces 500 on the base substrate 100 , and the distance between adjacent overlapping traces 500 is not less than 1.5 microns.
  • the spacing between adjacent overlapping traces 500 is no less than 2 microns.
  • the spacing between adjacent overlapping traces 500 is no less than 2.5 microns.
  • the spacing between adjacent overlapping traces 500 is no less than 3 microns.
  • the spacing between adjacent overlapping traces 500 is no less than 3.5 microns.
  • the spacing between adjacent overlapping traces 500 is no less than 4 microns.
  • the spacing between adjacent overlapping traces 500 is no less than 4.5 microns.
  • the spacing between adjacent overlapping traces 500 is no less than 5 microns.
  • the spacing between adjacent overlapping traces 500 is no greater than 6 microns.
  • a frame sealing glue is provided on the display side of the display substrate, and the frame sealing glue overlaps with the space between adjacent overlapping traces in a direction perpendicular to the base substrate.
  • light such as ultraviolet light
  • the spacing between adjacent overlapping traces can be shorter. Good light transmission to achieve curing of the frame sealant.
  • the overlapping traces can be made
  • the connection line with the signal line has a maximized overlapping area to perform capacitance compensation on the gate line in the second area, and at the same time, meets the light transmittance of the metal layer at the position of the display substrate facing the frame sealant.
  • the number of overlapping traces 500 is the same as the number of signal line connection lines 400 .
  • the embodiments of the present disclosure are not limited to this.
  • the number of overlapping traces can be the same as that of the signal lines.
  • the number of connecting wires is different.
  • the number of overlapping wires can be greater than the number of signal wires, or the number of overlapping wires can be smaller than the number of signal wires.
  • one overlapping trace may overlap with one signal line connection line, and one overlapping trace may also overlap with multiple signal line connection lines.
  • the signal lines include gate lines 300
  • the display substrate further includes a plurality of data lines 600 .
  • the plurality of data lines 600 are located on a side of the plurality of gate lines 300 away from the substrate substrate 100 , and at least part of each data line 600 extends along the second direction, and the second direction intersects the first direction; along the direction perpendicular to the substrate substrate 100, the data line 600 does not overlap with the signal line connection line 400, for example,
  • the data line 600 is located only in the first area 101.
  • the data line 600 includes portions located in the first area 101 and the second area 102 .
  • a plurality of data lines 600 are arranged along a first direction, and each data line 600 extends along a second direction.
  • a plurality of data lines 600 and a plurality of gate lines 300 are intersected to define a pixel area where a plurality of sub-pixels 200 arranged in an array along the first direction and the second direction are located.
  • at least part of the pixel area is located in the display area.
  • Figure 9 is a partial enlarged view of the B2 area shown in Figure 6.
  • Figure 10 is a schematic diagram of the layer where the gate lines in the area shown in Figure 9 are located.
  • Figure 11 is a partial enlarged view of the B3 area shown in Figure 9.
  • Figure 12 is a schematic diagram of the layer shown in Figure 10.
  • Figure 13 shows a partial enlarged view of the B5 area.
  • Figure 13 is a schematic diagram of the layer where the data line is located in the area shown in Figure 11.
  • Figure 14 is a partial enlarged view of the B4 area shown in Figure 9.
  • Figure 15 is a partial enlarged view of the B6 area shown in Figure 10.
  • Figure 16 is a schematic diagram of the layer where the data lines in the area shown in Figure 14 are located.
  • the signal line connection line 400 is electrically connected to the gate line 300 located on at least one side of the signal line connection line 400 in the first direction, and the signal line connection line 400 is electrically connected to the gate line 300 .
  • a block-shaped capacitance compensation structure 700 is provided between the connected gate lines 300, and the capacitance compensation structure 700 is located in the non-display area. The capacitance compensation structure 700 is electrically connected to the gate lines 300 and the signal line connection lines 400 located on both sides thereof. .
  • the number of capacitance compensation structures 700 provided between a signal line connection line 400 and the gate line 300 electrically connected thereto is at least one.
  • the number of capacitance compensation structures 700 electrically connected to different gate lines 300 may be the same or different.
  • the length of the gate line 300 gradually decreases.
  • the number of capacitance compensation structures 700 electrically connected to the gate lines 300 with a shorter length may be greater than the number of capacitance compensation structures 700 electrically connected with the gate lines 300 with a longer length to balance the RC between gate lines of different lengths. load difference.
  • the length of the signal line connection line 400 electrically connected to the shorter gate line 300 may be greater than the length of the signal line connection line 400 electrically connected to the longer length gate line 300 to balance between gate lines of different lengths. RC load difference.
  • At least one capacitance compensation structure 700 includes a two-layer structure arranged in a stack.
  • One structure is located on the same layer as the gate line 300 and is electrically connected to the gate line 300 , and the other layer can be connected to the data line.
  • 600 is located on the same layer, but is not limited to this. It can also be a conductive layer on the side of the data line away from the base substrate (such as a conductive layer on the same layer as the common electrode).
  • At least one capacitance compensation structure may also include a three-layer structure arranged in a stack, such as a layer on the same layer as the gate line and electrically connected to it, a layer on the same layer as the data line, and a layer on the same layer as the data line.
  • the lines are away from the conductive layer on the side of the base substrate.
  • At least one capacitive compensation structure 700 includes an opening to increase the light transmittance of the location where the capacitive compensation structure is located, which is beneficial to the curing of the frame sealant.
  • the non-display area within the second area 102 includes a first sub-area 1021 and a second sub-area 1022 , and the second sub-area 1022 is located between the first sub-area 1021 and the display area.
  • the signal line connection line 400 is located in the first sub-region 1021
  • the capacitance compensation structure 700 is located in the second sub-region 1022.
  • 9 and 10 schematically show the dividing line 1023 between the first sub-region 1021 and the second sub-region 1022.
  • the dividing line 1023 may be the signal line connecting line 400 in the first sub-region 1021 and the second sub-region 1022.
  • the spacing between the capacitance compensation structures 700 in the sub-region 1022 may also be a common electrode line between the signal line connection line 400 in the first sub-region 1021 and the capacitance compensation structure 700 in the second sub-region 1022.
  • the second sub-region 1022 is provided with a connection portion 401 , and the signal line connection line 400 is electrically connected to the gate line 300 through the connection portion 401 .
  • the signal line connection line 400, the connection part 401 and the gate line 300 may be an integrated structure.
  • the second sub-region 1022 is located on both sides of the notch 103 in the first direction.
  • the second sub-region 1022 is located on a side of the first sub-region 1021 away from the notch 103 .
  • the capacitance compensation structure 700 is only distributed on both sides of the notch 103 in the first direction, and there is no capacitance compensation structure 700 between the notch 103 and the first area 101 , then the second sub-region 1022 is distributed in the notch 103 On both sides of the first direction, there is no second sub-area 1022 between the notch 103 and the first area 101 .
  • the signal line connection line 400 includes two parts distributed on both sides of the notch 103 in the first direction and a part distributed between the notch 103 and the first region 101 , then the first sub-region 1021 includes a part located in the notch 102 . Two parts on both sides of 103 in the first direction and a part between the notch 103 and the first area 101 .
  • the second sub-regions 1022 located on both sides of the notch 103 are symmetrically distributed with respect to the center line of the non-display area extending along the Y direction.
  • the capacitance compensation structures 700 located on both sides of the notch 103 are symmetrically distributed with respect to the center line of the non-display area extending along the Y direction.
  • the first area 1021 is symmetrically distributed with respect to the center line extending along the Y direction of the non-display area.
  • the first sub-region 1021 includes a portion between the notch 103 and the display area of the second area 102 and a portion between the notch 103 and the display area of the first area 101 .
  • the first sub-region 1021 extends along the edge of the notch 103 .
  • the signal line connection line 400 located on one side of the notch 103 in the X direction extends along the Y direction.
  • the display substrate provided by the embodiment of the present disclosure sets the orthographic projection of the signal line connection line on the overlapping wiring line to be completely located within the overlapping wiring line, and at the same time, sets a capacitance compensation structure between the signal line connecting line and the gate line.
  • the RC load on the gate line in the second region can be jointly compensated to minimize the difference between the RC load on the gate line in the second region and the RC load on the gate line in the first region.
  • the RC load on the gate line 300 in the first region 101 is electrically connected to a row of sub-pixels 200
  • the RC load on the gate line 300 in the second region 102 is electrically connected to a row of sub-pixels 200 .
  • the RC load on the gate line 300 is a second RC load, and the ratio of the second RC load to the first RC load is 0.85 ⁇ 1.
  • the ratio of the second RC load to the first RC load is not less than 0.88.
  • the ratio of the second RC load to the first RC load is not less than 0.9.
  • the ratio of the second RC load to the first RC load is not less than 0.92.
  • the ratio of the second RC load to the first RC load is not less than 0.95.
  • the plurality of signal lines include multiple gate lines
  • the sub-pixels 200 include a common electrode (subsequent description 801) located on a side of the data line away from the base substrate; in the first area 101, electrically connected to a row of sub-pixels 200
  • the value of the capacitance generated between the connected gate line 300 and the overlapping data line 600 and the common electrode 801 is the first capacitance value C1; in the second area 102, the gate line 300 electrically connected to a row of sub-pixels 200 and its
  • the total capacitance value of the capacitors is the second capacitance value C2, and the ratio of the second capacitance value C2 to the first capacitance value C1 is 0.85-1.
  • each pixel unit may include a pixel electrode and a thin film transistor.
  • the gate line is connected to the gate electrode of the thin film transistor to control the opening or closing of the thin film transistor.
  • the pixel electrode is connected to the source and drain of the thin film transistor.
  • One of the electrodes is connected to the data line, and the data line is connected to the other of the source and drain electrodes of the thin film transistor.
  • the data line inputs the voltage signal required for displaying the picture to the pixel electrode through the thin film transistor to realize the display of the array substrate.
  • FIG. 17 is a diagram showing the relationship between capacitance values on gate lines in different areas of the display substrate shown in FIG. 1 and the display substrate shown in FIG. 5 .
  • the abscissa of line S1 to line S4 represents the number of gate lines. In the figure, 57 gate lines are taken as an example.
  • the ordinate of line S1 represents the signal line connecting line 11 and the corresponding cover strip 13 shown in Figure 2.
  • the ordinate of line S2 represents the value of the capacitance generated between the signal line connection line 400 and the overlapping trace 500 shown in FIG.
  • the ordinate of line S3 represents the capacitance value generated between the signal line connection line 11 shown in Figure 2 and the corresponding cover strip 13 and the capacitance generated using the capacitance compensation structure 16, which is shown in Figure 1.
  • the value C03 of the capacitance generated between the corresponding gate lines and other conductive layers in the first display area and the second display area on both sides of the notch after capacitance compensation is the same as the value C03 of the capacitance between the gate lines and other conductive layers in the third display area.
  • the ratio of the capacitance value C02 generated between layers is, for example, less than 70%, or less than 80%; the ordinate of line S4 represents the capacitance generated between the signal line connection line 400 and the overlapping trace 500 shown in Figure 7 and
  • the capacitance generated by the capacitance compensation structure 700 shown in Figure 11 is used to jointly perform capacitance compensation on the capacitance generated between the gate line and other conductive layers in the second region.
  • the value of the capacitance is the same as that between the gate line and other conductive layers in the first region.
  • the ratio between the resulting capacitance values is, for example, greater than 90%.
  • the capacitance on the gate line in the second region is compensated so that the ratio of the capacitance on the gate line in the second region to the capacitance on the gate line in the first region is greater than 90%, which is beneficial to reducing the RC load difference between first and second area to reduce display difference.
  • the value of the capacitance generated between each gate line 300 and other conductive layers in the first area 101 of the display substrate shown in FIGS. 5 to 16 is C1, and the capacitance values on different gate lines 300 can be equal. same.
  • the range of the third display area in the display substrate shown in FIGS. 1 to 4 may be the same as the range of the display area in the first area in the display substrate shown in FIGS. 5 to 16.
  • the value C02 of the capacitance generated between each gate line in the third display area and other conductive layers is the same as the value C02 generated between each gate line and other conductive layers in the first area of the display substrate shown in FIGS.
  • the capacitance value C1 is the same, then the value of the capacitance generated between a signal line connection line 400 and an overlapping trace 500 in the display substrate shown in Figures 5 to 16 is greater than that of a signal line connection line 500 in the display substrate shown in Figures 1 to 4 The value of the capacitance generated between the signal line connection line 11 and the corresponding cover strip 13 .
  • the capacitance generated between a signal line connecting line 400 and an overlapping trace 500 shown in Figures 5 to 16 and the capacitance generated by using the capacitance compensation structure 700 shown in Figure 11 jointly affect the third
  • the capacitance value after capacitance compensation of the capacitance generated between a corresponding gate line in the second area (a gate line electrically connected to the above-mentioned signal line connection line and the capacitance compensation structure) and other conductive layers is the same as that of each gate line in the first area.
  • the ratio of the capacitance value generated between the line and the conductive layer of other layers is not less than 90%.
  • the RC load on the gate line in the second area is different from the RC load on the gate line in the first area. More than 90% of the RC load, thereby achieving better display effects.
  • the display substrate provided by the embodiment of the present disclosure can greatly reduce the RC load on the gate line in the second area and the first The difference between the RC loads on the gate lines within the area.
  • Figure 18 is a partial cross-sectional structural diagram taken along line DD' shown in Figure 14.
  • the signal line connection line 400 and the gate line 300 electrically connected thereto are arranged in the same layer.
  • the signal line connection line 400 and the gate line 300 electrically connected thereto may be an integrated structure.
  • the signal line connection line 400 may also be called a part of the gate line 300.
  • the signal line connection line 400 and the connection portion 401 can both be called a part of the gate line 300 .
  • the capacitance compensation structure 700 may include two layers, one layer is on the same layer as the data line 600 and is spaced apart, and the other layer is on the same layer as the gate line 300 and is electrically connected.
  • two portions of connecting portions 401 are provided on both sides of the capacitance compensation structure 700 .
  • the portion of the capacitance compensation structure 700 located on the same layer as the gate line 300, the gate line 300, the signal line connection line 400 and the connection portion 401 may be an integrated structure.
  • the overlapping traces 500 are located on a side of the signal line connecting lines 400 away from the base substrate 100 .
  • the overlapping traces 500 and the data lines 600 are arranged on the same layer.
  • one layer of the capacitance compensation structure 700, the overlapping traces 500 and the data lines 600 can be arranged on the same layer.
  • the capacitance compensation structure 700 may also be provided with a film layer located on the side of the data line away from the base substrate to further compensate the RC load of the gate line in the second region.
  • an insulating layer 001 such as a gate insulating layer 001, is provided between the gate line 300 and the data line 600.
  • an insulating layer 002, such as a passivation layer 002 is provided on the side of the data line 400 away from the gate line 300.
  • the sub-pixel 200 includes a common electrode 801 located on a side of the data line 600 away from the base substrate 100 .
  • FIG. 18 schematically shows the position of the common electrode 801.
  • the common electrode 801 on the left side of position D' may have a whole-layer structure, and the common electrode 801 on the right side of position D' may have a grid-like structure.
  • the common electrode 801 does not overlap the overlapping trace 500 .
  • the display substrate further includes a common electrode line 802 located on the base substrate 100 , and the common electrode line 802 is configured to be electrically connected to the common electrode 801 .
  • the common electrode line 802 includes a portion provided in the same layer as the data line 600 .
  • the common electrode line 802 may also include a portion disposed in the same layer as the common electrode 801 .
  • the common electrode line may be a dividing line between the first sub-region 1021 and the second sub-region 1022 .
  • the common electrode line may surround the second sub-region 1022.
  • a ground wire (GND) 803 is also provided on the side of the first sub-region 1021 away from the display area.
  • the common electrode line can also surround the area formed by the first sub-region 1021 and the second sub-region 1022.
  • the arrangement of the common electrode line on the side of the first sub-region 1021 away from the display area can refer to the arrangement of the ground line 803. .
  • Figure 19 is a partial cross-sectional structural schematic diagram taken along line DD' shown in Figure 14 in another example according to an embodiment of the present disclosure.
  • the difference between the display substrate shown in FIG. 19 and the display substrate shown in FIG. 18 is that the overlapping traces 500 are located on the side of the data lines 600 away from the base substrate 100 .
  • the overlapping traces 500 can be arranged on the same layer as the common electrode 801 .
  • the overlapping trace 500 can be made of the same material as the common electrode 801 .
  • a space is provided between the overlapping trace 500 and the common electrode 801 .
  • gaps are provided between adjacent overlapping traces 500 .
  • the common electrode and the overlapping wiring can also be integrated into an integrated structure.
  • the overlapping wiring can be part of the entire common electrode.
  • the embodiments of the present disclosure are not limited to the overlapping traces 500 overlapping the signal line connection lines 400 including only one film layer.
  • two layers of overlapping traces may be provided on the side of the signal line connection lines 400 away from the base substrate 100 .
  • the positions of the two layers of overlapping traces can be the same as the positions of the two layers of overlapping traces shown in Figures 18 and 19, that is, the two layers of overlapping traces 500 are arranged on the same layer as the data lines and the common electrodes respectively.
  • FIG. 20 is a partial enlarged view of the B7 area shown in FIG. 11
  • FIG. 21 is a partial enlarged view of the B8 area shown in FIG. 11
  • the common electrode line 802 is electrically connected to the overlapping trace 500 .
  • the part of the common electrode line 802 located in the second area is arranged on the same layer as the overlapping trace 500 , and the part of the common electrode line 802 is located in the overlapping trace. 500 and the display area, the overlapping wiring 500 and this part of the common electrode line 802 are integrally provided.
  • the gate line 300 on the right is electrically connected, and the overlapping trace 500 covering the signal line connection line 400 extends to the right side to the common electrode line 802.
  • the gate line 300, the connection part 401 and the signal line connection line 400 are integrated.
  • the common electrode line 802 can be used as the dividing line between the gate line 300 and the connecting part 401, and/or the dividing line between the connecting part 401 and the signal line connecting line 400.
  • the common electrode lines 802 and the overlapping traces 500 can both be symmetrically distributed with respect to the center line extending along the Y direction of the first region.
  • FIG. 11 shows the portion located on the right side of the center line.
  • the section on the left can reference the section to the right of the center line.
  • the overall impedance of the common electrode can be reduced by electrically connecting the signal line connection line to the common electrode line.
  • the common electrode line 802 also includes a portion located on the side of the capacitance compensation structure 700 away from the overlapping traces 500.
  • this part of the common electrode line 802 can be in a step shape, and the capacitance compensation structure 700 is close to the overlapping traces.
  • the part on one side of the line 500 may be arc-shaped.
  • the embodiments of the present disclosure are not limited thereto, and the shape of the common electrode line may be set according to space and product requirements.
  • the overlapping trace 500 may be electrically connected to an arc-shaped portion of the common electrode line 802 .
  • the portions of the two portions of the common electrode lines 802 located on both sides of the capacitance compensation structure 700 and close to the first area may be spaced apart.
  • the display substrate further includes a connection line 501 , the extension direction of the connection line 510 intersects the extension direction of the overlapping trace 500 ; the connection line 501 is configured to connect the overlapping trace 500 is electrically connected to the portion of the common electrode line 802 located in the second area; the connection line 501 is arranged in the same layer as at least one of the overlapping wiring 500 and the common electrode line 802 .
  • connection line 501, the overlapping wiring 500 and the common electrode line 802 are all arranged in the same layer.
  • the connecting line 501 and the overlapping wiring 500 form a grid structure, such as the common electrode line 802 , the connection lines 501 and the overlapping traces 500 are integrated structures.
  • the connection line 501 is electrically connected to a portion of the common electrode line 802 located away from the capacitance compensation structure 700 and away from the overlapping wiring 500 .
  • the above-mentioned method of integrating the signal line connecting line and the common electrode line to achieve electrical connection and the method of arranging the connecting line to achieve electrical connection of the signal line connecting line and the common electrode line in Figure 20 can be used at the same time, or only one of them can be used.
  • FIG. 22 is a schematic partial structural diagram of a display substrate according to another example of an embodiment of the present disclosure
  • FIG. 23 is a schematic partial cross-sectional structural diagram taken along line EE' shown in FIG. 22 .
  • the difference between the display substrate shown in FIG. 22 and the display substrate shown in FIGS. 5 to 21 is that the overlapping traces 500 and the common electrode lines 802 electrically connected thereto are located on different layers.
  • the part of the common electrode line 802 located in the second area and the overlapping wiring 500 are located on different layers, and an insulating layer 003 is provided between the two.
  • the overlapping wiring 500 This part of the common electrode line 802 is electrically connected through a via hole 0031 located in the insulating layer 003 .
  • the common electrode line 802 is located on a side of the overlapping trace 500 away from the base substrate 100 .
  • the common electrode line 802 and the common electrode shown in FIG. 23 are located on the same layer.
  • the common electrode line 802 and the common electrode are both transparent conductive layers.
  • the film layers where the overlapping traces 500 and the common electrode lines 802 are located can be interchanged.
  • the overlapping traces 500 are arranged on the same layer as the common electrodes, and the common electrode lines 802 are arranged on the same layer as the data lines, overlapping.
  • the trace 500 is electrically connected to the common electrode line 802 through a via hole in the insulation layer between the trace 500 and the common electrode line 802 .
  • the display substrate may include the connection lines shown in FIG. 21 , which are located on different layers from the common electrode lines.
  • the connection lines, overlapping traces and data lines are located on the same layer, and the common electrode lines are on the same layer as the common electrode lines.
  • the electrodes are on the same layer, or the connecting lines, overlapping traces and common electrodes are on the same layer.
  • the common electrode lines and data lines are on the same layer.
  • the connecting lines are electrically connected to the common electrode lines through vias between them and the common electrode lines. .
  • the overlapping traces can be electrically connected to the common electrode lines in the manner shown in Figure 22, and the overlapping traces can also be electrically connected to the common electrode lines in the manner of connecting lines shown in Figure 21, or overlapping
  • the wiring is electrically connected to the common electrode line using both the method shown in Figure 22 and the method of connecting lines shown in Figure 21 .
  • FIG. 24 is a schematic diagram of a partial planar structure of a display substrate according to another example of an embodiment of the present disclosure.
  • FIGS. 25 to 27 are schematic diagrams of different examples of partial cross-sectional structures taken along the FF' line shown in FIG. 24 .
  • the difference between the display substrate shown in FIG. 24 and the display substrate shown in FIG. 5 is that the signal line connection line 400 and the gate line 300 electrically connected thereto are located on different layers.
  • the gate lines, sub-pixels, data lines, capacitance compensation structures, common electrodes and other structures in the example shown in Figure 24 may have the same structures as the gate lines, sub-pixels, data lines, capacitance compensation structures, common electrodes and other structures in the above example. The technical characteristics will not be repeated here.
  • FIG. 24 only schematically shows the signal line connection lines 400 and does not show the overlapping traces 500.
  • the signal line connection line 400 is located on a side of the gate line 300 away from the base substrate 100 .
  • the signal line connecting lines 400 and the data lines 600 are arranged on the same layer.
  • the signal line connection line 400 is electrically connected through a via hole between the gate insulation layer 001 between the signal line connection line 400 and the gate line 300 .
  • the signal line connection line 400 is made of the same material as the data line 600 .
  • FIG. 25 schematically shows that the signal line connection line 400 is directly electrically connected to the gate line 300 through the via hole between the gate insulation layer 001 between the signal line connection line 400 and the gate line 300.
  • the signal line connection line 400 also It can be connected to the gate line through other conductive layers. At this time, the orthographic projection of the signal line connection line 400 on the substrate is still completely located within the orthographic projection of the overlapping wiring on the substrate.
  • the overlapping trace 500 is located between the signal line connection line 400 and the base substrate 100 .
  • the overlapping traces 500 and the gate lines 300 are arranged on the same layer.
  • the material of the overlapping trace 500 is the same as the material of the gate line 300 .
  • the overlapping traces 500 are spaced apart from the gate lines 300 .
  • the overlapping traces 500 and the gate lines 300 are arranged in the same layer, the overlapping traces 500 can be electrically connected to the common electrode lines arranged in the same layer, and the overlapping traces 300 can also be connected to the data lines or common electrodes.
  • the common electrode lines of the film layer are electrically connected.
  • the overlapping traces 500 are located on a side of the signal line connecting lines 400 away from the base substrate 100 .
  • the overlapping trace 500 may be disposed on the same layer as the common electrode 801 .
  • the material of the overlapping trace 500 may be the same as the material of the common electrode 801 .
  • the overlapping traces 500 and the common electrode 801 are arranged in the same layer
  • the overlapping traces 500 can be electrically connected to the common electrode lines arranged in the same layer
  • the overlapping traces 300 can also be connected to the common electrode lines located on the film layer where the data lines are located.
  • the common electrode wire is electrically connected.
  • the overlapping traces 500 include a first overlapping trace 510 and a second overlapping trace 510 respectively located on both sides of the signal line connection line 400 in a direction perpendicular to the base substrate 100 .
  • the display substrate is provided with first overlapping wiring lines and second overlapping wiring lines that overlap with the signal line connecting lines and are respectively located on both sides of the signal line connecting lines, so that a double-layer capacitor can be formed in parallel. structure to maximize the capacitance formed between the signal line connection line and other conductive layers.
  • the signal line connection line 400 and the data line 600 are arranged on the same layer, and one of the first overlapping trace 510 and the second overlapping trace 520 is on the same layer as the gate line 300 It is provided that the other of the first overlapping wire 510 and the second overlapping wire 520 is arranged in the same layer as the common electrode 801 .
  • FIG. 28 is a schematic plan view of a display substrate according to another embodiment of the present disclosure.
  • FIG. 29 is a partial structural schematic view of the region G1 shown in FIG. 28 .
  • FIG. 30 is a partial cross-sectional structural schematic view taken along the HH' line shown in FIG. 29
  • Figure 31 is a partial structural schematic diagram of the region G2 shown in Figure 28
  • Figure 32 is a partial cross-sectional structural schematic diagram taken along line II' shown in Figure 31.
  • the display substrate includes a base substrate 100 and a plurality of sub-pixels 200 , a plurality of signal lines 300 and a plurality of signal line connection lines 400 located on the base substrate 100 .
  • the base substrate 100 includes a first region 101 and a second region 102 located around the first region 101 .
  • multiple sub-pixels 200 are located in the first area 101 and the second area 102.
  • the number of sub-pixels 200 arranged along the first direction in the first area 101 is greater than that along the first direction in the second area 102.
  • the number of arranged sub-pixels 200 For example, the number of a row of sub-pixels 200 or a column of sub-pixels 200 arranged along the first direction in the first area 101 is greater than the number of a row of sub-pixels 200 or a column of sub-pixels 200 arranged along the first direction in the second area 102.
  • a plurality of signal lines 300 are located in the first area 101 and the second area 102 , and at least part of each signal line 300 extends along the first direction.
  • a row of sub-pixels 200 or a column of sub-pixels 200 are electrically connected.
  • a plurality of signal line connection lines 400 are located in the second area 102 , and the plurality of signal line connection lines 400 are configured to be electrically connected to the signal line 300 located in the second area 102 , and each signal line At least part of the connection line 500 extends along the first direction.
  • the display substrate also includes a plurality of overlapping traces 500 located in the second area 102 .
  • the plurality of overlapping traces 500 are spaced apart and located on different layers from the plurality of signal line connecting lines 400 .
  • the orthographic projection of the signal line connection line 400 on the base substrate 100 is completely located within the orthographic projection of an overlapping trace 500 on the base substrate 100 .
  • the display substrate provided by the present disclosure, by arranging the orthographic projection of at least one signal line connection line on the substrate to be completely located within the orthographic projection of the overlapping wiring on the substrate, it is possible to satisfy the positive requirements of the frame sealing glue as much as possible.
  • the overlapping area of the signal line connection line and the overlapping trace is increased, thereby reducing the resistance-capacitance load ( RC load) to maximize compensation to avoid uneven display of low grayscale images in special-shaped display substrates.
  • the difference between the display substrate shown in FIG. 28 and the display substrate shown in FIG. 5 lies in the shape of the display area 104.
  • the display area 104 shown in FIG. 5 includes a notch, and the shape of the display area 104 shown in FIG. 28 may be similar to a triangle.
  • the first direction shown in FIG. 28 is the The position where the RC load ratio on the gate line 300 electrically connected to a row of sub-pixels 200 arranged along the X direction in the first region 101 is approximately 0.85 serves as the boundary between the first region 101 and the second region 102 .
  • the first direction shown in FIG. 28 is the The position where the RC load ratio on the gate line 300 electrically connected to a row of sub-pixels 200 arranged along the X direction in the first region 101 is approximately 0.85 serves as the boundary between the first region 101 and the second region 102 .
  • the signal line 300 is a data line
  • the boundary between the first region 101 and the second region 102 is located at a point where the ratio of the RC load on the data line electrically connected to a row of sub-pixels 200 arranged along the Y direction in the first region 101 is approximately 0.85.
  • the first direction may be the extension direction of the gate line 300 , in which case the signal line is the gate line 300 , the signal line connecting line 400 is electrically connected to the gate line 300 , and the signal line connecting line 400
  • the orthographic projection on the base substrate 100 is completely located within the orthographic projection of the overlapping traces 500 on the base substrate 100; alternatively, the first direction can be the extension direction of the data line 600, in which case the signal line is the data line 600,
  • the signal line connection line 400 is electrically connected to the data line 600, and the orthographic projection of the signal line connection line 400 on the substrate substrate 100 is completely located within the orthographic projection of the overlapping trace 500 on the substrate substrate 100; alternatively, the signal line includes The data line 600 and the gate line 300.
  • the signal line connection line 400 includes a data line connection line that is electrically connected to the data line 600, and a gate line connection line that is electrically connected to the gate line 300.
  • the overlapping trace 500 includes a data line connection line that is electrically connected to the data line. The overlapping part and the overlapping part with the gate line connection line.
  • the signal line connection lines 400 are electrically connected to the gate lines 300 , the signal line connection lines 400 and the gate lines 300 are arranged in the same layer, and the overlapping traces 500 are located away from the signal line connection lines 400 and the substrate. one side of the substrate 100 .
  • the signal line connection line 400 may be an extension line of the gate line 300 that is integrated with the gate line 300 .
  • the signal line connection line 400 is electrically connected to the data line 600 .
  • the signal line connection lines 400 can be arranged on the same layer as the data lines 600 and have an integrated structure.
  • the overlapping traces 500 can be located between the signal line connection lines 400 and the substrate 100, such as the same layer as the gate lines 300. Layer arrangement, the overlapping traces 500 can also be located on the side of the signal line connecting lines 400 away from the substrate substrate 100, such as being arranged on the same layer as the common electrodes, or the overlapping traces 500 can include located on the signal line connecting lines 400 perpendicular to the substrate.
  • the overlapping traces 500 are electrically connected to the common electrode lines.
  • the overlapping traces 500 can be on the same layer as the common electrode lines and integrated to achieve electrical connection, or the overlapping traces 500 can be on different layers from the common electrode lines and pass through vias in the insulating layer between them.
  • the signal line connection line 400 may be an extension line of the data line 600 that is integrated with the data line 600 .
  • the signal line connection line 400 can be located on a different layer from the data line 600, such as being located on the side of the data line 600 close to the base substrate 100, such as being placed on the same layer as the gate line 300.
  • the overlapping wiring 500 is located on the signal line.
  • the connection line 400 is on the side away from the base substrate 100, for example, it can be located on the film layer where the data line 600 is located or on the film layer where the common electrode is located, or it may include a two-part structure located on the film layer where the data line 600 is located and the film layer where the common electrode is located.
  • the signal line connection line 400 can be located on a different layer from the data line 600, such as on a side of the data line 600 away from the base substrate 100, such as being arranged on the same layer as the common electrode.
  • the overlapping wiring 500 is located on the signal line connection
  • the line 400 is close to the side of the base substrate 100, for example, it can be located on the film layer where the data line 600 is located or on the film layer where the gate line is located, or it may include a two-part structure located on the film layer where the data line 600 is located and the film layer where the gate line is located.
  • the overlapping trace 500 is electrically connected to the common electrode line.
  • the display substrate shown in FIG. 28 may also be provided with the capacitance compensation structure 700 in the display substrate shown in FIG. 11 .
  • the display substrate provided by the embodiment of the present disclosure includes a special-shaped display area.
  • the special-shaped display area is not limited to having a notch on the edge as shown in Figure 5 or a triangle-like shape as shown in Figure 28. It can also be a circular display area, an arc-shaped display area, and other special shapes. shape.
  • An embodiment of the present disclosure provides a display device, including the display substrate shown in any of the above examples.
  • the display device may be a liquid crystal display device.
  • the display substrate provided by the present disclosure may be an array substrate, and the display device further includes an opposing substrate disposed opposite to the array substrate.
  • the opposite substrate may be a color filter substrate.
  • the side of the color filter substrate facing the array substrate may be provided with a color filter layer corresponding to the pixel unit and a black matrix covering structures such as gate lines and data lines located in the non-display area.
  • a liquid crystal layer is disposed between the array substrate and the color filter substrate, and the common electrode is configured to apply a common voltage to generate an electric field with the pixel electrode that drives the deflection of liquid crystal molecules in the liquid crystal layer.
  • the liquid crystal molecules are deflected to change the transmittance of the liquid crystal layer, thereby achieving the display of the desired grayscale image.
  • the display device further includes a first polarizer disposed on a side of the array substrate away from the opposite substrate and a second polarizer disposed on a side of the opposite substrate away from the array substrate.
  • the first polarizer includes a light transmission axis extending along a first direction and polarizes the backlight incident therein along the first direction.
  • the second polarizer includes a light transmission axis extending along the second direction and polarizes the light incident on the second polarizer along the second direction.
  • the transmission axis of the first polarizer and the transmission axis of the second polarizer are perpendicular to each other.
  • the display device further includes a backlight source located on the non-display side of the display substrate to provide backlight for the display substrate.
  • the functional components may be provided at the notch in the second area.
  • the functional components include a camera module (for example, a front camera module), a 3D structured light module (for example, a 3D structured light sensor), a time-of-flight module At least one of a 3D imaging module (for example, a time-of-flight sensor) and an infrared sensing module (for example, an infrared sensing sensor).
  • the front camera module is usually activated when the user takes a selfie or makes a video call, and the pixel display area of the display device displays the image obtained by the selfie for the user to view.
  • the front camera module includes, for example, a lens, an image sensor, an image processing chip, etc.
  • 3D structured light sensors and Time of Flight (ToF) sensors can be used for face recognition to unlock display devices, etc.
  • the functional component may only include a camera module to realize the function of taking selfies or video calls; for example, the functional component may further include a 3D structured light module or a time-of-flight 3D imaging module to realize face recognition and unlocking, etc.
  • This implementation Examples include but are not limited to this.
  • the display device can be any product or component with a display function such as a mobile phone with an under-screen camera, a tablet computer, a notebook computer, a navigator, etc. This embodiment is not limited thereto.

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Abstract

一种显示基板以及显示装置。显示基板包括衬底基板（100）、子像素（200）、信号线（300）以及信号线连接线（400）。衬底基板（100）包括第一区域（101）以及第二区域（102）；第一区域（101）内沿第一方向排列的子像素（200）的数量大于第二区域（102）内沿第一方向排列的子像素（200）的数量;每条信号线（300）与沿第一方向排列的子像素（200）电连接；信号线连接线（400）与位于第二区域（102）的信号线（300）电连接，且每条信号线连接线（400）的至少部分沿第一方向延伸。显示基板还包括交叠走线（500），交叠走线（500）间隔设置且与信号线连接线（400）位于不同层，至少一条信号线连接线（400）在衬底基板上的正投影完全位于至少一条交叠走线（500）在衬底基板上的正投影内。显示基板在满足封框胶正对的显示基板透光率的前提下，提高信号线连接线（400）与交叠走线（500）的交叠面积以改善显示效果。

Description

显示基板以及显示装置 技术领域
本公开实施例涉及一种显示基板以及显示装置。
背景技术
目前，越来越多的手机产品中显示区域具有异形外形，如显示区域设置一开口或者显示区域形状为类似三角形等，摄像头、光敏器件等可以设置在上述开口内或类似三角形的显示区域以外位置，以在提高显示屏的屏占比的同时，还可以拥有流畅美观的外形。
发明内容
本公开提供一种显示基板以及显示装置。显示基板包括衬底基板、位于衬底基板上的多个子像素、多条信号线以及多条信号线连接线。衬底基板包括第一区域以及位于所述第一区域周边的第二区域；多个子像素位于所述第一区域和所述第二区域，所述第一区域内沿第一方向排列的子像素的数量大于所述第二区域内沿所述第一方向排列的子像素的数量；多条信号线位于所述第一区域和所述第二区域，且每条信号线的至少部分沿所述第一方向延伸，每条信号线与沿所述第一方向排列的一排子像素电连接；多条信号线连接线位于所述第二区域，所述多条信号线连接线被配置为与位于所述第二区域的所述信号线电连接，且每条信号线连接线的至少部分沿所述第一方向延伸。所述显示基板还包括位于所述第二区域的多条交叠走线，所述多条交叠走线间隔设置且与所述多条信号线连接线位于不同层，至少一条信号线连接线在所述衬底基板上的正投影完全位于至少一条交叠走线在所述衬底基板上的正投影内。
例如，根据本公开的实施例，所述多条信号线包括多条栅线和多条数据线的至少一种。
例如，根据本公开的实施例，所述交叠走线的延伸方向与所述信号线连接线的延伸方向相同，且所述交叠走线的线宽大于等于所述信号线连接线的线宽。
例如，根据本公开的实施例，所述多条交叠走线分别与所述多条信号线连接线一一对应设置，每条信号线连接线在所述衬底基板上的正投影完全位于对 应设置的所述交叠走线在所述衬底基板上的正投影内，且相邻交叠走线之间的间隔不小于1.5微米。
例如，根据本公开的实施例，所述信号线连接线和与其电连接的所述信号线同层设置。
例如，根据本公开的实施例，所述交叠走线位于所述信号线连接线远离所述衬底基板的一侧。
例如，根据本公开的实施例，所述多条信号线包括多条栅线，所述显示基板还包括：多条数据线，位于所述多条栅线远离所述衬底基板的一侧，且每条数据线的至少部分沿第二方向延伸，所述第二方向与所述第一方向相交。沿垂直于所述衬底基板的方向，所述数据线与所述信号线连接线不交叠，所述交叠走线与所述数据线同层设置；或者，所述交叠走线位于所述数据线远离所述衬底基板的一侧。
例如，根据本公开的实施例，所述信号线连接线和与其电连接的所述信号线位于不同层。
例如，根据本公开的实施例，所述多条信号线包括多条栅线，所述显示基板还包括：多条数据线，位于所述多条栅线远离所述衬底基板的一侧，且每条数据线的至少部分沿第二方向延伸，所述第二方向与所述第一方向相交。沿垂直于所述衬底基板的方向，所述数据线与所述信号线连接线不交叠，所述信号线连接线与所述数据线同层设置。
例如，根据本公开的实施例，所述交叠走线与所述栅线同层设置，或者，所述交叠走线位于所述信号线连接线远离所述衬底基板的一侧。
例如，根据本公开的实施例，所述交叠走线包括在垂直于所述衬底基板的方向上分别位于所述信号线连接线两侧的第一交叠走线和第二交叠走线；在垂直于所述衬底基板的方向，所述第一交叠走线和所述第二交叠走线交叠，且所述信号线连接线在所述衬底基板上的正投影位于所述第一交叠走线和所述第二交叠走线至少之一在所述衬底基板上的正投影内。
例如，根据本公开的实施例，所述多条信号线包括多条栅线，所述显示基板还包括：多条数据线，位于所述多条栅线远离所述衬底基板的一侧，且每条数据线的至少部分沿第二方向延伸，所述第二方向与所述第一方向相交。所述子像素包括公共电极，位于所述数据线远离所述衬底基板的一侧，沿垂直于所述衬底基板的方向，所述数据线与所述信号线连接线不交叠，所述信号线连接 线与所述数据线同层设置，所述第一交叠走线与所述第二交叠走线之一与所述栅线同层设置，所述第一交叠走线与所述第二交叠走线的另一个与所述公共电极同层设置。
例如，根据本公开的实施例，所述显示基板包括显示区和非显示区，所述第二区域包括所述显示区的一部分以及所述非显示区的一部分，且所述信号线连接线的至少部分位于所述非显示区。
例如，根据本公开的实施例，所述信号线连接线与在所述第一方向上位于该信号线连接线至少一侧的所述信号线电连接，所述信号线连接线和与其电连接的所述信号线之间设置至少一个电容补偿结构，且所述电容补偿结构位于所述非显示区，所述电容补偿结构与分别位于其两侧的所述信号线和所述信号线连接线均电连接，所述第二方向与所述第一方向相交。
例如，根据本公开的实施例，所述多条信号线包括多条栅线，所述显示基板还包括：多条数据线，位于所述多条栅线远离所述衬底基板的一侧，且每条数据线的至少部分沿第二方向延伸，所述第二方向与所述第一方向相交；所述子像素包括公共电极，位于所述数据线远离所述衬底基板的一侧；所述第一区域内，与一行子像素电连接的所述栅线和与其交叠的所述数据线和所述公共电极之间产生的电容的值为第一电容值；所述第二区域内，与一行子像素电连接的所述栅线和与其交叠的所述数据线和所述公共电极之间产生的电容、与该栅线电连接的一条信号线连接线和与其交叠的所述交叠走线之间产生的电容以及所述电容补偿结构上的电容的总电容的值为第二电容值，所述第二电容值与所述第一电容值的比值为0.85～1。
例如，根据本公开的实施例，所述至少一条信号线连接线沿着所述第二区域远离所述第一区域的部分边缘延伸。
例如，根据本公开的实施例，所述第二区域内的所述非显示区包括第一子区域和第二子区域，所述第二子区域位于所述第一子区域与所述显示区之间，所述信号线连接线位于所述第一子区域，所述电容补偿结构位于所述第二子区域。
例如，根据本公开的实施例，所述子像素包括公共电极，位于所述信号线远离所述衬底基板的一侧。所述显示基板还包括位于所述衬底基板上的公共电极线，所述公共电极线被配置为与所述公共电极电连接，且所述公共电极线与所述交叠走线电连接。
例如，根据本公开的实施例，所述公共电极线位于所述第二区域的部分与所述交叠走线同层设置，且所述公共电极线的该部分位于所述交叠走线与所述显示区之间，所述交叠走线与所述公共电极线的该部分一体化设置。
例如，根据本公开的实施例，所述公共电极线位于所述第二区域的部分与所述交叠走线位于不同层，且两者之间设置有绝缘层，所述交叠走线通过位于所述绝缘层中的过孔与所述公共电极线的该部分电连接。
例如，根据本公开的实施例，显示基板还包括连接线，所述连接线的延伸方向与所述交叠走线的延伸方向相交。所述连接线被配置为将所述交叠走线与所述公共电极线位于所述第二区域的部分电连接；所述连接线与所述交叠走线同层设置。
例如，根据本公开的实施例，所述第二区域内的所述显示区包括沿所述第一方向排列的两个子显示区，所述两个子显示区之间设置有间隔以使所述第二区域远离所述第一区域的边缘形成凹口，所述显示基板包括位于所述非显示区域的封框胶区域，所述封框胶区域被配置为设置封框胶；所述信号线连接线包括位于所述两个子显示区之间且位于所述封框胶区域的部分，且所述信号线连接线被配置为连接分别位于所述两个子显示区的所述信号线，所述第二方向与所述第一方向相交。
例如，根据本公开的实施例，所述至少一条信号线连接线沿着所述凹口的至少部分边缘延伸。
本公开实施例提供一种显示装置，包括上述任一显示基板。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1为一种显示基板的平面示意图。
图2为图1所示A1区域的局部放大示意图。
图3为图2所示A2区域的局部放大示意图。
图4为图2所示A3区域的局部放大示意图。
图5为根据本公开实施例提供的显示基板的整体轮廓图。
图6为图5所示B1区域的局部放大图。
图7和图8为图6所示结构的示意性图。
图9为图6所示B2区域的局部放大图。
图10为图9所示区域的栅线所在层的示意图。
图11为图9所示B3区域的局部放大图。
图12为图10所示B5区域的局部放大图。
图13为图11所示区域的数据线所在层的示意图。
图14为图9所示B4区域的局部放大图。
图15为图10所示B6区域的局部放大图。
图16为图14所示区域的数据线所在层的示意图。
图17为图1所示显示基板与图5所示显示基板中不同区域栅线上的电容值的关系图。
图18为沿图14所示的DD’线所截的局部截面结构示意图。
图19为根据本公开实施例的另一示例中沿图14所示的DD’线所截的局部截面结构示意图。
图20为图11所示B7区域的局部放大图。
图21为图11所示B8区域的局部放大图。
图22为根据本公开实施例的另一示例提供的显示基板中的局部结构示意图。
图23为沿图22所示EE’线所截的局部截面结构示意图。
图24为根据本公开实施例的另一示例提供的显示基板的局部平面结构示意图。
图25至图27为沿图24所示FF’线所截的局部截面结构的不同示例的示意图。
图28为根据本公开另一实施例提供的显示基板的平面示意图。
图29为图28所示区域G1的部分结构示意图。
图30为沿图29所示HH’线所截的局部截面结构示意图。
图31为图28所示区域G2的部分结构示意图。
图32为沿图31所示II’线所截的局部截面结构示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开 实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。
本公开实施例中使用的“平行”、“垂直”以及“相同”等特征均包括严格意义的“平行”、“垂直”、“相同”等特征，以及“大致平行”、“大致垂直”、“大致相同”等包含一定误差的情况，考虑到测量和与特定量的测量相关的误差(例如，测量系统的限制)，表示在本领域的普通技术人员所确定的对于特定值的可接受的偏差范围内。例如，“大致”能够表示在一个或多个标准偏差内，或者在所述值的10％或者5％内。在本公开实施例的下文中没有特别指出一个成分的数量时，意味着该成分可以是一个也可以是多个，或可理解为至少一个。“至少一个”指一个或多个，“多个”指至少两个。本公开中所称的“同层设置”是指两种(或两种以上)结构通过同一道沉积工艺形成并通过同一道构图工艺得以图案化而形成的结构，它们的材料可以相同或不同。本公开中的“一体化设置的结构”是指两种(或两种以上)结构通过同一道沉积工艺形成并通过同一道构图工艺得以图案化而形成的彼此连接的结构，它们的材料可以相同或不同。
图1为一种显示基板的平面示意图，图2为图1所示A1区域的局部放大示意图，图3为图2所示A2区域的局部放大示意图，图4为图2所示A3区域的局部放大示意图。如图1至图4所示，显示基板10包括异形显示区，该异形显示区的一侧设置有凹口17，异形显示区内设置有位于衬底基板上的多个子像素12。以X方向为行方向，Y方向为列方向为例，位于凹口17在X方向上的两侧的显示区可以分别为第一显示区和第二显示区，与分别位于第一显示区和第二显示区且分布在同一行的子像素12电连接的栅线14通过栅线连接线11电连接，如栅线连接线11与栅线14可以为同层设置的走线，如栅线连接线 11与栅线14可以为一体化设置的结构。
如图1至图4所示，由于凹口17在X方向上的两侧的第一显示区和第二显示区设置的一行子像素12的数量小于凹口17在Y方向上的一侧的显示区(如第三显示区)设置的一行子像素12的数量，与第一显示区和第二显示区中同一行子像素12电连接的栅线14以及栅线连接线11与其他导电层(如数据线所在导电层以及公共电极所在导电层)之间产生的电容的电容值为C01，与第三显示区中一行子像素12电连接的栅线与其他导电层(如数据线所在导电层以及公共电极所在导电层)之间产生的电容的电容值为C02，为了降低C01与C02之间的差异，可以在栅线连接线11与第一显示区或第二显示区的子像素12之间设置电容补偿结构16，和/或，在位于第三显示区靠近凹口17的部分栅线连接线11远离衬底基板的一侧设置多条沿Y方向延伸的覆盖条13。在采用上述方式对电容值C01进行补偿后得到电容值C03。
在研究中，本申请的发明人发现：电容值C03和与电容值C02之比小于70％，会导致第一显示区显示图案时出现低灰阶发白的现象。
本公开实施例提供一种显示基板以及显示装置。显示基板包括衬底基板、位于衬底基板上的多个子像素、多条信号线以及多条信号线连接线。衬底基板包括第一区域以及位于第一区域周边的第二区域；多个子像素位于第一区域和第二区域，第一区域内沿第一方向排列的子像素的数量大于第二区域内沿第一方向排列的子像素的数量；多条信号线位于第一区域和第二区域，且每条信号线的至少部分沿第一方向延伸，每条信号线与沿第一方向排列的一排子像素电连接；多条信号线连接线位于第二区域，多条信号线连接线被配置为与位于第二区域的信号线电连接，且每条信号线连接线的至少部分沿第一方向延伸。显示基板还包括位于第二区域的多条交叠走线，多条交叠走线间隔设置且与多条信号线连接线位于不同层，至少一条信号线连接线在衬底基板上的正投影完全位于至少一条交叠走线在衬底基板上的正投影内。
本公开提供的显示基板中，通过将信号线连接线在衬底基板上的正投影设置为完全位于交叠走线在衬底基板上的正投影内，可以在尽量满足封框胶(seal)正对的显示基板中金属层的透光率的前提下，提高信号线连接线与交叠走线的交叠面积，从而对异形显示基板的第二区域内的信号线上的电阻-电容负载(RC负载)进行最大化的补偿以尽量避免异形显示基板中低灰阶画面显示不均现象的产生。
下面结合附图对本公开实施例提供的显示基板以及显示装置进行描述。
图5为根据本公开实施例提供的显示基板的整体轮廓图，图6为图5所示B1区域的局部放大图，图7和图8为图6所示结构的示意性图。
如图5至图8所示，显示基板包括衬底基板100以及位于衬底基板100上的多个子像素200、多条信号线300以及多条信号线连接线400。衬底基板100包括第一区域101以及位于第一区域101周边的第二区域102。例如，第二区域102可以位于第一区域101在某一方向，如图1所示的Y方向上的一侧，也可以为围绕第一区域101的至少部分。
如图5至图8所示，多个子像素200位于第一区域101和第二区域102，第一区域101内沿第一方向排列的子像素200的数量大于第二区域102内沿第一方向排列的子像素200的数量。例如，第一区域101内沿第一方向排列的一行子像素200或一列子像素200的数量大于第二区域102内沿第一方向排列的一行子像素200或一列子像素200的数量。
例如，本公开实施例中的第一方向为图中所示的X方向，第一方向可以为行方向，也可以为列方向。第一方向为信号线的延伸方向。例如，第一区域101和第二区域102的排列方向与第一方向相交。例如，图中示意性的示出第一区域101和第二区域102沿Y方向排列，Y方向可以为第二方向。例如，第一方向和第二方向之一可以为行方向，另一个可以为列方向。当然，第一方向和第二方向可以互换，但位于显示区域的信号线的延伸方向平行于第一方向。
例如，第二区域102在第一方向上的尺寸小于第一区域101在第一方向上的尺寸，如第二区域102在第一方向上的最大尺寸不大于第一区域101在第一方向上的最小尺寸，由此，第二区域102中设置的沿第一方向排列的子像素200的数量小于第一区域101中设置的沿第一方向排列的子像素200的数量。
例如，第二区域102中设置的沿第一方向排列的子像素200的数量与第一区域101中设置的沿第一方向排列的子像素200的数量之比可以为0.01～0.9。例如，第二区域102中设置的沿第一方向排列的子像素200的数量与第一区域101中设置的沿第一方向排列的子像素200的数量之比可以为0.05～0.8。例如，第二区域102中设置的沿第一方向排列的子像素200的数量与第一区域101中设置的沿第一方向排列的子像素200的数量之比可以为0.07～0.7。例如，第二区域102中设置的沿第一方向排列的子像素200的数量与第一区域101中设置的沿第一方向排列的子像素200的数量之比可以为0.1～0.6。例如，第二区域 102中设置的沿第一方向排列的子像素200的数量与第一区域101中设置的沿第一方向排列的子像素200的数量之比可以为0.2～0.5。例如，第二区域102中设置的沿第一方向排列的子像素200的数量与第一区域101中设置的沿第一方向排列的子像素200的数量之比可以为0.25～0.4。例如，第二区域102中设置的沿第一方向排列的子像素200的数量与第一区域101中设置的沿第一方向排列的子像素200的数量之比可以为0.35～0.45。
例如，第二区域102远离第一区域101的部分包括边框，边框的尺寸设置的较窄。例如，第二区域102在第一方向上的尺寸与第一区域101在第一方向上的尺寸之比可以为0.01～0.9。例如，第二区域102在第一方向上的尺寸与第一区域101在第一方向上的尺寸之比可以为0.04～0.8。例如，第二区域102在第一方向上的尺寸与第一区域101在第一方向上的尺寸之比可以为0.06～0.7。例如，第二区域102在第一方向上的尺寸与第一区域101在第一方向上的尺寸之比可以为0.1～0.75。例如，第二区域102在第一方向上的尺寸与第一区域101在第一方向上的尺寸之比可以为0.15～0.6。例如，第二区域102在第一方向上的尺寸与第一区域101在第一方向上的尺寸之比可以为0.25～0.65。例如，第二区域102在第一方向上的尺寸与第一区域101在第一方向上的尺寸之比可以为0.2～0.55。例如，第二区域102在第一方向上的尺寸与第一区域101在第一方向上的尺寸之比可以为0.25～0.5。例如，第二区域102在第一方向上的尺寸与第一区域101在第一方向上的尺寸之比可以为0.3～0.45。例如，第二区域102在第一方向上的尺寸与第一区域101在第一方向上的尺寸之比可以为0.35～0.4。
例如，如图7和图8所示，位于第一区域101的子像素200沿第一方向和第二方向阵列排布。例如，位于第二区域102的子像素200沿第一方向和第二方向阵列排布。
例如，以图中第一方向为行方向，第二方向为列方向为例，位于第一区域101的子像素200包括沿第二方向排列的多个子像素行，每个子像素行中的子像素200沿第一方向排列，且第一区域101的至少部分区域中的各子像素行包括的子像素200的数量相同。例如，第一区域101中各子像素行包括的子像素200的数量相同。本公开实施例不限于此，第一方向可以为列方向，第二方向可以为行方向。
例如，位于第二区域102的子像素包括沿第二方向排列的多个子像素行， 每个子像素行中的子像素200沿第一方向排列，且不同子像素行中的子像素200的数量可以相同，也可以不同。例如，第二区域102中的任一子像素行中的子像素的数量均小于第一区域101中的任一子像素行中的子像素的数量。图5至图8示意性的示出显示基板的第二区域102包括凹口103，此时，第二区域102中的每个子像素行包括位于凹口103两侧的两部分。
如图5至图8所示，多条信号线300位于第一区域101和第二区域102，且每条信号线300的至少部分沿第一方向延伸，每条信号线300与沿第一方向排列的一行子像素200或一列子像素200电连接。
在一些示例中，信号线300包括栅线和数据线的至少一种。例如，信号线300可以仅为栅线，或者仅为数据线，或者包括栅线和数据线。图5至图8所示实施例示意性的示出信号线300为栅线。
在一些示例中，如图5至图8所示，显示基板包括显示区104和非显示区105，第二区域102包括显示区104的一部分以及非显示区105的一部分。例如，显示区104为用于显示图像的区域，非显示区105为不显示图像的区域。例如，非显示区105可以包括边框。例如，显示区104中分布有用于显示图像的子像素以及相邻子像素之间设置的信号线(包括栅线以及数据线)。例如，本公开实施例示意性的示出非显示区105可以位于显示区104的一侧，或者围绕显示区104，但不限于此，显示区也可以围绕非显示区。例如，位于第一区域101内显示区104中的各栅线300均沿第一方向延伸，且位于第一区域101中的栅线300沿第二方向排列。例如，位于第二区域102内显示区104中的各栅线300均沿第一方向延伸，且位于第二区域102中的栅线300沿第二方向排列。
如图5至图8所示，多条信号线连接线400位于第二区域102，多条信号线连接线400被配置为与位于第二区域102的信号线300电连接，且每条信号线连接线500的至少部分沿第一方向延伸。例如，信号线连接线400的至少部分位于非显示区105。
例如，图5至图8示意性的示出信号线为栅线，信号线连接线为与栅线电连接的栅线连接线。但不限于此，信号线为数据线时，信号线连接线为与数据线电连接的数据线连接线。
在一些示例中，如图5至图8所示，第二区域102内的显示区104包括沿第一方向排列的两个子显示区1041和1042，两个子显示区1041和1042之间 设置有间隔以使第二区域102远离第一区域104的边缘形成上述凹口103。例如，凹口103两侧的两个子显示区1041和1042对称分布。例如，凹口103两侧的两个子显示区1041和1042内的子像素200相对于显示区104的沿Y方向延伸的中心线对称分布。例如，凹口103两侧的两个子显示区1041和1043内的栅线300相对于上述中心线对称分布。例如，信号线连接线400的至少部分相对于上述中心线对称分布。
在一些示例中，如图5至图8所示，显示基板包括位于非显示区域105的封框胶区域SR，封框胶区域SR被配置为设置封框胶(后续描述)。例如，信号线连接线400包括位于两个子显示区1041和1042之间且位于封框胶区域SR的部分，且信号线连接线400被配置为连接分别位于两个子显示区1041和1042的栅线300。例如，沿垂直于衬底基板的方向，信号线连接线与封框胶区域设置的封框胶交叠。
例如，与位于凹口103两侧的且位于同一行的子像素200电连接的两部分栅线300通过一条信号线连接线400电连接。例如，与位于凹口103两侧的子像素行电连接的两部分栅线300的数量相同，且信号线连接线400的数量与位于凹口103一侧的栅线300的数量相同。
例如，图5至图8示意性的示出两个子显示区沿栅线的延伸方向排列，但不限于此，两个子显示区也可以沿数据线的延伸方向排列，则与位于凹口两侧的且位于同一列的子像素电连接的两部分数据线通过一条信号线连接线电连接。
如图5至图8所示，显示基板还包括位于第二区域102的多条交叠走线500，多条交叠走线500间隔设置且与多条信号线连接线400位于不同层，一条信号线连接线400在衬底基板100上的正投影完全位于一条交叠走线500在衬底基板100上的正投影内。
例如，信号线可以为栅线，与位于第二区域的至少一条栅线电连接的栅线连接线在衬底基板上的正投影位于至少一条交叠走线在衬底基板上的正投影内；信号线可以为数据线，与位于第二区域的至少一条数据线电连接的数据线连接线在衬底基板上的正投影位于至少一条交叠走线在衬底基板上的正投影内。
例如，至少一条信号线连接线400在衬底基板100上的正投影完全位于至少一条交叠走线500在衬底基板100上的正投影内。例如，至少部分信号线连 接线400在衬底基板100上的正投影完全位于相应的交叠走线500在衬底基板100上的正投影内。例如，每条交叠走线500和与其交叠的信号线连接线400的延伸方向相同。由于本公开提供的显示基板中，信号线连接线与交叠走线交叠设置，为了清晰地体现信号线连接线400的位置以及与栅线300的连接关系，图8省去了交叠走线500。此外，图7所示交叠走线500与栅线300之间示意的间隙表示交叠走线500与栅线300没有电连接。
本公开提供的显示基板中，通过将至少一条信号线连接线在衬底基板上的正投影设置为完全位于交叠走线在衬底基板上的正投影内，可以在尽量满足封框胶正对的显示基板中金属层的透光率的前提下，提高信号线连接线与交叠走线的交叠面积，从而对异形显示基板的第二区域内的信号线上的电阻-电容负载(RC负载)进行最大化的补偿以尽量避免异形显示基板中低灰阶画面显示不均现象的产生。
每根信号线的电阻和电容直接关系信号线电压变化时的延迟时间，从而影响子像素的充电时间以及对子像素的充电。本公开实施例通过补偿信号线的电阻和电容，以将每根信号线的RC负载补偿到跟其相邻信号线和其他所有信号线的RC负载趋于一致，进而这些信号线的延迟时间趋于一致，则不会对子像素的充电时间和充电有影响，从而，避免出现这种问题导致的不均匀(mura)。
与图4所示覆盖条13的延伸方向与信号线连接线11的延伸方向相交，且一条信号线连接线11在衬底基板上的正投影的部分与和该一条信号线连接线11交叠的覆盖条13在衬底基板上的正投影不交叠的情况相比，根据电容计算公式C＝ε0*εr*S/d，ε0*εr为介电常数，S为信号线连接线与交叠走线正对面积，d为信号线连接线与交叠走线之间的距离，本公开提供的显示基板中，将信号线连接线在衬底基板上的正投影设置为完全位于交叠走线在衬底基板上的正投影内，可以提高信号线连接线与交叠走线的交叠面积S，且其他参数不变，从而实现对异形显示基板的第二区域内信号线的RC负载进行最大化的补偿，以尽量避免异形显示基板中低灰阶画面显示不均现象的产生。
例如，如图7和图8所示，在第二区域102设置有凹口103时，信号线连接线400沿着凹口103的边缘延伸。例如，凹口103的边缘包括沿X方向延伸的直线边以及弧形边，信号线连接线400包括沿着凹口103的直线边延伸的直线部分以及沿着凹口103的弧形边延伸的弧形部分。例如，信号线连接线400的直线部分平行于第一方向。例如，信号线连接线400的弧形部分与位于第二 区域102的信号线300电连接。例如，信号线连接线400还可以包括弧形部分远离凹口103的且沿第一方向延伸的另一部分直线部分，该直线部分与栅线300连接。例如，信号线连接线400与信号线300之间可以设置一连接部以连接信号线连接线400和信号线300。
在一些示例中，如图5至图8所示，交叠走线500的延伸方向与信号线连接线400的延伸方向相同。例如，在信号线连接线400包括上述直线部分和弧形部分时，交叠走线500也包括与信号线连接线400的直线部分交叠的直线部分，以及与信号线连接线400的弧形部分交叠的弧形部分。
在一些示例中，如图5至图8所示，交叠走线500的线宽大于等于信号线连接线400的线宽。例如，交叠走线500的线宽大于信号线连接线400的线宽。例如，交叠走线500的线宽等于信号线连接线400的线宽。
例如，信号线连接线400的线宽不小于2微米。例如，信号线连接线400的线宽可以为3～6微米。例如，信号线连接线400的线宽可以为4～5.5微米。例如，信号线连接线400的线宽可以为4.5～5微米。例如，信号线连接线400之间的距离可以为1.5～6微米。例如，信号线连接线400之间的距离可以为1.5～6微米。例如，信号线连接线400之间的距离可以为2～4微米。例如，信号线连接线400之间的距离可以为3～5微米。
例如，交叠走线500的单边线宽(即线宽的一半)比信号线连接线400的单边线宽大0.5～2.5微米。例如，交叠走线500的线宽比信号线连接线400的线宽大1～5微米。例如，交叠走线500的线宽比信号线连接线400的线宽大1.5～4微米。例如，交叠走线500的线宽比信号线连接线400的线宽大2～2.5微米。例如，交叠走线500的线宽比信号线连接线400的线宽大2.2～3微米。本公开提供的显示基板中，通过将交叠走线的线宽设置为大于信号线连接线的线宽，可以降低对生产工艺中交叠走线和信号线连接线的制程要求，即使交叠走线相对于信号线连接线存在一定的相对位移，信号线连接线在衬底基板上的正投影依然完全位于交叠走线在衬底基板上的正投影内。
在一些示例中，如图5至图8所示，多条交叠走线500分别与多条信号线连接线400一一对应设置，每条信号线连接线400在衬底基板100上的正投影完全位于对应设置的交叠走线500在衬底基板100上的正投影内，且相邻交叠走线500之间的间隔不小于1.5微米。
例如，相邻交叠走线500之间的间隔不小于2微米。例如，相邻交叠走线 500之间的间隔不小于2.5微米。例如，相邻交叠走线500之间的间隔不小于3微米。例如，相邻交叠走线500之间的间隔不小于3.5微米。例如，相邻交叠走线500之间的间隔不小于4微米。例如，相邻交叠走线500之间的间隔不小于4.5微米。例如，相邻交叠走线500之间的间隔不小于5微米。例如，相邻交叠走线500之间的间隔不大于6微米。
例如，显示基板的显示侧设置有封框胶，沿垂直于衬底基板的方向，封框胶与相邻交叠走线之间的间隔交叠。例如，液晶显示装置的对盒制程中封框胶的固化过程中，需要采用光线(如紫外光)对封框胶的材料进行照射以实现固化，相邻交叠走线之间的间隔可以较好地透过光线以实现对封框胶的固化。
本公开实施例中，通过设置与多条信号线连接线一一交叠的多条交叠走线，且相邻交叠走线之间的间隔不小于1.5微米，可以在使得交叠走线与信号线连接线具有最大化交叠面积以对第二区域内的栅线进行电容补偿的同时，满足封框胶正对的显示基板位置处金属层的透光率。
例如，交叠走线500的数量与信号线连接线400的数量相同。当然，本公开实施例不限于此，在将信号线连接线在交叠走线所在层上的正投影设置为完全位于交叠走线中的情况下，交叠走线的数量可以与信号线连接线的数量不同，如交叠走线的数量可以大于信号线连接线的数量，或者交叠走线的数量也可以小于信号线连接线的数量。例如，沿垂直于衬底基板的方向，一条交叠走线可以与一条信号线连接线交叠，一条交叠走线也可以与多条信号线连接线交叠。
在一些示例中，如图5至图8所示，信号线包括栅线300，显示基板还包括多条数据线600，多条数据线600位于多条栅线300远离衬底基板100的一侧，且每条数据线600的至少部分沿第二方向延伸，第二方向与第一方向相交；沿垂直于衬底基板100的方向，数据线600与信号线连接线400不交叠，例如，数据线600仅位于第一区域101。例如，数据线600包括位于第一区域101和第二区域102的部分。
例如，如图5至图8所示，多条数据线600沿第一方向排列，且每条数据线600沿第二方向延伸。例如，多条数据线600和多条栅线300交叉设置以限定多个沿第一方向和第二方向阵列排布的子像素200所在的像素区。例如，至少部分像素区位于显示区。
图9为图6所示B2区域的局部放大图，图10为图9所示区域的栅线所在 层的示意图，图11为图9所示B3区域的局部放大图，图12为图10所示B5区域的局部放大图，图13为图11所示区域的数据线所在层的示意图，图14为图9所示B4区域的局部放大图，图15为图10所示B6区域的局部放大图，图16为图14所示区域的数据线所在层的示意图。
在一些示例中，如图11至图16所示，信号线连接线400与在第一方向上位于该信号线连接线400至少一侧的栅线300电连接，信号线连接线400和与其电连接的栅线300之间设置有块状的电容补偿结构700，且电容补偿结构700位于非显示区，电容补偿结构700与分别位于其两侧的栅线300和信号线连接线400均电连接。
例如，如图11至图16所示，一条信号线连接线400和与其电连接的栅线300之间设置的电容补偿结构700的数量至少为一个。例如，与不同栅线300电连接的电容补偿结构700的数量可以相同，也可以不同。
例如，如图5至图16所示，第二区域102的至少部分区域中，沿第一区域101和第二区域102的排列方向(图中所示Y方向的箭头所指的方向)排列的栅线300的长度逐渐减小。例如，与长度较短的栅线300电连接的电容补偿结构700的数量可以大于与长度较长的栅线300电连接的电容补偿结构700的数量，以平衡不同长度的栅线之间的RC负载差异。例如，与长度较短的栅线300电连接的信号线连接线400的长度可以大于与长度较长的栅线300电连接的信号线连接线400的长度，以平衡不同长度的栅线之间的RC负载差异。
例如，如图11至图16所示，至少一个电容补偿结构700包括层叠设置的两层结构，一层结构与栅线300位于同一层且与栅线300电连接，另一层可以与数据线600位于同一层，但不限于此，也可以为数据线远离衬底基板一侧的导电层(如与公共电极同层的导电层)。通过将电容补偿结构设置为双层结构，有利于降低与其电连接的栅线上的RC负载与第一区域的栅线上的RC负载的差异。当然，本公开实施例不限于此，至少一个电容补偿结构还可以包括层叠设置的三层结构，如分别为与栅线同层且电连接的一层，与数据线同层的一层以及数据线远离衬底基板一侧的导电层。
例如，如图11至图16所示，至少一个电容补偿结构700包括开口，以提高电容补偿结构所在位置的透光率，有利于封框胶的固化。
在一些示例中，如图9至图16所示，第二区域102内的非显示区包括第一子区域1021和第二子区域1022，第二子区域1022位于第一子区域1021与 显示区104之间，信号线连接线400位于第一子区域1021，电容补偿结构700位于第二子区域1022。图中9和图10示意性的示出了第一子区域1021与第二子区域1022之间的分界线1023，该分界线1023可以为第一子区域1021内信号线连接线400与第二子区域1022内电容补偿结构700之间的间隔，也可以为第一子区域1021内信号线连接线400与第二子区域1022内电容补偿结构700之间的公共电极线。
例如，如图11所示，第二子区域1022设置有连接部401，信号线连接线400通过连接部401与栅线300电连接。例如，信号线连接线400、连接部401以及栅线300可以为一体化设置的结构。
例如，如图9至图16所示，第二子区域1022位于凹口103在第一方向上的两侧。例如，第二子区域1022位于第一子区域1021远离凹口103的一侧。例如，电容补偿结构700仅分布在凹口103在第一方向上的两侧，凹口103与第一区域101之间没有设置电容补偿结构700，则第二子区域1022分分布在凹口103在第一方向的两侧，凹口103与第一区域101之间没有第二子区域1022。例如，信号线连接线400包括分布在凹口103在第一方向上的两侧的两部分以及分布在凹口103与第一区域101之间的部分，则第一子区域1021包括位于凹口103在第一方向上的两侧的两部分以及位于凹口103与第一区域101之间的部分。
例如，位于凹口103两侧的第二子区域1022相对于非显示区的沿Y方向延伸的中心线对称分布。例如，位于凹口103两侧的电容补偿结构700相对于非显示区的沿Y方向延伸的中心线对称分布。例如，第一区域1021相对于非显示区的沿Y方向延伸的中心线对称分布。
例如，如图5至图16所示，第一子区域1021包括位于凹口103与第二区域102的显示区之间的部分以及位于凹口103与第一区域101的显示区之间的部分。例如，第一子区域1021沿着凹口103的边缘延伸。例如，位于凹口103在X方向上的一侧的信号线连接线400沿Y方向延伸。
本公开实施例提供的显示基板，通过将信号线连接线在交叠走线上的正投影设置为完全位于交叠走线内的同时，在信号线连接线与栅线之间设置电容补偿结构，可以共同对第二区域内栅线上的RC负载进行补偿，以使第二区域内栅线上RC负载与第一区域内栅线上RC负载之间的差异降到最低。
例如，如图5至图16所示，第一区域内101与一行子像素200电连接的 栅线300上的RC负载为第一RC负载，第二区域102内与一行子像素200电连接的栅线300上的RC负载为第二RC负载，第二RC负载与第一RC负载的比值为0.85～1。
例如，第二RC负载与第一RC负载的比值不小于0.88。例如，第二RC负载与第一RC负载的比值不小于0.9。例如，第二RC负载与第一RC负载的比值不小于0.92。例如，第二RC负载与第一RC负载的比值不小于0.95。
在一些示例中，多条信号线包括多条栅线，子像素200包括公共电极(后续描述801)，位于数据线远离衬底基板的一侧；第一区域101内，与一行子像素200电连接的栅线300和与其交叠的数据线600和公共电极801之间产生的电容的值为第一电容值C1；第二区域102内，与一行子像素200电连接的栅线300和与其交叠的数据线600和公共电极801之间产生的电容、与该栅线300电连接的一条信号线连接线400和与其交叠的交叠走线500之间产生的电容以及电容补偿结构700上的电容的总电容的值为第二电容值C2，第二电容值C2与第一电容值C1的比值为0.85～1。
例如，本公开实施例提供的显示基板中，每个像素单元可以包括像素电极以及薄膜晶体管，栅线与薄膜晶体管的栅极相连以控制薄膜晶体管的打开或者关闭，像素电极与薄膜晶体管的源漏极之一相连，数据线与薄膜晶体管的源漏极中的另一个相连，数据线通过薄膜晶体管对像素电极输入显示画面所需的电压信号以实现该阵列基板的显示。
图17为图1所示显示基板与图5所示显示基板中不同区域栅线上的电容值的关系图。如图17所示，线S1至线S4的横坐标表示栅线的数量，图中以57条栅线为例，线S1的纵坐标表示图2所示信号线连接线11与相应覆盖条13之间产生的电容的值与第三显示区内的栅线和其他层导电层(数据线和公共电极)之间产生的电容的值C02的比值，如不到20％；线S2的纵坐标表示图7所示信号线连接线400与交叠走线500之间产生的电容的值与第一区域内栅线和其他层导电层(数据线和公共电极)之间产生的电容的值的比值，如大于20％；线S3的纵坐标表示采用图2所示信号线连接线11与相应覆盖条13之间产生的电容值以及采用电容补偿结构16产生的电容共同对图1所示位于凹口两侧的第一显示区和第二显示区中相应栅线和其他层导电层之间产生的电容进行电容补偿后的电容的值C03与第三显示区内的栅线和其他层导电层之间产生的电容的值C02的比值，如小于70％，或小于80％；线S4的纵坐标表 示采用图7所示信号线连接线400与交叠走线500之间产生的电容以及采用图11所示电容补偿结构700产生的电容共同对第二区域内栅线和其他层导电层之间产生的电容进行电容补偿后的电容的值与第一区域内栅线和其他层导电层之间产生的电容的值的比值，如大于90％。
本公开提供的显示基板中，通过对第二区域的栅线上的电容进行补偿以使第二区域的栅线上的电容与第一区域的栅线上的电容比值大于90％，有利于降低第一区域和第二区域的RC负载差异，以降低显示差异。
例如，图5至图16所示的显示基板中的第一区域101内每条栅线300和其他层导电层之间产生的电容的值为C1，不同栅线300上的电容的值可以均相同。
例如，图1至图4所示显示基板中第三显示区的范围可以与图5至图16所示显示基板中第一区域内显示区的范围相同，图1至图4所示显示基板中第三显示区内的每条栅线和其他层导电层之间产生的电容的值C02与图5至图16所示显示基板中第一区域内每条栅线和其他层导电层之间产生的电容的值C1相同，则图5至图16所示显示基板中一条信号线连接线400和一条交叠走线500之间产生的电容的值大于图1至图4所示显示基板中一条信号线连接线11和相应覆盖条13之间产生的电容的值。
例如，如图17所示，采用图5至图16所示一条信号线连接线400与一条交叠走线500之间产生的电容以及采用图11所示电容补偿结构700产生的电容共同对第二区域内相应一条栅线(与上述一条信号线连接线和电容补偿结构电连接的栅线)和其他层导电层之间产生的电容进行电容补偿后的电容值与第一区域内每条栅线和其他层导电层之间产生的电容值的比值不小于90％，如在需要补偿至最大显示行数的RC负载时，第二区域内栅线上RC负载与第一区域内栅线上RC负载的90％以上，从而实现较好的显示效果。
本公开实施例提供的显示基板，通过将信号线连接线在交叠走线上的正投影设置为完全位于交叠走线内，可以极大地降低第二区域内栅线上RC负载与第一区域内栅线上RC负载之间的差异。
图18为沿图14所示的DD’线所截的局部截面结构示意图。在一些示例中，如图18所示，信号线连接线400和与其电连接的栅线300同层设置。例如，信号线连接线400和与其电连接的栅线300可以为一体化设置的结构。在信号线连接线400与栅线300为一体化设置的结构时，信号线连接线400也可以称 为栅线300的一部分。例如，信号线连接线400、连接部401均可以称为栅线300的一部分。
例如，如图14和图18所示，电容补偿结构700可以包括两层，一层与数据线600同层且间隔设置，另一层与栅线300同层且电连接设置。例如，例如，电容补偿结构700两侧设置有两部分连接部401。例如，电容补偿结构700位于栅线300同层的部分、栅线300、信号线连接线400以及连接部401可以为一体化设置的结构。
在一些示例中，如图14和图18所示，交叠走线500位于信号线连接线400远离衬底基板100的一侧。
在一些示例中，如图14和图18所示，交叠走线500与数据线600同层设置。例如，电容补偿结构700的一层、交叠走线500以及数据线600可以同层设置。当然，本公开实施例不限于此，电容补偿结构700还可以设置有位于数据线远离衬底基板一侧的一层膜层以进一步补偿第二区域的栅线的RC负载。
例如，如图18所示，栅线300与数据线600之间设置有绝缘层001，如栅极绝缘层001。例如，数据线400远离栅线300的一侧设置有绝缘层002，如钝化层002。
例如，如图18所示，子像素200包括公共电极801，位于数据线600远离衬底基板100的一侧。例如，图18示意性的示出公共电极801的位置，如D’位置左侧部分公共电极801可以为整层结构，D’位置右侧部分公共电极可以为网格状结构。例如，公共电极801与交叠走线500没有交叠。
例如，如图14和图18所示，显示基板还包括位于衬底基板100上的公共电极线802，公共电极线802被配置为与公共电极801电连接。例如，公共电极线802包括与数据线600同层设置的部分。例如，公共电极线802还可以包括与公共电极801同层设置的部分。
例如，如图6和图9所示，公共电极线可以为第一子区域1021和第二子区域1022之间的分界线。例如，公共电极线可以围绕第二子区域1022。例如，如图11所示，第一子区域1021远离显示区的一侧还设置有地线(GND)803。例如，公共电极线也可以围绕第一子区域1021和第二子区域1022构成的区域，如公共电极线位于第一子区域1021远离显示区一侧的部分的设置情况可以参考地线803的设置。
图19为根据本公开实施例的另一示例中沿图14所示的DD’线所截的局部 截面结构示意图。图19所示显示基板与图18所示显示基板的不同之处在于交叠走线500位于数据线600远离衬底基板100的一侧。
例如，如图19所示，交叠走线500可以与公共电极801同层设置。例如，交叠走线500可以与公共电极801采用相同的材料制作。例如，交叠走线500与公共电极801之间设置有间隔。例如，相邻交叠走线500之间设置有间隔。例如，公共电极也可以与交叠走线为一体化设置的结构，如交叠走线为整面的公共电极的一部分。
当然，本公开实施例不限于与信号线连接线400交叠的交叠走线500仅包括一层膜层，如信号线连接线400远离衬底基板100一侧可以设置两层交叠走线500，这两层交叠走线位置可以分别与图18和图19所示两层交叠走线的位置相同，即两层交叠走线500分别与数据线和公共电极同层设置。
图20为图11所示B7区域的局部放大图，图21为图11所示B8区域的局部放大图。在一些示例中，如图11、图16和图20所示，公共电极线802与交叠走线500电连接。
在一些示例中，如图11、图16和图20所示，公共电极线802位于第二区域的部分与交叠走线500同层设置，且公共电极线802的该部分位于交叠走线500与显示区之间，交叠走线500与公共电极线802的该部分一体化设置。
例如，如图11、图16和图20所示，以X方向的箭头所指的方向为向右为例，信号线连接线400向右侧延伸至公共电极线802以与位于公共电极线802右侧的栅线300电连接，覆盖该信号线连接线400的交叠走线500在向右侧延伸至公共电极线802，如在栅线300、连接部401与信号线连接线400为一体化结构时，公共电极线802可以作为栅线300与连接部401之间的分界线，和/或，连接部401与信号线连接线400之间的分界线。例如，公共电极线802以及交叠走线500可以均为相对于第一区域的沿Y方向延伸的中心线对称分布的结构，则图11示出了位于中心线右侧的部分，位于中心线左侧的部分可以参考位于中心线右侧的部分。
本公开实施例通过将信号线连接线与公共电极线电连接，可以降低公共电极整体阻抗。
例如，如图11所示，公共电极线802还包括位于电容补偿结构700远离交叠走线500一侧的部分，如该部分公共电极线802可以呈台阶形状，电容补偿结构700靠近交叠走线500一侧的部分可以呈弧形，当然，本公开实施例不 限于此，公共电极线的形状可以根据空间以及产品的需求进行设置。例如，交叠走线500可以与公共电极线802的呈弧形的部分电连接。例如，位于电容补偿结构700两侧的两部分公共电极线802的靠近第一区域的部分可以间隔分布。
在一些示例中，如图11和图21所示，显示基板还包括连接线501，连接线510的延伸方向与交叠走线500的延伸方向相交；连接线501被配置为将交叠走线500与公共电极线802位于第二区域的部分电连接；连接线501与交叠走线500和公共电极线802的至少之一同层设置。
例如，如图21所示，连接线501、交叠走线500以及公共电极线802均为同层设置的结构，连接线501和交叠走线500构成网格状结构，如公共电极线802的部分、连接线501以及交叠走线500为一体化设置的结构。例如，连接线501与公共电极线802中位于电容补偿结构700远离交叠走线500的部分电连接。
上述图20中信号线连接线与公共电极线一体化实现电连接的方式与设置连接线实现信号线连接线与公共电极线电连接的方式可以同时采用，也可以只采用其中之一。
图22为根据本公开实施例的另一示例提供的显示基板中的局部结构示意图，图23为沿图22所示EE’线所截的局部截面结构示意图。图22所示显示基板与图5至图21所示显示基板的不同之处在于交叠走线500和与其电连接的公共电极线802位于不同层。在一些示例中，如图22和图23所示，公共电极线802位于第二区域的部分与交叠走线500位于不同层，且两者之间设置有绝缘层003，交叠走线500通过位于绝缘层003中的过孔0031与公共电极线802的该部分电连接。例如，公共电极线802位于交叠走线500远离衬底基板100的一侧。例如，图23所示公共电极线802与公共电极位于同层，如公共电极线802与公共电极均为透明导电层。
例如，在本示例中，交叠走线500与公共电极线802所在膜层可以互换，如交叠走线500与公共电极同层设置，公共电极线802与数据线同层设置，交叠走线500通过其与公共电极线802之间的绝缘层中的过孔与公共电极线802电连接。
例如，在本示例中，显示基板可以包括图21所示的连接线，该连接线与公共电极线位于不同层，如连接线、交叠走线与数据线位于同层，公共电极线 与公共电极位于同层，或者连接线、交叠走线与公共电极位于同层，公共电极线与数据线位于同层，连接线通过位于其与公共电极线之间的过孔与公共电极线电连接。
例如，本示例中，交叠走线可以通过图22所示方式与公共电极线电连接，交叠走线也可以采用图21所示的连接线的方式与公共电极线电连接，或者交叠走线同时采用图22所示方式以及图21所示连接线的方式与公共电极线电连接。
图24为根据本公开实施例的另一示例提供的显示基板的局部平面结构示意图，图25至图27为沿图24所示FF’线所截的局部截面结构的不同示例的示意图。图24所示显示基板与图5所示显示基板的不同之处在于信号线连接线400和与其电连接的栅线300位于不同层。图24所示示例中的栅线、子像素、数据线、电容补偿结构、公共电极等结构可以与上述示例中的栅线、子像素、数据线、电容补偿结构、公共电极等结构具有相同的技术特征，在此不再赘述。
需要说明的是，由于信号线连接线与交叠走线重叠，图24仅示意性的示出信号线连接线400，没有示出交叠走线500。
例如，信号线连接线400位于栅线300远离衬底基板100的一侧。
在一些示例中，如图24至图26所示，信号线连接线400与数据线600同层设置。例如，信号线连接线400通过位于信号线连接线400与栅线300之间的栅极绝缘层001之间的过孔电连接。例如，信号线连接线400的材料与数据线600的材料相同。图25示意性的示出信号线连接线400通过位于信号线连接线400与栅线300之间的栅极绝缘层001之间的过孔直接与栅线300电连接，信号线连接线400还可以通过其他导电层与栅线转接，此时，信号线连接线400在衬底基板上的正投影仍完全位于交叠走线在衬底基板上的正投影内。
例如，交叠走线500位于信号线连接线400与衬底基板100之间。
在一些示例中，如图24和图25所示，交叠走线500与栅线300同层设置。例如，交叠走线500的材料与栅线300的材料相同。例如，交叠走线500与栅线300间隔设置。
例如，在交叠走线500与栅线300同层设置时，交叠走线500可以和与其同层设置的公共电极线电连接，交叠走线300也可以与位于数据线或者公共电极所在膜层的公共电极线电连接。
在一些示例中，如图24和图26所示，交叠走线500位于信号线连接线400 远离衬底基板100的一侧。例如，交叠走线500可以与公共电极801同层设置。例如，交叠走线500的材料可以与公共电极801的材料相同。
例如，在交叠走线500与公共电极801同层设置时，交叠走线500可以和与其同层设置的公共电极线电连接，交叠走线300也可以与位于数据线所在膜层的公共电极线电连接。
在一些示例中，如图24和图27所示，交叠走线500包括在垂直于衬底基板100的方向上分别位于信号线连接线400两侧的第一交叠走线510和第二交叠走线520；在垂直于衬底基板100的方向，第一交叠走线510和第二交叠走线520交叠，且信号线连接线400在衬底基板100上的正投影位于第一交叠走线510和第二交叠走线520至少之一在衬底基板100上的正投影内。
本公开实施例通过在显示基板中设置有与信号线连接线均交叠，且分别位于信号线连接线两侧的第一交叠走线和第二交叠走线，可以形成双层电容并联结构，从而最大化的信号线连接线与其他导电层之间形成的电容。采用本公开实施例提供的双层交叠走线的设置方式，可以进一步降低位于第二区域的栅线上的RC负载与第一区域的栅线上的RC负载差异，如位于第二区域的栅线上的RC负载与第一区域的栅线上的RC负载之比大于0.9，或者大于0.92，或者0.95，或者9.98。
在一些示例中，如图24和图27所示，信号线连接线400与数据线600同层设置，第一交叠走线510与第二交叠走线520之一与栅线300同层设置，第一交叠走线510与第二交叠走线520的另一个与公共电极801同层设置。
图28为根据本公开另一实施例提供的显示基板的平面示意图，图29为图28所示区域G1的部分结构示意图，图30为沿图29所示HH’线所截的局部截面结构示意图，图31为图28所示区域G2的部分结构示意图，图32为沿图31所示II’线所截的局部截面结构示意图。
如图28至图32所示，显示基板包括衬底基板100以及位于衬底基板100上的多个子像素200、多条信号线300以及多条信号线连接线400。衬底基板100包括第一区域101以及位于第一区域101周边的第二区域102。
如图28至图32所示，多个子像素200位于第一区域101和第二区域102，第一区域101内沿第一方向排列的子像素200的数量大于第二区域102内沿第一方向排列的子像素200的数量。例如，第一区域101内沿第一方向排列的一行子像素200或一列子像素200的数量大于第二区域102内沿第一方向排列的 一行子像素200或一列子像素200的数量。
如图28至图32所示，多条信号线300位于第一区域101和第二区域102，且每条信号线300的至少部分沿第一方向延伸，每条信号线300与沿第一方向排列的一行子像素200或一列子像素200电连接。
如图28至图32所示，多条信号线连接线400位于第二区域102，多条信号线连接线400被配置为与位于第二区域102的信号线300电连接，且每条信号线连接线500的至少部分沿第一方向延伸。
如图28至图32所示，显示基板还包括位于第二区域102的多条交叠走线500，多条交叠走线500间隔设置且与多条信号线连接线400位于不同层，一条信号线连接线400在衬底基板100上的正投影完全位于一条交叠走线500在衬底基板100上的正投影内。
本公开提供的显示基板中，通过将至少一条信号线连接线在衬底基板上的正投影设置为完全位于交叠走线在衬底基板上的正投影内，可以在尽量满足封框胶正对的显示基板中金属层的透光率的前提下，提高信号线连接线与交叠走线的交叠面积，从而对异形显示基板的第二区域内的信号线上的电阻-电容负载(RC负载)进行最大化的补偿以尽量避免异形显示基板中低灰阶画面显示不均现象的产生。
图28所示显示基板与图5所示显示基板的不同之处在于显示区104的形状，图5所示显示区104包括凹口，图28所示显示区104的形状可以为类似三角形。
例如，以图28所示第一方向为X方向，则信号线300为栅线，与位于第二区域102的沿X方向排列的一行子像素200电连接的栅线300上的RC负载和与位于第一区域101的沿X方向排列的一行子像素200电连接的栅线300上的RC负载之比大致为0.85之处作为第一区域101和第二区域102的分界位置。同理，以图28所示第一方向为Y方向，则信号线300为数据线，与位于第二区域102的沿Y方向排列的一列子像素200电连接的数据线上的RC负载和与位于第一区域101的沿Y方向排列的一列子像素200电连接的数据线上的RC负载之比大致为0.85之处作为第一区域101和第二区域102的分界位置。
例如，如图28至图32所示，第一方向可以为栅线300的延伸方向，此时信号线为栅线300，信号线连接线400与栅线300电连接，且信号线连接线400在衬底基板100上的正投影完全位于交叠走线500在衬底基板100上的正投影 内；或者，第一方向可以为数据线600的延伸方向，此时信号线为数据线600，信号线连接线400与数据线600电连接，且信号线连接线400在衬底基板100上的正投影完全位于交叠走线500在衬底基板100上的正投影内；或者，信号线包括数据线600和栅线300，信号线连接线400包括与数据线600电连接的数据线连接线，以及与栅线300电连接的栅线连接线，交叠走线500包括与数据线连接线交叠的部分，以及与栅线连接线交叠的部分。
例如，如图28至图32所示，信号线连接线400与栅线300电连接，信号线连接线400与栅线300同层设置，交叠走线500位于信号线连接线400远离衬底基板100的一侧。例如，信号线连接线400可以为与栅线300一体化设置的栅线300的延长线。
本示例中信号线连接线、栅线以及交叠走线的位置关系可以参见图5至图27所示实施例，在此不再赘述。
例如，如图28至图32所示，信号线连接线400与数据线600电连接。例如，信号线连接线400可以与数据线600同层设置，且为一体化设置的结构，交叠走线500可以位于信号线连接线400与衬底基板100之间，如与栅线300同层设置，交叠走线500也可以位于信号线连接线400远离衬底基板100的一侧，如与公共电极同层设置，或者交叠走线500包括位于信号线连接线400在垂直于衬底基板100的方向上的两侧的两层结构，且交叠走线500与公共电极线电连接。例如，交叠走线500可以与公共电极线同层且一体化设置以实现电连接，或者交叠走线500可以与公共电极线位于不同层且通过两者之间的绝缘层中的过孔实现电连接。例如，信号线连接线400可以为与数据线600一体化设置的数据线600的延长线。
例如，信号线连接线400可以与数据线600位于不同层，如位于数据线600靠近衬底基板100的一侧，如与栅线300同层设置，此时，交叠走线500位于信号线连接线400远离衬底基板100的一侧，如可以位于数据线600所在膜层或者位于公共电极所在膜层，或者包括位于数据线600所在膜层以及公共电极所在膜层两部分结构。
例如，信号线连接线400可以与数据线600位于不同层，如位于数据线600远离衬底基板100的一侧，如与公共电极同层设置，此时，交叠走线500位于信号线连接线400靠近衬底基板100的一侧，如可以位于数据线600所在膜层或者位于栅线所在膜层，或者包括位于数据线600所在膜层以及栅线所在膜层 两部分结构。
例如，交叠走线500与公共电极线电连接。
例如，图28所示显示基板中也可以设置图11所示显示基板中的电容补偿结构700。
本公开实施例提供的显示基板包括异形显示区，异形显示区不限于图5所示边缘具有凹口或者图28所示类似三角形的形状，还可以为圆形显示区、弧形显示区等异形形状。
本公开实施例提供一种显示装置，包括上述任一示例所示的显示基板。
例如，显示装置可以为液晶显示装置。
例如，本公开提供的显示基板可以为阵列基板，显示装置还包括与阵列基板对置设置的对置基板。例如，对置基板可以为彩膜基板。例如，彩膜基板面向阵列基板的一侧可以设置与像素单元对应的彩膜层以及覆盖栅线和数据线等位于非显示区的结构的黑矩阵。例如，阵列基板与彩膜基板之间设置有液晶层，公共电极被配置为施加公共电压以与像素电极产生驱动液晶层中的液晶分子偏转的电场。液晶分子通过发生偏转以改变液晶层的透过率，从而实现期望灰度图像的显示。
例如，显示装置还包括设置在阵列基板远离对置基板的一侧的第一偏光片和设置在对置基板远离阵列基板的一侧的第二偏光片。第一偏光片包括沿第一方向延伸的透光轴并使入射到其中的背光沿着第一方向偏振。第二偏光片包括沿第二方向延伸的透光轴并使入射到第二偏光片的光沿着第二方向偏振。例如，第一偏光片的透光轴和第二偏光片的透光轴彼此垂直。
例如，显示装置还包括位于显示基板非显示侧的背光源以为显示基板提供背光。
例如，显示装置中，第二区域的凹口处可以设置功能部件，功能部件包括相机模组(例如，前置摄像模组)、3D结构光模组(例如，3D结构光传感器)、飞行时间法3D成像模组(例如，飞行时间法传感器)、红外感测模组(例如，红外感测传感器)等至少之一。
例如，前置摄像模组通常在用户自拍或视频通话时启用，显示装置的像素显示区显示自拍所得到的图像供用户观看。前置摄像模组例如包括镜头、图像传感器、图像处理芯片等。
例如，3D结构光传感器和飞行时间法(Time of Flight，ToF)传感器可以 用于人脸识别以对显示装置进行解锁等。
例如，功能部件可以仅包括相机模组以实现自拍或者视频通话的功能；例如，该功能部件可以进一步包括3D结构光模组或者飞行时间法3D成像模组以实现人脸识别解锁等，本实施例包括但不限于此。
例如，该显示装置可以为具有屏下摄像头的手机、平板电脑、笔记本电脑、导航仪等任何具有显示功能的产品或者部件，本实施例不限于此。
有以下几点需要说明：
(1)本公开的实施例附图中，只涉及到与本公开实施例涉及到的结构，其他结构可参考通常设计。
(2)在不冲突的情况下，本公开的同一实施例及不同实施例中的特征可以相互组合。
以上所述仅是本公开的示范性实施方式，而非用于限制本公开的保护范围，本公开的保护范围由所附的权利要求确定。

Claims (24)

  1. 一种显示基板，包括：
    衬底基板，包括第一区域以及位于所述第一区域周边的第二区域；
    多个子像素，位于所述第一区域和所述第二区域，所述第一区域内沿第一方向排列的子像素的数量大于所述第二区域内沿所述第一方向排列的子像素的数量；
    多条信号线，位于所述第一区域和所述第二区域，且每条信号线的至少部分沿所述第一方向延伸，每条信号线与沿所述第一方向排列的一排子像素电连接；
    多条信号线连接线，位于所述第二区域，所述多条信号线连接线被配置为与位于所述第二区域的所述信号线电连接，且每条信号线连接线的至少部分沿所述第一方向延伸，
    其中，所述显示基板还包括位于所述第二区域的多条交叠走线，所述多条交叠走线间隔设置且与所述多条信号线连接线位于不同层，至少一条信号线连接线在所述衬底基板上的正投影完全位于至少一条交叠走线在所述衬底基板上的正投影内。
  2. 根据权利要求1所述的显示基板，其中，所述多条信号线包括多条栅线和多条数据线的至少一种。
  3. 根据权利要求1或2所述的显示基板，其中，所述交叠走线的延伸方向与所述信号线连接线的延伸方向相同，且所述交叠走线的线宽大于等于所述信号线连接线的线宽。
  4. 根据权利要求1-3任一项所述的显示基板，其中，所述多条交叠走线分别与所述多条信号线连接线一一对应设置，每条信号线连接线在所述衬底基板上的正投影完全位于对应设置的所述交叠走线在所述衬底基板上的正投影内，且相邻交叠走线之间的间隔不小于1.5微米。
  5. 根据权利要求1所述的显示基板，其中，所述信号线连接线和与其电连接的所述信号线同层设置。
  6. 根据权利要求5所述的显示基板，其中，所述交叠走线位于所述信号线连接线远离所述衬底基板的一侧。
  7. 根据权利要求5所述的显示基板，其中，所述多条信号线包括多条栅 线，所述显示基板还包括：
    多条数据线，位于所述多条栅线远离所述衬底基板的一侧，且每条数据线的至少部分沿第二方向延伸，所述第二方向与所述第一方向相交，
    其中，沿垂直于所述衬底基板的方向，所述数据线与所述信号线连接线不交叠，
    所述交叠走线与所述数据线同层设置；或者，所述交叠走线位于所述数据线远离所述衬底基板的一侧。
  8. 根据权利要求1所述的显示基板，其中，所述信号线连接线和与其电连接的所述信号线位于不同层。
  9. 根据权利要求8所述的显示基板，其中，所述多条信号线包括多条栅线，所述显示基板还包括：
    多条数据线，位于所述多条栅线远离所述衬底基板的一侧，且每条数据线的至少部分沿第二方向延伸，所述第二方向与所述第一方向相交，
    其中，沿垂直于所述衬底基板的方向，所述数据线与所述信号线连接线不交叠，所述信号线连接线与所述数据线同层设置。
  10. 根据权利要求9所述的显示基板，其中，所述交叠走线与所述栅线同层设置，或者，所述交叠走线位于所述信号线连接线远离所述衬底基板的一侧。
  11. 根据权利要求8所述的显示基板，其中，所述交叠走线包括在垂直于所述衬底基板的方向上分别位于所述信号线连接线两侧的第一交叠走线和第二交叠走线；在垂直于所述衬底基板的方向，所述第一交叠走线和所述第二交叠走线交叠，且所述信号线连接线在所述衬底基板上的正投影位于所述第一交叠走线和所述第二交叠走线至少之一在所述衬底基板上的正投影内。
  12. 根据权利要求10所述的显示基板，其中，所述多条信号线包括多条栅线，所述显示基板还包括：
    多条数据线，位于所述多条栅线远离所述衬底基板的一侧，且每条数据线的至少部分沿第二方向延伸，所述第二方向与所述第一方向相交，
    其中，所述子像素包括公共电极，位于所述数据线远离所述衬底基板的一侧，沿垂直于所述衬底基板的方向，所述数据线与所述信号线连接线不交叠，所述信号线连接线与所述数据线同层设置，所述第一交叠走线与所述第二交叠走线之一与所述栅线同层设置，所述第一交叠走线与所述第二交叠走线的另一个与所述公共电极同层设置。
  13. 根据权利要求1-4任一项所述的显示基板，其中，所述显示基板包括显示区和非显示区，所述第二区域包括所述显示区的一部分以及所述非显示区的一部分，且所述信号线连接线的至少部分位于所述非显示区。
  14. 根据权利要求13所述的显示基板，其中，所述信号线连接线与在第一方向上位于该信号线连接线至少一侧的所述信号线电连接，所述信号线连接线和与其电连接的所述信号线之间设置至少一个电容补偿结构，且所述电容补偿结构位于所述非显示区，所述电容补偿结构与分别位于其两侧的所述信号线和所述信号线连接线均电连接。
  15. 根据权利要求14所述的显示基板，其中，所述多条信号线包括多条栅线，所述显示基板还包括：多条数据线，位于所述多条栅线远离所述衬底基板的一侧，且每条数据线的至少部分沿第二方向延伸，所述第二方向与所述第一方向相交；
    所述子像素包括公共电极，位于所述数据线远离所述衬底基板的一侧；
    所述第一区域内，与一行子像素电连接的所述栅线和与其交叠的所述数据线和所述公共电极之间产生的电容的值为第一电容值；所述第二区域内，与一行子像素电连接的所述栅线和与其交叠的所述数据线和所述公共电极之间产生的电容、与该栅线电连接的一条信号线连接线和与其交叠的所述交叠走线之间产生的电容以及所述电容补偿结构上的电容的总电容的值为第二电容值，所述第二电容值与所述第一电容值的比值为0.85～1。
  16. 根据权利要求13-15任一项所述的显示基板，其中，所述至少一条信号线连接线沿着所述第二区域远离所述第一区域的部分边缘延伸。
  17. 根据权利要求14或15所述的显示基板，其中，所述第二区域内的所述非显示区包括第一子区域和第二子区域，所述第二子区域位于所述第一子区域与所述显示区之间，所述信号线连接线位于所述第一子区域，所述电容补偿结构位于所述第二子区域。
  18. 根据权利要求13或14所述的显示基板，其中，所述子像素包括公共电极，位于所述信号线远离所述衬底基板的一侧，
    其中，所述显示基板还包括位于所述衬底基板上的公共电极线，所述公共电极线被配置为与所述公共电极电连接，且所述公共电极线与所述交叠走线电连接。
  19. 根据权利要求18所述的显示基板，其中，所述公共电极线位于所述 第二区域的部分与所述交叠走线同层设置，且所述公共电极线的该部分位于所述交叠走线与所述显示区之间，所述交叠走线与所述公共电极线的该部分一体化设置。
  20. 根据权利要求18所述的显示基板，其中，所述公共电极线位于所述第二区域的部分与所述交叠走线位于不同层，且两者之间设置有绝缘层，所述交叠走线通过位于所述绝缘层中的过孔与所述公共电极线的该部分电连接。
  21. 根据权利要求18或19所述的显示基板，还包括：
    连接线，所述连接线的延伸方向与所述交叠走线的延伸方向相交；
    其中，所述连接线被配置为将所述交叠走线与所述公共电极线位于所述第二区域的部分电连接；
    所述连接线与所述交叠走线同层设置。
  22. 根据权利要求13所述的显示基板，其中，所述第二区域内的所述显示区包括沿所述第一方向排列的两个子显示区，所述两个子显示区之间设置有间隔以使所述第二区域远离所述第一区域的边缘形成凹口，所述显示基板包括位于所述非显示区域的封框胶区域，所述封框胶区域被配置为设置封框胶；
    所述信号线连接线包括位于所述两个子显示区之间且位于所述封框胶区域的部分，且所述信号线连接线被配置为连接分别位于所述两个子显示区的所述信号线。
  23. 根据权利要求22所述的显示基板，其中，所述至少一条信号线连接线沿着述凹口的至少部分边缘延伸。
  24. 一种显示装置，包括权利要求1-23任一项所述的显示基板。
PCT/CN2022/101070 2022-06-24 2022-06-24 显示基板以及显示装置 WO2023245610A1 (zh)

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CN107705756A (zh) * 2017-11-22 2018-02-16 武汉天马微电子有限公司 一种显示面板及显示装置
CN107966864A (zh) * 2017-12-15 2018-04-27 昆山龙腾光电有限公司 一种液晶显示装置
CN108598139A (zh) * 2018-06-26 2018-09-28 武汉天马微电子有限公司 显示面板及显示装置
CN109521594A (zh) * 2018-12-28 2019-03-26 厦门天马微电子有限公司 显示面板和显示装置
CN209560243U (zh) * 2019-03-12 2019-10-29 昆山龙腾光电有限公司 阵列基板、异形显示面板和显示装置
CN110459572A (zh) * 2019-08-19 2019-11-15 京东方科技集团股份有限公司 显示面板
CN114429959A (zh) * 2020-10-29 2022-05-03 京东方科技集团股份有限公司 显示基板及其制备方法、显示装置

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CN107301831A (zh) * 2016-04-15 2017-10-27 三星显示有限公司 显示装置
CN107705756A (zh) * 2017-11-22 2018-02-16 武汉天马微电子有限公司 一种显示面板及显示装置
CN107966864A (zh) * 2017-12-15 2018-04-27 昆山龙腾光电有限公司 一种液晶显示装置
CN108598139A (zh) * 2018-06-26 2018-09-28 武汉天马微电子有限公司 显示面板及显示装置
CN109521594A (zh) * 2018-12-28 2019-03-26 厦门天马微电子有限公司 显示面板和显示装置
CN209560243U (zh) * 2019-03-12 2019-10-29 昆山龙腾光电有限公司 阵列基板、异形显示面板和显示装置
CN110459572A (zh) * 2019-08-19 2019-11-15 京东方科技集团股份有限公司 显示面板
CN114429959A (zh) * 2020-10-29 2022-05-03 京东方科技集团股份有限公司 显示基板及其制备方法、显示装置

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