WO2023245531A1 - 一种显示面板、显示屏及电子设备 - Google Patents

一种显示面板、显示屏及电子设备 Download PDF

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Publication number
WO2023245531A1
WO2023245531A1 PCT/CN2022/100641 CN2022100641W WO2023245531A1 WO 2023245531 A1 WO2023245531 A1 WO 2023245531A1 CN 2022100641 W CN2022100641 W CN 2022100641W WO 2023245531 A1 WO2023245531 A1 WO 2023245531A1
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WIPO (PCT)
Prior art keywords
line
dummy
signal
lines
power signal
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PCT/CN2022/100641
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English (en)
French (fr)
Inventor
王玲
张林涛
Original Assignee
北京小米移动软件有限公司
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Filing date
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Application filed by 北京小米移动软件有限公司 filed Critical 北京小米移动软件有限公司
Priority to PCT/CN2022/100641 priority Critical patent/WO2023245531A1/zh
Priority to CN202280004327.9A priority patent/CN117751702A/zh
Publication of WO2023245531A1 publication Critical patent/WO2023245531A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body

Definitions

  • Embodiments of the present disclosure relate to, but are not limited to, a display panel, a display screen, and an electronic device.
  • the present disclosure provides a display panel, a display screen and an electronic device.
  • a display panel is provided.
  • a display area of the display panel has a central area and an edge area located outside the central area.
  • the display panel includes a plurality of data lines located in the display area. , a plurality of first power signal lines and a plurality of second power signal lines, wherein each data line located in the edge area is connected to the middle area through a signal line signal line, at least part of the signal line
  • the wiring corresponds to the position of the first power signal line
  • the conductive layer where the signal wiring and signal wiring is located also includes a dummy pattern, and the dummy pattern is spaced apart from the signal wiring and signal wiring.
  • At least part of the dummy pattern is electrically connected to the second power signal line.
  • the display panel includes a stacked first conductive layer, a second conductive layer and a third conductive layer,
  • the data lines are located on the first conductive layer and extend along a first direction.
  • the plurality of data lines are arranged at intervals along a second direction.
  • the first direction and the second direction are sandwiched. corner settings;
  • Each of the signal traces includes a first signal trace extending along the second direction and a second signal trace extending along the first direction.
  • the first signal trace extends along the first direction.
  • the signal trace is located on the second conductive layer, the second signal trace is located on the third conductive layer, and the first end of the first signal trace is located on the edge. area and connected to the corresponding data line through the first connection hole.
  • the second end of the first signal line and the second signal line are located in the middle area. The second end of the first signal line is connected to the second signal line through the second connection hole.
  • the dummy pattern includes a plurality of first dummy electrode lines and a plurality of second dummy electrode lines, wherein,
  • the plurality of first dummy electrode lines are located on the second conductive layer, and form a first pattern evenly distributed in the display area with the first signal wiring signal wiring;
  • the plurality of second dummy electrode lines are located on the third conductive layer, and form a second pattern evenly distributed in the display area with the second signal line signal line.
  • the plurality of second power signal lines are all connected to a second power signal bus, the second power signal bus is located on the second conductive layer, and at least part of the first dummy electrode line Connected to the second power signal bus.
  • the second power signal bus extends along the first direction, and in the second direction, the second power signal bus is located in a non-display area outside the display area,
  • the plurality of first dummy electrode lines include:
  • the first dummy sub-electrode line is collinear with the first signal trace and is located between the first signal trace and the second power signal bus;
  • the second dummy sub-electrode line is co-linear with the first signal trace and located on the side of the first signal trace away from the second power signal bus;
  • the third dummy sub-electrode line is parallel to the first signal line signal line;
  • the first dummy sub-electrode line and the third dummy sub-electrode line are both connected to the second power signal bus, and the second dummy sub-electrode line is connected to the first dummy sub-electrode line through a connection structure.
  • the third dummy sub-electrode line or the second dummy electrode line are both connected to the second power signal bus, and the second dummy sub-electrode line is connected to the first dummy sub-electrode line through a connection structure.
  • the plurality of first power signal lines are located on the first conductive layer, and the first power signal lines and the data lines are alternately arranged along the second direction;
  • Part of the second dummy electrode lines and part of the second signal traces correspond to the positions of the data lines in the middle area, and another part of the second dummy electrode lines and another part of the second signal traces
  • the signal wiring corresponds to the position of the first power signal line in the middle area.
  • each second dummy electrode line is connected to the intersecting first dummy electrode line through a third connection hole; or,
  • Part of the second dummy electrode lines is connected to the intersecting first dummy electrode lines through a third connection hole, and another part of the second dummy electrode lines is connected to the first power signal line through a fourth connection hole.
  • second dummy electrode lines connected to the first dummy electrode lines and second dummy electrode lines connected to the first power signal line are alternately arranged along the second direction.
  • the plurality of second dummy electrode lines include a fourth dummy sub-electrode line that is co-linear with the second signal line and a signal line that is co-linear with the second signal line.
  • Parallel fifth dummy sub-electrode lines, the second dummy sub-electrode line among the first dummy electrode lines is connected to the fourth dummy sub-electrode line through a connection structure.
  • the second dummy sub-electrode line is provided with the connection structure near an endpoint of the collinear first signal line signal line.
  • a display screen including the display panel as described in the first aspect.
  • an electronic device including the display screen as described in the second aspect.
  • the technical solution provided by the embodiments of the present disclosure may include the following beneficial effects: by electrically connecting at least part of the dummy pattern to the second power signal line, so that at least part of the dummy pattern is equivalent to the second power signal line, thereby reducing the number of data lines and the first power signal line.
  • the coupling capacitance between the power signal lines reduces the voltage fluctuation amplitude of the first power signal line when the data line signal jumps, thereby improving signal crosstalk and improving the display effect of the display panel.
  • Figure 1 is a schematic structural diagram of a display panel.
  • Figure 2 is a voltage change diagram of a display panel.
  • FIG. 3 is a schematic structural diagram of a display panel according to an exemplary embodiment.
  • FIG. 4 is a partial cross-sectional view along the A-A direction of the display panel according to an exemplary embodiment.
  • Figure 5 is a top view of the second conductive layer according to an exemplary embodiment.
  • FIG. 6 is a top view of the third conductive layer according to an exemplary embodiment.
  • FIG. 7 is a partial cross-sectional view along the B-B direction of the display panel according to an exemplary embodiment.
  • FIG 8 is a top view of the first conductive layer according to an exemplary embodiment.
  • FIG. 9 is a partial cross-sectional view of the display panel along the C-C direction according to an exemplary embodiment.
  • FIG. 10 is a schematic layout diagram of a display panel according to an exemplary embodiment.
  • FIG. 11 is a partial cross-sectional view along the C-C direction of the display panel according to an exemplary embodiment.
  • FIG. 12 is a schematic layout diagram of a display panel according to an exemplary embodiment.
  • FIG. 13 is a partial cross-sectional view along the D-D direction of the display panel according to an exemplary embodiment.
  • 100 display panel; 10: first conductive layer; 20: second conductive layer; 30: third conductive layer; 1: middle area; 2: edge area; 3: data line; 4: first power signal line; 5 : second power supply signal line; 6: signal wiring; 61: first signal wiring; 62: second signal wiring; 7: dummy pattern; 71: first dummy electrode line; 711: first dummy sub-electrode line ; 712: second dummy sub-electrode line; 713: third dummy sub-electrode line; 72: second dummy electrode line; 721: fourth dummy sub-electrode line; 722: fifth dummy sub-electrode line; 8: second power supply Signal bus; 91: first connection hole; 92: second connection hole; 93: third connection hole; 94: fourth connection hole; 11: connection structure.
  • the narrow borders of the left and right borders of the display panel have been realized, but the lower border of the display panel is affected by the data line winding and the area where the control chip is bound, and the edge width of the lower border is still large.
  • a flexible panel is usually used, and the area where the chip and the control chip are bound on the flexible panel is bent to the back of the display panel, thereby reducing part of the lower frame space, but the edge width of the lower frame is still relatively large. big.
  • data lines are routed into the display area to reduce the height of the fan-out area (Fanout), thereby reducing the display area.
  • the data line 3 (Data) in the edge area 2 of the display area is wound to In the middle area 1 of the display area, the first signal line 61 is connected to the data line 3, and the second signal line 62 forms a bonding connection with the Bending Area (binding area) on the edge of the display panel 100 and the driver IC, thereby achieving reduction in The width of the edge below the display area.
  • a dummy pattern 7 is provided on the conductive layer where the first signal trace 61 and the second signal trace 62 are provided, and the dummy pattern 7 is connected to the VDD line. .
  • the second signal trace 62 connected to the data line 3 since part of the second signal trace 62 connected to the data line 3 is located above the VDD line, there is a coupling capacitance between the signal trace 6 and the VDD line, so that there is a coupling capacitance between the data line 3 and the VDD line, and the dummy The pattern 7 is also connected to the VDD line, so the dummy pattern 7 is equivalent to the VDD line, so that there is a coupling capacitance between the dummy pattern 7 and the second signal line 62 , so that the coupling capacitance between the VDD line and the data line 3 is further increased. As shown in Figure 2, when the signal of the data line 3 jumps, the signal trace 6 connected to the data line 3 will also jump.
  • the voltage of the VDD line is affected by the coupling capacitance and fluctuates synchronously. Since the power IC is far away at the far end of the display panel 100, the voltage fluctuation is more severe than at the near end of the display panel 100, resulting in serious signal crosstalk. On the display panel 100, a bright line or a dark line will appear at the intersection of black and white blocks. , affecting the display effect.
  • the present disclosure provides a display panel.
  • the display area of the display panel has a middle area and an edge area located outside the middle area.
  • the display panel includes a plurality of data lines, a plurality of first power signal lines and a plurality of first power signal lines located in the display area.
  • the second power supply signal line wherein each data line located in the edge area is led to the middle area through a signal line, at least part of the signal line corresponds to the position of the first power signal line, and the conductive layer where the signal line is located also includes
  • the dummy pattern is provided separated from the signal trace, wherein at least part of the dummy pattern is electrically connected to the second power supply signal line.
  • FIG 3 is a schematic structural diagram of a display panel according to an exemplary embodiment.
  • an exemplary embodiment of the present disclosure provides a display panel 100.
  • the display area of the display panel 100 has a middle area 1 and Located in the edge area 2 outside the central area 1, the display panel 100 includes a plurality of data lines 3, a plurality of first power signal lines 4 and a plurality of second power signal lines 5 located in the display area, wherein each of the edge areas 2 is located in the edge area 2.
  • Each data line 3 is led to the middle area 1 through a signal line 6.
  • At least part of the signal line 6 corresponds to the position of the first power signal line 4.
  • the conductive layer where the signal line 6 is located also includes a dummy pattern 7.
  • the dummy pattern 7 It is separated from the signal trace 6 , wherein at least part of the dummy pattern 7 is electrically connected to the second power signal line 5 .
  • the display area refers to the image display area of the display panel 100
  • the Bending Area is an area of the non-display area of the display panel 100.
  • the multiple data lines 3 in the display area and the driver IC are in the Bending area. Area forms a Bending, that is, a connection, and the driver IC inputs a control signal to the data line 3 to control the pixels of the array in the display area, thereby realizing imaging of the display panel 100.
  • the display panel 100 may be a flexible display panel that can be bent and folded so that the non-display area can be bent to the back of the display area.
  • the display panel 100 includes a plurality of data lines 3 , a plurality of first power signal lines 4 and a plurality of second power signal lines 5 located in the display area.
  • the data lines 3 are used to transmit data signals, and the data lines 3 are connected to the plurality of second power signal lines 5 .
  • the scanning lines (not shown in the figure) cross each other and are insulated. The intersection of the data line 3 and the scanning line defines a sub-pixel, thereby forming a pixel array.
  • Various control signals related to the Bending Area scan drive are transmitted to the data lines 3 and The scan line and data line 3 drive the transistor to emit light according to the data signal, so that the display area of the display panel 100 displays the target image.
  • the first power signal line 4 may be a VDD power signal line, that is, a power signal line connected to the drain of the transistor to provide a drain voltage for the transistor.
  • the second power signal line 5 may be a VSS power signal line, that is, a power signal line connected to the source of the transistor to provide source voltage for the transistor.
  • the display area of the display panel 100 has a central area 1 and an edge area 2 located outside the central area 1.
  • the Bending Area is provided near the central area 1 of the display area to facilitate the transmission of control signals to the data lines 3 and scan lines. Since multiple data lines 3 are arranged in the display area of the display panel 100 according to certain rules, and the wiring area of the data lines 3 in the display area is larger than the area where the Bending Area is located, when the data lines 3 are connected from the display area to the Bending Area , the relatively scattered data lines 3 need to be concentrated. Therefore, the data lines 3 in the central area 1 can be connected to the driver IC in the Bending Area. Each data line 3 located in the edge area 2 is led to the middle through a signal trace 6 Area 1 is connected to the driver IC in the Bending Area to realize the transmission of data signals on data line 3 in edge area 2.
  • part of the signal traces 6 corresponds to the position of the first power signal line 4 , that is to say, the projection of part of the signal trace 6 coincides with the first power signal line 4 and coincides with the first power signal line 4 .
  • the routing direction and line shape of the part of the signal trace 6 corresponding to the position of the power signal line 4 is consistent with the first power signal line 4 to improve the structural performance and display performance uniformity of the display panel 100 and reduce the reflectivity difference.
  • the signal traces 6 may all correspond to the positions of the first power signal lines 4 to further improve the structural performance and display performance uniformity of the display panel 100 and reduce reflectivity differences.
  • the conductive layer where the signal trace 6 is located A dummy pattern 7 is also provided.
  • the dummy pattern 7 is separated from the signal trace 6 and is insulated from each other.
  • the dummy pattern 7 is not used to transmit electrical signals to the signal trace 6 .
  • the dummy pattern 7 improves the reflectivity difference caused by the difference in metal density and film thickness caused by the signal wiring 6 in some areas of the display area, thereby improving the screen color of the display panel 100 in the screen-off state. Uniformity.
  • At least part of the dummy patterns 7 is electrically connected to the second power signal line 5, and part of the dummy pattern 7 is equivalent to a VSS line.
  • the data line 3 and the first power signal line 4 The coupling capacitance is reduced, which reduces the voltage fluctuation amplitude of the first power signal line 4 when the data line 3 signal jumps, thereby improving signal crosstalk and achieving a good display effect of the display panel 100.
  • all dummy patterns 7 can also be electrically connected to the second power signal line 5 , and all dummy patterns 7 are VSS lines to further reduce the coupling capacitance between the data line 3 and the first power signal line 4 .
  • the voltage fluctuation amplitude of the first power signal line 4 when the data line 3 signal jumps reduces signal crosstalk and improves the display effect of the display panel 100 .
  • FIG. 3 only shows the lower part of the display panel 100 , and the data line 3 is shown as a solid line in FIG. 3 , and the middle part is shown in FIG. 3 .
  • Only two data lines 3 in area 1 are shown as an example, and only four data lines 3 in the edge areas 2 on both sides of the display area are shown as an example; only two first power signal lines 4 are shown as an example.
  • only two second power supply signal lines 5 are shown as an example; only four signal traces 6 are shown as an example.
  • the data line 3, the first power signal line 4, and the second power signal line 5 are distributed throughout the display panel 100 according to preset rules, and the signal wiring 6 is also based on the data lines in the edge area 2
  • the quantity of 3 is set for multiple items.
  • the data line 3 is shown as a solid line
  • the dummy pattern 7 is shown as a dotted line.
  • the solid line and the dotted line are not the actual forms of the signal lines, and are only for the purpose of distinction.
  • the actual forms of the plurality of data lines 3, the plurality of first power signal lines 4, the plurality of second power signal lines 5, the plurality of signal lines 6 and the dummy patterns 7 are strip-shaped metal lines for data transmission and Electrical signal transmission and other functions.
  • the data line 3 may be a Data line in the circuit design
  • the first power signal line 4 may be a VDD line in the circuit design
  • the second power signal line 5 may be a VSS line in the circuit design
  • the signal trace 6 In circuit design it can be SD line (Source&Drain line)
  • dummy pattern 7 can be dummy pattern in circuit design.
  • a plurality of data lines 3, a plurality of first power signal lines 4, a plurality of second power signal lines 5, a plurality of signal traces 6 and dummy patterns 7 are insulated from each other in the display area of the display panel 100.
  • the plurality of data lines 3 , the plurality of first power signal lines 4 , the plurality of second power signal lines 5 , the plurality of signal traces 6 and the dummy patterns 7 can be arranged on the initial substrate of the display panel 100 according to a certain application layout. Carry out layout design for the layout, and then form the above multiple lines on the initial substrate according to the layout design.
  • material formation techniques may be used to form on the initial substrate, such as chemical vapor deposition, electroless plating, electrolytic plating, printing, spin coating, spray coating, sputtering, or Vacuum deposition method (vacuum deposition) and so on.
  • the materials of the above multiple lines may be, for example, copper, aluminum, tungsten and other conductive materials.
  • the materials of the above multiple lines may be the same or different, and this disclosure does not limit this.
  • the display panel 100 includes a stacked first conductive layer 10 , a second conductive layer 20 and a third conductive layer 30 , wherein the data line 3 is located on the first conductive layer 10 , the second conductive layer 20 and the third conductive layer 30 .
  • the conductive layer 10 extends along the first direction, and the plurality of data lines 3 are arranged at intervals along the second direction, and are arranged at an angle between the first direction and the second direction; each signal line 6 includes a The extended first signal trace 61 and the second signal trace 62 extending along the first direction, the first signal trace 61 is located on the second conductive layer 20, the second signal trace 62 is located on the third conductive layer 30, the first The first end of the signal trace 61 is located in the edge area 2 and is connected to the corresponding data line 3 through the first connection hole 91. The second end of the first signal trace 61 and the second signal trace 62 are both located in the middle area 1. The second end of the first signal trace 61 is connected to the second signal trace 62 through the second connection hole 92 .
  • the first conductive layer 10 , the second conductive layer 20 and the third conductive layer 30 may be separated by an isolation layer, and the isolation layer is an insulating material.
  • the data line 3 is located on the first conductive layer 10.
  • the data line 3 may be formed on the first conductive layer 10 through material formation technology.
  • the data line 3 extends along the first direction on the first conductive layer 10, and the plurality of data lines 3 extend along the first conductive layer 10.
  • the data lines 3 are arranged at intervals in the second direction so that the plurality of data lines 3 are insulated from each other.
  • the first direction may be the Y direction in Figure 3
  • the second direction may be the X direction in Figure 3.
  • the first direction and the second direction are arranged at an included angle, and the included angle between the first direction and the second direction It can be 90°, so that the plurality of data lines 3 do not intersect with each other, and the plurality of data lines 3 transmit different display content data to achieve display imaging of the display panel 100 .
  • Each signal trace 6 includes a first signal trace 61 extending along the X direction and a second signal trace 62 extending along the Y direction.
  • the first signal trace 61 is located on the second conductive layer 20 and the second signal trace 62 extends along the X direction.
  • 62 is located on the third conductive layer 30.
  • the first signal trace 61 and the second signal trace 62 may be formed on the second conductive layer 20 and the third conductive layer 30 respectively through material formation technology.
  • the first signal trace 61 and the second signal trace 62 are located on different conductive layers, so that the wiring of the display panel 100 is reasonable and compact, which not only improves the production efficiency, but also improves the uniformity of the display performance of the display panel 100 .
  • the first signal trace 61 may be an SD1 line in the circuit design
  • the second signal trace 62 may be an SD2 line in the circuit design.
  • FIG. 4 exemplarily shows a certain data line 3 located in the edge area 2 and the first signal trace 61 and the second signal connected thereto in the display panel 100 , cut along the A-A direction in FIG. 3 A partial cross-sectional view of the trace 62.
  • the first end of the first signal trace 61 is located in the edge area 2 and is connected to the corresponding data line 3 through the first connection hole 91.
  • the first connection hole 91 may be etched in the first conductive layer.
  • the conductive material is then filled into the via hole through deposition to form a conductive via (conductive via), so that the electrical signal can be connected between the data line 3 and the first signal transmission between traces 61.
  • the second end of the first signal trace 61 and the second signal trace 62 are both located in the middle area 1.
  • the second end of the first signal trace 61 is connected to the second signal trace 62 through the second connection hole 92.
  • the connection hole 92 is formed in the isolation layer between the second conductive layer 20 and the third conductive layer 30, and its formation method can be the same as the formation method of the first connection hole 91, so that the electrical signal can be transmitted between the first signal trace 61 and the first connection hole 91.
  • the data line 3 located in the edge area 2 is connected to the first signal line 61 through the first connection hole 91, and the first signal line 61 is connected to the second signal line 62 provided in the middle area 1 through the second connection hole 92. , so that the data line 3 in the edge area 2 can be connected to the Bending Area, realizing the transmission of electrical signals between the data line 3 and the driving IC, so that the display panel 100 has a good imaging effect.
  • the first direction may be the X direction in FIG. 3
  • the second direction may be the Y direction in FIG. 3
  • the first direction may be any one between the X direction and the Y direction in FIG. 3 direction
  • the second direction is another direction with an angle of 90° to this direction, etc., as long as the plurality of data lines 3 do not intersect each other and are insulated from each other
  • the signal wiring 62 can be set accordingly, and this disclosure does not limit this.
  • the dummy pattern 7 includes a plurality of first dummy electrode lines 71 and a plurality of second dummy electrode lines 72 , wherein the plurality of first dummy electrode lines 71 are located on the second conductive layer 20 and are connected to the second dummy electrode line 71 .
  • a signal trace 61 forms a first pattern evenly distributed in the display area; a plurality of second dummy electrode lines 72 are located on the third conductive layer 30 and form a second pattern evenly distributed in the display area together with the second signal trace 62 .
  • the dummy pattern 7 includes a plurality of first dummy electrode lines 71 and a plurality of second dummy electrode lines 72 .
  • the first dummy electrode lines 71 and the second dummy electrode lines 72 are arranged according to the positions of the conductive layers of the dummy pattern 7 . Divide according to different extension and arrangement directions. Referring to FIG. 5 , FIG. 5 exemplarily shows a top view of the second conductive layer 20 .
  • a plurality of first dummy electrode lines 71 and first signal traces 61 are located in the second conductive layer 20 , and the first dummy electrodes
  • the line 71 extends in the same direction as the first signal line 61
  • the first dummy electrode line 71 is insulated from the first signal line 61 .
  • the plurality of first dummy electrode lines 71 and the first signal traces 61 form a first pattern evenly distributed in the display area.
  • the first pattern is, for example, the first dummy electrode lines 71 and the first signal traces evenly arranged along the Y direction.
  • the first dummy electrode line 71 may be an SD1 dummy line in circuit design, and is disposed on the same SD metal layer (Source & Drain Electrode) as the first signal line 61 (SD1 line), that is, the second conductive layer 20;
  • the two dummy electrode lines 72 may be SD2 dummy lines in circuit design, and are disposed on the same SD metal layer, that is, the third conductive layer 30, as the second signal line 62 (SD2 line).
  • FIG. 6 exemplarily shows a top view of the third conductive layer 30 .
  • the second dummy electrode line 72 and the second signal trace 62 are both located in the third conductive layer 30 , and the second dummy electrode line 72 In the same extending direction as the second signal trace 62 , the second dummy electrode line 72 is not used to transmit electrical signals to the second signal trace 62 .
  • the second dummy electrode lines 72 and the second signal traces 62 form a second pattern evenly distributed in the display area.
  • the second pattern is, for example, the second dummy electrode lines 72 and the second signal traces 62 evenly arranged along the X direction.
  • the reflectivity difference caused by the metal density difference and film thickness difference caused by the second signal trace 62 being provided in part of the third conductive layer 30 is improved, thereby improving the structural performance and display performance uniformity of the display panel 100 .
  • a plurality of second power signal lines 5 are connected to a second power signal bus 8 , and the second power signal bus 8 is located on the second conductive layer 20 , at least partially on the first dummy
  • the electrode line 71 is connected to the second power signal bus 8 .
  • the second power signal bus 8 can be located in the non-display area of the second conductive layer 20, the second power signal bus 8 can be connected to the Bending Area, and the plurality of second power signal lines 5 are connected to the second power signal Bus 8.
  • a plurality of second power signal lines 5 are provided on the second conductive layer 20 , at least part of the first dummy electrode lines 71 and the second power signal bus 8 connections.
  • the first dummy electrode line 71 is connected to the first power signal line 4, and the first dummy electrode line 71 is equivalent to the first power signal line 4, so that the first power signal line 4 and the second signal line are connected
  • the coupling capacitance between 62 causes the coupling capacitance between the data line 3 and the first power signal line 4 to increase.
  • part of the first dummy electrode lines 71 is connected to the second power signal bus 8, so that part of the first dummy electrode lines 71 is equivalent to the second power signal bus 8, thereby reducing the cost of the data line 3 and the first power signal bus.
  • the coupling capacitance between the first power signal line 4 reduces the voltage fluctuation amplitude of the first power signal line 4 when the data line 3 signal jumps, thereby improving signal crosstalk and achieving a good display effect of the display panel 100.
  • the plurality of first dummy electrode lines 71 can also all be connected to the second power signal bus 8 , and all the first dummy electrode lines 71 are equivalent to the second power signal bus 8 to further reduce the number of data lines 3 and The coupling capacitance of the first power signal line 4 further reduces the voltage fluctuation amplitude of the first power signal line 4 when the data line 3 signal jumps, weakens signal crosstalk, and improves the display effect of the display panel 100 .
  • the second power signal bus 8 extends along the first direction, and in the second direction, the second power signal bus 8 is located on at least one side of the display area, and multiple
  • the first dummy electrode line 71 includes a first dummy sub-electrode line 711, a second dummy sub-electrode line 712 and a third dummy sub-electrode line 713, wherein the first dummy sub-electrode line 711 is collinear with the first signal line 61 and Located between the first signal trace 61 and the second power signal bus 8 ; the second dummy sub-electrode line 712 is collinear with the first signal trace 61 and is located on the side of the first signal trace 61 away from the second power signal bus 8 On one side; the third dummy sub-electrode line 713 is parallel to the first signal trace 61; the first dummy sub-electrode line 711 and the third dummy sub
  • the second power signal bus 8 extends along the first direction, and the first direction is the Y direction. Since the plurality of second power signal lines 5 are connected to the second power signal bus 8, the first dummy electrode lines 71 and The second power signal bus 8 is connected, and the first dummy electrode line 71 and the second power signal line 5 are both provided on the second conductive layer 20.
  • the plurality of second power signal lines 5 extend along a second direction, and the second direction is the X direction, that is, the second power signal lines 5 extend in the same direction as the first dummy electrode lines 71 , and the second power signal lines 5 are
  • the dummy electrode lines 71 are alternately arranged along the first direction and are insulated from each other.
  • the second power signal bus 8 can be located on one side of the display area or on both sides of the display area, so that the first dummy electrode line 71 can be connected to the second power signal bus 8 .
  • the plurality of first dummy electrode lines 71 includes a plurality of first dummy sub-electrode lines 711 , a plurality of second dummy sub-electrode lines 712 and a plurality of third dummy sub-electrode lines 713 .
  • the first dummy sub-electrode line 711 , the second dummy sub-electrode line 712 and the third dummy sub-electrode line 713 are divided according to different positions and types of the first dummy electrode line 71 on the second conductive layer 20 .
  • the plurality of first dummy electrode lines 71 include a plurality of first dummy sub-electrode lines 711 .
  • the first dummy sub-electrode lines 711 are collinear with the corresponding first signal lines 61 and are insulated from each other.
  • the first dummy sub-electrodes Line 711 does not receive electrical signals.
  • the first dummy sub-electrode line 711 is located between the first signal trace 61 and the second power signal bus 8 , so that the area between the first signal trace 61 and the second power signal bus 8 in the second conductive layer 20 is The difference in metal density is reduced, thereby improving the film thickness and reflectivity uniformity of the display panel 100 .
  • the first dummy sub-electrode line 711 may be connected to the second power signal bus 8 so that the first dummy sub-electrode line 711 is equivalent to the second power signal bus 8 , thereby reducing the coupling between the data line 3 and the first power signal line 4
  • the capacitor reduces the voltage fluctuation amplitude of the first power signal line 4 when the data line 3 signal jumps, thereby improving signal crosstalk and achieving a good display effect of the display panel 100 .
  • first dummy sub-electrode lines 711 are a plurality of short lines between the first signal wiring 61 and the second power signal bus 8 in the display area, and each first dummy sub-electrode line 711 is related to the corresponding first A signal trace 61 is collinear and insulated, and is connected to the second power signal bus 8 .
  • the plurality of first dummy electrode lines 71 also include a plurality of second dummy sub-electrode lines 712.
  • the second dummy sub-electrode lines 712 are collinear with the corresponding first signal lines 61 and are insulated from each other.
  • the second dummy sub-electrode lines 712 are not Receive electrical signals.
  • the data lines 3 on both sides of the display area in the X direction are evenly arranged.
  • a plurality of first signal lines 61 extend along the The data line 3 is connected, and the other end is located in the middle area 1 and connected to the corresponding second signal line 62. Therefore, the first signal line 61 can also be evenly arranged in the X direction.
  • the first signal traces 61 on both sides of the display area in the The electrode lines 712 are located between the first signal traces 61 on both sides of the display area in the X direction, so that the metal density difference in the area of the second conductive layer 20 between the first signal traces 61 on both sides of the X direction is reduced.
  • the film thickness and reflectivity uniformity of the display panel 100 are improved.
  • the plurality of first dummy electrode lines 71 also include a plurality of third dummy sub-electrode lines 713.
  • the third dummy sub-electrode lines 713 are parallel to the first signal wiring 61.
  • the power signal bus 8 is connected so that the third dummy sub-electrode line 713 is equivalent to the second power signal bus 8, thereby reducing the coupling capacitance between the data line 3 and the first power signal line 4, and reducing the The voltage fluctuation amplitude of the power supply signal line 4 is thereby improved to improve signal crosstalk and achieve a good display effect of the display panel 100 .
  • a plurality of third dummy sub-electrode lines 713 parallel to the first signal traces 61 are provided, which improves the film thickness and reflectivity differences caused by the provision of the first signal traces 61 in some areas of the second conductive layer 20 situation, thereby improving the uniformity of the display performance of the display panel 100 .
  • Figure 7 is a partial cross-sectional view of the first dummy sub-electrode line 711 and the second dummy sub-electrode line 712 connected thereto along the B-B direction in Figure 3. In this embodiment, only the second conductive sub-electrode line is shown. A partial cross-sectional view of layer 20.
  • the second dummy sub-electrode line 712 can be connected to the first dummy sub-electrode line 711 through the connection structure 11.
  • the connection structure 11 is provided between the first conductive layer 10 and the second conductive layer 20. In the isolation layer between them, since the first signal line 61 and the data line 3 are connected through the first connection hole 91, the connection structure 11 bypasses the position of the first connection hole 91, that is, the connection structure 11 and the first connection hole
  • the projections of 91 on a plane parallel to the display panel 100 do not intersect, so that the first signal trace 61 transmits data content, and the second dummy sub-electrode line 712 can communicate with the second power signal bus 8 through the first dummy sub-electrode line 711
  • the indirect connection makes all the first dummy electrode lines 71 equivalent to the second power signal bus 8, thereby reducing the coupling capacitance between the data line 3 and the first power signal line 4, and reducing the first power signal when the data line 3 signal transitions.
  • the second dummy sub-electrode line 712 can also be connected to the third dummy sub-electrode line 713 through the connection structure 11 (not shown in the figure).
  • the connection structure 11 is disposed between the first conductive layer 10 and the second dummy sub-electrode line 713. In the isolation layer between the conductive layers 20, the connection structure 11 extends along the Y direction in FIG. 3, so that the second dummy sub-electrode line 712 can be indirectly connected to the second power signal bus 8 through the third dummy sub-electrode line 713, thereby
  • the coupling capacitance between the data line 3 and the first power signal line 4 is reduced, signal crosstalk is improved, and a good display effect of the display panel 100 is achieved.
  • the second dummy sub-electrode line 712 can also be connected to the second dummy electrode line 72 through the connection structure 11 (described in detail below).
  • the connection structure 11 is provided between the second conductive layer 20 and the third conductive layer. 30 in the isolation layer, so that the second dummy sub-electrode line 712 can be indirectly connected to the second power signal bus 8 or the first power signal line 4 through the second dummy electrode line 72, thereby reducing the connection between the data line 3 and the first power supply.
  • the coupling capacitance generated by the signal line 4 improves the crosstalk of the lines and achieves a good display effect of the display panel 100 .
  • connection structure 11 may be first etched to form a via hole inside the isolation layer between the first conductive layer 10 and the second conductive layer 20 or the isolation layer between the second conductive layer 20 and the third conductive layer 30 Then, the conductive material is filled into the via holes through deposition to form a conductive hole, so that the second dummy sub-electrode line 712 can be indirectly connected to the second power signal bus 8 or the first power signal line 4, thereby reducing the connection between the data line 3 and the first power signal line 4.
  • the coupling capacitance between the first power signal lines 4 improves signal crosstalk and achieves a good display effect of the display panel 100 .
  • a plurality of first power signal lines 4 are located on the first conductive layer 10 , and the first power signal lines 4 and the data lines 3 are alternately arranged along the second direction. ; Part of the second dummy electrode line 72 and part of the second signal trace 62 correspond to the position of the data line 3 in the middle region 1, and another part of the second dummy electrode line 72 and another part of the second signal trace 62 correspond to the position of the data line 3 in the middle region 1.
  • One power signal line corresponds to 4 positions.
  • the first power signal line 4 and the data line 3 are both provided on the first conductive layer 10 .
  • the first power signal lines 4 extend along the first direction, and the first direction is the Y direction, that is, the first power signal lines 4 and the data lines 3 extend in the same direction, and the first power signal lines 4 and the data lines 3 extend along the second direction.
  • the directions are arranged alternately to make the film thickness and metal density of the first conductive layer 10 uniform and reduce the difference in reflectivity.
  • the second dummy electrode line 72 and the second signal trace 62 are located in the third conductive layer 30
  • the first power signal line 4 and the data line 3 are located in the first conductive layer 10
  • the second dummy electrode line 72 and the second signal trace 62 extend in the same direction as the first power signal line 4 and the data line 3
  • the second signal trace 62 is located in the middle region 1 .
  • part of the second dummy electrode line 72 and part of the second signal trace 62 on the third conductive layer 30 correspond to the position of the data line 3 in the middle region 1
  • the other part is A part of the second dummy electrode lines 72 and another part of the second signal wiring 62 correspond to the positions of the first power signal lines 4 in the middle region 1 . That is to say, the projection of part of the second dummy electrode lines 72 and part of the second signal trace 62 on the first conductive layer 10 coincides with the data line 3 in the middle region 1, and the other part of the second dummy electrode line 72 and the other part of the second signal trace 62 overlap with the data line 3 in the middle region 1.
  • the projection of the two signal traces 62 on the first conductive layer 10 coincides with the first power signal line 4 in the middle region 1 .
  • the routing direction and line shape of the part of the second dummy electrode line 72 corresponding to the position of the data line 3 and the part of the second signal trace 62 are consistent with that of the data line 3 , and the other part of the second dummy electrode line 72 corresponding to the position of the first power signal line 4
  • the wiring directions and line shapes of the electrode lines 72 and another part of the second signal wiring 62 are consistent with the first power signal lines 4 to improve the structural performance and display performance uniformity of the display panel 100 and reduce reflectivity differences.
  • FIG. 9 shows the first dummy electrode line 71 and the second dummy electrode line 72 cut along the C-C direction in FIG. 3 according to an exemplary embodiment.
  • FIG. 10 is a schematic layout diagram of a display panel according to an exemplary embodiment. This embodiment shows a partial cross-sectional view of the second conductive layer 20 and the third conductive layer 30 . Each second dummy electrode line 72 is connected to the intersecting first dummy electrode line 71 through the third connection hole 93 .
  • the first dummy electrode line 71 is located in the second conductive layer 20 and extends in the first direction. Extending along the second direction, when the second conductive layer 20 and the third conductive layer 30 are stacked, the projection of each second dummy electrode line 72 on the second conductive layer 20 intersects with the plurality of first dummy electrode lines 71 point.
  • Each second dummy electrode line 72 is connected to the crossed first dummy electrode line 71 through a third connection hole 93 , and the third connection hole 93 is provided in the isolation layer between the second conductive layer 20 and the third conductive layer 30 , since the first dummy electrode line 71 is connected to the second power signal bus 8, the second dummy electrode line 72 can be indirectly connected to the second power signal bus 8 through the first dummy electrode line 71, so that all the second dummy electrode lines 72 are equivalent to the second power signal bus 8, thereby reducing the coupling capacitance between the data line 3 and the first power signal line 4, reducing the voltage fluctuation amplitude of the first power signal line 4 when the data line 3 signal jumps, and improving the signal crosstalk to achieve a good display effect of the display panel 100 .
  • the plurality of first dummy electrode lines 71 and the plurality of second dummy electrode lines 72 are connected to the second power signal bus 8.
  • the buses 8 are connected in parallel, thereby reducing the resistance of the second power signal bus 8 , thereby reducing the voltage drop, thereby reducing the power consumption of the display panel 100 .
  • FIG. 11 shows a second dummy electrode line 72 cut along the C-C direction in FIG. 3 connected to the first dummy electrode line 72 according to an exemplary embodiment. and a partial cross-sectional view of the first power signal line 4.
  • FIG. 12 is a schematic layout diagram of a display panel according to an exemplary embodiment. Part of the second dummy electrode lines 72 is connected to the intersecting first dummy electrode lines 71 through the third connection hole 93 , and another part of the second dummy electrode line 72 is connected to the first power signal line 4 through the fourth connection hole 94 .
  • the part of the second dummy electrode line 72 connected to the intersecting first dummy electrode line 71 through the third connection hole 93 corresponds to the position of the data line 3, and is connected to the first power signal line 4 through the fourth connection hole 94.
  • the other part of the connected second dummy electrode line 72 corresponds to the position of the first power signal line 4, so that the wiring layout inside the display panel 100 is reasonable and facilitates production.
  • the fourth connection hole 94 is provided in the isolation layer between the first conductive layer 10 and the third conductive layer 30 so that the second dummy electrode line 72 can be connected to the first power signal line 4 .
  • the first power signal line 4 is reduced and the resistance of the second power signal bus 8 to reduce the power consumption of the display panel 100 .
  • part of the second dummy electrode line 72 is connected to the second power signal bus 8
  • part of the second dummy electrode line 72 is equivalent to the second power signal bus 8, thereby reducing the interference between the data line 3 and the first power signal line 4.
  • the coupling capacitor reduces the voltage fluctuation amplitude of the first power signal line 4 when the data line 3 signal jumps, thereby improving signal crosstalk and achieving a good display effect of the display panel 100 .
  • the second dummy electrode line 72 connected to the first dummy electrode line 71 corresponds to the position of the data line 3
  • the second dummy electrode line 72 connected to the first power signal line 4 corresponds to the position of the data line 3 .
  • the positions of the first power signal lines 4 correspond to each other, and since the data lines 3 and the first power signal lines 4 are alternately arranged along the second direction on the first conductive layer 10 , the second power signal lines connected to the first dummy electrode lines 71
  • the dummy electrode lines 72 and the second dummy electrode lines 72 connected to the first power signal line 4 are alternately arranged along the second direction on the third conductive layer 30 so that the film thickness and metal density of the third conductive layer 30 are uniform. The difference in reflectivity of the display panel 100 is reduced.
  • the plurality of second dummy electrode lines 72 include a fourth dummy sub-electrode line 721 co-linear with the second signal trace 62 and a second dummy sub-electrode line 721 with the second signal trace 62 .
  • the signal wiring 62 is parallel to the fifth dummy sub-electrode line 722
  • the second dummy sub-electrode line 712 among the first dummy electrode lines 71 is connected to the fourth dummy sub-electrode line 721 through the connection structure 11 .
  • the lines 61 together form a second pattern evenly distributed on the third conductive layer 30, which improves the metal density difference and film thickness difference caused by the second signal trace 62 being provided in some areas of the third conductive layer 30, and reduces reflection. The rate difference is improved, thereby improving the structural performance and display performance uniformity of the display panel 100.
  • the fourth dummy sub-electrode line 721 may be connected to the intersecting third dummy sub-electrode line 713 or the second dummy sub-electrode line 712.
  • the combination 9 , the fourth dummy sub-electrode line 721 and the third dummy sub-electrode line 713 can be connected through the third connection hole 93 , so that the fourth dummy sub-electrode line 721 is indirectly connected to the second power signal bus 8 .
  • the fourth dummy sub-electrode line 721 and the second signal trace 62 are co-linear and insulated from each other, the second dummy sub-electrode line 712 and the first signal trace 61 are co-linear and insulated from each other, and the second dummy sub-electrode line 712 and the first signal trace 61 are co-linear and insulated from each other.
  • a signal trace 61 and a second signal trace 62 are connected through the second connection hole 92 .
  • Figure 13 is the fourth dummy sub-electrode line 721 and the second dummy sub-electrode line 712 cut along the D-D direction in Figure 3
  • this embodiment only shows the partial cross-sectional view of the second conductive layer 20 and the third conductive layer 30 .
  • the second dummy sub-electrode line 712 is provided with the connection structure 11 near the end point of the collinear first signal trace 61 , that is to say, the connection structure 11 and the second connection hole 92 are on a plane parallel to the display panel 100
  • the projections do not overlap or intersect, so that the fourth dummy sub-electrode line 721 is connected to the second dummy sub-electrode line 712 through the connection structure 11, and the second dummy sub-electrode line 712 is connected to the second power signal through the first dummy sub-electrode line 711.
  • the bus 8 is connected, so that the fourth dummy sub-electrode line 721 is indirectly connected to the second power signal bus 8, so that the fourth dummy sub-electrode line 721 is equivalent to the second power signal bus 8, thereby reducing the data line 3 and the first power signal
  • the coupling capacitance between the lines 4 reduces the voltage fluctuation amplitude of the first power signal line 4 when the signal of the data line 3 jumps, improves signal crosstalk, and enhances the display performance of the display panel 100 .
  • the present disclosure provides a display screen, which includes the above-mentioned display panel 100, so that signal crosstalk in the display screen can be improved and the display effect of the display screen can be improved.
  • the display screen may also include a touch control layer, and the touch control layer may be arranged in close contact with the display panel 100 so that the display screen can implement a touch control function.
  • the display screen may be an LCD (Liquid Crystal Display) display screen or an OLED (Organic Light-Emitting Diode, organic light-emitting diode) display screen.
  • the present disclosure also provides an electronic device.
  • the electronic device includes the above-mentioned display screen, so that signal crosstalk of the electronic device can be improved and the display effect of the electronic device can be improved.
  • the electronic device may be, for example, a terminal device that needs to achieve narrow bezels, and may include, for example, a smartphone, a full-screen mobile phone, a tablet computer, and the like.
  • At least part of the dummy pattern is electrically connected to the second power signal line, so that at least part of the dummy pattern is equivalent to the second power signal line, thereby reducing the coupling capacitance between the data line and the first power signal line, reducing the data line
  • the voltage fluctuation amplitude of the first power signal line when the signal jumps is improved, thereby improving signal crosstalk and improving the display effect of the display panel.

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Abstract

本公开是关于一种显示面板，显示面板的显示区具有中部区域以及位于中部区域外侧的边缘区域，显示面板包括位于显示区的多条数据线、多条第一电源信号线以及多条第二电源信号线，其中，位于边缘区域的每一条数据线均通过一信号走线引至中部区域，至少部分信号走线与第一电源信号线位置对应，信号走线所在的导电层还包括虚设图案，虚设图案与信号走线隔开设置，其中，至少部分虚设图案与第二电源信号线电连接。

Description

一种显示面板、显示屏及电子设备 技术领域
本公开实施例涉及但不限于一种显示面板、显示屏及电子设备。
背景技术
随着科技的发展，终端设备成为人们日常生活中不可或缺的部分，用户在追求终端设备更优质的显示效果的同时，对显示区的屏占比的要求也在提高。目前，显示面板的左右边框的窄边框已经实现，但显示面板的下边框受到数据线绕线以及绑定控制芯片的区域的影响，下边框的边缘宽度还是较大。
发明内容
为克服相关技术中存在的问题，本公开提供一种显示面板、显示屏及电子设备。
根据本公开的第一方面，提供一种显示面板，所述显示面板的显示区具有中部区域以及位于所述中部区域外侧的边缘区域，所述显示面板包括位于所述显示区的多条数据线、多条第一电源信号线以及多条第二电源信号线，其中，位于所述边缘区域的每一条数据线均通过一信号走线信号走线连接至所述中部区域，至少部分所述信号走线与所述第一电源信号线位置对应，所述信号走线信号走线所在的导电层还包括虚设图案，所述虚设图案与所述信号走线信号走线隔开设置，
其中，至少部分所述虚设图案与所述第二电源信号线电连接。
本公开的一些实施例中，所述显示面板包括层叠设置的第一导电层、第二导电层和第三导电层，
其中，所述数据线位于所述第一导电层，并沿第一方向延伸，所述多条数据线沿第二方向间隔排布，所述第一方向与所述第二方向之间呈夹角设置；
每一条所述信号走线信号走线均包括沿所述第二方向延伸的第一信号走线信号走线和沿所述第一方向延伸的第二信号走线信号走线，所述第一信号走线信号走线位于所述第二导电层，所述第二信号走线信号走线位于所述第三导电层，所述第一信号走线信号走线的第一端位于所述边缘区域并通过第一连接孔与对应的所述数据线连接，所述第一信号走线信号走线的第二端以及所述第二信号走线信号走线均位于所述中部区域，所述第一信号走线信号走线 的第二端通过第二连接孔与所述第二信号走线信号走线连接。
本公开的一些实施例中，所述虚设图案包括多条第一虚设电极线和多条第二虚设电极线，其中，
所述多条第一虚设电极线位于所述第二导电层，并与所述第一信号走线信号走线形成均布于所述显示区的第一图案；
所述多条第二虚设电极线位于所述第三导电层，并与所述第二信号走线信号走线形成均布于所述显示区的第二图案。
本公开的一些实施例中，所述多条第二电源信号线均连接至第二电源信号总线，所述第二电源信号总线位于所述第二导电层，至少部分所述第一虚设电极线与所述第二电源信号总线连接。
本公开的一些实施例中，所述第二电源信号总线沿所述第一方向延伸，且在所述第二方向上，所述第二电源信号总线位于所述显示区外侧的非显示区，所述多条第一虚设电极线包括：
第一虚设子电极线，与所述第一信号走线信号走线共线且位于所述第一信号走线信号走线与所述第二电源信号总线之间；
第二虚设子电极线，与所述第一信号走线信号走线共线且位于所述第一信号走线信号走线的远离所述第二电源信号总线的一侧；
第三虚设子电极线，与所述第一信号走线信号走线平行；
所述第一虚设子电极线和所述第三虚设子电极线均与所述第二电源信号总线连接，所述第二虚设子电极线通过连接结构连接至所述第一虚设子电极线、所述第三虚设子电极线或者所述第二虚设电极线。
本公开的一些实施例中，所述多条第一电源信号线位于所述第一导电层，且所述第一电源信号线与所述数据线沿所述第二方向交替排布；
部分所述第二虚设电极线以及部分所述第二信号走线信号走线与所述中部区域的数据线位置对应，另一部分所述第二拟电极线以及另一部分所述第二信号走线信号走线与所述中部区域的第一电源信号线位置对应。
本公开的一些实施例中，每条所述第二虚设电极线均通过第三连接孔与交叉的所述第一虚设电极线连接；或者，
部分所述第二虚设电极线通过第三连接孔与交叉的所述第一虚设电极线连接，另一部分所述第二虚设电极线通过第四连接孔与所述第一电源信号线连接。
本公开的一些实施例中，与所述第一虚设电极线连接的第二虚设电极线以及与所述第一电源信号线连接的第二虚设电极线沿所述第二方向交替排布。
本公开的一些实施例中，所述多条第二虚设电极线包括与所述第二信号走线信号走线共线的第四虚设子电极线以及与所述第二信号走线信号走线平行的第五虚设子电极线，所述第一虚设电极线中的第二虚设子电极线通过连接结构与所述第四虚设子电极线连接。
本公开的一些实施例中，所述第二虚设子电极线在靠近共线的第一信号走线信号走线的端点处设置所述连接结构。
根据本公开的第二方面，提供一种显示屏，包括如第一方面所述的显示面板。
根据本公开的第三方面，提供一种电子设备，包括如第二方面所述的显示屏。
本公开的实施例提供的技术方案可以包括以下有益效果：通过将至少部分虚设图案与第二电源信号线电连接，使得至少部分虚设图案相当于第二电源信号线，从而降低数据线和第一电源信号线之间的耦合电容，降低数据线信号跳变时第一电源信号线的电压波动幅度，从而改善信号串扰，提高显示面板的显示效果。
应当理解的是，以上的一般描述和后文的细节描述仅是示例性和解释性的，并不能限制本公开。
附图说明
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合本发明的实施例，并与说明书一起用于解释本发明的原理。
图1是一种显示面板的结构示意图。
图2是一种显示面板的电压变化图。
图3是根据一示例性实施例示出的一种显示面板的结构示意图。
图4是根据一示例性实施例示出的显示面板沿A-A方向的局部剖视图。
图5是根据一示例性实施例示出的第二导电层的俯视图。
图6是根据一示例性实施例示出的第三导电层的俯视图。
图7是根据一示例性实施例示出的显示面板沿B-B方向的局部剖视图。
图8是根据一示例性实施例示出的第一导电层的俯视图。
图9是根据一示例性实施例示出的显示面板沿C-C方向的局部剖视图。
图10是根据一示例性实施例示出的显示面板的版图示意图。
图11是根据一示例性实施例示出的显示面板沿C-C方向的局部剖视图。
图12是根据一示例性实施例示出的显示面板的版图示意图。
图13是根据一示例性实施例示出的显示面板沿D-D方向的局部剖视图。
附图说明：
100：显示面板；10：第一导电层；20：第二导电层；30：第三导电层；1：中部区域；2：边缘区域；3：数据线；4：第一电源信号线；5：第二电源信号线；6：信号走线；61：第一信号走线；62：第二信号走线；7：虚设图案；71：第一虚设电极线；711：第一虚设子电极线；712：第二虚设子电极线；713：第三虚设子电极线；72：第二拟电极线；721：第四虚设子电极线；722：第五虚设子电极线；8：第二电源信号总线；91：第一连接孔；92：第二连接孔；93：第三连接孔；94：第四连接孔；11：连接结构。
具体实施方式
这里将详细地对示例性实施例进行说明，其示例表示在附图中。下面的描述涉及附图时，除非另有表示，不同附图中的相同数字表示相同或相似的要素。以下示例性实施例中所描述的实施方式并不代表与本发明相一致的所有实施方式。相反，它们仅是与如所附权利要求书中所详述的、本发明的一些方面相一致的装置和方法的例子。
目前，显示面板的左右边框的窄边框已经实现，但显示面板的下边框受到数据线绕线以及绑定控制芯片的区域的影响，下边框的边缘宽度还是较大。为了减小显示区下方的边缘宽度，通常采用柔性面板，并将柔性面板上芯片及绑定控制芯片的区域弯折至显示面板的背面，减少一部分下边框空间，但下边框的边缘宽度还是较大。
为了进一步减小显示区下方的边缘宽度，实现四边框等宽设计，相关技术中，通过将数据线绕线布局至显示区内，缩减扇出区(Fanout)的高度，从而减小了显示区下方的边缘宽度，参见图1所示，显示面板100中，通过将显示区的边缘区域2的数据线3(Data)通过相连的第一信号走线61和第二信号走线62绕线至显示区的中部区域1，第一信号走线61与数据线3连接，第二信号走线62与显示面板100边缘的Bending Area(绑定区)与驱动IC形成绑定连接，从而实现减小显示区下方的边缘宽度。同时，为了避免金属密度差异造成的显示面板100熄屏时的反射率差异，在设置第一信号走线61和第二信号走线62的导电层设置虚设图案7，虚设图案7与VDD线连接。
但是，由于部分与数据线3连接的第二信号走线62位于VDD线的上方，信号走线6与VDD线之间具有耦合电容，使得数据线3与VDD线之间具有耦合电容，而虚设图案7也与VDD线连接，则虚设图案7相当于是VDD线，使得虚设图案7与第二信号走线62之间具有 耦合电容，从而VDD线和数据线3的耦合电容进一步增大。参见图2所示，当数据线3的信号跳变时，与数据线3相连的信号走线6也会发生跳变，VDD线的电压受耦合电容的影响从而同步产生波动。显示面板100的远端由于功率IC较远，因而电压波动比显示面板100的近端更严重，从而导致信号串扰严重，在显示面板100上表现为，黑白块交接处会出现一条亮线或者暗线，影响显示效果。
基于此，本公开提供一种显示面板，显示面板的显示区具有中部区域以及位于中部区域外侧的边缘区域，显示面板包括位于显示区的多条数据线、多条第一电源信号线以及多条第二电源信号线，其中，位于边缘区域的每一条数据线均通过一信号走线引至中部区域，至少部分信号走线与第一电源信号线位置对应，信号走线所在的导电层还包括虚设图案，虚设图案与信号走线隔开设置，其中，至少部分虚设图案与第二电源信号线电连接。通过将至少部分虚设图案与第二电源信号线电连接，使得数据线和第一电源信号线的耦合电容减小，减弱信号串扰。
图3是根据一示例性实施例示出的一种显示面板的结构示意图，如图3所示，本公开一示例性实施例提供一种显示面板100，显示面板100的显示区具有中部区域1以及位于中部区域1外侧的边缘区域2，显示面板100包括位于显示区的多条数据线3、多条第一电源信号线4以及多条第二电源信号线5，其中，位于边缘区域2的每一条数据线3均通过一信号走线6引至中部区域1，至少部分信号走线6与第一电源信号线4位置对应，信号走线6所在的导电层还包括虚设图案7，虚设图案7与信号走线6隔开设置，其中，至少部分虚设图案7与第二电源信号线5电连接。
本实施例中，显示区是指显示面板100的图像显示区域，Bending Area(绑定区)为显示面板100的非显示区的一个区域，显示区中的多条数据线3与驱动IC在Bending Area形成Bending，也就是连接，驱动IC向数据线3输入控制信号，控制显示区中阵列的像素，从而实现显示面板100的成像。显示面板100可以是柔性显示面板，柔性显示面板可弯曲和折叠，使得非显示区可以弯折至显示区的背面。
显示面板100包括位于显示区的多条数据线3、多条第一电源信号线4以及多条第二电源信号线5，其中，数据线3用于传输数据信号，多条数据线3与多条扫描线(图中未示出)相互交叉且绝缘设置，数据线3与扫描线交叉处限定一个子像素，进而构成像素阵列，Bending Area扫描驱动相关的各种控制信号传输至数据线3和扫描线，数据线3根据数据信号驱动晶体管发光，使得显示面板100的显示区显示目标图像。第一电源信号线4可以是VDD电源信号线，即连接至晶体管的漏极(Drain)的电源信号线，为晶体管提供漏极电压。第二电源 信号线5可以是VSS电源信号线，即连接至晶体管的源极(Source)的电源信号线，为晶体管提供源极电压。
显示面板100的显示区具有中部区域1以及位于中部区域1外侧的边缘区域2，Bending Area设置于靠近显示区的中部区域1，以便于向数据线3和扫描线传输控制信号。由于多条数据线3是按一定规则排布在显示面板100的显示区，且数据线3在显示区中的布线区域比Bending Area所在的区域大，数据线3从显示区与Bending Area连接时，需要将相对分散的数据线3集中，因此，中部区域1的数据线3可以在Bending Area与驱动IC形成连接，位于边缘区域2的每一条数据线3均通过一信号走线6引至中部区域1，在Bending Area与驱动IC连接，从而实现边缘区域2的数据线3的数据信号的传输。
一些实施例中，信号走线6中的部分信号走线6与第一电源信号线4的位置对应，也就是说，部分信号走线6的投影与第一电源信号线4重合，与第一电源信号线4位置对应的部分信号走线6的走线方向及线路形状与第一电源信号线4一致，以提升显示面板100的结构性能和显示性能的均一性，降低反射率差异。
另一些实施例中，信号走线6也可以全部与第一电源信号线4的位置对应，以进一步提升显示面板100的结构性能和显示性能的均一性，降低反射率差异。
为了保证显示面板100的结构性能和电学性能，避免金属密度差异和膜层厚度差异造成显示面板100的熄屏反射率差异，本实施例提供的显示面板100中，信号走线6所在的导电层还设置了虚设图案(dummy pattern)7，虚设图案7与信号走线6隔开设置，相互绝缘，且虚设图案7不用于向信号走线6传输电信号。虚设图案7改善了显示区的部分区域设置了信号走线6产生的金属密度有差异、膜层厚度有差异而导致的反射率差异的情况，从而提高显示面板100的熄屏状态下的屏幕颜色均一性。
一些实施例中，虚设图案7中的至少部分虚设图案7与第二电源信号线5电连接，部分虚设图案7相当于是VSS线，相对于现有技术，数据线3和第一电源信号线4的耦合电容减小，降低数据线3信号跳变时第一电源信号线4的电压波动幅度，从而改善信号串扰，实现显示面板100良好的显示效果。
另一些实施例中，虚设图案7也可以全部与第二电源信号线5电连接，所有虚设图案7都是VSS线，以进一步降低数据线3和第一电源信号线4的耦合电容，进一步降低数据线3信号跳变时第一电源信号线4的电压波动幅度，减弱信号串扰，提升显示面板100的显示效果。
需要说明的是，由于信号线较多，为了图3中可以清楚的示出各信号线，图3仅示出了 显示面板100的下部，数据线3在图3中以实线示出，中部区域1的数据线3仅示例性地示出两条，显示区两侧的边缘区域2中的数据线3仅示例性地各示出四条；第一电源信号线4仅示例性地示出两条；第二电源信号线5仅示例性地示出两条；信号走线6仅示例性地示出四条。在实际的设计及生产过程中，数据线3、第一电源信号线4、第二电源信号线5是按照预设规则遍布于显示面板100的，信号走线6也是根据边缘区域2的数据线3的数量设置多条的。此外，数据线3以实线示出，虚设图案7以虚线示出，实线和虚线并不是信号线的实际形态，仅以区分为目的。多条数据线3、多条第一电源信号线4、多条第二电源信号线5、多条信号走线6和虚设图案7的实际形态为条状的金属线条，以起到数据传输及电信号传输等作用。
示例性地，数据线3在电路设计中可以是Data line，第一电源信号线4在电路设计中可以是VDD line，第二电源信号线5在电路设计中可以是VSS line，信号走线6在电路设计中可以是SD line(Source&Drain line)，虚设图案7在电路设计中可以是dummy pattern。
本实施例中，多条数据线3、多条第一电源信号线4、多条第二电源信号线5、多条信号走线6和虚设图案7在显示面板100的显示区相互绝缘设置，且可以在显示面板100的初始基板上依照一定的应用布局对多条数据线3、多条第一电源信号线4、多条第二电源信号线5、多条信号走线6和虚设图案7的排布进行版图设计，然后依照版图设计在初始基板上形成以上多条线路。例如，可以采用材料形成技术在初始基板上形成，材料形成技术例如是化学气相沉积、无电镀法(electroless plating)、电解电镀(electrolytic plating)、印刷、旋涂、喷涂、溅镀(sputtering)或真空沉积法(vacuum deposition)等等。以上多条线路的材料例如可以为铜、铝、钨等导电材料。以上多条线路的材料可以相同，也可以不同，本公开对此不作限制。
在一个示例性实施例中，结合图3和图4所示，显示面板100包括层叠设置的第一导电层10、第二导电层20和第三导电层30，其中，数据线3位于第一导电层10，并沿第一方向延伸，多条数据线3沿第二方向间隔排布，第一方向与第二方向之间呈夹角设置；每一条信号走线6均包括沿第二方向延伸的第一信号走线61和沿第一方向延伸的第二信号走线62，第一信号走线61位于第二导电层20，第二信号走线62位于第三导电层30，第一信号走线61的第一端位于边缘区域2并通过第一连接孔91与对应的数据线3连接，第一信号走线61的第二端以及第二信号走线62均位于中部区域1，第一信号走线61的第二端通过第二连接孔92与第二信号走线62连接。
本实施例中，第一导电层10、第二导电层20和第三导电层30之间可以由隔离层隔开，隔离层为绝缘材料。数据线3位于第一导电层10，数据线3可以是通过材料形成技术形成于 第一导电层10上，数据线3在第一导电层10沿第一方向延伸，且多条数据线3沿第二方向间隔排布，使得多条数据线3相互绝缘。第一方向可以是图3中的Y方向，第二方向可以是图3中的X方向，第一方向与第二方向之间呈夹角设置，第一方向和第二方向之间的夹角可以是90°，使得多条数据线3之间互不相交，多条数据线3传输不同的显示内容数据，实现显示面板100的显示成像。
每一条信号走线6均包括沿X方向延伸的第一信号走线61和沿Y方向延伸的第二信号走线62，第一信号走线61位于第二导电层20，第二信号走线62位于第三导电层30，第一信号走线61和第二信号走线62可以是通过材料形成技术分别形成于第二导电层20和第三导电层30上。第一信号走线61和第二信号走线62位于不同的导电层，使得显示面板100的布线合理紧凑，提高生产效率的同时，提升显示面板100的显示性能的均一性。示例性地，第一信号走线61在电路设计中可以是SD1 line，第二信号走线62在电路设计中可以是SD2 line。
由于显示区的边缘区域2设置有多条数据线3，每条数据线3均通过对应的第一信号走线61和第二信号走线62引至中部区域1。参见图4，图4示例性地示出了显示面板100中，沿图3中A-A方向剖开的位于边缘区域2的某一数据线3以及与其连接的第一信号走线61和第二信号走线62的局部剖视图，第一信号走线61的第一端位于边缘区域2并通过第一连接孔91与对应的数据线3连接，第一连接孔91可以是刻蚀在第一导电层10和第二导电层20之间的隔离绝缘层形成过孔后，再通过沉积将导电材料填入过孔中形成导通孔(conductive via)，使得电信号可以在数据线3和第一信号走线61之间进行传输。第一信号走线61的第二端以及第二信号走线62均位于中部区域1，第一信号走线61的第二端通过第二连接孔92与第二信号走线62连接，第二连接孔92形成于第二导电层20和第三导电层30之间的隔离层内，其形成方法可以与第一连接孔91的形成方法相同，使得电信号可以在第一信号走线61和第二信号走线62之间进行传输。位于边缘区域2的数据线3通过第一连接孔91与第一信号走线61连接，第一信号走线61再通过第二连接孔92与设置于中部区域1的第二信号走线62连接，使得边缘区域2的数据线3可以连接至Bending Area，实现电信号在数据线3和驱动IC之间进行传输，使得显示面板100具有良好的成像效果。
示例性地，第一方向也可以是图3中的X方向，第二方向可以是图3中的Y方向，或者，第一方向还可以是图3中X方向与Y方向之间的某一个方向，第二方向为与该方向之间呈夹角为90°的另一方向，等等，只要多条数据线3之间互不相交且相互绝缘，且第一信号走线61和第二信号走线62相应设置即可，本公开对此不作限制。
在一个示例性实施例中，虚设图案7包括多条第一虚设电极线71和多条第二虚设电极线 72，其中，多条第一虚设电极线71位于第二导电层20，并与第一信号走线61形成均布于显示区的第一图案；多条第二虚设电极线72位于第三导电层30，并与第二信号走线62形成均布于显示区的第二图案。
本实施例中，虚设图案7包括多条第一虚设电极线71和多条第二虚设电极线72，第一虚设电极线71和第二虚设电极线72按虚设图案7设置的导电层的位置不同及延伸、排布方向不同进行划分。参见图5所示，图5示例性地示出了第二导电层20的俯视图，多条第一虚设电极线71与第一信号走线61均位于第二导电层20，并且第一虚设电极线71与第一信号走线61的延伸方向相同，第一虚设电极线71与第一信号走线61绝缘。多条第一虚设电极线71与第一信号走线61形成均布于显示区的第一图案，第一图案例如是沿Y方向均匀排布的第一虚设电极线71和第一信号走线61，改善了由于第二导电层20的部分区域设置了第一信号走线61产生的金属密度差异和膜层厚度差异而导致的反射率差异，从而提升显示面板100的结构性能和显示性能的均一性。示例性地，第一虚设电极线71在电路设计中可以是SD1 dummy line，与第一信号走线61(SD1 line)设置于同一SD金属层(Source&Drain Electrode)，即第二导电层20；第二虚设电极线72在电路设计中可以是SD2 dummy line，与第二信号走线62(SD2 line)设置于同一SD金属层，即第三导电层30。
参见图6所示，图6示例性地示出了第三导电层30的俯视图，第二虚设电极线72与第二信号走线62均位于第三导电层30，并且第二虚设电极线72与第二信号走线62的延伸方向相同，第二虚设电极线72不用于向第二信号走线62传输电信号。第二虚设电极线72与第二信号走线62形成均布于显示区的第二图案，第二图案例如是沿X方向均匀排布的第二虚设电极线72和第二信号走线62，改善了由于第三导电层30的部分区域设置了第二信号走线62产生的金属密度差异和膜层厚度差异而导致的反射率差异，从而提升显示面板100的结构性能和显示性能的均一性。
在一个示例性实施例中，如图5所示，多条第二电源信号线5均连接至第二电源信号总线8，第二电源信号总线8位于第二导电层20，至少部分第一虚设电极线71与第二电源信号总线8连接。
本实施例中，第二电源信号总线8可以位于第二导电层20的非显示区，第二电源信号总线8可以与Bending Area连接，多条第二电源信号线5均连接至第二电源信号总线8。为了使得第二导电层20的布线合理紧凑，减少不必要的绕线，将多条第二电源信号线5设置于第二导电层20，至少部分第一虚设电极线71与第二电源信号总线8连接。相对于现有技术中，第一虚设电极线71连接至第一电源信号线4，第一虚设电极线71相当于是第一电源信号线4， 使得第一电源信号线4与第二信号走线62之间具有耦合电容导致的数据线3和第一电源信号线4之间的耦合电容增大。本实施例中的部分第一虚设电极线71与第二电源信号总线8连接，可以使得部分第一虚设电极线71相当于第二电源信号总线8，从而降低数据线3和第一电源信号线4之间的耦合电容，降低数据线3信号跳变时第一电源信号线4的电压波动幅度，从而改善信号串扰，实现显示面板100良好的显示效果。
在一些实施例中，多条第一虚设电极线71也可以全部与第二电源信号总线8连接，所有第一虚设电极线71都相当于第二电源信号总线8，以进一步降低数据线3和第一电源信号线4的耦合电容，进一步降低数据线3信号跳变时第一电源信号线4的电压波动幅度，减弱信号串扰，提升显示面板100的显示效果。
在一些可能的实施方式中，结合图3和图5，第二电源信号总线8沿第一方向延伸，且在第二方向上，第二电源信号总线8位于显示区的至少一侧，多条第一虚设电极线71包括第一虚设子电极线711，第二虚设子电极线712和第三虚设子电极线713，其中，第一虚设子电极线711与第一信号走线61共线且位于第一信号走线61与第二电源信号总线8之间；第二虚设子电极线712与第一信号走线61共线且位于第一信号走线61的远离第二电源信号总线8的一侧；第三虚设子电极线713与第一信号走线61平行；第一虚设子电极线711和第三虚设子电极线713均与第二电源信号总线8连接，第二虚设子电极线712通过连接结构连接至第一虚设子电极线711、第三虚设子电极线713或者第二虚设电极线72。
本实施例中，第二电源信号总线8沿第一方向延伸，第一方向为Y方向，由于多条第二电源信号线5均连接至第二电源信号总线8，第一虚设电极线71与第二电源信号总线8连接，且第一虚设电极线71和第二电源信号线5都设置于第二导电层20，为了使得第二导电层20的布线合理紧凑，减少不必要的绕线，多条第二电源信号线5沿第二方向延伸，第二方向为X方向，即第二电源信号线5与第一虚设电极线71的延伸方向相同，且第二电源信号线5与第一虚设电极线71沿第一方向交替排布，相互绝缘。第二电源信号总线8可以位于显示区的一侧，也可以位于显示区的两侧，便于第一虚设电极线71连接至第二电源信号总线8上。
多条第一虚设电极线71包括多条第一虚设子电极线711，多条第二虚设子电极线712和多条第三虚设子电极线713。第一虚设子电极线711，第二虚设子电极线712和第三虚设子电极线713按第一虚设电极线71在第二导电层20上设置的位置不同及类型不同进行划分。参见图5，多条第一虚设电极线71包括多条第一虚设子电极线711，第一虚设子电极线711与对应的第一信号走线61共线且相互绝缘，第一虚设子电极线711不接收电信号。第一虚设子电极线711位于第一信号走线61与第二电源信号总线8之间，使得第二导电层20中，第一 信号走线61和第二电源信号总线8之间的区域的金属密度差异减小，从而提高显示面板100的膜层厚度和反射率均一性。第一虚设子电极线711可以与第二电源信号总线8连接，使得第一虚设子电极线711相当于第二电源信号总线8，从而降低数据线3和第一电源信号线4之间的耦合电容，降低数据线3信号跳变时第一电源信号线4的电压波动幅度，从而改善信号串扰，实现显示面板100良好的显示效果。需要说明的是，第一虚设子电极线711为显示区的第一信号走线61和第二电源信号总线8之间的多条短线，每条第一虚设子电极线711的与对应的第一信号走线61共线并绝缘，且与第二电源信号总线8连接。
多条第一虚设电极线71还包括多条第二虚设子电极线712，第二虚设子电极线712与对应的第一信号走线61共线且相互绝缘，第二虚设子电极线712不接收电信号。结合图3和图5，显示区在X方向两侧的数据线3均匀排布，多条第一信号走线61沿X方向延伸且第一信号走线61的一端位于边缘区域2并与对应的数据线3连接，另一端位于中部区域1并与对应的第二信号走线62连接，因此，第一信号走线61在X方向也可以均匀排布。例如，显示区在X方向两侧的第一信号走线61共线，第二虚设子电极线712位于第一信号走线61的远离第二电源信号总线8的一侧，即第二虚设子电极线712位于显示区在X方向两侧的第一信号走线61之间，使得第二导电层20在X方向两侧的第一信号走线61之间的区域的金属密度差异减小，从而提高显示面板100的膜层厚度和反射率均一性。
多条第一虚设电极线71还包括多条第三虚设子电极线713，第三虚设子电极线713与第一信号走线61平行，当第二电源信号总线8设置在显示区的一侧时，第三虚设子电极线713的一端与第二电源信号总线8连接，当第二电源信号总线8设置在显示区的两侧时，第三虚设子电极线713的两端均与第二电源信号总线8连接，使得第三虚设子电极线713相当于第二电源信号总线8，从而降低数据线3和第一电源信号线4之间的耦合电容，降低数据线3信号跳变时第一电源信号线4的电压波动幅度，从而改善信号串扰，实现显示面板100良好的显示效果。同时，设置与第一信号走线61平行的多条第三虚设子电极线713，改善了由于第二导电层20的部分区域设置第一信号走线61而产生的膜层厚度及反射率差异的情况，从而提高显示面板100的显示性能的均一性。
参见图5所示，由于第二虚设子电极线712与第一信号走线61共线且位于第一信号走线61的远离第二电源信号总线8的一侧，第二虚设子电极线712不与第二电源信号总线8直接连接。参见图7所示，图7是沿图3中B-B方向剖开的第一虚设子电极线711及与其连接的第二虚设子电极线712的局部剖视图，本实施例中仅示出第二导电层20的局部剖视图，在本实施例中，第二虚设子电极线712可以通过连接结构11与第一虚设子电极线711连接，连接 结构11设置于第一导电层10与第二导电层20之间的隔离层中，由于此处第一信号走线61与数据线3通过第一连接孔91连接，连接结构11绕开第一连接孔91的位置，即连接结构11与第一连接孔91在平行于显示面板100的一个平面上的投影不相交，使得第一信号走线61传输数据内容，第二虚设子电极线712可以通过第一虚设子电极线711与第二电源信号总线8间接连接，使得全部第一虚设电极线71相当于第二电源信号总线8，从而降低数据线3和第一电源信号线4之间的耦合电容，降低数据线3信号跳变时第一电源信号线4的电压波动幅度，改善信号串扰，实现显示面板100良好的显示效果。
在另一个实施例中，第二虚设子电极线712也可以通过连接结构11与第三虚设子电极线713连接(图中未示出)，连接结构11设置于第一导电层10与第二导电层20之间的隔离层中，连接结构11沿图3中的Y方向延伸，使得第二虚设子电极线712可以通过第三虚设子电极线713与第二电源信号总线8间接连接，从而降低数据线3与第一电源信号线4之间的耦合电容，改善信号串扰，实现显示面板100良好的显示效果。
在再一个实施例中，第二虚设子电极线712还可以通过连接结构11与第二虚设电极线72连接(下面会详细说明)，连接结构11设置于第二导电层20与第三导电层30之间的隔离层中，使得第二虚设子电极线712可以通过第二虚设电极线72与第二电源信号总线8或第一电源信号线4间接连接，从而降低数据线3与第一电源信号线4产生的耦合电容，改善线的串扰，实现显示面板100良好的显示效果。
示例性地，连接结构11可以是先刻蚀在第一导电层10与第二导电层20之间的隔离层或第二导电层20与第三导电层30之间的隔离层的内部形成过孔后，再通过沉积将导电材料填入过孔中形成导通孔，使得第二虚设子电极线712可以与第二电源信号总线8或第一电源信号线4间接连接，从而降低数据线3与第一电源信号线4之间的耦合电容，改善信号串扰，实现显示面板100良好的显示效果。
在一个示例性实施例中，结合图6和图8所示，多条第一电源信号线4位于第一导电层10，且第一电源信号线4与数据线3沿第二方向交替排布；部分第二虚设电极线72以及部分第二信号走线62与中部区域1的数据线3位置对应，另一部分第二虚设电极线72以及另一部分第二信号走线62与中部区域1的第一电源信号线4位置对应。
本实施例中，参见图6所示，第一电源信号线4和数据线3都设置于第一导电层10，为了使得第一导电层10的布线合理紧凑，减少不必要的绕线，多条第一电源信号线4沿第一方向延伸，第一方向为Y方向，即第一电源信号线4与数据线3的延伸方向相同，且第一电源信号线4与数据线3沿第二方向交替排布，使得第一导电层10的膜层厚度和金属密度均一， 减小反射率差异。
结合图3、图6和图8所示，第二虚设电极线72以及第二信号走线62位于第三导电层30，第一电源信号线4和数据线3位于第一导电层10，且第二虚设电极线72和第二信号走线62与第一电源信号线4和数据线3的延伸方向相同，第二信号走线62均位于中部区域1。当第一导电层10和第三导电层30层叠设置时，第三导电层30上的部分第二虚设电极线72以及部分第二信号走线62与中部区域1的数据线3位置对应，另一部分第二虚设电极线72以及另一部分第二信号走线62与中部区域1的第一电源信号线4位置对应。也就是说，部分第二虚设电极线72以及部分第二信号走线62在第一导电层10上的投影与中部区域1的数据线3重合，另一部分第二虚设电极线72以及另一部分第二信号走线62在第一导电层10上的投影与中部区域1的第一电源信号线4重合。与数据线3位置对应的部分第二虚设电极线72以及部分第二信号走线62的走线方向及线路形状与数据线3一致，与第一电源信号线4位置对应的另一部分第二虚设电极线72以及另一部分第二信号走线62的走线方向及线路形状与第一电源信号线4一致，以提升显示面板100的结构性能和显示性能的均一性，降低反射率差异。
在一些可能的实施方式中，结合图9和图10所示，图9是根据一示例性实施例示出的沿图3中C-C方向剖开的第一虚设电极线71与第二虚设电极线72连接部位的局部剖视图，图10是根据一示例性实施例示出的显示面板的版图示意图。本实施例示出第二导电层20及第三导电层30的局部剖视图，每条第二虚设电极线72均通过第三连接孔93与交叉的第一虚设电极线71连接。
本实施例中，结合图3、图9和图10所示，由于第二虚设电极线72位于第三导电层30并沿第一方向延伸，第一虚设电极线71位于第二导电层20并沿第二方向延伸，当第二导电层20和第三导电层30层叠设置时，每条第二虚设电极线72在第二导电层20上的投影与多条第一虚设电极线71产生交叉点。每条第二虚设电极线72均通过第三连接孔93与交叉的第一虚设电极线71连接，第三连接孔93设置于第二导电层20与第三导电层30之间的额隔离层中，由于第一虚设电极线71与第二电源信号总线8连接，使得第二虚设电极线72可以通过第一虚设电极线71与第二电源信号总线8间接连接，使得所有第二虚设电极线72都相当于第二电源信号总线8，从而降低数据线3和第一电源信号线4之间的耦合电容，降低数据线3信号跳变时第一电源信号线4的电压波动幅度，改善信号串扰，实现显示面板100良好的显示效果。此外，当所有第一虚设电极线71和第二虚设电极线72都与第二电源信号总线8连接时，多条第一虚设电极线71和多条第二虚设电极线72与第二电源信号总线8并联， 从而降低第二电源信号总线8的电阻，从而降低电压降，进而降低显示面板100的功耗。
在一些可能的实施方式中，结合图11和图12所示，图11是根据一示例性实施例示出的沿图3中C-C方向剖开的第二虚设电极线72连接第一虚设电极线72和第一电源信号线4的局部剖视图，图12是根据一示例性实施例示出的显示面板的版图示意图。部分第二虚设电极线72通过第三连接孔93与交叉的第一虚设电极线71连接，另一部分第二虚设电极线72通过第四连接孔94与第一电源信号线4连接。
本实施例中，通过第三连接孔93与交叉的第一虚设电极线71连接的部分第二虚设电极线72与数据线3的位置对应，通过第四连接孔94与第一电源信号线4连接的另一部分第二虚设电极线72与第一电源信号线4的位置对应，使得显示面板100内部的走线布局合理，便于生产。第四连接孔94设置于第一导电层10和第三导电层30之间的隔离层中，使得第二虚设电极线72可以与第一电源信号线4连接。通过将部分第二虚设电极线72经由第一虚设电极线71并联至第二电源信号总线8，另一部分第二虚设电极线72并联至第一电源信号线4，从而降低第一电源信号线4和第二电源信号总线8的电阻，降低显示面板100的功耗。同时由于部分第二虚设电极线72与第二电源信号总线8连接，使得部分第二虚设电极线72相当于第二电源信号总线8，从而降低数据线3和第一电源信号线4之间的耦合电容，降低数据线3信号跳变时第一电源信号线4的电压波动幅度，从而改善信号串扰，实现显示面板100良好的显示效果。
示例性地，如图11所示，由于与第一虚设电极线71连接的第二虚设电极线72与数据线3的位置对应，与第一电源信号线4连接的第二虚设电极线72与第一电源信号线4的位置对应，又由于数据线3与第一电源信号线4在第一导电层10上沿第二方向交替排布，因此，与第一虚设电极线71连接的第二虚设电极线72以及与第一电源信号线4连接的第二虚设电极线72在第三导电层30上沿第二方向交替排布，使得第三导电层30的膜层厚度和金属密度均一，减小显示面板100的反射率差异。
在一个示例性实施例中，结合图3、图6和图13所示，多条第二虚设电极线72包括与第二信号走线62共线的第四虚设子电极线721以及与第二信号走线62平行的第五虚设子电极线722，第一虚设电极线71中的第二虚设子电极线712通过连接结构11与第四虚设子电极线721连接。
本实施例中，多条与第二信号走线62共线的第四虚设子电极线721、多条与第二信号走线62平行的第五虚设子电极线722以及多条第二信号走线61共同形成均布于第三导电层30的第二图案，改善了由于第三导电层30的部分区域设置了第二信号走线62而产生的金属密 度差异和膜层厚度差异，降低反射率差异，从而提升显示面板100的结构性能和显示性能的均一性。
第四虚设子电极线721可以与交叉的第三虚设子电极线713或第二虚设子电极线712连接，当第四虚设子电极线721与交叉的第三虚设子电极线713连接时，结合图9，第四虚设子电极线721与第三虚设子电极线713可以通过第三连接孔93连接，从而使得第四虚设子电极线721与第二电源信号总线8间接连接。
参见图3和图4，由于第四虚设子电极线721与第二信号走线62共线且相互绝缘，第二虚设子电极线712与第一信号走线61共线且相互绝缘，且第一信号走线61与第二信号走线62通过第二连接孔92连接。当第四虚设子电极线721与第二虚设子电极线712连接时，参见图13，图13是沿图3中D-D方向剖开的第四虚设子电极线721与第二虚设子电极线712连接的局部剖视图，本实施例仅示出第二导电层20及第三导电层30的局部剖视图。第二虚设子电极线712在靠近共线的第一信号走线61的端点处设置连接结构11，也就是说，连接结构11与第二连接孔92在平行于显示面板100的一个平面上的投影并不重合或相交，使得第四虚设子电极线721通过连接结构11与第二虚设子电极线712连接，第二虚设子电极线712再通过第一虚设子电极线711与第二电源信号总线8连接，从而使得第四虚设子电极线721与第二电源信号总线8间接连接，使得第四虚设子电极线721相当于第二电源信号总线8，从而降低数据线3和第一电源信号线4之间的耦合电容，降低数据线3信号跳变时第一电源信号线4的电压波动幅度，改善信号串扰，提升显示面板100的显示性能。
在一个示例性实施例中，本公开提供了一种显示屏，显示屏包括上述的显示面板100，使得显示屏中的信号串扰得以改善，提高显示屏的显示效果。显示屏还可以包括触控层，触控层可以与显示面板100贴合设置，使得显示屏可以实现触控功能。示例性地，显示屏例如可以是LCD(Liquid Crystal Display,液晶显示器)显示屏，也可以是OLED(Organic Light-Emitting Diode，有机发光二极管)显示屏。
在一个示例性实施例中，本公开还提供了一种电子设备，电子设备包括上述的显示屏，使得电子设备的信号串扰得以改善，提高电子设备的显示效果。电子设备例如可以是需要实现窄边框的终端设备，例如可以包括智能手机、全面屏手机、平板电脑等等。
本领域技术人员在考虑说明书及实践这里公开的发明后，将容易想到本发明的其它实施方案。本申请旨在涵盖本发明的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本发明的一般性原理并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本发明的真正范围和精神由下面的权利要求指出。
应当理解的是，本发明并不局限于上面已经描述并在附图中示出的精确结构，并且可以在不脱离其范围进行各种修改和改变。本发明的范围仅由所附的权利要求来限制。
工业实用性
本文中，通过将至少部分虚设图案与第二电源信号线电连接，使得至少部分虚设图案相当于第二电源信号线，从而降低数据线和第一电源信号线之间的耦合电容，降低数据线信号跳变时第一电源信号线的电压波动幅度，从而改善信号串扰，提高显示面板的显示效果。

Claims (12)

  1. 一种显示面板，所述显示面板的显示区具有中部区域以及位于所述中部区域外侧的边缘区域，所述显示面板包括位于所述显示区的多条数据线、多条第一电源信号线以及多条第二电源信号线，其中，位于所述边缘区域的每一条数据线均通过一信号走线连接至所述中部区域，至少部分所述信号走线与所述第一电源信号线位置对应，所述信号走线所在的导电层还包括虚设图案，所述虚设图案与所述信号走线隔开设置，
    其中，至少部分所述虚设图案与所述第二电源信号线电连接。
  2. 根据权利要求1所述的显示面板，其中，所述显示面板包括层叠设置的第一导电层、第二导电层和第三导电层，
    其中，所述数据线位于所述第一导电层，并沿第一方向延伸，所述多条数据线沿第二方向间隔排布，所述第一方向与所述第二方向之间呈夹角设置；
    每一条所述信号走线均包括沿所述第二方向延伸的第一信号走线和沿所述第一方向延伸的第二信号走线，所述第一信号走线位于所述第二导电层，所述第二信号走线位于所述第三导电层，所述第一信号走线的第一端位于所述边缘区域并通过第一连接孔与对应的所述数据线连接，所述第一信号走线的第二端以及所述第二信号走线均位于所述中部区域，所述第一信号走线的第二端通过第二连接孔与所述第二信号走线连接。
  3. 根据权利要求2所述的显示面板，其中，所述虚设图案包括多条第一虚设电极线和多条第二虚设电极线，其中，
    所述多条第一虚设电极线位于所述第二导电层，并与所述第一信号走线形成均布于所述显示区的第一图案；
    所述多条第二虚设电极线位于所述第三导电层，并与所述第二信号走线形成均布于所述显示区的第二图案。
  4. 根据权利要求3所述的显示面板，其中，所述多条第二电源信号线均连接至第二电源信号总线，所述第二电源信号总线位于所述第二导电层，至少部分所述第一虚设电极线与所述第二电源信号总线连接。
  5. 根据权利要求4所述的显示面板，其中，所述第二电源信号总线沿所述第一方向延伸，且在所述第二方向上，所述第二电源信号总线位于所述显示区外侧的非显示区，所述多条第一虚设电极线包括：
    第一虚设子电极线，与所述第一信号走线共线且位于所述第一信号走线与所述第二电源 信号总线之间；
    第二虚设子电极线，与所述第一信号走线共线且位于所述第一信号走线的远离所述第二电源信号总线的一侧；
    第三虚设子电极线，与所述第一信号走线平行；
    所述第一虚设子电极线和所述第三虚设子电极线均与所述第二电源信号总线连接，所述第二虚设子电极线通过连接结构连接至所述第一虚设子电极线、所述第三虚设子电极线或者所述第二虚设电极线。
  6. 根据权利要求3至5任一项所述的显示面板，其中，所述多条第一电源信号线位于所述第一导电层，且所述第一电源信号线与所述数据线沿所述第二方向交替排布；
    部分所述第二虚设电极线以及部分所述第二信号走线与所述中部区域的数据线位置对应，另一部分所述第二拟电极线以及另一部分所述第二信号走线与所述中部区域的第一电源信号线位置对应。
  7. 根据权利要求6所述的显示面板，其中，每条所述第二虚设电极线均通过第三连接孔与交叉的所述第一虚设电极线连接；或者，
    部分所述第二虚设电极线通过第三连接孔与交叉的所述第一虚设电极线连接，另一部分所述第二虚设电极线通过第四连接孔与所述第一电源信号线连接。
  8. 根据权利要求7所述的显示面板，其中，与所述第一虚设电极线连接的第二虚设电极线以及与所述第一电源信号线连接的第二虚设电极线沿所述第二方向交替排布。
  9. 根据权利要求6所述的显示面板，其中，所述多条第二虚设电极线包括与所述第二信号走线共线的第四虚设子电极线以及与所述第二信号走线平行的第五虚设子电极线，所述第一虚设电极线中的第二虚设子电极线通过连接结构与所述第四虚设子电极线连接。
  10. 根据权利要求9所述的显示面板，其中，所述第二虚设子电极线在靠近共线的第一信号走线的端点处设置所述连接结构。
  11. 一种显示屏，包括如权利要求1至10任一项所述的显示面板。
  12. 一种电子设备，包括如权利要求11所述的显示屏。
PCT/CN2022/100641 2022-06-23 2022-06-23 一种显示面板、显示屏及电子设备 WO2023245531A1 (zh)

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