WO2023243302A1 - 表示装置 - Google Patents

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Publication number
WO2023243302A1
WO2023243302A1 PCT/JP2023/018631 JP2023018631W WO2023243302A1 WO 2023243302 A1 WO2023243302 A1 WO 2023243302A1 JP 2023018631 W JP2023018631 W JP 2023018631W WO 2023243302 A1 WO2023243302 A1 WO 2023243302A1
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WO
WIPO (PCT)
Prior art keywords
signal
light emission
row
transistor
pixel
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2023/018631
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English (en)
French (fr)
Japanese (ja)
Inventor
圭 木村
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Sony Group Corp
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Sony Group Corp
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Publication date
Application filed by Sony Group Corp filed Critical Sony Group Corp
Priority to US18/865,579 priority Critical patent/US12487712B2/en
Priority to JP2024528404A priority patent/JPWO2023243302A1/ja
Publication of WO2023243302A1 publication Critical patent/WO2023243302A1/ja
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/042—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by opto-electronic means
    • G06F3/0421—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by opto-electronic means by interrupting or reflecting a light beam, e.g. optical touch-screen
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0416—Control or interface arrangements specially adapted for digitisers
    • G06F3/04166—Details of scanning methods, e.g. sampling time, grouping of sub areas or time sharing with display driving
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes

Definitions

  • a self-luminous display device that has a pixel array section in which pixels including organic EL light emitting elements are arranged in a two-dimensional matrix.
  • light emission is controlled by line sequential driving.
  • This line sequential driving is a driving method in which display data is written and pixels are driven to emit light sequentially on a row-by-row basis.
  • a display device has been proposed that sequentially selects rows using a shift register and performs line-sequential driving (for example, see Patent Document 1).
  • the above-mentioned conventional technology has a problem in that it is difficult to perform local panel refresh of the pixel array section or bundled drive in which pixels in multiple rows are driven simultaneously. This is because it is difficult to select an arbitrary row in a shift register. Therefore, a display device has been proposed in which line-sequential driving is performed using a decoder that selects a row based on an input address instead of a shift register.
  • a self-luminous display device such as an organic EL display device
  • This duty drive is a driving method that alternately provides light emission and non-light emission periods in one frame period. In this duty driving, in addition to a scan to start light emission, a scan to stop light emission is required.
  • decoders are required for each of these multiple scans, which poses a problem in that the configuration of the display device becomes complicated.
  • the present disclosure proposes a display device that simplifies the configuration of a display device that performs duty drive.
  • a display device includes a pixel array section, a plurality of row signal lines, a plurality of data lines, and a vertical drive section.
  • a pixel array section a plurality of pixels each including a light emitting element and a pixel circuit that causes the light emitting element to emit light in accordance with an image signal are arranged in a two-dimensional matrix.
  • the plurality of row signal lines are arranged for each row in the pixel array section and transmit control signals for the pixel circuits.
  • a plurality of data lines are arranged for each column in the pixel array section and transmit the image signal.
  • FIG. 7 is a diagram illustrating a configuration example of a pixel according to a second embodiment of the present disclosure.
  • FIG. 7 is a diagram illustrating an example of a pixel driving method according to a second embodiment of the present disclosure.
  • FIG. 7 is a diagram illustrating a configuration example of a vertical drive unit according to a second embodiment of the present disclosure.
  • FIG. 7 is a diagram illustrating an example of a driving method according to a second embodiment of the present disclosure.
  • FIG. 7 is a diagram illustrating an example of a drive signal according to a second embodiment of the present disclosure.
  • FIG. 7 is a diagram illustrating an example of light emission driving according to a second embodiment of the present disclosure.
  • FIG. 7 is a diagram illustrating a configuration example of a pixel according to a third modified example of the embodiment of the present disclosure.
  • FIG. 7 is a diagram illustrating another configuration example of a pixel according to a third modified example of the embodiment of the present disclosure.
  • FIG. 7 is a diagram showing drive waveforms of another configuration example of a pixel according to a third modified example of the embodiment of the present disclosure.
  • FIG. 7 is a diagram illustrating another configuration example of a pixel according to a third modified example of the embodiment of the present disclosure.
  • 1 is a diagram illustrating an example of the appearance of a head-mounted display to which the technology according to the present disclosure can be applied.
  • FIG. 7 is a diagram illustrating a configuration example of a head-mounted display to which the technology according to the present disclosure can be applied.
  • FIG. 1 is a diagram illustrating a configuration example of a display device according to an embodiment of the present disclosure.
  • the figure is a block diagram showing an example of the configuration of the display device 10.
  • the display device 10 displays images based on image data input from the outside.
  • the display device 10 includes a pixel array section 20, a horizontal drive section 40, a vertical drive section 30, and a control section 50.
  • the pixel array section 20 is configured by arranging a plurality of pixels 100.
  • the pixel array section 20 in the figure represents an example in which a plurality of pixels 100 are arranged in the shape of a two-dimensional matrix.
  • the pixel 100 includes a light emitting element and a pixel circuit that causes the light emitting element to emit light, and emits light at a brightness according to an input image signal.
  • an organic EL element can be used as this light emitting element.
  • a row signal line 21 and a data line 22 are wired to each pixel 100.
  • the row signal line 21 transmits a control signal for the pixel circuit.
  • Data line 22 transmits an image signal. Note that the row signal line 21 is arranged for each row in the shape of a two-dimensional matrix, and is wired in common to a plurality of pixels 100 arranged in one row.
  • the data lines 22 are arranged for each column in the shape of a two-dimensional matrix, and are commonly wired to a plurality of pixels 100 arranged in one column.
  • FIG. 2 is a diagram illustrating a configuration example of a pixel according to the first embodiment of the present disclosure.
  • This figure is a circuit diagram showing an example of the configuration of the pixel 100.
  • the pixel 100 includes a light emitting element 101, a driving transistor 103, a sampling transistor 104, a reset transistor 105, and a storage capacitor 102.
  • the drive transistor 103, the sampling transistor 104, and the reset transistor 105 n-channel MOS transistors can be used.
  • the MOS transistor can be made conductive by applying a gate-source voltage Vgs exceeding the threshold voltage Vth to the gate.
  • the gate-source voltage Vgs that brings this conduction state is referred to as an on-voltage.
  • the on-voltage applied to the gate is higher than the voltage applied to the source.
  • a signal line WS, a signal line RESET, and a signal line Sig are wired to the pixel 100.
  • the signal line WS and the signal line RESET constitute the row signal line 21 described above.
  • the signal line Sig constitutes the data line 22 described above.
  • the pixel 100 is further wired with a power line Vccp, a power line Vss, and a power line Vcath.
  • the cathode of the light emitting element 101 is connected to the power supply line Vcath, and the anode is connected to the source of the drive transistor 103.
  • the drain of the drive transistor 103 is connected to the power supply line Vccp, and the gate is connected to the drain of the sampling transistor 104, the drain of the reset transistor 105, and one end of the storage capacitor 102.
  • the other end of the holding capacitor 102 is connected to the power supply line Vss.
  • the source of the sampling transistor 104 is connected to the signal line Sig, and the gate is connected to the signal line WS.
  • the source of the reset transistor 105 is connected to the power supply line Vss, and the gate is connected to the signal line RESET.
  • a circuit configured by the drive transistor 103, sampling transistor 104, and storage capacitor 102 of the pixel 100 constitutes a pixel circuit. That is, the circuits other than the light emitting element 101 in the pixel 100 constitute a pixel circuit.
  • This pixel circuit is a circuit that drives the light emitting element 101 by passing a current through the light emitting element 101.
  • an organic EL element can be used as the light emitting element 101.
  • This light emitting element 101 emits light with a brightness that corresponds to the flowing current.
  • the drive transistor 103 is a transistor that drives the light emitting element 101 by passing a current through it.
  • the reset transistor 105 is a transistor that discharges the image signal voltage Vsig held in the storage capacitor 102, makes the drive transistor 103 non-conductive, and stops the light emitting element 101 from emitting light. Reset transistor 105 is controlled by a control signal transmitted through signal line RESET.
  • FIG. 4 is a diagram illustrating a configuration example of a decoding circuit according to an embodiment of the present disclosure.
  • This figure is a circuit diagram showing an example of the configuration of the decoding circuit 31.
  • the decoding circuit 31 in the figure includes four inversion gates 202 and an AND gate 201 arranged for each row of the pixel array section 20.
  • "A0", “A1", “A2” and “A3" represent address signals.
  • the address signal in the figure is assumed to be a 4-bit signal.
  • a signal (bit value) corresponding to the row address of the pixel array section 20 among the 4-bit address signals is input to each AND gate 201 .
  • the output signal of AND gate 201 corresponds to a selection signal.
  • FIG. 5 is a diagram illustrating an example of a driving method according to the first embodiment of the present disclosure.
  • This figure is a timing chart showing an example of a method for driving the light emitting element 101 in the pixel 100.
  • "Hsync” in the figure is a signal representing the horizontal scanning period in line sequential driving.
  • "Horizontal scanning period” in the figure represents a horizontal scanning period. Note that the number added to the "horizontal scanning period” identifies the vertical scanning period. For example, “horizontal scanning period 0" represents the first horizontal scanning period in the vertical scanning period.
  • Address signal represents an address signal input to the decoding circuit 31.
  • Selection signal represents a selection signal output from the decoding circuit 31. This selection signal represents a state in which the "1" portion of the binarized signal is selected.
  • WRT_CLK and “RST_CLK” represent the clock signals described in FIG. 3.
  • WS and “RESET” represent control signals for the signal line WS and signal line RESET. The “1” portion of these binary control signals represents the above-mentioned on-voltage. On the other hand, the "0" portion represents the off-voltage.
  • the sampling transistor 104 of the pixel 100 described in FIG. A light emitting current corresponding to the written image signal flows through the drive transistor 103 and is supplied to the light emitting element 101. In this way, in the pixel 100 in FIG. 2, the light emitting element 101 starts emitting light at the same time as writing is performed.
  • the reset transistor 105 of the pixel 100 in FIG. is discharged. As a result, the drive transistor 103 of the pixel 100 becomes non-conductive, and the light emitting element 101 stops emitting light.
  • FIG. 6 is a diagram illustrating an example of light emission driving according to the first embodiment of the present disclosure.
  • This figure is a timing diagram showing an example of duty drive in the pixel array section 20.
  • "Vsync” in the figure is a signal representing the vertical scanning period in line sequential driving.
  • "Hsync” in the figure is a signal representing the horizontal scanning period in line sequential driving. Note that the numbers identify horizontal scanning periods.
  • “Row address” in the figure represents the address (in hexadecimal notation) of the row of the pixel array section 20. Row address "0" corresponds to the first row of pixel array section 20, and row address "F” corresponds to the last row of pixel array section 20.
  • a write address "0" is input to the decode circuit 31, writing is performed in the row with the row address "0" and light emission starts, and an erase address "8" is input to the decode circuit 31.
  • the row with row address "8” stops emitting light.
  • a value "1” is added to the write address and the erase address in each horizontal scanning period and input to the decoding circuit 31. Therefore, following writing 210, light emission start 211 and light emission stop 212 are sequentially executed for each row of the pixel array section 20. Thereby, duty driving can be performed in the pixel array section 20, and it is possible to reduce the feeling of afterimage when displaying a moving image.
  • a plurality of address signals are input to the decoding circuit 31 at different timings during one horizontal scanning period.
  • the decoding circuit 31 selects a row in response to these plural address signals. Therefore, the circuit can be simplified compared to the case where a decoding circuit is arranged for each of a plurality of address signals.
  • the display device 10 of the first embodiment described above the light emission current of the drive transistor 103 flows in accordance with the image signal held in the storage capacitor 102 of the pixel 100.
  • the display device 10 according to the second embodiment of the present disclosure differs from the above-described first embodiment in that variations in the threshold values of the drive transistors 103 of the pixels 100 are corrected.
  • FIG. 7 is a diagram illustrating a configuration example of a pixel according to the second embodiment of the present disclosure. Similar to FIG. 2, this figure is a circuit diagram showing an example of the configuration of the pixel 100.
  • the pixel 100 in the figure differs from the pixel 100 in FIG. 2 in that the reset transistor 105 is omitted and the pixel 100 further includes a light emission control transistor 107, a switching transistor 108, and an auxiliary capacitor 106.
  • p-channel MOS transistors can be used as the drive transistor 103, sampling transistor 104, light emission control transistor 107, and switching transistor 108 in the figure.
  • the cathode of the light emitting element 101 is connected to the power supply line Vcath, and the anode is connected to the drain of the drive transistor 103 and the drain of the switching transistor 108.
  • the source of the switching transistor 108 is connected to the power supply line Vss, and the gate is connected to the signal line AZ.
  • the gate of the drive transistor 103 is connected to the drain of the sampling transistor 104 and one end of the storage capacitor 102.
  • the other end of the storage capacitor 102 is connected to the source of the drive transistor 103, the drain of the light emission control transistor 107, and one end of the auxiliary capacitor 106.
  • the other end of the auxiliary capacitor 106 is connected to the power supply line Vccp.
  • the source of the light emission control transistor 107 is connected to the power supply line Vccp, and the gate is connected to the signal line DS.
  • the source of the sampling transistor 104 is connected to the signal line Sig, and the gate is connected to the signal line WS.
  • the light emission control transistor 107 is a transistor that controls light emission and non-light emission of the light emitting element 101. This light emission control transistor 107 is controlled by a light emission control signal transmitted through a signal line DS. Note that the light emission control transistor 107 is an example of a "switch element" in the present disclosure.
  • the switching transistor 108 is a transistor that controls the light emitting element 101 so that it does not emit light during the non-emission period of the light emitting element 101. This switching transistor 108 is controlled by a control signal transmitted through a signal line AZ. When the switching transistor 108 becomes conductive, a path bypassing the light emitting element 101 is formed, and the light emitting element 101 stops emitting light. Note that the switching transistor 108 is an example of a "second switching element" in the present disclosure.
  • the auxiliary capacitor 106 is a capacitor that suppresses fluctuations in the source voltage of the drive transistor 103 when the image signal voltage Vsig is written. Further, the auxiliary capacitor 106 has the function of adjusting the gate-source voltage Vgs of the drive transistor 103 to the threshold voltage Vth of the drive transistor 103.
  • the on-voltage applied to the gate is lower than that to the source.
  • FIG. 8 is a diagram illustrating an example of a pixel driving method according to the second embodiment of the present disclosure. This figure is a timing chart showing an example of a method for driving the light emitting element 101 in the pixel 100.
  • "Sig” in the figure represents the image signal voltage Vsig and reference voltage Vofs transmitted by the signal line Sig.
  • Vsig” and “Vofs” in the figure represent portions to which the image signal voltage Vsig and the reference voltage Vofs are applied.
  • "WS”, “DS”, and “AZ” in the figure represent the control signals transmitted by the signal line WS, signal line DS, and signal line AZ, respectively, and are the values of these binary control signals.
  • the “0” portion represents the above-mentioned on-voltage.
  • the value “1” represents the off-voltage.
  • “Vs” and “Vg” in the figure represent the source voltage and gate voltage of the drive transistor 103.
  • the reference voltage Vofs is applied to the signal line Sig.
  • An off voltage is applied to the signal line DS, signal line WS, and signal line AZ.
  • an on-voltage is applied to the signal line DS, and the light emission control transistor 107 becomes conductive. Further, an on-voltage is applied to the signal line AZ, and the switching transistor 108 becomes conductive. As a result, the current flowing through the drive transistor 103 flows into the power supply line Vss via the switching transistor 108.
  • an on-voltage is applied to the signal line WS, and the sampling transistor 104 becomes conductive.
  • the power supply voltage Vccp is applied to the source node of the drive transistor 103.
  • a reference voltage Vofs is written to the gate node of the drive transistor 103 via the sampling transistor 104 .
  • the gate node and source node of the drive transistor 103 are both brought into a floating state, whereby a self-discharge operation is performed.
  • the self-discharge operation the potential of each node is discharged through a path of the drive transistor 103, the switching transistor 108, and the power supply line Vss.
  • both the source voltage Vs and gate voltage Vg of the drive transistor 103 gradually decrease due to the self-discharge operation.
  • the gate-source voltage Vgs reaches the threshold voltage Vth, the drive transistor 103 becomes non-conductive and the self-discharge operation is stopped.
  • an on-voltage is applied to the signal line WS, and the sampling transistor 104 becomes conductive.
  • the signal voltage Vsig is written by sampling by the sampling transistor 104 while the source node of the drive transistor 103 remains in a floating state.
  • the voltage held in the holding capacitor 102 is Vth+Vsig. Further, application of the on-voltage to the signal line AZ is stopped, and the switching transistor 108 becomes non-conductive.
  • FIG. 9 is a diagram illustrating a configuration example of a vertical drive unit according to a second embodiment of the present disclosure.
  • This figure like FIG. 3, is a block diagram showing a configuration example of the vertical drive section 30.
  • the vertical drive unit 30 in FIG. 3 further includes an AND gate 34, a NAND gate 35, and a logic circuit 36, and a signal line EM_CLK and a signal line STP_CLK are arranged instead of the signal line RES_CLK. Different from 30.
  • a light emission start address signal and a light emission stop address signal are input to the decoding circuit 31 shown in the figure.
  • the Q output of the latch circuit 32 in the figure outputs the WT_EN signal, which is a write selection signal. This signal is input to the logic circuit 36.
  • the AND gate 34 receives a selection signal and a clock signal EM_CLK transmitted through the signal line EM_CLK. The output of the AND gate 34 is connected to the clock terminal of the latch circuit 33.
  • a selection signal and a clock signal STP_CLK transmitted through the signal line STP_CLK are input to the input of the NAND gate 35 .
  • the output of the NAND gate 35 is connected to the clear terminal of the latch circuit 33. Further, a power supply voltage is applied to the D input terminal of the latch circuit 33.
  • the latch circuit 33 generates a signal with a pulse width from the rising edge of EM_CLK to the rising edge of STP_CLK.
  • the Q output of the latch circuit 33 outputs an EM_EN signal which is a light emission control selection signal. This signal is input to the logic circuit 36.
  • the logic circuit 36 is a circuit that generates a drive signal for the pixel 100. This logic circuit 36 generates control signals to be applied to the signal line WS, signal line DS, and signal line AZ described in FIG. 7 based on the input WT_EN signal and EM_EN signal.
  • the logic circuit 36 can be configured, for example, by a circuit that is a combination of logic gates. Specifically, a combinational logic circuit based on a truth table receives the WT_EN signal, the EM_EN signal, and a signal that toggles in one horizontal period as input, and generates control signals for the signal line WS, signal line DS, and signal line AZ. Can be configured.
  • FIG. 10 is a diagram illustrating an example of a driving method according to the second embodiment of the present disclosure. Similar to FIG. 5, this figure is a timing chart showing an example of a method for driving the light emitting element 101 in the pixel 100.
  • EM_CLK and “STP_CLK” represent the clock signals explained in FIG.
  • WT_EN and “EM_EN” represent the WT_EN signal and EM_EN signal described in FIG. 9.
  • the same notation as in FIG. 5 is used.
  • a write address 220, a light emission start address 222, and a light emission stop address 223 are input to the decoding circuit 31 every horizontal scanning period. Rows of the pixel array section 20 corresponding to these addresses are selected and a selection signal is output.
  • the selection signal selected by the write address is held in the latch circuit 32 at the rising edge of WRT_CLK and output as the WT_EN signal.
  • the selection signal selected by the light emission start address is held in the latch circuit 33 at the rising edge of EM_CLK, and the EM_EN signal changes to "1".
  • the output of the latch circuit 33 is cleared by the AND signal of the selection signal selected by the light emission stop address and STP_CLK, and the EM_EN signal changes to "0". Note that this figure shows an example in which the write address and the light emission start address are the same.
  • the selection signal selected by the write address corresponds to the write selection signal representing the row of the pixel array section 20 to which writing is to be performed. Further, the selection signal selected by the light emission start address and the selection signal selected by the light emission stop address correspond to the light emission control selection signal representing the row in which the light emission current is controlled. Among these, the selection signal selected by the light emission start address corresponds to the light emission start control selection signal, and the selection signal selected by the light emission stop address corresponds to the light emission stop control selection signal.
  • the write address signal, the light emission start address signal, and the light emission stop address signal are input to the decoding circuit 31 during one horizontal scanning period, and the selection signal of the corresponding row is outputted.
  • the selection signal based on the write address signal and the selection signal based on the light emission stop address signal are captured and held in the latch circuits 32 and 33 at different timings by the clock signals WRT_CLK and EM_CLK. Further, the signal held in the latch circuit 33 is cleared in synchronization with the selection signal based on the light emission stop address signal and the signal based on the clock signal STP_CLK.
  • FIG. 11 is a diagram illustrating an example of a drive signal according to the second embodiment of the present disclosure. This figure is a timing diagram showing an example of a drive signal generated by the logic circuit 36.
  • “Address signal” in the figure represents an address signal input to the decoding circuit 31.
  • “WRT_CLK”, “EM_CLK” and “STP_CLK” represent clock signals.
  • “WS” and “DS” represent control signals generated by the logic circuit 36 and output to the signal line WS and the signal line DS.
  • a signal having the waveform described in FIG. 8 is generated and sequentially output to the signal line WS and the signal line DS in the row corresponding to the address signal.
  • this figure represents a drive signal when the number of horizontal scanning periods is greater than the number of rows of the pixel array section 20.
  • a blanking period (vertical blanking period) is arranged after write driving is completed for all rows. This vertical blanking period is a period in which writing and light emission start control are not performed.
  • the supply of WRT_CLK and EM_CLK is stopped during the vertical blanking period, and row selection is stopped.
  • STP_CLK as well, supply of the clock signal can be stopped and selection of unnecessary rows can be stopped. Note that it is also possible to adopt a method of stopping row selection by outputting an address signal that does not correspond to a row of the pixel array section 20 during the vertical blanking period.
  • FIG. 12 is a diagram illustrating an example of light emission driving according to the second embodiment of the present disclosure. Similar to FIG. 6, this figure is a timing chart showing an example of duty driving in the pixel array section 20, and is a diagram showing a state of light emission driving using the drive signal of FIG. 11. In this figure, the same notation as in FIG. 6 is used. Further, the figure shows an example in which the number of rows of the pixel array section 20 is 16 and the number of horizontal scanning periods is 26. The periods “horizontal scanning period 16" to "horizontal scanning period 25" correspond to the above-mentioned vertical blanking period. Duty driving can be performed in the pixel array section 20.
  • the display device 10 performs bundling drive by simultaneously selecting two adjacent rows of the pixel array section 20 based on the address signal input during the horizontal scanning period. It can be carried out.
  • the display device 10 of the second embodiment described above performs duty driving by inputting the light emission start address signal and the light emission stop address signal to the decoding circuit 31 during the horizontal scanning period.
  • the display device 10 according to the fourth embodiment of the present disclosure differs from the second embodiment in that a plurality of light emission start address signals and light emission stop address signals are input to the decoding circuit 31 during the horizontal scanning period. different from.
  • the light emission drive according to the fourth embodiment of the present disclosure is not limited to this example.
  • the configuration of the display device 10 other than this is the same as the configuration of the display device 10 in the second embodiment of the present disclosure, so a description thereof will be omitted.
  • two light emission start address signals and two light emission stop address signals are input to the decoding circuit 31 in one horizontal scanning period. . Thereby, split light emission can be performed.
  • FIG. 16 is a diagram illustrating a configuration example of a vertical drive unit according to a fifth embodiment of the present disclosure.
  • This figure like FIG. 9, is a block diagram showing a configuration example of the vertical drive section 30.
  • the vertical drive unit 30 in the figure is different from the vertical drive unit 30 in FIG. 9 in that it further includes an AND gate 38, an OR gate 39, and a latch circuit 37, and a signal line Vsync and a signal line GEM are arranged.
  • the signal line Vsync is a signal line that transmits a vertical synchronization signal.
  • the signal line GEM is a signal line that transmits a GEM signal that controls collective light emission.
  • FIG. 17 is a diagram illustrating an example of light emission driving according to the fifth embodiment of the present disclosure. Similar to FIG. 12, this figure is a timing chart showing an example of driving in the pixel array section 20, and is a diagram showing a state of light emission driving using the drive signal of FIG. 16. In the figure, "GEM" represents a GEM signal.
  • writing 210 is sequentially performed on the rows of the pixel array section 20. Thereafter, all the rows of the pixel array section 20 collectively enter a light emitting state during the period when the GEM signal is "1".
  • the light emission drive in the two vertical scanning periods in the latter part of the figure represents an example in which light emission drive is performed for a row in which writing 210 has been performed. This can be done, for example, by using the vertical drive section 30 that has the function of latching the write flag.
  • the configuration of the display device 10 other than this is the same as the configuration of the display device 10 in the second embodiment of the present disclosure, so a description thereof will be omitted.
  • the display device 10 can drive all the rows of the pixel array section 20 to emit light at once.
  • FIG. 18 is a diagram illustrating a configuration example of a pixel according to a first modified example of the embodiment of the present disclosure. Similar to FIG. 7, this figure is a circuit diagram showing a configuration example of the pixel 100.
  • the pixel 100 in the figure differs from the pixel 100 in FIG. 2 in that the auxiliary capacitor 106 is omitted and the pixel 100 further includes a switching transistor 109.
  • the switching transistor 109 is a transistor that short-circuits the gate and drain of the drive transistor 103.
  • a p-channel MOS transistor can be used as switching transistor 109.
  • a signal line AZ2 is connected to the gate of the switching transistor 109.
  • the light emission control transistor 107 when performing light emission control similar to that of the pixel circuit of FIG. 2, the light emission control transistor 107 is made non-conductive, and the switching transistor 109 is made conductive. As a result, the storage capacitor 102 is discharged, the drive transistor 103 can be brought into a non-conductive state, and the supply of light emitting current to the light emitting element 101 can be stopped.
  • the light emission control transistor 107 when performing light emission control similar to the pixel circuit of FIG. 7, the light emission control transistor 107 is controlled to be conductive or non-conductive. Thereby, the start and stop of supply of light emitting current to the light emitting element 101 can be controlled.
  • FIG. 19 is a diagram illustrating a configuration example of a pixel according to a second modified example of the embodiment of the present disclosure. Similar to FIG. 18, this figure is a circuit diagram showing a configuration example of the pixel 100. The pixel 100 in the figure differs from the pixel 100 in FIG. 18 in that it further includes a sampling transistor 110 and capacitors 112 and 113.
  • the source of the sampling transistor 110 is connected to the drain of the sampling transistor 104, and the drain is connected to the signal line Sig1.
  • a signal line WS1 is connected to the gate of the sampling transistor 110.
  • Capacitor 112 is connected between the drain and source of sampling transistor 110.
  • Capacitor 113 is connected between the drain of sampling transistor 110 and power supply line Vss.
  • a signal line Sig2 is connected to the drain of the sampling transistor 104.
  • a signal line WS2 is connected to the gate of the sampling transistor 104.
  • the light emission control transistor 107 when performing light emission control similar to the pixel circuit of FIG. 2, the light emission control transistor 107 is made non-conductive, and the switching transistor 109 and the sampling transistor 104 are made conductive. As a result, the storage capacitor 102 is discharged, the drive transistor 103 can be brought into a non-conductive state, and the supply of light emitting current to the light emitting element 101 can be stopped.
  • the light emission control transistor 107 when performing light emission control similar to the pixel circuit of FIG. 7, the light emission control transistor 107 is controlled to be conductive or non-conductive. Thereby, the start and stop of supply of light emitting current to the light emitting element 101 can be controlled.
  • FIG. 20 is a diagram illustrating a configuration example of a pixel according to a third modification of the embodiment of the present disclosure. Similar to FIG. 2, this figure is a circuit diagram showing an example of the configuration of the pixel 100.
  • the pixel 100 in FIG. 2 differs from the pixel 100 in FIG. 2 in that it further includes a sampling transistor 114, a light emission control transistor 107, and a switching transistor 108.
  • a p-channel MOS transistor can be used as sampling transistor 114.
  • the drain and source of the sampling transistor 114 are connected to the drain and source of the sampling transistor 104, respectively.
  • the light emission control transistor 107 is connected between the source of the drive transistor 103 and the anode of the light emitting element 101.
  • the storage capacitor 102 is connected between the gate and source of the drive transistor 103.
  • the drain and source of the reset transistor 105 are connected to the gate and source of the drive transistor 103, respectively.
  • the drain of the switching transistor 108 is connected to the source of the drive transistor 103, and the source is connected to the power supply line Vss.
  • a signal line WS_N and a signal line WS_P are connected to the gates of the sampling transistors 104 and 401, respectively.
  • a signal line DS is connected to the gate of the light emission control transistor 107.
  • a signal line AZ is connected to the gate of the switching transistor 108.
  • the reset transistor 105 when performing light emission control similar to the pixel circuit of FIG. 2, the reset transistor 105 is made conductive and the storage capacitor 102 is discharged.
  • the drive transistor 103 can be brought into a non-conductive state, and the supply of light emitting current to the light emitting element 101 can be stopped.
  • FIG. 21A is a diagram illustrating another configuration example of a pixel according to a third modification of the embodiment of the present disclosure.
  • the pixel circuit in the figure is the same as the pixel circuit in FIG. 20, with the reset transistor 105 omitted.
  • light emission control similar to that of the pixel circuit of FIG. 7 can be performed by controlling the voltage of the power supply line Vccp.
  • FIG. 22 is a diagram illustrating another configuration example of pixels according to the third modification of the embodiment of the present disclosure.
  • the pixel circuit in the figure includes a storage capacitor 102, a drive transistor 103, a sampling transistor 104, a light emission control transistor 107, a switching transistor 108, transistors 405 to 409, and a light emitting element 101.
  • the drive transistor 103, the sampling transistor 104, the light emission control transistor 107, the switching transistor 108, and the transistors 405 to 409 are p-channel MOS transistors.
  • the sampling transistor 104 has a gate connected to the signal line WS, a source connected to the signal line Sig, and a drain connected to the drain of the light emission control transistor 107 and the source of the drive transistor 103.
  • the gate of the light emission control transistor 107 is connected to the signal line DS, the source is connected to the power supply line Vccp, and the drain is connected to the drain of the sampling transistor 104 and the source of the drive transistor 103.
  • the gate of the drive transistor 103 is connected to the source of the transistor 405, the drain of the transistor 407, and the storage capacitor 102, the source is connected to the drains of the sampling transistor 104 and the light emission control transistor 107, and the drain is connected to the sources of the transistor 408 and transistor 409. Connected.
  • One end of the storage capacitor 102 is connected to the power supply line Vccp, and the other end is connected to the gate of the drive transistor 103, the source of the transistor 405, and the drain of the transistor 407.
  • the holding capacitor 102 may include two capacitors connected in parallel.
  • the gate of the transistor 405 is connected to the signal line AZ2, the source is connected to the gate of the drive transistor 103, the drain of the transistor 407, and the other end of the storage capacitor 102, and the drain is connected to the source of the transistor 406.
  • the gate of the transistor 406 is connected to the signal line AZ2, the source is connected to the drain of the transistor 405, and the drain is connected to the power supply line Vss.
  • the gate of the transistor 407 is connected to the signal line WS, the drain is connected to the gate of the drive transistor 103, the source of the transistor 405, and the other end of the storage capacitor 102, and the source is connected to the drain of the transistor 408.
  • the gate of the transistor 408 is connected to the signal line WS, the drain is connected to the source of the transistor 407, and the source is connected to the drain of the drive transistor 103 and the source of the transistor 409.
  • the gate of the transistor 409 is connected to the signal line DS, the source is connected to the drain of the driving transistor 103 and the source of the transistor 408, and the drain is connected to the source of the switching transistor 108 and the anode of the light emitting element 101.
  • the gate of the switching transistor 108 is connected to the signal line AZ1, the source is connected to the drain of the transistor 409 and the anode of the light emitting element 101, and the drain is connected to the power supply line Vss.
  • the sampling transistor 104, the driving transistor 103, the transistor 408, and the transistor 407 are turned on, so that the voltage across the storage capacitor 102 increases based on the image signal supplied from the signal line Sig. Set.
  • the light emission control transistor 107 and the transistor 409 are turned on and off based on the signal on the signal line DS.
  • the drive transistor 103 causes a current corresponding to the voltage across the storage capacitor 102 to flow through the light emitting element 101 during a period when the light emission control transistor 107 and the transistor 409 are in an on state.
  • the light emitting element 101 emits light based on the current supplied from the drive transistor 103. In this way, the pixel 100 emits light with a brightness that corresponds to the pixel signal.
  • Transistor 405 and transistor 406 are turned on and off based on the signal on signal line AZ2.
  • the voltage at the gate of the drive transistor 103 is initialized by being set to the voltage of the power supply line Vss.
  • the switching transistor 108 is turned on and off based on the signal on the signal line AZ1.
  • the voltage at the anode of the light emitting element 101 is initialized by being set to the voltage of the power supply line Vss.
  • all the MOS transistors in the pixel circuits in FIGS. 2, 7, 18, 19, 20, 21A, and 22 may be transistors using low temperature polycrystalline silicon (LTPS).
  • LTPS low temperature polycrystalline silicon
  • a transistor using an oxide semiconductor may be used as at least one of the sampling transistor 104 and the reset transistor 105.
  • a transistor using an oxide semiconductor may be used as at least one of the sampling transistor 104 and the switching transistor 108.
  • a transistor using an oxide semiconductor may be used as at least one of the sampling transistor 104, the switching transistor 108, and the transistor 109.
  • a transistor using an oxide semiconductor may be used as at least one of the sampling transistor 104, the switching transistor 108, and the sampling transistor 110.
  • a transistor using an oxide semiconductor may be used as at least one of the sampling transistor 104, the reset transistor 105, the switching transistor 108, and the sampling transistor 114.
  • a transistor using an oxide semiconductor may be used as at least one of the sampling transistor 104, the switching transistor 108, and the sampling transistor 114.
  • a transistor using an oxide semiconductor may be used as the switching transistor 108 and at least one of the transistors 405 to 408.
  • the head mounted display 620 is a so-called light guide plate type head mounted display, it is not limited thereto, and may be, for example, a so-called bird bath type head mounted display.
  • This birdbath type head-mounted display includes, for example, a beam splitter and a partially transparent mirror.
  • the beam splitter outputs light encoded with image information toward a mirror, which reflects the light toward the user's eyes.
  • Both the beam splitter and the partially transparent mirror are partially transparent. This allows light from the surrounding environment to reach the user's eyes.
  • the monitor 514 is provided on the left side of the rear surface of the camera body 131 from approximately the center.
  • Electronic viewfinder 515 is provided above monitor 514 on the back of camera body 131 . By looking through the electronic viewfinder 515, the photographer can visually recognize the light image of the subject guided from the photographic lens unit 512 and determine the composition.
  • the technology according to the embodiments described above can be applied to the electronic viewfinder 515.
  • FIG. 26 is a diagram illustrating an example of the appearance of a television device 710 to which the technology according to the present disclosure can be applied.
  • Television device 710 has a video display screen section 711 including a front panel 712 and filter glass 713.
  • the techniques related to the above embodiments and the like can be applied to this video display screen section 711.
  • FIG. 27 is a diagram illustrating an example of the appearance of a smartphone 800 to which the technology according to the present disclosure can be applied.
  • the smartphone 800 includes a display section 801 that displays various information, and an operation section 802 that includes buttons and the like that accept operation inputs from the user.
  • the technology related to the above embodiments and the like can be applied to this display portion 801.
  • FIGS. 28A and 28B are diagrams illustrating an example of the configuration of a vehicle to which the technology according to the present disclosure can be applied.
  • 28A shows an example of the interior of the vehicle 200 as seen from the rear
  • FIG. 28B shows an example of the interior of the vehicle as seen from the left rear of the vehicle 200.
  • the vehicle of FIGS. 28A and 28B has a center display 911, a console display 912, a head-up display 913, a digital rear mirror 914, a steering wheel display 915, and a rear entertainment display 916.
  • the safety-related information is based on sensor detection results, such as detection of falling asleep, detection of looking away, detection of mischief by children in the same vehicle, presence or absence of seatbelts, and detection of occupants being left behind.
  • the operation-related information is information on gestures related to the occupant's operations, which are detected using a sensor.
  • the gesture may include the operation of various equipment in the vehicle, and includes, for example, the operation of an air conditioner, a navigation device, an AV (Audio/Visual) device, a lighting device, and the like.
  • the life log includes life logs of all crew members. For example, a life log includes a record of each occupant's actions.
  • the digital rear mirror 914 can not only display the rear of the vehicle but also display the state of the occupants in the rear seats, so it can be used, for example, to display life log information of the occupants in the rear seats.
  • the technology according to the above embodiments can be applied to the center display 911, console display 912, head-up display 913, digital rear mirror 914, steering wheel display 915, and rear entertainment display 916.
  • a display device comprising: a decoding circuit that outputs a plurality of the selection signals, and generates the control signal based on the plurality of output selection signals.
  • the pixel circuit includes a storage capacitor that holds the image signal, and drives the light emitting element to emit light by supplying a light emitting current according to the image signal held in the storage capacitor,
  • the decoding circuit includes a write selection signal, which is the selection signal representing the row in which writing is performed to cause the storage capacitor to hold the image signal, and a light emission control selection signal, which is the selection signal representing the row in which the light emission current is to be controlled.
  • the display device wherein the vertical drive section generates a signal based on the light emission control selection signal that controls a voltage of a power supply line that is arranged for each row and supplies the light emission current.
  • the decoding circuit transmits a light emission start control selection signal representing the row in which control is performed to start supply of the light emission current and a light emission stop control selection signal representing the row in which control is performed to stop supply of the light emission current to the light emission control. Generate as a selection signal, The display device according to (2), wherein the vertical drive section generates the control signal based on the light emission start control selection signal and the light emission stop control selection signal.

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