WO2023236523A1 - 一种增强型N沟道和P沟道GaN器件集成结构 - Google Patents

一种增强型N沟道和P沟道GaN器件集成结构 Download PDF

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WO2023236523A1
WO2023236523A1 PCT/CN2022/143216 CN2022143216W WO2023236523A1 WO 2023236523 A1 WO2023236523 A1 WO 2023236523A1 CN 2022143216 W CN2022143216 W CN 2022143216W WO 2023236523 A1 WO2023236523 A1 WO 2023236523A1
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layer
gallium nitride
channel
aluminum
type gallium
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French (fr)
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张龙
马杰
刘培港
刘斯扬
孙伟锋
时龙兴
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东南大学
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT

Definitions

  • the present invention mainly relates to the field of gallium nitride power semiconductor integration technology, and specifically, is an enhanced N-channel and P-channel GaN device integration structure.
  • Wide bandgap semiconductor electronics are used in tasks requiring high operating voltage/speed and low power loss, as well as withstanding harsh operating conditions.
  • the wide energy band gap suppresses spontaneous electronic transitions from the valence band to the conduction band, which can be activated by high electric fields, high temperatures, and ambient energy from energetic particles. This allows the device to maintain its electrical characteristics under a variety of extreme conditions.
  • Gallium nitride is a key wide-bandgap semiconductor, and the most popular device structure is the high electron mobility transistor (HEMT) based on planar heterojunctions.
  • HEMTs high electron mobility transistor
  • Gallium nitride HEMTs offer high electron mobility and small terminal capacitance in a two-dimensional electron gas (2DEG) channel, making them particularly suitable for high frequency/high power density applications such as RF power amplifiers and compact power converters/power supplies.
  • 2DEG two-dimensional electron gas
  • GaN HEMTs fabricated on large silicon substrates using silicon-compatible process equipment have been developed for power electronics, resulting in power with high-voltage blocking capability enhanced mode operation and excellent stability and reliability in long-term operation Development of switching devices.
  • discrete GaN HEMTs have been used to regulate currents of tens of amps and block high voltages up to about 1 kV (kilovolts). These core devices require peripheral circuits as drive, control, detection and protection modules.
  • Monolithic integration facilitates the creation of more on-chip functions, enhances robustness, and promotes miniaturization of the entire power conversion system.
  • Gallium nitride HEMTs have a planar configuration where all three device terminals (source, gate and drain) are on the top surface. This configuration facilitates high-density integration, which has led to the commercial development of GaN power switches with integrated gate drivers. However, all of these GaN integrated circuits are based on N-channel devices with electrons as majority carriers.
  • CMOS complementary logic metal-oxide semiconductor
  • P-GaN gate power HEMT platforms (based on P-GaN/AlGaN/GaN heterojunctions grown on silicon substrates) are promising for enabling monolithically integrated complementary logic circuits for logic control of power switches, Because enhancement mode N-channel devices are readily available, and the P-GaN layer provides a compelling venue for P-channel devices.
  • the performance of enhancement-mode P-channel devices has been improved through the use of processing techniques such as gate recessing.
  • the present invention proposes an enhancement mode N-channel and P-channel GaN device integrated structure.
  • the structure of the invention can ensure the enhancement mode of N-channel devices while using the traditional N-channel gallium nitride HEMT process. It can very well improve the output current and threshold voltage of P-channel gallium nitride HEMT.
  • An enhanced N-channel and P-channel GaN device integrated structure including: a substrate, an aluminum nitrogen nucleation layer is provided on the substrate, an aluminum nitride gallium buffer layer is provided on the aluminum nitrogen nucleation layer, and an aluminum nitride gallium buffer layer is provided on the aluminum nitrogen nucleation layer.
  • a gallium nitride channel layer is provided on the gallium nitride buffer layer, an aluminum gallium nitride barrier layer is provided on the gallium nitride channel layer, and an isolation layer is provided in the aluminum gallium nitride barrier layer and is as deep as the gallium nitride trench.
  • the isolation layer divides the aluminum gallium nitride barrier layer and the gallium nitride channel layer into two parts; a P-channel device is provided on one side of the isolation layer, and the P-channel device includes a A first P-type gallium nitride layer on the aluminum gallium nitride barrier layer on one side of the layer, a first gallium nitride isolation layer on the first P-type gallium nitride layer, and a first gallium nitride isolation layer on the first P-type gallium nitride barrier layer.
  • a first P + type gallium nitride layer is provided.
  • a first source electrode, a first gate electrode and a first drain electrode are provided on the first P + type gallium nitride layer.
  • the first gate electrode is sunk into the third A P + type gallium nitride layer, a gate dielectric layer is provided between the first gate electrode and the first P + type gallium nitride layer; an N channel device is provided on the other side of the isolation layer, the N The channel device includes a second source electrode, a second P-type gallium nitride layer and a second drain electrode located on the aluminum gallium nitride barrier layer on the other side of the isolation layer.
  • the second source electrode and the second drain electrode are respectively located on On both sides of the second P-type gallium nitride layer, a second gallium nitride isolation layer is provided above the second P-type gallium nitride layer, and a second P + -type gallium nitride layer is provided above the second gallium nitride isolation layer. layer, and a second gate electrode is provided above the second P + type gallium nitride layer.
  • the present invention has the following beneficial effects:
  • the present invention mainly divides P-GaN into three levels with different doping concentrations, keeping the two layers of P-GaN in contact with the aluminum gallium nitrogen barrier layer and in contact with the ohmic metal layer with a higher doping concentration. High, while the layer of P-GaN between the two layers of high-concentration P-GaN maintains a lower doping concentration; the aluminum nitrogen insertion layer and the gate dielectric layer in the gate area of the P-channel device form the gate dielectric stack. At least the following beneficial effects can be achieved:
  • the bottom P-type gallium nitride layer provides a conduction channel in the P-channel device and provides a certain concentration of holes under P-type doping, which increases the output current after the device is turned on; on the other hand, the bottom layer in the N-channel device
  • the holes provided by the P-type gallium nitride layer shut off the two-dimensional electron gas under the aluminum gallium nitride barrier layer, ensuring the enhancement mode of the N-channel device.
  • the middle gallium nitride isolation layer maintains a low doping concentration.
  • the hole concentration in GaN under the gate area is low, making it easier to achieve turn-off.
  • the thickness of GaN under the gate can be increased. Reduce the on-resistance of the device and increase the output current; it has no significant impact on the threshold of N-channel devices.
  • the top P + type gallium nitride layer maintains a high doping concentration.
  • the high doping of the P + type gallium nitride layer is beneficial to the formation of ohmic contacts in the source and drain regions and reduces the contact resistance; in addition, in the P channel After the device is turned on, it provides a high hole concentration to increase the device output current.
  • the dielectric stack in the gate area, the aluminum nitrogen insertion layer and the underlying GaN generate a high concentration of two-dimensional electron gas due to the polarization effect, and the electron gas turns off the hole gas in the gate area; the gate metal and aluminum nitrogen are inserted between the layers There is a gate dielectric layer, and the use of a high band gap dielectric can further shut down the hole gas in the gate area; the gate dielectric stack can increase the threshold voltage of the P-channel device.
  • CMOS integration of N-channel and P-channel gallium nitride devices can be realized.
  • Figure 1 shows a schematic diagram of the integrated structure of traditional N-channel and P-channel gallium nitride power devices.
  • Figure 2 shows a schematic diagram of an integrated structure of enhancement mode N-channel and P-channel gallium nitride power devices according to an embodiment of the present invention.
  • Figure 3 shows a comparison chart of the same threshold data achieved under different P-GaN thicknesses in the gate region of a P-channel device according to an embodiment of the present invention and a traditional structure.
  • Figure 4 shows a comparison diagram of the output characteristic curves of a P-channel device according to an embodiment of the present invention and a traditional structure when the same threshold value is obtained with different P-GaN thicknesses in the gate region.
  • Figure 5 shows a comparison chart of the same threshold data achieved at different P-GaN thicknesses in the gate region of a P-channel device without an aluminum nitrogen insertion layer structure and a traditional structure according to an embodiment of the present invention.
  • Figure 6 shows a comparison diagram of the output characteristic curves of a P-channel device according to the present invention when the thickness of the P-GaN gate region is different and the same threshold value is obtained when the gate region of the P-channel device does not contain an aluminum nitrogen insertion layer and the traditional structure.
  • Figure 7 shows a comparison diagram of transfer characteristic curves between an embodiment of the structure of the present invention and a traditional structure of an N-channel device.
  • Figure 8 shows a comparison diagram of the output characteristic curves of an N-channel device according to an embodiment of the present invention and a traditional structure.
  • Figure 9 shows the energy band comparison diagram between the gate region and the gate-drain region of a traditional structure of a P-channel device.
  • Figure 10 shows the energy band diagram of the gate region when the threshold of an embodiment of the structure of the present invention is the same as that of the traditional structure of a P-channel device.
  • the figure includes: substrate 1, aluminum nitride nucleation layer 2, aluminum gallium nitride buffer layer 3, gallium nitride channel layer 4, aluminum gallium nitride barrier layer 5, first P-type gallium nitride layer 601, second P-type gallium nitride layer 602, first source electrode 7, first drain electrode 8, gate dielectric layer 9, first gate electrode 10, second source electrode 11, second drain electrode 12, second gate electrode 13, The first gallium nitride isolation layer 1401, the second gallium nitride isolation layer 1402, the first P + type gallium nitride layer 1501, the second P + type gallium nitride layer 1502, the aluminum nitrogen insertion layer 16, and the isolation layer 17.
  • An enhanced N-channel and P-channel GaN device integrated structure including: a substrate 1, an aluminum nitrogen nucleation layer 2 on the substrate 1, and an aluminum nitride gallium buffer on the aluminum nitrogen nucleation layer 2 Layer 3, a gallium nitride channel layer 4 is provided on the aluminum gallium nitride buffer layer 3, an aluminum gallium nitride barrier layer 5 is provided on the gallium nitride channel layer 4, and an aluminum gallium nitride barrier layer 5 is provided inside the aluminum gallium nitride barrier layer 5. There is an isolation layer 17 and it is deep into the gallium nitride channel layer 4.
  • the isolation layer 17 divides the aluminum gallium nitride barrier layer 5 and the gallium nitride channel layer 4 into two parts; There is a P-channel device.
  • the P-channel device includes a first P-type gallium nitride layer 601 provided on the aluminum gallium nitride barrier layer 5 on one side of the isolation layer 17.
  • the first P-type gallium nitride layer 601 A first gallium nitride isolation layer 1401 is provided on the first gallium nitride isolation layer 1401.
  • a first P + type gallium nitride layer 1501 is provided on the first P + type gallium nitride layer 1501.
  • the first gate electrode 10 is sunk into the first P + type gallium nitride layer 1501. Between the first gate electrode 10 and the first P + type gallium nitride layer 1501, A gate dielectric layer 9 is provided between the gallium nitride layers 1501; an N-channel device is provided on the other side of the isolation layer 17, and the N-channel device includes an aluminum gallium nitrogen potential on the other side of the isolation layer 17.
  • the second source electrode 11, the second P-type gallium nitride layer 602 and the second drain electrode 12 are on the barrier layer 5. The second source electrode 11 and the second drain electrode 12 are respectively located on the second P-type gallium nitride layer 602.
  • a second gallium nitride isolation layer 1402 is provided above the second P-type gallium nitride layer 602, and a second P + -type gallium nitride layer 1502 is provided above the second gallium nitride isolation layer 1402.
  • a second gate 13 is provided above the + -type gallium nitride layer 1502; the material of the substrate 1 is P-type silicon, sapphire or SiC, and the two-dimensional electron gas that conducts the N-channel device is located in the gallium nitride trench. In the channel layer 4, the two-dimensional hole gas that conducts the P-channel device is located in the first P-type gallium nitride layer 601.
  • the thickness of the aluminum gallium nitride barrier layer 5 is 12-25nm, and the aluminum composition is 0.15-0.3; Two-dimensional hole gas exists at the contact surface between the first P-type gallium nitride layer 601 and the first aluminum gallium nitride barrier layer 5 and is located in the first P-type gallium nitride 601 .
  • the groove shape of the gate area of the P-channel device, the gate dielectric layer 9 and the aluminum nitrogen insertion layer 16 can ensure that the two-dimensional hole gas in the gate area is disconnected, so that the P-channel device is an enhancement type; aluminum gallium nitrogen Two-dimensional electron gas exists at the contact surface between the barrier layer 5 and the gallium nitride channel layer 4 , and the two-dimensional electron gas is in the gallium nitride channel layer 4 .
  • the second P-type gallium nitride layer 602, the second gallium nitride isolation layer 1402 and the second P + -type gallium nitride layer 1502 ensure that the two-dimensional electron gas in the gate region is disconnected, so that the N-channel device is an enhancement mode .
  • the N-channel device is an enhancement mode
  • the first gate 10 and the gate dielectric layer 9 extend toward the first gallium nitride isolation layer 1401 and enter the first gallium nitride isolation layer 1401, and an aluminum nitrogen insertion layer 16 is provided on the lower surface of the gate dielectric layer 9.
  • the aluminum nitrogen insertion layer 16 is located below the first gate 10 , and the gate dielectric layer 9 extends and covers the side surfaces of the aluminum nitrogen insertion layer 16 .
  • the thickness of the first P-type gallium nitride layer 601 and the second P-type gallium nitride layer 602 is 10-15nm, and the doping concentration is 1.0 ⁇ 10 18 /cm 3 ⁇ 1.0 ⁇ 10 19 /cm 3 ; the first nitride The thickness of the gallium isolation layer 1401 and the second gallium nitride isolation layer 1402 is 30-40nm, and the doping concentration is 1.0 ⁇ 10 14 /cm 3 ⁇ 1.0 ⁇ 10 16 /cm 3 ; the first P + type gallium nitride layer 1501 The thickness of the second P + type gallium nitride layer 1502 is 20-35nm, the doping concentration is 1.0 ⁇ 10 19 /cm 3 ⁇ 1.0 ⁇ 10 20 /cm 3 , and the dopant is Mg or Be; the first The sum of the thicknesses of the gallium nitride isolation layer 1401 and the first P-type gallium nitride layer 601
  • One of the current main application scenarios for gallium nitride materials is to generate high-concentration two-dimensional electron gas (2DEG) at the heterojunction interface through the AlGaN/GaN heterojunction structure.
  • the two-dimensional electron gas has good high-frequency characteristics and is based on Two-dimensional electron gas designs high-performance gallium nitride circuits.
  • the design of GaN CMOS logic circuits lacks good P-channel devices that can be integrated with N-channel devices.
  • P-channel GaN HEMTs for example, in N-channel devices
  • the epitaxial structure of the channel gallium nitride HEMT is realized by a P-type gallium nitride layer, or by a two-dimensional hole gas generated by the polarization effect between gallium nitride and aluminum gallium nitrogen heterojunction, but these methods obtain P-channel devices have smaller current capabilities.
  • P-channel devices with small current capabilities will lead to excessively large CMOS logic circuit design areas and extremely poor performance; designing to increase the output current of P-channel devices is the focus of realizing gallium nitride CMOS circuits.
  • the present invention proposes a new structure based on the traditional structure;
  • Figure 1 shows a schematic diagram of a traditional structure implementing a gallium nitride CMOS logic circuit
  • Figure 2 shows an embodiment of the present invention implementing enhanced N Schematic diagram of channel and P-channel GaN device integration structures.
  • the present invention divides the traditional layer of P-GaN with the same doping concentration into three layers with different doping concentrations. The sum of the thicknesses of the three layers of P-GaN with different doping concentrations remains consistent with the traditional structure P-GaN. The three layers of P-GaN have different doping concentrations. The thickness of GaN takes different values according to requirements.
  • the two layers of P-GaN that remain in contact with the aluminum gallium nitride barrier layer and the ohmic metal layer are doped at a higher concentration, while the layer of P-GaN between the two layers of high-concentration P-GaN remains at a lower doping concentration. concentration, the highest doping concentration is P-GaN in contact with the ohmic metal layer.
  • the three-layer P-GaN configuration realizes P-channel gallium nitride devices on a compatible traditional N-channel P-GaN process, ensuring the enhancement mode of N-channel and P-channel devices respectively while maintaining a high output current, thus Realize the gallium nitride CMOS structure; the gate stack composed of an aluminum nitrogen insertion layer and a gate dielectric layer in the gate area of the P-channel device can further increase the threshold voltage of the P-channel device.
  • the thickness of the underlying P-GaN is 8-15nm, which provides a conduction channel in the conductive state of the P-channel device to conduct the existing ionized holes and polarized two-dimensional hole gas; due to the P-type doping Impurity has a certain hindering effect on the mobility of two-dimensional hole gas, so the doping of the P-type gallium nitride layer is kept slightly lower than the traditional doping.
  • the gate region contains a second P-type gallium nitride layer. The second P-type gallium nitride layer maintains the P-type doping effect like P-GaN of the traditional N-channel enhancement mode high electron mobility transistor.
  • FIG. 7 shows a comparison chart of the transfer characteristic curves of the N-channel device structure of the present invention and the traditional structure. It can be seen from the figure that the threshold value of the N-channel device of the structure of the present invention is not significantly lower than that of the traditional structure.
  • Figure 8 shows a comparison chart of the output characteristic curves of the structure of the present invention and the traditional structure of the N-channel device.
  • the slope of the linear region curve of the structure of the present invention is greater than that of the traditional structure, indicating that the on-resistance of the structure of the present invention of the N-channel device is slightly lower than that of the traditional structure. Decrease, the switching speed is fast.
  • the saturation current of the N-channel device of the structure of the present invention is basically consistent with that of the traditional structure.
  • the middle P-GaN layer maintains a very low doping concentration.
  • P-GaN with low doping concentration contains less hole concentration.
  • the bottom and left and right sides of the gate dielectric stack in the gate region are in contact with the gallium nitride isolation layer.
  • the smaller hole concentration can maintain a thicker GaN thickness under the gate dielectric stack, which makes the gate
  • the valence band at the GaN/AlGaN heterojunction in the polar region moves below the Fermi level, enabling the device to turn off.
  • Figure 9 shows the energy band comparison diagram between the gate region and the gate-drain region of the traditional structure.
  • FIG. 4 shows a P-channel device whose structure according to one embodiment of the present invention is different from the gate area of the traditional structure. P- Comparing the output characteristic curves when the GaN thickness reaches the same threshold, it can be seen that the output current of the present invention is significantly larger than the traditional structure under the same simulation environment.
  • the gate region of the P-channel device is formed by etching the top P-GaN of the gate region. During the etching process, as the etching depth increases, the two-dimensional space below will decrease.
  • the GaN under the gate of the present invention is thicker, that is, the etching depth is shallower, which can avoid the impact of etching on the mobility of two-dimensional hole gas, thereby increasing the device output current.
  • the top P + type gallium nitride layer maintain a high doping concentration of P-channel dopants such as Mg and Be. High doping is beneficial to the formation of ohmic contacts in the source and drain regions of P-channel devices and reduces contact resistance.
  • the highly doped P + type gallium nitride layer provides a higher hole concentration, which is beneficial to increasing the output current of the P-channel device.
  • the present invention adopts a method of combining an aluminum nitrogen insertion layer with a traditional gate dielectric layer to form a gate dielectric stack.
  • the high concentration of two-dimensional electron gas generated by the polarization effect between the aluminum nitrogen insertion layer and the underlying GaN can consume holes in the gate area P-GaN, thereby increasing the threshold voltage of the P-channel device;
  • Figure 5 shows the P-channel A comparison chart of the same threshold data achieved under different P-GaN thicknesses in the gate region of a channel device according to an embodiment of the present invention without aluminum nitrogen insertion layer structure and a traditional structure.
  • the GaN thickness in this embodiment remains the same as the structure in Figure 3.
  • the aluminum nitrogen insertion layer significantly increases the device threshold voltage.
  • the second step is the gate dielectric layer of a traditional P-channel device with a certain thickness.
  • the gate dielectric layer is made of high-bandgap dielectrics such as aluminum oxide, silicon oxide, and silicon nitride.
  • this type of dielectric can further reduce the cost band of the heterojunction. height, achieving an increase in the device threshold voltage.
  • the high bandgap width can withstand higher voltages and increase the gate withstand voltage.
  • Figure 6 shows a comparison diagram of the output characteristic curves of the P-channel device in the present invention without aluminum nitrogen insertion layer structure and the traditional structure when the thickness of the P-GaN gate region is different and the same threshold value is obtained.
  • the three layers have different doping concentrations.
  • the setting of P-GaN can obviously retain thicker GaN in the gate area in P-channel devices, thereby reducing the device on-resistance.
  • the P-type gallium nitride layer 602 and the P + -type gallium nitride layer 1502 contain holes to turn off the electron gas under the aluminum gallium nitride barrier layer 5 of the N-channel device to ensure the enhanced mode of the N-channel device.
  • the gallium nitride isolation layer 1401 and the gate dielectric layer 9 reduce holes generated by polarization in the P-type gallium nitride layer 601 of the P-channel device, while the aluminum nitrogen insertion layer 16 and the gallium nitride isolation layer 1401 generate electron gas.
  • both the P-type gallium nitride layer 601 and the P + -type gallium nitride layer 1501 provide holes after the P-channel device is turned on.
  • the P + -type gallium nitride layer 1501 provides a high concentration of holes.
  • the gallium nitride isolation layer 1401 ensures that the conduction channel has a larger area; a higher hole concentration and a larger channel area can result in a smaller conduction resistance.
  • the high hole concentration ensures that the ohmic contact resistance between the first source electrode 7 and the first drain electrode 8 and the P + type gallium nitride layer 1501 is smaller; the output of the P-channel device of the present invention under the dual effects of small on-resistance and small contact resistance The current is higher.
  • the output current of the structure of the present invention in Figures 4 and 6 is increased by 43% and 71% respectively.
  • the high output current P-channel device will greatly reduce the area of the CMOS logic gallium nitride circuit.
  • the present invention not only ensures the enhanced operation of N-channel and P-channel gallium nitride devices, but also improves the output current of the P-channel device; at the same time, the present invention is different from the traditional P-type gallium nitride type (P- GaN) high electron mobility transistor process is compatible and has great practicality; it is of great significance to the realization of high-performance gallium nitride CMOS logic circuits.
  • P- GaN P-type gallium nitride type

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Abstract

一种增强型N沟道和P沟道GaN器件集成结构，包括衬底，在衬底上依次设铝氮成核层、铝氮镓缓冲层、氮化镓沟道层和铝镓氮势垒层，铝镓氮势垒层和氮化镓沟道层被隔离层分割；隔离层一侧设有P沟道器件，包括第一P型氮化镓层，在第一P型氮化镓层上依次设第一氮化镓隔离层和第一P+型氮化镓层，在第一P+型氮化镓层上设第一源、栅极和第一漏极，第一栅极陷入第一P+型氮化镓层，其间设有栅极介质层；在隔离层的另一侧设有N沟道器件，包括第二源极、第二P型氮化镓层和第二漏极，第二源、漏极分别位于第二P型氮化镓层的两侧，在第二P型氮化镓层上方依次设有第二氮化镓隔离层、第二P+型氮化镓层和第二栅极。

Description

一种增强型N沟道和P沟道GaN器件集成结构 技术领域
本发明主要涉及氮化镓功率半导体集成技术领域，具体来说，是一种增强型N沟道和P沟道GaN器件集成结构。
背景技术
宽带隙半导体电子器件可用于要求高工作电压/速度和低功率损耗以及耐受恶劣工作条件的任务中。在这种器件中，宽能带隙抑制了从价带到导带的自发电子跃迁，这种跃迁可能被高电场、高温和高能粒子的环境能量激活。这使得器件能够在各种极端情况下保持其电气特性。氮化镓是一种关键的宽带隙半导体，最流行的器件结构是基于平面异质结的高电子迁移率晶体管(HEMT)。氮化镓HEMT在二维电子气(2DEG)通道中提供高电子迁移率和小终端电容，使其特别适合高频/高功率密度应用，如射频功率放大器和紧凑型功率转换器/电源。
使用硅兼容工艺设备在大硅衬底上制造的氮化镓HEMT已经被开发用于电力电子，这导致了具有高电压阻断能力增强模式操作以及长期操作中的优异稳定性和可靠性的电力开关器件的发展。作为功率开关器件，分立氮化镓HEMT已被用于调节几十安培的电流，并阻挡高达约1kV(千伏)的高电压。这些核心器件需要外围电路作为驱动、控制、检测和保护模块。单片集成有利于创建更多的片上功能、增强鲁棒性并促进整个功率转换系统的小型化。氮化镓HEMT具有平面配置，其中所有三个器件端(源极、栅极和漏极)都位于顶部表面上。这种配置有利于高密度集成，这种集成导致了集成栅极驱动器的氮化镓功率开关的商业发展。然而，所有这些氮化镓集成电路都是基于以电子作为多数载流子的N沟道器件。
氮化镓功率器件的外围电路通常由数量可观的逻辑模块组成。对于硅基逻辑电路，互补逻辑金属氧化物半导体(CMOS)拓扑占主导地位，因为它为超大规模集成电路和混合信号集成电路提供了最节能的方案。尽管氮化镓基器件发展迅速并已商业化，但实际氮化镓CMOS电路的开发仍充满挑战。这尤其是由于缺乏合适的集成策略来同时结合增强型N沟道器件和P沟道器件。商用P-GaN栅极功率HEMT平台(基于生长在硅衬底上的P-GaN/AlGaN/GaN异质结)对于实现用于功率开关的逻辑控制的单片集成互补逻辑电路是有希望的，因为增强型N沟道器件是容易获得的，并且P-GaN层为P沟道器件提供了引人注目的场所。通过使用栅极凹槽等处理技术，增强模式P沟道器件的性能得到了改善。尽管氮化镓中电子和空穴的大迁移率失配(几乎两个数量级)不支 持氮化镓作为高速先进CMOS的最佳候选，氮化镓功率开关的逻辑控制要求较低的操作速度(在100kHz-10MHz范围内)，这为氮化镓片上互补逻辑集成电路在“全氮化镓”片上系统功率电子解决方案中提供了一个可行的机会。
发明内容
针对上述问题，本发明提出一种增强型N沟道和P沟道GaN器件集成结构，本发明结构能够在使用传统N沟道氮化镓HEMT工艺的基础上保证N沟道器件的增强型同时很好的提高P沟道氮化镓HEMT的输出电流和阈值电压。
本发明采用如下技术方案：
一种增强型N沟道和P沟道GaN器件集成结构，包括：衬底，在衬底上设有铝氮成核层，在铝氮成核层上设有铝氮镓缓冲层，在铝氮镓缓冲层上设有氮化镓沟道层，在氮化镓沟道层上设有铝镓氮势垒层，在铝镓氮势垒层内设有隔离层且深及氮化镓沟道层内，所述隔离层将铝镓氮势垒层和氮化镓沟道层分割为两部分；在隔离层的一侧设有P沟道器件，所述P沟道器件包括设在隔离层一侧的铝镓氮势垒层上的第一P型氮化镓层，在第一P型氮化镓层上设有第一氮化镓隔离层，在第一氮化镓隔离层上设有第一P +型氮化镓层，在第一P +型氮化镓层上设有第一源极、第一栅极和第一漏极，所述第一栅极陷入所述第一P +型氮化镓层，在第一栅极与第一P +型氮化镓层之间设有栅极介质层；在隔离层的另一侧设有N沟道器件，所述N沟道器件包括设在隔离层另一侧的铝镓氮势垒层上的第二源极、第二P型氮化镓层和第二漏极，第二源极、第二漏极分别位于第二P型氮化镓层的两侧，在第二P型氮化镓层上方设有第二氮化镓隔离层，第二氮化镓隔离层上方设有第二P +型氮化镓层，第二P +型氮化镓层上方设有第二栅极。
与现有技术相比，本发明具有如下有益效果：
从上述技术方案可以看出，本发明主要将P-GaN分成三个不同掺杂浓度的层次，保持与铝镓氮势垒层接触和与欧姆金属层接触的两层P-GaN掺杂浓度较高，而这两层高浓度P-GaN之间的一层P-GaN保持较低的掺杂浓度；P沟道器件栅极区域铝氮插入层和栅极介质层组成栅介质叠层。可至少实现以下有益效果：
1，底层P型氮化镓层一方面在P沟道器件中提供导通通道，P型掺杂下提供一定浓度空穴，器件开启后增加输出电流；另一方面在N沟道器件中底层P型氮化镓层提供的空穴关断铝镓氮势垒层下方的二维电子气，保证N沟道器件的增强型。
2，中间氮化镓隔离层保持低的掺杂浓度，在P沟道器件中栅极区域下方的GaN中空穴 浓度低，更容易实现关断，在阈值一定时可通过增加栅下GaN厚度，减少器件导通电阻，增加输出电流；对于N沟道器件的阈值无明显影响。
3，顶层P +型氮化镓层保持一个高掺杂浓度，对于P沟道器件P +型氮化镓层高掺杂利于源漏区欧姆接触的形成减小接触电阻；另外在P沟道器件导通后提供高空穴浓度从而提高器件输出电流。
4，栅极区域介质叠层，铝氮插入层与下方GaN由于极化效应产生高浓度的二维电子气，电子气关断栅极区域的空穴气；栅极金属与铝氮插入层间有一层栅极介质层，采取高禁带宽度的介质可进一步关断栅极区域空穴气；栅极介质叠层实现提高P沟道器件的阈值电压。
5，可实现N沟道与P沟道氮化镓器件的CMOS集成。
附图说明
图1所示为传统N沟道和P沟道氮化镓功率器件集成结构的示意图。
图2所示为本发明增强型N沟道和P沟道氮化镓功率器件集成结构的一实施例示意图。
图3所示为P沟道器件本发明结构一实施例与传统结构栅极区域不同P-GaN厚度下实现相同阈值数据对比图。
图4所示为P沟道器件本发明结构一实施例与传统结构栅极区域不同P-GaN厚度得到相同阈值时的输出特性曲线对比图。
图5所示为P沟道器件本发明中一实施例不含铝氮插入层结构与传统结构栅极区域不同P-GaN厚度下实现的相同阈值数据对比图。
图6所示为P沟道器件本发明中一实施例不含铝氮插入层结构与传统结构栅极区域不同P-GaN厚度得到相同阈值时的输出特性曲线对比图。
图7所示为N沟道器件本发明结构一实施例与传统结构转移特性曲线对比图。
图8所示为N沟道器件本发明结构一实施例与传统结构输出特性曲线对比图。
图9所示为P沟道器件传统结构栅极区域与栅漏间区域能带对比图。
图10所示为P沟道器件本发明结构一实施例与传统结构相同阈值时栅极区域能带图。
图中有：衬底1，铝氮成核层2，铝镓氮缓冲层3，氮化镓沟道层4，铝镓氮势垒层5，第一P型氮化镓层601，第二P型氮化镓层602，第一源极7，第一漏极8，栅极介质层9，第一栅极10，第二源极11，第二漏极12，第二栅极13，第一氮化镓隔离层1401，第二氮化镓隔离层1402，第一P +型氮化镓层1501，第二P +型氮化镓层1502，铝氮插入层16，隔离层17。
具体实施方式
一种增强型N沟道和P沟道GaN器件集成结构，包括：衬底1，在衬底1上设有铝氮成核层2，在铝氮成核层2上设有铝氮镓缓冲层3，在铝氮镓缓冲层3上设有氮化镓沟道层4，在氮化镓沟道层4上设有铝镓氮势垒层5，在铝镓氮势垒层5内设有隔离层17且深及氮化镓沟道层4内，所述隔离层17将铝镓氮势垒层5和氮化镓沟道层4分割为两部分；在隔离层17的一侧设有P沟道器件，所述P沟道器件包括设在隔离层17一侧的铝镓氮势垒层5上的第一P型氮化镓层601，在第一P型氮化镓层601上设有第一氮化镓隔离层1401，在第一氮化镓隔离层1401上设有第一P +型氮化镓层1501，在第一P +型氮化镓层1501上设有第一源极7、第一栅极10和第一漏极8，所述第一栅极10陷入所述第一P +型氮化镓层1501，在第一栅极10与第一P +型氮化镓层1501之间设有栅极介质层9；在隔离层17的另一侧设有N沟道器件，所述N沟道器件包括设在隔离层17另一侧的铝镓氮势垒层5上的第二源极11、第二P型氮化镓层602和第二漏极12，第二源极11、第二漏极12分别位于第二P型氮化镓层602的两侧，在第二P型氮化镓层602上方设有第二氮化镓隔离层1402，第二氮化镓隔离层1402上方设有第二P +型氮化镓层1502，第二P +型氮化镓层1502上方设有第二栅极13；其中，衬底1的材料为P型硅、蓝宝石或SiC等材料，导通N沟道器件的二维电子气位于氮化镓沟道层4内，导通P沟道器件的二维空穴气位于第一P型氮化镓层601内，铝镓氮势垒层5厚度为12-25nm，铝组分为0.15-0.3；第一P型氮化镓层601和第一铝镓氮势垒层5的接触面存在二维空穴气，且位于第一P型氮化镓601内。P沟道器件栅极区域的凹槽形状、栅极介质层9与铝氮插入层16，可以确保栅极区域的二维空穴气断开，这样P沟道器件就是增强型；铝镓氮势垒层5与氮化镓沟道层4的接触面存在二维电子气，且二维电子气在氮化镓沟道层4内。第二P型氮化镓层602、第二氮化镓隔离层1402与第二P +型氮化镓层1502，确保栅极区域的二维电子气断开，这样N沟道器件就是增强型。在本实施例中，
第一栅极10及栅极介质层9向第一氮化镓隔离层1401延伸并进入第一氮化镓隔离层1401，并在栅极介质层9的下表面设有铝氮插入层16，所述铝氮插入层16位于第一栅极10的下方，所述栅极介质层9再延伸并包覆于铝氮插入层16的侧面。
第一P型氮化镓层601和第二P型氮化镓层602的厚度为10-15nm、掺杂浓度为1.0×10 18/cm 3～1.0×10 19/cm 3；第一氮化镓隔离层1401和第二氮化镓隔离层1402的厚度为30-40nm、掺杂浓度为1.0×10 14/cm 3～1.0×10 16/cm 3；第一P +型氮化镓层1501和第二P +型氮化镓层1502的厚度为20-35nm、掺杂浓度为1.0×10 19/cm 3～1.0×10 20/cm 3，掺杂剂为Mg或Be；所述第一氮化镓隔离层1401与第一P型氮化镓层601的厚度之和为20nm～50nm；所述铝氮插入层16厚度为5-15nm；所述栅极介质层9厚度为5-10nm，栅极介质层9材料为氧化铝、氧化硅或氮化硅。
下面结合附图对本发明进行进一步说明。
本发明的工作原理：
对于氮化镓材料目前一个主要的应用场景就是通过AlGaN/GaN异质结结构在异质结界面产生高浓度的二维电子气(2DEG)，二维电子气具有很好的高频特性，基于二维电子气设计性能优异的氮化镓电路。但设计氮化镓CMOS逻辑电路缺少与N沟道器件可集成的良好P沟道器件，目前国内外研究机构的设计方案中，针对P沟道氮化镓HEMT，采取以下方式实现：比如在N沟道氮化镓HEMT的外延结构上通过P型氮化镓层实现，或通过氮化镓和铝镓氮异质结间的极化效应产生的二维空穴气实现，但这些方法获得的P沟道器件的电流能力都较小。小电流能力的P沟道器件将导致CMOS逻辑电路设计的面积过大，性能极差；设计提高P沟道器件的输出电流是实现氮化镓CMOS电路的重点。
本发明在传统结构的基础上，提出了一种新的结构；其中图1所示为传统结构实现氮化镓CMOS逻辑电路的示意图，图2为本发明的其中一种实施例实现增强型N沟道和P沟道GaN器件集成结构的示意图。本发明将传统相同掺杂浓度的一层P-GaN分成三个不同掺杂浓度的层次，三层不同掺杂浓度的P-GaN厚度之和与传统结构P-GaN保持一致，三层P-GaN的厚度按照需求分别取不同数值。保持与铝镓氮势垒层接触和与欧姆金属层接触的两层P-GaN掺杂浓度较高，而这两层高浓度P-GaN之间的一层P-GaN保持较低的掺杂浓度，其中掺杂浓度最高的是与欧姆金属层接触的P-GaN。三层P-GaN的设置在兼容传统N沟道P-GaN工艺上实现P沟道氮化镓器件，分别保证N沟道和P沟道器件的增强型、同时保持较高的输出电流，从而实现氮化镓CMOS结构；P沟道器件栅极区域铝氮插入层和栅极介质层组成栅叠层可进一步提高P沟道器件阈值电压。
首先底层的P-GaN厚度为8-15nm，在P沟道器件中导通状态下提供一个导通通道，导通本身存在的电离空穴与极化的二维空穴气；由于P型掺杂对二维空穴气的迁移率有一定阻碍作用，所以保持P型氮化镓层掺杂较传统掺杂略低。在N沟道器件中栅极区域含有第二P型氮化镓层，第二P型氮化镓层保持的P型掺杂作用如传统N沟道增强型高电子迁移率晶体管的P-GaN层，该层可以抬升整个异质结的导带从而耗尽异质结导电沟道(氮化镓沟道层)中的2DEG，保证N沟道器件的增强型。图7展示了N沟道器件本发明结构与传统结构转移特性曲线对比图，图中可以看出本发明结构的N沟道器件阈值相对传统结构没有明显降低。图8所示为N沟道器件本发明结构与传统结构输出特性曲线对比图，本发明结构的线性区曲线 斜率大于传统结构，说明N沟道器件本发明结构的导通电阻较传统结构略有减小，开关速度快。本发明结构的N沟道器件的饱和电流与传统结构基本一致。
其次中间的P-GaN层(氮化镓隔离层)保持非常低的掺杂浓度，掺杂浓度低的P-GaN中含有较少的空穴浓度。P沟道器件中栅极区域栅介质叠层的下方及左右两侧与氮化镓隔离层接触，较少的空穴浓度可以维持栅介质叠层下方的GaN具有更厚的厚度时就使得栅极区域GaN/AlGaN异质结处的价带移至费米能级以下，实现器件的关断。图9中为传统结构的栅极区域与栅漏间区域的能带对比图，可以看到更厚的GaN层将导致GaN/AlGaN异质结处价带明显高于费米能级，即器件为耗尽型工作模式，不利于安全工作。如图10所示的能带图，异质结处相同价带高度时本发明结构栅极区域GaN更厚；如图3所示为P沟道器件本发明结构与传统结构栅极区域GaN具有不同厚度实现相同阈值的数据对比图，结果进一步证明了图10的结论即同一阈值下本发明可增加栅极区域的GaN厚度。P沟道器件栅极区域下方的GaN厚度更厚将减小器件导通电阻，增加器件输出电流，图4所示为P沟道器件本发明结构一实施例与传统结构栅极区域不同P-GaN厚度得到相同阈值时的输出特性曲线对比图，可以看到在相同仿真环境下本发明的输出电流明显大于传统结构。对于本发明的一个具体实施例，传统方法中形成P沟道器件的栅极区域是通过刻蚀栅极区域的顶部P-GaN，刻蚀过程中随刻蚀深度增加将会降低下方二维空穴气的迁移率，本发明栅极下方的GaN更厚即刻蚀深度较浅，可以避免刻蚀对二维空穴气迁移率的影响，从而实现增加器件输出电流。
而对于顶层P +型氮化镓层保持一个Mg、Be等P沟道掺杂剂的高掺杂浓度，高掺杂利于P沟道器件源漏区欧姆接触的形成减小接触电阻，另外在器件导通后高掺杂浓度的P +型氮化镓层提供更高空穴浓度有利于提高P沟道器件输出电流。
此外，对于栅极区域介质层，本发明采取铝氮插入层与传统栅介质层结合组成栅介质叠层的方式。首先铝氮插入层与下方GaN由于极化效应产生高浓度的二维电子气可以消耗栅极区域P-GaN中的空穴，实现提高P沟道器件的阈值电压；图5所示为P沟道器件本发明中一实施例不含铝氮插入层结构与传统结构栅极区域不同P-GaN厚度下实现的相同阈值数据对比图，该实施例GaN厚度分别保持与图3结构相同，对比可知铝氮插入层明显增加器件阈值电压。其次是一定厚度传统P沟道器件栅极介质层，栅介质层材料采取氧化铝、氧化硅、氮化硅等高禁带宽度的介质；该类介质一方面可进一步降低异质结处价带高度、实现增加器件阈值电压，一方面由于高禁带宽度可承受更高的电压、增加栅极耐压。
图6所示为P沟道器件本发明中不含铝氮插入层结构与传统结构栅极区域不同P-GaN厚度得到相同阈值时的输出特性曲线对比图，本发明中三层不同掺杂浓度P-GaN的设置在P沟道器件中可明显保留栅极区域更厚的GaN，从而减小器件导通电阻。
N沟道与P沟道器件均为增强型模式工作是电力电子技术安全要求，也是本发明设计的基础。本发明中P型氮化镓层602与P +型氮化镓层1502，两层内含有的空穴关断N沟道器件铝镓氮势垒层5下方电子气保证N沟道器件增强型；氮化镓隔离层1401与栅极介质层9减小P沟道器件P型氮化镓层601中极化产生的空穴，同时铝氮插入层16与氮化镓隔离层1401产生电子气与P型氮化镓层601中的空穴形成电中性，实现P沟道器件的增强型操作。对于P沟道器件，P型氮化镓层601与P +型氮化镓层1501在P沟道器件导通后均提供空穴，尤其是P +型氮化镓层1501提供高浓度的空穴，氮化镓隔离层1401保证导通沟道具有更大的面积；更高的空穴浓度，更大的沟道面积可以得到更小的导通电阻。高空穴浓度保证第一源极7和第一漏极8与P +型氮化镓层1501的欧姆接触电阻更小；小导通电阻和小接触电阻双重效应下本发明的P沟道器件输出电流更高，图4和图6本发明结构的输出电流分别提高了43％和71％，高输出电流的P沟道器件将极大的减小CMOS逻辑氮化镓电路的面积。
综上所述，本发明即保证了N沟道与P沟道氮化镓器件的增强型操作，又提高了P沟道器件输出电流；同时本发明与传统P型氮化镓型(P-GaN)高电子迁移率晶体管工艺兼容，具有很大实用性；对实现高性能氮化镓CMOS逻辑电路具有重大意义。

Claims (6)

  1. 一种增强型N沟道和P沟道GaN器件集成结构，包括：衬底(1)，在衬底(1)上设有铝氮成核层(2)，在铝氮成核层(2)上设有铝氮镓缓冲层(3)，在铝氮镓缓冲层(3)上设有氮化镓沟道层(4)，在氮化镓沟道层(4)上设有铝镓氮势垒层(5)，其特征在于，在铝镓氮势垒层(5)内设有隔离层(17)且深及氮化镓沟道层(4)内，所述隔离层(17)将铝镓氮势垒层(5)和氮化镓沟道层(4)分割为两部分；在隔离层(17)的一侧设有P沟道器件，所述P沟道器件包括设在隔离层(17)一侧的铝镓氮势垒层(5)上的第一P型氮化镓层(601)，在第一P型氮化镓层(601)上设有第一氮化镓隔离层(1401)，在第一氮化镓隔离层(1401)上设有第一P +型氮化镓层(1501)，在第一P +型氮化镓层(1501)上设有第一源极(7)、第一栅极(10)和第一漏极(8)，所述第一栅极(10)陷入所述第一P +型氮化镓层(1501)，在第一栅极(10)与第一P +型氮化镓层(1501)之间设有栅极介质层(9)；在隔离层(17)的另一侧设有N沟道器件，所述N沟道器件包括设在隔离层(17)另一侧的铝镓氮势垒层(5)上的第二源极(11)、第二P型氮化镓层(602)和第二漏极(12)，第二源极(11)、第二漏极(12)分别位于第二P型氮化镓层(602)的两侧，在第二P型氮化镓层(602)上方设有第二氮化镓隔离层(1402)，第二氮化镓隔离层(1402)上方设有第二P +型氮化镓层(1502)，第二P +型氮化镓层(1502)上方设有第二栅极(13)。
  2. 根据权利要求1所述的增强型N沟道和P沟道GaN器件集成结构，其特征在于，第一栅极(10)及栅极介质层(9)向第一氮化镓隔离层(1401)延伸并进入第一氮化镓隔离层(1401)，并在栅极介质层(9)的下表面设有铝氮插入层(16)，所述铝氮插入层(16)位于第一栅极(10)的下方，所述栅极介质层(9)再延伸并包覆于铝氮插入层(16)的侧面。
  3. 根据权利要求1或2所述的一种增强型N沟道和P沟道GaN器件集成结构，其特征在于，第一P型氮化镓层(601)和第二P型氮化镓层(602)的厚度为10-15nm、掺杂浓度为1.0×10 18/cm 3～1.0×10 19/cm 3；第一氮化镓隔离层(1401)和第二氮化镓隔离层(1402)的厚度为30-40nm、掺杂浓度为1.0×10 14/cm 3～1.0×10 16/cm 3；第一P +型氮化镓层(1501)和第二P +型氮化镓层(1502)的厚度为20-35nm、掺杂浓度为1.0×10 19/cm 3～1.0×10 20/cm 3，掺杂剂为Mg或Be。
  4. 根据权利要求2所述的一种增强型N沟道和P沟道GaN器件集成结构，其特征在于，所述第一氮化镓隔离层(1401)与第一P型氮化镓层(601)的厚度之和为20nm～50nm。
  5. 根据权利要求2所述的一种增强型N沟道和P沟道GaN器件集成结构，其特征在于，所述铝氮插入层(16)厚度为5-15nm。
  6. 根据权利要求1所述的一种增强型N沟道和P沟道GaN器件集成结构，其特征在于，所述栅极介质层(9)厚度为5-10nm，栅极介质层(9)材料为氧化铝、氧化硅或氮化硅。
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