WO2023233766A1 - 半導体装置および半導体装置の製造方法 - Google Patents

半導体装置および半導体装置の製造方法 Download PDF

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Publication number
WO2023233766A1
WO2023233766A1 PCT/JP2023/010900 JP2023010900W WO2023233766A1 WO 2023233766 A1 WO2023233766 A1 WO 2023233766A1 JP 2023010900 W JP2023010900 W JP 2023010900W WO 2023233766 A1 WO2023233766 A1 WO 2023233766A1
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Prior art keywords
layer
metal film
semiconductor device
barrier layer
composite layer
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French (fr)
Japanese (ja)
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拓真 南條
達郎 綿引
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Mitsubishi Electric Corp
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Mitsubishi Electric Corp
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Priority to US18/868,177 priority Critical patent/US20250359126A1/en
Priority to JP2024524187A priority patent/JPWO2023233766A1/ja
Priority to CN202380041010.7A priority patent/CN119213571A/zh
Publication of WO2023233766A1 publication Critical patent/WO2023233766A1/ja
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/40—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels
    • H10D30/47—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having two-dimensional [2D] charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
    • H10D30/471—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT]
    • H10D30/475—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT] having wider bandgap layer formed on top of lower bandgap active layer, e.g. undoped barrier HEMTs such as i-AlGaN/GaN HEMTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/015—Manufacture or treatment of FETs having heterojunction interface channels or heterojunction gate electrodes, e.g. HEMT
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/82—Heterojunctions
    • H10D62/824—Heterojunctions comprising only Group III-V materials heterojunctions, e.g. GaN/AlGaN heterojunctions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/012—Manufacture or treatment of electrodes comprising a Schottky barrier to a semiconductor
    • H10D64/0124—Manufacture or treatment of electrodes comprising a Schottky barrier to a semiconductor to Group III-V semiconductors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/62—Electrodes ohmically coupled to a semiconductor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/64—Electrodes comprising a Schottky barrier to a semiconductor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/40—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels
    • H10D30/47—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having two-dimensional [2D] charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
    • H10D30/471—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT]
    • H10D30/473—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT] having confinement of carriers by multiple heterojunctions, e.g. quantum well HEMT
    • H10D30/4732—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT] having confinement of carriers by multiple heterojunctions, e.g. quantum well HEMT using Group III-V semiconductor material
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/85—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group III-V materials, e.g. GaAs
    • H10D62/8503—Nitride Group III-V materials, e.g. AlN or GaN
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/012—Manufacture or treatment of electrodes comprising a Schottky barrier to a semiconductor
    • H10D64/0124—Manufacture or treatment of electrodes comprising a Schottky barrier to a semiconductor to Group III-V semiconductors
    • H10D64/0125—Manufacture or treatment of electrodes comprising a Schottky barrier to a semiconductor to Group III-V semiconductors characterised by the sectional shape, e.g. T or inverted T

Definitions

  • the present disclosure relates to a semiconductor device, and particularly relates to a heterojunction field effect semiconductor device made of a semiconductor containing nitride.
  • heterojunction field effect transistor An example of a conventional heterojunction field effect semiconductor device made of a semiconductor containing nitride (nitride semiconductor) is a heterojunction field effect transistor disclosed in Patent Document 1, for example.
  • the heterojunction field effect transistor includes an AlGaN/GaN heterojunction having a channel layer of GaN (gallium nitride) and a barrier layer of AlGaN (aluminum gallium nitride).
  • An ohmic electrode made of a metal film such as Ti (titanium), Al (aluminum), Mo (molybdenum), or a metal multilayer film or alloy film containing these is provided on the barrier layer, and is used as a drain electrode of the transistor. It constitutes a source electrode.
  • These ohmic electrodes are covered with an insulating film made of SiN (silicon nitride) or SiO 2 (silicon oxide), and a contact hole is formed by opening the insulating film so that a part of the top surface is exposed.
  • the configuration is such that it is connected to the wiring for connection to.
  • ohmic electrodes are made by depositing a metal film (including metal multilayer films and alloy films) on a semiconductor layer, then heat-treating it, and then depositing a SiN film to cover the heat-treated metal film. It is formed.
  • a metal film including metal multilayer films and alloy films
  • ohmic electrodes such as source electrodes, drain electrodes, and cathode electrodes used in semiconductor devices such as transistors and diodes formed on semiconductor layers containing AlGaN/GaN heterojunctions
  • resistance can be added to improve the performance of semiconductor devices. It is desirable that it be as low as possible.
  • a metal film is deposited on a semiconductor layer and then heat treated at a high temperature generally exceeding 600° C. to form an alloy with the semiconductor layer. Thereafter, in order to protect the surface of the semiconductor layer, a surface protection film such as SiN is formed, and the metal film is also covered at the same time.
  • a surface protection film such as SiN is formed, and the metal film is also covered at the same time.
  • part of the metal film will evaporate and re-deposit in areas other than those where the electrodes are formed, resulting in a gap between the semiconductor layer and the protective film. This may result in a state in which the semiconductor device is left behind, which may have a negative impact on various characteristics of the semiconductor device.
  • a high-temperature heat treatment is performed with a cap film such as SiN, which has low reactivity with the metal film, deposited to cover the metal film, and then the cap film is removed.
  • a process for depositing and then removing the cap film is added, the manufacturing process becomes complicated and the manufacturing cost increases.
  • the present disclosure has been made to solve the above-mentioned problems, and aims to provide a semiconductor device that does not reduce the characteristics of the semiconductor device and suppresses the complexity of the manufacturing process.
  • a semiconductor device includes a semiconductor substrate, a channel layer provided on the semiconductor substrate and made of a first nitride semiconductor, and a channel layer provided on the channel layer and made of a first nitride semiconductor.
  • a composite layer including at least a conductive material and an insulating material, and an insulating film formed on the barrier layer in a region where the metal film and the composite layer are not formed.
  • the semiconductor device According to the semiconductor device according to the present disclosure, it is possible to obtain a semiconductor device in which the characteristics as a semiconductor device are not deteriorated and the complexity of the manufacturing process is suppressed.
  • FIG. 1 is a cross-sectional view showing the configuration of a semiconductor device according to a first embodiment of the present disclosure.
  • FIG. 2 is a diagram schematically showing the flow of current in the semiconductor device of Embodiment 1 according to the present disclosure.
  • 1 is a cross-sectional view showing a method for manufacturing a semiconductor device according to a first embodiment of the present disclosure;
  • FIG. 1 is a cross-sectional view showing a method for manufacturing a semiconductor device according to a first embodiment of the present disclosure;
  • FIG. 1 is a cross-sectional view showing a method for manufacturing a semiconductor device according to a first embodiment of the present disclosure;
  • FIG. 1 is a cross-sectional view showing a method for manufacturing a semiconductor device according to a first embodiment of the present disclosure;
  • FIG. 1 is a cross-sectional view showing a method for manufacturing a semiconductor device according to a first embodiment of the present disclosure;
  • FIG. 1 is a cross-sectional view showing a method for manufacturing a semiconductor device according
  • FIG. 1 is a cross-sectional view showing a method for manufacturing a semiconductor device according to a first embodiment of the present disclosure
  • FIG. FIG. 2 is a cross-sectional view showing the configuration of a semiconductor device according to a second embodiment of the present disclosure
  • 7 is a cross-sectional view showing a method for manufacturing a semiconductor device according to a second embodiment of the present disclosure.
  • FIG. FIG. 3 is a cross-sectional view showing the configuration of a semiconductor device according to a third embodiment of the present disclosure.
  • 7 is a cross-sectional view showing a method for manufacturing a semiconductor device according to a third embodiment of the present disclosure.
  • FIG. 7 is a cross-sectional view showing a method for manufacturing a semiconductor device according to a third embodiment of the present disclosure.
  • FIG. 7 is a cross-sectional view showing a method for manufacturing a semiconductor device according to a third embodiment of the present disclosure.
  • FIG. 7 is a cross-sectional view showing a method for manufacturing a semiconductor device according to a third embodiment of the present disclosure.
  • FIG. 7 is a cross-sectional view showing a method for manufacturing a semiconductor device according to a third embodiment of the present disclosure.
  • FIG. 7 is a cross-sectional view showing a method for manufacturing a semiconductor device according to a third embodiment of the present disclosure.
  • FIG. 7 is a cross-sectional view showing a method for manufacturing a semiconductor device according to a third embodiment of the present disclosure.
  • FIG. 7 is a cross-sectional view showing the configuration of a semiconductor device according to a fourth embodiment of the present disclosure.
  • FIG. FIG. 7 is a cross-sectional view showing a method for manufacturing a semiconductor device according to a fourth embodiment of the present disclosure.
  • FIG. 7 is a cross-sectional view showing the configuration of a semiconductor device according to a fifth embodiment of the present disclosure.
  • FIG. FIG. 7 is a cross-sectional view showing a method for manufacturing a semiconductor device according to a fifth embodiment of the present disclosure.
  • FIG. 7 is a cross-sectional view showing a method for manufacturing a semiconductor device according to a fifth embodiment of the present disclosure.
  • FIG. 7 is a cross-sectional view showing a method for manufacturing a semiconductor device according to a fifth embodiment of the present disclosure.
  • FIG. 7 is a cross-sectional view showing a method for manufacturing a semiconductor device according to a fifth embodiment of the present disclosure.
  • FIG. 7 is a cross-sectional view showing a method for manufacturing a semiconductor device according to a fifth embodiment of the present disclosure.
  • FIG. 7 is a cross-sectional view showing a method for manufacturing a semiconductor device according to a fifth embodiment of the present disclosure.
  • FIG. 7 is a cross-sectional view showing a method for manufacturing a semiconductor device according to a fifth embodiment of the present disclosure.
  • FIG. 7 is a cross-sectional view showing a method for manufacturing a semiconductor device according to a fifth embodiment of the present disclosure.
  • 7 is a cross-sectional view showing the configuration of a semiconductor device according to a sixth embodiment of the present disclosure.
  • FIG. 7 is a cross-sectional view showing a method for manufacturing a semiconductor device according to a sixth embodiment of the present disclosure.
  • FIG. 12 is a cross-sectional view showing a semiconductor device according to a seventh embodiment of the present disclosure in a state where a metal film and an insulating film are not formed.
  • FIG. 7 is a cross-sectional view schematically showing 2DEG induced at the AlGaN/GaN interface of a semiconductor device according to a seventh embodiment of the present disclosure.
  • 9 is a cross-sectional view showing the configuration of a semiconductor device according to a ninth embodiment of the present disclosure.
  • FIG. 10 is a cross-sectional view showing the configuration of a semiconductor device according to a tenth embodiment of the present disclosure.
  • FIG. 11 is a cross-sectional view showing the configuration of a semiconductor device according to an eleventh embodiment of the present disclosure.
  • FIG. 12 is a cross-sectional view showing the configuration of a semiconductor device according to a twelfth embodiment of the present disclosure.
  • FIG. 1 is a cross-sectional view showing the configuration of a semiconductor device 100 according to a first embodiment of the present disclosure. Note that in FIG. 1, for convenience, only a main electrode portion that is a part of, for example, a heterojunction field effect transistor is shown.
  • a semiconductor device 100 includes a semiconductor substrate 1 made of, for example, silicon carbide (SiC), and a buffer layer 2 made of AlN (aluminum nitride) interposed therebetween.
  • a channel layer 3 made of AlGaN (a second nitride semiconductor) is stacked on top of the channel layer 3, and a barrier layer 4 made of AlGaN (a second nitride semiconductor) is formed on the channel layer 3 to form a heterojunction with the channel layer 3. .
  • a nitride semiconductor By using such a nitride semiconductor, a practical heterojunction field effect transistor can be obtained.
  • the AlGaN forming the barrier layer 4 has a larger band gap than the GaN forming the channel layer 3.
  • a metal film 5 constituting a drain electrode, a source electrode, etc. is selectively provided on the barrier layer 4, and a part of the side surface and top surface of the metal film 5 is covered with a composite layer 8 of a metal and an insulator. ing.
  • An insulating film 6 made of SiO 2 or SiN is provided in a region on the barrier layer 4 other than the region where the composite layer 8 and the metal film 5 are formed.
  • a contact hole CH is provided in the composite layer 8 on the top surface of the metal film 5 so that a part of the top surface of the metal film 5 is exposed, and a wiring layer 7 is provided in contact with the metal film 5 through the contact hole CH.
  • the composite layer 8 is, for example, a silicide layer in which the metal film 5 and SiO 2 have reacted, or a silicide layer in which the metal film 5 and SiN have reacted, and has a conductive part with a lower resistance than the metal film 5.
  • the composite layer 8 is not limited to a silicide layer, and any layer that is made of a conductive material and an insulating material by heat treatment at 600° C. or higher and has conductivity can be used.
  • FIG. 2 is a diagram schematically showing the current flowing into the channel layer 3 via the wiring layer 7.
  • the current flowing to the channel layer 3 via the wiring layer 7 has a current path C1 flowing from the wiring layer 7 to the channel layer 3 via the metal film 5, and a current path C1 flowing from the wiring layer 7 to the composite layer 8.
  • the current flows through two paths C2 through which the current flows to the channel layer 3, resulting in the effect of reducing contact resistance.
  • the contact resistance when the insulating film 6 is made of SiO 2 and the Al composition and thickness of the AlGaN barrier layer 4 are 26% and 15 nm, respectively, the contact resistance is 0.6 ⁇ mm to 0.6 ⁇ mm. It becomes 7 ⁇ mm. Note that from the above numerical values, it is predicted that the contact resistance will increase if the Al composition of the barrier layer 4 is reduced and the thickness thereof is made thin.
  • Such a structure in which the metal film 5 is covered with the composite layer 8 is obtained by forming the metal film 5 on the barrier layer 4 and depositing the insulating film 6 so as to cover the barrier layer 4 and the metal film 5, for example.
  • the metal film 5 is alloyed with the barrier layer 4 to become an ohmic electrode, and the metal film 5 and the insulating film 6 react to form a silicide layer. I can do it.
  • the insulating film 6 on the barrier layer 4 functions as a protective film that protects the semiconductor layers below the barrier layer 4, and a new process is added to evaporate the metal and re-deposit it onto the barrier layer 4 during high-temperature heat treatment. It can be prevented without doing anything.
  • FIGS. 3 to 7 which sequentially show the manufacturing steps. Note that in FIGS. 3 to 7, the same components as those of the semiconductor device 100 shown in FIG. 1 are denoted by the same reference numerals, and redundant explanation will be omitted.
  • a buffer layer 2 made of AlN is formed on a SiC semiconductor substrate 1 using an epitaxial growth method such as MOCVD (metal organic chemical vapor deposition) or MBE (molecular beam epitaxy).
  • MOCVD metal organic chemical vapor deposition
  • MBE molecular beam epitaxy
  • a channel layer 3 made of GaN and a barrier layer 4 made of AlGaN are grown in this order.
  • a metal film 5 is formed in a desired region using vapor deposition and a lift-off method. Note that the metal film 5 can be a single layer film of Ti, Al, Ni (nickel), Au (gold), Mo, or a multilayer film of these.
  • an insulating film 6 is deposited on the barrier layer 4 so as to cover the metal film 5 by, for example, plasma CVD.
  • the insulating film 6 for example, SiO 2 or SiN can be formed.
  • the method for forming the insulating film 6 is not limited to the plasma CVD method, and a thermal CVD method and a sputtering method can be used.
  • heat treatment is performed at a temperature of 500°C to 900°C, more preferably 800°C to 850°C, using an RTA (Rapid Thermal Annealing) method or the like to separate the metal film 5 and the insulating film 6.
  • RTA Rapid Thermal Annealing
  • the composite layer 8 in the region where the wiring layer 7 is to be formed is removed by using a dry etching method using, for example, a resist material as a mask, and the contact layer 8 is exposed on the bottom surface of the metal film 5. Form a hole CH.
  • a resist mask RM is formed on the composite layer 8 and the insulating film 6, with an opening OP at a portion where the wiring layer 7 is desired to be formed. Thereafter, a single layer film of Ti, Al, Ni, Au, etc., or a multilayer film of these is formed by vapor deposition on the resist mask RM and in the opening OP, and the resist mask RM is removed using a lift-off method. A wiring layer 7 is formed to obtain the semiconductor device 100 shown in FIG.
  • FIG. 8 is a cross-sectional view showing the configuration of a semiconductor device 200 according to a second embodiment of the present disclosure. Note that in FIG. 8, the same components as those of the semiconductor device 100 described using FIG.
  • the metal film 5 is covered with a composite layer 8, and a region on the barrier layer 4 other than the region where the composite layer 8 and the metal film 5 are formed is covered with SiO 2 or SiN, etc.
  • An insulating film 6 is provided.
  • a wiring layer 7 is selectively provided on the upper surface of the composite layer 8.
  • the composite layer 8 is, for example, a silicide layer in which the metal film 5 and SiO 2 have reacted, or a silicide layer in which the metal film 5 and SiN have reacted, and has a conductive portion having a lower resistance than the metal film 5. Therefore, the current flowing to the channel layer 3 via the wiring layer 7 has a current path flowing from the wiring layer 7 to the channel layer 3 via the composite layer 8 and the metal film 5, and from the wiring layer 7 via the composite layer 8. Since the current flows through the channel layer 3 through two paths, the effect of reducing contact resistance can be obtained.
  • the insulating film 6 on the barrier layer 4 provided to obtain such a structure in which the metal film 5 is covered with the composite layer 8 functions as a protective film to protect the semiconductor layer below the barrier layer 4 during heat treatment, and Evaporation of metal and redeposition to barrier layer 4 during heat treatment can be prevented without adding a new process.
  • the wiring layer 7 is provided in contact with the upper surface of the composite layer 8, there is no need to provide a contact hole in the composite layer 8, so the manufacturing process can be simplified.
  • FIG. 9 showing the manufacturing process.
  • the steps up to the steps shown in FIG. 9 are the same as the steps shown in FIGS. 3 to 5 used to explain the method for manufacturing the semiconductor device 100 of Embodiment 1, and the steps shown in FIG. 9 are the same as those shown in FIGS.
  • the portion in contact with the insulating film 6 is reacted to form a silicide layer to form a composite layer 8
  • the metal film 5 is covered with the composite layer 8
  • the metal film 5 is alloyed with the barrier layer 4 to form an ohmic electrode.
  • a resist mask RM is formed on the composite layer 8 and the insulating film 6, with the opening OP in the area where the wiring layer 7 is to be formed.
  • a single layer film of Ti, Al, Ni, Au, etc., or a multilayer film of these is formed by vapor deposition on the resist mask RM and in the opening OP, and the resist mask RM is removed using a lift-off method.
  • Wiring layer 7 is formed to obtain semiconductor device 200 shown in FIG. 8.
  • FIG. 10 is a cross-sectional view showing the configuration of a semiconductor device 300 according to a third embodiment of the present disclosure. Note that in FIG. 10, the same components as those of the semiconductor device 100 described using FIG.
  • the upper surface and side surfaces of the metal film 5 are covered with a composite layer 8, and the composite layer 8 is also provided between the lower surface of the metal film 5 and the barrier layer 4.
  • An insulating film 6 made of SiO 2 or SiN is provided in a region on the barrier layer 4 other than the region where the metal film 8 and the metal film 5 are formed.
  • a contact hole CH is provided in the composite layer 8 on the top surface of the metal film 5 so that a part of the top surface of the metal film 5 is exposed, and a wiring layer 7 is provided in contact with the metal film 5 through the contact hole CH.
  • the composite layer 8 is, for example, a silicide layer in which the metal film 5 and SiO 2 have reacted, or a silicide layer in which the metal film 5 and SiN have reacted, and has a conductive portion having a lower resistance than the metal film 5. Therefore, the current flowing through the wiring layer 7 to the channel layer 3 has a current path flowing from the wiring layer 7 to the channel layer 3 via the metal film 5 and the lower composite layer 8, and from the wiring layer 7 to the composite layer 8. The current flows through the channel layer 3 through two paths, and the effect of reducing the contact resistance can be obtained. Further, the lower composite layer 8 and the barrier layer 4 are in contact with each other, and the contact resistance can be further reduced than in the semiconductor device 100 of the first embodiment.
  • the insulating film 6 on the barrier layer 4 provided to obtain such a structure in which the metal film 5 is covered with the composite layer 8 functions as a protective film to protect the semiconductor layers below the barrier layer 4 during heat treatment. , metal evaporation and redeposition to the barrier layer 4 during high-temperature heat treatment can be prevented without adding a new process.
  • FIGS. 11 to 16 which sequentially show the manufacturing steps.
  • a buffer layer 2 made of AlN, a channel layer 3 made of GaN, and a layer made of AlGaN are formed on a SiC semiconductor substrate 1 using an epitaxial growth method such as MOCVD or MBE.
  • the barrier layer 4 is grown in this order.
  • an insulating film 61 (first insulating film) is deposited on the barrier layer 4 by, for example, plasma CVD.
  • the insulating film 61 for example, SiO 2 or SiN can be formed.
  • the metal film 5 is formed in a desired region on the insulating film 61 using vapor deposition and lift-off methods.
  • the metal film 5 can be a single layer film of Ti, Al, Ni, Au, Mo, or the like, or a multilayer film of these.
  • an insulating film 62 (second insulating film) is deposited by, for example, plasma CVD so as to cover the metal film 5 and the insulating film 61.
  • the insulating film 62 the same SiO 2 or SiN as the insulating film 61 can be formed. Note that the method for forming the insulating films 61 and 62 is not limited to the plasma CVD method, and a thermal CVD method or a sputtering method can be used.
  • heat treatment is performed at a temperature of 500 to 900 degrees Celsius using an RTA method or the like to cause a reaction between the contact portions of the metal film 5 and the insulating film 6 to form a silicide layer and form a composite.
  • layer 8 the entire metal film 5 is covered with the composite layer 8, and the metal film 5, the composite layer 8, and the barrier layer 4 are alloyed with each other to form an ohmic electrode.
  • the insulating films 61 and 62 are integrally represented as the insulating film 6.
  • the composite layer 8 in the region where the wiring layer 7 is to be formed is removed using, for example, a dry etching method using a resist material as a mask, so that the contact layer 8 is exposed on the bottom surface of the metal film 5.
  • a dry etching method using a resist material as a mask
  • a resist mask RM is formed on the composite layer 8 and the insulating film 6, with an opening OP in the area where the wiring layer 7 is to be formed. Thereafter, a single layer film of Ti, Al, Ni, Au, etc., or a multilayer film of these is formed by vapor deposition on the resist mask RM and in the opening OP, and the resist mask RM is removed using a lift-off method. Wiring layer 7 is formed to obtain semiconductor device 300 shown in FIG.
  • FIG. 17 is a cross-sectional view showing the configuration of a semiconductor device 400 according to a fourth embodiment of the present disclosure. Note that, in FIG. 17, the same components as those of the semiconductor device 100 described using FIG.
  • the upper surface and side surfaces of the metal film 5 are covered with a composite layer 8, and the composite layer 8 is also provided between the lower surface of the metal film 5 and the barrier layer 4.
  • An insulating film 6 made of SiO 2 or SiN is provided in a region on the barrier layer 4 other than the region where the metal film 8 and the metal film 5 are formed.
  • a wiring layer 7 is selectively provided on the upper surface of the composite layer 8.
  • the composite layer 8 is, for example, a silicide layer in which the metal film 5 and SiO 2 have reacted, or a silicide layer in which the metal film 5 and SiN have reacted, and has a conductive portion having a lower resistance than the metal film 5. For this reason, the current flowing to the channel layer 3 via the wiring layer 7 has a current path flowing from the wiring layer 7 to the channel layer 3 via the upper composite layer 8, the metal film 5, and the lower composite layer 8, and the wiring The current flows through two paths from the layer 7 to the channel layer 3 via the composite layer 8, resulting in the effect of reducing contact resistance.
  • the insulating film 6 on the barrier layer 4 provided to obtain such a structure in which the metal film 5 is covered with the composite layer 8 functions as a protective film to protect the semiconductor layers below the barrier layer 4 during heat treatment. , metal evaporation and redeposition to the barrier layer 4 during high-temperature heat treatment can be prevented without adding a new process.
  • the wiring layer 7 is provided in contact with the upper surface of the composite layer 8, there is no need to provide a contact hole in the composite layer 8, so the manufacturing process can be simplified.
  • FIG. 18 showing the manufacturing process.
  • the steps up to the steps shown in FIG. 18 are the same as the steps shown in FIGS. 11 to 14 used to explain the method for manufacturing the semiconductor device 300 of the third embodiment, and the steps shown in FIG. 18 are the same as those shown in FIGS.
  • the parts in contact with the insulating film 6 are reacted to form a silicide layer to form a composite layer 8, and the entire metal film 5 is covered with the composite layer 8, and the metal film 5, the composite layer 8, and the barrier layer 4 are mutually alloyed. to make it into an ohmic electrode.
  • a resist mask RM is formed on the composite layer 8 and the insulating film 6, with an opening OP in the portion where the wiring layer 7 is to be formed.
  • a single layer film of Ti, Al, Ni, Au, etc., or a multilayer film of these is formed by vapor deposition on the resist mask RM and in the opening OP, and the resist mask RM is removed using a lift-off method.
  • Wiring layer 7 is formed to obtain semiconductor device 400 shown in FIG. 17.
  • FIG. 19 is a cross-sectional view showing the configuration of a semiconductor device 500 according to a fifth embodiment of the present disclosure. Note that, in FIG. 19, the same components as those of the semiconductor device 100 described using FIG.
  • the upper surface and side surfaces of the metal film 5 are covered with a composite layer 8, and the composite layer 8 is also provided between a part of the lower surface of the metal film 5 and the barrier layer 4.
  • an insulating film 6 made of SiO 2 or SiN is provided in a region on the barrier layer 4 other than the region where the composite layer 8 and the metal film 5 are formed.
  • a contact hole CH is provided in the composite layer 8 on the top surface of the metal film 5 so that a part of the top surface of the metal film 5 is exposed, and a wiring layer 7 is provided in contact with the metal film 5 through the contact hole CH.
  • the composite layer 8 is, for example, a silicide layer in which the metal film 5 and SiO 2 have reacted, or a silicide layer in which the metal film 5 and SiN have reacted, and has a conductive portion having a lower resistance than the metal film 5. Therefore, the current flowing to the channel layer 3 via the wiring layer 7 has two current paths: one from the wiring layer 7 to the channel layer 3 via the metal film 5, and the other from the wiring layer 7 to the channel layer 3 via the composite layer 8. The current flows through two paths, resulting in an effect of reducing contact resistance.
  • the structure is such that the metal film 5 and the barrier layer 4 are in contact with each other, and in order to form the composite layer 8, the metal film 5 is alloyed with the barrier layer 4 by heat treatment at a high temperature of 600° C. or higher, for example, to form an ohmic electrode. Therefore, the contact resistance can be further reduced.
  • the insulating film 6 on the barrier layer 4 functions as a protective film that protects the semiconductor layers below the barrier layer 4, and the evaporation of metal and re-deposition to the barrier layer 4 during high-temperature heat treatment are prevented by a new process. This can be prevented without adding.
  • FIGS. 20 to 26 which sequentially show the manufacturing steps.
  • a buffer layer 2 made of AlN, a channel layer 3 made of GaN, and a layer made of AlGaN are formed on a SiC semiconductor substrate 1 using an epitaxial growth method such as MOCVD or MBE.
  • the barrier layer 4 is grown in this order.
  • an insulating film 61 is deposited on the barrier layer 4 by, for example, plasma CVD.
  • the insulating film 61 for example, SiO 2 or SiN can be formed.
  • the insulating film 61 in the region where the metal film 5 is to be formed is removed using, for example, a dry etching method using a resist material as a mask, and the contact layer 4 is exposed on the bottom surface of the insulating film 61 in the region where the metal film 5 is to be formed.
  • a hole CH1 is formed.
  • the metal film 5 is formed in a desired region on the insulating film 61 including over the contact hole CH1 using vapor deposition and lift-off methods.
  • the metal film 5 can be a single layer film of Ti, Al, Ni, Au, Mo, or the like, or a multilayer film of these.
  • an insulating film 62 is deposited by, for example, plasma CVD so as to cover the metal film 5 and the insulating film 61.
  • the insulating film 62 the same SiO 2 or SiN as the insulating film 61 can be formed. Note that the method for forming the insulating films 61 and 62 is not limited to the plasma CVD method, and a thermal CVD method or a sputtering method can be used.
  • heat treatment is performed at a temperature of 500 to 900 degrees Celsius using an RTA method or the like to cause a reaction between the contact portions of the metal film 5 and the insulating film 6 to form a silicide layer.
  • the metal film 5 is covered with the composite layer 8, and the metal film 5, the composite layer 8, and the barrier layer 4 are alloyed with each other to form an ohmic electrode.
  • a composite layer 8 is also formed between a portion of the lower surface of the metal film 5 and the barrier layer 4.
  • the insulating films 61 and 62 are integrally represented as the insulating film 6.
  • the composite layer 8 in the area where the wiring layer 7 is to be formed is removed using, for example, a dry etching method using a resist material as a mask, and the contact layer 8 is exposed on the bottom surface of the metal film 5. Form a hole CH.
  • a resist mask RM is formed on the composite layer 8 and the insulating film 6, with an opening OP in a portion where the wiring layer 7 is desired to be formed. Thereafter, a single layer film of Ti, Al, Ni, Au, etc., or a multilayer film of these is formed by vapor deposition on the resist mask RM and in the opening OP, and the resist mask RM is removed using a lift-off method. Wiring layer 7 is formed to obtain semiconductor device 500 shown in FIG. 19.
  • FIG. 27 is a cross-sectional view showing the configuration of a semiconductor device 600 according to Embodiment 6 of the present disclosure. Note that in FIG. 27, the same components as those of the semiconductor device 100 described using FIG.
  • the upper surface and side surfaces of the metal film 5 are covered with the composite layer 8, and the composite layer 8 is also provided between a part of the lower surface of the metal film 5 and the barrier layer 4.
  • an insulating film 6 made of SiO 2 or SiN is provided in a region on the barrier layer 4 other than the region where the composite layer 8 and the metal film 5 are formed.
  • a wiring layer 7 is selectively provided on the upper surface of the composite layer 8.
  • the composite layer 8 is, for example, a silicide layer in which the metal film 5 and SiO 2 have reacted, or a silicide layer in which the metal film 5 and SiN have reacted, and has a conductive portion having a lower resistance than the metal film 5. Therefore, the current flowing to the channel layer 3 via the wiring layer 7 has a current path flowing from the wiring layer 7 to the channel layer 3 via the upper composite layer 8 and the metal film 5, and a current path flowing from the wiring layer 7 to the composite layer 8. Since the current flows through the channel layer 3 through two paths, the effect of reducing contact resistance can be obtained.
  • the wiring layer 7 is provided in contact with the upper surface of the composite layer 8, there is no need to provide a contact hole in the composite layer 8, so the manufacturing process can be simplified.
  • FIG. 28 shows the manufacturing process.
  • the steps up to the steps shown in FIG. 28 are the same as the steps shown in FIGS. 20 to 24 used to explain the method for manufacturing the semiconductor device 500 of the fifth embodiment, and the steps shown in FIG. 28 are the same as those shown in FIGS.
  • the part in contact with the insulating film 6 is reacted to form a silicide layer to form a composite layer 8, the metal film 5 is covered with the composite layer 8, and the metal film 5, the composite layer 8, and the barrier layer 4 are mutually alloyed. to make it an ohmic electrode.
  • a composite layer 8 is also formed between a portion of the lower surface of the metal film 5 and the barrier layer 4.
  • a resist mask RM is formed on the composite layer 8 and the insulating film 6, with the opening OP being the portion where the wiring layer 7 is to be formed.
  • a single layer film of Ti, Al, Ni, Au, etc., or a multilayer film of these is formed by vapor deposition on the resist mask RM and in the opening OP, and the resist mask RM is removed using a lift-off method.
  • Wiring layer 7 is formed to obtain semiconductor device 600 shown in FIG. 27.
  • ⁇ Embodiment 7> ⁇ Device configuration>
  • the configuration of a semiconductor device 700 according to a seventh embodiment of the present disclosure is the same as that of the first embodiment shown in FIG.
  • the structure of the semiconductor device 700 is the same as that of the semiconductor device 100, and the semiconductor device 700 will be described using FIG. 29 and FIG. 30 while referring to FIG.
  • the semiconductor device 700 has an AlGaN/GaN heterojunction in which a barrier layer 4 made of AlGaN that forms a heterojunction with the channel layer 3 is formed on a channel layer 3 made of GaN.
  • the structure is as follows.
  • the Al composition and thickness of the AlGaN layer are as follows in the state where the metal film 5 and the insulating film 6 are not formed, that is, the state shown in FIG. , the sheet resistance due to two-dimensional electron gas (2DEG) generated at the interface between barrier layer 4 and channel layer 3 (AlGaN/GaN interface) is designed to be a sufficiently high value, that is, at least 10 k ⁇ /sq or more.
  • 2DEG two-dimensional electron gas
  • the sheet resistance is 10 k ⁇ /sq or more.
  • the sheet resistance in a state where the barrier layer 4 is simply formed on the channel layer 3 described above is defined as the inherent sheet resistance of the barrier layer 4.
  • An insulating film 6 made of, for example, SiO 2 is deposited on the barrier layer 4 composed of the AlGaN layer designed in this way, and heat treatment is performed at a temperature of 500°C to 900°C, thereby forming a layer of 1 at the AlGaN/GaN interface. It is possible to induce 2DEG at a concentration of ⁇ 10 12 cm ⁇ 2 or higher. This state is schematically shown in FIG.
  • FIG. 30 it is shown that 2DEG 9 is induced at the interface between the channel layer 3 and the barrier layer 4, and the sheet resistance can be reduced by 2DEG to, for example, 1 k ⁇ /sq or less.
  • the process can be simplified by simultaneously performing the formation of the composite layer 8 for forming the low-resistance ohmic electrode described in Embodiments 1 to 6 and the high-temperature heat treatment for inducing 2DEG. .
  • the sheet resistance due to 2DEG generated at the AlGaN/GaN interface is at a sufficiently high value, that is, at least 10 k ⁇ /sq or more in a state where the metal film 5 and the insulating film 6 are not formed. This is a more effective structure if it is designed to
  • Embodiment 8> ⁇ Device configuration>
  • the structure of the semiconductor device of Embodiment 8 according to the present disclosure is such that the composite layer 8 includes an element constituting the insulating film 6 and also includes one or more metal elements included in the barrier layer 4 and the metal film 5.
  • the other components are the same as the configuration of the semiconductor device 100 of the first embodiment shown in FIG. 1, and the semiconductor device of this embodiment will be described with reference to FIG.
  • the metal elements contained in the composite layer 8 can include one or more of Ga, Al, and Au.
  • the composite layer 8 includes materials constituting a semiconductor device, especially a nitride semiconductor device, and unnecessary impurities are not mixed into the composite layer 8, and the semiconductor has stable electrical characteristics. A device is obtained.
  • the barrier layer 4 is made of AlGaN
  • the metal film 5 is made of Al or Au
  • at least one of the metal elements Al and Ga contained in the barrier layer 4 is incorporated into the composite layer 8.
  • a structure may be adopted in which at least one of the metal elements Al and Au contained in the metal film 5 is incorporated into the composite layer 8.
  • the composite layer 8 by configuring the composite layer 8 to include one or more of the metal elements Al, Ga, and Au contained in the barrier layer 4 and the metal film 5, unnecessary elements can be removed from the composite layer 8. Contamination with impurities can be suppressed.
  • the composite layer 8 contains gallium, it is contained at 2 atomic percent (at%) or more, and when the composite layer 8 contains aluminum, it is contained at 10 atomic percent (at%) or more, and when the composite layer 8 contains gold, it is contained at 10 atomic percent (at%) or more. If it is included, it can be configured to contain 5 atomic percent (at%) or more.
  • the composite layer 8 can be formed using a material constituting a semiconductor device, particularly a nitride semiconductor device, and it is possible to suppress the complexity of the manufacturing process.
  • the layer 8 can also be configured to include one or more metal elements contained in the barrier layer 4 and the metal film 5.
  • FIG. 31 is a cross-sectional view showing the configuration of a semiconductor device 800 according to a ninth embodiment of the present disclosure. Note that in FIG. 31, the same components as those of the semiconductor device 100 explained using FIG.
  • a semiconductor device 800 has an insulating film 10 that partially covers the insulating film 6, composite layer 8, and wiring layer 7, in addition to the structure of the semiconductor device 100 shown in FIG.
  • the semiconductor device 800 is a transistor
  • the insulating film 10 functions as a gate insulating film of a gate electrode provided in a portion not shown. Further, when a gate insulating film is provided separately, it functions as a protective film for the gate electrode.
  • the insulating film 10, like the insulating film 6, can be made of Al 2 O 3 , SiO 2 or SiN.
  • the presence of the composite layer 8 has the effect of reducing the contact resistance and
  • the insulating film 10 as a protective film for a gate insulating film or a gate electrode, abnormalities such as deterioration, alteration, or peeling of the gate insulating film or gate electrode can be suppressed, and various semiconductor devices can be realized.
  • FIG. 31 shows a configuration in which the insulating film 10 is provided in the semiconductor device 100
  • the insulating film 10 can be provided in any of the structures of the semiconductor devices 200 to 700 of Embodiments 2 to 7.
  • FIG. 32 is a cross-sectional view showing the configuration of a semiconductor device 900 according to Embodiment 10 of the present disclosure. Note that in FIG. 32, the same components as those of the semiconductor device 100 described using FIG. 1 are given the same reference numerals, and redundant explanation will be omitted.
  • the semiconductor device 900 is provided such that the wiring layer 7 engages not only the inside of the contact hole CH provided in the composite layer 8 but also a part of the upper part of the composite layer 8. .
  • the contact hole CH is completely covered with the wiring layer 7, and it is possible to prevent a gap from forming between the contact hole CH and the wiring layer 7. Then, abnormalities such as peeling of the composite layer 8 or deterioration of the metal film 5 inside the contact hole CH can be suppressed.
  • FIG. 33 is a cross-sectional view showing the configuration of a semiconductor device 1000 according to an eleventh embodiment of the present disclosure. Note that in FIG. 33, the same components as those of the semiconductor device 100 described using FIG.
  • the semiconductor device 1000 has a structure in which the buffer layer 2 is formed of a plurality of AlN layers 21 and AlGaN layers 22 alternately repeated. Adopting such a configuration has the effect of suppressing deterioration in crystal quality due to a difference in lattice constant between the semiconductor substrate 1 and the channel layer 3 made of GaN.
  • FIG. 34 is a cross-sectional view showing the configuration of a semiconductor device 1100 according to Embodiment 12 of the present disclosure. Note that in FIG. 34, the same components as those of the semiconductor device 100 described using FIG.
  • the semiconductor device 1100 has a structure in which a back barrier layer 11 made of AlGaN is formed on the buffer layer 2.
  • a back barrier layer 11 made of AlGaN which has a larger band gap than the GaN of the channel layer 3, drain leakage current can be suppressed.
  • the semiconductor substrate 1 is made of SiC
  • the buffer layer 2 is made of AlN
  • the channel layer 3 is made of GaN
  • the barrier layer 4 is made of AlGaN. It is not limited to these.
  • the semiconductor substrate 1 can be made of Si, sapphire, AlN, and GaN.
  • the buffer layer 2 is required, but when the semiconductor substrate 1 is made of GaN, AlGaN, or InAlGaN, which is the same material as the channel layer 3, Buffer layer 2 is not necessarily required.
  • the channel layer 3 and the barrier layer 4 are formed as semiconductor layers formed on the semiconductor substrate 1, the effects of each embodiment according to the present disclosure can be obtained.
  • the buffer layer can be made of GaN and AlGaN, and the channel layer 3 can be made of AlGaN and InAlGaN.
  • Barrier layer 4 can be composed of GaN, AlN, InAlGaN, and InAlN.
  • the insulating film 6 and the insulating film 10 are not limited to SiO 2 or SiN, but can be made of alumina (Al 2 O 3 ), HfO x , SiON, AlON, or HfON.
  • the nitride semiconductor layer can be non-doped and does not contain impurities, but Si, Mg (magnesium), Fe (iron), C (carbon), and Ge ( It is also possible to contain impurities such as germanium.

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JP2002016086A (ja) * 2000-06-27 2002-01-18 Fujitsu Ltd 半導体装置
JP2017085059A (ja) * 2015-10-30 2017-05-18 富士通株式会社 化合物半導体装置及びその製造方法
JP2019036586A (ja) * 2017-08-10 2019-03-07 富士通株式会社 半導体装置、電源装置、増幅器及び半導体装置の製造方法

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JP2926897B2 (ja) * 1990-05-30 1999-07-28 ソニー株式会社 半導体装置の製造方法
JPH09326370A (ja) * 1996-06-05 1997-12-16 Oki Electric Ind Co Ltd 半導体装置の製造方法
JP2013004747A (ja) * 2011-06-16 2013-01-07 Renesas Electronics Corp 半導体装置およびその製造方法
US20220157980A1 (en) * 2019-03-20 2022-05-19 Panasonic Corporation Nitride semiconductor device
WO2021024502A1 (ja) * 2019-08-06 2021-02-11 三菱電機株式会社 半導体装置およびその製造方法
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JP2002016086A (ja) * 2000-06-27 2002-01-18 Fujitsu Ltd 半導体装置
JP2017085059A (ja) * 2015-10-30 2017-05-18 富士通株式会社 化合物半導体装置及びその製造方法
JP2019036586A (ja) * 2017-08-10 2019-03-07 富士通株式会社 半導体装置、電源装置、増幅器及び半導体装置の製造方法

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