WO2023231223A1 - 一种刷新地址产生电路 - Google Patents

一种刷新地址产生电路 Download PDF

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Publication number
WO2023231223A1
WO2023231223A1 PCT/CN2022/118035 CN2022118035W WO2023231223A1 WO 2023231223 A1 WO2023231223 A1 WO 2023231223A1 CN 2022118035 W CN2022118035 W CN 2022118035W WO 2023231223 A1 WO2023231223 A1 WO 2023231223A1
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Prior art keywords
refresh
address
signal
gate
circuit
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PCT/CN2022/118035
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English (en)
French (fr)
Inventor
谷银川
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长鑫存储技术有限公司
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Application filed by 长鑫存储技术有限公司 filed Critical 长鑫存储技术有限公司
Priority to EP22940943.8A priority Critical patent/EP4325499A1/en
Priority to US18/153,312 priority patent/US20230386547A1/en
Publication of WO2023231223A1 publication Critical patent/WO2023231223A1/zh

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408—Address circuits

Definitions

  • the present disclosure relates to, but is not limited to, a refresh address generation circuit.
  • the memory is divided into multiple memory banks (Banks), and there are two modes for refreshing storage addresses: All Bank Refresh (All Bank Refresh) in which all Banks refresh the same address together, and all Bank Refresh (All Bank Refresh) in which all Banks are refreshed at the same address.
  • All Bank Refresh All Bank Refresh
  • All Bank Refresh All Bank Refresh
  • All Bank Refresh All Bank Refresh
  • embodiments of the present disclosure provide a refresh address generation circuit that can not only generate the address to be refreshed but also maintain the pre-stored first address during the refresh operation. This ensures that the refresh operation does not miss the address. performed while maintaining the integrity of the address.
  • the refresh address generation circuit includes:
  • Refresh control circuit configured to receive multiple first refresh instructions in sequence and perform multiple first refresh operations correspondingly, to output a first clock signal when the number of first refresh operations is less than m, and when the first refresh operation The second clock signal is output when the number of operations is equal to m, where m is an integer greater than or equal to 1;
  • An address generator coupled to the refresh control circuit, used to prestore a first address, receive the first clock signal or the second clock signal, and respond to the first clock during each first refresh operation.
  • the signal outputs the address to be refreshed, and changes the first address in response to the second clock signal; the address to be refreshed includes the first address or the second address, and the lowest bit of the second address is the same as the second address. The lowest bit of the first address is reversed.
  • the embodiment of the present disclosure provides a refresh address generation circuit, which includes: a refresh control circuit and an address generator.
  • the refresh control circuit receives multiple first refresh instructions in sequence and performs multiple first refresh operations correspondingly, outputs a first clock signal when the number of first refresh operations is less than m, and when the number of first refresh operations is equal to m
  • m is an integer greater than or equal to 1.
  • the address generator is coupled to the refresh control circuit, used to prestore the first address, receive the first clock signal or the second clock signal, output the address to be refreshed in response to the first clock signal during each first refresh operation, and respond to the first clock signal during each first refresh operation.
  • the second clock signal changes the first address.
  • the address to be refreshed includes a first address or a second address, and the lowest bit of the second address is opposite to the lowest bit of the first address.
  • the address generator responds to the first clock signal, not only outputs the address to be refreshed including the first address or the second address, but also maintains the first address unchanged; while during the first refresh After the number of operations is equal to m, the address generator responds to the second clock signal and then changes the first address. In this way, it not only ensures that the refresh operation is carried out without missing a thing, but also maintains the integrity of the address.
  • Figure 1 is a schematic structural diagram of a refresh address generation circuit provided by an embodiment of the present disclosure
  • FIG. 2 is a signal schematic diagram 1 of the refresh address generation circuit provided by an embodiment of the present disclosure
  • Figure 3 is a second structural schematic diagram of a refresh address generation circuit provided by an embodiment of the present disclosure.
  • Figure 4 is a second signal schematic diagram of a refresh address generation circuit provided by an embodiment of the present disclosure.
  • Figure 5 is a signal diagram 3 of the refresh address generation circuit provided by an embodiment of the present disclosure.
  • Figure 6 is a schematic structural diagram three of a refresh address generation circuit provided by an embodiment of the present disclosure.
  • Figure 7 is a schematic structural diagram 4 of a refresh address generation circuit provided by an embodiment of the present disclosure.
  • Figure 8 is a schematic structural diagram 5 of a refresh address generation circuit provided by an embodiment of the present disclosure.
  • Figure 9 is a signal diagram 4 of the refresh address generation circuit provided by an embodiment of the present disclosure.
  • Figure 10 is a schematic structural diagram 6 of a refresh address generation circuit provided by an embodiment of the present disclosure.
  • Figure 11 is a schematic structural diagram 7 of a refresh address generation circuit provided by an embodiment of the present disclosure.
  • Figure 12 is a signal diagram 5 of the refresh address generation circuit provided by an embodiment of the present disclosure.
  • Figure 13 is a schematic structural diagram 8 of a refresh address generation circuit provided by an embodiment of the present disclosure.
  • Figure 14 is a signal diagram 6 of the refresh address generation circuit provided by an embodiment of the present disclosure.
  • Figure 15 is a signal diagram 7 of the refresh address generation circuit provided by an embodiment of the present disclosure.
  • Figure 16 is a schematic structural diagram 9 of a refresh address generation circuit provided by an embodiment of the present disclosure.
  • Figure 17 is a schematic structural diagram of a refresh address generation circuit provided by an embodiment of the present disclosure.
  • Figure 18 is a signal schematic diagram 8 of the refresh address generation circuit provided by an embodiment of the present disclosure.
  • Figure 19 is a schematic structural diagram 11 of a refresh address generation circuit provided by an embodiment of the present disclosure.
  • Figure 20 is a signal diagram 9 of the refresh address generation circuit provided by an embodiment of the present disclosure.
  • Figure 21 is a schematic structural diagram of a refresh address generation circuit provided by an embodiment of the present disclosure.
  • Figure 22 is a signal diagram 10 of the refresh address generation circuit provided by an embodiment of the present disclosure.
  • Figure 23 is a schematic structural diagram of a refresh address generation circuit provided by an embodiment of the present disclosure.
  • Figure 24 is a schematic structural diagram of a refresh address generation circuit provided by an embodiment of the present disclosure.
  • Figure 25 is a signal diagram 11 of the refresh address generation circuit provided by an embodiment of the present disclosure.
  • Figure 26 is a schematic structural diagram of a refresh address generation circuit provided by an embodiment of the present disclosure.
  • Figure 27 is a signal schematic diagram of a refresh address generation circuit provided by an embodiment of the present disclosure.
  • Figure 28 is a signal diagram 13 of the refresh address generation circuit provided by an embodiment of the present disclosure.
  • Figure 29 is a schematic structural diagram of a refresh address generation circuit provided by an embodiment of the present disclosure.
  • Figure 30 is a fourteenth signal schematic diagram of the refresh address generation circuit provided by an embodiment of the present disclosure.
  • Figure 31 is a signal schematic diagram of a refresh address generation circuit provided by an embodiment of the present disclosure.
  • Figure 32 is a schematic structural diagram of a refresh address generation circuit provided by an embodiment of the present disclosure.
  • Figure 33 is a signal schematic diagram of a refresh address generation circuit provided by an embodiment of the present disclosure.
  • Figure 34 is a signal diagram 17 of the refresh address generation circuit provided by an embodiment of the present disclosure.
  • Figure 35 is a schematic structural diagram of a refresh address generation circuit provided by an embodiment of the present disclosure.
  • Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM) is commonly used in the memory of electronic devices.
  • DDR4SDRAM or previous DDR SDRAM the refresh operation is performed on all banks together, and the addresses refreshed by all banks at the same time are the same, that is, All Bank Refresh.
  • Same Bank Refresh is newly added to DDR5SDRAM. In other words, in the Same Bank Refresh mode, different banks located in the same Bank Group cannot be refreshed at the same time. This will cause problems with address generation and saving.
  • FIG. 1 is a schematic structural diagram of a refresh address generation circuit provided by an embodiment of the disclosure. As shown in Figure 1, an embodiment of the disclosure provides a refresh address generation circuit 10, including: a refresh control circuit 101 and an address generator 102 . in:
  • the refresh control circuit 101 is used to receive multiple first refresh commands SB CMD ⁇ 0:m-1> in sequence and perform multiple first refresh operations correspondingly. When the number of first refresh operations is less than m, output the first clock signal, And, when the number of first refresh operations is equal to m, the second clock signal is output, and m is an integer greater than or equal to 1;
  • the address generator 102 is coupled to the refresh control circuit, used to prestore the first address, and receives the first clock signal or the second clock signal, and outputs the address to be refreshed in response to the first clock signal during each first refresh operation. And, the first address is changed in response to the second clock signal; the address to be refreshed includes the first address or the second address, and the lowest bit of the second address is opposite to the lowest bit of the first address.
  • the coupling method includes: direct electrical connection, and electrical connection through other electrical components (such as resistors, delays or inverters, etc.).
  • the "coupling” that appears in the following paragraphs all include these methods, and will not be described again in the following paragraphs.
  • the refresh control circuit 101 can receive multiple first refresh commands SB CMD ⁇ 0:m-1> in sequence, where SB CMD ⁇ 0:m-1> represents m first refresh commands SB CMD ⁇ 0> ⁇ SB CMD ⁇ m-1>.
  • each first refresh command SB CMD corresponds to a Bank in each Bank Group
  • each first refresh command SB CMD will trigger the corresponding Bank in each Bank Group to perform a first refresh operation (i.e. Same Bank Refresh) .
  • multiple first refresh instructions SB CMD ⁇ 0:m-1> received in sequence will trigger the corresponding Bank in each Bank Group to perform a first refresh operation respectively, that is, perform multiple first refresh operations in sequence.
  • the Bank Group includes m Banks, and the number m of Banks is set according to chip design standards.
  • Each Bank includes multiple rows of storage units, and the address to be refreshed is the row address of the storage unit in the Bank.
  • the address generator 102 outputs the address to be refreshed during the first refresh operation.
  • the storage unit where the address to be refreshed in the Bank corresponding to the first refresh command SB CMD is located. refresh.
  • the refresh control circuit 101 can output the SameBank refresh clock signal SB CBR CLK.
  • the SameBank refresh clock signal SB CBR CLK includes a first clock signal and a second clock signal. If the number of first refresh operations is less than m, it means that there are still Banks in the Bank Group that have not yet performed the first refresh operation on the memory unit where the refresh address Adress is located. At this time, the refresh control circuit 101 outputs the first clock signal; if the first If the number of refresh operations is equal to m, it means that the memory cells where the Address to be refreshed in all Banks in the Bank Group have completed the first refresh operation. At this time, the refresh control circuit 101 outputs the second clock signal.
  • SB CMD ⁇ 0>, SB CMD ⁇ 1>, SBCMD ⁇ 2> and SB CMD ⁇ 3> are all the first refresh instructions received by the refresh control circuit in sequence.
  • the pulses in SB CMD ⁇ 0>, SB CMD ⁇ 1>, SB CMD ⁇ 2> and SB CMD ⁇ 3> can sequentially trigger the refresh control circuit 101 to perform the first refresh operation.
  • the SameBank refresh clock signal SB CBR CLK includes a first clock signal and a second clock signal. The second clock signal is a pulse, and the first clock signal remains low.
  • the address generator 102 pre-stores the first address.
  • the address to be refreshed will be output in response to the first clock signal, where the address to be refreshed is
  • the refresh address Address includes the first address or the second address, and the lowest bit of the second address is opposite to the lowest bit of the first address. Since the address is a binary code, the second address with the lowest bit opposite to the first address is two adjacent addresses.
  • the second address is n+1 or n-1; that is to say , when the lowest bit of the first address n is 0, the second address inverts the lowest bit of n to 1, and the second address is n+1; when the lowest bit of the first address n is 1, the second address The lowest bit of n is inverted to 0, and the second address is n-1.
  • the address generator 102 receives the second clock signal, it will change its prestored first address in response to the second clock signal. That is, the next time the first refresh operation is performed, the address generator 102 will prestore the changed first address. address.
  • the address generator 102 can change the first address in an accumulative manner, and the accumulated value can be controlled by the second clock signal.
  • the address to be refreshed includes a first address and a second address.
  • the first address is n
  • the second address is n+1 or n-1.
  • the address generator 102 outputs the address to be refreshed as the first address and the second address that are output sequentially, where each group of the first address and the second address is in the first
  • the refresh instructions SB CMD ⁇ 0>, SB CMD ⁇ 1>, SB CMD ⁇ 2> and SB CMD ⁇ 3> sequentially trigger the refresh control circuit 101 to perform period output of the first refresh operation. That is to say, when the first refresh command SB CMD ⁇ 0> triggers the refresh control circuit 101 to perform the first refresh operation, the address generator 102 outputs the address to be refreshed.
  • the address to be refreshed includes the first address n and subsequent addresses.
  • the next second address n+1 or n-1 that is, the refresh controller will refresh the corresponding storage unit of Bank0 according to the address to be refreshed; similarly, the second first refresh command SB CMD ⁇ 1> triggers the refresh
  • the address generator 102 outputs the same Address to be refreshed, that is, the first address n and the immediately following second address n+1 or n-1.
  • the refresh controller will The address to be refreshed, Address, refreshes the corresponding storage unit in Bank1; and so on, until the corresponding storage unit in Bank3 is refreshed.
  • the address output signal Addr Counter Output represents the first address stored by the address generator 102 .
  • the first address n stored in the address generator 102 remains unchanged, and the address output signal Addr Counter Output continues to be the first address n;
  • the address generator 102 changes the first address n in response to the second clock signal, where, The second clock signal includes two pulses.
  • the address generator 102 Under the triggering of these two pulses, the address generator 102 accumulates 1 twice for the first address n, and the address output signal Addr Counter Output becomes n+2, thus being consistent with the refresh address. The progress matches; in the subsequent m first refresh operations, the address generator 102 continues to output the address to be refreshed, Adress, based on the first address that becomes n+2, to update the next two addresses of each bank in the Bank Group.
  • the storage units corresponding to adjacent addresses are refreshed, and by analogy, the storage units corresponding to all addresses in each Bank in the Bank Group can be refreshed in sequence.
  • the address generator 102 responds to the first clock signal and outputs the address to be refreshed Adress including the first address or the second address, while maintaining the first address. change; and after the number of first refresh operations reaches the preset number value m, the address generator 102 changes the first address in response to the second clock signal. In this way, it is ensured that the refresh operations are performed without omission, and the address consistency is maintained. Integrity.
  • FIG. 3 is an optional structural schematic diagram of the refresh control circuit 101 shown in FIG. 1
  • FIGS. 4 and 5 are signal diagrams corresponding to FIG. 3 .
  • FIG. 4 shows the signal timing when the refresh control circuit 101 sequentially receives multiple first refresh commands SB CMD and performs the first refresh operation, wherein the preset number value of the first refresh command SB CMD is For example, m equals 4.
  • FIG. 5 shows the signal timing when the refresh control circuit 101 receives the second refresh command AB CMD and performs the second refresh operation.
  • the refresh control circuit 101 includes: a refresh window signal generation circuit 201 and a clock pulse generation circuit 202 .
  • the refresh window signal generation circuit 201 is used to receive a plurality of first refresh instructions SB CMD (ie, SB CMD ⁇ 0> to SB CMD ⁇ m-1> shown in Figure 3) and a refresh window reset signal Refresh Window Reset.
  • SB CMD first refresh instructions
  • the first refresh command SB CMD and the refresh window reset signal Refresh Window Reset generate the refresh window signal Refresh Window.
  • the pulse duration of the refresh window signal Refresh Window is the window time for the refresh control circuit 101 to perform a refresh operation
  • the refresh window reset signal Refresh Window Reset is used to reset the refresh window signal generation circuit 201 after a refresh operation. Perform a reset.
  • the refresh operation performed by the refresh control circuit 101 is the first refresh operation, that is, the first refresh operation is performed on the Bank corresponding to the first refresh command SB CMD.
  • the clock pulse generation circuit 202 is coupled to the refresh window signal generation circuit 201 for receiving the refresh window signal Refresh Window and the first refresh command SB CMD.
  • the number of the first refresh commands SB CMD received by the clock pulse generation circuit 202 is less than or equal to m.
  • the first clock signal is generated before the m-th first refresh operation ends, or the second clock signal is generated after the m-th first refresh operation ends.
  • the SameBank refresh clock signal includes a first clock signal and a second clock signal, that is, the first clock signal and the second clock signal are values of the SameBank refresh clock signal in different periods.
  • the clock pulse generating circuit 202 includes: a counting circuit 203 , a counting reset signal generating circuit 204 and a first pulse generating sub-circuit 205 .
  • the counting circuit 203 is used to receive the first refresh command SB CMD and the count reset signal Bank Counter Reset, count the first refresh command SB CMD, and output the count signal Bank Counter, and reset according to the count reset signal Bank Counter Reset.
  • the count reset signal generation circuit 204 is coupled to the counting circuit 203 and the refresh window signal generation circuit 201, and is used to generate a count reset signal Bank Counter Reset after the mth first refresh operation is completed.
  • the first pulse generation sub-circuit 205 is coupled to the count reset signal generation circuit 204 and is used to generate a first clock signal according to the counting signal BankCounter when the first refresh instructions SB CMD are less than m, or when the first refresh instructions SB CMD are equal to m times, the second clock signal is generated according to the count reset signal Bank Counter Reset.
  • the refresh window signal generation circuit 201 includes: a plurality of refresh window sub-signal generation circuits 206 and a refresh window sub-signal processing circuit 207 .
  • the plurality of refresh window sub-signal generating circuits 206 are used to receive the refresh window reset signal Refresh Window Reset and respectively receive a plurality of first refresh instructions SB CMD in sequence. According to the plurality of first refresh instructions SB CMD and the refresh window reset signal Refresh Window Reset A plurality of refresh window sub-signals ReW (ie, ReW ⁇ 0> to ReW ⁇ m-1> shown in FIG. 3) are output in sequence.
  • the refresh window sub-signal processing circuit 207 is coupled to multiple refresh window sub-signal generating circuits 206, and is used to receive multiple refresh window sub-signals ReW in sequence, perform logical operations on the refresh window sub-signals ReW, and output the refresh window signal Refresh Window.
  • the refresh control circuit 101 is also used to receive the second refresh command AB CMD and perform the second refresh operation.
  • multiple refresh window sub-signal generation circuits 206 are also used to simultaneously receive the second refresh command AB CMD and the refresh window reset signal Refresh Window Reset, and generate one-to-one correspondence according to the second refresh command AB CMD and the refresh window reset signal Refresh Window Reset. The same multiple refresh window sub-signals ReW.
  • the refresh window sub-signal processing circuit 207 is also used to receive multiple refresh window sub-signals ReW, perform logical operations on the refresh window sub-signals ReW, and output a refresh window signal Refresh Window.
  • the second refresh operation is performed on all banks in the Bank Group at the same time, that is, All Bank Refresh.
  • the refresh control circuit 101 receives the second refresh command AB CMD and performs the second refresh operation, the first refresh command SB CMD does not include a valid pulse and remains low, that is, the first refresh command SB CMD is invalid, and then the count The signal Bank Counter also remains low, and the count refresh signal Bank Counter Reset does not generate a valid pulse and remains low.
  • the refresh control circuit 101 when the refresh control circuit 101 receives multiple first refresh commands SB CMD in sequence and performs the first refresh operation, the second refresh command AB CMD does not include valid pulses and remains low, that is, the second refresh command SB CMD is invalid.
  • multiple refresh window sub-signal generation circuits 206 when multiple refresh window sub-signal generation circuits 206 receive multiple first refresh commands SB CMD, since the multiple first refresh commands SB CMD are different, the multiple refresh window sub-signals ReW generated are Each is different. When the multiple refresh window sub-signal generating circuits 206 receive the second refresh command AB CMD, they can generate multiple identical refresh window sub-signals ReW.
  • the refresh control circuit 101 can sequentially receive multiple first refresh commands SB CMD and perform the first refresh operation as needed, or receive the second refresh command AB CMD and perform the second refresh operation. That is to say, using one set of refresh control circuit 101 can flexibly perform two refresh operations, thus improving the compatibility of the circuit.
  • the refresh control circuit 101 also includes: a second pulse generation sub-circuit 208, an internal refresh window signal generation circuit 209, an address command signal generation circuit 210, and a refresh window reset signal generation circuit. Circuit 211.
  • the second pulse generation sub-circuit 208 is coupled to the refresh window sub-signal processing circuit 207 for receiving the refresh window signal Refresh Window and the address command signal Addr CMD.
  • the control circuit 101 starts to perform the first refresh operation or the second refresh operation, it generates the first pulse of the third clock signal AB CBR CLK, and outputs the second pulse of the third clock signal AB CBR CLK according to the first pulse of the address command signal Addr CMD. pulse, thereby outputting the third clock signal AB CBR CLK.
  • the refresh control circuit 101 sequentially receives a plurality of first refresh commands SB CMD and performs a first refresh operation
  • the first pulse of the third clock signal AB CBR CLK is aligned with the plurality of first refresh commands SB CMD ⁇
  • the valid pulses of 0> ⁇ SB CMD ⁇ 3>, that is, the first pulse of the third clock signal AB CBR CLK is generated when the refresh control circuit 101 starts to perform the first refresh operation;
  • the second pulse of the third clock signal AB CBR CLK Aligned to the first pulse of the address command signal Addr CMD that is, the second pulse of the third clock signal AB CBR CLK is generated based on the first pulse of the address command signal Addr CMD.
  • the refresh control circuit 101 when the refresh control circuit 101 receives the second refresh command AB CMD and performs the second refresh operation, the first pulse of the third clock signal AB CBR CLK is aligned with the effective pulse of the second refresh command AB CMD, that is, the first pulse of the third clock signal AB CBR CLK is aligned with the valid pulse of the second refresh command AB CMD.
  • the first pulse of the third clock signal AB CBR CLK is generated when the refresh control circuit 101 starts to perform the second refresh operation; the second pulse of the third clock signal AB CBR CLK is aligned with the first pulse of the address command signal Addr CMD, that is, the second pulse of the third clock signal AB CBR CLK.
  • the second pulse of the three clock signals AB CBR CLK is generated based on the first pulse of the address command signal Addr CMD.
  • the internal refresh window signal generation circuit 209 receives the third clock signal AB CBR CLK and is used to generate the internal refresh window signal Inner ACT Window according to the third clock signal AB CBR CLK. ; Among them, the first pulse of the internal refresh window signal Inner ACT Window is generated after the first pulse of the third clock signal AB CBR CLK, and ends before the second pulse of the third clock signal AB CBR CLK is generated; the internal refresh window signal The second pulse of the Inner ACT Window is generated after the second pulse of the third clock signal AB CBR CLK and ends before the pulse of the refresh window signal Refresh Window ends.
  • the refresh controller in the memory will receive the internal refresh window signal Inner ACT Window and the address to be refreshed Adress and refresh the storage unit according to the internal refresh window signal Inner ACT Window, so the internal refresh window signal Inner ACT Window pulse The duration is the time for the storage unit to be refreshed.
  • the address command signal generation circuit 210 is used to generate the first pulse and the second pulse of the address command signal Addr CMD according to the falling edge of the internal refresh window signal Inner ACT Window; Among them, the first pulse of the address command signal Addr CMD is used to generate the second pulse of the internal refresh window signal Inner ACT Window and the second pulse of the third clock signal AB CBR CLK. A falling edge of the internal refresh window signal Inner ACT Window indicates the end of the refresh of an address, thereby generating the address command signal Addr CMD to control the generation of the next address.
  • the effective pulse of the internal refresh window signal Inner ACT Window can be compressed and shifted to obtain the effective pulse of the internal pre-command signal Inner PRE CMD. That is to say, first according to the internal refresh window signal Inner ACT Window The falling edge of the internal pre-command signal Inner PRE CMD is obtained; then, the address command signal generation circuit 210 can generate the first pulse and the second pulse of the address command signal Addr CMD according to the falling edge of the internal pre-command signal Inner PRE CMD.
  • the refresh window reset signal generation circuit 211 receives the internal refresh window signal Inner ACT Window and is used to generate the signal based on the falling edge of the second pulse of the internal refresh window signal Inner ACT Window.
  • Refresh window reset signal Refresh Window Reset pulse Refresh window reset signal Refresh Window Reset pulse.
  • the refresh control circuit 101 further includes: a signal selection circuit 212 .
  • the signal selection circuit 212 is coupled to the counting circuit 203, the first pulse generating sub-circuit 205 and the second pulse generating sub-circuit 208 for receiving the counting signal Bank Counter, the first The clock signal, the second clock signal (the first clock signal and the second clock signal are the SameBank refresh clock signal SB CBR CLK) and the third clock signal AB CBR CLK, when the refresh control circuit 101 performs the first refresh operation, according to the count signal
  • the Bank Counter outputs the first clock signal or the second clock signal, or when the refresh control circuit 101 performs the second refresh operation, the Bank Counter outputs the third clock signal AB CBR CLK according to the counting signal.
  • the signal selection circuit 212 when the refresh control circuit 101 performs the first refresh operation, if any count signal Bank Counter is high level, the signal selection circuit 212 outputs the first clock signal, that is, outputs the SameBank refresh clock signal. SB CBR CLK is low level. If all count signals Bank Counter jump to low level, the signal selection circuit 212 outputs the second clock signal, that is, outputs two consecutive valid pulses in the SameBank refresh clock signal SB CBR CLK.
  • the refresh control circuit 101 further includes: an address flag signal generating circuit 213 .
  • the address flag signal generation circuit 213 is coupled to the address command signal generation circuit 210 and the refresh window sub-signal processing circuit 207 for receiving the address command signal Addr CMD and the refresh window.
  • the signal Refresh Window generates the rising edge of the address flag signal Addr Flag according to the first rising edge of the address command signal Addr CMD, and generates the falling edge of the address flag signal Addr Flag according to the falling edge of the refresh window signal Refresh Window.
  • the address generator 102 includes: an address counter 301 and an address processing circuit 302 .
  • the address counter 301 is coupled to the signal selection circuit 212, used to prestore the first address, and receives the SameBank refresh clock signal SB CBR CLK or the third clock signal AB CBR CLK (not shown in Figure 6) from the signal selection circuit 212.
  • the address counter 301 can change the first address to the third address according to the second clock signal in the SameBank refresh clock signal SB CBR CLK, or change the first address and output the fourth address and the fifth address according to the third clock signal AB CBR CLK. .
  • the address processing circuit 302 is coupled to the address counter 301 and the refresh window sub-signal generation circuit 206, and is used to receive the address flag signal Addr Flag when the refresh control circuit 101 performs the first refresh operation, and obtain the first address.
  • the address processing circuit 302 is also configured to sequentially obtain the fourth address and the fifth address when the refresh control circuit 101 performs the second refresh operation, and sequentially output the fourth address and the fifth address according to the plurality of refresh window sub-signals ReW.
  • the refresh control circuit 101 when the refresh control circuit 101 performs the first refresh operation, the first address is a pre-stored address, and the second address is obtained by inverting the lowest bit of the first address, that is, the first address and the second address are two consecutive addresses. Therefore, the third address accumulates the value 2 on the basis of the first address to avoid repeating the first refresh operation on the same address. In this way, after all banks have completed the first refresh operation of the first address and the second address, the first address is converted into the third address by the accumulated value 2, and the refresh control circuit 101 can use the third address as a pre-stored address. To perform a new round of first refresh operation, thereby ensuring that the first refresh operation is performed without missing a beat.
  • the refresh control circuit 101 when the refresh control circuit 101 performs the second refresh operation, the first address is a prestored address, the fourth address has a value of 1 accumulated on the basis of the first address, and the fifth address is the fourth address.
  • the value 1 is accumulated on the basis of the address, that is to say, the first address, the fourth address and the fifth address are three consecutive addresses in sequence.
  • the refresh control circuit 101 can sequentially perform the second refresh operation on the addresses of all banks in address order, thereby ensuring that the second refresh operation is performed without missing a beat.
  • the address counter 301 when the signal selection circuit 212 outputs the second clock signal (ie, the two valid pulses in SB CBR CLK) to the address counter 301, the address counter 301 can be based on the second clock signal.
  • the two valid pulses of the clock signal sequentially accumulate the value 2 on the basis of the first address, thereby obtaining the third address.
  • the address counter 301 can accumulate the value 1 on the basis of the first address according to the first pulse of the third clock signal AB CBR CLK to obtain the third four addresses, and then the address counter 301 can accumulate the value 1 based on the fourth address according to the second pulse of the third clock signal AB CBR CLK to obtain the fifth address.
  • the address processing circuit 302 includes: a control signal generation circuit 303 and an address selection circuit 304 .
  • the control signal generation circuit 303 is coupled to the refresh window sub-signal generation circuit 206 and the address flag signal generation circuit 213, and is used to receive a plurality of refresh window sub-signals ReW and an address flag signal Addr Flag, according to the plurality of refresh window sub-signals ReW and address flags.
  • the signal Addr Flag generates the address control signal Addr Ctrl.
  • the address selection circuit 304 is coupled to the address counter 301 and the control signal generation circuit 303, and is used to output the first address according to the address control signal Addr Ctrl when the refresh control circuit 101 receives the first refresh command SB CMD, or to output the first address according to the address control signal Addr Ctrl inverts the first address and obtains and outputs the second address.
  • the address selection circuit 304 is also configured to sequentially output the fourth address and the fifth address in response to the address control signal Addr Ctrl when the refresh control circuit 101 receives the second refresh command AB CMD.
  • the counting circuit 203 includes: a plurality of first inverters D1, a plurality of first latches L1, and a second inverter D2.
  • the input terminals of the plurality of first inverters D1 receive a plurality of first refresh commands SB CMD in sequence.
  • the input terminal of the second inverter D2 receives the count reset signal Bank Counter Reset.
  • the set terminals of the plurality of first latches L1 are connected to the output terminals of the plurality of first inverters D1 in sequence, and the reset terminals of the plurality of first latches L1 are connected to the output terminals of the second inverter D2.
  • a plurality of first latches L1 correspondingly output a plurality of counting signals Bank Counter in sequence.
  • each valid pulse in the first refresh command SB CMD can trigger the corresponding count signal Bank Counter to jump from low level. to high level.
  • the pulse in the first refresh command SB CMD ⁇ 0> can trigger the instruction count signal Bank Counter ⁇ 0> to change from low level to high level.
  • the first refresh command SB CMD ⁇ 1 > can respectively trigger the instruction count signals Bank Counter ⁇ 1>, Bank Counter ⁇ 2> and Bank Counter ⁇ 3> to change from low level to high level.
  • the valid pulse in the count reset signal Bank Counter Reset can trigger all count signals Bank Counter ⁇ 0> ⁇ Bank Counter ⁇ 3> to jump from high level to low level.
  • the valid pulse in the count reset signal Bank Counter Reset is generated after the refresh control circuit completes the m-th first refresh operation.
  • the count reset signal generation circuit 204 includes: a first AND gate A1, a third inverter D3, a second AND gate A2, a first delayer H1, a third Quad inverter D4 and third AND gate A3.
  • the input terminal of the first AND gate A1 receives multiple counting signals Bank Counter.
  • the input terminal of the third inverter D3 receives the refresh window signal Refresh Window.
  • the input terminal of the second AND gate A2 is respectively connected to the output terminal of the first AND gate A1 and the output terminal of the third inverter D3.
  • the input terminal of the first delayer H1 is connected to the output terminal of the second AND gate A2.
  • the input terminal of the fourth inverter D4 is connected to the output terminal of the first delayer H1.
  • the input terminal of the third AND gate A3 is respectively connected to the output terminal of the second AND gate A2 and the output terminal of the fourth inverter D4.
  • the third AND gate A3 outputs a count reset signal Bank Counter Reset.
  • the first pulse generation sub-circuit 205 includes: a second delayer H2, a third delayer H3, and a first OR gate B1.
  • the input terminal of the second delayer H2 receives the count reset signal Bank Counter Reset.
  • the input terminal of the third delayer H3 is connected to the output terminal of the second delayer H2.
  • the input terminals of the first OR gate B1 are respectively connected to the output terminals of the second delayer H2 and the output terminal of the third delayer H3.
  • the first OR gate B1 outputs the first clock signal or the second clock signal, that is to say, The first OR gate B1 outputs the SameBank refresh clock signal SB CBR CLK.
  • the pulses in the count reset signal Bank Counter Reset are based on the count signal Bank Counter ⁇ 0>, Bank Counter ⁇ 1>, Bank Counter ⁇ 2>, Bank Counter ⁇ 3> and the refresh window signal Refresh Window are generated.
  • a valid pulse in the count reset signal Bank Counter Reset after passing through the second delayer H2, the third delayer H3 and the first OR gate B1, generates two valid pulses in the SB CBR CLK.
  • the first delayer H1 can delay the received signal by 0 ⁇ 2ns
  • the second delayer H2 can delay the received signal by 1 ⁇ 3ns
  • the third delayer H3 can delay the received signal by 0 ⁇ 2ns.
  • the delay is 4 ⁇ 6ns.
  • the refresh window sub-signal includes: a first refresh window sub-signal ReW ⁇ i> or a second refresh window sub-signal ReW ⁇ AB>.
  • Each refresh window sub-signal generating circuit 206 includes: a first NOR gate E1 and a second latch L2. When the refresh control circuit performs the first refresh operation, the first input terminal of the first NOR gate E1 receives the corresponding first refresh command SB CMD ⁇ i>, or when the refresh control circuit performs the second refresh operation, the first The second input terminal of the NOR gate E1 receives the second refresh command AB CMD.
  • the set terminal of the second latch L2 is connected to the output terminal of the first NOR gate E1, and the reset terminal of the second latch L2 receives the refresh window reset signal Refresh Window Reset; when the refresh control circuit performs the first refresh operation, The second latch L2 outputs the corresponding first refresh window sub-signal ReW ⁇ i>, or when the refresh control circuit performs the second refresh operation, the second latch L2 outputs the corresponding second refresh window sub-signal ReW ⁇ AB >.
  • i is greater than or equal to 0 and less than or equal to m-1
  • the first refresh command SB CMD ⁇ i> is any one of multiple first refresh commands
  • the first refresh window sub-signal ReW ⁇ i> corresponds to the first refresh command SB CMD ⁇ i>.
  • the valid pulse in the first refresh command SB CMD ⁇ 0> triggers The first refresh window sub-signal ReW ⁇ 0> jumps from low level to high level
  • the first valid pulse in the refresh window reset signal Refresh Window Reset triggers the first refresh window sub-signal ReW ⁇ 0> from high level. Jumps to low level, thereby obtaining the valid pulse of the first refresh window sub-signal ReW ⁇ 0>.
  • the valid pulses in the first refresh instructions SB CMD ⁇ 0>, SB CMD ⁇ 1> and SB CMD ⁇ 2> trigger the first refresh window sub-signals ReW ⁇ 0>, ReW ⁇ 1> and ReW ⁇ 2> respectively.
  • the second to four valid pulses in the refresh window reset signal Refresh Window Reset trigger the first refresh window sub-signals ReW ⁇ 0>, ReW ⁇ 1> and ReW ⁇ 2> respectively.
  • the high level jumps to the low level, thereby obtaining effective pulses of the first refresh window sub-signals ReW ⁇ 0>, ReW ⁇ 1> and ReW ⁇ 2>.
  • the valid pulse in the second refresh command AB CMD triggers the second refresh window sub-signal ReW ⁇ AB> to jump from a low level to high level
  • the valid pulse in the refresh window reset signal Refresh Window Reset triggers the second refresh window sub-signal ReW ⁇ AB> to jump from high level to low level, thereby obtaining the second refresh window sub-signal ReW ⁇ AB > effective pulse.
  • the refresh window sub-signal processing circuit 207 includes: a second OR gate B2.
  • the input end of the second OR gate B2 receives a plurality of first refresh window sub-signals ReW ⁇ i> from the plurality of refresh window sub-signal generating circuits 206 respectively, or when the refresh control circuit
  • the input terminal of the second OR gate receives the same plurality of second refresh window sub-signals ReW ⁇ AB> from the plurality of refresh window sub-signal generating circuits 206 respectively.
  • the second OR gate B2 outputs the refresh window signal Refresh Window.
  • the refresh window signal generation circuit 201 further includes a thirteenth inverter D13.
  • the refresh window reset signal Refresh Window Reset is transmitted to multiple refresh window sub-signal generating circuits 206 through the thirteenth inverter D13.
  • the refresh window signal Refresh Window output by the second OR gate B2 will include all valid pulses in the first refresh window sub-signal ReW ⁇ 0> ⁇ ReW ⁇ 3>.
  • the second OR gate B2 receives the same plurality of second refresh window sub-signals ReW ⁇ AB>, and the second OR gate B2
  • the refresh window signal Refresh Window output by B2 has the same waveform as the second refresh window sub-signal ReW ⁇ AB>.
  • the second pulse generation sub-circuit 208 includes: a fourth delayer H4, a fifth inverter D5, a fourth AND gate A4, and a sixth inverter D6 , the fifth AND gate A5, the second NOR gate E2 and the seventh inverter D7.
  • the input terminal of the fourth delayer H4 receives the refresh window signal Refresh Window.
  • the input terminal of the fifth inverter D5 is connected to the output terminal of the fourth delayer H4.
  • the first input terminal of the fourth AND gate A4 receives the refresh window signal Refresh Window, and the second input terminal of the fourth AND gate A4 is connected to the output terminal of the fifth inverter D5.
  • the input terminal of the sixth inverter D6 receives the address flag signal Addr Flag.
  • the first input terminal of the fifth AND gate A5 is connected to the output terminal of the sixth inverter D6, and the second input terminal of the fifth AND gate A5 receives the address command signal Addr CMD.
  • the input terminal of the second NOR gate E2 is respectively connected to the output terminal of the fourth AND gate A4 and the output terminal of the fifth AND gate A5.
  • the input terminal of the seventh inverter D7 is connected to the output terminal of the second NOR gate E2, and the seventh inverter D7 outputs the third clock signal AB CBR CLK.
  • the fourth delayer H4 can delay the received refresh window signal Refresh Window by 1 to 3 ns. Furthermore, after the refresh window signal Refresh Window passes through the fourth delayer H4, the fifth inverter D5 and the fourth AND gate A4, it can be converted into the internal activation command signal Inner ACT CMD. Among them, the pulse in the internal activation command signal Inner ACT CMD corresponds to the rising edge of the refresh window signal Refresh Window. After passing through the second NOR gate E2 and the seventh inverter D7, the pulse forms the third clock signal AB CBR CLK the first pulse. The second pulse of the third clock signal AB CBR CLK is formed based on the address flag signal Addr Flag and the address command signal Addr CMD.
  • the address command signal generation circuit 210 includes: an eighth inverter D8, a fifth delayer H5, and a sixth AND gate A6.
  • the input terminal of the eighth inverter D8 receives the internal refresh window signal Inner ACT Window.
  • the input terminal of the fifth delayer H5 is connected to the input terminal of the eighth inverter D8 and receives the internal refresh window signal Inner ACT Window.
  • the input terminals of the sixth AND gate A6 are respectively connected to the output terminal of the eighth inverter D8 and the output terminal of the fifth delay device H5.
  • the sixth AND gate A6 outputs the address command signal Addr CMD.
  • the fifth delayer H5 can delay the received internal refresh window signal Inner ACT Window by 0 to 2 ns.
  • the eighth inverter D8 the fifth delay H5 and the sixth AND gate A6, the first pulse of the internal refresh window signal Inner ACT Window can be converted into the third pulse of the address command signal Addr CMD.
  • One pulse, the second pulse of the internal refresh window signal Inner ACT Window can be converted into the second pulse of the address command signal Addr CMD.
  • the internal refresh window signal generation circuit 209 includes: a third latch L3.
  • the set terminal of the third latch L3 receives the third clock signal AB CBR CLK, the reset terminal of the third latch L3 is connected to the output terminal of the eighth inverter D8, and the third latch L3 outputs the internal refresh window signal.
  • Inner ACT Window receives the third clock signal AB CBR CLK.
  • the refresh window reset signal generation circuit 211 includes: a sixth delayer H6, a seventh AND gate A7, and a seventh delayer H7.
  • the input terminal of the sixth delayer H6 receives the address flag signal Addr Flag.
  • the first input terminal of the seventh AND gate A7 is connected to the output terminal of the sixth delayer H6, and the second input terminal of the seventh AND gate A7 receives the internal refresh window signal Inner ACT Window.
  • the input terminal of the seventh delayer H7 is connected to the output terminal of the seventh AND gate A7, and the seventh delayer H7 outputs the refresh window reset signal Refresh Window Reset.
  • the sixth delayer H6 can delay the received address flag signal Addr Flag by 0 to 2 ns, and the seventh delayer H7 can delay the received signal by 4 to 6 ns.
  • the refresh window reset signal Refresh Window can be obtained from the internal refresh window signal Inner ACT Window and the address flag signal Addr Flag. Reset.
  • the signal selection circuit 212 includes: a third NOR gate E3, a third OR gate B3, and an eighth AND gate A8.
  • the input terminals of the third NOR gate E3 respectively receive multiple counting signals Bank Counter.
  • the first input terminal of the third OR gate B3 receives the first clock signal or the second clock signal, that is, the first input terminal of the third OR gate B3 receives the SameBank refresh clock signal SB CBR CLK, and the second input terminal of the third OR gate B3 The terminal receives the third clock signal AB CBR CLK.
  • the first input terminal of the eighth AND gate A8 is connected to the output terminal of the third NOR gate E3, the second input terminal of the eighth AND gate A8 is connected to the output terminal of the third OR gate B3, and the eighth AND gate A8 outputs the first clock. signal, the second clock signal or the third clock signal AB CBR CLK.
  • the waveforms of each signal received by the signal selection circuit 212 are as shown in Figure 4.
  • the third OR gate B3 outputs The signal can include all valid pulses in the SameBank refresh clock signal SB CBR CLK and the third clock signal AB CBR CLK.
  • the signal output by the third NOR gate E3 can shield the valid pulses in the third clock signal AB CBR CLK.
  • the signal output by the eighth AND gate A8 has the same waveform as the SameBank refresh clock signal SB CBR CLK. That is to say, when the first refresh operation is performed, the eighth AND gate A8 outputs the first clock signal or the second clock signal.
  • the multiple count signals Bank Counter ⁇ 0> ⁇ Bank Counter ⁇ 3> and the SameBank refresh clock signal SB CBR CLK all remain low (not shown in Figure 4), and the third The waveform of the clock signal AB CBR CLK is still as shown in Figure 4.
  • the signal output by the eighth AND gate A8 is the same as the waveform of the third clock signal AB CBR CLK. That is to say, when the first refresh operation is performed, The eighth AND gate A8 outputs the third clock signal AB CBR CLK.
  • the address flag signal generating circuit 213 includes: a ninth inverter D9 and a fourth latch L4.
  • the input terminal of the ninth inverter D9 receives the address command signal Addr CMD.
  • the set terminal of the fourth latch L4 is connected to the output terminal of the ninth inverter D9, the reset terminal of the fourth latch L4 receives the refresh window signal Refresh Window, and the fourth latch L4 outputs the address flag signal Addr Flag.
  • the first pulse of the address command signal Addr CMD triggers the address flag signal Addr Flag to jump from low level to high level, and the falling edge of the refresh window signal Refresh Window triggers the address flag.
  • the signal Addr Flag jumps from high level to low level, thereby obtaining the waveform of the address flag signal Addr Flag shown in Figure 25.
  • Figure 26 shows an optional implementation of the refresh control circuit 101.
  • Figure 26 includes Figures 8, 10, 11, 13, 16, 17, 19, 21, 23 and Circuit elements shown in Figure 24.
  • Figures 27 and 28 show an optional waveform diagram of some of the signals in Figure 26.
  • Figure 27 is a schematic diagram of the corresponding signals when the refresh control circuit 101 performs the first refresh operation.
  • Figure 28 is a schematic diagram of the refresh control circuit. 101 corresponds to the signal diagram when performing the second refresh operation.
  • the four first refresh instructions SB CMD ⁇ 0>, SB CMD ⁇ 1>, SB CMD ⁇ 2> and SB CMD ⁇ 3> includes valid pulses
  • the second refresh command AB CMD does not include valid pulses, that is, the second refresh command AB CMD remains low. Therefore, the set ends of the four first latches L1 respectively receive the four first refresh instructions SB CMD ⁇ 0>, SB CMD ⁇ 1>, SB CMD ⁇ 2> and SB through the four first inverters D1.
  • the four first latches L1 respectively output four counting signals Bank Counter ⁇ 0>, Bank Counter ⁇ 1>, Bank Counter ⁇ 2> and Bank Counter ⁇ 3> to the third NOR gate E3 input terminal and the input terminal of the first AND gate A1.
  • the signal selection circuit 212 outputs the SameBank refresh clock signal SB CBR CLK (ie, the first clock signal or the second clock signal) through the eighth AND gate A8.
  • the set ends of the four second latches L2 receive the four first refresh instructions SB CMD ⁇ 0>, SB CMD ⁇ 1>, SB CMD ⁇ 2> and SB respectively through the four first NOR gates E1.
  • the four second latches L2 respectively output four first refresh window sub-signals ReW ⁇ 0>, ReW ⁇ 1>, ReW ⁇ 2> and ReW ⁇ 3>.
  • the signal selection circuit 212 outputs the SameBank refresh clock signal SB CBR CLK (i.e. the first clock signal or the second clock signal) to Address processing circuit 302, four refresh window sub-signal generation circuits 206 output four first refresh window sub-signals ReW ⁇ 0>, ReW ⁇ 1>, ReW ⁇ 2> and ReW ⁇ 3> to the address processing circuit 302, address flag
  • the signal generation circuit 213 outputs the address flag signal Addr Flag to the address processing circuit 302.
  • the four first refresh instructions SB CMD ⁇ 0>, SB CMD ⁇ 1>, SB CMD ⁇ 2> and SB CMD ⁇ 3> does not include valid pulses, that is, the four first refresh instructions SB CMD ⁇ 0>, SB CMD ⁇ 1>, SB CMD ⁇ 2> and SB CMD ⁇ 3> all remain low
  • the second refresh command AB CMD includes valid pulses.
  • the four count signals Bank Counter ⁇ 0>, Bank Counter ⁇ 1>, Bank Counter ⁇ 2> and Bank Counter ⁇ 3> output by the four first latches L1 all remain low (not shown in Figure 28 out).
  • the signal selection circuit 212 outputs the third clock signal AB CBR CLK through the eighth AND gate A8.
  • the set ends of the four second latches L2 receive the second refresh command AB CMD through the four first NOR gates E1, and the four second latches L2 all output four identical second refresh windows. Sub-signal ReW ⁇ AB>.
  • the control signal generation circuit 303 includes: a ninth AND gate A9, a tenth inverter D10, and a fourth NOR gate E4.
  • the input terminals of the ninth AND gate A9 respectively receive multiple refresh window sub-signals ReW.
  • the input terminal of the tenth inverter D10 receives the address flag signal Addr Flag.
  • the first input terminal of the fourth NOR gate E4 is connected to the output terminal of the ninth AND gate A9, the second input terminal of the fourth NOR gate E4 is connected to the output terminal of the tenth inverter D10, and the output terminal of the fourth NOR gate E4 is Address control signal Addr Ctrl.
  • each input end of the ninth AND gate A9 receives a plurality of first refresh operations. Refresh the window sub-signals ReW ⁇ 0>, ReW ⁇ 1>, ReW ⁇ 2> and ReW ⁇ 3>, then the signal ReW ⁇ And> output by the ninth AND gate A9 is always low level.
  • the address control signal Addr Ctrl The waveform is the same as the address flag signal Addr Flag, that is to say, the address flag signal Addr Flag still maintains the same waveform after passing through the control signal generation circuit 303.
  • each input terminal of the ninth AND gate A9 receives the same second refresh window sub-signal ReW ⁇ AB>, then the ninth AND gate A9
  • the output signal ReW ⁇ And> has the same waveform as the second refresh window sub-signal ReW ⁇ AB>, and the high-level area of the signal ReW ⁇ And> covers the high-level area of the address flag signal Addr Flag.
  • the signal ReW ⁇ And> can shield the high level area of the address flag signal Addr Flag, so that the address control signal Addr Ctrl is always low level, that is to say, the address flag signal Addr Flag passes through the control signal generation circuit Blocked after 303.
  • the multiple first refresh window sub-signals ReW ⁇ 0>, ReW ⁇ 1>, ReW ⁇ 2> and ReW ⁇ 3> shown in Figure 30 are different from the multiple first refresh window sub-signals shown in Figure 14
  • the waveforms of the signals ReW ⁇ 0>, ReW ⁇ 1>, ReW ⁇ 2> and ReW ⁇ 3> are the same, that is to say, the multiple first refresh window sub-signals ReW ⁇ 0>, ReW ⁇ 1>, ReW in Figure 30 ⁇ 2> and ReW ⁇ 3> can be obtained according to the example of Figure 14.
  • the second refresh window sub-signal ReW ⁇ AB> shown in FIG. 31 has the same waveform as the second refresh window sub-signal ReW ⁇ AB> shown in FIG. 15 , that is to say, the second refresh window sub-signal ReW ⁇ in FIG. 31 AB> can be obtained according to the example in Figure 15.
  • the address selection circuit 304 includes: a non-inverting output module 305, an inverting output module 306, an eleventh inverter D11 and an address delay module 307.
  • the input end of the non-inverting output module 305 is connected to the address counter 301.
  • the first control end of the in-phase output module 305 is configured to receive the address control signal Addr Ctrl.
  • the second control end of the in-phase output module 305 is configured to receive the address control signal through the eleventh inverter D11.
  • the non-phase output module 305 is configured to acquire and output the lowest bit of the first address in response to the address control signal Addr Ctrl when the refresh control circuit receives the first refresh instruction and the address flag signal Addr Flag is the first value.
  • the input end of the inverting output module 306 is connected to the address counter 301.
  • the first control end of the inverting output module 306 is configured to receive the address control signal Addr Ctrl through the eleventh inverter D11.
  • the second control end of the inverting output module 306 Configured to receive the address control signal Addr Ctrl.
  • the inverting output module 306 is configured to, when the refresh control circuit receives the first refresh instruction and the address flag signal Addr Flag is the second value, in response to the address control signal Addr Ctrl, obtain the lowest bit of the first address and change the lowest bit of the first address. Output after bit inversion.
  • the address delay module 307 is connected to the address counter 301 and is configured to obtain other bits of the first address when the refresh control circuit receives the first refresh instruction, and output the other bits of the first address after delay, wherein the other bits are except the lowest bits other than address bits.
  • the first address received by the address selection circuit 304 from the address counter 301 is divided into two parts for transmission, in which the lowest bit of the first address is transmitted to the non-inverting output module 305 and the inverting output module 306, The bits in the first address except the lowest bit are transferred to the address delay module 307.
  • the non-inverting output module 305 and the inverting output module 306 both receive the address control signal Addr Ctrl.
  • the in-phase output module 305 outputs the lowest bit of the first address under the control of the address control signal Addr Ctrl, while the inverting output module 306 outputs the lowest bit of the first address under the control of the address control signal Addr Ctrl.
  • the number of address bits of the first address can be set according to actual needs. For example, if the first address Address ⁇ 15:0> is a 16-bit address, then the lowest bit of the first address Address ⁇ 15:0> is the 16-bit address.
  • the 15-bit address Address ⁇ 15>, the address bits except the lowest bit in the first address Address ⁇ 15:0> are the 0th to 14th address Address ⁇ 14:0>. This disclosure does not limit this.
  • the address counter 301 when the refresh control circuit receives the first refresh command, the address counter 301 receives the SameBank refresh clock signal SB CBR CLK, that is, receives the first clock signal or the second clock Signal.
  • the address output signal Addr Counter Output represents the first address stored by the address counter 301.
  • the address control signal Addr Ctrl when the address counter 301 receives the first clock signal, the first address remains n unchanged; and the address selection circuit 304 outputs the to-be-received address. Refreshing the address Address is controlled by the address control signal Addr Ctrl, and alternately outputs n and n+1, or alternately outputs n and n-1.
  • n+1 or n-1 is the second address, and the lowest bit of the second address is opposite to the lowest bit of the first address n.
  • the address counter 301 When the number of first refresh operations reaches m, that is, after all banks have completed the first refresh operation of this round, the address counter 301 receives the second clock signal. Since the second clock signal includes two valid pulses, the address counter 301 301 will accumulate 2 on the first address, that is, change the first address to the third address. At this time, all banks in the Bank Group have completed the previous round of first refresh operations. After the refresh control circuit receives the next round of first refresh instructions, it can perform the next round of first refresh operations according to the third address.
  • the current first address is 0000.
  • the lowest bit of the first address is flipped and becomes the second address 0001.
  • the second address is incremented by 1 relative to the first address.
  • the first refresh operation (Same Bank Refresh) is performed on each bank.
  • the address generator 102 is triggered by two pulses in the second clock signal, accumulates 2 to the first address, outputs 0010, and then performs the first refresh operation of the next round.
  • the current first address is 0001.
  • the lowest bit of the first address is flipped and becomes the second address 0000.
  • the second address is decremented by 1 relative to the first address.
  • the address is generated.
  • the device 102 is triggered by two pulses in the second clock signal, accumulates 2 on the first address, outputs 0011, and then performs the next round of first refresh operation.
  • the waveform of the first clock signal or the second clock signal shown in Figure 33 is the same as that of the first clock signal or the second clock signal shown in Figure 2. That is to say, the first clock signal or the second clock signal shown in Figure 33 can be obtained by the example of Figure 2 Come and get.
  • the first refresh operation when the SameBank in the Bank Group performs the first refresh operation, the first refresh operation will be performed on two adjacent addresses in a group of SameBanks (i.e. n and n+1, or n and n-1) , and the first address n remains unchanged during this process.
  • the first address accumulates 2 and becomes the third address.
  • the next round of first refresh operation can be performed according to the third address. In this way, the first refresh operation can be performed on the addresses in each bank in the order of the addresses, ensuring the continuity of the refresh addresses and avoiding missing addresses without performing the first refresh operation.
  • the non-inverting output module 305 is also configured to obtain and output the lowest bit of the fourth address or the fifth address in response to the address control signal Addr Ctrl when the refresh control circuit receives the second refresh instruction. lowest position.
  • the address delay module 307 is also configured to obtain other bits of the fourth address or other bits of the fifth address and delay other bits of the fourth address or other bits of the fifth address when the refresh control circuit receives the second refresh instruction. output later.
  • the fourth address or the fifth address received by the address selection circuit 304 from the address counter 301 is divided into two parts for transmission, in which the lowest bit of the address is transmitted to the non-inverting output module 305 and the inverting output module. 306.
  • the other bits in the address except the lowest bit are transmitted to the delay module 307.
  • Both the non-inverting output module 305 and the inverting output module 306 receive the address control signal Addr Ctrl.
  • the non-inverting output module 305 outputs the lowest bit of the address under the control of the address control signal Addr Ctrl, while the inverting output module 306 outputs the lowest bit of the address under the control of the address control signal Addr Ctrl.
  • the lowest bit of the address is inverted and output. Since the lowest bit of the address will be delayed in timing after passing through the non-inverting output module 305 or the inverting output module 306, other bits of the address need to pass through the address delay module 307 to match the timing.
  • the address counter 301 receives the third clock signal AB CBR CLK. Each valid pulse in the third clock signal AB CBR CLK will trigger the address counter 301 to accumulate 1 on the first address.
  • the address output signal Addr Counter Output represents the first address stored by the address counter 301.
  • the address output signal Addr Counter Output is accumulated under the trigger of the third clock signal AB CBR CLK.
  • the third clock signal AB CBR CLK shown in Figure 34 includes four cycles, and every two valid pulses are one cycle. Therefore, in the first cycle, the first address n is triggered to change to the fifth address n. +2; in the second cycle, n+2 is triggered as the first address and changes to the fifth address n+4, and so on.
  • the address control signal Addr Ctrl remains low, so the inverting output module 306 does not work, and the lowest bits of the address are output through the non-inverting output module 305, that is, the address to be refreshed for the second refresh operation Address is consistent with the address output signal Addr Counter Output.
  • the second refresh operation can be performed on the addresses in all banks in the order of the addresses, thereby avoiding missing addresses and not performing the second refresh operation.
  • the address generator 102 when all Banks in the Bank Group perform the second refresh operation, the address generator 102 generates continuous addresses to be refreshed according to the third clock signal AB CBR CLK, so that each address in all Banks completes the first refresh operation in sequence. 2.
  • Refresh operation i.e. All Bank Refresh.
  • the second refresh operation can be performed on the addresses in all banks in the order of the addresses, ensuring the continuity of the refresh addresses and avoiding missing addresses without performing the second refresh operation.
  • using a set of address generators 102 can flexibly perform two refresh operations, thus improving the compatibility of the circuit.
  • the non-inverting output module 305 includes: a first PMOS transistor P1 and a first NMOS transistor N1.
  • the inverting output module 306 includes: a twelfth inverter D12, a second PMOS transistor P2, and a second NMOS transistor N2.
  • the gate of the first PMOS transistor P1 serves as the first control terminal of the non-inverting output module 305
  • the gate of the first NMOS transistor N1 serves as the second control terminal of the non-inverting output module 305
  • the source of the first PMOS transistor P1 is connected to the first NMOS.
  • the drain of the transistor N1 serves as the input terminal of the non-inverting output module 305 .
  • the drain of the first PMOS transistor P1 is connected with the source of the first NMOS transistor N1 and serves as the output terminal of the non-inverting output module 305 .
  • the gate of the second PMOS transistor P2 serves as the first control terminal of the inverting output module 306
  • the gate of the second NMOS transistor N2 serves as the second control terminal of the inverting output module 306, and the input terminal of the twelfth inverter D12
  • the output terminal of the twelfth inverter D12 is connected to the source of the second PMOS transistor P2 and the drain of the second NMOS transistor N2, and the drain of the second PMOS transistor P2 is connected to the second
  • the source of the NMOS transistor N2 also serves as the output terminal of the inverting output module 306 .
  • the source of the first PMOS transistor P1 is connected to the drain of the first NMOS transistor N1 and serves as the input terminal of the non-inverting output module 305 to receive the lowest bit of the address from the address counter 301 .
  • the address control signal Addr Ctrl is low level, the first PMOS transistor P1 and the first NMOS transistor N1 are in the on state, and the lowest bit of the address is output by the drain of the first PMOS transistor P1 and the source of the first NMOS transistor N1 ; If the address control signal Addr Ctrl is high level, the first PMOS transistor P1 and the first NMOS transistor N1 are in a cut-off state, and the drain of the first PMOS transistor P1 and the source of the first NMOS transistor N1 do not output a signal.
  • the input terminal of the twelfth inverter D12 serves as the input terminal of the inverting output module 306 and receives the lowest bit of the address from the address counter 301.
  • the lowest bit of the address is inverted after passing through the twelfth inverter D12. If the address control signal Addr Ctrl is high level, the second PMOS transistor P2 and the second NMOS transistor N2 are in the on state, and the lowest bit of the inverted address is determined by the drain of the second PMOS transistor P2 and the second NMOS transistor.
  • non-inverting output module 305 can also be configured to output the lowest bit of the address when the address control signal Addr Ctrl is high level
  • the inverting output module 306 can also be configured to output the lowest bit of the address when the address control signal Addr Ctrl is low level. The lowest bit of the address is inverted and output. There is no restriction here.
  • the embodiment of the present disclosure provides a refresh address generation circuit, including: a refresh control circuit and an address generator.
  • the refresh control circuit receives multiple first refresh instructions in sequence and performs multiple first refresh operations correspondingly, outputs a first clock signal when the number of first refresh operations is less than m, and when the number of first refresh operations is equal to m
  • m is an integer greater than or equal to 1.
  • the address generator is coupled to the refresh control circuit, used to prestore the first address, receive the first clock signal or the second clock signal, output the address to be refreshed in response to the first clock signal during each first refresh operation, and respond to the first clock signal during each first refresh operation.
  • the second clock signal changes the first address.
  • the address to be refreshed includes a first address or a second address, and the lowest bit of the second address is opposite to the lowest bit of the first address.
  • the address generator responds to the first clock signal, not only outputs the address to be refreshed including the first address or the second address, but also maintains the first address unchanged; while during the first refresh After the number of operations is equal to m, the address generator responds to the second clock signal and then changes the first address. In this way, it not only ensures that the refresh operation is carried out without missing a thing, but also maintains the integrity of the address.

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Abstract

本公开实施例公开了一种刷新地址产生电路，包括：刷新控制电路和地址产生器。其中，刷新控制电路依次接收多个第一刷新指令并对应进行多次第一刷新操作，当第一刷新操作的次数小于m时输出第一时钟信号，以及，当第一刷新操作的次数等于m时输出第二时钟信号，m为大于或等于1的整数。地址产生器耦接刷新控制电路，用于预存第一地址，并接收第一时钟信号或第二时钟信号，在每一次第一刷新操作期间响应于第一时钟信号输出待刷新地址，以及，响应于第二时钟信号改变第一地址。待刷新地址包括第一地址或第二地址，第二地址的最低位与第一地址的最低位相反。

Description

一种刷新地址产生电路
相关申请的交叉引用
本公开基于申请号为202210601980.5、申请日为2022年05月30日、发明名称为“一种刷新地址产生电路”的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本公开作为参考。
技术领域
本公开涉及但不限于一种刷新地址产生电路。
背景技术
在存储器中，存储器被划分为多个存储体(Bank)，存储地址的刷新则存在两种模式：所有Bank就同一地址一起刷新操作的全存储体刷新(All Bank Refresh)，以及对位于同一存储体组(Bank Group)的不同Bank就同一地址依次先后刷新的相同存储体刷新(Same Bank Refresh)。
在进行Same Bank Refresh的过程中，如何产生地址和保存地址是需要解决的问题。
发明内容
有鉴于此，本公开实施例提供了一种刷新地址产生电路，能够在进行刷新操作的过程中，既生成待刷新地址，又维持预存的第一地址，如此，既保证了刷新操作不遗漏地进行，又维持了地址的完整性。
本公开实施例的技术方案是这样实现的：
本公开实施例提供一种刷新地址产生电路，所述刷新地址产生电路包括：
刷新控制电路，用于依次接收多个第一刷新指令并对应进行多次第一刷新操作，当所述第一刷新操作的次数小于m时输出第一时钟信号，以及，当所述第一刷新操作的次数等于m时输出第二时钟信号，m为大于或等于1的整数；
地址产生器，耦接所述刷新控制电路，用于预存第一地址，并接收所述第一时钟信号或所述第二时钟信号，在每一次第一刷新操作期间响应于所述第一时钟信号输出待刷新地址，以及，响应于所述第二时钟信号改变所述第一地址；所述待刷新地址包括所述第一地址或第二地址，所述第二地址的最低位与所述第一地址的最低位相反。
由此可见，本公开实施例提供了一种刷新地址产生电路，包括：刷新控制电路和地址产生器。其中，刷新控制电路依次接收多个第一刷新指令并对应进行多次第一刷新操作，当第一刷新操作的次数小于m时输出第一时钟信号，以及，当第一刷新操作的次数等于m时输出第二时钟信号，m为大于或等于1的整数。地址产生器耦接刷新控制电路，用于预存第一地址，并接收第一时钟信号或第二时钟信号，在每一次第一刷新操作期间响应于第一时钟信号输出待刷新地址，以及响应于第二时钟信号改变第一地址。待刷新地址包括第一地址或第二地址，第二地址的最低位与第一地址的最低位相反。如此，在进行第一刷新操作的过程中，地址产生器响应于第一时钟信号，既输出包括第一地址或第二地址的待刷新地址，又维持第一地址不改变；而在第一刷新操作次数等于m后，地址产生器响应于第二时钟信号，再改变第一地址。这样，既保证了刷新操作不遗漏地进行，又维持了地址的完整性。
附图说明
图1是本公开实施例提供的刷新地址产生电路的结构示意图一；
图2是本公开实施例提供的刷新地址产生电路的信号示意图一；
图3是本公开实施例提供的刷新地址产生电路的结构示意图二；
图4是本公开实施例提供的刷新地址产生电路的信号示意图二；
图5是本公开实施例提供的刷新地址产生电路的信号示意图三；
图6是本公开实施例提供的刷新地址产生电路的结构示意图三；
图7是本公开实施例提供的刷新地址产生电路的结构示意图四；
图8是本公开实施例提供的刷新地址产生电路的结构示意图五；
图9是本公开实施例提供的刷新地址产生电路的信号示意图四；
图10是本公开实施例提供的刷新地址产生电路的结构示意图六；
图11是本公开实施例提供的刷新地址产生电路的结构示意图七；
图12是本公开实施例提供的刷新地址产生电路的信号示意图五；
图13是本公开实施例提供的刷新地址产生电路的结构示意图八；
图14是本公开实施例提供的刷新地址产生电路的信号示意图六；
图15是本公开实施例提供的刷新地址产生电路的信号示意图七；
图16是本公开实施例提供的刷新地址产生电路的结构示意图九；
图17是本公开实施例提供的刷新地址产生电路的结构示意图十；
图18是本公开实施例提供的刷新地址产生电路的信号示意图八；
图19是本公开实施例提供的刷新地址产生电路的结构示意图十一；
图20是本公开实施例提供的刷新地址产生电路的信号示意图九；
图21是本公开实施例提供的刷新地址产生电路的结构示意图十二；
图22是本公开实施例提供的刷新地址产生电路的信号示意图十；
图23是本公开实施例提供的刷新地址产生电路的结构示意图十三；
图24是本公开实施例提供的刷新地址产生电路的结构示意图十四；
图25是本公开实施例提供的刷新地址产生电路的信号示意图十一；
图26是本公开实施例提供的刷新地址产生电路的结构示意图十五；
图27是本公开实施例提供的刷新地址产生电路的信号示意图十二；
图28是本公开实施例提供的刷新地址产生电路的信号示意图十三；
图29是本公开实施例提供的刷新地址产生电路的结构示意图十六；
图30是本公开实施例提供的刷新地址产生电路的信号示意图十四；
图31是本公开实施例提供的刷新地址产生电路的信号示意图十五；
图32是本公开实施例提供的刷新地址产生电路的结构示意图十七；
图33是本公开实施例提供的刷新地址产生电路的信号示意图十六；
图34是本公开实施例提供的刷新地址产生电路的信号示意图十七；
图35是本公开实施例提供的刷新地址产生电路的结构示意图十八。
具体实施方式
为了使本公开的目的、技术方案和优点更加清楚，下面结合附图和实施例对本公开的技术方案进一步详细阐述，所描述的实施例不应视为对本公开的限制，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其它实施例，都属于本公开保护的范围。
在以下的描述中，涉及到“一些实施例”，其描述了所有可能实施例的子集，但是可以理解，“一些实施例”可以是所有可能实施例的相同子集或不同子集，并且可以在不冲突的情况下相互结合。
如果申请文件中出现“第一/第二”的类似描述则增加以下的说明，在以下的描述中，所涉及的术语“第一/第二/第三”仅仅是区别类似的对象，不代表针对对象的特定排序，可以理解地，“第一/第二/第三”在允许的情况下可以互换特定的顺序或先后次序，以使这里描述的本公开实施例能够以除了在这里图示或描述的以外的顺序实施。
除非另有定义，本文所使用的所有的技术和科学术语与属于本公开的技术领域的技术人员通常理解的含义相同。本文中所使用的术语只是为了描述本公开实施例的目的，不是旨在限制本公开。
双倍速率同步动态随机存储器(Double Data Rate Synchronous Dynamic Random Access Memory，DDR SDRAM)常用于电子设备的内存。在DDR4SDRAM或者之前的DDR SDRAM中，刷新操作是所有Bank一起进行的，所有的Bank在同一时间的刷新的地址是相同的，即All Bank Refresh。而在DDR5SDRAM中新加入了Same Bank Refresh。也就是说，在Same Bank Refresh的模式下，位于同一个Bank Group中的不同Bank无法同时进行刷新，这样，会带来地址产生与保存的问题。
图1是本公开实施例提供的一种刷新地址产生电路的结构示意图，如图1所示，本公开实施例提供了一种刷新地址产生电路10，包括：刷新控制电路101和地址产生器102。其中：
刷新控制电路101，用于依次接收多个第一刷新指令SB CMD<0:m-1>并对应进行多次第一刷新操作，当第一刷新操作的次数小于m时输出第一时钟信号，以及，当第一刷新操作的次数等于m时输出第二时钟信号，m为大于或等于1的整数；
地址产生器102，耦接刷新控制电路，用于预存第一地址，并接收第一时钟信号或第二时钟信号，在每一次第一刷新操作期间响应于第一时钟信号输出待刷新地址Address，以及，响应于第二时钟信号改变第一地址；待刷新地址Address包括第一地址或第二地址，第二地址的最低位与第一地址的最低位相反。
需要说明的是，在本公开实施例中，耦接的方式包括了：直接电连接，以及，通过其他电元件(如电阻、延时器或反相器等)电连接。后文中出现的“耦接”均包括了这些方式，后文不再赘述。
本公开实施例中，刷新控制电路101可以依次接收多个第一刷新指令SB CMD<0:m-1>，这里，SB CMD<0:m-1>表示m个第一刷新指令SB CMD<0>～SB CMD<m-1>。其中，每个第一刷新指令SB CMD对应每个Bank Group中的一个Bank，每个第一刷新指令SB CMD会触发每个Bank Group中对应的Bank进行一次第一刷新操作(即Same Bank Refresh)。相应的，依次接收的多个第一刷新指令SB CMD<0:m-1>会依次触发每个Bank Group中对应的Bank分别进行一次第一刷新操作，即依次进行多次第一刷新操作。
本公开实施例中，Bank Group中包括了m个Bank，Bank的数量m按照芯片设计标准进行设定。每个Bank包括多行存储单元，待刷新地址Address为Bank中存储单元的行地址。在刷新控制电路101进行第一刷新操作的过程中，地址产生器102在第一刷新操作期间输出待刷新地址Address，该第一刷新指令SB CMD对应的Bank中待刷新地址Address所在的存储单元被刷新。
本公开实施例中，刷新控制电路101可以输出SameBank刷新时钟信号SB CBR CLK，SameBank刷新时钟信号SB CBR CLK包括了第一时钟信号和第二时钟信号。若第一刷新操作的次数小于m，则表征Bank Group中还有未对待刷新地址Adress所在的存储单元进行第一刷新操作的Bank，此时，刷新控制电路101输出第一时钟信号；若第一刷新操作的次数等于m，则表征Bank Group中的所有Bank中待刷新地址Address所在的存储单元均完成了第一刷新操作，此时，刷新控制电路101输出第二时钟信号。
如图2所示，以m＝4为例，SB CMD<0>、SB CMD<1>、SBCMD<2>和SB CMD<3>均为刷新控制电路依次收到的第一刷新指令，其分别对应同一个Bank Group中的4个Bank，即Bank0、Bank1、Bank2和Bank3。相应的，SB CMD<0>、SB CMD<1>、SB CMD<2>和SB CMD<3>中的脉冲，可以分别依次触发刷新控制电路101进行第一刷新操作。SameBank刷新时钟信号SB CBR CLK则包括了第一时钟信号和第二时钟信号，第二时钟信号为脉冲，第一时钟信号则保持低电平。
本公开实施例中，地址产生器102中预存了第一地址，在接收到第一时钟信号时，在每一次第一刷新操作期间会响应于第一时钟信号输出待刷新地址Address，其中，待刷新地址Address包括第一地址或第二地址，第二地址的最低位与第一地址的最低位相反。由于地址为二进制码，因此，最低位相反的第二地址与第一地址是相邻的两个地址，若第一地址为n，则第二地址为n+1或n-1；也就是说，当第一地址n的最低位为0时，第二地址将n的最低位取反后为1，第二地址为n+1；当第一地址n的最低位为1时，第二地址将n的最低位取反后为0，第二地址为n-1。地址产生器102在接收到第二时钟信号时，会响应于第二时钟信号改变其预存的第一地址，即下一次进行第一刷新操作时，地址产生器102中预存了改变后的第一地址。地址产生器102可以采用累加的方式改变第一地址，累加的值则可以由第二时钟信号进行控制。
如图2所示，待刷新地址Address包括了第一地址和第二地址，第一地址为n，第二地址为n+1或n-1。在SameBank刷新时钟信号SB CBR CLK为第一时钟信号时，地址产生器102输出待刷新地址Address为先后输出的第一地址和第二地址，其中，每组第一地址和第二地址在第一刷新指令SB CMD<0>、SB CMD<1>、SB CMD<2>和SB CMD<3>依次触发刷新控制电路101进行第一刷新操作的期间输出。也就是说，第一刷新指令SB CMD<0>触发刷新控制电路101进行第1次第一刷新操作时，地址产生器102输出待刷新地址Address，该待刷新地址Address包括第一地址n以及后续紧邻的第二地址n+1或n-1，即刷新控制器会根据待刷新地址Address对Bank0的对应的存储单元进行刷新；同样的，第二个第一刷新指令SB CMD<1>触发刷新控制电路101进行第2次第一刷新操作时，地址产生器102输出相同的待刷新地址Address，即第一地址n以及后续紧邻的第二地址n+1或n-1，刷新控制器会根据待刷新地址Address对Bank1中对应的存储单元进行刷新；以此类推，直到完成对Bank3中的对应的存储单元进行刷新。这样，Bank Group中的所有Bank(即Bank0、Bank1、Bank2和Bank3)中第一地址n以及第二地址n+1或n-1对应的存储单元均完成了刷新，即Bank Group中的所有Bank完成了对两个相邻地址的刷新。
继续参考图2，地址输出信号Addr Counter Output表征了地址产生器102所存储的第一地址。在刷新控制电路101进行第一刷新操作的次数小于m时，地址产生器102中所存储的第一地址n维持不变，地址输出信号Addr Counter Output持续为第一地址n；当Bank Group中的所有Bank中两个相邻地址对应的存储单元完成刷新后，即刷新控制电路101进行第一刷新操作的次数等于m时，地址产生器102响应于第二时钟信号改变第一地址n，其中，第二时钟信号包括了两个脉冲，在这两个脉冲的触发下，地址产生器102对第一地址n两次累加1，地址输出信号Addr Counter Output变为n+2，从而与刷新地址的进度相匹配；而后进行的m次第一刷新操作中，地址产生器102以变为n+2的第一地址为基础，继续输出待刷新地址Adress，以对Bank Group中各Bank的下两个相邻地址对应的存储单元完成刷新，以此类推，可以对Bank Group中各Bank的所有地址对应的存储单元依次完成刷新。
可以理解的是，在进行一次第一刷新操作的过程中，地址产生器102响应于第一时钟信号，输出包括第一地址或第二地址的待刷新地址Adress的同时，又维持第一地址不改变；而在第一刷新操作次数达到预设数量值m后，地址产生器102响应于第二时钟信号，改变第一地址，这样，既保证了刷新操作不遗漏地进行，又维持了地址的完整性。
图3为图1示出的刷新控制电路101的一种可选的结构示意图，图4和图5为对应于图3的信号示意图。
需要说明的是，图4示出了刷新控制电路101依次接收多个第一刷新指令SB CMD并进行第一刷新操作情况下的信号时序，其中，以第一刷新指令SB CMD的预设数量值m等于4为例。图5示出了刷新控制电路101接收第二刷新指令AB CMD并进行第二刷新操作情况下的信号时序。
另外，在图4和图5中，除第一刷新指令SB CMD、计数信号Bank Counter、计数复位信号Bank Counter Reset和SameBank刷新时钟信号SB CBR CLK之外，所有信号均示出了4个周期的波形，其中，每个周期的波形中若包括两个有效脉冲，则时序靠前的有效脉冲为第一脉冲，时序靠后的有效脉冲为第二脉冲。后续附图中的信号波形，也按照类似规则予以划分，后文不再赘述。
在本公开的一些实施例中，如图3和图4所示，刷新控制电路101包括：刷新窗口信号生成电路201和时钟脉冲生成电路202。
刷新窗口信号生成电路201用于接收多个第一刷新指令SB CMD(即图3示出的SB CMD<0>至SB CMD<m-1>)和刷新窗口复位信号Refresh Window Reset，根据多个第一刷新指令SB CMD和刷新窗口复位信号Refresh Window Reset生成刷新窗口信号Refresh Window。其中，参考图4，刷新窗口信号Refresh Window的脉冲持续时间为刷新控制电路101执行一次刷新操作的窗口时间，刷新窗口复位信号Refresh Window Reset用于在一次刷新操作结束后对刷新窗口信号生成电路201进行复位。这里，刷新控制电路101执行的刷新操作为第一刷新操作，即对第一刷新指令SB CMD对应的Bank执行第一刷新操作。
时钟脉冲生成电路202耦接刷新窗口信号生成电路201，用于接收刷新窗口信号Refresh Window和第一刷新指令SB CMD，在时钟脉冲生成电路202接收的第一刷新指令SB CMD的数量小于或等于m且第m次第一刷新操作结束前，生成第一时钟信号，或者，在第m次第一刷新操作结束后，生成第二时钟信号。参考图4，SameBank刷新时钟信号包括第一时钟信号和第二时钟信号，即第一时钟信号和第二时钟信号分别为SameBank刷新时钟信号不同时段的值。
在本公开的一些实施例中，如图3和图4所示，时钟脉冲生成电路202包括：计数电路203、计数复位信号生成电路204和第一脉冲生成子电路205。
计数电路203用于接收第一刷新指令SB CMD和计数复位信号Bank Counter Reset，对第一刷新指令SB CMD进行计数，并输出计数信号Bank Counter，以及，根据计数复位信号Bank Counter Reset进行复位。
计数复位信号生成电路204耦接计数电路203和刷新窗口信号生成电路201，用于在第m次第一刷新操作结束后，生成计数复位信号Bank Counter Reset。
第一脉冲生成子电路205耦接计数复位信号生成电路204，用于在第一刷新指令SB CMD小于m个时，根据计数信号BankCounter生成第一时钟信号，或者，在第一刷新指令SB CMD等于m个时根据计数复位信号Bank Counter Reset生成第二时钟信号。
在本公开的一些实施例中，如图3和图4所示，刷新窗口信号生成电路201包括：多个刷新窗口子信号生成电路206和刷新窗口子信号处理电路207。
多个刷新窗口子信号生成电路206用于接收刷新窗口复位信号Refresh Window Reset且分别依次对应接收多个第一刷新指令SB CMD，根据多个第一刷新指令SB CMD和刷新窗口复位信号Refresh Window Reset依次输出多个刷新窗口子信号ReW(即图3示出的ReW<0>至ReW<m-1>)。
刷新窗口子信号处理电路207耦接多个刷新窗口子信号生成电路206，用于依次接收多个刷新窗口子信号ReW，对刷新窗口子信号ReW进行逻辑运算，输出刷新窗口信号Refresh Window。
在本公开的一些实施例中，如图3和图5所示，刷新控制电路101还用于接收第二刷新指令AB CMD并进行第二刷新操作。
其中，多个刷新窗口子信号生成电路206还用于同时接收第二刷新指令AB CMD和刷新窗口复位信号Refresh Window Reset，根据第二刷新指令AB CMD和刷新窗口复位信号Refresh Window Reset一一对应生成相同的多个刷新窗口子信号ReW。
刷新窗口子信号处理电路207还用于接收多个刷新窗口子信号ReW，并将刷新窗口子信号ReW进行逻辑运算，输出刷新窗口信号Refresh Window。
需要说明的是，第二刷新操作是对Bank Group中的所有Bank同时进行的，即All Bank Refresh。在刷新控制电路101接收第二刷新指令AB CMD并进行第二刷新操作情况下，第一刷新指令SB CMD不包括有效的脉冲而保持低电平，即第一刷新指令SB CMD无效，进而，计数信号Bank Counter也保持低电平，计数刷新信号Bank Counter Reset也不产生有效的脉冲而保持低电平。
相应的，在刷新控制电路101依次接收多个第一刷新指令SB CMD并进行第一刷新操作情况下，第二刷新指令AB CMD不包括有效的脉冲而保持低电平，即第二刷新指令SB CMD无效。
本公开实施例中，多个刷新窗口子信号生成电路206在接收多个第一刷新指令SB CMD时，由于多个第一刷新指令SB CMD各不相同，则生成的多个刷新窗口子信号ReW各不相同。而多个刷新窗口子信号生成电路206在接收第二刷新指令AB CMD时，其可以生成多个相同的刷新窗口子信号ReW。
可以理解的是，刷新控制电路101可以根据需要依次接收多个第一刷新指令SB CMD并进行第一刷新操作情况，或者，接收第二刷新指令AB CMD并进行第二刷新操作。也就是说，采用一套刷新控制电路101便可以灵活进行两种刷新操作，这样，提高了电路的兼容性。
在本公开的一些实施例中，如图3所示，刷新控制电路101还包括：第二脉冲生成子电路208、内部刷新窗口信号生成电路209、地址命令信号生成电路210和刷新窗口复位信号生成电路211。
本公开实施例中，参考图3、图4和图5，第二脉冲生成子电路208耦接刷新窗口子信号处理电路207，用于接收刷新窗口信号Refresh Window和地址命令信号Addr CMD，在刷新控制电路101开始进行第一刷新操作或第二刷新操作时生成第三时钟信号AB CBR CLK的第一脉冲，并根据地址命令信号Addr CMD的第一脉冲输出第三时钟信号AB CBR CLK的第二脉冲，从而输出第三时钟信号AB CBR CLK。
参考图4，在刷新控制电路101依次接收多个第一刷新指令SB CMD并进行第一刷新操作情况下，第三时钟信号AB CBR CLK的第一脉冲对齐于多个第一刷新指令SB CMD<0>～SB CMD<3>的 有效脉冲，即第三时钟信号AB CBR CLK的第一脉冲在刷新控制电路101开始进行第一刷新操作时被生成；第三时钟信号AB CBR CLK的第二脉冲对齐于地址命令信号Addr CMD的第一脉冲，即第三时钟信号AB CBR CLK的第二脉冲是根据地址命令信号Addr CMD的第一脉冲而生成的。
参考图5，在刷新控制电路101接收第二刷新指令AB CMD并进行第二刷新操作情况下，第三时钟信号AB CBR CLK的第一脉冲对齐于第二刷新指令AB CMD的有效脉冲，即第三时钟信号AB CBR CLK的第一脉冲在刷新控制电路101开始进行第二刷新操作时被生成；第三时钟信号AB CBR CLK的第二脉冲对齐于地址命令信号Addr CMD的第一脉冲，即第三时钟信号AB CBR CLK的第二脉冲是根据地址命令信号Addr CMD的第一脉冲而生成的。
本公开实施例中，参考图3、图4和图5，内部刷新窗口信号生成电路209接收第三时钟信号AB CBR CLK，用于根据第三时钟信号AB CBR CLK生成内部刷新窗口信号Inner ACT Window；其中，内部刷新窗口信号Inner ACT Window的第一脉冲在第三时钟信号AB CBR CLK的第一脉冲之后产生，且在第三时钟信号AB CBR CLK的第二脉冲产生之前结束；内部刷新窗口信号Inner ACT Window的第二脉冲在第三时钟信号AB CBR CLK的第二脉冲之后产生，且在刷新窗口信号Refresh Window的脉冲结束之前结束。需要说明的是，存储器中的刷新控制器会接收内部刷新窗口信号Inner ACT Window和待刷新地址Adress并根据内部刷新窗口信号Inner ACT Window对存储单元进行刷新，因此内部刷新窗口信号Inner ACT Window脉冲的持续时间为对存储单元进行刷新的时间。
本公开实施例中，参考图3、图4和图5，地址命令信号生成电路210用于根据内部刷新窗口信号Inner ACT Window的下降沿生成地址命令信号Addr CMD的第一脉冲和第二脉冲；其中，地址命令信号Addr CMD的第一脉冲用于生成内部刷新窗口信号Inner ACT Window的第二脉冲以及第三时钟信号AB CBR CLK的第二脉冲。内部刷新窗口信号Inner ACT Window的一个下降沿表征一个地址的刷新结束，从而产生地址命令信号Addr CMD去控制产生下一个地址。
参考图4和图5，内部刷新窗口信号Inner ACT Window的有效脉冲可以被压缩和移位，从而得到内部预命令信号Inner PRE CMD的有效脉冲，也就是说，首先根据内部刷新窗口信号Inner ACT Window的下降沿得到内部预命令信号Inner PRE CMD的下降沿；而后，地址命令信号生成电路210可以根据内部预命令信号Inner PRE CMD的下降沿生成地址命令信号Addr CMD的第一脉冲和第二脉冲。
本公开实施例中，参考图3、图4和图5，刷新窗口复位信号生成电路211接收内部刷新窗口信号Inner ACT Window，用于根据内部刷新窗口信号Inner ACT Window的第二脉冲的下降沿生成刷新窗口复位信号Refresh Window Reset的脉冲。
在本公开的一些实施例中，如图3所示，刷新控制电路101还包括：信号选择电路212。
本公开实施例中，参考图3、4和5，信号选择电路212耦接计数电路203、第一脉冲生成子电路205和第二脉冲生成子电路208，用于接收计数信号Bank Counter、第一时钟信号、第二时钟信号(第一时钟信号和第二时钟信号即SameBank刷新时钟信号SB CBR CLK)和第三时钟信号AB CBR CLK，在刷新控制电路101进行第一刷新操作时，根据计数信号Bank Counter输出第一时钟信号或第二时钟信号，或者，在刷新控制电路101进行第二刷新操作时，根据计数信号Bank Counter输出第三时钟信号AB CBR CLK。
参考图3和图4，在刷新控制电路101进行第一刷新操作的情况下，若任一计数信号Bank Counter为高电平，则信号选择电路212输出第一时钟信号，即输出SameBank刷新时钟信号SB CBR CLK为低电平，若所有计数信号Bank Counter均跳转为低电平，则信号选择电路212输出第二时钟信号，即输出SameBank刷新时钟信号SB CBR CLK中两个连续的有效脉冲。
参考图3和图5，在刷新控制电路101进行第二刷新操作的情况下，所有计数信号Bank Counter均保持低电平(图5未示出)，则信号选择电路212输出第三时钟信号AB CBR CLK中的有效脉冲。
在本公开的一些实施例中，如图3所示，刷新控制电路101还包括：地址标志信号生成电路213。
本公开实施例中，参考图3、图4和图5，地址标志信号生成电路213耦接地址命令信号生成电路210和刷新窗口子信号处理电路207，用于接收地址命令信号Addr CMD和刷新窗口信号Refresh Window，根据地址命令信号Addr CMD的第一个上升沿生成地址标志信号Addr Flag的上升沿，根据刷新窗口信号Refresh Window的下降沿生成地址标志信号Addr Flag的下降沿。
在本公开的一些实施例中，如图6所示，地址产生器102包括：地址计数器301和地址处理电路302。
地址计数器301耦接信号选择电路212，用于预存第一地址，并从信号选择电路212接收SameBank刷新时钟信号SB CBR CLK或第三时钟信号AB CBR CLK(图6中未示出)。地址计数器301可以根据SameBank刷新时钟信号SB CBR CLK中的第二时钟信号改变第一地址为第三地址，或者，根据第三时钟信号AB CBR CLK改变第一地址并输出第四地址和第五地址。
地址处理电路302耦接地址计数器301和刷新窗口子信号生成电路206，用于在刷新控制电路101进行第一刷新操作时接收地址标志信号Addr Flag，并获取第一地址，在地址标志信号Addr Flag的上升沿到来前输出第一地址，或者，在地址标志信号Addr Flag上升沿到来后输出第二地址。地址处理电路302还用于在刷新控制电路101进行第二刷新操作时，依次获取第四地址和第五地址，并根据多个刷新窗口子信号ReW依次输出第四地址和第五地址。
本公开实施例中，在刷新控制电路101进行第一刷新操作的情况下，第一地址为预存的地址，第二地址则是将第一地址的最低位取反后得到的，即第一地址和第二地址为连续的两个地址，因此，第三地址在第一地址的基础上累加了数值2，避免对相同的地址重复进行第一刷新操作。这样，在所有的Bank完成了对第一地址和第二地址的第一刷新操作后，第一地址被累加数值2变为第三地址，刷新控制电路101可以将第三地址作为预存的地址，来进行新一轮的第一刷新操作，从而保证了第一刷新操作不遗漏地进行。
本公开实施例中，在刷新控制电路101进行第二刷新操作的情况下，第一地址为预存的地址，第四地址在第一地址的基础上累加了数值1，第五地址则在第四地址的基础上累加了数值1，也就是说，第一地址、第四地址和第五地址为依次连续的三个地址。这样，刷新控制电路101可以按照地址顺序对所有Bank的地址依次进行第二刷新操作，从而保证了第二刷新操作不遗漏地进行。
本公开实施例中，结合图4和图6，在信号选择电路212输出第二时钟信号(即SB CBR CLK中的两个有效脉冲)到地址计数器301的情况下，地址计数器301可以根据第二时钟信号的两个有效脉冲，依次在第一地址的基础上累加数值2，从而得到第三地址。在信号选择电路212输出第三时钟信号AB CBR CLK到地址计数器301的情况下，地址计数器301可以根据第三时钟信号AB CBR CLK的第一脉冲在第一地址的基础上累加数值1，得到第四地址，而后，地址计数器301可以根据第三时钟信号AB CBR CLK的第二脉冲在第四地址的基础上累加数值1，得到第五地址。
在本公开的一些实施例中，如图7所示，地址处理电路302包括：控制信号生成电路303和地址选择电路304。
控制信号生成电路303耦接刷新窗口子信号生成电路206和地址标志信号生成电路213，用于接收多个刷新窗口子信号ReW和地址标志信号Addr Flag，根据多个刷新窗口子信号ReW和地址标志信号Addr Flag生成地址控制信号Addr Ctrl。
地址选择电路304耦接地址计数器301和控制信号生成电路303，用于在刷新控制电路101接收第一刷新指令SB CMD时，根据地址控制信号Addr Ctrl输出第一地址，或者，根据地址控制信号Addr Ctrl对第一地址进行取反，得到并输出第二地址。地址选择电路304还用于在刷新控制电路101接收第二刷新指令AB CMD时，响应于地址控制信号Addr Ctrl，依次输出第四地址和第五地址。
在本公开的一些实施例中，如图8所示，计数电路203包括：多个第一反相器D1、多个第一锁存器L1和第二反相器D2。多个第一反相器D1的输入端依次接收多个第一刷新指令SB CMD。第二反相器D2的输入端接收计数复位信号Bank Counter Reset。多个第一锁存器L1的置位端依次对应连接多个第一反相器D1的输出端，多个第一锁存器L1的复位端均连接第二反相器D2的输出端，多个第一锁存器L1依次对应输出多个计数信号Bank Counter。
本公开实施例中，图9为m＝4时的信号时序图，结合图8和图9，每个第一刷新指令SB CMD中的有效脉冲可以触发对应的计数信号Bank Counter由低电平跳转为高电平，如第一刷新指令SB CMD<0>中的脉冲可以触发指令计数信号Bank Counter<0>由低电平变为高电平，同样的，第一刷新指令SB CMD<1>、SB CMD<2>和SB CMD<3>中的脉冲可以分别触发指令计数信号Bank Counter<1>、Bank Counter<2>和Bank Counter<3>由低电平变为高电平。而计数复位信号Bank Counter Reset中的有效脉冲可以触发所有的计数信号Bank Counter<0>～Bank Counter<3>由高电平跳转为低电平。计数复位信号Bank Counter Reset中的有效脉冲，在刷新控制电路完成第m次第一刷新操作后生成。
在本公开的一些实施例中，如图10所示，计数复位信号生成电路204包括：第一与门A1、第三反相器D3、第二与门A2、第一延时器H1、第四反相器D4和第三与门A3。第一与门A1的输入端接收多个计数信号Bank Counter。第三反相器D3的输入端接收刷新窗口信号Refresh Window。第二与门A2的输入端分别连接第一与门A1的输出端和第三反相器D3的输出端。第一延时器H1的输入端连接第二与门A2的输出端。第四反相器D4的输入端连接第一延时器H1的输出端。第三与门A3的输入端分别连接第二与门A2的输出端和第四反相器D4的输出端，第三与门A3输出计数复位信号Bank Counter Reset。
在本公开的一些实施例中，如图11所示，第一脉冲生成子电路205包括：第二延时器H2、第三延时器H3和第一或门B1。第二延时器H2的输入端接收计数复位信号Bank Counter Reset。第三延时器H3的输入端连接第二延时器H2的输出端。第一或门B1的输入端分别连接第二延时器H2的输出端和第三延时器H3的输出端，第一或门B1输出第一时钟信号或第二时钟信号，也就是说，第一或门B1输出SameBank刷新时钟信号SB CBR CLK。
本公开实施例中，图12为m＝4时的信号时序图，结合图10、图11和图12，在进行第一刷新操作的情况下，计数复位信号Bank Counter Reset中的脉冲基于计数信号Bank Counter<0>、Bank Counter<1>、Bank Counter<2>、Bank Counter<3>和刷新窗口信号Refresh Window而生成。计数复位信号Bank Counter Reset中的一个有效脉冲，经过第二延时器H2、第三延时器H3和第一或门B1后，生成SB CBR CLK中的两个有效脉冲。其中，第一延时器H1可以将接收到的信号延时0～2ns，第二延时器H2可以将接收到的信号延时1～3ns，第三延时器H3可以将接收到的信号延时4～6ns。
在本公开的一些实施例中，如图13所示，刷新窗口子信号包括：第一刷新窗口子信号ReW<i>或第二刷新窗口子信号ReW<AB>。每个刷新窗口子信号生成电路206包括：第一或非门E1和第二 锁存器L2。当刷新控制电路进行第一刷新操作时，第一或非门E1的第一输入端接收对应的第一刷新指令SB CMD<i>，或者，当刷新控制电路进行第二刷新操作时，第一或非门E1的第二输入端接收第二刷新指令AB CMD。第二锁存器L2的置位端连接第一或非门E1的输出端，第二锁存器L2的复位端接收刷新窗口复位信号Refresh Window Reset；当刷新控制电路进行第一刷新操作时，第二锁存器L2输出对应的第一刷新窗口子信号ReW<i>，或者，当刷新控制电路进行第二刷新操作时，第二锁存器输出对应的第二刷新窗口子信号ReW<AB>。这里，i大于等于0且小于等于m-1，第一刷新指令SB CMD<i>为多个第一刷新指令中的任一个，第一刷新窗口子信号ReW<i>对应于第一刷新指令SB CMD<i>。
本公开实施例中，图14为m＝4时的信号时序图，结合图13和图14，当刷新控制电路进行第一刷新操作时，第一刷新指令SB CMD<0>中的有效脉冲触发第一刷新窗口子信号ReW<0>由低电平跳转为高电平，刷新窗口复位信号Refresh Window Reset中的第一个有效脉冲触发第一刷新窗口子信号ReW<0>由高电平跳转为低电平，从而得到第一刷新窗口子信号ReW<0>的有效脉冲。类似的，第一刷新指令SB CMD<0>、SB CMD<1>和SB CMD<2>中的有效脉冲分别触发第一刷新窗口子信号ReW<0>、ReW<1>和ReW<2>由低电平跳转为高电平，刷新窗口复位信号Refresh Window Reset中的第二至四个有效脉冲分别触发第一刷新窗口子信号ReW<0>、ReW<1>和ReW<2>由高电平跳转为低电平，从而得到第一刷新窗口子信号ReW<0>、ReW<1>和ReW<2>的有效脉冲。
本公开实施例中，结合图13和图15，当刷新控制电路进行第二刷新操作时，第二刷新指令AB CMD中的有效脉冲触发第二刷新窗口子信号ReW<AB>由低电平跳转为高电平，刷新窗口复位信号Refresh Window Reset中的有效脉冲触发第二刷新窗口子信号ReW<AB>由高电平跳转为低电平，从而得到第二刷新窗口子信号ReW<AB>的有效脉冲。
在本公开的一些实施例中，结合图13和图16，刷新窗口子信号处理电路207包括：第二或门B2。当刷新控制电路进行第一刷新操作时，第二或门B2的输入端从多个刷新窗口子信号生成电路206分别接收多个第一刷新窗口子信号ReW<i>，或者，当刷新控制电路进行第二刷新操作时，第二或门的输入端从多个刷新窗口子信号生成电路206分别接收相同的多个第二刷新窗口子信号ReW<AB>。第二或门B2输出刷新窗口信号Refresh Window。
本公开实施例中，参考图16，刷新窗口信号生成电路201还包括第十三反相器D13。刷新窗口复位信号Refresh Window Reset通过第十三反相器D13后传输到多个刷新窗口子信号生成电路206。
本公开实施例中，参考图14和图16，当刷新控制电路进行第一刷新操作时，由于第一刷新窗口子信号ReW<0>～ReW<3>均为高电平有效，因此，第二或门B2输出的刷新窗口信号Refresh Window会包括第一刷新窗口子信号ReW<0>～ReW<3>中所有的有效脉冲。
本公开实施例中，参考图15和图16，当刷新控制电路进行第二刷新操作时，第二或门B2接收了相同的多个第二刷新窗口子信号ReW<AB>，第二或门B2输出的刷新窗口信号Refresh Window与第二刷新窗口子信号ReW<AB>波形相同。
在本公开的一些实施例中，如图17所示，第二脉冲生成子电路208包括：第四延时器H4、第五反相器D5、第四与门A4、第六反相器D6、第五与门A5、第二或非门E2和第七反相器D7。第四延时器H4的输入端接收刷新窗口信号Refresh Window。第五反相器D5的输入端连接第四延时器H4的输出端。第四与门A4的第一输入端接收刷新窗口信号Refresh Window，第四与门A4的第二输入端连接第五反相器D5的输出端。第六反相器D6的输入端接收地址标志信号Addr Flag。第五与门A5的第一输入端连接第六反相器D6的输出端，第五与门A5的第二输入端接收地址命令信号Addr CMD。第二或非门E2的输入端分别连接第四与门A4的输出端和第五与门A5的输出端。第七反相器D7的输入端连接第二或非门E2的输出端，第七反相器D7输出第三时钟信号AB CBR CLK。
本公开实施例中，参考图17和图18，第四延时器H4可以将接收到的刷新窗口信号Refresh Window延时1～3ns。进而，刷新窗口信号Refresh Window经过第四延时器H4、第五反相器D5和第四与门A4后，可以被转换为内部激活命令信号Inner ACT CMD。其中，内部激活命令信号Inner ACT CMD中的脉冲对应于刷新窗口信号Refresh Window的上升沿，该脉冲经过第二或非门E2和第七反相器D7后，构成了第三时钟信号AB CBR CLK的第一脉冲。第三时钟信号AB CBR CLK的第二脉冲则基于地址标志信号Addr Flag和地址命令信号Addr CMD而形成。
在本公开的一些实施例中，如图19所示，地址命令信号生成电路210包括：第八反相器D8、第五延时器H5和第六与门A6。第八反相器D8的输入端接收内部刷新窗口信号Inner ACT Window。第五延时器H5的输入端连接第八反相器D8的输入端，接收内部刷新窗口信号Inner ACT Window。第六与门A6的输入端分别连接第八反相器D8的输出端和第五延时器H5的输出端，第六与门A6输出地址命令信号Addr CMD。
本公开实施例中，第五延时器H5可以将接收到的内部刷新窗口信号Inner ACT Window延时0～2ns。结合图19和图20，经过第八反相器D8、第五延时器H5和第六与门A6，内部刷新窗口信号Inner ACT Window的第一脉冲可以被转换为地址命令信号Addr CMD的第一脉冲，内部刷新窗口信号Inner ACT Window的第二脉冲可以被转换为地址命令信号Addr CMD的第二脉冲。
在本公开的一些实施例中，如图19所示，内部刷新窗口信号生成电路209包括：第三锁存器L3。第三锁存器L3的置位端接收第三时钟信号AB CBR CLK，第三锁存器L3的复位端连接第八反 相器D8的输出端，第三锁存器L3输出内部刷新窗口信号Inner ACT Window。
在本公开的一些实施例中，如图21所示，刷新窗口复位信号生成电路211包括：第六延时器H6、第七与门A7和第七延时器H7。第六延时器H6的输入端接收地址标志信号Addr Flag。第七与门A7的第一输入端连接第六延时器H6的输出端，第七与门A7的第二输入端接收内部刷新窗口信号Inner ACT Window。第七延时器H7的输入端连接第七与门A7的输出端，第七延时器H7输出刷新窗口复位信号Refresh Window Reset。
本公开实施例中，第六延时器H6可以将接收到的地址标志信号Addr Flag延时0～2ns，第七延时器H7可以将接收到的信号延时4～6ns。结合图21和图22，经过第六延时器H6、第七与门A7和第七延时器H7，可以由内部刷新窗口信号Inner ACT Window和地址标志信号Addr Flag得到刷新窗口复位信号Refresh Window Reset。
在本公开的一些实施例中，如图23所示，信号选择电路212包括：第三或非门E3、第三或门B3和第八与门A8。第三或非门E3的输入端分别接收多个计数信号Bank Counter。第三或门B3的第一输入端接收第一时钟信号或第二时钟信号，即第三或门B3的第一输入端接收SameBank刷新时钟信号SB CBR CLK，第三或门B3的第二输入端接收第三时钟信号AB CBR CLK。第八与门A8的第一输入端连接第三或非门E3的输出端，第八与门A8的第二输入端连接第三或门B3的输出端，第八与门A8输出第一时钟信号、第二时钟信号或第三时钟信号AB CBR CLK。
本公开实施例中，结合图4和图23，在进行第一刷新操作的情况下，信号选择电路212所接收的各个信号的波形均如图4所示，这样，第三或门B3所输出的信号可以包括SameBank刷新时钟信号SB CBR CLK和第三时钟信号AB CBR CLK中所有的有效脉冲，然而，第三或非门E3输出的信号可以屏蔽掉第三时钟信号AB CBR CLK中的有效脉冲，从而，第八与门A8所输出的信号与SameBank刷新时钟信号SB CBR CLK波形相同，也就是说，在进行第一刷新操作的情况下，第八与门A8输出第一时钟信号或第二时钟信号。
在进行第二刷新操作的情况下，多个计数信号Bank Counter<0>～Bank Counter<3>以及SameBank刷新时钟信号SB CBR CLK均保持低电平(图4中未示出)，而第三时钟信号AB CBR CLK的波形仍如图4所示，这样，第八与门A8所输出的信号与第三时钟信号AB CBR CLK波形相同，也就是说，在进行第一刷新操作的情况下，第八与门A8输出第三时钟信号AB CBR CLK。
在本公开的一些实施例中，如图24所示，地址标志信号生成电路213包括：第九反相器D9和第四锁存器L4。第九反相器D9的输入端接收地址命令信号Addr CMD。第四锁存器L4的置位端连接第九反相器D9的输出端，第四锁存器L4的复位端接收刷新窗口信号Refresh Window，第四锁存器L4输出地址标志信号Addr Flag。
本公开实施例中，结合图24和图25，地址命令信号Addr CMD的第一脉冲触发地址标志信号Addr Flag由低电平跳转为高电平，刷新窗口信号Refresh Window的下降沿触发地址标志信号Addr Flag由高电平跳转为低电平，从而得到图25示出的地址标志信号Addr Flag的波形。
图26示出了刷新控制电路101的一种可选的实现方式，图26中包括了图8、图10、图11、图13、图16、图17、图19、图21、图23和图24中示出的电路元件。图27和图28示出了图26中部分信号的一种可选的波形图，其中，图27为刷新控制电路101进行第一刷新操作的情况下对应的信号示意图，图28为刷新控制电路101进行第二刷新操作的情况下对应的信号示意图。
图26以Bank Group中Bank的数量m＝4为例，从而，图26中包括了4个第一锁存器L1、4个第一反相器D1、以及4个刷新窗口子信号生成电路206。
结合图26和图27，在刷新控制电路101进行第一刷新操作的情况下，4个第一刷新指令SB CMD<0>、SB CMD<1>、SB CMD<2>和SB CMD<3>中包括了有效脉冲，而第二刷新指令AB CMD(图27中未示出)中则不包括有效脉冲，即第二刷新指令AB CMD保持低电平。从而，4个第一锁存器L1的置位端通过4个第一反相器D1分别接收4个第一刷新指令SB CMD<0>、SB CMD<1>、SB CMD<2>和SB CMD<3>，4个第一锁存器L1分别输出4个计数信号Bank Counter<0>、Bank Counter<1>、Bank Counter<2>和Bank Counter<3>到第三或非门E3的输入端以及第一与门A1的输入端。进而，信号选择电路212通过第八与门A8输出SameBank刷新时钟信号SB CBR CLK(即第一时钟信号或第二时钟信号)。同时，4个第二锁存器L2的置位端通过4个第一或非门E1分别接收4个第一刷新指令SB CMD<0>、SB CMD<1>、SB CMD<2>和SB CMD<3>，4个第二锁存器L2分别输出4个第一刷新窗口子信号ReW<0>、ReW<1>、ReW<2>和ReW<3>。
结合图7、图26和图27可知，在刷新控制电路101进行第一刷新操作的情况下，信号选择电路212输出SameBank刷新时钟信号SB CBR CLK(即第一时钟信号或第二时钟信号)到地址处理电路302，4个刷新窗口子信号生成电路206输出4个第一刷新窗口子信号ReW<0>、ReW<1>、ReW<2>和ReW<3>到地址处理电路302，地址标志信号生成电路213输出地址标志信号Addr Flag到地址处理电路302。
结合图26和图28，在刷新控制电路101进行第二刷新操作的情况下，4个第一刷新指令SB CMD<0>、SB CMD<1>、SB CMD<2>和SB CMD<3>(图28中未示出)中均不包括有效脉冲，即4个第一刷新指令SB CMD<0>、SB CMD<1>、SB CMD<2>和SB CMD<3>均保持低电平，而第二刷新指令AB CMD中则包括了有效脉冲。从而，4个第一锁存器L1输出的4个计数信号Bank  Counter<0>、Bank Counter<1>、Bank Counter<2>和Bank Counter<3>均保持低电平(图28中未示出)。进而，信号选择电路212通过第八与门A8输出第三时钟信号AB CBR CLK。同时，4个第二锁存器L2的置位端通过4个第一或非门E1均接收第二刷新指令AB CMD，4个第二锁存器L2均输出4个相同的第二刷新窗口子信号ReW<AB>。
结合图7、图26和图28可知，在刷新控制电路101进行第二刷新操作的情况下，信号选择电路212输出第三时钟信号AB CBR CLK到地址处理电路302，4个刷新窗口子信号生成电路206输出4个相同的第二刷新窗口子信号ReW<AB>到地址处理电路302，地址标志信号生成电路213输出地址标志信号Addr Flag到地址处理电路302。
在本公开的一些实施例中，如图29所示，控制信号生成电路303包括：第九与门A9、第十反相器D10和第四或非门E4。第九与门A9的输入端分别对应接收多个刷新窗口子信号ReW。第十反相器D10的输入端接收地址标志信号Addr Flag。第四或非门E4的第一输入端连接第九与门A9的输出端，第四或非门E4的第二输入端连接第十反相器D10的输出端，第四或非门E4输出地址控制信号Addr Ctrl。
本公开实施例中，图30以m＝4为例，结合图29和图30，在刷新控制电路进行第一刷新操作的情况下，第九与门A9的各输入端分别接收多个第一刷新窗口子信号ReW<0>、ReW<1>、ReW<2>和ReW<3>，则第九与门A9输出的信号ReW<And>恒为低电平，这样，地址控制信号Addr Ctrl与地址标志信号Addr Flag波形相同，也就是说，地址标志信号Addr Flag经过控制信号生成电路303后仍保持波形不变。
结合图29和图31，在刷新控制电路进行第二刷新操作的情况下，第九与门A9的各输入端均接收相同的第二刷新窗口子信号ReW<AB>，则第九与门A9输出的信号ReW<And>与第二刷新窗口子信号ReW<AB>波形相同，而信号ReW<And>的高电平区域覆盖了地址标志信号Addr Flag的高电平区域，这样，通过第四或非门E4，信号ReW<And>可以屏蔽地址标志信号Addr Flag的高电平区域，从而，地址控制信号Addr Ctrl恒为低电平，也就是说，地址标志信号Addr Flag经过控制信号生成电路303后被屏蔽。
需要说明的是，图30示出的多个第一刷新窗口子信号ReW<0>、ReW<1>、ReW<2>和ReW<3>与图14示出的多个第一刷新窗口子信号ReW<0>、ReW<1>、ReW<2>和ReW<3>波形相同，也就是说，图30中的多个第一刷新窗口子信号ReW<0>、ReW<1>、ReW<2>和ReW<3>可以按照图14的示例来得到。图31示出的第二刷新窗口子信号ReW<AB>与图15示出的第二刷新窗口子信号ReW<AB>波形相同，也就是说，图31中的第二刷新窗口子信号ReW<AB>可以按照图15的示例来得到。
在本公开的一些实施例中，如图32所示，地址选择电路304包括：同相输出模块305、反相输出模块306、第十一反相器D11和地址延时模块307。
同相输出模块305的输入端连接地址计数器301，同相输出模块305的第一控制端配置为接收地址控制信号Addr Ctrl，同相输出模块305的第二控制端配置为通过第十一反相器D11接收地址控制信号Addr Ctrl。同相输出模块305配置为在刷新控制电路接收第一刷新指令且地址标志信号Addr Flag为第一值时，响应于地址控制信号Addr Ctrl，获取并输出第一地址的最低位。
反相输出模块306的输入端连接地址计数器301，反相输出模块306的第一控制端配置为通过第十一反相器D11接收地址控制信号Addr Ctrl，反相输出模块306的第二控制端配置为接收地址控制信号Addr Ctrl。反相输出模块306配置为在刷新控制电路接收第一刷新指令且地址标志信号Addr Flag为第二值时，响应于地址控制信号Addr Ctrl，获取第一地址的最低位，将第一地址的最低位取反后输出。
地址延时模块307连接地址计数器301，配置为在刷新控制电路接收第一刷新指令时，获取第一地址的其他位，将第一地址的其他位延时后输出，其中，其他位为除最低位以外的地址位。
本公开实施例中，地址选择电路304从地址计数器301所接收的第一地址，被分为两部分传输，其中，第一地址的最低位被传输到同相输出模块305和反相输出模块306，第一地址中除最低位以外的其他位被传输到地址延时模块307。同相输出模块305和反相输出模块306均接收地址控制信号Addr Ctrl，同相输出模块305在地址控制信号Addr Ctrl控制下，输出第一地址的最低位，而反相输出模块306则在地址控制信号Addr Ctrl的控制下，将第一地址的最低位取反后输出。由于第一地址的最低位在经过同相输出模块305或反相输出模块306后，会在时序上有所延后，因此，第一地址的其他位需要经过地址延时模块307，以匹配时序。
需要说明的是，第一地址的地址位数目可以根据实际需要而设置，例如，第一地址Address<15:0>为16位地址，则第一地址Address<15:0>的最低位为第15位地址Address<15>，第一地址Address<15:0>中除最低位以外的地址位为第0位至第14位地址Address<14:0>。本公开对此不作限制。
本公开实施例中，参考图32和图33，在刷新控制电路接收第一刷新指令的情况下，地址计数器301接收到SameBank刷新时钟信号SB CBR CLK，即接收到第一时钟信号或第二时钟信号。
当地址计数器301接收到第一时钟信号时，由于第一时钟信号不包括有效脉冲，因此，不会触发地址计数器301改变第一地址。地址输出信号Addr Counter Output表征了地址计数器301所存储 的第一地址，参考图33，当地址计数器301接收到第一时钟信号时，第一地址维持n不变；而地址选择电路304输出的待刷新地址Address，则受控于地址控制信号Addr Ctrl，交替输出n和n+1，或者，交替输出n和n-1。这里，n+1或n-1为第二地址，第二地址的最低位与第一地址n的最低位相反。当第一地址n的最低位为0时，第二地址为n+1。当第一地址n的最低位为1时，第二地址为n-1。待刷新地址Address输出的每一组n和n+1，或者，n和n-1，都会用于Bank Group中对应的SameBank进行第一刷新操作，直至Bank Group中所有Bank完成第一刷新操作，即第一刷新操作的次数达到m(图33中以m＝4为例)，在这一过程中，地址计数器301所存储的第一地址一直维持n不变。
当第一刷新操作的次数达到m，即所有Bank均完成了本轮第一刷新操作后，地址计数器301接收到第二时钟信号，由于第二时钟信号包括了两个有效脉冲，因此，地址计数器301会在第一地址上累加2，即改变第一地址为第三地址。此时，Bank Group中所有Bank已经完成了上一轮第一刷新操作，在刷新控制电路接收到下一轮第一刷新指令后，可以按照第三地址进行下一轮第一刷新操作。
例如，当前的第一地址是0000，第一地址最低位翻转，变为第二地址0001，第二地址相对于第一地址加1，如此对各Bank进行第一刷新操作(Same Bank Refresh)。当所有bank完成本轮第一刷新操作后，地址产生器102受第二时钟信号中两个脉冲触发，对第一地址累加2，输出0010，再进行下一轮的第一刷新操作。又如，当前的第一地址是0001，第一地址最低位翻转，变为第二地址0000，第二地址相对于第一地址减1，当所有bank完成本轮第一刷新操作后，地址产生器102受第二时钟信号中两个脉冲触发，对第一地址累加2，输出0011，再进行下一轮的第一刷新操作。
需要说明的是，图33与图2中示出的第一时钟信号或第二时钟信号波形相同，也就是说，图33示出的第一时钟信号或第二时钟信号可以通过图2的示例来得到。
可以理解的是，在Bank Group中的SameBank进行第一刷新操作时，会对一组SameBank中两个相邻地址(即n和n+1，或者，n和n-1)进行第一刷新操作，且在这一过程中第一地址n维持不变。而当Bank Group中的所有Bank完成了对两个相邻地址的第一刷新操作后，即Bank Group中所有Bank完成了上一轮第一刷新操作后，第一地址累加2变为第三地址，可以按照第三地址进行下一轮第一刷新操作。这样，可以按照地址的顺序对各Bank中的地址进行第一刷新操作，保证了刷新地址的连续性，避免了遗漏地址而未进行第一刷新操作。
本公开实施例中，参考图32，同相输出模块305还配置为在刷新控制电路接收第二刷新指令时，响应于地址控制信号Addr Ctrl，获取并输出第四地址的最低位或第五地址的最低位。
地址延时模块307还配置为在刷新控制电路接收第二刷新指令时，获取第四地址的其他位或第五地址的其他位，将第四地址的其他位或第五地址的其他位延时后输出。
本公开实施例中，地址选择电路304从地址计数器301所接收的第四地址或第五地址，被分为两部分传输，其中，地址的最低位被传输到同相输出模块305和反相输出模块306，地址中除最低位以外的其他位被传输到延时模块307。同相输出模块305和反相输出模块306均接收地址控制信号Addr Ctrl，同相输出模块305在地址控制信号Addr Ctrl控制下，输出地址的最低位，而反相输出模块306则在地址控制信号Addr Ctrl的控制下，将地址的最低位取反后输出。由于地址的最低位在经过同相输出模块305或反相输出模块306后，会在时序上有所延后，因此，地址的其他位需要经过地址延时模块307，以匹配时序。
参考图32和图34，在刷新控制电路接收第二刷新指令的情况下，地址计数器301接收到第三时钟信号AB CBR CLK。第三时钟信号AB CBR CLK中的每个有效脉冲，均会触发地址计数器301在第一地址上累加1。地址输出信号Addr Counter Output表征了地址计数器301所存储的第一地址，参考图34，地址输出信号Addr Counter Output在第三时钟信号AB CBR CLK的触发下累加。其中，图34示出的第三时钟信号AB CBR CLK包含了四个周期，每两个有效脉冲为一个周期，从而，在第一个周期内，第一地址n被触发改变为第五地址n+2；在第二个周期内，n+2作为第一地址被触发改变为第五地址n+4，依次类推。
同时，地址控制信号Addr Ctrl保持低电平，从而，反相输出模块306不起作用，地址的最低位均通过同相输出模块305被输出，也就是说，用于第二刷新操作的待刷新地址Address与地址输出信号Addr Counter Output保持一致。这样，可以按照地址的顺序对所有Bank中的地址进行第二刷新操作，避免了遗漏地址而未进行第二刷新操作。
需要说明的是，图34与图5示出的第三时钟信号AB CBR CLK波形相同，也就是说，图34示出的第三时钟信号AB CBR CLK可以通过图5的示例来得到。
可以理解的是，在Bank Group中的所有Bank进行第二刷新操作时，地址产生器102根据第三时钟信号AB CBR CLK生成连续的待刷新地址Address，以使得所有Bank中的各地址依次完成第二刷新操作(即All Bank Refresh)。这样，可以按照地址的顺序对所有Bank中的地址进行第二刷新操作，保证了刷新地址的连续性，避免了遗漏地址而未进行第二刷新操作。同时，采用一套地址产生器102便可以灵活进行两种刷新操作，这样，提高了电路的兼容性。
在本公开的一些实施例中，如图35所示，同相输出模块305包括：第一PMOS管P1和第一NMOS管N1。反相输出模块306包括：第十二反相器D12、第二PMOS管P2和第二NMOS管N2。
第一PMOS管P1的栅极作为同相输出模块305的第一控制端，第一NMOS管N1的栅极作为同相输出模块305的第二控制端，第一PMOS管P1的源极连接第一NMOS管N1的漏极并作为同相输出模块305的输入端，第一PMOS管P1的漏极连接第一NMOS管N1的源极并作为同相输出模块305的输出端。第二PMOS管P2的栅极作为反相输出模块306的第一控制端，第二NMOS管N2的栅极作为反相输出模块306的第二控制端，第十二反相器D12的输入端作为反相输出模块306的输入端，第十二反相器D12的输出端连接第二PMOS管P2的源极和第二NMOS管N2的漏极，第二PMOS管P2的漏极连接第二NMOS管N2的源极并作为反相输出模块306的输出端。
本公开实施例中，第一PMOS管P1的源极连接第一NMOS管N1的漏极并作为同相输出模块305的输入端，从地址计数器301接收地址的最低位。若地址控制信号Addr Ctrl为低电平，则第一PMOS管P1和第一NMOS管N1为开启状态，地址的最低位由第一PMOS管P1的漏极和第一NMOS管N1的源极输出；若地址控制信号Addr Ctrl为高电平，则第一PMOS管P1和第一NMOS管N1为截止状态，第一PMOS管P1的漏极和第一NMOS管N1的源极没有输出信号。
第十二反相器D12的输入端作为反相输出模块306的输入端，从地址计数器301接收地址的最低位，地址的最低位经过第十二反相器D12后被取反。若地址控制信号Addr Ctrl为高电平，则第二PMOS管P2和第二NMOS管N2为开启状态，被取反后的地址的最低位由第二PMOS管P2的漏极和第二NMOS管N2的源极输出；若地址控制信号Addr Ctrl为低电平，则第二PMOS管P2和第二NMOS管N2为截止状态，第二PMOS管P2的漏极和第二NMOS管N2的源极没有输出信号。
需要说明的是，同相输出模块305也可以被配置为在地址控制信号Addr Ctrl为高电平时输出地址的最低位，反相输出模块306也可以被配置为在地址控制信号Addr Ctrl为低电平时将地址的最低位取反后输出，在此不做限制。
需要说明的是，在本公开中，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、物品或者装置不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、物品或者装置所固有的要素。在没有更多限制的情况下，由语句“包括一个……”限定的要素，并不排除在包括该要素的过程、方法、物品或者装置中还存在另外的相同要素。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。
工业实用性
本公开实施例提供了一种刷新地址产生电路，包括：刷新控制电路和地址产生器。其中，刷新控制电路依次接收多个第一刷新指令并对应进行多次第一刷新操作，当第一刷新操作的次数小于m时输出第一时钟信号，以及，当第一刷新操作的次数等于m时输出第二时钟信号，m为大于或等于1的整数。地址产生器耦接刷新控制电路，用于预存第一地址，并接收第一时钟信号或第二时钟信号，在每一次第一刷新操作期间响应于第一时钟信号输出待刷新地址，以及响应于第二时钟信号改变第一地址。待刷新地址包括第一地址或第二地址，第二地址的最低位与第一地址的最低位相反。如此，在进行第一刷新操作的过程中，地址产生器响应于第一时钟信号，既输出包括第一地址或第二地址的待刷新地址，又维持第一地址不改变；而在第一刷新操作次数等于m后，地址产生器响应于第二时钟信号，再改变第一地址。这样，既保证了刷新操作不遗漏地进行，又维持了地址的完整性。

Claims (25)

  1. 一种刷新地址产生电路，所述刷新地址产生电路包括：
    刷新控制电路，用于依次接收多个第一刷新指令并对应进行多次第一刷新操作，当所述第一刷新操作的次数小于m时输出第一时钟信号，以及，当所述第一刷新操作的次数等于m时输出第二时钟信号，m为大于或等于1的整数；
    地址产生器，耦接所述刷新控制电路，用于预存第一地址，并接收所述第一时钟信号或所述第二时钟信号，在每一次所述第一刷新操作期间响应于所述第一时钟信号输出待刷新地址，以及，响应于所述第二时钟信号改变所述第一地址；所述待刷新地址包括所述第一地址或第二地址，所述第二地址的最低位与所述第一地址的最低位相反。
  2. 根据权利要求1所述的电路，其中，所述刷新控制电路包括：
    刷新窗口信号生成电路，用于接收多个所述第一刷新指令和刷新窗口复位信号，根据多个所述第一刷新指令和所述刷新窗口复位信号生成刷新窗口信号；其中，所述刷新窗口信号的脉冲持续时间为所述刷新控制电路执行一次刷新操作的窗口时间，所述刷新窗口复位信号用于在一次刷新操作结束后对所述刷新窗口信号生成电路进行复位；
    时钟脉冲生成电路，耦接所述刷新窗口信号生成电路，用于接收刷新窗口信号和所述第一刷新指令，在所述时钟脉冲生成电路接收的所述第一刷新指令的数量小于或等于m且第m次所述第一刷新操作结束前，生成所述第一时钟信号，或者，在第m次所述第一刷新操作结束后，生成所述第二时钟信号。
  3. 根据权利要求2所述的电路，其中，所述时钟脉冲生成电路包括：
    计数电路，用于接收所述第一刷新指令和计数复位信号，对所述第一刷新指令进行计数，并输出计数信号，以及，根据所述计数复位信号进行复位；
    计数复位信号生成电路，耦接所述计数电路和所述刷新窗口信号生成电路，用于在第m次所述第一刷新操作结束后，生成所述计数复位信号；
    第一脉冲生成子电路，耦接所述计数复位信号生成电路，用于在所述第一刷新指令小于m个时，根据所述计数信号生成所述第一时钟信号，或者，在所述第一刷新指令等于m个时根据所述计数复位信号生成所述第二时钟信号。
  4. 根据权利要求2所述的电路，其中，所述刷新窗口信号生成电路包括：
    多个刷新窗口子信号生成电路，用于接收刷新窗口复位信号且分别依次对应接收多个所述第一刷新指令，根据多个所述第一刷新指令和所述刷新窗口复位信号依次输出多个刷新窗口子信号；
    刷新窗口子信号处理电路，耦接所述多个刷新窗口子信号生成电路，用于依次接收多个所述刷新窗口子信号，对所述刷新窗口子信号进行逻辑运算，输出所述刷新窗口信号。
  5. 根据权利要求4所述的电路，其中，所述刷新控制电路，还用于接收第二刷新指令并进行第二刷新操作；其中，
    多个所述刷新窗口子信号生成电路，还用于同时接收所述第二刷新指令和所述刷新窗口复位信号，根据所述第二刷新指令和所述刷新窗口复位信号一一对应生成相同的多个所述刷新窗口子信号；
    所述刷新窗口子信号处理电路，还用于接收多个所述刷新窗口子信号，并将所述刷新窗口子信号进行逻辑运算，输出所述刷新窗口信号。
  6. 根据权利要求4所述的电路，其中，所述刷新控制电路还包括：
    第二脉冲生成子电路，耦接所述刷新窗口信号生成电路，用于接收刷新窗口信号和地址命令信号，在所述刷新控制电路开始进行所述第一刷新操作或所述第二刷新操作时生成所述第三时钟信号的第一脉冲，并根据所述地址命令信号的第一脉冲输出所述第三时钟信号的第二脉冲，从而输出所述第三时钟信号；
    内部刷新窗口信号生成电路，接收所述第三时钟信号，用于根据所述第三时钟信号生成所述内部刷新窗口信号；其中，所述内部刷新窗口信号的第一脉冲在所述第三时钟信号的第一脉冲之后产生，且在所述第三时钟信号的第二脉冲产生之前结束；所述内部刷新窗口信号的第二脉冲在所述第三时钟信号的第二脉冲之后产生，且在所述刷新窗口信号的脉冲结束之前结束；
    地址命令信号生成电路，用于根据所述内部刷新窗口信号的下降沿生成所述地址命令信号的第一脉冲和第二脉冲；其中，所述地址命令信号的第一脉冲用于生成所述内部刷新窗口信号的第二脉冲以及所述第三时钟信号的第二脉冲；
    刷新窗口复位信号生成电路，接收所述内部刷新窗口信号，用于根据所述内部刷新窗口信号的第二脉冲的下降沿生成所述刷新窗口复位信号的脉冲。
  7. 根据权利要求6所述的电路，其中，所述刷新控制电路还包括：
    信号选择电路，耦接所述计数电路、所述第一脉冲生成子电路和所述第二脉冲生成子电路，用于接收所述计数信号、所述第一时钟信号、所述第二时钟信号和所述第三时钟信号，在所述刷新控制电路进行所述第一刷新操作时，根据所述计数信号输出所述第一时钟信号或所述第二时钟信号，或者，在所述刷新控制电路进行所述第二刷新操作时，根据计数信号输出所述第三时钟信号。
  8. 根据权利要求6所述的电路，其中，所述刷新控制电路还包括：
    地址标志信号生成电路，耦接所述地址命令信号生成电路和所述刷新窗口信号生成电路，用于接收所述地址命令信号和所述刷新窗口信号，根据所述地址命令信号的第一个上升沿生成地址标志信号的上升沿，根据所述刷新窗口信号的下降沿生成所述地址标志信号的下降沿。
  9. 根据权利要求7所述的电路，其中，所述地址产生器包括：
    地址计数器，耦接所述信号选择电路，用于预存所述第一地址，根据所述第二时钟信号改变所述第一地址为第三地址，或者，根据所述第三时钟信号改变所述第一地址并输出第四地址和第五地址；所述第一地址、所述第四地址和所述第五地址为依次连续的三个地址；
    地址处理电路，耦接所述地址计数器和所述刷新窗口子信号生成电路，用于在所述刷新控制电路进行所述第一刷新操作时接收所述地址标志信号，并获取所述第一地址，在所述地址标志信号的上升沿到来前输出所述第一地址，或者，在所述地址标志信号上升沿到来后输出所述第二地址；
    所述地址处理电路，还用于在所述刷新控制电路进行所述第二刷新操作时，依次获取所述第四地址和所述第五地址，并根据多个所述刷新窗口子信号依次输出所述第四地址和所述第五地址。
  10. 根据权利要求9所述的电路，其中，所述地址处理电路包括：
    控制信号生成电路，耦接所述刷新窗口子信号生成电路和所述地址标志信号生成电路，用于接收多个所述刷新窗口子信号和所述地址标志信号，根据多个所述刷新窗口子信号和所述地址标志信号生成地址控制信号；
    地址选择电路，耦接所述地址计数器和所述控制信号生成电路，用于在所述刷新控制电路接收所述第一刷新指令时，根据所述地址控制信号输出所述第一地址，或者，根据所述地址控制信号对所述第一地址进行取反，得到并输出所述第二地址；
    所述地址选择电路，还用于在所述刷新控制电路接收所述第二刷新指令时，响应于所述地址控制信号，依次输出所述第四地址和所述第五地址。
  11. 根据权利要求3所述的电路，其中，所述计数电路包括：
    多个第一反相器，多个所述第一反相器的输入端依次接收多个所述第一刷新指令；
    第二反相器，所述第二反相器的输入端接收所述计数复位信号；
    多个第一锁存器，多个所述第一锁存器的置位端依次对应连接多个所述第一反相器的输出端，多个所述第一锁存器的复位端均连接所述第二反相器的输出端，多个所述第一锁存器依次对应输出多个所述计数信号。
  12. 根据权利要求3所述的电路，其中，所述计数复位信号生成电路包括：
    第一与门，所述第一与门的输入端接收多个所述计数信号；
    第三反相器，所述第三反相器的输入端接收所述刷新窗口信号；
    第二与门，所述第二与门的输入端分别连接所述第一与门的输出端和所述第三反相器的输出端；
    第一延时器，所述第一延时器的输入端连接所述第二与门的输出端；
    第四反相器，所述第四反相器的输入端连接所述第一延时器的输出端；
    第三与门，所述第三与门的输入端分别连接所述第二与门的输出端和所述第四反相器的输出端，所述第三与门输出所述计数复位信号。
  13. 根据权利要求3所述的电路，其中，所述第一脉冲生成子电路包括：
    第二延时器，所述第二延时器的输入端接收所述计数复位信号；
    第三延时器，所述第三延时器的输入端连接所述第二延时器的输出端；
    第一或门，所述第一或门的输入端分别连接所述第二延时器的输出端和所述第三延时器的输出端，所述第一或门输出所述第一时钟信号或所述第二时钟信号。
  14. 根据权利要求5所述的电路，其中，所述刷新窗口子信号包括：第一刷新窗口子信号或第二刷新窗口子信号；每个所述刷新窗口子信号生成电路包括：
    第一或非门，当所述刷新控制电路进行所述第一刷新操作时，所述第一或非门的第一输入端接收对应的所述第一刷新指令，或者，当所述刷新控制电路进行所述第二刷新操作时，所述第一或非门的第二输入端接收所述第二刷新指令；
    第二锁存器，所述第二锁存器的置位端连接所述第一或非门的输出端，所述第二锁存器的复位端接收所述刷新窗口复位信号；当所述刷新控制电路进行所述第一刷新操作时，所述第二锁存器输出对应的所述第一刷新窗口子信号，或者，当所述刷新控制电路进行所述第二刷新操作时，所述第二锁存器输出对应的所述第二刷新窗口子信号。
  15. 根据权利要求14所述的电路，其中，所述刷新窗口子信号处理电路包括：
    第二或门，当所述刷新控制电路进行所述第一刷新操作时，所述第二或门的输入端分别接收多个所述第一刷新窗口子信号，或者，当所述刷新控制电路进行所述第二刷新操作时，所述第二或门的输入端分别接收相同的多个所述第二刷新窗口子信号；所述第二或门输出所述刷新窗口信号。
  16. 根据权利要求6所述的电路，其中，所述第二脉冲生成子电路包括：
    第四延时器，所述第四延时器的输入端接收所述刷新窗口信号；
    第五反相器，所述第五反相器的输入端连接所述第四延时器的输出端；
    第四与门，所述第四与门的第一输入端接收所述刷新窗口信号，所述第四与门的第二输入端连接所述第五反相器的输出端；
    第六反相器，所述第六反相器的输入端接收地址标志信号；
    第五与门，所述第五与门的第一输入端连接所述第六反相器的输出端，所述第五与门的第二输入端接收所述地址命令信号；
    第二或非门，所述第二或非门的输入端分别连接所述第四与门的输出端和所述第五与门的输出端；
    第七反相器，所述第七反相器的输入端连接所述第二或非门的输出端，所述第七反相器输出所述第三时钟信号。
  17. 根据权利要求6所述的电路，其中，所述地址命令信号生成电路包括：
    第八反相器，所述第八反相器的输入端接收所述内部刷新窗口信号；
    第五延时器，所述第五延时器的输入端连接所述第八反相器的输入端，接收所述内部刷新窗口信号；
    第六与门，所述第六与门的输入端分别连接所述第八反相器的输出端和所述第五延时器的输出端，所述第六与门输出所述地址命令信号。
  18. 根据权利要求17所述的电路，其中，所述内部刷新窗口信号生成电路包括：
    第三锁存器，所述第三锁存器的置位端接收所述第三时钟信号，所述第三锁存器的复位端连接所述第八反相器的输出端，所述第三锁存器输出所述内部刷新窗口信号。
  19. 根据权利要求6所述的电路，其中，所述刷新窗口复位信号生成电路包括：
    第六延时器，所述第六延时器的输入端接收地址标志信号；
    第七与门，所述第七与门的第一输入端连接所述第六延时器的输出端，所述第七与门的第二输入端接收所述内部刷新窗口信号；
    第七延时器，所述第七延时器的输入端连接所述第七与门的输出端，所述第七延时器输出所述刷新窗口复位信号。
  20. 根据权利要求7所述的电路，其中，所述信号选择电路包括：
    第三或非门，所述第三或非门的输入端分别接收多个所述计数信号；
    第三或门，所述第三或门的第一输入端接收所述第一时钟信号或所述第二时钟信号，所述第三或门的第二输入端接收所述第三时钟信号；
    第八与门，所述第八与门的第一输入端连接所述第三或非门的输出端，所述第八与门的第二输入端连接所述第三或门的输出端，所述第八与门输出所述第一时钟信号、所述第二时钟信号或所述第三时钟信号。
  21. 根据权利要求8所述的电路，其中，所述地址标志信号生成电路包括：
    第九反相器，所述第九反相器的输入端接收所述地址命令信号；
    第四锁存器，所述第四锁存器的置位端连接所述第九反相器的输出端，所述第四锁存器的复位端接收所述刷新窗口信号，所述第四锁存器输出所述地址标志信号。
  22. 根据权利要求10所述的电路，其中，所述控制信号生成电路包括：
    第九与门，所述第九与门的输入端分别对应接收多个所述刷新窗口子信号；
    第十反相器，所述第十反相器的输入端接收所述地址标志信号；
    第四或非门，所述第四或非门的第一输入端连接所述第九与门的输出端，所述第四或非门的第二输入端连接所述第十反相器的输出端，所述第四或非门输出所述地址控制信号。
  23. 根据权利要求10所述的电路，其中，所述地址选择电路包括：同相输出模块、反相输出模块、第十一反相器和地址延时模块；
    所述同相输出模块的输入端连接所述地址计数器；所述同相输出模块的第一控制端，配置为接收所述地址控制信号；所述同相输出模块的第二控制端，配置为通过所述第十一反相器接收所述地址控制信号；所述同相输出模块，配置为在所述刷新控制电路接收所述第一刷新指令且所述地址标志信号为第一值时，响应于所述地址控制信号，获取并输出所述第一地址的最低位；
    所述反相输出模块的输入端连接所述地址计数器；所述反相输出模块的第一控制端，配置为通过所述第十一反相器接收所述地址控制信号；所述反相输出模块的第二控制端，配置为接收所述地址控制信号；所述反相输出模块，配置为在所述刷新控制电路接收所述第一刷新指令且所述地址标志信号为第二值时，响应于所述地址控制信号，获取所述第一地址的最低位，将所述第一地址的最低位取反后输出；
    所述地址延时模块，连接所述地址计数器，配置为在所述刷新控制电路接收所述第一刷新指令时，获取所述第一地址的其他位，将所述第一地址的其他位延时后输出；所述其他位为除最低位以外的地址位。
  24. 根据权利要求23所述的电路，其中，
    所述同相输出模块，还配置为在所述刷新控制电路接收所述第二刷新指令时，响应于所述地址控制信号，获取并输出所述第四地址的最低位或所述第五地址的最低位；
    所述地址延时模块，还配置为在所述刷新控制电路接收所述第二刷新指令时，获取所述第四地址的其他位或所述第五地址的其他位，将所述第四地址的其他位或所述第五地址的其他位延时后输出。
  25. 根据权利要求23所述的电路，其中，所述同相输出模块包括：第一PMOS管和第一NMOS管；所述反相输出模块包括：第十二反相器、第二PMOS管和第二NMOS管；
    所述第一PMOS管的栅极作为所述同相输出模块的第一控制端，所述第一NMOS管的栅极作为所述同相输出模块的第二控制端，所述第一PMOS管的源极连接所述第一NMOS管的漏极并作为所述同相输出模块的输入端，所述第一PMOS管的漏极连接所述第一NMOS管的源极并作为所述同相输出模块的输出端；
    所述第二PMOS管的栅极作为所述反相输出模块的第一控制端，所述第二NMOS管的栅极作为所述反相输出模块的第二控制端，所述第十二反相器的输入端作为所述反相输出模块的输入端，所述第十二反相器的输出端连接所述第二PMOS管的源极和所述第二NMOS管的漏极，所述第二PMOS管的漏极连接所述第二NMOS管的源极并作为所述反相输出模块的输出端。
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