WO2023228853A1 - 基板処理装置 - Google Patents

基板処理装置 Download PDF

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Publication number
WO2023228853A1
WO2023228853A1 PCT/JP2023/018559 JP2023018559W WO2023228853A1 WO 2023228853 A1 WO2023228853 A1 WO 2023228853A1 JP 2023018559 W JP2023018559 W JP 2023018559W WO 2023228853 A1 WO2023228853 A1 WO 2023228853A1
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WO
WIPO (PCT)
Prior art keywords
layer
processing apparatus
resistance
layers
substrate processing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2023/018559
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English (en)
French (fr)
Japanese (ja)
Inventor
能吏 山本
和人 山田
雅典 ▲高▼橋
真矢 石川
匠大 江崎
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Tokyo Electron Ltd
Original Assignee
Tokyo Electron Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Electron Ltd filed Critical Tokyo Electron Ltd
Priority to CN202380041066.2A priority Critical patent/CN119213547A/zh
Priority to JP2024523080A priority patent/JPWO2023228853A1/ja
Priority to KR1020247041557A priority patent/KR20250019055A/ko
Publication of WO2023228853A1 publication Critical patent/WO2023228853A1/ja
Priority to US18/957,942 priority patent/US20250087470A1/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/76—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using mechanical means, e.g. clamps or pinches
    • H10P72/7604—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using mechanical means, e.g. clamps or pinches the wafers being placed on a susceptor, stage or support
    • H10P72/7624—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using mechanical means, e.g. clamps or pinches the wafers being placed on a susceptor, stage or support characterised by the mechanical construction of the susceptor, stage or support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/32—Gas-filled discharge tubes
    • H01J37/32431—Constructional details of the reactor
    • H01J37/32715—Workpiece holder
    • H01J37/32724—Temperature
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01K—MEASURING TEMPERATURE; MEASURING QUANTITY OF HEAT; THERMALLY-SENSITIVE ELEMENTS NOT OTHERWISE PROVIDED FOR
    • G01K7/00—Measuring temperature based on the use of electric or magnetic elements directly sensitive to heat ; Power supply therefor, e.g. using thermoelectric elements
    • G01K7/16—Measuring temperature based on the use of electric or magnetic elements directly sensitive to heat ; Power supply therefor, e.g. using thermoelectric elements using resistive elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/32—Gas-filled discharge tubes
    • H01J37/32009—Arrangements for generation of plasma specially adapted for examination or treatment of objects, e.g. plasma sources
    • H01J37/32082—Radio frequency generated discharge
    • H01J37/32091—Radio frequency generated discharge the radio frequency energy being capacitively coupled to the plasma
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/32—Gas-filled discharge tubes
    • H01J37/32431—Constructional details of the reactor
    • H01J37/32532—Electrodes
    • H01J37/32568—Relative arrangement or disposition of electrodes; moving means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/32—Gas-filled discharge tubes
    • H01J37/32431—Constructional details of the reactor
    • H01J37/32697—Electrostatic control
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/32—Gas-filled discharge tubes
    • H01J37/32917—Plasma diagnostics
    • H01J37/32935—Monitoring and controlling tubes by information coming from the object and/or discharge
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/04—Apparatus for manufacture or treatment
    • H10P72/0431—Apparatus for thermal treatment
    • H10P72/0432—Apparatus for thermal treatment mainly by conduction
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/06—Apparatus for monitoring, sorting, marking, testing or measuring
    • H10P72/0602—Temperature monitoring
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/72—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using electrostatic chucks
    • H10P72/722—Details of electrostatic chucks

Definitions

  • An exemplary embodiment of the present disclosure relates to a substrate processing apparatus.
  • a substrate processing apparatus is used in processing a substrate.
  • the substrate processing apparatus includes a chamber, a base disposed within the chamber, and an electrostatic chuck disposed on the base.
  • a heater is arranged within an electrostatic chuck.
  • the present disclosure provides a technique for determining the temperature of an electrostatic chuck.
  • a substrate processing apparatus in one exemplary embodiment, includes a chamber, a base, an electrostatic chuck, a control circuit, and a detection circuit.
  • the chamber provides a processing space within it.
  • the base is located within the processing space.
  • the base provides an internal space within it.
  • the electrostatic chuck is placed on the base.
  • the electrostatic chuck includes a dielectric member, at least one heater electrode layer, and at least one resistive layer.
  • the dielectric member has a support surface.
  • the support surface includes a substrate support surface.
  • At least one heater electrode layer is disposed within the dielectric member.
  • At least one heater electrode layer is formed from a first material.
  • At least one resistive layer is disposed within the dielectric member.
  • At least one resistive layer is formed from a second material.
  • the at least one resistive layer is at least one resistive layer having a thickness of 300 ⁇ m or less.
  • the temperature coefficient of resistance of the second material is greater than or equal to the temperature coefficient of resistance of the first material.
  • a control circuit is arranged within the interior space. The control circuit is configured to control power applied to at least one heater electrode layer.
  • a sensing circuit is located within the interior space. The sensing circuit is configured to sense a voltage across the at least one resistive layer.
  • a technique for determining the temperature of an electrostatic chuck is provided.
  • FIG. 1 is a diagram for explaining a configuration example of a plasma processing system.
  • FIG. 2 is a diagram for explaining a configuration example of a capacitively coupled plasma processing apparatus.
  • FIG. 3 is a partially enlarged cross-sectional view of a substrate support according to one exemplary embodiment.
  • 1 is an exploded perspective view showing the configuration of an electrostatic chuck according to one exemplary embodiment.
  • FIG. 1 is a diagram illustrating a configuration of a sensing circuit according to one exemplary embodiment;
  • FIG. FIG. 2 is a plan view illustrating a multiple zone configuration of an electrostatic chuck according to one exemplary embodiment.
  • FIG. 3 is a partially enlarged cross-sectional view of an electrostatic chuck according to another exemplary embodiment.
  • FIG. 7 is a partially enlarged cross-sectional view of an electrostatic chuck according to yet another exemplary embodiment.
  • FIG. 7 is a partially enlarged cross-sectional view of an electrostatic chuck according to yet another exemplary embodiment.
  • FIG. 7 is a partially enlarged cross-sectional view of an electrostatic chuck according to yet another exemplary embodiment.
  • FIG. 7 is a partially enlarged cross-sectional view of an electrostatic chuck according to yet another exemplary embodiment.
  • FIG. 7 is a diagram illustrating a configuration of a sensing circuit according to another exemplary embodiment.
  • a plasma processing apparatus which is a substrate processing apparatus according to one exemplary embodiment, will be described with reference to FIGS. 1 and 2.
  • FIG. 1 is a diagram for explaining a configuration example of a plasma processing system.
  • a plasma processing system includes a plasma processing apparatus 1 and a controller 2.
  • the plasma processing system is an example of a substrate processing system
  • the plasma processing apparatus 1 is an example of a substrate processing apparatus.
  • the plasma processing apparatus 1 includes a plasma processing chamber 10, a substrate support section 11, and a plasma generation section 12.
  • the plasma processing chamber 10 has a plasma processing space.
  • the plasma processing chamber 10 also includes at least one gas supply port for supplying at least one processing gas to the plasma processing space, and at least one gas exhaust port for discharging gas from the plasma processing space.
  • the gas supply port is connected to a gas supply section 20, which will be described later, and the gas discharge port is connected to an exhaust system 40, which will be described later.
  • the substrate support section 11 is disposed within the plasma processing space and has a substrate support surface for supporting a substrate.
  • the plasma generation unit 12 is configured to generate plasma from at least one processing gas supplied into the plasma processing space.
  • the plasmas formed in the plasma processing space are capacitively coupled plasma (CCP), inductively coupled plasma (ICP), and ECR plasma (Electron-Cyclotron-Resonance Plasma).
  • CCP capacitively coupled plasma
  • ICP inductively coupled plasma
  • ECR plasma Electro-Cyclotron-Resonance Plasma
  • sma helicon wave excited plasma
  • HWP Helicon Wave Plasma
  • SWP surface wave plasma
  • various types of plasma generation sections may be used, including an AC (Alternating Current) plasma generation section and a DC (Direct Current) plasma generation section.
  • the AC signal (AC power) used in the AC plasma generator has a frequency in the range of 100 kHz to 10 GHz. Therefore, the AC signal includes an RF (Radio Frequency) signal and a microwave signal.
  • the RF signal has a frequency within the range of 100kHz to 150MHz.
  • the control unit 2 processes computer-executable instructions that cause the plasma processing apparatus 1 to perform various steps described in this disclosure.
  • the control unit 2 may be configured to control each element of the plasma processing apparatus 1 to perform the various steps described herein. In one embodiment, part or all of the control unit 2 may be included in the plasma processing apparatus 1.
  • the control unit 2 may include a processing unit 2a1, a storage unit 2a2, and a communication interface 2a3.
  • the control unit 2 is realized by, for example, a computer 2a.
  • the processing unit two a1 may be configured to read a program from the storage unit two a2 and perform various control operations by executing the read program. This program may be stored in the storage unit 2a2 in advance, or may be acquired via a medium when necessary.
  • the acquired program is stored in the storage unit 2a2, and is read out from the storage unit 2a2 and executed by the processing unit 2a1.
  • the medium may be various storage media readable by the computer 2a, or may be a communication line connected to the communication interface 2a3.
  • the processing unit 2a1 may be a CPU (Central Processing Unit).
  • the storage unit 2a2 includes a RAM (Random Access Memory), a ROM (Read Only Memory), an HDD (Hard Disk Drive), an SSD (Solid State Drive), or a combination thereof. You can.
  • the communication interface 2a3 may communicate with the plasma processing apparatus 1 via a communication line such as a LAN (Local Area Network).
  • FIG. 2 is a diagram for explaining a configuration example of a capacitively coupled plasma processing apparatus.
  • the capacitively coupled plasma processing apparatus 1 includes a plasma processing chamber 10, a gas supply section 20, a power supply 30, and an exhaust system 40. Further, the plasma processing apparatus 1 includes a substrate support section 11 and a gas introduction section. The gas inlet is configured to introduce at least one processing gas into the plasma processing chamber 10 .
  • the gas introduction section includes a shower head 13.
  • Substrate support 11 is arranged within plasma processing chamber 10 .
  • the shower head 13 is arranged above the substrate support section 11 . In one embodiment, showerhead 13 forms at least a portion of the ceiling of plasma processing chamber 10 .
  • the plasma processing chamber 10 has a plasma processing space 10s defined by a shower head 13, a side wall 10a of the plasma processing chamber 10, and a substrate support 11. Plasma processing chamber 10 is grounded.
  • the shower head 13 and the substrate support section 11 are electrically insulated from the casing of the plasma processing chamber 10.
  • the substrate support section 11 includes a main body section 111 and a ring assembly 112.
  • the main body portion 111 has a central region 111a for supporting the substrate W and an annular region 111b for supporting the ring assembly 112.
  • a wafer is an example of a substrate W.
  • the annular region 111b of the main body 111 surrounds the central region 111a of the main body 111 in plan view.
  • the substrate W is placed on the central region 111a of the main body 111, and the ring assembly 112 is placed on the annular region 111b of the main body 111 so as to surround the substrate W on the central region 111a of the main body 111. Therefore, the central region 111a is also called a substrate support surface for supporting the substrate W, and the annular region 111b is also called a ring support surface for supporting the ring assembly 112.
  • the main body 111 includes a base 5 and an electrostatic chuck 6.
  • Base 5 includes a conductive member.
  • the conductive member of the base 5 can function as a lower electrode.
  • the electrostatic chuck 6 is placed on the base 5.
  • the electrostatic chuck 6 includes a ceramic member 1111a and an electrostatic electrode 1111b disposed within the ceramic member 1111a.
  • Ceramic member 1111a has a central region 111a. In one embodiment, ceramic member 1111a also has an annular region 111b. Note that another member surrounding the electrostatic chuck 6, such as an annular electrostatic chuck or an annular insulating member, may have the annular region 111b.
  • the ring assembly 112 may be placed on the annular electrostatic chuck or the annular insulating member, or may be placed on both the electrostatic chuck 6 and the annular insulating member.
  • at least one RF/DC electrode coupled to an RF power source 31 and/or a DC power source 32, which will be described later, may be disposed within the ceramic member 1111a.
  • at least one RF/DC electrode functions as a bottom electrode.
  • An RF/DC electrode is also referred to as a bias electrode if a bias RF signal and/or a DC signal, as described below, is supplied to at least one RF/DC electrode.
  • the conductive member of the base 5 and at least one RF/DC electrode may function as a plurality of lower electrodes.
  • the electrostatic electrode 1111b may function as a lower electrode. Therefore, the substrate support 11 includes at least one lower electrode.
  • Ring assembly 112 includes one or more annular members.
  • the one or more annular members include one or more edge rings and at least one cover ring.
  • the edge ring is made of a conductive or insulating material
  • the cover ring is made of an insulating material.
  • the substrate support section 11 may include a temperature control module configured to adjust at least one of the electrostatic chuck 6, the ring assembly 112, and the substrate to a target temperature.
  • the temperature control module may include a heater, a heat transfer medium, a flow path 1110a, or a combination thereof.
  • a heat transfer fluid such as brine or gas flows through the flow path 1110a.
  • a channel 1110a is formed in the base 5 and one or more heaters are disposed in the ceramic member 1111a of the electrostatic chuck 6.
  • the substrate support section 11 may include a heat transfer gas supply section configured to supply heat transfer gas to the gap between the back surface of the substrate W and the central region 111a.
  • the shower head 13 is configured to introduce at least one processing gas from the gas supply section 20 into the plasma processing space 10s.
  • the shower head 13 has at least one gas supply port 13a, at least one gas diffusion chamber 13b, and a plurality of gas introduction ports 13c.
  • the processing gas supplied to the gas supply port 13a passes through the gas diffusion chamber 13b and is introduced into the plasma processing space 10s from the plurality of gas introduction ports 13c.
  • the showerhead 13 also includes at least one upper electrode.
  • the gas introduction section may include one or more side gas injectors (SGI) attached to one or more openings formed in the side wall 10a.
  • SGI side gas injectors
  • the gas supply section 20 may include at least one gas source 21 and at least one flow rate controller 22.
  • the gas supply 20 is configured to supply at least one process gas from a respective gas source 21 to the showerhead 13 via a respective flow controller 22 .
  • Each flow controller 22 may include, for example, a mass flow controller or a pressure-controlled flow controller.
  • gas supply 20 may include at least one flow modulation device that modulates or pulses the flow rate of at least one process gas.
  • Power supply 30 includes an RF power supply 31 coupled to plasma processing chamber 10 via at least one impedance matching circuit.
  • RF power source 31 is configured to supply at least one RF signal (RF power) to at least one bottom electrode and/or at least one top electrode.
  • RF power supply 31 can function as at least a part of the plasma generation section 12. Further, by supplying a bias RF signal to at least one lower electrode, a bias potential is generated in the substrate W, and ion components in the formed plasma can be drawn into the substrate W.
  • the RF power supply 31 includes a first RF generation section 31a and a second RF generation section 31b.
  • the first RF generation section 31a is coupled to at least one lower electrode and/or at least one upper electrode via at least one impedance matching circuit, and generates a source RF signal (source RF power) for plasma generation. It is configured as follows.
  • the source RF signal has a frequency within the range of 10 MHz to 150 MHz.
  • the first RF generator 31a may be configured to generate multiple source RF signals having different frequencies. The generated one or more source RF signals are provided to at least one bottom electrode and/or at least one top electrode.
  • the second RF generating section 31b is coupled to at least one lower electrode via at least one impedance matching circuit, and is configured to generate a bias RF signal (bias RF power).
  • the frequency of the bias RF signal may be the same or different than the frequency of the source RF signal.
  • the bias RF signal has a lower frequency than the frequency of the source RF signal.
  • the bias RF signal has a frequency within the range of 100kHz to 60MHz.
  • the second RF generator 31b may be configured to generate multiple bias RF signals having different frequencies.
  • the generated one or more bias RF signals are provided to at least one bottom electrode. Also, in various embodiments, at least one of the source RF signal and the bias RF signal may be pulsed.
  • Power source 30 may also include a DC power source 32 coupled to plasma processing chamber 10 .
  • the DC power supply 32 includes a first DC generation section 32a and a second DC generation section 32b.
  • the first DC generator 32a is connected to at least one lower electrode and configured to generate a first DC signal.
  • the generated first DC signal is applied to at least one bottom electrode.
  • the second DC generator 32b is connected to the at least one upper electrode and configured to generate a second DC signal.
  • the generated second DC signal is applied to the at least one top electrode.
  • the first and second DC signals may be pulsed.
  • a sequence of voltage pulses is applied to at least one lower electrode and/or at least one upper electrode.
  • the voltage pulse may have a pulse waveform that is rectangular, trapezoidal, triangular, or a combination thereof.
  • a waveform generator for generating a sequence of voltage pulses from a DC signal is connected between the first DC generator 32a and the at least one bottom electrode. Therefore, the first DC generation section 32a and the waveform generation section constitute a voltage pulse generation section.
  • the voltage pulse generation section is connected to at least one upper electrode.
  • the voltage pulse may have positive polarity or negative polarity.
  • the sequence of voltage pulses may include one or more positive voltage pulses and one or more negative voltage pulses within one cycle.
  • the first and second DC generation units 32a and 32b may be provided in addition to the RF power source 31, or the first DC generation unit 32a may be provided in place of the second RF generation unit 31b. good.
  • the exhaust system 40 may be connected to a gas exhaust port 10e provided at the bottom of the plasma processing chamber 10, for example.
  • Evacuation system 40 may include a pressure regulating valve and a vacuum pump. The pressure within the plasma processing space 10s is adjusted by the pressure regulating valve.
  • the vacuum pump may include a turbomolecular pump, a dry pump, or a combination thereof.
  • FIG. 3 is a partially enlarged cross-sectional view of a substrate support according to one exemplary embodiment.
  • the plasma processing apparatus 1 includes the chamber 10, the base 5, and the electrostatic chuck 6.
  • the chamber 10 provides a processing space 10s therein.
  • the base 5 is arranged within the processing space 10s.
  • the base 5 provides an internal space 5s inside thereof.
  • the electrostatic chuck 6 is placed on the base 5.
  • the electrostatic chuck 6 may be placed on the base 5 with a heat insulating member (adhesive layer) 51 in between.
  • the heat insulating member 51 is made of silicone, for example.
  • Electrostatic chuck 6 includes a dielectric member 61, at least one heater electrode layer, and at least one resistive layer. At least one resistive layer has a thickness of 300 ⁇ m or less. In one embodiment, at least one resistive layer may have a thickness of 100 ⁇ m or less.
  • a plasma processing apparatus 1 including a plurality of heater electrode layers 62 and a plurality of resistance layers 63 will be described, but the plasma processing apparatus 1 may include a single heater electrode layer and a single resistance layer.
  • Each of the plurality of resistance layers 63 has a thickness of 300 ⁇ m or less.
  • Each of the plurality of resistance layers 63 may have a thickness of 100 ⁇ m or less.
  • the ceramic member 1111a is an example of the dielectric member 61. Ceramic member 1111a may be formed by thermal spraying. Dielectric member 61 may be made of polyimide. Dielectric member 61 has a support surface 61a. The support surface 61a is the upper surface of each of the dielectric member 61 and the electrostatic chuck 6. The support surface 61a includes a substrate support surface, ie, a central region 111a. The support surface 61a may further include a ring support surface or annular region 111b.
  • the plurality of heater electrode layers 62 are arranged within the dielectric member 61.
  • the plurality of resistance layers 63 are arranged within the dielectric member 61.
  • the positions of the plurality of heater electrode layers 62 in the thickness direction D1 within the electrostatic chuck 6 are different from the positions of the plurality of resistance layers 63 in the thickness direction D1.
  • the positions of the plurality of heater electrode layers 62 in the thickness direction D1 within the electrostatic chuck 6 are 6/7 of the thickness of the electrostatic chuck 6 from the support surface 61a, or from the support surface 61a to This position is closer to the support surface 61a than 6/7 of the thickness of the chuck 6.
  • the plurality of heater electrode layers 62 may extend between the plurality of resistance layers 63 and the support surface 61a.
  • the electrostatic electrode 1111b may extend between the plurality of heater electrode layers 62 and the support surface 61a.
  • FIG. 4 is an exploded perspective view showing the configuration of an electrostatic chuck according to one exemplary embodiment.
  • the dielectric member 61 is composed of a plurality of stacked dielectric layers 61b.
  • the thickness direction D1 may be the same as the stacking direction of the plurality of dielectric layers 61b.
  • the thickness of the dielectric layer 61b is, for example, 0.35 mm.
  • the plurality of heater electrode layers 62 and the plurality of resistance layers 63 are respectively arranged on two dielectric layers among the plurality of dielectric layers 61b.
  • the two dielectric layers may be adjacent to each other in the stacking direction. In this case, the distance between the plurality of heater electrode layers 62 and the plurality of resistance layers 63 in the thickness direction D1 is 0.35 mm or more.
  • each of the plurality of heater electrode layers 62 may include a first end 62a and a second end 62b. In one example, each of the plurality of heater electrode layers 62 extends in a meandering manner from a first end 62a to a second end 62b on a corresponding dielectric layer among the plurality of dielectric layers 61b.
  • Each of the plurality of resistance layers 63 may include a first end 63a and a second end 63b. In one example, each of the plurality of resistance layers 63 extends in a meandering manner from a first end 63a to a second end 63b on a corresponding dielectric layer among the plurality of dielectric layers 61b.
  • the plurality of heater electrode layers 62 are formed from a first material.
  • the first material includes at least one material selected from a first group of materials consisting of tungsten, copper, silver, and aluminum.
  • the plurality of resistance layers 63 are formed from a second material.
  • the second material includes at least one material selected from the second group of materials consisting of tungsten, nickel, molybdenum, and platinum.
  • the temperature coefficient of resistance of the second material is greater than or equal to the temperature coefficient of resistance of the first material.
  • the first material and the second material are selected from the first group of materials and the second group of materials such that the temperature coefficient of resistance of the second material is greater than or equal to the temperature coefficient of resistance of the first material. , respectively, are selected.
  • the second material may be tungsten.
  • the first material and the second material may be tungsten.
  • the first material may be copper and the second material may be tungsten.
  • the first material may be tungsten and the second material may be nickel.
  • the first material may be silver and the second material may be molybdenum.
  • the first material may be aluminum and the second material may be molybdenum.
  • the temperature coefficient of resistance of the second material may be greater than the temperature coefficient of resistance of the first material.
  • the plasma processing apparatus 1 further includes a control circuit 7 and a detection circuit 8.
  • the control circuit 7 and the detection circuit 8 are communicably connected to each other.
  • the control circuit 7 and the detection circuit 8 may be communicably connected to the control unit 2.
  • the control circuit 7 and the detection circuit 8 may be part of the control section 2.
  • the control circuit 7 is arranged in the internal space 5s.
  • the control circuit 7 is configured to control the power applied to each of the plurality of heater electrode layers 62.
  • the control circuit 7 may be electrically connected to each of the first end 62a and the second end 62b.
  • the detection circuit 8 is arranged in the internal space 5s.
  • the detection circuit 8 is configured to detect the voltage applied to each of the plurality of resistance layers 63.
  • the detection circuit 8 may be electrically connected to each of the first end 63a and the second end 63b.
  • FIG. 5 is a diagram illustrating the configuration of a sensing circuit according to one exemplary embodiment.
  • the sensing circuit 8 may include multiple resistor voltage divider circuits 81 and multiple A/D converters 82.
  • each of the plurality of resistance voltage divider circuits 81 includes a corresponding resistance layer 630 among the plurality of resistance layers 63 and a reference resistor R.
  • a reference resistor R is connected in series to the resistive layer 630.
  • One end of the reference resistor R is connected to a power source, and the other end of the reference resistor R is connected to one end (for example, the first end 63a) of the resistance layer 630.
  • the other end of the resistance layer 630 (for example, the second end 63b) is connected to the ground G.
  • Each of the plurality of A/D converters 82 converts the voltage applied to the corresponding resistance layer 630 into a digital value.
  • each of the plurality of A/D converters 82 is connected to the first end 63a of the resistance layer 630.
  • the first end 63a is connected to the reference resistor R.
  • the second end 63b may be connected to ground G.
  • a power supply voltage is applied to the reference resistor R and the resistance layer 630.
  • a voltage of R2/(R1+R2) ⁇ Vin is applied to the resistance layer 630.
  • R1 is the resistance value of the reference resistor R
  • R2 is the resistance value of the resistance layer 630
  • Vin is the power supply voltage.
  • A/D converter 82 converts the voltage applied to resistive layer 630 into a digital value.
  • the detection circuit 8 further includes an FPGA 83 (Field Programmable Gate Array). The FPGA 83 acquires a digital value from the A/D converter 82 and outputs the digital value in a communicable format.
  • the amount of heat generated by the plurality of heater electrode layers 62 is controlled according to the applied power controlled by the control circuit 7.
  • the temperature of the electrostatic chuck 6 changes depending on the amount of heat generated by the plurality of heater electrode layers 62.
  • the temperature of the corresponding resistance layer 630 among the plurality of resistance layers 63 arranged in the dielectric member 61 changes.
  • the resistance value of the resistance layer 630 changes in proportion to the temperature coefficient of resistance of the second material forming the resistance layer 630.
  • the temperature of the resistance layer 630 is determined from the voltage applied to the resistance layer 630. Therefore, in the plasma processing apparatus 1, the temperature of the electrostatic chuck is specified.
  • the sensing circuit 8 is configured to determine the temperature of the resistive layer 630 from the voltage across the resistive layer 630.
  • the respective relationships between the temperatures of the plurality of resistance layers 63 and the voltages applied to the plurality of resistance layers 63 may be given in advance.
  • the detection circuit 8 stores the resistance value of the reference resistor R and the reference voltage.
  • control circuit 7 may be configured to determine the temperature of resistive layer 630 from the voltage across resistive layer 630. Control circuit 7 can obtain the voltage applied to resistance layer 630 from detection circuit 8 .
  • the control unit 2 may be configured to identify the temperature of the resistance layer 630 from the voltage applied to the resistance layer 630.
  • FIG. 6 is a top view illustrating the configuration of multiple zones of an electrostatic chuck according to one exemplary embodiment.
  • FIG. 6 shows the support surface 61a viewed from the thickness direction D1.
  • the support surface 61a has a circular shape centered on the central axis AX when viewed from the thickness direction D1.
  • support surface 61a includes multiple regions 61c.
  • the region concentric with the central axis AX includes one or more corresponding regions among the plurality of regions 61c.
  • the plurality of regions 61c may include a plurality of sector-shaped regions including the central axis AX, and a plurality of sector-shaped trapezoidal regions centered on the central axis AX.
  • the electrostatic chuck 6 includes a plurality of zones 6a each including a plurality of regions 61c. As shown in FIG. 6, the plurality of zones 6a may each include a plurality of regions 61c that overlap with the plurality of zones 6a when viewed from the thickness direction D1. In the example shown in FIG. 6, the electrostatic chuck 6 includes 32 zones, but the invention is not limited to this. The electrostatic chuck 6 may include 32 or more zones, or may include fewer than 32 zones.
  • the plurality of heater electrode layers 62 are arranged within the plurality of zones 6a, respectively.
  • the plurality of resistance layers 63 are arranged within the plurality of zones 6a, respectively.
  • the control circuit 7 is configured to control a plurality of applied powers applied to the plurality of heater electrode layers 62, respectively.
  • the detection circuit 8 is configured to detect a plurality of voltage values applied to the plurality of resistance layers 63, respectively.
  • the amount of heat generated by the plurality of heater electrode layers 62 is controlled according to the plurality of applied powers controlled by the control circuit 7.
  • the temperatures of the plurality of zones 6a change depending on the amount of heat generated by the plurality of heater electrode layers 62, respectively.
  • the temperature of the resistance layer 630 disposed within the dielectric member 61 of the corresponding zone among the plurality of zones 6a changes.
  • the resistance value of the resistance layer 630 changes in proportion to the temperature coefficient of resistance of the second material forming the resistance layer 630.
  • the voltage applied to the resistance layer 630 changes.
  • the temperature of the resistance layer 630 is determined from the voltage applied to the resistance layer 630. Therefore, in the plasma processing apparatus 1, the temperatures of each of the plurality of zones 6a are specified.
  • FIG. 7 is a partially enlarged cross-sectional view of an electrostatic chuck according to another exemplary embodiment.
  • the electrostatic chuck 6A of the plasma processing apparatus 1A shown in FIG. 7 will be described below from the viewpoint of differences from the electrostatic chuck 6 of the plasma processing apparatus 1.
  • the plurality of resistance layers 63 extend between the plurality of heater electrode layers 62 and the support surface 61a. According to the plasma processing apparatus 1A, since the plurality of resistance layers 63 are provided closer to the support surface 61a than the plurality of heater electrode layers 62, the difference between the temperature of the plurality of resistance layers 63 and the temperature of the support surface 61a is reduced. is small. Note that the electrostatic electrode 1111b may extend between the plurality of resistance layers 63 and the support surface 61a.
  • FIG. 8 is a partially enlarged cross-sectional view of an electrostatic chuck according to yet another exemplary embodiment.
  • the electrostatic chuck 6B of the plasma processing apparatus 1B shown in FIG. 8 will be described below from the viewpoint of differences from the electrostatic chuck 6A of the plasma processing apparatus 1A.
  • the electrostatic chuck 6B includes at least one high frequency electrode layer.
  • the electrostatic chuck 6B includes a plurality of high frequency electrode layers 64.
  • the plurality of high-frequency electrode layers 64 may be arranged within the plurality of zones 6a, respectively.
  • Each of the plurality of high frequency electrode layers 64 is electrically connected to the base 5.
  • the plurality of high frequency electrode layers 64 may be formed from the same material as the material forming the base 5.
  • the plurality of high frequency electrode layers 64 are formed from aluminum.
  • the plasma processing apparatus 1B further includes a high frequency power source.
  • the high frequency power source is electrically connected to the base 5.
  • the RF power source 31 is an example of the high frequency power source.
  • the plurality of high-frequency electrode layers 64 surround the plurality of heater electrode layers 62 and the plurality of resistance layers 63, respectively, within the electrostatic chuck 6B. Seen from the thickness direction D1, the plurality of heater electrode layers 62 and the plurality of resistance layers 63 may be covered with the plurality of high-frequency electrode layers 64, respectively. In one embodiment, the electrostatic electrode 1111b may extend between the support surface 61a and the plurality of high frequency electrode layers 64.
  • the plurality of high-frequency electrode layers 64 are at the same potential as the base 5, so the plurality of high-frequency electrode layers 64 can function as a lower electrode.
  • the plural heater electrode layers 62 and the plural resistance layers 63 are surrounded by the plural high frequency electrode layers 64 having the same potential as the base 5. Therefore, RF noise caused by RF signals (RF power) is suppressed from being applied to the plurality of resistance layers 63.
  • the electrostatic chuck 6B may include a single high-frequency electrode layer.
  • a single high frequency electrode layer is arranged across multiple zones 6a.
  • a single high frequency electrode layer surrounds multiple heater electrode layers 62 and multiple resistive layers 63 within electrostatic chuck 6B. When viewed from the thickness direction D1, the plurality of heater electrode layers 62 and the plurality of resistance layers 63 may be covered by a single high-frequency electrode layer.
  • FIG. 9 is a partially enlarged cross-sectional view of an electrostatic chuck according to yet another exemplary embodiment.
  • the electrostatic chuck 6C of the plasma processing apparatus 1C shown in FIG. 9 will be described below from the viewpoint of differences from the electrostatic chuck 6A of the plasma processing apparatus 1A.
  • the electrostatic chuck 6C includes a plurality of resistance layers 63C.
  • Each of the plurality of resistance layers 63C includes a first resistance layer 631 and a second resistance layer 632.
  • the second resistive layer 632 extends between the first resistive layer 631 and the support surface 61a.
  • Electrostatic electrode 1111b may extend between second resistance layer 632 and support surface 61a.
  • the control unit 2 is configured to detect the first voltage applied to the first resistance layer 631 and the second voltage applied to the second resistance layer 632, respectively.
  • the detection circuit 8 may be configured to detect the first voltage applied to the first resistance layer 631 and the second voltage applied to the second resistance layer 632, respectively.
  • the detection circuit 8 includes a plurality of resistance voltage divider circuits 81 and a plurality of A/D converters 82 corresponding to the first resistance layer 631 and the second resistance layer 632, respectively.
  • the first resistance voltage divider circuit corresponding to the first resistance layer 631 among the plurality of resistance voltage divider circuits 81 includes the first resistance layer 631 and the first reference resistance instead of the resistance layer 630 and the reference resistance R. including.
  • the second resistance voltage divider circuit corresponding to the second resistance layer 632 among the plurality of resistance voltage divider circuits 81 includes a second resistance layer 632 and a second reference resistance instead of the resistance layer 630 and the reference resistance R. including.
  • the first A/D converter corresponding to the first resistance layer 631 among the plurality of A/D converters 82 converts the voltage applied to the first resistance layer 631 into a digital value.
  • the second A/D converter corresponding to the second resistance layer 632 among the plurality of A/D converters 82 converts the voltage applied to the second resistance layer 632 into a digital value.
  • a first voltage is applied to the first resistance layer 631.
  • a second voltage is applied to the second resistance layer 632.
  • the control unit 2 is configured to specify the first temperature of the first resistance layer 631 and the second temperature of the second resistance layer 632, respectively, from the first voltage and the second voltage.
  • the sensing circuit 8 or the control circuit 7 determines the first temperature of the first resistive layer 631 and the second temperature of the second resistive layer 632 from the first voltage and the second voltage, respectively. It may be configured to specify.
  • the control unit 2 controls a first temperature T1 (K), a second temperature T2 (K), a thermal conductivity S (W/(m ⁇ K)) of the dielectric member 61, and a first temperature in the thickness direction D1.
  • the heat flux q (W/m 2 ) from the support surface 61a is determined based on the distance L (m) between the resistance layer 631 and the second resistance layer 632.
  • the thermal conductivity S (W/(m ⁇ K)) and the distance L (m) may be given in advance.
  • the control unit 2 stores thermal conductivity S (W/(m ⁇ K)) and distance L (m).
  • FIG. 10 is a partially enlarged cross-sectional view of an electrostatic chuck according to yet another exemplary embodiment.
  • the electrostatic chuck 6D of the plasma processing apparatus 1D shown in FIG. 10 will be described below from the viewpoint of differences from the electrostatic chuck 6 of the plasma processing apparatus 1.
  • the positions of the plurality of heater electrode layers 62 in the thickness direction D1 within the electrostatic chuck 6D are the same as the positions of the plurality of resistance layers 63 in the thickness direction D1.
  • the distance between the support surface 61a and the plurality of heater electrode layers 62 in the thickness direction D1 and the distance between the support surface 61a and the plurality of resistance layers 63 in the thickness direction D1 are equal to each other.
  • the plurality of heater electrode layers 62 and the plurality of resistance layers 63 are arranged at the same position in the thickness direction D1 within the electrostatic chuck 6D.
  • FIG. 11 is a partially enlarged cross-sectional view of an electrostatic chuck according to yet another exemplary embodiment.
  • the electrostatic chuck 6E of the plasma processing apparatus 1E shown in FIG. 11 will be described below from the viewpoint of differences from the electrostatic chuck 6 of the plasma processing apparatus 1.
  • the electrostatic chuck 6E includes a plurality of resistance layers 63E.
  • Each of the plurality of resistance layers 63E includes a plurality of layers 63c.
  • resistive layer 630 may include multiple layers 63c.
  • Each of the plurality of layers 63c is a resistance layer.
  • the plurality of layers 63c are laminated between the support surface 61a and the base 5 within the electrostatic chuck 6E.
  • the plurality of layers 63c are stacked between the base 5 and the plurality of heater electrode layers 62.
  • the plurality of layers 63c may be laminated between the support surface 61a and the plurality of heater electrode layers 62.
  • the plurality of layers 63c are connected in series. Adjacent layers among the plurality of layers 63c may be connected in series through via holes.
  • control circuit 7 and the detection circuit 8 may be placed outside the internal space 5s.
  • FIG. 12 is a diagram showing the configuration of a detection circuit according to another exemplary embodiment.
  • the detection circuit 8 may include a constant current source I instead of the reference resistor R.
  • Constant current source I is connected to resistance layer 630.
  • A/D converter 82 converts the voltage applied to resistive layer 630 into a digital value.
  • the constant current source I is connected to one end (for example, the first end 63a) of the resistance layer 630.
  • the A/D converter 82 is connected to one end (first end 63a) connected to the constant current source I.
  • the voltage value applied to the resistance layer 630 changes in accordance with the change in the resistance value of the resistance layer 630 so that the current applied to the resistance layer 630 becomes constant.
  • two or more of the plurality of resistance layers 63 may be arranged in at least one of the plurality of zones 6a. In at least one zone, the temperatures of two or more portions where two or more resistive layers are respectively disposed are determined.
  • the two or more resistance layers may each include a plurality of layers 63c.
  • At least one of the plurality of resistance layers 63 may be arranged across two or more zones among the plurality of zones 6a. Two or more zones may be adjacent to each other. The temperatures of two or more zones among the plurality of zones 6a are specified by at least one resistance layer among the plurality of resistance layers 63.
  • the plurality of high frequency electrode layers 64 may be applied to the electrostatic chuck 6 shown in FIG. 3 in which the plurality of heater electrode layers 62 extend between the plurality of resistance layers 63 and the support surface 61a.
  • the plurality of high frequency electrode layers 64 may be applied to an electrostatic chuck 6C including a first resistance layer 631 and a second resistance layer 632 shown in FIG.
  • the plurality of high-frequency electrode layers 64 are an electrostatic chuck in which the positions of the plurality of heater electrode layers 62 in the thickness direction D1 in the electrostatic chuck 6D shown in FIG. 10 are the same as the positions of the plurality of resistance layers 63 in the thickness direction D1. 6D may also be applied.
  • a plurality of heater electrode layers 62 may extend between a plurality of resistance layers 63C and a support surface 61a.
  • a substrate processing apparatus comprising: [E2] The substrate processing apparatus according to [E1], wherein the temperature coefficient of resistance of the second material is larger than the temperature coefficient of resistance
  • [E3] The substrate processing apparatus according to [E1] or [E2], wherein the second material is tungsten.
  • [E4] The substrate processing apparatus according to any one of [E1] to [E3], wherein the thickness of the at least one resistance layer is 100 ⁇ m or less.
  • the position of the at least one heater electrode layer in the thickness direction within the electrostatic chuck is different from the position of the at least one resistance layer in the thickness direction, and may be any one of [E1] to [E4].
  • [E6] The substrate processing apparatus according to [E5], wherein the at least one heater electrode layer extends between the at least one resistance layer and the support surface.
  • the substrate processing apparatus includes a first resistive layer and a second resistive layer; the second resistive layer extends between the first resistive layer and the support surface;
  • the detection circuit is configured to detect a first voltage applied to the first resistance layer and a second voltage applied to the second resistance layer, respectively,
  • the substrate processing apparatus is configured to identify a first temperature of the first resistance layer and a second temperature of the second resistance layer from the first voltage and the second voltage, respectively.
  • a control unit that controls the first temperature, the second temperature, the thermal conductivity of the dielectric member, and the first resistance layer and the second resistance layer in the thickness direction.
  • the substrate processing apparatus according to any one of [E1] to [E7], further comprising the control unit configured to specify the heat flux from the support surface based on the distance between the support surfaces.
  • the position of the at least one heater electrode layer in the thickness direction within the electrostatic chuck is the same as the position of the at least one resistance layer in the thickness direction, [E1] to [E4], [E8 ] The substrate processing apparatus according to any one of the above.
  • the support surface includes a plurality of regions
  • the electrostatic chuck includes a plurality of zones each including the plurality of regions, the at least one heater electrode layer includes a plurality of heater electrode layers;
  • the plurality of heater electrode layers are each arranged within the plurality of zones, the at least one resistive layer includes a plurality of resistive layers;
  • the plurality of resistive layers each include at least one other resistive layer disposed within each of the plurality of zones,
  • the control circuit is configured to control each of the plurality of applied powers to the plurality of heater electrode layers,
  • the substrate processing apparatus according to any one of [E1] to [E9], wherein the detection circuit is configured to detect each of a plurality of voltage values applied to the plurality of resistance layers.
  • the support surface includes a plurality of regions,
  • the electrostatic chuck includes a plurality of zones each including the plurality of regions, the at least one heater electrode layer includes a plurality of heater electrode layers;
  • the plurality of heater electrode layers are each arranged within the plurality of zones, the at least one resistive layer includes a plurality of resistive layers;
  • the plurality of resistive layers include a resistive layer disposed across two or more corresponding zones among the plurality of zones,
  • the control circuit is configured to control each of the plurality of applied powers to the plurality of heater electrode layers,
  • the substrate processing apparatus according to any one of [E1] to [E9], wherein the detection circuit is configured to detect each of a plurality of voltage values applied to the plurality of resistance layers.
  • the at least one resistive layer includes a plurality of layers;
  • the substrate according to any one of [E1] to [E11], wherein the plurality of layers are stacked and connected in series between the support surface and the base within the electrostatic chuck.
  • Processing equipment [E13]
  • the electrostatic chuck further includes at least one high frequency electrode layer, the at least one high-frequency electrode layer is electrically connected to the base and surrounds the at least one heater electrode layer and the at least one resistance layer within the electrostatic chuck; [E1 ] to [E12].
  • the substrate processing apparatus according to any one of [E12].
  • the electrostatic chuck further includes an electrostatic electrode, The substrate processing apparatus according to [E13], wherein the electrostatic electrode extends between the support surface and the at least one high-frequency electrode layer.
  • the detection circuit includes: a resistive voltage divider circuit including the at least one resistive layer and a reference resistor connected in series with the at least one resistive layer; an A/D converter that converts the voltage applied to the at least one resistance layer into a digital value;
  • the A/D converter is connected to one end of the at least one resistance layer,
  • the substrate processing apparatus according to [E16] wherein the one end of the at least one resistance layer is connected to the reference resistor.
  • the detection circuit includes: a constant current source connected to the at least one resistance layer; an A/D converter that converts the voltage applied to the at least one resistance layer into a digital value;
  • the substrate processing apparatus according to any one of [E1] to [E15], comprising: [E19] The substrate processing apparatus according to [E18], wherein the A/D converter is connected to one end of the at least one resistance layer connected to the constant current source.
  • SYMBOLS 1 Plasma processing apparatus, 2... Control part, 5... Base, 5s... Internal space, 6, 6A, 6B, 6C, 6D, 6E... Electrostatic chuck, 6a... Plural zones, 7... Control circuit, 8...
  • Detection circuit 10...Chamber, 10s...Processing space, 61...Dielectric member, 61a...Supporting surface, 61c...Region, 62...Plurality of heater electrode layers, 63, 63C, 63E...Plurality of resistance layers, 631...First resistance layer, 632...second resistance layer, 63c...multiple layers, 64...high frequency electrode layer, 81...resistance voltage divider circuit, 82...A/D converter, 1111b...electrostatic electrode, D1...thickness direction , R...Reference resistance, I... Constant current source.

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  • Physics & Mathematics (AREA)
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  • Plasma & Fusion (AREA)
  • Chemical & Material Sciences (AREA)
  • Analytical Chemistry (AREA)
  • General Physics & Mathematics (AREA)
  • Drying Of Semiconductors (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
PCT/JP2023/018559 2022-05-26 2023-05-18 基板処理装置 Ceased WO2023228853A1 (ja)

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KR1020247041557A KR20250019055A (ko) 2022-05-26 2023-05-18 기판 처리 장치
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US20250087470A1 (en) 2025-03-13

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