WO2023221265A1 - 相控阵芯片测试系统架构 - Google Patents

相控阵芯片测试系统架构 Download PDF

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WO2023221265A1
WO2023221265A1 PCT/CN2022/104095 CN2022104095W WO2023221265A1 WO 2023221265 A1 WO2023221265 A1 WO 2023221265A1 CN 2022104095 W CN2022104095 W CN 2022104095W WO 2023221265 A1 WO2023221265 A1 WO 2023221265A1
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phased array
array chip
digital
test
system architecture
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PCT/CN2022/104095
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English (en)
French (fr)
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郭鹏
缪晔
陈智慧
何爱平
赵涤燹
叶晓菁
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成都天锐星通科技有限公司
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Publication of WO2023221265A1 publication Critical patent/WO2023221265A1/zh

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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G01R31/2886—Features relating to contacting the IC under test, e.g. probe heads; chucks
    • G01R31/2887—Features relating to contacting the IC under test, e.g. probe heads; chucks involving moving the probe head or the IC under test; docking stations
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G01R31/2884—Testing of integrated circuits [IC] using dedicated test connectors, test elements or test circuits on the IC under test

Definitions

  • the present invention relates to the field of chip testing technology, and specifically to a phased array chip testing system architecture.
  • phased array chip testing In the later period are becoming more and more complex.
  • chip test solutions There are currently a variety of existing chip test solutions, but they are mainly aimed at functional verification of digital chips.
  • phased array chip test methods After investigation by the inventor, it was found that it is difficult to conduct comprehensive functional testing of phased array chips with existing testing technology, so a new testing method is urgently needed to verify the complex functions of phased array chips.
  • the objects of the present invention include, for example, providing a phased array chip testing system architecture, which can realize the testing of the phased array chip, realize the functional testing of the radio frequency and digital parts of the phased array chip at the same time, and can completely It can test whether the radio frequency function of the phased array chip is qualified and whether there are any problems in digital signal transmission, which solves the problem of complex function verification of the phased array chip.
  • the present invention provides a phased array chip testing system architecture, including:
  • phased array chip the phased array chip is mounted on the test circuit board;
  • a radio frequency probe is arranged above the test circuit board and is used to make electrical contact with the phased array chip to realize the transmission of radio frequency signals of the phased array chip;
  • a digital wiring layer is provided on the test circuit board, the phased array chip is electrically connected to the digital wiring layer, and the digital wiring layer is used to realize the transmission of digital signals of the phased array chip.
  • the phased array chip test system architecture also includes a digital signal processing module, the digital signal processing module is communicatively connected to the digital wiring layer, and is used to control the digital signal of the phased array chip. signals, and implement digital signal testing of the phased array chip.
  • the test circuit board is provided with a mounting area for mounting the phased array chip, the phased array chip is being mounted in the mounting area, and the phased array chip is mounted in the mounting area.
  • a number of conductive gold wires are provided on the surface of the side of the chip away from the test circuit board. The conductive gold wires are connected to the digital wiring layer, so that the phased array chip is electrically connected to the digital wiring layer.
  • the digital wiring layer includes a power supply line and a digital transmission line
  • the test circuit board is also provided with a power interface and a digital interface
  • the power interface is provided at one end of the power supply line.
  • the other end of the power supply line extends to the phased array chip and is electrically connected to the phased array chip through the conductive gold wire;
  • the digital interface is provided at one end of the digital transmission line, and the digital transmission line The other end of the line extends to the phased array chip and is electrically connected to the phased array chip through the conductive gold wire.
  • the digital signal processing module is communicatively connected to the digital interface.
  • both the power supply line and the digital transmission line extend to the mounting area, and one end of the digital transmission line away from the digital interface is provided with a digital pin.
  • the conductive gold wire is electrically connected to the phased array chip.
  • One end of the power supply line away from the power interface is provided with a power supply pin.
  • the power supply pin is connected to the phased array chip through the conductive gold wire. Chip electrical connections.
  • the power supply lines are distributed on both sides of the mounting area, and the power supply pins are provided on both sides of the mounting area, and the two power supply lines are far away from the mounting area.
  • the power interface is provided at both ends of the mounting area.
  • the digital signal processing module and the digital interface are connected through SPI serial port communication.
  • the phased array chip is bonded to the mounting area through conductive adhesive.
  • the digital signal processing module is an FPGA module, and the FPGA module is used to connect to a central control computer and set the register status of the phased array chip.
  • the phased array chip testing system architecture further includes a probe station, the radio frequency probe is arranged on the probe station, and the phased array chip is far away from the test circuit board.
  • a radio frequency pin is provided on one side, and the radio frequency probe is used to move above the phased array chip driven by the probe station and make alignment contact with the radio frequency pin to realize radio frequency signal interconnection.
  • the phased array chip test system architecture provided by the embodiment of the present invention is provided with an additional test circuit board with a digital wiring layer.
  • the phased array chip is mounted on the test circuit board, and the digital wiring layer is adapted to the phased array chip. Electrical connection is used to realize the transmission of digital signals of the phased array chip.
  • it is above the test circuit board and in electrical contact with the phased array chip, realizing the transmission of the radio frequency signal of the phased array chip.
  • the test instrument can be communicated with the RF probe and the test circuit board to achieve functional testing of the RF part and digital part of the phased array chip respectively.
  • the test circuit board has a simple structure and is easy to make, solving the problem of In the existing technology, phased array chip testing costs are high and functional verification is incomplete.
  • the present invention is based on the design of the test circuit board structure and is combined with the digital wiring layer to achieve complete functional testing of the phased array chip, with low cost, short production cycle, reliable structure, and simplified According to the requirements of the test environment and test equipment, only external test instruments are needed to realize the interconnection of the test platform and complete the corresponding tests.
  • the present invention can test the phased array chip more comprehensively, avoiding incomplete chip testing that may lead to potential use risks.
  • Figure 1 is a schematic structural diagram of the phased array chip testing system architecture provided by the present invention from a first perspective;
  • Figure 2 is a schematic structural diagram of the phased array chip testing system architecture provided by the present invention from a second perspective.
  • Icon 100-phased array chip test system architecture; 110-test circuit board; 111-digital wiring layer; 113-power supply line; 115-digital transmission line; 130-phased array chip; 131-conductive gold wire; 133- Conductive glue; 150-RF probe; 170-Digital signal processing module; 180-Power interface; 190-Digital interface.
  • the testing system for digital chips in the prior art is very mature, and there are many test solutions. However, it is mainly aimed at functional verification of digital chips.
  • the main test methods include probe card testing, built-in self-test, and FPGA testing. These methods are very suitable for digital chip testing and can quickly and accurately verify the performance of digital chips.
  • the above test solutions are difficult to verify their radio frequency functions and digital parts. They can only simply test the chip pad. Due to the interconnection between them, it is impossible to completely test whether the radio frequency function of the phased array chip is qualified, whether there are any problems in digital signal transmission, and it is impossible to provide reference data for chip function index optimization and mass production.
  • a low-frequency probe card or low-frequency needle when using a low-frequency probe card or low-frequency needle to test a phased array chip, for different chips, the pin positions are different, and the probe card needs to be customized.
  • a low-frequency probe card or low-frequency needle is used to supply power to the RF chip. If there is a relative deviation in the position, it is easy to cause some power supply pins to open circuit and the test cannot be completed normally.
  • the present invention provides a new phased array chip test system architecture. It should be noted that the features in the embodiments of the present invention can be combined with each other as long as there is no conflict.
  • this embodiment provides a phased array chip testing system architecture 100, which can implement testing of the phased array chip 130 and simultaneously implement the radio frequency and digital parts of the phased array chip 130.
  • the functional test can completely test whether the radio frequency function of the phased array chip 130 is qualified and whether there are problems with digital signal transmission, which solves the complex function verification problem of the phased array chip 130.
  • the cost is low and the production cycle is short, which simplifies the test environment and test equipment requirements. Only external test instruments are needed to realize the interconnection of the test platform and complete the corresponding tests.
  • the phased array chip testing system architecture 100 includes a test circuit board 110, a phased array chip 130, a radio frequency probe 150 and a digital signal processing module 170.
  • the phased array chip 130 is mounted on the test circuit board 110.
  • the radio frequency probe 150 is arranged above the test circuit board 110 and is used to make electrical contact with the phased array chip 130 to realize the transmission of radio frequency signals of the phased array chip 130 .
  • the test circuit board 110 is provided with a digital wiring layer 111
  • the phased array chip 130 is electrically connected to the digital wiring layer 111
  • the digital wiring layer 111 is used to realize the transmission of digital signals of the phased array chip 130 .
  • the digital signal processing module 170 is communicatively connected to the digital wiring layer 111 and is used to control the digital signals of the phased array chip 130 and implement digital signal testing of the phased array chip 130 .
  • the digital signal processing module 170 can be an FPGA module, using FPGA (Field Programmable Gate Array) to implement programming.
  • the FPGA module is used to connect to a central control computer and is used to process the register status of the phased array chip 130 Make settings.
  • the central control computer can be a conventional PC computer, which can realize related functions of programming, control and analysis.
  • the digital signal processing module 170 using FPGA in this embodiment is mainly composed of a digital logic processing unit.
  • the program is loaded into the FPGA to realize SPI digital signal communication of the FPGA, and realize The PC computer terminal inputs the code and controls the FPGA module to set the register status of the phased array chip 130 through the SPI protocol, thereby achieving corresponding functional test verification of the PC computer terminal controlling the phased array chip 130 .
  • the test environment is more reliable and the operation is relatively simpler.
  • the test circuit board 110 is provided with a mounting area for mounting the phased array chip 130 .
  • the phased array chip 130 is installed in the mounting area, and the phased array chip 130 is away from a side of the test circuit board 110 .
  • Several conductive gold wires 131 are provided on the side surface, and the conductive gold wires 131 are connected to the digital wiring layer 111 so that the phased array chip 130 is electrically connected to the digital wiring layer 111 .
  • the mounting area is located in the center area of the test circuit board 110.
  • the phased array chip 130 adopts the formal assembly process, with the back facing down, and its radio frequency and digital pins/pads (PAD) are all facing upward, and are bonded by gold wires. Through the process, a plurality of conductive gold wires 131 are formed to realize the electrical connection between the phased array chip 130 and the digital wiring layer 111.
  • PAD radio frequency and digital pins/pads
  • the test circuit board 110 is a PCB circuit board, which can design a digital circuit layer consistent with the position of the phased array chip 130 based on the position information of the PAD on the phased array chip 130.
  • the material of the conductive gold wire 131 may be copper and fixed by welding.
  • the material of the conductive gold wire 131 may also be silver or aluminum, which is not specifically limited here.
  • the phased array chip 130 is bonded to the mounting area through conductive adhesive 133 .
  • the phased array chip 130 is bonded to the test circuit board 110 through the conductive adhesive 133 at high temperature to realize the structural connection between the phased array chip 130 and the test circuit board 110, and through the gold wire bonding process,
  • the signal connection between different links of the phased array chip 130 is realized, and the electrical structural connection between the phased array chip 130 and the test circuit board 110 is realized through the gold wire bonding process.
  • the digital wiring layer 111 includes a power supply line 113 and a digital transmission line 115.
  • the test circuit board 110 is also provided with a power interface 180 and a digital interface 190.
  • the power interface 180 is provided at one end of the power supply line 113, and the other end of the power supply line 113 extends to the phase.
  • the control array chip 130 is electrically connected to the phased array chip 130 through a conductive gold wire 131;
  • the digital interface 190 is provided at one end of the digital transmission line 115, and the other end of the digital transmission line 115 extends to the phased array chip 130 and is connected to the phased array chip 130 through a conductive gold wire.
  • the gold wire 131 is electrically connected to the phased array chip 130, and the digital signal processing module 170 is communicatively connected to the digital interface 190.
  • the digital signal processing module 170 and the digital interface 190 are connected through SPI serial port communication. Specifically, the communication connection with the digital processing module is realized through the digital interface 190 provided by the test circuit board 110, and then the digital part function of the phased array chip 130 is controlled by the program, and finally the radio frequency probe 150 and the phased array chip 130 are connected. The RF input and output are connected to realize the construction of a complete phased array chip 130 test platform.
  • both the power supply line 113 and the digital transmission line 115 extend to the mounting area.
  • the end of the digital transmission line 115 away from the digital interface 190 is provided with digital pins.
  • the digital pins are connected to the phased array chip through the conductive gold wire 131 130 is electrically connected.
  • the power supply line 113 is provided with a power supply pin at one end away from the power interface.
  • the power supply pin is electrically connected to the phased array chip 130 through a conductive gold wire 131 .
  • both the power supply line 113 and the digital transmission line 115 can be adaptively designed according to the structural characteristics and positional characteristics of the phased array chip 130 .
  • the power supply line 113 and the digital transmission line 115 are divided into multiple links, and each link is electrically connected to the phased array chip 130 through at least one conductive gold wire 131.
  • each link is electrically connected to the phased array chip 130 through at least one conductive gold wire 131.
  • the power supply lines 113 are distributed on both sides of the mounting area, and the power supply pins are provided on both sides of the mounting area, and the ends of the two power supply lines 113 away from the mounting area are provided with power interfaces 180 .
  • the line power supply function can be better realized.
  • the test circuit board 110 can re-wire the power supply line 113 and the digital transmission line 115 on the test circuit board 110 according to the PAD distribution on the phased array chip 130 to meet the power supply requirements and digital transmission requirements of the phased array chip 130. Signal communication requirements, and provide corresponding power supply interfaces and digital communication interfaces to provide hardware support for subsequent testing.
  • the phased array chip 130 can be bonded to the test circuit board using conductive adhesive 133 at high temperature to ensure that the phased array chip 130 and the test circuit board are fully combined, and then a gold wire bonding machine is used to bond the phased array chip 130 to the test circuit board.
  • the GND (Ground), power supply and digital signal PAD of the chip 130 are bonded with the pin PAD of the line test board to ensure that the corresponding GND, power supply PAD and digital signal PAD on the phased array chip 130 and the test circuit board 110 Structurally connected to each other, the signals are transmitted from the test circuit board 110 to the phased array chip 130 .
  • the chip power supply and GND need to be structurally interconnected through gold wire bonding to achieve power supply for each radio frequency link.
  • the phased array chip testing system architecture 100 also includes a probe station (not shown).
  • the radio frequency probe 150 is set on the probe station.
  • the phased array chip 130 is provided with a radio frequency lead on the side away from the test circuit board 110.
  • the radio frequency probe 150 is driven by the probe station to move above the phased array chip 130 and make alignment contact with the radio frequency pins to realize radio frequency signal interconnection.
  • the radio frequency probe 150 mainly implements the radio frequency function test and verification of the phased array chip 130.
  • the influence of the cable and the radio frequency probe 150 on the radio frequency signal is removed through the calibration component, and the radio frequency probe is removed through the probe station.
  • 150 moves to the radio frequency input and output PAD corresponding to the chip to realize radio frequency signal interconnection, and is connected to the network analyzer through a cable to implement data collection and analysis of the radio frequency performance of the phased array chip 130.
  • the network analyzer here can also be connected to the central control computer to achieve overall control.
  • This embodiment mainly solves the problems of high testing cost and incomplete functional verification of the phased array chip 130.
  • the traditional testing method has the disadvantages of high cost, long cycle, high test environment requirements, poor stability, and difficulty in implementation.
  • This embodiment is based on the structural design of the test circuit board 110 and cleverly combines it with FPGA digital communication to realize the PC-side control test program and complete functional testing of the phased array chip 130 .
  • this embodiment makes full use of the existing PCB price advantage and short production cycle, and is relatively stable and mature with FPGA digital signal processing technology. The two are organically combined, thereby providing a stable and comprehensive test for performance verification of the phased array chip 130 method.
  • the phased array chip testing system architecture 100 mainly solves several problems of existing phased array chip 130 performance testing.
  • Cost and production cycle existing testing technologies, such as automated testing equipment testing, exploration Pin card testing and built-in self-testing have relatively high production costs and long production cycles, which greatly increase the cost and production time of chip production.
  • This embodiment solves this problem very well.
  • the PCB manufacturing process used to form the test circuit board 110 is mature and has a short production cycle, and can be completed within the chip tape-out cycle. At the same time, the bonding and gluing process between the phased array chip 130 and the test circuit board 110 is mature and reliable, and the production cost is greatly reduced. 2.
  • test environment equipment For automated test equipment testing, probe card testing, and built-in self-testing, professional equipment and instruments are generally required and can only be carried out in wafer processing plants or packaging plants.
  • This embodiment uses an organic combination of FPGA and PCB, which greatly simplifies the test environment and requirements for test equipment. Only a computer, probe station and cables are needed to interconnect the test platform and complete the corresponding test. 3.
  • Comprehensiveness of the test With the existing test method, the digital signal of the phased array chip 130 can only be simply tested, and the radio frequency performance of the phased array chip 130 cannot be fully and comprehensively tested. In this embodiment, communication with the FPGA is realized through the serial port through the test program on the computer side. Then, according to the digital signal protocol of the phased array chip 130, the corresponding function register information of the chip is sent to the corresponding register position of the chip to realize each phase of the phased array chip 130. Comprehensive functional verification avoids potential use risks caused by incomplete chip testing.
  • the phased array chip test system architecture 100 is provided with an additional test circuit board with a digital wiring layer 111.
  • the phased array chip 130 is mounted on the test circuit board 110, and the digital wiring layer 111 is connected to the phased array chip.
  • the array chip 130 is adapted for electrical connection and is used to realize the transmission of digital signals of the phased array chip 130 .
  • it is above the test circuit board 110 and is in electrical contact with the phased array chip 130, thereby realizing the transmission of radio frequency signals of the phased array chip 130.
  • the test instrument can be connected through communication with the radio frequency probe 150 and the test circuit board 110 to implement functional testing of the radio frequency part and the digital part of the phased array chip 130 respectively, and the test circuit board 110 has a simple structure and is easy to manufacture. It is convenient and solves the problems of high testing cost and incomplete functional verification of the phased array chip 130 in the existing technology.
  • This embodiment is based on the structural design of the test circuit board 110 and is combined with the digital wiring layer 111 to achieve complete functional testing of the phased array chip 130, with low cost, short production cycle, reliable structure, and at the same time simplifying the test environment and According to the test equipment requirements, only external test instruments are needed to realize the interconnection of the test platform and complete the corresponding tests.
  • the present invention tests the phased array chip 130 more comprehensively, thereby avoiding potential use risks caused by incomplete chip testing.

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Abstract

一种相控阵芯片（130）测试系统架构（100），涉及芯片测试技术领域，相控阵芯片（130）测试系统架构（100）包括测试电路板（110）、相控阵芯片（130）、射频探针（150）和数字信号处理模块（170），在实际测试时，可以将测试仪器与射频探针（150）和测试电路板（110）通信连接，从而分别实现对相控阵芯片（130）的射频部分和数字部分的功能测试。基于测试电路板（110）结构上的设计，与数字布线层（111）的结合，能够实现相控阵芯片（130）完整的功能测试，并且成本低廉、生产周期短，结构可靠，同时简化了测试环境和测试设备的要求，只需要外接测试仪器即可实现测试平台的互联，并完成相应的测试。此外，对相控阵芯片（130）的测试更加全面，避免芯片测试不全面，导致潜在的使用风险。

Description

相控阵芯片测试系统架构 技术领域
本发明涉及芯片测试技术领域，具体而言，涉及一种相控阵芯片测试系统架构。
背景技术
当前，集成电路产业快速发展，芯片制造，封装测试领域成为整个集成电路行业发展的重点，随着芯片集成度越来越高，越来越多相控阵芯片出现。后期对相控阵芯片测试的要求越来越复杂。目前现有芯片测试方案有多种，但是主要针对的是数字芯片的功能验证，相控阵芯片的测试方法市场上缺少完整的测试方案。经过发明人调研发现，现有的测试技术很难全面的对相控阵芯片，进行全方位的功能测试，所以迫切的需要一种新的测试方法，去解决相控阵芯片复杂功能验证。
发明内容
本发明的目的包括，例如，提供了一种相控阵芯片测试系统架构，其能够实现对相控阵芯片的测试，实现同时实现对相控阵芯片的射频和数字部分的功能测试，能够完整地测试相控阵芯片的射频功能是否合格，数字信号传输是否存在问题，解决了相控阵芯片的复杂功能验证问题。
本发明的实施例可以这样实现：
第一方面，本发明提供一种相控阵芯片测试系统架构，包括：
测试电路板；
相控阵芯片，所述相控阵芯片贴装在所述测试电路板上；
射频探针，所述射频探针设置在所述测试电路板上方，并用于与所述相控阵芯片电接触，以实现所述相控阵芯片的射频信号的传输；
其中，所述测试电路板上设置有数字布线层，所述相控阵芯片 与所述数字布线层电连接，所述数字布线层用于实现所述相控阵芯片的数字信号的传输。
在可选的实施方式中，所述相控阵芯片测试系统架构还包括数字信号处理模块，所述数字信号处理模块与所述数字布线层通信连接，用于控制所述相控阵芯片的数字信号，并实现对所述相控阵芯片的数字信号测试。
在可选的实施方式中，所述测试电路板上设置有用于贴装所述相控阵芯片的贴装区域，所述相控阵芯片正装在所述贴装区域，且所述相控阵芯片远离所述测试电路板的一侧表面设置有若干个导电金线，所述导电金线与所述数字布线层连接，以使所述相控阵芯片与所述数字布线层电连接。
在可选的实施方式中，所述数字布线层包括供电线路和数字传输线路，所述测试电路板上还设置有电源接口和数字接口，所述电源接口设置在所述供电线路的一端，所述供电线路的另一端延伸至所述相控阵芯片，并通过所述导电金线与所述相控阵芯片电连接；所述数字接口设置在所述数字传输线路的一端，所述数字传输线路的另一端延伸至所述相控阵芯片，并通过所述导电金线与所述相控阵芯片电连接，所述数字信号处理模块与所述数字接口通信连接。
在可选的实施方式中，所述供电线路和所述数字传输线路均延伸至所述贴装区域，所述数字传输线路远离所述数字接口的一端设置有数字引脚，所述数字引脚通过所述导电金线与所述相控阵芯片电连接，所述供电线路远离所述电源接口的一端设置有供电引脚，所述供电引脚通过所述导电金线与所述相控阵芯片电连接。
在可选的实施方式中，所述供电线路分布在所述贴装区域的两侧，且所述供电引脚设置在所述贴装区域的两侧，且两路所述供电线路远离所述贴装区域的端部均设置有所述电源接口。
在可选的实施方式中，所述数字信号处理模块与所述数字接口之间通过SPI串口通信连接。
在可选的实施方式中，所述相控阵芯片通过导电胶粘接在所述 贴装区域。
在可选的实施方式中，所述数字信号处理模块为FPGA模块，所述FPGA模块用于与一中控电脑连接，并用于对所述相控阵芯片的寄存器状态进行设置。
在可选的实施方式中，所述相控阵芯片测试系统架构还包括探针台，所述射频探针设置在所述探针台上，所述相控阵芯片远离所述测试电路板的一侧设置有射频引脚，所述射频探针用于在所述探针台的驱动下移动至所述相控阵芯片上方并与所述射频引脚对位接触，以实现射频信号互联。
本发明实施例的有益效果包括，例如：
本发明实施例提供的相控阵芯片测试系统架构，通过额外设置带有数字布线层的测试线路板，相控阵芯片贴装在测试电路板上，且数字布线层与相控阵芯片适配电连，用于实现相控阵芯片的数字信号的传输。同时在测试电路板上方，并与相控阵芯片电接触，实现了相控阵芯片的射频信号的传输。在实际测试时，可以将测试仪器与射频探针和测试电路板通信连接，从而分别实现对相控阵芯片的射频部分和数字部分的功能测试，且测试电路板结构简单，制作方便，解决了现有技术中相控阵芯片测试成本高、功能验证不全的问题。相较于现有技术，本发明基于测试电路板结构上的设计，与数字布线层的结合，能够实现相控阵芯片完整的功能测试，并且成本低廉、生产周期段，结构可靠，同时简化了测试环境和测试设备的要求，只需要外接测试仪器即可实现测试平台的互联，并完成相应的测试。此外，本发明对相控阵芯片的测试更加全面，避免芯片测试不全面，导致潜在的使用风险。
附图说明
为了更清楚地说明本发明实施例的技术方案，下面将对实施例中所需要使用的附图作简单地介绍，应当理解，以下附图仅示出了本发明的某些实施例，因此不应被看作是对范围的限定，对于本领域普 通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他相关的附图。
图1为本发明提供的相控阵芯片测试系统架构在第一视角下的结构示意图；
图2为本发明提供的相控阵芯片测试系统架构在第二视角下的结构示意图。
图标：100-相控阵芯片测试系统架构；110-测试电路板；111-数字布线层；113-供电线路；115-数字传输线路；130-相控阵芯片；131-导电金线；133-导电胶；150-射频探针；170-数字信号处理模块；180-电源接口；190-数字接口。
具体实施方式
为使本发明实施例的目的、技术方案和优点更加清楚，下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本发明一部分实施例，而不是全部的实施例。通常在此处附图中描述和示出的本发明实施例的组件可以以各种不同的配置来布置和设计。
因此，以下对在附图中提供的本发明的实施例的详细描述并非旨在限制要求保护的本发明的范围，而是仅仅表示本发明的选定实施例。基于本发明中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
应注意到：相似的标号和字母在下面的附图中表示类似项，因此，一旦某一项在一个附图中被定义，则在随后的附图中不需要对其进行进一步定义和解释。
在本发明的描述中，需要说明的是，若出现术语“上”、“下”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，或者是该发明产品使用时惯常摆放的方位或位置关系，仅是为了便于描述本发明和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为 对本发明的限制。
此外，若出现术语“第一”、“第二”等仅用于区分描述，而不能理解为指示或暗示相对重要性。
正如背景技术中所公开的，现有技术中针对数字芯片的测试系统十分成熟，测试方案有多种，然而，其主要是针对数字芯片的功能验证。
参考一些数字芯片测试，主要测试方法有探针卡测试，内建自测试，FPGA测试。这些方法对于数字芯片测试很适用，能够快速准确的验证数字芯片的性能，但是对相控阵芯片而言，以上的测试方案，难以验证其射频功能和数字部分，只能简单的测试芯片pad之间的互联性，无法完整的测试相控阵芯片的射频功能是否合格，数字信号传输是否存在问题，无法给芯片功能指标优化和批量生产给出参考数据。
例如，当使用低频探针卡或低频针测试相控阵芯片对于不同的芯片，引脚位置不同，探针卡需要定制。在测试过程中，使用低频探针卡或低频针实现射频芯片的供电，如果位置出现相对的偏移，容易导致部分供电引脚开路，无法正常的完成测试。
针对上述问题，本发明提供了一种新型的相控阵芯片测试系统架构，需要说明的是，在不冲突的情况下，本发明的实施例中的特征可以相互结合。
具体实施例
结合参见图1和图2，本实施例提供了一种相控阵芯片测试系统架构100，其能够实现对相控阵芯片130的测试，实现同时实现对相控阵芯片130的射频和数字部分的功能测试，能够完整地测试相控阵芯片130的射频功能是否合格，数字信号传输是否存在问题，解决了相控阵芯片130的复杂功能验证问题。同时成本低廉、制作周期短，简化了测试环境和测试设备的要求，只需要外接测试仪器即可实现测试平台的互联，并完成相应的测试。
本实施例提供的相控阵芯片测试系统架构100，包括测试电路板110、相控阵芯片130、射频探针150和数字信号处理模块170，相控 阵芯片130贴装在测试电路板110上，射频探针150设置在测试电路板110上方，并用于与相控阵芯片130电接触，以实现相控阵芯片130的射频信号的传输。其中，测试电路板110上设置有数字布线层111，相控阵芯片130与数字布线层111电连接，数字布线层111用于实现相控阵芯片130的数字信号的传输。数字信号处理模块170与数字布线层111通信连接，用于控制相控阵芯片130的数字信号，并实现对相控阵芯片130的数字信号测试。
在本实施例中，数字信号处理模块170可以是FPGA模块，应用FPGA(Field Programmable Gate Array)来实现编程，FPGA模块用于与一中控电脑连接，并用于对相控阵芯片130的寄存器状态进行设置。其中，该中控电脑可以是常规的PC端电脑，能够实现编程、控制和分析的相关功能。
需要说明的是，本实施例中的应用FPGA的数字信号处理模块170，主要是由数字逻辑处理单元构成，通过程序代码编程，将程序加载到FPGA里，实现FPGA的SPI数字信号通信，并实现PC电脑端输入代码，控制FPGA模块通过SPI协议对相控阵芯片130的寄存器状态进行设置，从而达到PC电脑端控制相控阵芯片130的相应功能测试验证。对比于传统的数字信号测试，测试环境更可靠，相对操作也更简单。
在本实施例中，测试电路板110上设置有用于贴装相控阵芯片130的贴装区域，相控阵芯片130正装在贴装区域，且相控阵芯片130远离测试电路板110的一侧表面设置有若干个导电金线131，导电金线131与数字布线层111连接，以使相控阵芯片130与数字布线层111电连接。具体地，贴装区域位于测试电路板110的中心区域，相控阵芯片130采用正装工艺，背面朝下，其射频、数字引脚/焊盘(PAD)均朝上设置，通过金丝键合工艺，形成了多个导电金线131，实现了相控阵芯片130与数字布线层111之间的电连接。
需要说明的是，本实施例中测试电路板110为PCB电路板，其可以根据相控阵芯片130上PAD的位置信息来设计符合相控阵芯片 130位置的数字线路层。此外，本实施例中导电金线131的材料可以是铜，并通过焊接方式实现固定，当然，此处导电金线131的材料也可以是银或者铝等，在此不作具体限定。
在本实施例中，相控阵芯片130通过导电胶133粘接在贴装区域。具体地，将相控阵芯片130通过导电胶133，与测试电路板110在高温下实现粘合，实现相控阵芯片130与测试电路板110结构上的连接，并且通过金丝键合工艺，实现相控阵芯片130不同链路之间的信号连接，同时通过金丝键合工艺，实现相控阵芯片130与测试电路板110之间电气结构连接。
数字布线层111包括供电线路113和数字传输线路115，测试电路板110上还设置有电源接口180和数字接口190，电源接口180设置在供电线路113的一端，供电线路113的另一端延伸至相控阵芯片130，并通过导电金线131与相控阵芯片130电连接；数字接口190设置在数字传输线路115的一端，数字传输线路115的另一端延伸至相控阵芯片130，并通过导电金线131与相控阵芯片130电连接，数字信号处理模块170与数字接口190通信连接。
在本实施例中，数字信号处理模块170与数字接口190之间通过SPI串口通信连接。具体地，通过测试电路板110提供的数字接口190实现与数字处理模块之间的通信连接，进而实现程序控制相控阵芯片130的数字部分功能，最终通过射频探针150与相控阵芯片130的射频输入输出相连接，实现了完整的相控阵芯片130测试平台搭建。
在本实施例中，供电线路113和数字传输线路115均延伸至贴装区域，数字传输线路115远离数字接口190的一端设置有数字引脚，数字引脚通过导电金线131与相控阵芯片130电连接，供电线路113远离电源接口的一端设置有供电引脚，供电引脚通过导电金线131与相控阵芯片130电连接。具体地，此处供电线路113和数字传输线路115均可以根据相控阵芯片130的结构特性和位置特性进行适应性设计。
需要说明的是，本实施例中供电线路113和数字传输线路115均分为多个链路，且每个链路都通过至少一个导电金线131与相控阵 芯片130实现电连接，通过合理分配导电金线131的位置，能够提高相控阵芯片130的通道测试数量，保证相控阵芯片130全部射频链路和设计功能都可以完成测试。
在本实施例中，供电线路113分布在贴装区域的两侧，且供电引脚设置在贴装区域的两侧，且两路供电线路113远离贴装区域的端部均设置有电源接口180。通过设置两路供电线路113，能够更好地实现线路供电功能。
需要说明的是，测试电路板110可以根据相控阵芯片130上的PAD分布，重新在测试电路板110上对供电线路113和数字传输线路115进行布线，满足相控阵芯片130供电要求和数字信号通信要求，并提供相应的电源电源接口和数字通信接口，为后续测试提供硬件支撑。在组装时，可以将相控阵芯片130使用导电胶133高温与测试线路板粘接，保证相控阵芯片130与测试线路板之间充分结合，之后使用金丝键合机，将相控阵芯片130的GND(Ground)、电源和数字信号的PAD与线路测试板的引脚PAD金丝键合，保证相控阵芯片130与测试电路板110上的对应的GND、电源PAD，数字信号PAD结构上互相连接，实现信号从测试电路板110到相控阵芯片130的传输。为了保证芯片各个链路都能测试到，需要将芯片电源和GND通过金丝键合，实现结构上互连，从而实现每个射频链路供电。
进一步地，相控阵芯片测试系统架构100还包括探针台(图未示)，射频探针150设置在探针台上，相控阵芯片130远离测试电路板110的一侧设置有射频引脚，射频探针150用于在探针台的驱动下移动至相控阵芯片130上方并与射频引脚对位接触，以实现射频信号互联。
在本实施例中，射频探针150主要是实现相控阵芯片130的射频功能测试验证，通过校准件把线缆和射频探针150对射频信号影响去除，并通过探针台将射频探针150移动到芯片对应的射频输入输出PAD，实现射频信号互联，通过线缆连接到网络分析仪，实现对相控阵芯片130射频性能进行数据采集分析。需要说明的是，此处网络分析仪也可以与中控电脑连接，从而实现整体的控制。
本实施例主要解决相控阵芯片130测试成本高，功能验证不全的问题，传统的测试方法存在成本高，周期长，测试环境要求高，稳定度差，难以实现的缺点。本实施例基于测试电路板110结构上的设计，与FPGA数字通信巧妙的结合，实现PC电脑端控制测试程序，实现相控阵芯片130完整的功能测试。同时本实施例充分利用现有PCB价格优势和生产周期短，与FPGA数字信号处理技术相对稳定成熟，两者之间有机结合，从而提供了一种稳定全面的相控阵芯片130性能验证的测试方法。
本实施例提供的相控阵芯片测试系统架构100，主要解决了现有相控阵芯片130性能测试几个问题，一、成本制作周期方面：现有的测试技术，如自动化测试设备测试，探针卡测试，内建自测试，相对的制作成本比较高，生产周期比较长，大大增加芯片生产的成本和生产时间。本实施例很好的解决了这一问题，用于形成测试电路板110的PCB制作工艺成熟生产周期短，可在芯片流片周期内完成。同时相控阵芯片130与测试电路板110之间的键合和胶接工艺成熟可靠，生产成本大大降低。二、对测试环境设备要求：对于自动化测试设备测试，探针卡测试，内建自测试，一般需要专业设备仪器，在晶圆加工厂或封装厂才能进行。本实施例采用FPGA与PCB有机结合，大大简化测试环境和对测试设备的要求，只需要一台电脑、探针台和线缆即可实现测试平台的互联，就可以完成相应的测试。三、测试的全面性：对于现有的测试方法，只能简单的测试相控阵芯片130数字信号的测试，无法对相控阵芯片130的射频性能有一个完整全面的测试。本实施例通过电脑端的测试程序，通过串口实现与FPGA通信，之后根据相控阵芯片130的数字信号协议，将芯片对应的功能寄存器信息，发送到芯片对应寄存器位置，实现相控阵芯片130各个功能全面的验证，避免芯片测试不全面，导致潜在的使用风险。
综上所述，相控阵芯片测试系统架构100，通过额外设置带有数字布线层111的测试线路板，相控阵芯片130贴装在测试电路板110上，且数字布线层111与相控阵芯片130适配电连，用于实现相控阵芯 片130的数字信号的传输。同时在测试电路板110上方，并与相控阵芯片130电接触，实现了相控阵芯片130的射频信号的传输。在实际测试时，可以将测试仪器与射频探针150和测试电路板110通信连接，从而分别实现对相控阵芯片130的射频部分和数字部分的功能测试，且测试电路板110结构简单，制作方便，解决了现有技术中相控阵芯片130测试成本高、功能验证不全的问题。本实施例基于测试电路板110结构上的设计，与数字布线层111的结合，能够实现相控阵芯片130完整的功能测试，并且成本低廉、生产周期段，结构可靠，同时简化了测试环境和测试设备的要求，只需要外接测试仪器即可实现测试平台的互联，并完成相应的测试。此外，本发明对相控阵芯片130的测试更加全面，避免芯片测试不全面，导致潜在的使用风险。
以上所述，仅为本发明的具体实施方式，但本发明的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本发明揭露的技术范围内，可轻易想到的变化或替换，都应涵盖在本发明的保护范围之内。因此，本发明的保护范围应以所述权利要求的保护范围为准。

Claims (10)

  1. 一种相控阵芯片测试系统架构，其特征在于，包括：
    测试电路板；
    相控阵芯片，所述相控阵芯片贴装在所述测试电路板上；
    射频探针，所述射频探针设置在所述测试电路板上方，并用于与所述相控阵芯片电接触，以实现所述相控阵芯片的射频信号的传输；
    其中，所述测试电路板上设置有数字布线层，所述相控阵芯片与所述数字布线层电连接，所述数字布线层用于实现所述相控阵芯片的数字信号的传输。
  2. 根据权利要求1所述的相控阵芯片测试系统架构，其特征在于，所述相控阵芯片测试系统架构还包括数字信号处理模块，所述数字信号处理模块与所述数字布线层通信连接，用于控制所述相控阵芯片的数字信号，并实现对所述相控阵芯片的数字信号测试。
  3. 根据权利要求2所述的相控阵芯片测试系统架构，其特征在于，所述测试电路板上设置有用于贴装所述相控阵芯片的贴装区域，所述相控阵芯片正装在所述贴装区域，且所述相控阵芯片远离所述测试电路板的一侧表面设置有若干个导电金线，所述导电金线与所述数字布线层连接，以使所述相控阵芯片与所述数字布线层电连接。
  4. 根据权利要求3所述的相控阵芯片测试系统架构，其特征在于，所述数字布线层包括供电线路和数字传输线路，所述测试电路板上还设置有电源接口和数字接口，所述电源接口设置在所述供电线路的一端，所述供电线路的另一端延伸至所述相控阵芯片，并通过所述导电金线与所述相控阵芯片电连接；所述数字接口设置在所述数字传输线路的一端，所述数字传输线路的另一端延伸至所述相控阵芯片，并通过所述导电金线与所述相控阵芯片电连接，所述数字信号处理模块与 所述数字接口通信连接。
  5. 根据权利要求4所述的相控阵芯片测试系统架构，其特征在于，所述供电线路和所述数字传输线路均延伸至所述贴装区域，所述数字传输线路远离所述数字接口的一端设置有数字引脚，所述数字引脚通过所述导电金线与所述相控阵芯片电连接，所述供电线路远离所述电源接口的一端设置有供电引脚，所述供电引脚通过所述导电金线与所述相控阵芯片电连接。
  6. 根据权利要求5所述的相控阵芯片测试系统架构，其特征在于，所述供电线路分布在所述贴装区域的两侧，且所述供电引脚设置在所述贴装区域的两侧，且两路所述供电线路远离所述贴装区域的端部均设置有所述电源接口。
  7. 根据权利要求4所述的相控阵芯片测试系统架构，其特征在于，所述数字信号处理模块与所述数字接口之间通过SPI串口通信连接。
  8. 根据权利要求3所述的相控阵芯片测试系统架构，其特征在于，所述相控阵芯片通过导电胶粘接在所述贴装区域。
  9. 根据权利要求2所述的相控阵芯片测试系统架构，其特征在于，所述数字信号处理模块为FPGA模块，所述FPGA模块用于与一中控电脑连接，并用于对所述相控阵芯片的寄存器状态进行设置。
  10. 根据权利要求2所述的相控阵芯片测试系统架构，其特征在于，所述相控阵芯片测试系统架构还包括探针台，所述射频探针设置在所述探针台上，所述相控阵芯片远离所述测试电路板的一侧设置有射频引脚，所述射频探针用于在所述探针台的驱动下移动至所述相控阵芯片上方并与所述射频引脚对位接触，以实现射频信号互联。
PCT/CN2022/104095 2022-05-20 2022-07-06 相控阵芯片测试系统架构 WO2023221265A1 (zh)

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