WO2023220968A1 - 一种芯片及其制备方法、电子设备 - Google Patents

一种芯片及其制备方法、电子设备 Download PDF

Info

Publication number
WO2023220968A1
WO2023220968A1 PCT/CN2022/093575 CN2022093575W WO2023220968A1 WO 2023220968 A1 WO2023220968 A1 WO 2023220968A1 CN 2022093575 W CN2022093575 W CN 2022093575W WO 2023220968 A1 WO2023220968 A1 WO 2023220968A1
Authority
WO
WIPO (PCT)
Prior art keywords
conductive
layer
dielectric layer
contact hole
stacked
Prior art date
Application number
PCT/CN2022/093575
Other languages
English (en)
French (fr)
Inventor
范荣伟
林军
胡成仕
Original Assignee
华为技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to PCT/CN2022/093575 priority Critical patent/WO2023220968A1/zh
Publication of WO2023220968A1 publication Critical patent/WO2023220968A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics

Definitions

  • the present application relates to the field of semiconductor technology, and in particular to a chip and its preparation method, and electronic equipment.
  • a chip in the related art, includes a substrate, and a transfer layer and a rewiring layer stacked on the substrate.
  • the transfer layer includes a first dielectric layer and a second dielectric layer stacked on the substrate.
  • the conductive pattern is a conductive pillar penetrating the second dielectric layer, wherein the conductive pillar is electrically connected to the conductive pattern.
  • Embodiments of the present application provide a chip, its preparation method, and electronic equipment, aiming to improve the stability of the interconnection between the conductive pillars and the conductive patterns in the chip, so as to improve the reliability of the chip.
  • a chip in a first aspect, is provided.
  • the chip may be a bare chip or a packaged chip, which includes a first conductive pattern, a stacked layer and a conductive pillar, wherein the first conductive pattern includes, for example, a conductive pattern prepared by a mid-stage process. At least one layer of conductive pattern.
  • the stacked layer includes a plurality of dielectric layers prepared in an intermediate process, for example, at least one first dielectric layer and at least one second dielectric layer that are sequentially stacked on the first conductive pattern.
  • the conductive pillar may be, for example, a conductive structure prepared in an intermediate process. The conductive pillar penetrates the stacked layer and has one end electrically connected to the first conductive pattern.
  • the conductive pillar includes at least one first conductive part and at least one second conductive part that are connected, the first conductive part penetrates the first dielectric layer, and the second conductive part penetrates the second dielectric layer.
  • the end surface of the first conductive part connected to the second conductive part is the first end surface of the first conductive part
  • the end surface of the second conductive part connected to the first conductive part is the second end surface of the second conductive part
  • the second end surface is on the reference surface
  • the orthographic projection on is located within the orthographic projection range of the first end surface on the reference plane, which is the plane where the surface of the side of the first conductive pattern close to the stacked layer is located.
  • the shape of the conductive pillar is designed so that the orthogonal projection of the second end surface of the second conductive part on the reference plane is located at the orthogonal projection of the first end surface of the first conductive part on the reference plane.
  • the edge of the first end surface exceeds the edge of the second end surface, causing the side surface of the first conductive part to protrude relative to the side surface of the second conductive part.
  • the end of the conductive pillar away from the first conductive pattern is polished. Even if the polishing fluid penetrates along the gap between the second conductive part and the second dielectric layer, the end of the first end surface exceeds the edge of the second end surface.
  • the part can also prevent the grinding liquid from continuing to penetrate, preventing the grinding liquid from contacting and corroding the first conductive pattern, thereby ensuring the stability of the interconnection between the conductive pillar and the first conductive pattern, and improving the reliability of the chip.
  • the end of the conductive pillar away from the first conductive pattern will generate a torque due to friction, and the conductive pillar will move in the stacked layer, or even come out of the stacked layer.
  • the part of the first end face that extends beyond the edge of the second end face offsets the second dielectric layer, which can limit the movement of the conductive pillar, thereby preventing the conductive pillar from coming out of the stacked layer and avoiding reliability problems in the chip. .
  • the stacked layer has a contact hole
  • the contact hole includes at least one first sub-contact hole and at least one second sub-contact hole that are connected
  • the first sub-contact hole penetrates the first dielectric layer
  • the second sub-contact hole The hole penetrates the second dielectric layer.
  • the first conductive part is located in the first sub-contact hole
  • the second conductive part is located in the second sub-contact hole.
  • the opening connecting the first sub-contact hole and the second sub-contact hole is the first opening of the first sub-contact hole
  • the opening connecting the second sub-contact hole and the first sub-contact hole is the second opening of the second sub-contact hole.
  • the orthographic projection of the second opening on the reference plane is within the orthographic projection range of the first opening on the reference plane.
  • the arrangement in the above embodiment is to design the shape of the contact hole in the stacked layer so that the orthographic projection of the second opening of the second sub-contact hole on the reference plane is located, and the first opening of the first sub-contact hole is located on the reference plane.
  • the edge of the first opening exceeds the edge of the second opening, and the side wall of the first sub-contact hole is further away from the side wall of the second sub-contact hole.
  • the axis of the conductive pillar, the side wall of the first sub-contact hole and the side wall of the second sub-contact hole are not in the same plane.
  • the material of the first dielectric layer is different from the material of the second dielectric layer.
  • the etching selectivity ratio of the first dielectric layer and the second dielectric layer can be adjusted by setting the material of the first dielectric layer 21 to be different from the material of the second dielectric layer 23 to satisfy the requirement of the first dielectric layer.
  • the etching rate of the second dielectric layer is much greater than the etching rate of the second dielectric layer.
  • the first dielectric layer is etched without etching the second dielectric layer, so that the first dielectric layer is etched.
  • the side wall of the contact hole is further away from the axis of the conductive pillar than the side wall of the second sub-contact hole.
  • the etching rate of the first dielectric layer is different from the etching rate of the second dielectric layer.
  • the setting method in the above embodiment can adjust the etching selectivity ratio of the first dielectric layer and the second dielectric layer to satisfy that the etching rate of the first dielectric layer is much greater than the etching rate of the second dielectric layer. For example, by Adjust the etching selectivity ratio between the two so that the first dielectric layer is etched without etching the second dielectric layer, so that the side walls of the first sub-contact hole are farther away from the conductive side than the side walls of the second sub-contact hole.
  • the axis of the column can adjust the etching selectivity ratio of the first dielectric layer and the second dielectric layer to satisfy that the etching rate of the first dielectric layer is much greater than the etching rate of the second dielectric layer.
  • the material of the first dielectric layer and the second dielectric layer is any of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxynitride, nitrogen-doped carbide, and oxygen-doped carbide. Two kinds.
  • the arrangement method in the above embodiment only needs to ensure that the materials of the first dielectric layer and the second dielectric layer are different.
  • the stacked layer includes a first dielectric layer and a second dielectric layer
  • the conductive pillar includes a first conductive portion and a second conductive portion
  • the conductive pillar is provided with a first conductive part and a second conductive part, so that the edge of the first end surface of the first conductive part exceeds the edge of the second end surface of the second conductive part.
  • the stacked layer includes a plurality of first dielectric layers and a plurality of second dielectric layers that are alternately arranged
  • the conductive pillars include a plurality of first conductive portions and a plurality of second conductive portions that are alternately connected.
  • the conductive pillar by arranging the conductive pillar to have a plurality of first conductive parts and a plurality of second conductive parts, during the process of grinding the conductive pillar, the first end surface of the plurality of first conductive parts connected to the second conductive part above them , can prevent the grinding fluid from continuing to penetrate, further reduce the risk of the grinding fluid penetrating, and prevent the grinding fluid from contacting and corroding the first conductive pattern, thereby further improving the reliability of the chip.
  • the end of the conductive pillar away from the first conductive pattern will generate a torque due to friction, and the conductive pillar will move in the stacked layer, or even come out of the stacked layer.
  • the shape of the conductive pillars is similar to a thread structure, and the first end surfaces of the plurality of first conductive parts offset the plurality of second dielectric layers. Further restricting the movement of the conductive pillars can prevent the conductive pillars from coming out of the stacked layers and avoid reliability problems in the chip.
  • the average diameter of the first conductive portion is greater than the average diameter of the second conductive portion.
  • the end where the first conductive part is connected to the second conductive part is smaller than the end where the second conductive part is connected to the first conductive part.
  • One end protrudes. In this way, during the process of grinding the conductive pillar, the protruding end of the first conductive part can prevent the grinding fluid from continuing to penetrate downward, preventing the grinding fluid from contacting and corroding the first conductive pattern.
  • the stacked layer further includes a third dielectric layer located between the first conductive pattern and the first dielectric layer closest to the first conductive pattern.
  • the conductive pillar also includes a third conductive part that penetrates the third dielectric layer and is electrically connected to the first conductive part closest to the first conductive pattern.
  • the end surface connecting the first conductive part and the third conductive part is the third end surface
  • the end surface connecting the third conductive part and the first conductive part is the fourth end surface
  • the orthographic projection of the fourth end surface on the reference plane is located on the third end surface. Within the orthographic projection of the reference plane.
  • the diameter change trend of the conductive pillars is small, large, small, large.
  • the material of the third dielectric layer is the same as the material of the second dielectric layer.
  • the etching rate of the third dielectric layer is the same as the etching rate of the second dielectric layer.
  • the stacked layer has a contact hole
  • the conductive pillar is located in the contact hole
  • the shape of the side of the conductive pillar matches the shape of the side wall of the contact hole.
  • the arrangement in the above embodiment is conducive to reducing the gap between the side surfaces of the conductive pillars and the side walls of the contact holes. During the process of grinding the conductive pillars, the flow of the grinding liquid along the gaps between the conductive pillars and the contact holes can be improved. seepage problem.
  • the shape of the first conductive part is a cylinder or a truncated cone
  • the shape of the second conductive part is a cylinder or a truncated cone
  • the chip further includes a second conductive pattern disposed on a side of the stacked layer away from the first conductive pattern. One end of the conductive pillar away from the first conductive pattern is electrically connected to the second conductive pattern.
  • the interconnection and signal transmission between the first conductive pattern and the second conductive pattern are realized through the conductive pillars.
  • a method of manufacturing a chip includes: forming a first conductive pattern.
  • a stacked layer is formed on the first conductive pattern, and the stacked layer includes at least one first dielectric layer and at least one second dielectric layer that are stacked in sequence.
  • the conductive pillar includes at least one first conductive part and at least one second conductive part that are connected, and the first conductive part penetrates the first dielectric layer,
  • the second conductive part penetrates the second dielectric layer.
  • the end surface where the first conductive part is connected to the second conductive part is the first end surface
  • the end surface where the second conductive part is connected to the first conductive part is the second end surface
  • the orthographic projection of the second end surface on the reference plane is located on the first end surface.
  • the orthogonal projection of the second end surface of the second conductive part on the reference plane of the conductive pillar prepared is located at the orthogonal projection of the first end surface of the first conductive part on the reference surface.
  • the edge of the first end surface exceeds the edge of the second end surface, causing the side surface of the first conductive part to protrude relative to the side surface of the second conductive part.
  • the portion of the first end surface beyond the edge of the second end surface can prevent the grinding fluid from continuing to penetrate. , to prevent the polishing liquid from contacting and corroding the first conductive pattern, thereby ensuring the stability of the interconnection between the conductive pillar and the first conductive pattern, and improving the reliability of the chip.
  • the end of the conductive pillar away from the first conductive pattern will generate a torque due to friction, and the conductive pillar will move in the stacked layer, or even come out of the stacked layer.
  • the portion of the first end surface beyond the edge of the second end surface offsets the second dielectric layer, which can limit the movement of the conductive pillars, thereby preventing the conductive pillars from coming out of the stacked layer and avoiding reliability problems in the chip.
  • forming the conductive pillar penetrating the stacked layer includes forming a contact hole penetrating the stacked layer. Fill the contact hole with conductive material to form a conductive pillar.
  • a selective deposition process can be used to fill the contact holes with conductive material, which can avoid the occurrence of voids inside the conductive material in the contact holes, thereby avoiding the occurrence of voids inside the initial conductive pillars.
  • the stack of layers includes a first dielectric layer and a second dielectric layer.
  • Forming a contact hole penetrating the stacked layer includes: forming a mask layer, and the mask layer is located on the stacked layer. Based on the mask layer, the second dielectric layer is etched to form a preformed hole penetrating the second dielectric layer. Remove the mask layer. The first dielectric layer is etched through the preformed hole to expose the first conductive pattern.
  • a contact hole is formed through the stacked layer.
  • a stripping liquid is used to remove the mask layer, and then the first dielectric layer is etched to expose the first conductive pattern, thereby preventing the stripping liquid from contacting and corroding the first conductive pattern.
  • the stacked layers include a plurality of first dielectric layers and a plurality of second dielectric layers that are alternately arranged, and the first dielectric layer among the plurality of first dielectric layers that is closest to the first conductive pattern is the first dielectric layer.
  • Forming a contact hole penetrating the stacked layer includes: forming a mask layer, and the mask layer is located on the stacked layer. Based on the mask layer, the target film layer of the stacked layer is etched to form a preformed hole penetrating the target film layer; the target film layer is the film layer located above the set first dielectric layer in the stacked layer. Through the preformed hole, the first dielectric layer in the target film layer is etched close to the side of the preformed hole to form a groove. Remove the mask layer. The first dielectric layer is etched through the preformed hole to expose the first conductive pattern.
  • the stacked layer when the stacked layer includes a plurality of first dielectric layers and a plurality of second dielectric layers that are alternately arranged, contact holes are formed through the stacked layer.
  • a stripping liquid is used to remove the mask layer, and then etching and setting the first dielectric layer to expose the first conductive pattern can prevent the stripping liquid from contacting and corroding the first conductive pattern.
  • the method further includes: forming a protective layer, and the protective layer covers the stacked layer.
  • a sacrificial layer is formed, and the sacrificial layer covers the protective layer.
  • the portions of the sacrificial layer, the protective layer and the stacked layer away from the first conductive pattern are ground to expose the ends of the conductive pillars away from the first conductive pattern.
  • the sacrificial layer, the protective layer and the portion of the stacked layer on the side away from the first conductive pattern will be removed, exposing the end of the conductive pillar away from the first conductive pattern, and grinding can make the stacked layer
  • the surface on the side away from the first conductive pattern is planarized to facilitate the subsequent preparation of a second conductive pattern on the surface of the stacked layer.
  • the protective layer can block the polishing liquid and prevent the polishing liquid from seeping down from the gap between the conductive pillar and the contact hole, thereby preventing the polishing liquid from contacting and corroding the first conductive pattern.
  • the method further includes: forming a second conductive pattern, the second conductive pattern is located on the stacked layer, and an end of the conductive pillar away from the first conductive pattern is electrically connected to the second conductive pattern.
  • the interconnection and signal transmission between the first conductive pattern and the second conductive pattern are realized through the conductive pillars.
  • an electronic device is provided.
  • the electronic device is, for example, a consumer electronic product, a household electronic product, a vehicle-mounted electronic product, a financial terminal product, or a communication electronic product.
  • the electronic device includes a circuit board and the chip described in any of the above embodiments, and the chip is electrically connected to the circuit board.
  • Figure 1 is a structural diagram of an electronic device according to some embodiments.
  • Figure 2 is a structural diagram of a chip in the related art
  • Figure 3 is a structural diagram of a chip according to some embodiments.
  • Figures 4A to 4J are diagrams of steps for preparing a chip according to some embodiments.
  • Figure 5 is a structural diagram of another chip according to some embodiments.
  • Figure 6 is a partial enlarged view of the chip in Figure 5 at position M;
  • Figure 7 is a structural diagram of yet another chip according to some embodiments.
  • Figure 8 is a partial enlarged view of the chip in Figure 7 at position N;
  • Figure 9 is a schematic diagram of grinding a conductive pillar according to some embodiments.
  • Figure 10 is a structural diagram of yet another chip according to some embodiments.
  • Figures 11A to 11E are flow charts for preparing a chip according to some embodiments.
  • Figures 12A to 12K are diagrams of steps for preparing a chip according to some embodiments.
  • Figures 13A to 13E are flow charts for preparing another chip according to some embodiments.
  • Figures 14A to 14L are diagrams of steps for preparing another chip according to some embodiments.
  • first and second are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the quantity of indicated technical features. Therefore, features defined as “first” and “second” may explicitly or implicitly include one or more of these features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.
  • a and/or B includes the following three combinations: A only, B only, and a combination of A and B.
  • Example embodiments are described herein with reference to cross-sectional illustrations and/or plan views that are idealized illustrations.
  • the thickness of layers and regions are exaggerated for clarity. Accordingly, variations from the shapes in the drawings due, for example, to manufacturing techniques and/or tolerances are contemplated.
  • example embodiments should not be construed as limited to the shapes of regions illustrated herein but are to include deviations in shapes that result from, for example, manufacturing. For example, an etched area shown as a rectangle will typically have curved features. Accordingly, the regions shown in the figures are schematic in nature and their shapes are not intended to illustrate the actual shapes of regions of the device and are not intended to limit the scope of the exemplary embodiments.
  • the electronic equipment is, for example, consumer electronic products, household electronic products, vehicle-mounted electronic products, financial terminal products, and communication electronic products.
  • consumer electronic products include mobile phones, tablets, laptops, e-readers, personal computers (PCs), personal digital assistants (Personal Digital Assistants, PDAs), desktop monitors, smart wearable products (such as smart phones, etc.) Watches, smart bracelets), virtual reality (Virtual Reality, VR) terminal equipment, augmented reality (Augmented Reality, AR) terminal equipment, drones, etc.
  • Home electronic products include smart door locks, TVs, remote controls, refrigerators, rechargeable small household appliances (such as soymilk machines, sweeping robots), etc.
  • Vehicle-mounted electronic products include vehicle navigation systems, vehicle-mounted high-density digital video discs, etc.
  • Financial terminal products include automatic teller machines, self-service terminals, etc.
  • Communication electronic products include communication equipment such as servers, memories, and base stations.
  • the embodiments of the present application do not place any special restrictions on the specific forms of the above-mentioned electronic devices.
  • the following embodiments take the electronic device as a mobile phone as an example.
  • Figure 1 is a structural diagram of an electronic device according to some embodiments.
  • the electronic device 1 mainly includes a cover 11 , a display 12 , a middle frame 13 and a rear case 14 .
  • the back shell 14 and the display screen 12 are respectively located on both sides of the middle frame 13 , and the middle frame 13 and the display screen 12 are arranged in the back shell 14 .
  • the cover plate 11 is disposed on the side of the display screen 12 away from the middle frame 13 .
  • the display screen 12 The display surface faces the cover 11.
  • the display screen 12 can be a liquid crystal display (Liquid Crystal Display, LCD).
  • the liquid crystal display screen includes a liquid crystal display panel and a backlight module.
  • the liquid crystal display panel is arranged between the cover 11 and the backlight module.
  • Backlight modules are used to provide light sources for LCD panels.
  • the above-mentioned display screen 12 may also be an organic light emitting diode (OLED) display screen. Since the OLED display is a self-luminous display, there is no need to set up a backlight module.
  • OLED organic light emitting diode
  • the above-mentioned middle frame 13 includes a bearing plate 131 and a frame 132 surrounding the bearing plate 131 .
  • the electronic device 1 also includes electronic components such as a circuit board 15 , a battery, and a camera, which are disposed on the carrier board 131 .
  • the above-mentioned electronic device 1 may further include a chip 10 disposed on a circuit board 15 , and the chip 10 is electrically connected to the circuit board 15 .
  • the above-mentioned chip 10 may include a processor chip, a memory chip, a radio frequency chip, a radio frequency power amplifier chip, a power management chip, an audio processor chip, a touch screen control chip, an image sensor chip, a charging protection chip, etc.
  • the chip 10 provided in the embodiment of the present application may be a bare chip or a packaged chip, and the packaged chip may include one or more bare chips.
  • the following embodiments of the present application are described by taking the chip 10 as a two-dimensional bare chip as an example.
  • FIG. 2 is a structural diagram of a chip in the related art.
  • the chip 10' includes a substrate 20', and a transfer layer L' and a rewiring layer 27' laminated on the substrate 20'.
  • the substrate 20' includes a substrate G' and an electronic component T' disposed on the substrate G'.
  • the electronic component T' may include a transistor, a capacitor, an inductor, etc.
  • the electronic component T' in Figure 2 takes a transistor as an example.
  • the transistor includes a gate G, a source S and a drain D.
  • the transfer layer L' includes a first dielectric layer 21' and a second dielectric layer 23' stacked on the substrate 20', a conductive pattern 22' penetrating the first dielectric layer 21', and a second dielectric layer 23'. Conductive pillars 24' of the dielectric layer 23'.
  • One end of the conductive pattern 22' is electrically connected to the electronic component T'.
  • the gate G, the source S and the drain D of the transistor respectively correspond to and are electrically connected to one conductive pattern 22'.
  • the transfer layer L' also includes an adhesive layer 26' surrounding the side and bottom surfaces of the conductive pillar 24'.
  • the adhesive layer 26' can be used to adhere the conductive pillar 24' to improve the connection between the conductive pillar 24' and the third The connection strength between the two dielectric layers 23'.
  • the rewiring layer 27 ′ includes a plurality of conductive layers, and the lowest conductive layer among the plurality of conductive layers is electrically connected to the conductive pillar 24 ′.
  • the uppermost conductive layer is exposed to the surface of the rewiring layer 27' and can be used to connect functional devices.
  • the uppermost conductive layer can be used as a pad to connect functional devices.
  • the electrical signal in the electronic component T' can be transmitted to the conductive layer of the rewiring layer 27' through the conductive pattern 22' and the conductive pillar 24', and then the electrical signal can pass through the rewiring layer.
  • the uppermost conductive layer in 27' is transmitted to the functional device connected to it.
  • the electronic component T' is first prepared on the substrate G' to form the substrate 20', and then the first dielectric layer 21' is formed on the substrate 20', and a penetrating first dielectric layer is formed. 21′ conductive pattern 22′. After that, a second dielectric layer 23' is formed on the side of the first dielectric layer 21' away from the substrate 20', and a conductive pillar 24' is formed penetrating the second dielectric layer 23'. Finally, the second dielectric layer 23' is away from the substrate 20. 'A rewiring layer 27' is formed on one side.
  • a chemical vapor deposition (Chemical Vapor Deposition, CVD) process can be used to deposit conductive material in the via hole to form a conductive pillar 24'.
  • the inventor of the present application found through research that, with reference to Figure 2, during the process of depositing conductive material in the via hole, the conductive material is deposited simultaneously on the side walls and bottom of the via hole, and at the connection (corner) between the side wall and the bottom ), the deposition rate is faster. Furthermore, when the conductive material at the top of the via hole is closed, a gap 25' will be generated inside the conductive material in the via hole, so that there will be a gap 25' inside the conductive pillar 24', which will Increasing the resistance of the conductive pillar 24' will cause loss of the electrical signal during transmission on the conductive pillar 24' (for example, the voltage value of the electrical signal will decrease), thereby affecting the performance of the chip 10'.
  • the adhesive layer 26' since the adhesive layer 26' has a certain thickness, it will occupy the space of the via hole, causing the diameter of the conductive pillar 24' to decrease and the radial cross-sectional area to decrease, which will also increase the resistance of the conductive pillar 24'. .
  • the conductive pattern 22' and the conductive pillar 24' are separated by an adhesive layer 26'.
  • the material of the adhesive layer 26' is titanium or titanium nitride, but the conductive properties of titanium or titanium nitride are relatively poor. The difference will increase the contact resistance between the conductive pattern 22', the conductive pillar 24' and the adhesive layer 26', resulting in losses during the transmission of electrical signals from the conductive pattern 22' through the adhesive layer 26' to the conductive pillar 24', affecting Chip 10' performance.
  • FIG. 3 is a structural diagram of a chip according to some embodiments.
  • the chip 10 includes a substrate 20 , and a transfer layer L and a rewiring layer 27 stacked on the substrate 20 .
  • the substrate 20 includes a substrate G and an electronic component T disposed on the substrate G.
  • the electronic component T may include a transistor, a capacitor, an inductor, or the like.
  • the electronic component T in FIG. 3 takes a transistor as an example.
  • the transistor includes a gate G, a source S, and a drain D.
  • the transfer layer L includes a plurality of dielectric layers stacked on the substrate 20 .
  • the plurality of dielectric layers may include a first dielectric layer 21 , a second dielectric layer 231 , a third dielectric layer 232 and a fourth dielectric layer. layer 233 , as well as the first conductive pattern 22 penetrating the first dielectric layer 21 , and the conductive pillars 24 penetrating the second dielectric layer 231 , the third dielectric layer 232 and the fourth dielectric layer 233 .
  • the first conductive patterns 22 include a plurality of first conductive patterns 22
  • the first dielectric layer 21 can serve as a dielectric layer between the plurality of first conductive patterns 22
  • the material of the first dielectric layer 21 may include plasma enhanced oxide (Plasma Enhanced Oxide, PEOX).
  • the electronic component T in the chip 10 may also include a high-resistance structure (not shown in FIG. 3 , for example, the high-resistance structure may be a resistor), and the second dielectric layer 231 may serve as a stop layer for etching to form the high-resistance structure.
  • the material of the second dielectric layer 231 may include silicon nitride.
  • the third dielectric layer 232 may serve as a stop layer for etching the fourth dielectric layer 233 .
  • the material of the third dielectric layer 232 may be the same as the material of the second dielectric layer 231 , that is, the material of the third dielectric layer 232 also includes silicon nitride.
  • the material of the third dielectric layer 232 may also be different from the material of the second dielectric layer 231, which is not limited in the embodiments of the present application.
  • the conductive pillars 24 include multiple, and the second dielectric layer 231 , the third dielectric layer 232 and the fourth dielectric layer 233 can jointly serve as a dielectric layer between the plurality of conductive pillars 24 .
  • the material of the fourth dielectric layer 233 may include silicon oxide, for example.
  • one end of the first conductive pattern 22 is electrically connected to the electronic component T.
  • the gate electrode G, the source electrode S, and the drain electrode D of the transistor respectively correspond to and are electrically connected to one first conductive pattern 22 .
  • the other end of the first conductive pattern 22 is electrically connected to the conductive pillar 24 .
  • the conductive pillar 24 includes a connected contact portion 24 a and a conductive portion 24 b.
  • the contact portion 24 a is in contact with and electrically connected to the first conductive pattern 22 .
  • the conductive portion 24 b penetrates the second dielectric layer 231 , the third dielectric layer 232 and the third dielectric layer 231 .
  • the orthographic projection M1 on the substrate 20 of the end surface of the conductive part 24 b connected to the contact part 24 a is located within the range of the orthographic projection M2 of the end surface of the contact part 24 a connected to the conductive part 24 b on the substrate 20 , for example, the outer shape of the conductive pillar 24 Similar to the shape of a “rivet”, the conductive portion 24b serves as the stem of the “rivet”, and the contact portion 24a serves as the cap of the “rivet”.
  • the rewiring layer 27 includes a plurality of conductive layers.
  • the plurality of conductive layers include a first conductive layer 271 , a second conductive layer 272 , and a third conductive layer 273 that are sequentially away from the substrate 20 .
  • the first conductive layer 271 includes a second conductive pattern 27a, and one end of the conductive pillar 24 away from the first conductive pattern 22 is electrically connected to the second conductive pattern 27a.
  • the second conductive layer 272 includes a transfer pattern 27b, and the transfer pattern 27b is electrically connected to the second conductive pattern 27a.
  • the third conductive layer 273 includes a bonding pad 27c, which is electrically connected to the transfer pattern 27b. The bonding pad 27c is exposed on the surface of the rewiring layer 27 and can be used for soldering functional devices.
  • FIGS. 4A to 4J are diagrams of steps for preparing the chip according to some embodiments.
  • the method for preparing the chip 10 includes the following steps S10 to S19:
  • a substrate 20 is formed, a first dielectric layer 21 is formed on the substrate 20, and a first conductive pattern 22 penetrating the first dielectric layer 21 is formed. Then, the second dielectric layer 231 , the third dielectric layer 232 and the fourth dielectric layer 233 are sequentially formed on the side of the first dielectric layer 21 away from the substrate 20 .
  • the material of the first conductive pattern 22 may include cobalt.
  • first preformed holes H1 are formed through the fourth dielectric layer 233.
  • the plurality of first preformed holes H1 correspond to the plurality of first conductive patterns 22, and each The first preformed hole H1 is located above the corresponding first conductive pattern 22 .
  • the etching liquid L2 contacts the first conductive pattern 22 through the contact hole H2, and etches the first conductive pattern 22 to form the groove 220.
  • the orthographic projection of the contact hole H2 on the substrate 20 is located within the orthographic projection range of the groove 220 on the substrate 20 , that is, the diameter of the contact hole H2 is smaller than the diameter of the opening of the groove 220 .
  • S15 Referring to FIG. 4F, a selective deposition process is used to deposit conductive material in the groove 220 and the contact hole H2 to form the initial conductive pillar 240.
  • the contact hole H2 and the first conductive pattern 22 need to be surface treated to remove chemical residues and dangling bonds attached to the inner wall of the contact hole H2, as well as the Chemical residues and dangling bonds on the surface of the first conductive pattern 22 are exposed to expose the non-metallic material on the inner wall of the contact hole H2 and the metallic material on the surface of the first conductive pattern 22 .
  • the deposition rate of the conductive material on the surface of the metal material is greater than the deposition rate of the conductive material on the surface of the non-metal material, that is, the deposition rate of the conductive material on the surface of the first conductive pattern 22 , is greater than the deposition rate of the conductive material on the inner wall of the contact hole H2, achieving "selective deposition" of the conductive material.
  • the contact hole H2 has been filled with the conductive material, which can avoid the occurrence of voids inside the conductive material in the contact hole H2, thereby avoiding the occurrence of voids inside the initial conductive pillar 240, which is beneficial to reducing the cost of the conductive material.
  • Small initial resistance of conductive pillar 240 Small initial resistance of conductive pillar 240.
  • the above-mentioned “chemical residues” may be chemical substances remaining in the process of forming the contact hole H2; the “dangling bonds” may be, for example, chemical bonds without electrons capable of pairing.
  • the "surface treatment” method may include, for example, heat treatment, plasma treatment, treatment by introducing reducing gas (such as hydrogen), and introducing oxidizing gas (such as oxygen and Nitrous oxide) treatment, inert gas treatment, etc.
  • reducing gas such as hydrogen
  • oxidizing gas such as oxygen and Nitrous oxide
  • S16 Referring to FIG. 4G, use an ion implantation process to inject ions into the second dielectric layer 231, the third dielectric layer 232 and the fourth dielectric layer 233, so that the second dielectric layer 231, the third dielectric layer 232 and the fourth dielectric layer 233 expands, thereby reducing the aperture of the contact hole H2 penetrating the three, and narrowing the gap between the initial conductive pillar 240 and the side wall of the contact hole H2.
  • germanium ions may be implanted into the contact hole H2.
  • a protective layer 28 is formed on the side of the fourth dielectric layer 233 away from the substrate 20.
  • the material of the protective layer 28 may include, for example, titanium nitride.
  • a sacrificial layer 29 is formed on the side of the protective layer 28 away from the substrate 20 .
  • CMP chemical mechanical polishing
  • a rewiring layer 27 is formed on the side of the fourth dielectric layer 233 away from the substrate 20 .
  • the preparation method provided by the above embodiments of the present application includes etching the first conductive pattern 22 to form the groove 220 and depositing conductive material in the groove 220 and the contact hole H2 to form the initial conductive pillar 240 . Since the orthographic projection of the contact hole H2 on the substrate 20 is located within the orthographic projection range of the groove 220 on the substrate 20 , that is, the diameter of the contact hole H2 is smaller than the diameter of the opening of the groove 220 , therefore, the shape of the initial conductive pillar 240 Similar in appearance to "rivets".
  • the "nail cap" of the initial conductive pillar 240 can be used to block the grinding fluid to prevent the grinding fluid from contacting and damaging the contact hole H2.
  • the first conductive pattern 22 is etched.
  • Figure 5 is a structural diagram of a chip according to some embodiments
  • Figure 6 is a partial enlarged view of the chip in Figure 5 at M
  • Figure 7 is a diagram of a chip according to some implementations.
  • a structural diagram of another chip in the example
  • Figure 8 is a partial enlarged view of the chip in Figure 7 at position N
  • Figure 9 is a schematic diagram of grinding conductive pillars according to some embodiments.
  • the chip 10 includes a substrate 20 and a transfer layer L disposed on the substrate 20 .
  • the substrate 20 includes a substrate G and an electronic component T disposed on the substrate G.
  • the electronic component T may include a transistor, a capacitor, an inductor, or the like.
  • the electronic component T in FIG. 5 takes a transistor as an example.
  • the transistor includes a gate G, a source S, and a drain D.
  • the transfer layer L includes a first conductive pattern 22 , and one end of the first conductive pattern 22 is electrically connected to the electronic component T.
  • the gate G, the source S and the drain D of the transistor respectively correspond to and are electrically connected to a first conductive pattern 22, that is, the first conductive pattern 22 can be used as a transistor. of connecting electrodes.
  • the material of the first conductive pattern 22 may include cobalt.
  • the transfer layer L also includes a stacked layer D, which includes at least one first dielectric layer 21 and at least one second dielectric layer 23 sequentially stacked on the first conductive pattern 22 .
  • the stacked layer D includes a first dielectric layer 21 and a second dielectric layer 23 that are sequentially stacked on the first conductive pattern 22 , that is, the second dielectric layer 23 is located on the first dielectric layer. 21 away from the first conductive pattern 22 .
  • the stacked layer D includes a plurality of first dielectric layers 21 and a plurality of second dielectric layers 23 , and the plurality of first dielectric layers 21 and the plurality of second dielectric layers 23 are alternately stacked.
  • the transfer layer L also includes a conductive pillar 24 that penetrates the stacked layer D and has one end electrically connected to the first conductive pattern 22 .
  • the conductive pillar 24 includes at least one first conductive part 241 and at least one second conductive part 242 connected, wherein, along the thickness direction of the first dielectric layer 21 , the first conductive part 241 penetrates the first conductive part 241 and the second conductive part 242 . Dielectric layer 21; along the thickness direction of the second dielectric layer 23, the second conductive portion 242 penetrates the second dielectric layer 23.
  • the stacked layer D includes a first dielectric layer 21 and a second dielectric layer 23 that are sequentially stacked on the first conductive pattern 22 .
  • the conductive pillars 24 include connected A first conductive part 241 and a second conductive part 242, wherein a first conductive part 241 penetrates a first dielectric layer 21, and a second conductive part 242 penetrates a second dielectric layer 23.
  • the stacked layer D includes a plurality of first dielectric layers 21 and a plurality of second dielectric layers 23 .
  • the plurality of first dielectric layers 21 and the plurality of second dielectric layers 23 are alternately stacked.
  • the conductive pillar 24 includes a plurality of first conductive parts 241 and a plurality of second conductive parts 242 that are connected, and the plurality of first conductive parts 241 and the plurality of second conductive parts 242 are alternately connected.
  • Each first conductive part 241 penetrates a first dielectric layer 21
  • each second conductive part 242 penetrates a second dielectric layer 23 .
  • first conductive part 241 and the second conductive part 242 of the conductive pillar 24 may be integrally formed, and the materials of both include tungsten.
  • the end surface of the first conductive part 241 connected to the second conductive part 242 is the first end surface S1 of the first conductive part 241
  • the end surface of the second conductive part 242 connected to the first conductive part 241 is the second end surface of the first conductive part 241 .
  • the second end surface S2 of the conductive portion 242 is located within the range of the orthographic projection of the first end face S1 on the reference plane P.
  • first end surface S1 is the end surface of the first conductive part 241
  • second end surface S2 is the end surface of the second conductive part 242.
  • the second end surface S2 of 242 is connected, that is, the first end surface S1 and the second end surface S2 are in the same plane.
  • the “reference plane P” is the plane on which the surface of the first conductive pattern 22 close to the stacked layer D is located. It can be understood that the reference plane P may be parallel to the plane on which the substrate 20 is located.
  • the chip 10 provided in the above embodiment of the present application does not need to etch the first conductive pattern 22 to form a groove, but uses the shape design of the conductive pillar 24 so that the second end surface S2 of the second conductive part 242 is on the reference plane P.
  • the orthographic projection on the first end surface S1 of the first conductive part 241 is within the orthographic projection range on the reference plane P, that is, along the direction parallel to the reference plane P, the edge of the first end surface S1 exceeds the edge of the second end surface S2 , making the side surface of the first conductive part 241 protrude relative to the side surface of the second conductive part 242 .
  • the end of the conductive pillar 24 away from the first conductive pattern 22 is polished. Even if the polishing fluid penetrates along the gap between the second conductive part 242 and the second dielectric layer 23 , the first end surface S1 The portion beyond the edge of the second end surface S2 can also prevent the grinding liquid from continuing to penetrate, preventing the grinding liquid from contacting and corroding the first conductive pattern 22, thereby ensuring the stability of the interconnection between the conductive pillar 24 and the first conductive pattern 22, and improving Chip 10 reliability.
  • the end of the conductive pillar 24 away from the first conductive pattern 22 will generate torque when it is subjected to friction, and the conductive pillar 24 will move within the stacked layer D, and even from Detached from stack layer D.
  • the portion of the first end surface S1 beyond the edge of the second end surface S2 offsets the second dielectric layer 23, which can limit the movement of the conductive pillar 24, thus preventing the conductive pillar 24 from coming out of the stacked layer D. , to avoid reliability problems with chip 10.
  • the chip 10 provided by the above embodiment of the present application reduces the loss of electrical signal transmission by at least 50%, and the performance of the chip 10 is subsequently improved by about 5%.
  • the stacked layer D has a contact hole H3, which includes at least one first sub-contact hole H31 and at least one second sub-contact hole H32 that are connected.
  • a sub-contact hole H31 penetrates the first dielectric layer 21
  • a second sub-contact hole H32 penetrates the second dielectric layer 23 .
  • the stacked layer D includes a first dielectric layer 21 and a second dielectric layer 23 that are sequentially stacked on the first conductive pattern 22 .
  • the contact hole H3 It includes a first sub-contact hole H31 and a second sub-contact hole H32 that are connected.
  • the stacked layer D includes a plurality of first dielectric layers 21 and a plurality of second dielectric layers 23 , and the plurality of first dielectric layers 21 and the plurality of second dielectric layers 23 are alternately stacked.
  • the contact hole H3 includes a plurality of first sub-contact holes H31 and a plurality of second sub-contact holes H32 that are connected, and the first sub-contact holes H31 and the second sub-contact holes H32 are alternately connected.
  • the first conductive part 241 is located in the first sub-contact hole H31
  • the second conductive part 242 is located in the second sub-contact hole H32 .
  • the first sub-contact hole H31 is in contact with the second sub-contact hole H32 .
  • the opening connected to the hole H32 is the first opening K1 of the first sub-contact hole H31.
  • the opening connected to the second sub-contact hole H32 and the first sub-contact hole H31 is the second opening K2 of the second sub-contact hole H32.
  • the second opening The orthographic projection of K2 on the reference plane P is located within the orthographic projection range of the first opening K1 on the reference plane P.
  • the orthographic projection of the second opening K2 of the second sub-contact hole H32 on the reference plane P is located at the first sub-contact hole H31
  • the first opening K1 is within the orthographic projection range on the reference plane P, that is, along the direction parallel to the reference plane P, the edge of the first opening K1 exceeds the edge of the second opening K2, and the side wall of the first sub-contact hole H31
  • the side walls of the second sub-contact hole H32 are further away from the axis A of the conductive pillar 24 , and the side walls of the first sub-contact hole H31 and the side walls of the second sub-contact hole H32 are not in the same plane.
  • the stacked layer D has a contact hole H3
  • the conductive pillar 24 is located in the contact hole H3
  • the shape of the side of the conductive pillar 24 is similar to the shape of the sidewall of the contact hole H3 . adaptation.
  • the contact hole H3 is formed in the stacked layer D, and then the conductive material is deposited in the contact hole H3, and the conductive material fills the contact hole H3 to form the conductive pillar 24. Therefore, the conductive pillar 24
  • the shape of the side surface of the contact hole H3 matches the shape of the side wall of the contact hole H3.
  • the material of the first dielectric layer 21 is different from the material of the second dielectric layer 23 .
  • the materials of the first dielectric layer 21 and the second dielectric layer 23 are different, and the etching selectivity ratios of the two are different.
  • the etching selectivity ratio means that while the first dielectric layer 21 is being etched, the second dielectric layer 23 will not be etched, so that the sidewalls of the first sub-contact hole H31 are farther away from the conductive side than the sidewalls of the second sub-contact hole H32.
  • the material of the first dielectric layer 21 and the second dielectric layer 23 is any of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxynitride, nitrogen-doped carbide, and oxygen-doped carbide. Two types, just ensure that the materials of the first dielectric layer 21 and the second dielectric layer 23 are different.
  • the etching rate of the first dielectric layer 21 is different from the etching rate of the second dielectric layer 23 .
  • the etching rate of the first dielectric layer 21 and the etching rate of the second dielectric layer 23 are different, therefore, the etching selectivity ratios of the two are different.
  • the etching selectivity ratio means that while the first dielectric layer 21 is being etched, the second dielectric layer 23 will not be etched, so that the sidewalls of the first sub-contact hole H31 are farther away from the conductive side than the sidewalls of the second sub-contact hole H32.
  • the stacked layer D includes a first dielectric layer 21 and a second dielectric layer 23
  • the conductive pillar 24 includes a first conductive portion 241 and a second conductive portion 242 .
  • the second dielectric layer 23 is first etched to form a via hole, the first dielectric layer 21 is etched to form a via hole, and then a conductive material is deposited and filled with the conductive material.
  • the via hole of the second dielectric layer 23 forms a second conductive part 242 penetrating the second dielectric layer 23 ; the conductive material fills the via hole of the first dielectric layer 21 to form a first conductive part 241 penetrating the first dielectric layer 21 . Therefore, in the case where the stacked layer D includes a first dielectric layer 21 and a second dielectric layer 23 , the conductive pillar 24 includes a first conductive portion 241 and a second conductive portion 242 .
  • the conductive pillar 24 is provided with a first conductive part 241 and a second conductive part 242, so that the edge of the first end surface S1 of the first conductive part 241 exceeds the second edge of the second conductive part 242.
  • the stacked layer D includes a plurality of first dielectric layers 21 and a plurality of second dielectric layers 23 that are alternately arranged, and the conductive pillars 24 include a plurality of alternately connected first conductive layers. part 241 and a plurality of second conductive parts 242.
  • the conductive pillars 24 include a plurality of first conductive portions 241 and a plurality of second conductive portions 242 . Furthermore, the number of the first dielectric layers 21 is equal to the number of the first conductive parts 241 , and the number of the second dielectric layers 23 is equal to the number of the second conductive parts 242 .
  • the conductive pillar 24 is provided with a plurality of first conductive parts 241 and a plurality of second conductive parts 242, and among the adjacent first conductive parts 241 and second conductive parts 242, the first conductive part 242 is The edge of the first end surface S1 of the portion 241 exceeds the edge of the second end surface S2 of the second conductive portion 242 .
  • the first end surface S1 connected to the plurality of first conductive parts 241 and the second conductive part 242 above can block the grinding liquid from continuing to seep down, which can further reduce the possibility of the grinding liquid seeping down. Risks are avoided to prevent the polishing liquid from contacting and corroding the first conductive pattern 22 , thereby further improving the reliability of the chip 10 .
  • the end of the conductive pillar 24 away from the first conductive pattern 22 will generate torque when it is subjected to friction, and the conductive pillar 24 will move in the contact hole H3 , and even from the contact hole H3 . Detached from stack layer D.
  • the conductive pillar 24 By arranging the conductive pillar 24 to include a plurality of first conductive parts 241 and a plurality of second conductive parts 242 that are alternately connected, the shape of the conductive pillar 24 is similar to a thread structure, and the first end surfaces S1 of the plurality of first conductive parts 241 are in contact with the plurality of third conductive parts 242 .
  • the two dielectric layers 23 offset each other, which can further restrict the movement of the conductive pillars 24 , thereby preventing the conductive pillars 24 from coming out of the stacked layer D and avoiding reliability problems of the chip 10 .
  • the conductive pillar 24 even if the conductive pillar 24 moves within the contact hole H3 , a gap is generated between a part of the conductive pillar 24 and the side wall of the contact hole H3 .
  • the conductive pillar 24 By arranging the conductive pillar 24 to have a plurality of first conductive portions 241 and a plurality of second conductive portions 242, the plurality of first conductive portions 241 and the plurality of second conductive portions 242 can interact with the plurality of first dielectric layers 21 and the plurality of third conductive portions.
  • the two dielectric layers 23 form multiple seals, such as the seals a, b, and c shown in FIG. 9 , to ensure that seals are formed along the circumferential direction of the conductive pillar 24 to prevent the polishing liquid from contacting and corroding the first conductive pattern 22 .
  • the average diameter of the first conductive portion 241 is greater than the average diameter of the second conductive portion 242 .
  • the diameters of the first conductive part 241 and the second conductive part 242 both change.
  • the "average diameter of the first conductive part 241" may be half of the sum of the maximum diameter and the minimum diameter of the first conductive part 241.
  • the "average diameter of the second conductive part 242" may be, the second conductive part 242 half of the sum of the maximum diameter and the minimum diameter.
  • the end of the first conductive part 241 connected to the second conductive part 242 is connected to the first conductive part 241 relative to the second conductive part 242.
  • One end protrudes. In this way, during the process of grinding the conductive pillar 24, the protruding end of the first conductive part 241 can prevent the grinding liquid from continuing to penetrate downward, preventing the grinding liquid from contacting and corroding the first conductive pattern 22.
  • the first conductive part 241 is in the shape of a cylinder or a truncated cone
  • the second conductive part 242 is in the shape of a cylinder or a truncated cone.
  • the shapes of the first conductive part 241 and the second conductive part 242 may also be prisms, for example, triangular prisms, four prisms, or pentagonal prisms, etc., and the embodiments of the present application are not limited thereto.
  • the chip 10 further includes a rewiring layer 27 , and the rewiring layer 27 includes a plurality of conductive layers.
  • the plurality of conductive layers include a plurality of conductive layers disposed in sequence on the stacked layer D away from the first layer.
  • the first conductive layer 271 includes a second conductive pattern 27a.
  • One end of the conductive pillar 24 away from the first conductive pattern 22 is electrically connected to the second conductive pattern 27a, so that the first conductive pattern 22 and the second conductive pattern 27a are connected through the conductive pillar 24. Interconnection and signal transmission between patterns 27a.
  • the second conductive layer 272 includes a transfer pattern 27b, and the transfer pattern 27b is electrically connected to the second conductive pattern 27a.
  • the third conductive layer 273 includes a bonding pad 27c, which is electrically connected to the transfer pattern 27b.
  • the bonding pad 27c is exposed on the surface of the rewiring layer 27 and can be used for soldering functional devices.
  • FIG. 10 is a structural diagram of the chip according to some embodiments.
  • the stacked layer D also includes a third dielectric layer 30, which is located between the first conductive pattern 22 and the first dielectric layer 21 closest to the first conductive pattern 22. Furthermore, the conductive pillar 24 further includes a third conductive portion 243 that penetrates the third dielectric layer 30 and is electrically connected to the first conductive portion 241 closest to the first conductive pattern 22 .
  • the end surface connecting the first conductive part 241 and the third conductive part 243 is the third end surface S3
  • the end surface connecting the third conductive part 243 and the first conductive part 241 is the fourth end surface S4
  • the fourth end surface S4 is on the reference plane P.
  • the orthographic projection on is located within the orthographic projection range of the third end surface S3 on the reference plane P.
  • the diameter change trend of the conductive pillar 24 is small, large, small, large..., the embodiments of the present application are not limited to this.
  • the diameter change trend of the conductive pillar 24 is large, small, large, small....
  • the material of the third dielectric layer 30 is the same as the material of the second dielectric layer 23, and/or, under the same etching conditions, the etching rate of the third dielectric layer 30 is the same as the etching rate of the second dielectric layer 23. The rate is the same.
  • the material of the third dielectric layer 30 is the same as the material of the second dielectric layer 23, and their etching selectivity ratios are different. Therefore, under the same etching conditions, the etching rate of the third dielectric layer 30 is different from that of the second dielectric layer 23. The etching rate of the second dielectric layer 23 is the same.
  • Figures 11A to 11E are flow charts for preparing a chip according to some embodiments;
  • Figures 12A to 12K are flow charts for preparing a chip according to some embodiments. Diagram of each step.
  • the preparation method of chip 10 includes the following steps S10 to S30:
  • a substrate 20 is provided, and the substrate 20 includes a substrate G, and an electronic component T disposed on the substrate G. Then, a first conductive pattern 22 is formed on the substrate 20 , and the first conductive pattern 22 is electrically connected to the electronic component T.
  • the electronic component T is a transistor, and the transistor includes a gate G, a source S, and a drain D. The gate G, the source S, and the drain D of the transistor respectively correspond to and are electrically connected to a first conductive pattern 22 .
  • a stacked layer D is formed on the first conductive pattern 22.
  • the stacked layer D includes at least one first dielectric layer 21 and at least one second dielectric layer 23 that are stacked in sequence.
  • the stacked layer D includes a first dielectric layer 21 and a second dielectric layer 23 that are stacked in sequence.
  • the conductive pillar 24 includes at least one first conductive part 241 and at least one second conductive part 242 connected, the first conductive part 241 penetrates the first dielectric layer 21 , and the second conductive part 242 penetrates the second dielectric layer 23 .
  • the end surface where the first conductive part 241 is connected to the second conductive part 242 is the first end surface S1
  • the end surface where the second conductive part 242 is connected to the first conductive part 241 is the second end surface S2.
  • the orthographic projection of the second end face S2 on the reference plane P is located within the range of the orthographic projection of the first end face S1 on the reference plane P.
  • the conductive pillar 24 includes a first conductive part 241 and a second conductive part 242 connected, a first conductive part 241 penetrating a first dielectric layer 21 , and a second conductive part 242 penetrating A second dielectric layer 23.
  • the above-mentioned S30: forming conductive pillars 24 penetrating the stacked layer D may include the following S301 to S302:
  • the above-mentioned S301 also includes the following S3011 ⁇ S3014:
  • the mask layer R has an opening, which can expose the stacked layer D, so that the stacked layer D can be subsequently etched through the mask layer R.
  • the mask layer R can be a photoresist layer, and an exposure and development process can be used to form openings on the mask layer R.
  • a stripping liquid can be used to remove the mask layer R from the stacked layer D.
  • the stripping liquid used is an acidic liquid, which has a corrosive effect on metal. Therefore, before etching the first dielectric layer 21, the stripping liquid is used to remove the mask layer R. The layer R is removed, and then the first dielectric layer 21 is etched to expose the first conductive pattern 22, which can prevent the stripping liquid from contacting and corroding the first conductive pattern 22.
  • a contact hole H3 is formed that penetrates the stacked layer D.
  • the contact hole H3 needs to be cleaned. For example, a wet cleaning process is used to remove the etching by-products with a cleaning solution.
  • a wet cleaning process is used to remove the etching by-products with a cleaning solution.
  • the contact hole H3 and the first conductive pattern 22 need to be surface treated to remove the chemical residues and dangling bonds attached to the inner wall of the contact hole H3 and the chemical residues and dangling bonds attached to the surface of the first conductive pattern 22 .
  • a selective growth process can be used to fill the contact hole H3 with conductive material to form the initial conductive pillar 240 , which can avoid the formation of voids inside the conductive material in the contact hole H3 , thereby avoiding the initial conductive pillar 240 voids are created inside.
  • the preparation method of the chip 10 further includes the following steps S303 to S305:
  • a protective layer 28 is formed, and the protective layer 28 covers the stacked layer D.
  • the material of protective layer 28 may include titanium nitride.
  • a sacrificial layer 29 is formed, and the sacrificial layer 29 covers the protective layer 28.
  • a metal oxide chemical vapor deposition process may be used to form the sacrificial layer 29 .
  • the material of the sacrificial layer 29 can be the same as the material of the initial conductive pillar 240.
  • the materials of both include tungsten, which is beneficial to improving the uniformity of grinding and improving the quality of surface grinding in the subsequent grinding process.
  • S305 As shown in FIG. 12I and FIG. 12J , grind the portion of the sacrificial layer 29 , the protective layer 28 and the stacked layer D away from the first conductive pattern 22 to expose the end of the conductive pillar 24 away from the first conductive pattern 22 .
  • a chemical mechanical polishing process may be used to polish the portions of the sacrificial layer 29 , the protective layer 28 and the stacked layer D away from the first conductive pattern 22 .
  • a second conductive pattern 27a is prepared.
  • the protective layer 28 can block the polishing liquid and prevent the polishing liquid from seeping down from the gap between the conductive pillar 24 and the contact hole H3, thereby preventing the polishing liquid from contacting and corroding the first conductive pattern 22.
  • the preparation method of the chip 10 further includes the following S40:
  • a second conductive pattern 27a is formed.
  • the second conductive pattern 27a is located on the stacked layer D.
  • One end of the conductive pillar 24 away from the first conductive pattern 22 is electrically connected to the second conductive pattern 27a.
  • the conductive pillars 24 realize interconnection and signal transmission between the first conductive pattern 22 and the second conductive pattern 27a.
  • the orthographic projection of the second end surface S2 of the second conductive part 242 of the conductive pillar 24 on the reference plane P is located at the first end surface S1 of the first conductive part 241 within the orthographic projection range on the reference plane P, that is, along the direction parallel to the reference plane P, the edge of the first end surface S1 exceeds the edge of the second end surface S2, so that the side surface of the first conductive part 241 is relative to the second conductive part 242 The sides are bulging.
  • the polishing fluid continues to penetrate downward to prevent the polishing fluid from contacting and corroding the first conductive pattern 22 , thereby ensuring the stability of the interconnection between the conductive pillar 24 and the first conductive pattern 22 and improving the reliability of the chip 10 .
  • the end of the conductive pillar 24 away from the first conductive pattern 22 will generate a torque due to friction, and the conductive pillar 24 will move in the stacked layer D, or even come out of the stacked layer D.
  • the portion of the first end surface S1 beyond the edge of the second end surface S2 offsets the second dielectric layer 23, which can limit the movement of the conductive pillars 24, thereby preventing the conductive pillars 24 from coming out of the stacked layer D. Avoid reliability problems with chip 10.
  • the stacked layer D of the chip 10 includes a first dielectric layer 21 and a second dielectric layer 23 that are stacked in sequence.
  • Some embodiments of the present application also provide a method for manufacturing a chip.
  • the preparation method is similar to the above-mentioned preparation method. The difference lies in the chip 10 to which the preparation method is applied.
  • the stacked layer D of the chip 10 includes a plurality of alternately arranged first layers. dielectric layer 21 and a plurality of second dielectric layers 23 .
  • Figures 13A to 13E are flow charts for preparing another chip according to some embodiments;
  • Figures 14A to 14L are step diagrams for preparing another chip according to some embodiments.
  • the preparation method of chip 10 includes the following steps S10' to S30':
  • a substrate 20 is provided, and the substrate 20 includes a substrate G, and an electronic component T disposed on the substrate G.
  • the electronic component T is a transistor, and the transistor includes a gate G, a source S, and a drain D.
  • a stacked layer D is formed on the first conductive pattern 22.
  • the stacked layer D includes a plurality of first dielectric layers 21 and a plurality of second dielectric layers 23 that are alternately arranged.
  • conductive pillars 24 are formed through the stacked layer D, and one end of the conductive pillars 24 is electrically connected to the first conductive pattern 22.
  • the conductive pillar 24 includes a plurality of first conductive parts 241 and a plurality of second conductive parts 242 that are alternately connected.
  • Each first conductive part 241 passes through a first dielectric layer 21
  • each second conductive part 242 passes through A second dielectric layer 23.
  • the end surface where the first conductive part 241 is connected to the second conductive part 242 is the first end surface S1
  • the end surface where the second conductive part 242 is connected to the first conductive part 241 is the second end surface S2.
  • the orthographic projection of the second end face S2 on the reference plane P is located within the range of the orthographic projection of the first end face S1 on the reference plane P.
  • the above-mentioned S30': forming the conductive pillar 24 penetrating the stacked layer D may include the following S301'-S302':
  • the above-mentioned S301' may include the following S3011' ⁇ S3015':
  • the mask layer R has an opening, which can expose the stacked layer D, so that the stacked layer D can be subsequently etched through the mask layer R.
  • the mask layer R can be a photoresist layer, and an exposure and development process can be used to form openings on the mask layer R.
  • the first dielectric layer 21 closest to the first conductive pattern 22 among the plurality of first dielectric layers 21 of the stacked layer D is the “set first dielectric layer 21 a ”.
  • the "target film layer” of the stacked layer D refers to the film layer located above the set first dielectric layer 21a in the stacked layer D.
  • the above-mentioned second preformed hole H4 exposes and sets the first dielectric layer 21a.
  • a stripping liquid can be used to remove the mask layer R from the stacked layer D.
  • the mask layer R is removed with a stripping solution, and then the first dielectric layer 21a is etched and set to expose the first conductive pattern 22, thereby avoiding peeling.
  • the liquid contacts and corrodes the first conductive pattern 22 .
  • a contact hole H3 penetrating the stacked layer D is formed, and the contact hole H3 needs to be cleaned.
  • a wet cleaning process is used to remove the etching vice by using a cleaning solution. product to ensure the exposure of the first conductive pattern 22.
  • the contact hole H3 and the first conductive pattern 22 need to be surface treated to remove the chemical residues and dangling bonds attached to the inner wall of the contact hole H3 and the chemical residues and dangling bonds attached to the surface of the first conductive pattern 22 .
  • the preparation method of the chip 10 further includes the following steps S303′ to S305′:
  • a protective layer 28 is formed, and the protective layer 28 covers the stacked layer D.
  • the material of protective layer 28 may include titanium nitride.
  • S304' As shown in FIG. 14J, a sacrificial layer 29 is formed, and the sacrificial layer 29 covers the protective layer 28.
  • the preparation method of the chip 10 further includes the following S40′:
  • a second conductive pattern 27a is formed.
  • the second conductive pattern 27a is located on the stacked layer D.
  • One end of the conductive pillar 24 away from the first conductive pattern 22 is electrically connected to the second conductive pattern 27a.
  • the conductive pillar 24 prepared by the preparation method provided by the above embodiments of the present application has a plurality of first conductive parts 241 and a plurality of second conductive parts 242, and the adjacent first conductive parts 241 and In the second conductive part 242 , the edge of the first end surface S1 of the first conductive part 241 exceeds the edge of the second end surface S2 of the second conductive part 242 .
  • the first end surface S1 connected to the plurality of first conductive parts 241 and the second conductive part 242 above can block the grinding liquid from continuing to seep down, which can further reduce the possibility of the grinding liquid seeping down. Risks are avoided to prevent the polishing liquid from contacting and corroding the first conductive pattern 22 , thereby further improving the reliability of the chip 10 .
  • the movement of the conductive pillar 24 can be further restricted during the grinding process of the conductive pillar 24, thereby preventing the conductive pillar 24 from coming out of the stacked layer D and avoiding reliability problems of the chip 10. .
  • the electronic device 1 provided in some embodiments of the present application includes the chip 10 provided in any of the above embodiments.
  • the beneficial effects it can achieve can be referred to the beneficial effects of the chip 10 mentioned above, which will not be described again here.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

本申请的一些实施例提供了一种芯片及其制备方法、电子设备，涉及半导体技术领域，提高了芯片的可靠性。该芯片可以是裸芯片，也可以是封装后的芯片，其包括中段工艺制备的第一导电图案、堆叠层和导电柱，堆叠层包括层叠设置于第一导电图案上的第一介质层和第二介质层。导电柱包括第一导电部和第二导电部，第一导电部贯穿第一介质层，第二导电部贯穿第二介质层。第一导电部与第二导电部相连的端面为第一导电部的第一端面，第二导电部与第一导电部相连的端面为第二导电部的第二端面，第二端面在参考面上的正投影位于第一端面在参考面上的正投影范围内，该参考面为第一导电图案的靠近堆叠层一侧表面所在的平面。上述芯片可应用于电子设备中。

Description

一种芯片及其制备方法、电子设备 技术领域
本申请涉及半导体技术领域，尤其涉及一种芯片及其制备方法、电子设备。
背景技术
随着半导体技术的发展，电子设备中的芯片的集成度逐渐提高，有利于实现芯片的小尺寸化和轻薄化。
在相关技术中，芯片包括基板，以及层叠设置于基板上的转接层和重新布线层，转接层包括层叠设置于基板上的第一介质层和第二介质层，贯穿第一介质层的导电图案，贯穿第二介质层的导电柱，其中，导电柱与导电图案电连接。
但是，随着芯片的小尺寸化，芯片中导电图案的尺寸也随之减小，这给导电柱与导电图案之间的互连带来较大的挑战，不利于提高芯片的可靠性。因此，如何提高导电柱与导电图案之间互连的稳定性，成为本领域亟待解决的问题。
发明内容
本申请实施例提供一种芯片及其制备方法、电子设备，旨在提高芯片中导电柱与导电图案之间互连的稳定性，以提高芯片的可靠性。
为达到上述目的，本申请的实施例采用如下技术方案：
第一方面，提供了一种芯片，该芯片可以是裸芯片，也可以是封装后的芯片，其包括第一导电图案、堆叠层和导电柱，其中，第一导电图案例如包括中段工艺制备的至少一层导电图案。堆叠层包括中段工艺制备的多个介质层，例如包括依次层叠设置于第一导电图案上的至少一个第一介质层和至少一个第二介质层。导电柱例如可以是中段工艺制备的导电结构，该导电柱贯穿堆叠层，且一端与第一导电图案电连接。导电柱包括相连接的至少一个第一导电部和至少一个第二导电部，第一导电部贯穿第一介质层，第二导电部贯穿第二介质层。第一导电部与第二导电部相连的端面为第一导电部的第一端面，第二导电部与第一导电部相连的端面为第二导电部的第二端面，第二端面在参考面上的正投影位于第一端面在参考面上的正投影范围内，该参考面为第一导电图案的靠近堆叠层一侧表面所在的平面。
本申请的上述实施例所提供的芯片，通过导电柱的外形设计，使第二导电部的第二端面在参考面上的正投影位于，第一导电部的第一端面在参考面上的正投影范围内，即沿平行于参考面的方向，第一端面的边缘超出第二端面的边缘，使第一导电部的侧面相对于第二导电部的侧面凸出。
基于此，在制备芯片的过程中，研磨导电柱的远离第一导电图案的一端，即使研磨液沿第二导电部与第二介质层之间的缝隙渗入，第一端面的超出第二端面边缘的部分也可阻挡研磨液继续下渗，避免研磨液接触并腐蚀第一导电图案，从而保证导电柱与第一导电图案之间互连的稳定性，提高芯片的可靠性。
并且，在研磨导电柱的过程中，导电柱的远离第一导电图案的一端受到摩擦力会产生扭矩，导电柱会在堆叠层中移动，甚至从堆叠层中脱出。通过上述导电柱的外形 设计，第一端面的超出第二端面边缘的部分与第二介质层相抵，可限制导电柱的移动，从而可避免导电柱从堆叠层中脱出，避免芯片出现可靠性问题。
在一些实施例中，堆叠层具有接触孔，该接触孔包括相连通的至少一个第一子接触孔和至少一个第二子接触孔，第一子接触孔贯穿第一介质层，第二子接触孔贯穿第二介质层。第一导电部位于第一子接触孔内，第二导电部位于第二子接触孔内。其中，第一子接触孔与第二子接触孔相连的开口为第一子接触孔的第一开口，第二子接触孔与第一子接触孔相连的开口为第二子接触孔的第二开口，第二开口在参考面上的正投影位于第一开口在参考面上的正投影范围内。
上述实施例中的设置方式，通过对堆叠层中的接触孔的形状设计，使第二子接触孔的第二开口在参考面上的正投影位于，第一子接触孔的第一开口在参考面上的正投影范围内，即沿平行于参考面的方向，第一开口的边缘超出第二开口的边缘，第一子接触孔的侧壁，相对于第二子接触孔的侧壁更远离导电柱的轴线，第一子接触孔的侧壁与第二子接触孔的侧壁不处于同一平面内。这样，在研磨导电柱的过程中，即使研磨液沿第二子接触孔的侧壁渗入，由于第一子接触孔的侧壁与第二子接触孔的侧壁不处于同一平面内，研磨液不易从第二子接触孔的侧壁下渗至第一子接触孔的侧壁，避免研磨液接触并腐蚀第一导电图案，从而提高芯片的可靠性。
在一些实施例中，第一介质层的材料与第二介质层的材料不同。
上述实施例中的设置方式，可通过设置第一介质层21的材料与第二介质层23的材料不同，来调整第一介质层和第二介质层的刻蚀选择比，满足第一介质层的刻蚀速率远大于第二介质层的刻蚀速率，例如，可通过调整二者的刻蚀选择比，刻蚀第一介质层的同时不会刻蚀第二介质层，从而使第一子接触孔的侧壁，相对于第二子接触孔的侧壁更远离导电柱的轴线。在一些实施例中，在同一刻蚀条件下，第一介质层的刻蚀速率与第二介质层的刻蚀速率不同。
上述实施例中的设置方式，可通过调整第一介质层和第二介质层的刻蚀选择比，满足第一介质层的刻蚀速率远大于第二介质层的刻蚀速率，例如，可通过调整二者的刻蚀选择比，刻蚀第一介质层的同时不会刻蚀第二介质层，从而使第一子接触孔的侧壁，相对于第二子接触孔的侧壁更远离导电柱的轴线。
在一些实施例中，第一介质层和第二介质层的材料为，氧化硅、氮化硅、氮氧化硅、碳氧氮化硅、氮掺杂碳化物、氧掺杂碳化物中的任意两种。
上述实施例中的设置方式，保证第一介质层和第二介质层的材料不同即可。
在一些实施例中，堆叠层包括一个第一介质层和一个第二介质层，导电柱包括一个第一导电部和一个第二导电部。
上述实施例中，通过设置导电柱具有一个第一导电部和一个第二导电部，使第一导电部的第一端面的边缘，超出第二导电部的第二端面的边缘。在研磨导电柱的过程中，即使研磨液沿第二导电部与第二介质层之间的缝隙渗入，第一端面的超出第二端面边缘的部分也可阻挡研磨液继续下渗，避免研磨液接触并腐蚀第一导电图案，从而提高芯片的可靠性。
在一些实施例中，堆叠层包括交替设置的多个第一介质层和多个第二介质层，导电柱包括交替相连的多个第一导电部和多个第二导电部。
上述实施例中，通过设置导电柱具有多个第一导电部和多个第二导电部，在研磨导电柱的过程中，多个第一导电部与其上方的第二导电部相连的第一端面，均可阻挡研磨液继续下渗，可进一步降低研磨液下渗的风险，避免研磨液接触并腐蚀第一导电图案，从而进一步提高芯片的可靠性。
并且，在研磨导电柱的过程中，导电柱的远离第一导电图案的一端受到摩擦力会产生扭矩，导电柱会在堆叠层中移动，甚至从堆叠层中脱出。通过设置导电柱包括交替相连的多个第一导电部和多个第二导电部，导电柱的外形近似螺纹结构，多个第一导电部的第一端面与多个第二介质层相抵，可进一步限制导电柱移动，从而可避免导电柱从堆叠层中脱出，避免芯片出现可靠性问题。
在一些实施例中，第一导电部的平均直径大于第二导电部的平均直径。
上述实施例中，通过设置第一导电部的平均直径大于第二导电部的平均直径，使第一导电部与第二导电部相连的一端，相对于第二导电部与第一导电部相连的一端凸出。这样，在研磨导电柱的过程中，第一导电部的凸出的端部可阻挡研磨液继续下渗，避免研磨液接触并腐蚀第一导电图案。
在一些实施例中，堆叠层还包括第三介质层，位于第一导电图案与最靠近第一导电图案的第一介质层之间。导电柱还包括第三导电部，贯穿第三介质层，且与最靠近第一导电图案的第一导电部电连接。其中，第一导电部与第三导电部相连的端面为第三端面，第三导电部与第一导电部相连的端面为第四端面，第四端面在参考面上的正投影位于第三端面在参考面上的正投影范围内。
上述实施例中，沿第一导电图案指向堆叠层的方向，导电柱的直径变化趋势为小、大、小、大……。
在一些实施例中，第三介质层的材料与第二介质层的材料相同。
上述实施例中，可以理解的是，在同一刻蚀条件下，第三介质层的刻蚀速率与第二介质层的刻蚀速率相同。
在一些实施例中，堆叠层具有接触孔，导电柱位于接触孔内，导电柱的侧面的形状与接触孔的侧壁的形状相适配。
上述实施例中的设置方式，有利于减小导电柱的侧面与接触孔的侧壁之间的缝隙，在研磨导电柱的过程中，可改善研磨液沿导电柱与接触孔之间的缝隙下渗的问题。
在一些实施例中，第一导电部的形状为圆柱体或圆台，第二导电部的形状为圆柱体或圆台。
在一些实施例中，芯片还包括第二导电图案，设置于堆叠层远离第一导电图案的一侧。导电柱远离第一导电图案的一端与第二导电图案电连接。
上述实施例中，通过导电柱实现了第一导电图案与第二导电图案之间的互连及信号传输。
第二方面，提供了一种芯片的制备方法，该制备方法包括：形成第一导电图案。在第一导电图案上形成堆叠层，堆叠层包括依次层叠设置的至少一个第一介质层和至少一个第二介质层。形成贯穿堆叠层的导电柱，导电柱的一端与第一导电图案电连接；导电柱包括相连接的至少一个第一导电部和至少一个第二导电部，第一导电部贯穿第一介质层，第二导电部贯穿第二介质层。其中，第一导电部与第二导电部相连的端面 为第一端面，第二导电部与第一导电部相连的端面为第二端面，第二端面在参考面上的正投影位于第一端面在参考面上的正投影范围内。
本申请的上述实施例所提供的制备方法，制备得到的导电柱，其第二导电部的第二端面在参考面上的正投影位于，第一导电部的第一端面在参考面上的正投影范围内，即沿平行于参考面P的方向，第一端面的边缘超出第二端面的边缘，使第一导电部的侧面相对于第二导电部的侧面凸出。
基于此，在后续研磨导电柱的过程中，即使研磨液沿第二导电部与第二介质层之间的缝隙渗入，第一端面的超出第二端面边缘的部分也可阻挡研磨液继续下渗，避免研磨液接触并腐蚀第一导电图案，从而保证导电柱与第一导电图案之间互连的稳定性，提高芯片的可靠性。
并且，在研磨导电柱的过程中，导电柱的远离第一导电图案的一端受到摩擦力会产生扭矩，导电柱会在堆叠层中移动，甚至从堆叠层中脱出。通过上述导电柱的制备，第一端面的超出第二端面边缘的部分与第二介质层相抵，可限制导电柱的移动，从而可避免导电柱从堆叠层中脱出，避免芯片出现可靠性问题。
在一些实施例中，形成贯穿堆叠层的导电柱，包括：形成贯穿堆叠层的接触孔。在接触孔内填充导电材料，形成导电柱。
上述实施例中，可采用选择性沉积工艺，在接触孔内填充导电材料，可避免接触孔中导电材料的内部产生空隙，从而避免初始导电柱的内部产生空隙。
在一些实施例中，堆叠层包括一个第一介质层和一个第二介质层。形成贯穿堆叠层的接触孔，包括：形成掩膜层，掩膜层位于堆叠层上。基于掩膜层，刻蚀第二介质层，形成贯穿第二介质层的预制孔。去除掩膜层。经由预制孔，刻蚀第一介质层，以暴露第一导电图案。
上述实施例中，在堆叠层包括一个第一介质层和一个第二介质层的情况下，形成贯穿堆叠层的接触孔。在刻蚀第一介质层之前，采用剥离液将掩膜层去除，然后再刻蚀第一介质层以暴露第一导电图案，可避免剥离液接触并腐蚀第一导电图案。
在一些实施例中，堆叠层包括交替设置的多个第一介质层和多个第二介质层，多个第一介质层中最靠近第一导电图案的第一介质层为设定第一介质层。形成贯穿堆叠层的接触孔，包括：形成掩膜层，掩膜层位于堆叠层上。基于掩膜层，刻蚀堆叠层的目标膜层，形成贯穿目标膜层的预制孔；目标膜层为，堆叠层中位于设定第一介质层上方的膜层。经由预制孔，刻蚀目标膜层中的第一介质层靠近预制孔的侧面，形成凹槽。去除掩膜层。经由预制孔，刻蚀设定第一介质层，以暴露第一导电图案。
上述实施例中，在堆叠层包括交替设置的多个第一介质层和多个第二介质层的情况下，形成贯穿堆叠层的接触孔。在刻蚀设定第一介质层之前，便采用剥离液将掩膜层去除，然后再刻蚀设定第一介质层以暴露第一导电图案，可避免剥离液接触并腐蚀第一导电图案。
在一些实施例中，在接触孔内填充导电材料之后，还包括：形成保护层，保护层覆盖堆叠层。形成牺牲层，牺牲层覆盖保护层。研磨牺牲层、保护层及堆叠层远离第一导电图案一侧的部分，以暴露导电柱远离第一导电图案的端部。
上述实施例中，在研磨的过程中，会去除牺牲层、保护层以及堆叠层远离第一导 电图案一侧的部分，暴露导电柱远离第一导电图案的端部，并且，研磨可使堆叠层远离第一导电图案一侧的表面平坦化，以便于后续在堆叠层的表面上制备第二导电图案。
并且，在研磨的过程中，保护层可起到阻挡研磨液的作用，可防止研磨液从导电柱与接触孔的缝隙下渗，从而避免研磨液接触并腐蚀第一导电图案。
在一些实施例中，形成导电柱之后，还包括：形成第二导电图案，第二导电图案位于堆叠层上，导电柱远离第一导电图案的一端与第二导电图案电连接。
上述实施例中，通过导电柱实现了第一导电图案与第二导电图案之间的互连及信号传输。
第三方面，提供了一种电子设备，该电子设备例如为消费性电子产品、家居式电子产品、车载式电子产品、金融终端产品、通信电子产品。该电子设备包括电路板，以及上述任一实施例所述的芯片，该芯片与电路板电连接。
可以理解地，本公开的上述实施例提供的电子设备，其所能达到的有益效果可参考上文中芯片的有益效果，此处不再赘述。
附图说明
为了更清楚地说明本公开中的技术方案，下面将对本公开一些实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例的附图，对于本领域普通技术人员来讲，还可以根据这些附图获得其他的附图。此外，以下描述中的附图可以视作示意图，并非对本公开实施例所涉及的产品的实际尺寸、方法的实际流程、信号的实际时序等的限制。
图1为根据一些实施例的电子设备的结构图；
图2为相关技术中的芯片的结构图；
图3为根据一些实施例的一种芯片的结构图；
图4A～图4J为根据一些实施例的制备芯片的各步骤图；
图5为根据一些实施例的另一种芯片的结构图；
图6为图5中的芯片在M处的局部放大图；
图7为根据一些实施例的又一种芯片的结构图；
图8为图7中的芯片在N处的局部放大图；
图9为根据一些实施例的研磨导电柱的示意图；
图10为根据一些实施例的又一种芯片的结构图；
图11A～图11E为根据一些实施例的制备一种芯片的各流程图；
图12A～图12K为根据一些实施例的制备一种芯片的各步骤图；
图13A～图13E为根据一些实施例的制备另一种芯片的各流程图；
图14A～图14L为根据一些实施例的制备另一种芯片的各步骤图。
具体实施方式
下面将结合附图，对本公开一些实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开所提供的实施例，本领域普通技术人员所获得的所有其他实施例，都属于本公开保护的范围。
在本公开的描述中，需要理解的是，术语“中心”、“上”、“下”、“前”、 “后”、“左”、“右”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本公开和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。
除非上下文另有要求，否则，在整个说明书和权利要求书中，术语“包括”被解释为开放、包含的意思，即为“包含，但不限于”。在说明书的描述中，术语“一个实施例”、“一些实施例”、“示例性实施例”、“示例性地”或“一些示例”等旨在表明与该实施例或示例相关的特定特征、结构、材料或特性包括在本公开的至少一个实施例或示例中。上述术语的示意性表示不一定是指同一实施例或示例。此外，所述的特定特征、结构、材料或特点可以以任何适当方式包括在任何一个或多个实施例或示例中。
以下，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本公开实施例的描述中，除非另有说明，“多个”的含义是两个或两个以上。
在描述一些实施例时，可能使用了“耦接”和“连接”及其衍伸的表达。例如，描述一些实施例时可能使用了术语“连接”以表明两个或两个以上部件彼此间有直接物理接触或电接触。又如，描述一些实施例时可能使用了术语“耦接”以表明两个或两个以上部件有直接物理接触或电接触。然而，术语“耦接”也可能指两个或两个以上部件彼此间并无直接接触，但仍彼此协作或相互作用。这里所公开的实施例并不必然限制于本文内容。
“A和/或B”，包括以下三种组合：仅A，仅B，及A和B的组合。
另外，“基于”的使用意味着开放和包容性，因为“基于”一个或多个所述条件或值的过程、步骤、计算或其他动作在实践中可以基于额外条件或超出所述的值。
如本文所使用的那样，“约”、“大致”或“近似”包括所阐述的值以及处于特定值的可接受偏差范围内的平均值，其中所述可接受偏差范围如由本领域普通技术人员考虑到正在讨论的测量以及与特定量的测量相关的误差(即，测量系统的局限性)所确定。
在本公开的内容中，“在……上”、“上方”、和“之上”的含义应当以最宽泛的方式解释，使得“在...上”不仅意味着“直接在某物上”，而且还包括其间具有中间特征或层的“在某物上”的含义，并且“上方”或“之上”不仅意味着在某物“上方”或“之上”，还包括其间没有中间特征或层的在某物“上方”或“之上”的含义(即，直接在某物上)。
本文参照作为理想化示例性附图的剖视图和/或平面图描述了示例性实施方式。在附图中，为了清楚，放大了层和区域的厚度。因此，可设想到由于例如制造技术和/或公差引起的相对于附图的形状的变动。因此，示例性实施方式不应解释为局限于本文示出的区域的形状，而是包括因例如制造而引起的形状偏差。例如，示为矩形的蚀刻区域通常将具有弯曲的特征。因此，附图中所示的区域本质上是示意性的，且它们的形状并非旨在示出设备的区域的实际形状，并且并非旨在限制示例性实施方式的范 围。
本申请的实施例提供一种电子设备。该电子设备例如为消费性电子产品、家居式电子产品、车载式电子产品、金融终端产品、通信电子产品。其中，消费性电子产品如为手机、平板电脑、笔记本电脑、电子阅读器、个人计算机(Personal Computer，PC)、个人数字助理(Personal Digital Assistant，PDA)、桌面显示器、智能穿戴产品(例如，智能手表、智能手环)、虚拟现实(Virtual Reality，VR)终端设备、增强现实(Augmented Reality，AR)终端设备、无人机等。家居式电子产品如为智能门锁、电视、遥控器、冰箱、充电家用小型电器(例如豆浆机、扫地机器人)等。车载式电子产品如为车载导航仪、车载高密度数字视频光盘等。金融终端产品如为自动取款机、自助办理业务的终端等。通信电子产品如为服务器、存储器、基站等通信设备。
本申请的实施例对上述电子设备的具体形式不做特殊限制。以下实施例为了方便说明，均是以电子设备为手机为例进行举例说明。
图1为根据一些实施例的电子设备的结构图。
如图1所示，电子设备1主要包括盖板11、显示屏12、中框13以及后壳14。后壳14和显示屏12分别位于中框13的两侧，且中框13和显示屏12设置于后壳14内，盖板11设置在显示屏12远离中框13的一侧，显示屏12的显示面朝向盖板11。
其中，显示屏12可以是液晶显示屏(Liquid Crystal Display，LCD)，在此情况下，液晶显示屏包括液晶显示面板和背光模组，液晶显示面板设置在盖板11和背光模组之间，背光模组用于为液晶显示面板提供光源。上述显示屏12也可以为有机发光二极管(Organic Light Emitting Diode，OLED)显示屏。由于OLED显示屏为自发光显示屏，因而无需设置背光模组。
上述中框13包括承载板131以及绕承载板131一周的边框132。电子设备1中还包括设置于承载板131上的电路板15、电池、摄像头等电子元器件。
如图1所示，上述电子设备1还可以包括设置于电路板15上的芯片10，该芯片10与电路板15电连接。
上述芯片10可包括处理器芯片、存储芯片、射频芯片、射频功率放大器芯片、电源管理芯片、音频处理器芯片、触摸屏控制芯片、图像传感器芯片、充电保护芯片等。
本申请的实施例所提供的芯片10，可以是裸芯片，也可以是经过封装的芯片，封装的芯片中可包括一个或多个裸芯片。本申请的以下实施例以芯片10为二维的裸芯片为例进行说明。
图2为相关技术中的芯片的结构图。
参见图2，芯片10＇包括基板20＇，以及层叠设置于基板20＇上的转接层L＇和重新布线层27＇。
其中，基板20＇包括衬底G＇，以及设置于衬底G＇上的电子元件T＇。
示例性地，电子元件T＇可包括晶体管、电容器、电感器等。图2中的电子元件T＇以晶体管为例进行说明，晶体管包括栅极G、源极S和漏极D。
继续参见图2，转接层L＇包括层叠设置于基板20＇上的第一介质层21＇和第二介质层23＇，贯穿第一介质层21＇的导电图案22＇，以及贯穿第二介质层23＇的导电柱24＇。
其中，导电图案22＇的一端与电子元件T＇电连接，例如，晶体管的栅极G、源极S和漏极D分别与一个导电图案22＇对应且电连接。
导电柱24＇的一端与导电图案22＇的另一端电连接。需要说明的是，转接层L＇还包括围绕在导电柱24＇侧面和底面的粘结层26＇，粘结层26＇可用于粘附导电柱24＇，以提高导电柱24＇与第二介质层23＇之间的连接强度。
继续参见图2，重新布线层27＇中包括多个导电层，多个导电层中位于最下方的导电层与导电柱24＇电连接。位于最上方的导电层暴露于重新布线层27＇的表面，可用于连接功能器件，例如，位于最上方的导电层可用作连接功能器件的焊盘。
上述芯片10＇在工作过程中，电子元件T＇中的电信号可依次经导电图案22＇、导电柱24＇传输至重新布线层27＇的导电层，进而，该电信号可通过重新布线层27＇中位于最上方的导电层传输至与其连接的功能器件。
在制备上述芯片10＇的过程中，通常先在衬底G＇上制备电子元件T＇以形成基板20＇，然后在基板20＇上形成第一介质层21＇，并形成贯穿第一介质层21＇的导电图案22＇。之后，在第一介质层21＇远离基板20＇的一侧形成第二介质层23＇，并形成贯穿第二介质层23＇的导电柱24＇，最后在第二介质层23＇远离基板20＇的一侧形成重新布线层27＇。
其中，在形成贯穿第二介质层23＇的导电柱24＇的过程中，需要先形成贯穿第二介质层23＇的过孔，该过孔暴露导电图案22＇，然后在该过孔的侧壁和底部形成粘结层26＇，最后，可采用化学气相沉积(Chemical Vapor Deposition，CVD)工艺，在过孔中沉积导电材料以形成导电柱24＇。
本申请的发明人经研究发现，参考图2，在过孔内沉积导电材料的过程中，导电材料在过孔的侧壁和底部同时沉积，且在侧壁与底部之间的连接处(拐角处)沉积的速率较快，进而，在过孔的顶部导电材料封闭的情况下，过孔中导电材料的内部会产生空隙25＇，从而使导电柱24＇的内部具有空隙25＇，这会增大导电柱24＇的电阻，导致电信号在导电柱24＇上传输的过程中产生损失(例如，电信号的电压值下降)，进而影响芯片10＇的性能。
并且，由于粘结层26＇具有一定的厚度，会占据过孔的空间，导致导电柱24＇的直径减小、径向横截面的面积减小，这也会增大导电柱24＇的电阻。
此外，导电图案22＇与导电柱24＇之间被粘结层26＇隔开，通常情况下，粘结层26＇的材料采用钛或氮化钛，但钛或氮化钛的导电性能较差，会增加导电图案22＇和导电柱24＇与粘结层26＇的接触电阻，导致电信号从导电图案22＇经粘结层26＇传输至导电柱24＇的过程中产生损失，影响芯片10＇的性能。
为解决上述问题，本申请的一些实施例提供了一种芯片，图3为根据一些实施例的一种芯片的结构图。
参见图3，芯片10包括基板20，以及层叠设置于基板20上的转接层L和重新布线层27。
其中，基板20包括衬底G，以及设置于衬底G上的电子元件T。
示例性地，电子元件T可包括晶体管、电容器、电感器等。图3中的电子元件T以晶体管为例进行说明，晶体管包括栅极G、源极S和漏极D。
参见图3，转接层L包括层叠设置于基板20上的多个介质层，例如，多个介质层可包括第一介质层21、第二介质层231、第三介质层232和第四介质层233，以及贯穿第一介质层21的第一导电图案22，贯穿第二介质层231、第三介质层232和第四介质层233的导电柱24。
需要说明的是，第一导电图案22包括多个，第一介质层21可作为多个第一导电图案22之间的介电层。例如，第一介质层21的材料可包括等离子体增强氧化物(Plasma Enhanced Oxide，PEOX)。
并且，芯片10中电子元件T还可包括高阻结构(图3中未示出，例如，高阻结构可以是电阻器)，第二介质层231可作为刻蚀形成高阻结构的停止层。例如，第二介质层231的材料可包括氮化硅。
第三介质层232可作为刻蚀第四介质层233的停止层。例如，第三介质层232的材料可与第二介质层231的材料相同，即第三介质层232的材料也包括氮化硅。又例如，第三介质层232的材料也可与第二介质层231的材料不相同，本申请的实施例对此不做限定。
此外，导电柱24包括多个，第二介质层231、第三介质层232和第四介质层233可共同作为多个导电柱24之间的介电层。其中，第四介质层233的材料例如可包括氧化硅。
参见图3，第一导电图案22的一端与电子元件T电连接，例如，晶体管的栅极G、源极S和漏极D分别与一个第一导电图案22对应且电连接。第一导电图案22的另一端与导电柱24电连接。
参见图3，导电柱24包括相连接的接触部24a和导电部24b，接触部24a与第一导电图案22接触且电连接，导电部24b贯穿第二介质层231、第三介质层232和第四介质层233。其中，导电部24b与接触部24a相连的端面在基板20上的正投影M1，位于接触部24a与导电部24b相连的端面在基板20上的正投影M2范围内，例如，导电柱24的外形与“铆钉”的外形类似，导电部24b作为“铆钉”的钉杆，接触部24a作为“铆钉”的钉帽。
继续参见图3，重新布线层27中包括多个导电层，例如，多个导电层包括依次远离基板20的第一导电层271、第二导电层272和第三导电层273。
其中，第一导电层271包括第二导电图案27a，导电柱24远离第一导电图案22的一端与第二导电图案27a电连接。第二导电层272包括转接图案27b，转接图案27b与第二导电图案27a电连接。第三导电层273包括焊盘27c，焊盘27c与转接图案27b电连接，且焊盘27c暴露于重新布线层27的表面，可用于焊接功能器件。
本申请的一些实施例还提供了上述芯片10的制备方法，图4A～图4J为根据一些实施例的制备芯片的各步骤图，该芯片10的制备方法包括如下S10～S19：
S10：参见图4A，形成基板20，在基板20上形成第一介质层21，形成贯穿第一介质层21的第一导电图案22。然后，在第一介质层21远离基板20的一侧依次形成第二介质层231、第三介质层232和第四介质层233。
示例性地，第一导电图案22的材料可包括钴。
S11：参见图4B，形成贯穿第四介质层233的第一预制孔H1，沿垂直于基板20 的方向Z，多个第一预制孔H1与多个第一导电图案22相对应，且每个第一预制孔H1位于对应的第一导电图案22的上方。
S12：参见图4B和图4C，经由第一预制孔H1，刻蚀第二介质层231和第三介质层232，并去除刻蚀副产物，以形成贯穿第二介质层231、第三介质层232和第四介质层233的接触孔H2，接触孔H2暴露第一导电图案22。
S13：参见图4D，采用湿法清洗工艺，利用清洗液L1深度去除刻蚀副产物。
S14：参见图4E，采用回刻工艺，刻蚀液L2经由接触孔H2与第一导电图案22接触，刻蚀第一导电图案22以形成凹槽220。并且，接触孔H2在基板20上的正投影，位于凹槽220在基板20上的正投影范围内，即接触孔H2的孔径要小于凹槽220的开口的直径。
S15：参见图4F，采用选择性沉积工艺，在凹槽220和接触孔H2内沉积导电材料，以形成初始导电柱240。
在一些示例中，在接触孔H2内沉积导电材料之前，需要对接触孔H2和第一导电图案22进行表面处理，以去除附着在接触孔H2的内壁的化学残余物和悬挂键，以及附着在第一导电图案22表面的化学残余物和悬挂键，以暴露接触孔H2内壁的非金属材料，以及第一导电图案22表面的金属材料。
进而，在接触孔H2内沉积导电材料的过程中，导电材料在金属材料表面的沉积速率，大于导电材料在非金属材料表面的沉积速率，即，导电材料在第一导电图案22表面的沉积速率，大于导电材料在接触孔H2内壁的沉积速率，实现了导电材料的“选择性沉积”。这样，在接触孔H2的顶部导电材料封闭之前，接触孔H2内已经填满导电材料，可避免接触孔H2中导电材料的内部产生空隙，从而避免初始导电柱240的内部产生空隙，有利于减小初始导电柱240的电阻。
需要说明的是，上述“化学残余物”可以是在形成接触孔H2的过程中残留下的化学物质；“悬挂键”例如可以是没有电子能配对的化学键。
对接触孔H2和第一导电图案22进行表面处理，“表面处理”的方式例如可包括加热处理、等离子体处理、通入还原性气体(例如氢气)处理、通入氧化性气体(例如氧气和一氧化二氮)处理、通入惰性气体处理等方式。
如图4F所示，初始导电柱240与接触孔H2的侧壁之间会存在缝隙，为消除该缝隙，可采用如下S16：
S16：参见图4G，采用离子注入工艺，向第二介质层231、第三介质层232和第四介质层233中注入离子，使第二介质层231、第三介质层232和第四介质层233膨胀，从而减小贯穿这三者的接触孔H2的孔径，缩小初始导电柱240与接触孔H2侧壁之间的缝隙。
示例性地，可向接触孔H2中注入锗离子。
S17：参见图4H，在第四介质层233远离基板20的一侧形成保护层28，保护层28的材料例如可包括氮化钛。
采用金属氧化物化学气相沉积(Metal Oxide Chemical Vapor Deposition，MOCVD)工艺，在保护层28远离基板20的一侧形成牺牲层29。
S18：参见图4H和图4I，采用化学机械研磨工艺(Chemical Mechanical Polishing， CMP)，研磨牺牲层29、保护层28、初始导电柱240及第四介质层233远离基板20一侧的部分，形成导电柱24，并暴露导电柱24远离第一导电图案22的端部。
S19：参见图4J，在第四介质层233远离基板20的一侧形成重新布线层27。
本申请的上述实施例所提供的制备方法，通过刻蚀第一导电图案22以形成凹槽220，并在凹槽220和接触孔H2内沉积导电材料，以形成初始导电柱240。由于接触孔H2在基板20上的正投影，位于凹槽220在基板20上的正投影范围内，即接触孔H2的孔径要小于凹槽220的开口的直径，因此，初始导电柱240的外形与“铆钉”的外形类似。
进而，在研磨初始导电柱240的过程中，若研磨液沿初始导电柱240与接触孔H2侧壁的缝隙渗入，初始导电柱240的“钉帽”可用于阻挡研磨液，避免研磨液接触并腐蚀第一导电图案22。
本申请的一些实施例还提供了两种芯片，图5为根据一些实施例的一种芯片的结构图；图6为图5中的芯片在M处的局部放大图；图7为根据一些实施例的另一种芯片的结构图；图8为图7中的芯片在N处的局部放大图；图9为根据一些实施例的研磨导电柱的示意图。
参见图5，芯片10包括基板20，以及设置于基板20上的转接层L。
其中，基板20包括衬底G，以及设置于衬底G上的电子元件T。
示例性地，电子元件T可包括晶体管、电容器、电感器等。图5中的电子元件T以晶体管为例进行说明，晶体管包括栅极G、源极S和漏极D。
参见图5，转接层L包括第一导电图案22，第一导电图案22的一端与电子元件T电连接。
可以理解的是，在电子元件T为晶体管的情况下，晶体管的栅极G、源极S和漏极D分别与一个第一导电图案22对应且电连接，即第一导电图案22可作为晶体管的连接电极。
示例性地，第一导电图案22的材料可包括钴。
参见图5和图7，转接层L还包括堆叠层D，该堆叠层D包括依次层叠设置于第一导电图案22上的至少一个第一介质层21和至少一个第二介质层23。
示例性地，如图5所示，堆叠层D包括依次层叠设置于第一导电图案22上的一个第一介质层21和一个第二介质层23，即第二介质层23位于第一介质层21的远离第一导电图案22的一侧。
示例性地，如图7所示，堆叠层D包括多个第一介质层21和多个第二介质层23，多个第一介质层21和多个第二介质层23交替层叠设置。
参见图5，转接层L还包括导电柱24，该导电柱24贯穿堆叠层D，且一端与第一导电图案22电连接。
参见图6和图8，导电柱24包括相连接的至少一个第一导电部241和至少一个第二导电部242，其中，沿第一介质层21的厚度方向，第一导电部241贯穿第一介质层21；沿第二介质层23的厚度方向，第二导电部242贯穿第二介质层23。
示例性地，如图6所示，堆叠层D包括依次层叠设置于第一导电图案22上的一个第一介质层21和一个第二介质层23，在此情况下，导电柱24包括相连接的一个第 一导电部241和一个第二导电部242，其中，一个第一导电部241贯穿一个第一介质层21，一个第二导电部242贯穿一个第二介质层23。
示例性地，如图8所示，堆叠层D包括多个第一介质层21和多个第二介质层23，多个第一介质层21和多个第二介质层23交替层叠设置，在此情况下，导电柱24包括相连接的多个第一导电部241和多个第二导电部242，多个第一导电部241和多个第二导电部242交替相连。其中，每个第一导电部241贯穿一个第一介质层21，每个第二导电部242贯穿一个第二介质层23。
示例性地，导电柱24的第一导电部241和第二导电部242可以是一体成型的，并且，二者的材料均包括钨。
参见图6和图8，第一导电部241与第二导电部242相连的端面为第一导电部241的第一端面S1，第二导电部242与第一导电部241相连的端面为第二导电部242的第二端面S2。第二端面S2在参考面P上的正投影位于，第一端面S1在参考面P上的正投影范围内。
需要说明的是，“第一端面S1”为第一导电部241的端面，“第二端面S2”为第二导电部242的端面，第一导电部241的第一端面S1与第二导电部242的第二端面S2相连接，即第一端面S1与第二端面S2处于同一平面内。
并且，“参考面P”为第一导电图案22的靠近堆叠层D一侧表面所在的平面，可以理解为，参考面P可与基板20所在的平面平行。
本申请的上述实施例所提供的芯片10，不需要刻蚀第一导电图案22形成凹槽，而是通过导电柱24的外形设计，使第二导电部242的第二端面S2在参考面P上的正投影位于，第一导电部241的第一端面S1在参考面P上的正投影范围内，即沿平行于参考面P的方向，第一端面S1的边缘超出第二端面S2的边缘，使第一导电部241的侧面相对于第二导电部242的侧面凸出。
基于此，在制备芯片10的过程中，研磨导电柱24的远离第一导电图案22的一端，即使研磨液沿第二导电部242与第二介质层23之间的缝隙渗入，第一端面S1的超出第二端面S2边缘的部分也可阻挡研磨液继续下渗，避免研磨液接触并腐蚀第一导电图案22，从而保证导电柱24与第一导电图案22之间互连的稳定性，提高芯片10的可靠性。
并且，参考图6和图9，在研磨导电柱24的过程中，导电柱24的远离第一导电图案22的一端受到摩擦力会产生扭矩，导电柱24会在堆叠层D内移动，甚至从堆叠层D中脱出。通过上述导电柱24的外形设计，第一端面S1的超出第二端面S2边缘的部分与第二介质层23相抵，可限制导电柱24的移动，从而可避免导电柱24从堆叠层D中脱出，避免芯片10出现可靠性问题。
此外，导电柱24与第一导电图案22之间不需要设置粘结层，而是直接与第一导电图案22电连接，可降低导电柱24与第一导电图案22的接触电阻，减小电信号从第一导电图案22传输至导电柱24的过程中产生的损失，从而提高芯片10的性能。
经验证，相较于相关技术中的芯片10＇，本申请的上述实施例所提供的芯片10，电信号传输的损失降低至少50％，芯片10的性能随之提升5％左右。
在一些实施例中，如图5～图8所示，堆叠层D具有接触孔H3，该接触孔H3包 括相连通的至少一个第一子接触孔H31和至少一个第二子接触孔H32，第一子接触孔H31贯穿第一介质层21，第二子接触孔H32贯穿第二介质层23。
示例性地，如图5和图6所示，堆叠层D包括依次层叠设置于第一导电图案22上的一个第一介质层21和一个第二介质层23，在此情况下，接触孔H3包括相连通的一个第一子接触孔H31和一个第二子接触孔H32。
示例性地，如图7和图8所示，堆叠层D包括多个第一介质层21和多个第二介质层23，多个第一介质层21和多个第二介质层23交替层叠设置，在此情况下，接触孔H3包括相连通的多个第一子接触孔H31和多个第二子接触孔H32，第一子接触孔H31和第二子接触孔H32交替相连。
如图6和图8所示，第一导电部241位于第一子接触孔H31内，第二导电部242位于第二子接触孔H32内，其中，第一子接触孔H31与第二子接触孔H32相连的开口为第一子接触孔H31的第一开口K1，第二子接触孔H32与第一子接触孔H31相连的开口为第二子接触孔H32的第二开口K2，第二开口K2在参考面P上的正投影位于第一开口K1在参考面P上的正投影范围内。
本申请的上述实施例中，通过对堆叠层D中的接触孔H3的形状设计，使第二子接触孔H32的第二开口K2在参考面P上的正投影位于，第一子接触孔H31的第一开口K1在参考面P上的正投影范围内，即沿平行于参考面P的方向，第一开口K1的边缘超出第二开口K2的边缘，第一子接触孔H31的侧壁，相对于第二子接触孔H32的侧壁更远离导电柱24的轴线A，第一子接触孔H31的侧壁与第二子接触孔H32的侧壁不处于同一平面内。这样，在研磨导电柱24的过程中，即使研磨液沿第二子接触孔H32的侧壁渗入，由于第一子接触孔H31的侧壁与第二子接触孔H32的侧壁不处于同一平面内，研磨液不易从第二子接触孔H32的侧壁下渗至第一子接触孔H31的侧壁，避免研磨液接触并腐蚀第一导电图案22，从而提高芯片10的可靠性。
在一些实施例中，如图5和图7所示，堆叠层D具有接触孔H3，导电柱24位于接触孔H3内，且导电柱24的侧面的形状与接触孔H3的侧壁的形状相适配。
可以理解的是，在制备芯片10的过程中，在堆叠层D中形成接触孔H3，然后在接触孔H3内沉积导电材料，导电材料填充接触孔H3以形成导电柱24，因此，导电柱24的侧面的形状与接触孔H3的侧壁的形状相适配。
基于上述设置方式，有利于减小导电柱24的侧面与接触孔H3的侧壁之间的缝隙，在研磨导电柱24的过程中，可改善研磨液沿导电柱24与接触孔H3之间的缝隙下渗的问题。
在一些实施例中，如图6和图8所示，第一介质层21的材料与第二介质层23的材料不同。
可以理解的是，第一介质层21的材料与第二介质层23的材料不同，二者的刻蚀选择比不同。
在刻蚀堆叠层D形成接触孔H3的过程中，需要先逐层刻蚀第一介质层21和第二介质层23形成预制孔。然后，调整第一介质层21和第二介质层23的刻蚀选择比，满足第一介质层21的刻蚀速率远大于第二介质层23的刻蚀速率，例如，可通过调整二者的刻蚀选择比，刻蚀第一介质层21的同时不会刻蚀第二介质层23，从而使第一子 接触孔H31的侧壁，相对于第二子接触孔H32的侧壁更远离导电柱24的轴线A。
示例性地，第一介质层21和第二介质层23的材料为，氧化硅、氮化硅、氮氧化硅、碳氧氮化硅、氮掺杂碳化物、氧掺杂碳化物中的任意两种，保证第一介质层21和第二介质层23的材料不同即可。
在一些实施例中，如图6和图8所示，在同一刻蚀条件下，第一介质层21的刻蚀速率与第二介质层23的刻蚀速率不同。
可以理解的是，在同一刻蚀条件下，第一介质层21的刻蚀速率与第二介质层23的刻蚀速率不同，因此，二者的刻蚀选择比不同。
在刻蚀堆叠层D形成接触孔H3的过程中，需要先逐层刻蚀第一介质层21和第二介质层23形成预制孔。然后，调整第一介质层21和第二介质层23的刻蚀选择比，满足第一介质层21的刻蚀速率远大于第二介质层23的刻蚀速率，例如，可通过调整二者的刻蚀选择比，刻蚀第一介质层21的同时不会刻蚀第二介质层23，从而使第一子接触孔H31的侧壁，相对于第二子接触孔H32的侧壁更远离导电柱24的轴线A。
在一些实施例中，如图5和图6所示，堆叠层D包括一个第一介质层21和一个第二介质层23，导电柱24包括一个第一导电部241和一个第二导电部242。
可以理解的是，在刻蚀堆叠层D形成接触孔H3的过程中，先刻蚀第二介质层23形成过孔，刻蚀第一介质层21形成过孔，然后，沉积导电材料，导电材料填充第二介质层23的过孔，形成贯穿第二介质层23的第二导电部242；导电材料填充第一介质层21的过孔，形成贯穿第一介质层21的第一导电部241。因此，在堆叠层D包括一个第一介质层21和一个第二介质层23的情况下，导电柱24包括一个第一导电部241和一个第二导电部242。
本申请的上述实施例，通过设置导电柱24具有一个第一导电部241和一个第二导电部242，使第一导电部241的第一端面S1的边缘，超出第二导电部242的第二端面S2的边缘。在研磨导电柱24的过程中，即使研磨液沿第二导电部242与第二介质层23之间的缝隙渗入，第一端面S1的超出第二端面S2边缘的部分也可阻挡研磨液继续下渗，避免研磨液接触并腐蚀第一导电图案22，从而提高芯片10的可靠性。
在一些实施例中，如图7和图8所示，堆叠层D包括交替设置的多个第一介质层21和多个第二介质层23，导电柱24包括交替相连的多个第一导电部241和多个第二导电部242。
可以理解的是，在刻蚀堆叠层D形成接触孔H3的过程中，依次刻蚀第二介质层23、第一介质层21、第二介质层23、第一介质层21……，然后，沉积导电材料，导电材料填充每个第二介质层23的过孔，形成多个第二导电部242；导电材料填充每个第一介质层21的过孔，形成多个第一导电部241。
因此，在堆叠层D包括多个第一介质层21和多个第二介质层23的情况下，导电柱24包括多个第一导电部241和多个第二导电部242。并且，第一介质层21的数量与第一导电部241的数量相等，第二介质层23的数量与第二导电部242的数量相等。
本申请的上述实施例，通过设置导电柱24具有多个第一导电部241和多个第二导电部242，并且，相邻的第一导电部241和第二导电部242中，第一导电部241的第一端面S1的边缘，超出第二导电部242的第二端面S2的边缘。这样，在研磨导电柱 24的过程中，多个第一导电部241与其上方的第二导电部242相连的第一端面S1，均可阻挡研磨液继续下渗，可进一步降低研磨液下渗的风险，避免研磨液接触并腐蚀第一导电图案22，从而进一步提高芯片10的可靠性。
并且，参考图8和图9，在研磨导电柱24的过程中，导电柱24的远离第一导电图案22的一端受到摩擦力会产生扭矩，导电柱24会在接触孔H3内移动，甚至从堆叠层D中脱出。通过设置导电柱24包括交替相连的多个第一导电部241和多个第二导电部242，导电柱24的外形近似螺纹结构，多个第一导电部241的第一端面S1与多个第二介质层23相抵，可进一步限制导电柱24移动，从而可避免导电柱24从堆叠层D中脱出，避免芯片10出现可靠性问题。
此外，参考图9，即使导电柱24在接触孔H3内移动，使导电柱24的局部与接触孔H3的侧壁产生缝隙。通过设置导电柱24具有多个第一导电部241和多个第二导电部242，多个第一导电部241和多个第二导电部242可与多个第一介质层21和多个第二介质层23形成多处密封，例如，图9中示出的a、b、c密封处，保证沿导电柱24的周向均形成密封，避免研磨液接触并腐蚀第一导电图案22。
在一些实施例中，如图6和图8所示，第一导电部241的平均直径大于第二导电部242的平均直径。
可以理解的是，沿导电柱24的轴线A方向，第一导电部241和第二导电部242的直径均是变化的。“第一导电部241的平均直径”可以是，第一导电部241的最大直径与最小直径的和的一半，同理，“第二导电部242的平均直径”可以是，第二导电部242的最大直径与最小直径的和的一半。
通过设置第一导电部241的平均直径大于第二导电部242的平均直径，使第一导电部241与第二导电部242相连的一端，相对于第二导电部242与第一导电部241相连的一端凸出。这样，在研磨导电柱24的过程中，第一导电部241的凸出的端部可阻挡研磨液继续下渗，避免研磨液接触并腐蚀第一导电图案22。
在一些实施例中，如图6和图8所示，第一导电部241的形状为圆柱体或圆台，第二导电部242的形状为圆柱体或圆台。在另一些实施例中，第一导电部241和第二导电部242的形状还可以为棱柱，例如，三棱柱、四棱柱或五棱柱等，本申请的实施例不限于此。
在一些实施例中，如图5和图7所示，芯片10还包括重新布线层27，重新布线层27中包括多个导电层，例如，多个导电层包括依次设置于堆叠层D远离第一导电图案22一侧的第一导电层271、第二导电层272和第三导电层273。
其中，第一导电层271包括第二导电图案27a，导电柱24远离第一导电图案22的一端与第二导电图案27a电连接，从而通过导电柱24实现了第一导电图案22与第二导电图案27a之间的互连及信号传输。
第二导电层272包括转接图案27b，转接图案27b与第二导电图案27a电连接。
第三导电层273包括焊盘27c，焊盘27c与转接图案27b电连接，且焊盘27c暴露于重新布线层27的表面，可用于焊接功能器件。
本申请的一些实施例还提供了一种芯片，图10为根据一些实施例的芯片的结构图。
参见图10，堆叠层D还包括第三介质层30，该第三介质层30位于第一导电图案 22与最靠近第一导电图案22的第一介质层21之间。并且，导电柱24还包括第三导电部243，该第三导电部243贯穿第三介质层30，且与最靠近第一导电图案22的第一导电部241电连接。
其中，第一导电部241与第三导电部243相连的端面为第三端面S3，第三导电部243与第一导电部241相连的端面为第四端面S4，第四端面S4在参考面P上的正投影位于第三端面S3在参考面P上的正投影范围内。
可以理解的是，参考图10，沿第一导电图案22指向第二导电图案27a的方向Z，导电柱24的直径变化趋势为小、大、小、大……，本申请的实施例不限于此。
例如，参考图8，沿方向Z，导电柱24的直径变化趋势为大、小、大、小……。
示例性地，第三介质层30的材料与第二介质层23的材料相同，和/或，在同一刻蚀条件下，第三介质层30的刻蚀速率与第二介质层23的刻蚀速率相同。
可以理解的是，第三介质层30的材料与第二介质层23的材料相同，二者的刻蚀选择比不同，因此，在同一刻蚀条件下，第三介质层30的刻蚀速率与第二介质层23的刻蚀速率相同。
本申请的一些实施例提供了一种芯片的制备方法，图11A～图11E为根据一些实施例的制备一种芯片的各流程图；图12A～图12K为根据一些实施例的制备一种芯片的各步骤图。
参见图11A，芯片10的制备方法包括如下S10～S30：
S10：如图12A所示，形成第一导电图案22。
示例性地，提供一基板20，该基板20包括衬底G，以及设置于衬底G上的电子元件T。然后，在基板20上形成第一导电图案22，该第一导电图案22与电子元件T电连接。例如，电子元件T为晶体管，晶体管包括栅极G、源极S和漏极D，晶体管的栅极G、源极S和漏极D分别与一个第一导电图案22对应且电连接。
S20：如图12B所示，在第一导电图案22上形成堆叠层D，该堆叠层D包括依次层叠设置的至少一个第一介质层21和至少一个第二介质层23。
示例性地，参见图12B，堆叠层D包括依次层叠设置的一个第一介质层21和一个第二介质层23。
S30：如图12C～图12J所示，形成贯穿堆叠层D的导电柱24，导电柱24的一端与第一导电图案22电连接。
结合图6，导电柱24包括相连接的至少一个第一导电部241和至少一个第二导电部242，第一导电部241贯穿第一介质层21，第二导电部242贯穿第二介质层23。其中，第一导电部241与第二导电部242相连的端面为第一端面S1，第二导电部242与第一导电部241相连的端面为第二端面S2。第二端面S2在参考面P上的正投影位于，第一端面S1在参考面P上的正投影范围内。
示例性地，参见图6，导电柱24包括相连接的一个第一导电部241和一个第二导电部242，一个第一导电部241贯穿一个第一介质层21，一个第二导电部242贯穿一个第二介质层23。
在一些示例中，参见图11B，上述S30：形成贯穿堆叠层D的导电柱24，可包括如下S301～S302：
S301：如图12C～图12F所示，形成贯穿堆叠层D的接触孔H3。
示例性地，参见图11C，在堆叠层D包括一个第一介质层21和一个第二介质层23的情况下，上述S301还包括如下S3011～S3014：
S3011：如图12C所示，形成掩膜层R，该掩膜层R位于堆叠层D上。
可以理解的是，掩膜层R具有开口，可暴露堆叠层D，以便于后续通过掩膜层R刻蚀堆叠层D。例如，掩膜层R可以为光刻胶层，可采用曝光显影工艺，在掩膜层R上形成开口。
S3012：如图12D所示，基于掩膜层R，刻蚀第二介质层23，形成贯穿第二介质层23的第二预制孔H4，该第二预制孔H4暴露第一介质层21。
S3013：如图12D和图12E所示，去除掩膜层R。
例如，可采用剥离液，将掩膜层R从堆叠层D上去除。
S3014：如图12E和图12F所示，经由第二预制孔H4，刻蚀第一介质层21，以暴露第一导电图案22。
需要说明的是，在去除掩膜层R的过程中，所使用的剥离液为酸性液体，其对金属具有腐蚀作用，因此，在刻蚀第一介质层21之前，便采用剥离液将掩膜层R去除，然后再刻蚀第一介质层21以暴露第一导电图案22，可避免剥离液接触并腐蚀第一导电图案22。
并且，经由第二预制孔H4刻蚀第一介质层21之后，形成贯穿堆叠层D的接触孔H3，需要清洗接触孔H3，例如，采用湿法清洗工艺，利用清洗液去除刻蚀副产物，以保证第一导电图案22的暴露。并且，需要对接触孔H3和第一导电图案22进行表面处理，以去除附着在接触孔H3的内壁的化学残余物和悬挂键，以及附着在第一导电图案22表面的化学残余物和悬挂键。
S302：如图12G～图12J所示，在接触孔H3内填充导电材料，形成导电柱24。
示例性地，如图12G所示，可采用选择性生长工艺，在接触孔H3内填充导电材料形成初始导电柱240，可避免接触孔H3中导电材料的内部产生空隙，从而避免初始导电柱240的内部产生空隙。
示例性地，参见图11D，在接触孔H3内填充导电材料之后，芯片10的制备方法还包括如下S303～S305：
S303：如图12H所示，形成保护层28，该保护层28覆盖堆叠层D。例如，保护层28的材料可包括氮化钛。
S304：如图12I所示，形成牺牲层29，该牺牲层29覆盖保护层28。例如，可采用金属氧化物化学气相沉积工艺，形成牺牲层29。牺牲层29的材料可与初始导电柱240的材料相同，例如，二者的材料均包括钨，从而在后续研磨的过程中，有利于提高研磨的均一性，提高表面研磨的质量。
S305：如图12I和图12J所示，研磨牺牲层29、保护层28及堆叠层D远离第一导电图案22一侧的部分，以暴露导电柱24远离第一导电图案22的端部。例如，可采用化学机械研磨工艺，研磨牺牲层29、保护层28及堆叠层D远离第一导电图案22一侧的部分。
可以理解的是，在研磨的过程中，会去除牺牲层29、保护层28以及堆叠层D远 离第一导电图案22一侧的部分，还会去除初始导电柱240远离第一导电图案22一端的部分，最后，会暴露导电柱24远离第一导电图案22的端部，并且，研磨可使堆叠层D远离第一导电图案22一侧的表面平坦化，以便于后续在堆叠层D的表面上制备第二导电图案27a。
并且，在研磨的过程中，保护层28可起到阻挡研磨液的作用，可防止研磨液从导电柱24与接触孔H3的缝隙下渗，从而避免研磨液接触并腐蚀第一导电图案22。
在一些示例中，参见图11E，在形成导电柱24之后，芯片10的制备方法还包括如下S40：
S40：如图12K所示，形成第二导电图案27a，第二导电图案27a位于堆叠层D上，导电柱24远离第一导电图案22的一端与第二导电图案27a电连接。通过导电柱24实现了第一导电图案22与第二导电图案27a之间的互连及信号传输。
本申请的上述实施例所提供的制备方法，制备得到的导电柱24，其第二导电部242的第二端面S2在参考面P上的正投影位于，第一导电部241的第一端面S1在参考面P上的正投影范围内，即沿平行于参考面P的方向，第一端面S1的边缘超出第二端面S2的边缘，使第一导电部241的侧面相对于第二导电部242的侧面凸出。
基于此，在后续研磨导电柱24的过程中，即使研磨液沿第二导电部242与第二介质层23之间的缝隙渗入，第一端面S1的超出第二端面S2边缘的部分也可阻挡研磨液继续下渗，避免研磨液接触并腐蚀第一导电图案22，从而保证导电柱24与第一导电图案22之间互连的稳定性，提高芯片10的可靠性。
并且，在研磨导电柱24的过程中，导电柱24的远离第一导电图案22的一端受到摩擦力会产生扭矩，导电柱24会在堆叠层D中移动，甚至从堆叠层D中脱出。通过上述导电柱24的制备，第一端面S1的超出第二端面S2边缘的部分与第二介质层23相抵，可限制导电柱24的移动，从而可避免导电柱24从堆叠层D中脱出，避免芯片10出现可靠性问题。
以上制备方法所应用的芯片10，芯片10的堆叠层D包括依次层叠设置的一个第一介质层21和一个第二介质层23。
本申请的一些实施例还提供了一种芯片的制备方法，该制备方法与上述制备方法类似，区别在于该制备方法所应用的芯片10，芯片10的堆叠层D包括交替设置的多个第一介质层21和多个第二介质层23。
图13A～图13E为根据一些实施例的制备另一种芯片的各流程图；图14A～图14L为根据一些实施例的制备另一种芯片的各步骤图。
参见图13A，芯片10的制备方法包括如下S10＇～S30＇：
S10＇：如图14A所示，形成第一导电图案22。
示例性地，提供一基板20，该基板20包括衬底G，以及设置于衬底G上的电子元件T。例如，电子元件T为晶体管，晶体管包括栅极G、源极S和漏极D。
S20＇：如图14B所示，在第一导电图案22上形成堆叠层D，该堆叠层D包括交替设置的多个第一介质层21和多个第二介质层23。
S30＇：如图14C～图14K所示，形成贯穿堆叠层D的导电柱24，导电柱24的一端与第一导电图案22电连接。
结合图8，导电柱24包括交替相连的多个第一导电部241和多个第二导电部242，每个第一导电部241贯穿一个第一介质层21，每个第二导电部242贯穿一个第二介质层23。其中，第一导电部241与第二导电部242相连的端面为第一端面S1，第二导电部242与第一导电部241相连的端面为第二端面S2。第二端面S2在参考面P上的正投影位于，第一端面S1在参考面P上的正投影范围内。
在一些示例中，参见图13B，上述S30＇：形成贯穿堆叠层D的导电柱24，可包括如下S301＇～S302＇：
S301＇：如图14C～图14G所示，形成贯穿堆叠层D的接触孔H3。
示例性地，参见图13C，上述S301＇可包括如下S3011＇～S3015＇：
S3011＇：如图14C所示，形成掩膜层R，该掩膜层R位于堆叠层D上。
可以理解的是，掩膜层R具有开口，可暴露堆叠层D，以便于后续通过掩膜层R刻蚀堆叠层D。例如，掩膜层R可以为光刻胶层，可采用曝光显影工艺，在掩膜层R上形成开口。
S3012＇：如图14D所示，基于掩膜层R，刻蚀堆叠层D的目标膜层，形成贯穿目标膜层的第二预制孔H4。
需要说明的是，参考图14D，堆叠层D的多个第一介质层21中最靠近第一导电图案22的第一介质层21为“设定第一介质层21a”。基于此，堆叠层D的“目标膜层”是指，堆叠层D中位于设定第一介质层21a上方的膜层。
并且，上述第二预制孔H4暴露设定第一介质层21a。
S3013＇：如图14E所示，经由第二预制孔H4，刻蚀目标膜层中的第一介质层21靠近第二预制孔H4的侧面，形成凹槽H5。
S3014＇：如图14E和图14F所示，去除掩膜层R。
例如，可采用剥离液，将掩膜层R从堆叠层D上去除。
S3015＇：如图14F和图14G所示，经由第二预制孔H4，刻蚀设定第一介质层21a，以暴露第一导电图案22。
需要说明的是，在刻蚀设定第一介质层21a之前，便采用剥离液将掩膜层R去除，然后再刻蚀设定第一介质层21a以暴露第一导电图案22，可避免剥离液接触并腐蚀第一导电图案22。
并且，经由第二预制孔H4刻蚀设定第一介质层21a之后，形成贯穿堆叠层D的接触孔H3，需要清洗接触孔H3，例如，采用湿法清洗工艺，利用清洗液去除刻蚀副产物，以保证第一导电图案22的暴露。并且，需要对接触孔H3和第一导电图案22进行表面处理，以去除附着在接触孔H3的内壁的化学残余物和悬挂键，以及附着在第一导电图案22表面的化学残余物和悬挂键。
S302＇：如图14H～图14K所示，在接触孔H3内填充导电材料，形成导电柱24。
示例性地，参见图13D，在接触孔H3内填充导电材料之后，芯片10的制备方法还包括如下S303＇～S305＇：
S303＇：如图14I所示，形成保护层28，该保护层28覆盖堆叠层D。例如，保护层28的材料可包括氮化钛。
S304＇：如图14J所示，形成牺牲层29，该牺牲层29覆盖保护层28。
S305＇：如图14J和图14K所示，研磨牺牲层29、保护层28及堆叠层D远离第一导电图案22一侧的部分，以暴露导电柱24远离第一导电图案22的端部。
在一些示例中，参见图13E，在形成导电柱24之后，芯片10的制备方法还包括如下S40＇：
S40＇：如图14L所示，形成第二导电图案27a，第二导电图案27a位于堆叠层D上，导电柱24远离第一导电图案22的一端与第二导电图案27a电连接。
本申请的上述实施例所提供的制备方法，制备得到的导电柱24，导电柱24具有多个第一导电部241和多个第二导电部242，并且，相邻的第一导电部241和第二导电部242中，第一导电部241的第一端面S1的边缘，超出第二导电部242的第二端面S2的边缘。这样，在研磨导电柱24的过程中，多个第一导电部241与其上方的第二导电部242相连的第一端面S1，均可阻挡研磨液继续下渗，可进一步降低研磨液下渗的风险，避免研磨液接触并腐蚀第一导电图案22，从而进一步提高芯片10的可靠性。
并且，通过设置导电柱24的外形近似螺纹结构，在研磨导电柱24的过程中，可进一步限制导电柱24移动，从而可避免导电柱24从堆叠层D中脱出，避免芯片10出现可靠性问题。
本申请的一些实施例所提供的电子设备1，包括上述任一实施例所提供的芯片10，其所能达到的有益效果可参考上文中芯片10的有益效果，此处不再赘述。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (20)

  1. 一种芯片，其特征在于，包括：
    第一导电图案；
    堆叠层，包括依次层叠设置于所述第一导电图案上的至少一个第一介质层和至少一个第二介质层；
    导电柱，贯穿所述堆叠层，且一端与所述第一导电图案电连接；所述导电柱包括相连接的至少一个第一导电部和至少一个第二导电部，所述第一导电部贯穿所述第一介质层，所述第二导电部贯穿所述第二介质层；
    其中，所述第一导电部与所述第二导电部相连的端面为，所述第一导电部的第一端面；所述第二导电部与所述第一导电部相连的端面为，所述第二导电部的第二端面；所述第二端面在参考面上的正投影位于所述第一端面在所述参考面上的正投影范围内，所述参考面为所述第一导电图案的靠近所述堆叠层一侧表面所在的平面。
  2. 根据权利要求1所述的芯片，其特征在于，所述堆叠层具有接触孔，所述接触孔包括相连通的至少一个第一子接触孔和至少一个第二子接触孔，所述第一子接触孔贯穿所述第一介质层，所述第二子接触孔贯穿所述第二介质层；
    所述第一导电部位于所述第一子接触孔内，所述第二导电部位于所述第二子接触孔内；
    其中，所述第一子接触孔与所述第二子接触孔相连的开口为，所述第一子接触孔的第一开口；所述第二子接触孔与所述第一子接触孔相连的开口为，所述第二子接触孔的第二开口；所述第二开口在所述参考面上的正投影位于所述第一开口在所述参考面上的正投影范围内。
  3. 根据权利要求1或2所述的芯片，其特征在于，所述第一介质层的材料与所述第二介质层的材料不同。
  4. 根据权利要求1～3中任一项所述的芯片，其特征在于，在同一刻蚀条件下，所述第一介质层的刻蚀速率与所述第二介质层的刻蚀速率不同。
  5. 根据权利要求4所述的芯片，其特征在于，所述第一介质层和所述第二介质层的材料为，氧化硅、氮化硅、氮氧化硅、碳氧氮化硅、氮掺杂碳化物、氧掺杂碳化物中的任意两种。
  6. 根据权利要求1～5中任一项所述的芯片，其特征在于，所述堆叠层包括一个所述第一介质层和一个所述第二介质层，所述导电柱包括一个所述第一导电部和一个所述第二导电部。
  7. 根据权利要求1～5中任一项所述的芯片，其特征在于，所述堆叠层包括交替设置的多个所述第一介质层和多个所述第二介质层，所述导电柱包括交替相连的多个所述第一导电部和多个所述第二导电部。
  8. 根据权利要求1～7中任一项所述的芯片，其特征在于，所述第一导电部的平均直径大于所述第二导电部的平均直径。
  9. 根据权利要求1～8中任一项所述的芯片，其特征在于，所述堆叠层还包括第三介质层，位于所述第一导电图案与最靠近所述第一导电图案的第一介质层之间；
    所述导电柱还包括第三导电部，贯穿所述第三介质层，且与最靠近所述第一导电 图案的第一导电部电连接；
    其中，所述第一导电部与所述第三导电部相连的端面为第三端面，所述第三导电部与所述第一导电部相连的端面为第四端面，所述第四端面在所述参考面上的正投影位于所述第三端面在所述参考面上的正投影范围内。
  10. 根据权利要求9所述的芯片，其特征在于，所述第三介质层的材料与所述第二介质层的材料相同。
  11. 根据权利要求1～10中任一项所述的芯片，其特征在于，所述堆叠层具有接触孔，所述导电柱位于所述接触孔内；
    所述导电柱的侧面的形状与所述接触孔的侧壁的形状相适配。
  12. 根据权利要求1～11中任一项所述的芯片，其特征在于，所述第一导电部的形状为圆柱体或圆台，所述第二导电部的形状为圆柱体或圆台。
  13. 根据权利要求1～12中任一项所述的芯片，其特征在于，所述芯片还包括第二导电图案，设置于所述堆叠层远离所述第一导电图案的一侧；
    所述导电柱远离所述第一导电图案的一端与所述第二导电图案电连接。
  14. 一种芯片的制备方法，其特征在于，包括：
    形成第一导电图案；
    在所述第一导电图案上形成堆叠层，所述堆叠层包括依次层叠设置的至少一个第一介质层和至少一个第二介质层；
    形成贯穿所述堆叠层的导电柱，所述导电柱的一端与所述第一导电图案电连接；所述导电柱包括相连接的至少一个第一导电部和至少一个第二导电部，所述第一导电部贯穿所述第一介质层，所述第二导电部贯穿所述第二介质层；
    其中，所述第一导电部与所述第二导电部相连的端面为第一端面，所述第二导电部与所述第一导电部相连的端面为第二端面，所述第二端面在参考面上的正投影位于所述第一端面在所述参考面上的正投影范围内。
  15. 根据权利要求14所述的制备方法，其特征在于，所述形成贯穿所述堆叠层的导电柱，包括：
    形成贯穿所述堆叠层的接触孔；
    在所述接触孔内填充导电材料，形成所述导电柱。
  16. 根据权利要求15所述的制备方法，其特征在于，所述堆叠层包括一个所述第一介质层和一个所述第二介质层；
    所述形成贯穿所述堆叠层的接触孔，包括：
    形成掩膜层，所述掩膜层位于所述堆叠层上；
    基于所述掩膜层，刻蚀所述第二介质层，形成贯穿所述第二介质层的预制孔；
    去除所述掩膜层；
    经由所述预制孔，刻蚀所述第一介质层，以暴露所述第一导电图案。
  17. 根据权利要求15所述的制备方法，其特征在于，所述堆叠层包括交替设置的多个所述第一介质层和多个所述第二介质层，多个所述第一介质层中最靠近所述第一导电图案的第一介质层为设定第一介质层；
    所述形成贯穿所述堆叠层的接触孔，包括：
    形成掩膜层，所述掩膜层位于所述堆叠层上；
    基于所述掩膜层，刻蚀所述堆叠层的目标膜层，形成贯穿所述目标膜层的预制孔；所述目标膜层为，所述堆叠层中位于所述设定第一介质层上方的膜层；
    经由所述预制孔，刻蚀所述目标膜层中的第一介质层靠近所述预制孔的侧面，形成凹槽；
    去除所述掩膜层；
    经由所述预制孔，刻蚀所述设定第一介质层，以暴露所述第一导电图案。
  18. 根据权利要求15～17中任一项所述的制备方法，其特征在于，所述在所述接触孔内填充导电材料之后，还包括：
    形成保护层，所述保护层覆盖所述堆叠层；
    形成牺牲层，所述牺牲层覆盖所述保护层；
    研磨所述牺牲层、所述保护层及所述堆叠层远离所述第一导电图案一侧的部分，以暴露所述导电柱远离所述第一导电图案的端部。
  19. 根据权利要求14～18中任一项所述的制备方法，其特征在于，所述形成所述导电柱之后，还包括：
    形成第二导电图案，所述第二导电图案位于所述堆叠层上，所述导电柱远离所述第一导电图案的一端与所述第二导电图案电连接。
  20. 一种电子设备，其特征在于，包括：
    电路板；
    如权利要求1～13中任一项所述的芯片，所述芯片与所述电路板电连接。
PCT/CN2022/093575 2022-05-18 2022-05-18 一种芯片及其制备方法、电子设备 WO2023220968A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
PCT/CN2022/093575 WO2023220968A1 (zh) 2022-05-18 2022-05-18 一种芯片及其制备方法、电子设备

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2022/093575 WO2023220968A1 (zh) 2022-05-18 2022-05-18 一种芯片及其制备方法、电子设备

Publications (1)

Publication Number Publication Date
WO2023220968A1 true WO2023220968A1 (zh) 2023-11-23

Family

ID=88834160

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2022/093575 WO2023220968A1 (zh) 2022-05-18 2022-05-18 一种芯片及其制备方法、电子设备

Country Status (1)

Country Link
WO (1) WO2023220968A1 (zh)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103582944A (zh) * 2011-06-02 2014-02-12 美光科技公司 导电结构、包含导电结构的系统及装置，及相关方法
US20150102461A1 (en) * 2013-10-16 2015-04-16 Conversant Intellectual Property Management Inc. Cost Effective Method of Forming Embedded DRAM Capacitor
CN112582341A (zh) * 2020-12-15 2021-03-30 上海集成电路研发中心有限公司 一种互连结构及其制造方法
CN112582340A (zh) * 2020-12-15 2021-03-30 上海集成电路研发中心有限公司 金属钴互连层和接触孔层的形成方法
CN112635396A (zh) * 2020-12-15 2021-04-09 上海集成电路研发中心有限公司 金属钴互连层和钨金属接触孔层的形成方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103582944A (zh) * 2011-06-02 2014-02-12 美光科技公司 导电结构、包含导电结构的系统及装置，及相关方法
US20150102461A1 (en) * 2013-10-16 2015-04-16 Conversant Intellectual Property Management Inc. Cost Effective Method of Forming Embedded DRAM Capacitor
CN112582341A (zh) * 2020-12-15 2021-03-30 上海集成电路研发中心有限公司 一种互连结构及其制造方法
CN112582340A (zh) * 2020-12-15 2021-03-30 上海集成电路研发中心有限公司 金属钴互连层和接触孔层的形成方法
CN112635396A (zh) * 2020-12-15 2021-04-09 上海集成电路研发中心有限公司 金属钴互连层和钨金属接触孔层的形成方法

Similar Documents

Publication Publication Date Title
CN110660930B (zh) 显示面板及其制备方法和显示装置
US8415804B2 (en) Semiconductor chip, method of fabricating the same, and stack module and memory card including the same
US9147640B2 (en) Semiconductor devices having back side bonding structures
US11114424B2 (en) Display substrate and method for preparing the same, and display device
US7544605B2 (en) Method of making a contact on a backside of a die
KR20160065631A (ko) Ｔｓｖ, 전면 범핑 패드 및 후면 범핑 패드를 갖는 반도체 소자
KR102008319B1 (ko) 반도체 소자의 형성 방법
CN110112205B (zh) 显示基板及其制造方法、有机发光二极管显示装置
KR20140133297A (ko) 점퍼 패턴 및 블로킹 패턴을 가진 반도체 소자
US8969971B2 (en) Semiconductor devices including a resistor structure
US9431341B2 (en) Semiconductor device having metal patterns and piezoelectric patterns
US20220255025A1 (en) Oled display panel and display device
CN107305840B (zh) 一种半导体器件及其制造方法和电子装置
CN113540201B (zh) 显示基板及显示装置
WO2023220968A1 (zh) 一种芯片及其制备方法、电子设备
WO2024032134A1 (zh) 芯片及其制备方法、电子设备
US7960273B2 (en) Metal interconnection of a semiconductor device and method of manufacturing the same
WO2024001801A1 (zh) 集成电路及其制备方法、电子设备
CN108573953B (zh) 一种半导体器件及其制备方法和电子装置
WO2024065853A1 (zh) 芯片及其制备方法、电子设备
US7759189B2 (en) Method of manufacturing a dual contact trench capacitor
WO2024065253A1 (zh) 芯片及其制备方法、电子设备
WO2023201598A1 (zh) 芯片及其制备方法、电子设备
TW201947746A (zh) 接觸結構、形成接觸結構的方法及記憶體裝置
WO2023230869A1 (zh) 芯片堆叠封装结构及其制备方法、电子设备

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 22942010

Country of ref document: EP

Kind code of ref document: A1