WO2024065253A1 - 芯片及其制备方法、电子设备 - Google Patents

芯片及其制备方法、电子设备 Download PDF

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Publication number
WO2024065253A1
WO2024065253A1 PCT/CN2022/122024 CN2022122024W WO2024065253A1 WO 2024065253 A1 WO2024065253 A1 WO 2024065253A1 CN 2022122024 W CN2022122024 W CN 2022122024W WO 2024065253 A1 WO2024065253 A1 WO 2024065253A1
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WIPO (PCT)
Prior art keywords
conductive
chip
layer
conductive pattern
dielectric layer
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PCT/CN2022/122024
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English (en)
French (fr)
Inventor
范荣伟
史志界
马野
黄伟川
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华为技术有限公司
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Priority to PCT/CN2022/122024 priority Critical patent/WO2024065253A1/zh
Publication of WO2024065253A1 publication Critical patent/WO2024065253A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates

Definitions

  • the present application relates to the field of semiconductor technology, and in particular to a chip and a method for preparing the same, and an electronic device.
  • the reduction in the size of the conductive patterns will increase the difficulty of interconnection and coupling between the conductive patterns.
  • the resistance, preparation process and other characteristics of the conductive pillars will have a direct impact on the interconnection and coupling effect and the yield of the chip.
  • the embodiments of the present application provide a chip and a method for manufacturing the same, and an electronic device, which are used to solve the problem of how to improve the interconnection coupling effect between conductive patterns in a chip.
  • a chip which may be a bare chip or a packaged chip.
  • the chip includes a dielectric layer and a conductive column penetrating the dielectric layer, a first conductive pattern, a second conductive pattern, and a filling layer.
  • the first conductive pattern and the second conductive pattern are respectively located on both sides of the dielectric layer; the two ends of the conductive column are respectively in contact with the first conductive pattern and coupled with the second conductive pattern; the filling layer is used to wrap at least part of the side surface of the conductive column and fill the gap between the conductive column and the dielectric layer.
  • a filling layer is arranged between the conductive column and the dielectric layer, and the filling layer is in contact with the conductive column and the dielectric layer respectively.
  • the filling layer fills the gap between the conductive column and the dielectric layer, and there is no gap between the conductive column and the dielectric layer, and there is no gap between the conductive column and the filling layer.
  • the conductive column is in direct contact with the first conductive pattern, and there is no film layer such as a barrier layer and a nucleation layer between the two, which can reduce the contact resistance of the conductive column and meet the chip performance.
  • the conductive column is formed by a selective growth process; the growth rate of the conductive column on the surface of the filling layer is less than the growth rate of the conductive column on the surface of the first conductive pattern; the growth rate of the conductive column on the surface of the filling layer is greater than the growth rate of the conductive column on the surface of the dielectric layer.
  • the conductive column grows slowly from the surface of the filling layer, and grows quickly from the bottom to the top from the surface of the first conductive pattern. This can avoid the problem that the conductive column is sealed early at the top and there are gaps inside the conductive column due to the conductive column growing too fast on the surface of the filling layer.
  • the material of the filling layer includes a metal or a metal compound.
  • the materials of the conductive column and the filling layer both include metal, so the connection effect between the conductive column and the filling layer is better, which can improve the adhesion between the conductive column body and the dielectric layer, and improve the problem of chip failure caused by the lack of the conductive column.
  • the material of the filling layer includes metal, which can minimize the resistance of the filling layer to an almost negligible level, thereby optimizing the problem of increased resistance of the conductive column due to the presence of the filling layer.
  • the metal included in the filling layer is different from the metal included in the conductive pillar.
  • the filling layer and the conductive pillar are different structures prepared by different processes.
  • the material of the filling layer includes at least one of TiN, TaN, TiOx, Ta 2 O 5 , WOy, Ti, and Ta; wherein 0 ⁇ x ⁇ 2, and 0 ⁇ y ⁇ 4.
  • the chip includes an electronic component and a first redistribution layer; the first conductive pattern is disposed between the conductive pillar and the electronic component, and the first redistribution layer includes a second conductive pattern.
  • the chip includes a first integrated circuit module, a second redistribution layer, a second integrated circuit module, and a third redistribution layer stacked in sequence;
  • the second redistribution layer includes a first conductive pattern, and the first conductive pattern is coupled to the first integrated circuit module;
  • the conductive column runs through the second integrated circuit module, and
  • the third redistribution layer includes a second conductive pattern;
  • the third redistribution layer is also coupled to the second integrated circuit module.
  • the chip includes a bare chip; the pad of the bare chip is a first conductive pattern; the conductive pillar runs from the inactive surface of the bare chip to the back of the pad; the chip also includes a fourth redistribution layer, and the fourth redistribution layer includes a second conductive pattern.
  • the chip includes a bare chip; the pad of the bare chip is a first conductive pattern; the conductive column runs from the inactive surface of the bare chip to the back of the pad; and the second conductive pattern is a solder joint located on the inactive surface of the bare chip.
  • a second aspect of an embodiment of the present application provides an electronic device, comprising the chip and circuit board of any one of the first aspects, wherein the chip is arranged on the circuit board.
  • the electronic device provided in the embodiment of the present application includes the chip of any one of the first aspects, and its beneficial effects are the same as the beneficial effects of the chip, which will not be repeated here.
  • a method for preparing a chip comprising: providing a dielectric layer and a first conductive pattern located on one side of the dielectric layer; the dielectric layer has a hole, the hole being located above the first conductive pattern; forming a filling film, the filling film covering the surface of the dielectric layer away from the first conductive pattern, the hole wall of the hole and the portion of the first conductive pattern located below the hole; patterning the filling film, removing the portion of the filling film covering the dielectric layer and the first conductive pattern to form a filling layer; using a selective growth process to form a conductive column in the hole; the conductive column penetrates the dielectric layer and contacts the first conductive pattern; wherein the filling layer is used to wrap at least part of the side surface of the conductive column and fill the gap between the conductive column and the dielectric layer; forming a second conductive pattern on the side of the dielectric layer away from the first conductive pattern, the second conductive
  • the chip preparation method provided in the embodiment of the present application is to attach a filling layer to the side wall of the hole in the dielectric layer through a film forming and patterning process before selectively growing the conductive column, and the filling layer is in contact with the dielectric layer and the conductive column respectively, which is equivalent to eliminating the gap between the conductive column and the dielectric layer through the filling layer.
  • it can effectively prevent the damage to the first conductive pattern by solutions such as grinding liquid, cleaning liquid or etching liquid through the above-mentioned gap.
  • the chip preparation method provided in the embodiment of the present application does not need to inject heavy atoms to reduce the gap between the conductive column and the dielectric layer, so the problem of metal atoms in the conductive column body being sputtered during the injection of heavy atoms, resulting in chip failure, will not occur.
  • a selective growth process is used to grow a conductive column from the surface of the first conductive pattern in the hole, including: using a selective growth process, growing a conductive column from the surface of the first conductive pattern and the surface of the filling layer in the hole at the same time; wherein the growth rate of the conductive column on the surface of the filling layer is less than the growth rate of the conductive column on the surface of the first conductive pattern; the growth rate of the conductive column on the surface of the filling layer is greater than the growth rate of the conductive column on the surface of the dielectric layer.
  • the conductive column grows slowly from the surface of the filling layer, and grows quickly from the bottom to the top from the surface of the first conductive pattern. This can avoid the problem that the conductive column is sealed early at the top and there are gaps inside the conductive column due to the conductive column growing too fast on the surface of the filling layer.
  • the material of the filling film includes a metal or a metal compound.
  • the resistance of the filling layer prepared by the filling film can be reduced as much as possible to an almost negligible level, thereby optimizing the problem of increased resistance of the conductive column caused by the presence of the filling layer.
  • forming a filling film includes: forming the filling film by an atomic layer deposition process. Since the portion of the filling film covering the hole wall will be retained in the hole as a filling layer in the subsequent preparation process, the thickness of the filling film will affect the resistance of the conductive column to be formed. If the thickness of the filling film is too thick, the resistance of the conductive column will be increased. Forming the filling film by an atomic layer deposition process can form a thinner filling film, which is conducive to reducing the resistance of the conductive column.
  • patterning the filling film includes: patterning the filling film using a dry etching process, which is a mature and low-cost process.
  • patterning the filling film includes: patterning the filling film using an inert atom bombardment process, which is a mature and low-cost process.
  • FIG1 is a schematic diagram of a framework of an electronic device provided in an embodiment of the present application.
  • 2A-2D are schematic diagrams of a chip preparation process provided in an embodiment of the present application.
  • FIG3A is a schematic diagram of the structure of a chip provided in an embodiment of the present application.
  • FIG3B is a schematic diagram of the structure of another chip provided in an embodiment of the present application.
  • FIGS. 4A-4D are schematic diagrams of another chip preparation process provided in an embodiment of the present application.
  • FIG5A is a schematic diagram of the structure of a chip provided in an embodiment of the present application.
  • FIG5B is a schematic diagram of a chip preparation process provided in an embodiment of the present application.
  • 6A-11B are schematic diagrams of a process for preparing another chip provided in an embodiment of the present application.
  • FIG12 is a schematic diagram of the structure of another chip provided in an embodiment of the present application.
  • FIGS. 13A-13E are schematic diagrams of a process for preparing another chip provided in an embodiment of the present application.
  • FIG14 is a schematic diagram of the structure of another chip provided in an embodiment of the present application.
  • 15A-15F are schematic diagrams of a process for preparing another chip provided in an embodiment of the present application.
  • FIG. 16 is a schematic diagram of the structure of another chip provided in an embodiment of the present application.
  • 1-electronic device 2-display module; 3-middle frame; 4-housing; 5-cover plate; 200-substrate; 10-electronic component; 20-first conductive pattern; 30-dielectric layer; 301-first dielectric layer; 302-second dielectric layer; 31-hole; 40-filling layer; 41-filling film; 50-conductive column; 51-conductive column body; 60-second conductive pattern; 61-first redistribution layer; 70-first integrated circuit module; 80-second redistribution layer; 90-second integrated circuit module; 100-third redistribution layer; 91-first bare chip; 92-second bare chip; 99-fourth redistribution layer.
  • the term “including” is interpreted as an open, inclusive meaning, that is, “including, but not limited to”.
  • the terms “one embodiment”, “some embodiments”, “exemplary embodiments”, “exemplarily” or “some examples” and the like are intended to indicate that specific features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure.
  • the schematic representation of the above terms does not necessarily refer to the same embodiment or example.
  • the specific features, structures, materials or characteristics described may be included in any one or more embodiments or examples in any appropriate manner.
  • Coupled When describing some embodiments, the term “coupled” and its derivative expressions may be used. For example, when describing some embodiments, the term “coupled” may be used to indicate that two or more components are in direct physical or electrical contact. However, the term “coupled” may also refer to two or more components that are not in direct contact with each other but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents of this document.
  • exemplary embodiments are described with reference to cross-sectional views and/or plan views and/or equivalent circuit diagrams as idealized exemplary drawings.
  • the thickness of the layers and regions is magnified for clarity. Therefore, it is conceivable that the shape changes relative to the drawings are caused by, for example, manufacturing technology and/or tolerances. Therefore, the exemplary embodiments should not be interpreted as being limited to the shapes of the regions shown herein, but include shape deviations caused by, for example, manufacturing. For example, an etched region shown as a rectangle will generally have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shapes of the regions of the device, and are not intended to limit the scope of the exemplary embodiments.
  • the embodiment of the present application provides an electronic device.
  • the electronic device is, for example, a consumer electronic product, a home electronic product, a vehicle-mounted electronic product, a financial terminal product, and a communication electronic product.
  • consumer electronic products are, for example, mobile phones, tablet computers (pad), laptop computers, e-readers, personal computers (PC), personal digital assistants (PDA), desktop displays, smart wearable products (for example, smart watches, smart bracelets), virtual reality (VR) terminal devices, augmented reality (AR) terminal devices, drones, etc.
  • Home electronic products are, for example, smart door locks, televisions, remote controls, refrigerators, rechargeable small household appliances (for example, soybean milk machines, sweeping robots), etc.
  • Vehicle-mounted electronic products are, for example, vehicle-mounted navigation systems, vehicle-mounted high-density digital video discs (DVD), etc.
  • Financial terminal products are, for example, automated teller machines (ATM), self-service terminals, etc.
  • Communication electronic products are, for example, communication equipment such as servers, storage devices, and base stations.
  • the electronic device 1 mainly includes a display module 2 , a middle frame 3 , a housing (or battery cover, rear housing) 4 and a cover plate 5 .
  • the display module 2 has a light emitting side through which a display image can be seen and a back side arranged opposite to the light emitting side.
  • the back side of the display module 2 is close to the middle frame 3 , and the cover plate 5 is arranged on the light emitting side of the display module 2 .
  • the above-mentioned display module 2 includes a display panel (DP).
  • the display module 2 is a liquid crystal display module.
  • the display screen is a liquid crystal display (LCD).
  • the display module 2 also includes a backlight unit (BLU) located on the back of the liquid crystal display (away from the side of the LCD for displaying images).
  • BLU backlight unit
  • the backlight module can provide light source to the LCD screen so that each sub-pixel in the LCD screen can emit light to display images.
  • the display module 2 is an organic light emitting diode display module.
  • the display screen is an organic light emitting diode (OLED) display screen. Since an electroluminescent layer is provided in each sub-pixel in the OLED display screen, the OLED display screen can realize self-luminescence after receiving the operating voltage. In this case, the display module 2 having the OLED display screen does not need to be provided with the backlight module.
  • the cover plate 5 is located on the side of the display module 2 away from the middle frame 3.
  • the cover plate 5 may be, for example, a cover glass (CG), and the cover glass may have a certain toughness.
  • the middle frame 3 is located between the display module 2 and the housing 4.
  • the surface of the middle frame 3 away from the display module 2 is used to install internal components such as batteries, printed circuit boards (PCB), cameras, antennas, etc. After the housing 4 and the middle frame 3 are covered, the above internal components are located between the housing 4 and the middle frame 3.
  • the electronic device 1 also includes a processor (center processing unit, CPU) chip, a radio frequency chip, a radio frequency power amplifier ((power amplifier, PA) chip, a system-on-a-chip (system on a chip, SOC), a power management chip (power management integrated circuits, PMIC), a storage chip (such as high bandwidth memory (high bandwidth memory, HBM)), an audio processor chip, a touch screen control chip, a NAND flash (flash memory), an image sensor chip, a charging protection chip and other chips arranged on the PCB.
  • the PCB is used to carry the above chips and complete signal interaction with the above chips.
  • the reliability and other performance of the chip (or logic integrated device, or integrated circuit device) itself have a direct impact on the service life and performance of electronic equipment.
  • An embodiment of the present application provides a chip, which can be applied to the above-mentioned electronic device.
  • the chip provided in the embodiment of the present application may be an unpackaged bare chip, which may include one integrated circuit module (which may be called a two-dimensional (2D) bare chip), or may include multiple integrated circuit modules (which may be called a three-dimensional (3D) bare chip).
  • the chip provided in the embodiment of the present application may also be a packaged chip, which may include one bare chip or multiple bare chips.
  • An embodiment of the present application provides a chip, which is a 2D bare chip.
  • the chip preparation process usually includes the front end of line (FEOL), the mid end of line (MEOL) and the back end of line (BEOL).
  • the front-end process is used to form an integrated circuit module including electronic components such as transistors, capacitors, and inductors.
  • the electronic components in the embodiment of the present application can be components that are prepared by the front-end process and formed on a substrate and are not independently packaged.
  • the integrated circuit module including electronic components such as transistors, capacitors, and inductors can also be prepared in the back-end process, and the embodiment of the present application is only an illustration.
  • FIG2A is a schematic illustration of two transistors in an integrated circuit module, and the transistor includes a source S, a drain D, and a gate G.
  • the middle process is used to form a transfer layer that leads the conductive patterns in multiple electronic components to the same plane.
  • the conductive pillars in the transfer layer are coupled to the source S, drain D, and gate G of the electronic components.
  • the formation of the transfer layer usually first forms a dielectric layer with holes, the holes in the dielectric layer are located above the conductive patterns, and then the conductive pillars are formed using the hole filling technology.
  • the transfer layer formed by the middle process includes two parts, the first part is: the bottom metal arranged on the surface of the integrated circuit and the first middle dielectric layer wrapped around the bottom metal, the bottom metal is coupled with the source S, drain D, and gate G of the electronic component.
  • the second part is: the conductive column arranged on the surface of the bottom metal and the second middle dielectric layer wrapped around the conductive column, the conductive column is coupled with the bottom metal.
  • the bottom metal is, for example, in the shape of a strip
  • the conductive column is, for example, in the shape of a column.
  • the structure formed in the middle process is taken as shown in FIG. 2C as an example.
  • the back-end process is used to form a redistribution layer located on the transfer layer.
  • the signal in the electronic component is transmitted to the redistribution layer through the transfer layer, and then led out to the signal terminal on the surface of the redistribution layer.
  • the signal terminal is exposed to the surface of the chip.
  • the signal terminal serves as a pad of the chip.
  • copper (Cu) pillars are formed as conductive pillars using an electroplating process.
  • CVD chemical vapor deposition
  • the electroplating process usually requires a barrier layer (or adhesion layer) and an electroplating seed layer, and the barrier layer covers the side and bottom of the conductive column.
  • the chemical vapor deposition process usually requires a nucleation layer, which covers the side and bottom of the conductive column.
  • the barrier layer, seed layer or nucleation layer will occupy the pore space of the hole in the second middle section dielectric layer, resulting in a reduced pore size, an increased depth-to-width ratio of the hole, and an increased process difficulty of the conductive column.
  • the metal column is electroplated from the bottom and side of the hole at the same time, and the electroplating rate at the corner is relatively fast, so it is easy to have a situation where the surface of the conductive column is already closed, but there are pores inside.
  • the metal column is also deposited from the bottom and side of the hole at the same time, and the deposition rate at the corner is relatively fast, so it is easy to have a situation where the surface of the conductive column is already closed, but there are pores inside (as shown in Figure 3A). The pores left inside the conductive column will cause the resistance of the conductive column to be high, which cannot meet the performance required for chip miniaturization.
  • a thinner titanium nitride (TiN) is used as a barrier layer and a hole-filling cobalt (Co) is used as a conductive column.
  • TiN titanium nitride
  • Co hole-filling cobalt
  • a selectively grown tungsten (W) chemical vapor deposition process is used to form the conductive pillar.
  • the selective growth process deposits metal from the bottom up on the surface of the bottom metal at the bottom of the hole, and will not grow on the hole wall of the hole in the second middle dielectric layer, and no barrier layer is required. In this way, there is no barrier layer occupying the pore space, and a conductive column is directly formed in the hole, which can be applied to chip structures with high aspect ratios. Moreover, since the metal tungsten grows from the bottom up, there will be no pores inside the formed conductive column, which can reduce the resistance of the conductive column. Furthermore, there is no barrier layer, nucleation layer, filling layer or other film layer between the conductive column and the bottom metal, which can reduce the contact resistance between the conductive column and the bottom metal.
  • a method for preparing a chip includes:
  • a hole is formed on the second middle dielectric layer, where the hole is located above the bottom metal.
  • a selective growth process is used to form a conductive column body.
  • Heavy atoms may refer to atoms having an atomic number greater than that of silicon, such as heavy metals such as Ge (germanium), Ar (argon), Si (silicon), and Xe (xenon).
  • heavy metals such as Ge (germanium), Ar (argon), Si (silicon), and Xe (xenon).
  • the volume of the second middle dielectric layer increases and expands, so that the surface of the second middle dielectric layer facing the conductive column body bulges toward the side of the conductive column body to reduce the gap between the second middle dielectric layer and the conductive column body.
  • the chip formed by the preparation process is injected with heavy atoms, and the heavy atoms enter the second middle dielectric layer, so that the volume of the second middle dielectric layer increases and expands.
  • the side wall of the second middle dielectric layer facing the conductive column body will bulge toward the conductive column to reduce the gap between the second middle dielectric layer and the conductive column. This solves the problem of chip failure caused by the gap between the second middle dielectric layer and the conductive column.
  • an embodiment of the present application further provides a chip and a method for preparing the same, which are used to solve the problem of poor adhesion between the second middle dielectric layer and the conductive pillar.
  • the structure and preparation method of the conductive pillars are schematically described below in conjunction with the structure of the chip.
  • a chip which includes a dielectric layer 30 and a conductive column 50 penetrating the dielectric layer 30, a first conductive pattern 20, a second conductive pattern 60, and a filling layer 40.
  • the first conductive pattern 20 and the second conductive pattern 60 are respectively located on both sides of the dielectric layer 30, and both ends of the conductive column 50 are respectively in contact with the first conductive pattern 20 and coupled with the second conductive pattern 60;
  • the filling layer 40 is used to wrap at least part of the side surface of the conductive column 50 and fill the gap between the conductive column 50 and the dielectric layer 30.
  • the chip preparation method includes:
  • step S10 includes:
  • An electronic component 10 is formed on a substrate 200 to form an integrated circuit module of a chip.
  • the material of the substrate 200 is an insulating material.
  • the material of the substrate 200 is a conductive material.
  • the electronic component 10 is a basic element in an electronic circuit and has at least one lead contact, which is used to couple with wiring interconnection to complete signal transmission.
  • the electronic component 10 can be a resistor, a capacitor, an inductor, a transistor, a diode, etc.
  • the electronic component 10 is a transistor, and the lead contacts included in the electronic component 10 are a source S, a drain D, and a gate G.
  • the chip may include one electronic component 10, or may include multiple electronic components 10.
  • the chip preparation method provided in the embodiment of the present application only takes one electronic component 10 in the chip as an example to schematically illustrate the structure of each part in the chip.
  • the multiple electronic components 10 may be electronic components of the same type or different types.
  • the embodiment of the present application does not limit the number, type, and arrangement of the electronic components 10 in the chip, and they can be reasonably set as needed.
  • the electronic component 10 includes a complementary metal oxide semiconductor device (CMOS), and the source S, drain D and gate G of the CMOS are all lead contacts of the electronic component 10.
  • FIG6A also schematically shows a gate insulating layer below the gate G and a sidewall on the side of the gate G.
  • the structure of the electronic component 10 shown in FIG6A is only a schematic diagram and is not limited in any way.
  • the electronic component 10 is a high electron mobility transistor (HEMT), a heterojunction bipolar transistor (HBT), a bipolar junction transistor (BJT), etc.
  • HEMT high electron mobility transistor
  • HBT heterojunction bipolar transistor
  • BJT bipolar junction transistor
  • a bottom metal (first conductive pattern 20) and an inter-level dielectric (ILD) layer wrapped around the bottom metal are formed on the surface of the electronic component 10.
  • the shape of the bottom metal top view is not limited, for example, it can be a strip.
  • the bottom metal can be used as the first conductive pattern 20 in the embodiment of the present application.
  • other conductive patterns on the bottom metal can also be used as the first conductive pattern 20 in the embodiment of the present application, which is only a schematic diagram.
  • the first conductive pattern 20 included in the chip can be one or more.
  • the embodiment of the present application does not limit the shape and size of the hole 31.
  • the hole 31 can expose a portion of the top surface of the first conductive pattern 20 away from the substrate 200, and the projection of the hole 31 on the substrate 200 can be located within the projection of the first conductive pattern 20 on the substrate 200, and the projection of the hole 31 on the substrate 200 can also overlap with the projection of the first conductive pattern 20 on the substrate 200.
  • the projection of the hole 31 on the substrate 200 can also cover the projection of the first conductive pattern 20 on the substrate 200, as long as it is ensured that the conductive column 50 subsequently formed in the hole 31 does not cause the adjacent first conductive pattern 20 to short-circuit.
  • the hole 31 is located directly above the first conductive pattern 20, the area of the hole 31 can be smaller than the area of the first conductive pattern 20, the area of the hole 31 can also be equal to the area of the first conductive pattern 20, and the area of the hole 31 can also be larger than the area of the first conductive pattern 20.
  • the embodiment of the present application takes the example that the area of the hole 31 is smaller than the area of the first conductive pattern 20 as an example.
  • the embodiment of the present application does not limit the number of holes 31, and the number of holes 31 can be set corresponding to the number of first conductive patterns 20. It should be emphasized that one first conductive pattern 20 can be set corresponding to one hole 31, that is, only one hole 31 can be set above one first conductive pattern 20. One first conductive pattern 20 can also be set corresponding to multiple holes 31, that is, multiple holes 31 can be set above one first conductive pattern 20. It is also possible that multiple first conductive patterns 20 are set corresponding to the same hole 31, that is, the same hole 31 is set above multiple first conductive patterns 20 (for example, the multiple first conductive patterns 20 transmit the same signal).
  • the dielectric layer 30 includes a plurality of holes 31 , and each hole 31 exposes a first conductive pattern 20 .
  • a middle dielectric film can be formed by chemical vapor deposition (CVD), physical vapor deposition or other deposition methods, and then holes 31 can be formed on the middle dielectric film by photolithography and etching to prepare the dielectric layer 30.
  • CVD chemical vapor deposition
  • PVD physical vapor deposition
  • holes 31 can be formed on the middle dielectric film by photolithography and etching to prepare the dielectric layer 30.
  • the material of dielectric layer 30 may include, for example, silicon oxide (eg, silicon dioxide SiO 2 ), silicon nitride (eg, silicon nitride SiN 4 ), silicon doped oxide, silicon fluorinated oxide, silicon carbon doped oxide, or various low dielectric constant (k) dielectric materials known in the related art and combinations thereof.
  • silicon oxide eg, silicon dioxide SiO 2
  • silicon nitride eg, silicon nitride SiN 4
  • silicon doped oxide silicon fluorinated oxide
  • silicon carbon doped oxide silicon carbon doped oxide
  • various low dielectric constant (k) dielectric materials known in the related art and combinations thereof.
  • the dielectric layer 30 is a single-layer film layer, so that the structure is simple and the process steps are few.
  • the dielectric layer 30 includes multiple dielectric film layers.
  • the materials of the multiple dielectric film layers can be the same, or the materials of the multiple dielectric film layers can be different.
  • the dielectric layer 30 includes a first dielectric layer 301 and a second dielectric layer 302 .
  • the first dielectric layer 301 is disposed close to the first conductive pattern 20 , and the dielectric constant of the first dielectric layer 301 is greater than the dielectric constant of the second dielectric layer 302 .
  • the first dielectric layer 301 with a large dielectric constant is arranged at a position where the conductive column to be formed is relatively close to the first conductive pattern 20 , so as to improve the insulation effect between the first conductive pattern 20 and the conductive column to be formed.
  • the dielectric layer 30 may also include a plurality of dielectric layers stacked together, which can be reasonably arranged according to needs.
  • the embodiment of the present application is only an illustration.
  • step S10 ends.
  • step S10 further includes:
  • the opening of the groove is larger than or equal to the opening of the hole 31.
  • the etching byproducts may be removed first, and then step S14 may be performed.
  • the etching byproducts may be removed by, for example, first dry cleaning to remove most of the etching byproducts, and then wet cleaning to deeply remove the etching byproducts.
  • a groove is formed by etching back on the surface of the first conductive pattern 20, and the opening of the groove is larger than the opening of the hole 31.
  • the cross-sectional area of the end of the conductive column formed subsequently close to the first conductive pattern 20 can be larger than the cross-sectional area at other positions, thereby generating a rivet effect. In this way, even if a solution such as an acidic grinding liquid or an etching liquid flows into the gap between the conductive column and the dielectric layer 30 during the subsequent preparation process, it will first contact the portion of the conductive column end located in the groove, thereby reducing the damage of the acidic grinding liquid or the etching liquid to the first conductive pattern 20.
  • the filling film 41 covers the surface of the dielectric layer 30 away from the first conductive pattern 20 , the hole wall of the hole 31 in the dielectric layer 30 , and the portion of the first conductive pattern 20 located below the hole 31 .
  • the thickness of the filling film 41 may be, for example, For example, the thickness of the filling film 41 is or
  • the thickness of the filling film 41 should be understood as the film thickness of the filling film 41 , or as the distance between the surface of the filling film 41 in contact with the dielectric layer 30 and the surface of the filling film 41 away from the dielectric layer 30 .
  • the filling film 41 may be formed by an atomic layer deposition (ALD) process.
  • ALD atomic layer deposition
  • the portion of the filling film 41 covering the hole wall of the hole 31 will remain in the hole 31 as the filling layer 40. Therefore, the thickness of the filling film 41 will affect the resistance of the conductive pillar 50 to be formed. If the thickness of the filling film 41 is too thick, the resistance of the conductive pillar 50 will be increased.
  • the filling film 41 is formed by the atomic layer deposition process, and a thinner filling film 41 can be formed, which is conducive to reducing the resistance of the conductive pillar 50.
  • the embodiment of the present application does not limit the material of the filling film 41 , as long as it can be in contact with the conductive pillar 50 and the dielectric layer 30 .
  • the material of the filling film 41 includes metal.
  • the material of the filling film 41 includes at least one of Ti (titanium) or Ta (tantalum).
  • the material of the filling film 41 includes a metal compound.
  • the material of the filling film 41 includes at least one of TiN (titanium nitride), TiO x (titanium oxide), TaN (tantalum nitride), Ta 2 O 5 (tantalum oxide) or WO y (tungsten oxide), wherein 0 ⁇ x ⁇ 2, and 0 ⁇ y ⁇ 4.
  • the resistance of the filling layer 40 prepared by the filling film 41 can be reduced as much as possible to an almost negligible level, thereby optimizing the problem of increased resistance of the conductive column 50 caused by the presence of the filling layer 40.
  • the filling film 41 includes a metal different from the metal included in the conductive pillar 50 .
  • the remaining portion of the filling film 41 is the portion of the hole wall of the hole 31 covered by the filling film 41, so the filling layer 40 covers the hole wall of the hole 31 in the dielectric layer 30 and contacts the hole wall of the hole 31.
  • the filling layer 40 can cover part of the hole wall or the entire hole wall of the hole 31, and FIG8 is taken as an example to illustrate the case where the filling layer 40 covers the entire hole wall of the hole 31.
  • the filling film 41 is patterned by using a dry etching process.
  • the filling film 41 is patterned by using an inert atom bombardment process.
  • a conductive column body 51 is formed in the hole 31 by a selective deposition process.
  • the conductive column body 51 formed by the selective growth process is in contact with the filling layer 40 .
  • the selective growth process refers to epitaxial growth in a limited area on the substrate.
  • the epitaxial growth starts from the surface of the first conductive pattern 20, and does not start from the surface of the dielectric layer 30. Since the present application epitaxially grows the conductive column body 51 directly on the surface of the metal structure of the first conductive pattern 20 through the selective epitaxial growth process, the conductive column body 51 is formed by the selective growth process without the need for film layers such as a barrier layer and a nucleation layer.
  • the conductive column 50 finally formed by the selective growth process in the present application has its bottom surface directly in contact with the first conductive pattern 20 , and its side surface directly in contact with the filling layer 40 .
  • the conductive column 50 is a solid structure, and there is no pore inside the conductive column 50 .
  • a selective growth process is used to simultaneously grow the conductive pillar body 51 from the surface of the first conductive pattern 20 and the surface of the filling layer 40 in the hole 31 .
  • a suitable material for the filling layer 40 is selected to achieve a growth rate of the conductive column body 51 on the surface of the filling layer 40 that is lower than the growth rate of the conductive column body 51 on the surface of the first conductive pattern 20 .
  • the growth rate corresponds to the nucleation rate of the material on the surface of the first conductive pattern 20 and the filling layer 40 during the epitaxial growth process. The greater the nucleation rate, the greater the growth rate.
  • the surface of the filling layer 40 may be understood as a surface of the filling layer 40 that is parallel to the hole wall of the hole 31 .
  • the growth rate of the conductive column body 51 on the surface of the filling layer 40 is lower than the growth rate of the conductive column body 51 on the surface of the first conductive pattern 20. Therefore, during the growth process of the conductive column body 51, the conductive column body 51 grows slowly from the surface of the filling layer 40, and grows quickly from the bottom to the top from the surface of the first conductive pattern 20. In this way, the problem of the conductive column body 51 sealing the top of the conductive column body 51 too early and the existence of gaps inside the conductive column body 51 due to the conductive column body 51 growing too fast on the surface of the filling layer 40 can be avoided.
  • the growth rate of the conductive pillar body 51 on the surface of the filling layer 40 can be greater than the growth rate of the conductive pillar body 51 on the surface of the dielectric layer 30 .
  • the height of the conductive column body 51 can be adjusted according to the depth of the hole 31 in the dielectric layer 30 and the grinding thickness of the subsequent chemical mechanical polishing process. As shown in FIG9, when multiple conductive column bodies 51 are formed simultaneously, the heights of the multiple conductive column bodies 51 can be the same or different.
  • the surface of the conductive pillar body 51 is lower than the surface of the dielectric layer 30 .
  • the depth of the conductive pillar body 51 is less than the depth of the hole 31 .
  • the height of the conductive column body 51 that is polished away can be reduced, thereby reducing material waste and lowering costs.
  • the material of the conductive column body 51 may include copper (Cu), aluminum (Al), titanium (Ti), zirconium (Zr), hafnium (Hf), vanadium (V), ruthenium (Ru), cobalt (Co), nickel (Ni), palladium (Pd), platinum (Pt), tungsten (W), silver (Ag), gold (Au), cobalt (CN) and the like.
  • the hole 31 in the dielectric layer 30 is first surface treated to remove chemical residues and dangling bonds on the hole wall of the hole 31 and the surface of the first conductive pattern 20 to improve selectivity.
  • the chemical residues may be, for example, chemical substances remaining in the process of forming the holes 31 on the dielectric layer 30
  • the dangling bonds may be, for example, chemical bonds with no electrons to pair with.
  • the surface of the holes 31 in the dielectric layer 30 may be treated by, for example, heating treatment, plasma treatment, introduction of reducing gas (such as hydrogen) treatment, introduction of oxidizing gas (such as oxygen and nitrous oxide) treatment, introduction of inert gas treatment, etc.
  • reducing gas such as hydrogen
  • oxidizing gas such as oxygen and nitrous oxide
  • the above-mentioned step of surface treatment of the holes 31 in the dielectric layer 30 can be performed after patterning the filling film 41.
  • the above-mentioned step of surface treatment of the holes 31 in the dielectric layer 30 can also be performed before selectively growing the conductive column body 51.
  • the above-mentioned surface treatment of the holes 31 in the dielectric layer 30 can also be performed once after patterning the filling film 41 and before selectively growing the conductive column body 51.
  • the embodiment of the present application does not limit this, and it can be reasonably selected according to needs.
  • the conductive column body 51 is processed to form a conductive column 50 .
  • a chemical mechanical polishing process may be used to polish the conductive pillar body 51 and the dielectric layer 30 to form the conductive pillar 50 .
  • step S50 includes:
  • the chemical mechanical polishing rate can be made uniform, the polishing effect is good, the surface of the conductive pillar 50 is flat, and the surface flatness of the plurality of conductive pillars 50 is high.
  • the conductive pillar 50 penetrates the dielectric layer 30 and contacts the first conductive pattern 20 .
  • the filling layer 40 is used to wrap at least a portion of the side surface of the conductive pillar 50 and fill the gap between the conductive pillar 50 and the dielectric layer 30 .
  • the step of processing the conductive pillar body 51 may not be included.
  • the conductive pillar 50 is directly formed in the hole 31 by adopting the selective growth process, and the conductive pillar 50 is in contact with the filling layer 40 .
  • the embodiment of the present application does not limit the shape, function, and material of the second conductive pattern 60 , and can be reasonably set according to the application scenario.
  • the second conductive pattern 60 is a conductive pattern included in the first redistribution layer 61.
  • the second conductive pattern 60 is a conductive pattern in the redistribution layer prepared in the back-end process.
  • the second conductive pattern 60 is a conductive pattern in a wiring layer in the first redistribution layer 61 that is closest to the dielectric layer 30.
  • the second conductive pattern 60 may be columnar, linear, or other shapes, which are not limited in the present embodiment.
  • a second conductive pattern 60 can be coupled to one or more conductive pillars 50.
  • the first conductive pattern 20 and the second conductive pattern 60 are coupled to both ends of the conductive pillar 50, respectively.
  • the conductive pillar 50 is in direct contact with the first conductive pattern 20, and the conductive pillar 50 and the second conductive pattern 60 can be in direct contact or indirect contact.
  • the chip preparation method provided in the embodiment of the present application before the selective growth of the conductive pillar 50, through the film forming and patterning process, attaches the filling layer 40 to the side wall of the hole 31 in the dielectric layer 30, and the filling layer 40 contacts the dielectric layer 30 and the conductive pillar 50 respectively, which is equivalent to eliminating the gap between the conductive pillar 50 and the dielectric layer 30 through the filling layer 40.
  • it can effectively prevent the polishing liquid, cleaning liquid or etching liquid and other solutions from damaging the first conductive pattern 20 through the above-mentioned gap.
  • the chip preparation method does not need to inject heavy atoms to reduce the gap between the conductive pillar 50 and the dielectric layer 30, so there will be no problem of metal atoms in the conductive pillar body being sputtered during the injection of heavy atoms, resulting in chip failure.
  • the chip includes a dielectric layer 30 , a filling layer 40 , a conductive column 50 , a first conductive pattern 20 , and a second conductive pattern 60 .
  • the dielectric layer 30 has a hole 31, and the hole 31 penetrates the dielectric layer 30 along the thickness direction of the dielectric layer 30.
  • the conductive pillar 50 is disposed in the hole 31 of the dielectric layer 30, and the conductive pillar 50 penetrates the dielectric layer 30 along the thickness direction of the dielectric layer 30.
  • the depth (or height) of the conductive pillar 50 may be the same as the thickness of the dielectric layer 30.
  • the filling layer 40 wraps at least a portion of the side surface of the conductive pillar 50 , and the filling layer 40 contacts the side wall of the conductive pillar 50 and the hole wall of the dielectric layer 30 , respectively.
  • FIG11B illustrates a chip including multiple conductive pillars 50 as an example.
  • the embodiment of the present application does not limit the shape of the conductive pillar 50 , and the shape of the conductive pillar 50 may be a cylindrical shape, a rectangular column shape, or a cuboid column shape, etc.
  • the conductive pillars 50 are formed by a selective growth process.
  • the growth rate of the conductive pillar 50 on the surface of the filling layer 40 is lower than the growth rate of the conductive pillar on the surface of the first conductive pattern 20.
  • the growth rate of the conductive pillar 50 on the surface of the filling layer 40 is higher than the growth rate of the conductive pillar on the surface of the dielectric layer 30.
  • the metal of the filling layer 40 is exemplary.
  • the material of the filling layer 40 includes at least one of Ti and Ta.
  • the material of the filling layer 40 includes a metal compound.
  • the material of the filling layer 40 includes at least one of TiN, TaN, TiOx, Ta 2 O 5 , and WOy, wherein 0 ⁇ x ⁇ 2, and 0 ⁇ y ⁇ 4.
  • the filling layer 40 includes a metal different from the metal included in the conductive pillar 50 .
  • the conductive pillar 50 includes W
  • the filling layer 40 includes Ti, Ta, TiN, TaN, TiOx, or Ta 2 O 5 .
  • dielectric layer 30 reference may be made to the relevant description of the dielectric layer 30 in the above chip preparation method, which will not be repeated here.
  • the first conductive pattern 20 and the second conductive pattern 60 are respectively located on the two sides of the dielectric layer 30.
  • the two sides of the dielectric layer 30 can be understood as the upper side and the lower side perpendicular to the thickness direction of the dielectric layer 30.
  • the first conductive pattern 20 and the second conductive pattern 60 are located on the opposite sides of the dielectric layer 30.
  • the two sides of the dielectric layer 30 can be understood as the upper side and the lower side perpendicular to the thickness direction of the dielectric layer 30.
  • the first conductive pattern 20 directly contacts one end of the conductive pillar 50 to achieve electrical connection between the first conductive pattern 20 and the conductive pillar 50.
  • the second conductive pattern 60 directly or indirectly contacts the other end of the conductive pillar 50 to achieve electrical connection between the second conductive pattern 60 and the conductive pillar 50.
  • the embodiment of the present application does not limit the shapes of the first conductive pattern 20 and the second conductive pattern 60, and the first conductive pattern 20 and the second conductive pattern 60 only need to be able to conduct electricity.
  • the first conductive pattern 20 and the second conductive pattern 60 in the chip reference can be made to the relevant description of the first conductive pattern 20 and the second conductive pattern 60 when describing the chip preparation method above.
  • the aspect ratio of the conductive pillar 50 is greater than 2:1.
  • the aspect ratio of the conductive pillar 50 is 3:1, 4:1, 5:1, 6:1, 7:1, 8:1, 9:1, 10:1, 11:1, 12:1 or greater.
  • the depth of the conductive pillar 50 refers to the dimension of the conductive pillar 50 in a direction perpendicular to the dielectric layer 30.
  • the width of the conductive pillar 50 refers to the dimension of the conductive pillar 50 in a direction parallel to the dielectric layer 30.
  • the first conductive pattern 20 is disposed between the conductive pillar 50 and the electronic component 20.
  • the conductive pillar 50 can also be directly coupled to the electronic component 20 without the bottom metal, and the conductive part of the electronic component 20 is the first conductive pattern 20.
  • a filling layer 40 is provided between the conductive pillar 50 and the dielectric layer 30, and the filling layer 40 is in contact with the conductive pillar 50 and the dielectric layer 30 respectively.
  • the filling layer 40 fills the gap between the conductive pillar 50 and the dielectric layer 30, and there is no gap between the conductive pillar 50 and the dielectric layer 30, and there is no gap between the conductive pillar 50 and the dielectric layer 30, and there is no gap between the conductive pillar 50 and the filling layer 40.
  • the problem that the first conductive pattern 20 at the bottom of the conductive pillar 50 is damaged due to the infiltration of acidic grinding liquid, cleaning liquid or etching liquid and other solutions in the gap between the conductive pillar 50 and the dielectric layer 30, which eventually leads to chip failure, can be almost avoided.
  • the filling layer 40 by providing the filling layer 40, the adhesion between the conductive pillar 50 and the dielectric layer 30 can be improved, and the problem of chip failure caused by the absence of the conductive pillar 50 can be improved.
  • the conductive pillar 50 is in direct contact with the first conductive pattern 20 , and there is no barrier layer, nucleation layer or other film layer therebetween, which can reduce the contact resistance of the conductive pillar 50 and meet chip performance requirements.
  • the embodiments of the present application further provide a chip, which is a chip obtained by packaging the above-mentioned 2D bare chip.
  • An embodiment of the present application provides a chip, which is a 3D bare chip.
  • the chip includes a first integrated circuit module 70 , a second redistribution layer 80 , a third integrated circuit module 90 , and a third redistribution layer 100 which are stacked in sequence.
  • the surface of the third redistribution layer 100 away from the second integrated circuit module 90 is the active surface of the chip, and the surface of the first integrated circuit module 70 away from the second redistribution layer 80 is the inactive surface of the chip.
  • the first integrated circuit module 70 and the second integrated circuit module 90 can be understood as structures including a plurality of circuit electronic components formed by a front-end process.
  • the embodiment of the present application does not limit the functions that the first integrated circuit module 70 is used to implement, so the structure of the electronic components included in the first integrated circuit module 70 is also not limited.
  • the first integrated circuit module 70 includes multiple electronic components, and the multiple electronic components are coupled in series and in parallel through a structure prepared by a subsequent process to achieve certain functions.
  • the embodiment of the present application does not limit the functions that the second integrated circuit module 90 is used to implement, so the structure of the electronic components included in the second integrated circuit module 90 is also not limited.
  • the second integrated circuit module 90 includes multiple electronic components, and the multiple electronic components are coupled in series and in parallel through a structure prepared by a subsequent process to achieve certain functions.
  • Figure 12 only takes a CMOS included in the first integrated circuit module 70 as an example for illustration, and takes a CMOS included in the second integrated circuit module 90 as an example for illustration.
  • the first integrated circuit module 70 is a circuit structure of a logic area
  • the second integrated circuit module 90 is a circuit structure of a storage area
  • the first integrated circuit module 70 is a circuit structure of a logic area
  • the second integrated circuit module 90 is a circuit structure of a detector.
  • the chip may include a transfer layer formed by the middle process.
  • the chip may not include a transfer layer formed by the middle process.
  • the second redistribution layer 80 includes a first conductive pattern 20, and the first conductive pattern 20 is coupled to the first integrated circuit module 70.
  • a wiring layer in the second redistribution layer 80 that is closest to the second integrated circuit module 90 includes the first conductive pattern 20, and the first conductive pattern 20 is in contact with electrodes (e.g., source S, drain D, gate D) of electronic components in the first integrated circuit module 70.
  • the third redistribution layer 100 includes a second conductive pattern 60.
  • a wiring layer in the third redistribution layer 100 that is closest to the second integrated circuit module 90 includes the second conductive pattern 60.
  • the conductive pillar 50 passes through the second integrated circuit module 90.
  • the conductive pillar 50 is coupled to the second conductive pattern 60 through the conductive pillar in the transfer layer (when the chip does not include the transfer layer, the conductive pillar 50 can directly contact the second conductive pattern 60).
  • the third redistribution layer 100 is also coupled to the second integrated circuit module 90.
  • the chip illustrated in this example includes at least two integrated circuit modules, and FIG12 only illustrates the first integrated circuit module 70 and the second integrated circuit module 90 as examples.
  • the chip shown in FIG12 includes two transmission paths: the signal on the active surface of the chip is transmitted to the first integrated circuit module 70 via the third redistribution layer 100, the conductive pillar 50, and the second redistribution layer 80 in sequence. The signal on the active surface of the chip is also transmitted to the second integrated circuit module 90 via the third redistribution layer 100.
  • FIG12 at least part of the side surface of the conductive pillar 50 is also wrapped with a filling layer 40 (FIG12 takes the case where all the side surfaces of the conductive pillar 50 are wrapped with the filling layer 40 as an example for illustration), and the filling layer 40 is in contact with the dielectric layer 30 and the conductive pillar 50 respectively.
  • the structure of the filling layer 40 and the conductive pillar 50 can be the same as that in Example 1, and the relevant description in Example 1 can be referred to, and will not be repeated here.
  • the above-mentioned conductive pillars 50 and filling layer 40 are arranged in the dielectric layer 30.
  • the material of the dielectric layer 30 in Example 1 is an insulating material.
  • the conductive pillars 50 and the second conductive pillars 32 penetrate the second integrated circuit module 90. Therefore, the dielectric layer 30 wrapped around the conductive pillars 50 and the second conductive pillars 32 is the substrate of the second integrated circuit module 90. In other words, the material of the dielectric layer 30 is a semiconductor.
  • S10 as shown in FIG. 13A , provide a dielectric layer 30 and a first conductive pattern 20 located on one side of the dielectric layer 30 .
  • the present application embodiment does not limit the method for preparing the structure shown in FIG. 13A.
  • a structure including a first integrated circuit module 70, a transfer layer, and a second wiring layer 60 can be formed by a front-end process, a middle-end process, and a back-end process, and then a second integrated circuit module 90 is formed on the aforementioned structure by a front-end process.
  • the second integrated circuit module 90 includes a dielectric layer 30, and the second wiring layer 60 includes a first conductive pattern 20.
  • the dielectric layer 30 includes a hole 31 .
  • the hole 31 is located above the first conductive pattern 20 and contacts the first conductive pattern 20 .
  • the conductive column body 51 is processed to form a conductive column 50 .
  • steps S20, S30, S40 and S50 can refer to the relevant description in Example 1, and will not be repeated here.
  • a third redistribution layer 100 is formed on the dielectric layer 30 , and the third redistribution layer 100 includes the second conductive pattern 60 .
  • a wiring layer in the third redistribution layer 100 that is closest to the second integrated circuit module 90 includes the second conductive pattern 60 .
  • the conductive column 50 in the chip provided in the embodiment of the present application is formed by a selective growth process, without the need for a barrier layer or other film layer.
  • the conductive column 50 in the chip provided in the embodiment of the present application is formed by a selective growth process, without the need for a barrier layer or other film layer.
  • an adhesion layer 40 is provided between the conductive pillar 50 and the dielectric layer 30, and the adhesion layer 40 is in contact with both the conductive pillar 50 and the dielectric layer 30. Therefore, there is no gap between the conductive pillar 50 and the dielectric layer 30. Thus, it is almost possible to avoid the problem that the first conductive pattern 20 at the bottom of the conductive pillar 50 is damaged due to the infiltration of acidic polishing liquid, cleaning liquid or etching liquid into the gap between the conductive pillar 50 and the dielectric layer 30, which eventually leads to chip failure.
  • the embodiments of the present application further provide a chip, which is a chip obtained by packaging the above-mentioned 3D bare chip in this example.
  • An embodiment of the present application provides a chip, which is a packaged chip.
  • the chip includes a first bare chip 91 , a second bare chip 92 , and a fourth wiring layer 99 .
  • the pad of the first bare chip 91 is a first conductive pattern 20, and the conductive column 50 runs through the inactive surface of the first bare chip 91 to the back of the pad.
  • the fourth redistribution layer 99 includes a second conductive pattern 60, and the second conductive pattern 60 is coupled to the conductive column 50.
  • the second bare chip 92 is located on the side of the fourth redistribution layer 99 away from the first bare chip 91, and the second bare chip 92 is coupled to the fourth redistribution layer 99. For example, as shown in FIG. 14, the second bare chip 92 is bonded and coupled to the fourth redistribution layer 99 through a solder ball.
  • the signal of the first bare chip 91 is transmitted through the pad to the substrate (not shown in FIG. 14 ) bonded to the first bare chip 91.
  • the signal of the second bare chip 92 is transmitted to the fourth redistribution layer 99, and is transmitted to the pad of the first bare chip 91 through the conductive column 50, and then transmitted to the substrate bonded to the first bare chip 91.
  • the embodiment of the present application does not limit the structures of the first bare chip 91 and the second bare chip 92 , and they can be reasonably configured as needed.
  • FIG14 at least part of the side surface of the conductive pillar 50 is also wrapped with a filling layer 40 (FIG14 takes the case where all the side surfaces of the conductive pillar 50 are wrapped with the filling layer 40 as an example for illustration), and the filling layer 40 is in contact with the dielectric layer 30 and the conductive pillar 50 respectively.
  • the structure of the filling layer 40 and the conductive pillar 50 can be the same as that in Example 1, and the relevant description in Example 1 can be referred to, and will not be repeated here.
  • the above-mentioned conductive pillars 50 and filling layer 40 are arranged in the dielectric layer 30.
  • the conductive pillars 50 in this example penetrate from the non-active surface of the first bare chip 91 to the back of the pad. Therefore, as shown in FIG15A, the dielectric layer 30 in this example includes the substrate in the integrated circuit module formed by the front-end process, the insulating layer in the transfer layer formed by the middle-end process, and the multi-layer insulating layer in the redistribution layer formed by the back-end process.
  • the hole 31 in the dielectric layer 30 is located above the pad in the first bare chip 91.
  • S10 as shown in FIG. 15A , provide a dielectric layer 30 and a first conductive pattern 20 located on one side of the dielectric layer 30 .
  • the structure shown in FIG. 12B can first be formed into a bare chip through a front-end process, a middle-end process, and a back-end process, and then a hole 31 is formed by a drilling process to obtain the first bare chip 91 in the present application.
  • the dielectric layer 30 includes a hole 31 .
  • the hole 31 is located above the first conductive pattern 20 and contacts the first conductive pattern 20 .
  • a selective deposition process is used to form a conductive column body 51 in the hole 31.
  • the conductive column body 51 is processed to form a conductive column 50 .
  • steps S20, S30, S40 and S50 can refer to the relevant description in Example 1, and will not be repeated here.
  • a second conductive pattern 60 is formed on a side of the dielectric layer 30 away from the first conductive pattern 20 , and the second conductive pattern 60 is coupled to the conductive pillar 50 .
  • a fourth redistribution layer 99 is formed on a side of the dielectric layer 30 away from the first conductive pattern 20 , and the fourth redistribution layer 99 includes the second conductive pattern 60 .
  • the chip can be bonded to the substrate via solder balls on the active surface of the first bare chip 91, for example.
  • the chip includes a first bare chip 91 , a second bare chip 92 , and solder joints.
  • the pad of the first bare chip 91 is the first conductive pattern 20 , and the conductive pillar 50 penetrates from the inactive surface of the first bare chip 91 to the back of the pad.
  • the solder joint is the second conductive pattern 60 , and the second conductive pattern 60 is coupled to the conductive pillar 50 .
  • the signal of the first bare chip 91 is transmitted to the conductive pillar 50 via the pad, then to the solder joint (the second conductive pattern 60 ), and then to the substrate (not shown in FIG. 16 ) bonded to the first bare chip 91 .
  • FIG16 Please continue to refer to FIG16, at least part of the side surface of the conductive pillar 50 is also wrapped with a filling layer 40 (FIG16 takes the case where all the side surfaces of the conductive pillar 50 are wrapped with the filling layer 40 as an example for illustration), and the filling layer 40 is in contact with the dielectric layer 30 and the conductive pillar 50 respectively.
  • the structure of the filling layer 40 and the conductive pillar 50 can be the same as that in Example 1, and the relevant description in Example 1 can be referred to, and will not be repeated here.
  • the above-mentioned conductive pillars 50 and filling layer 40 are arranged in the dielectric layer 30.
  • the conductive pillars 50 in this example penetrate from the non-active surface of the first bare chip 91 to the back of the pad. Therefore, as shown in FIG16, the dielectric layer 30 in this example includes the substrate in the integrated circuit module formed by the front-end process, the insulating layer in the transfer layer formed by the middle-end process, and the multi-layer insulating layer in the redistribution layer formed by the back-end process.
  • the hole 31 in the dielectric layer 30 is located above the pad in the first bare chip 91.
  • S10-S50 are the same as the chip preparation method when the chip includes the fourth redistribution layer 99 in this example, and will not be repeated here.
  • the second conductive pattern 60 is a solder joint located on the non-active surface of the first bare chip 91.
  • the second conductive pattern 60 is a structure such as a solder ball or a micro-bump.
  • step S70 can also be before step S10, or after other steps.
  • the embodiment of the present application is not limited to step S60 being after S50.
  • the chip can be bonded to the substrate via solder joints on the inactive surface of the first bare chip 91, for example.
  • the chip provided in the embodiment of the present application is based on the structure and preparation method of the conductive pillar 50, and can be applied to chips with high depth-to-width ratio requirements.

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Abstract

本申请实施例提供一种芯片及其制备方法、电子设备，涉及半导体技术领域，用于解决如何提高芯片中导电图案之间的互联耦接效果的问题。本申请提供的芯片可以是裸芯片，也可以是封装后的芯片。芯片包括：介质层和贯穿介质层的导电柱、第一导电图案、第二导电图案及填充层；第一导电图案和第二导电图案，分别位于介质层的两边，导电柱的两端分别与第一导电图案接触、与第二导电图案耦接；填充层用于包裹导电柱的至少部分侧面，以及填充导电柱和介质层之间的缝隙。适用于对导电柱深宽比要求比较高的芯片中。

Description

芯片及其制备方法、电子设备 技术领域
本申请涉及半导体技术领域，尤其涉及一种芯片及其制备方法、电子设备。
背景技术
随着电子技术的发展，用户对电子设备的性能要求越来越高，使得电子设备中芯片尺寸越来越大、数量越来越多。但随着电子设备不断向集成化、超薄化趋势发展，电子设备中的芯片也不得不向小型化发展。基于此，为了同时满足电子设备对芯片的性能需求和尺寸需求，不得不缩小芯片中导电图案的尺寸。
但是，导电图案尺寸的减小，会增加导电图案之间互连耦接的难度。而且，导电图案通过导电柱互连耦接时，导电柱的电阻、制备工艺等特性，会对互联耦接效果以及芯片的良率产生直接的影响。
发明内容
本申请实施例提供一种芯片及其制备方法、电子设备，用于解决如何提高芯片中导电图案之间的互联耦接效果的问题。
为达到上述目的，本申请采用如下技术方案：
本申请实施例的第一方面，提供一种芯片，芯片可以是裸芯片，也可以是封装后的芯片。芯片包括介质层和贯穿介质层的导电柱、第一导电图案、第二导电图案及填充层。第一导电图案和第二导电图案，分别位于介质层的两边；导电柱的两端分别与第一导电图案接触、与第二导电图案耦接；填充层用于包裹导电柱的至少部分侧面，以及填充导电柱和介质层之间的缝隙。
本申请实施例提供的芯片，导电柱与介质层之间设置有填充层，填充层与导电柱和介质层分别接触。这样一来，一方面，填充层填充导电柱与介质层之间的间隙，导电柱与介质层之间没有缝隙，导电柱与填充层之间也没有缝隙。从而几乎可以避免导电柱与介质层之间的缝隙处因渗入酸性研磨液、清洗液或者刻蚀液等溶液，导致导电柱底部的第一导电图案损伤，最终导致芯片失效的问题。另一方面，导电柱与第一导电图案直接接触，二者之间没有阻挡层、成核层等膜层，可降低导电柱的接触电阻，满足芯片性能。
在一种可能的实现方式中，导电柱采用选择性生长工艺形成；导电柱在填充层表面的生长速率，小于，导电柱在第一导电图案表面的生长速率；导电柱在填充层表面的生长速率，大于，导电柱在介质层表面的生长速率。这样一来，在生长导电柱的过程中，导电柱从填充层表面生长的慢，从第一导电图案表面自下而上生长的速度快。可以避免因导电柱在填充层的表面生长速度过快，导致导电柱顶部封口早，导电柱内部存在缝隙的问题。
在一种可能的实现方式中，填充层的材料包括金属或者金属化合物。通过将填充层的材料选择为金属或者金属化合物，一方面，导电柱和填充层的材料都包括金属， 因此导电柱和填充层的连接效果较好，可提高导电柱本体与介质层的粘附性，改善因导电柱缺失导致芯片失效的问题。另一方面，填充层的材料包括金属，可尽量降低填充层的电阻，达到几乎可以忽略的程度，从而优化因填充层的存在导致导电柱电阻升高的问题。
在一种可能的实现方式中，填充层包括的金属与导电柱包括的金属不同。填充层和导电柱属于采用不同工艺制备得到的不同结构。
在一种可能的实现方式中，填充层的材料包括TiN、TaN、TiOx、Ta 2O 5、WOy、Ti、Ta中的至少一种；其中，0<x<2，0<y<4。
在一种可能的实现方式中，芯片包括电子元件和第一重布线层；第一导电图案设置在导电柱与电子元件之间，第一重布线层包括第二导电图案。这是一种可能的应用场景。
在一种可能的实现方式中，芯片包括依次层叠设置的第一集成电路模块、第二重布线层、第二集成电路模块以及第三重布线层；第二重布线层包括第一导电图案，第一导电图案与第一集成电路模块耦接；导电柱贯穿第二集成电路模块，第三重布线层包括第二导电图案；第三重布线层还与第二集成电路模块耦接。这是一种可能的应用场景。
在一种可能的实现方式中，芯片包括裸芯片；裸芯片的焊盘为第一导电图案；导电柱从裸芯片的非有源面贯穿至焊盘背面；芯片还包括第四重布线层，第四重布线层包括第二导电图案。这是一种可能的应用场景。
在一种可能的实现方式中，芯片包括裸芯片；裸芯片的焊盘为第一导电图案；导电柱从裸芯片的非有源面贯穿至焊盘背面；第二导电图案为位于裸芯片非有源面上的焊点。这是一种可能的应用场景。
本申请实施例的第二方面，提供一种电子设备，包括第一方面任一项的芯片和电路板，芯片设置在电路板上。
本申请实施例提供的电子设备包括第一方面任一项的芯片，其有益效果与芯片的有益效果相同，此处不再赘述。
本申请实施例的第三方面，提供一种芯片的制备方法，包括：提供介质层和位于介质层一边的第一导电图案；介质层具有孔，孔位于第一导电图案上方；形成填充膜，填充膜覆盖介质层远离第一导电图案的表面、孔的孔壁以及第一导电图案位于孔下方的部分；对填充膜进行图案化，去除填充膜中覆盖介质层和第一导电图案的部分，形成填充层；采用选择性生长工艺，在孔内形成导电柱；导电柱贯穿介质层，与第一导电图案接触；其中，填充层用于包裹导电柱的至少部分侧面，以及填充导电柱和介质层之间的缝隙；在介质层远离第一导电图案一边形成第二导电图案，第二导电图案与导电柱耦接。
本申请实施例提供的芯片的制备方法，通过在选择性生长导电柱之前，通过成膜及图案化工艺，在介质层中孔的侧壁附着填充层，填充层与介质层和导电柱分别接触，相当于通过填充层消除了导电柱与介质层之间的缝隙。一方面，可以有效阻挡研磨液、清洗液或者刻蚀液等溶液通过上述缝隙对第一导电图案的损伤。另一方面，由于导电柱与填充层的连接效果好，因此可以改善在化学机械研磨过程中，将导电柱带走，导 致导电柱缺失，从而导致芯片失效的问题。而本申请实施例提供的芯片的制备方法，无需注入重原子来缩小导电柱与介质层之间的缝隙，因此不会出现在注入重原子的过程中，引起导电柱本体中的金属原子溅射，导致芯片失效的问题。
在一种可能的实现方式中，采用选择性生长工艺，在孔内从第一导电图案的表面开始生长形成导电柱，包括：采用选择性生长工艺，在孔内从第一导电图案的表面和填充层的表面同步开始生长形成导电柱；其中，导电柱在填充层表面的生长速率，小于，导电柱在第一导电图案表面的生长速率；导电柱在填充层表面的生长速率，大于，导电柱在介质层表面的生长速率。这样一来，在生长导电柱的过程中，导电柱从填充层表面生长的慢，从第一导电图案表面自下而上生长的速度快。可以避免因导电柱在填充层的表面生长速度过快，导致导电柱顶部封口早，导电柱内部存在缝隙的问题。
在一种可能的实现方式中，填充膜的材料包括金属或者金属化合物。通过将填充膜的材料选择为金属或者金属化合物，可尽量降低通过填充膜制备得到的填充层的电阻，达到几乎可以忽略的程度，从而优化填充层的存在导致导电柱电阻升高的问题。
在一种可能的实现方式中，形成填充膜，包括：采用原子层沉积工艺形成填充膜。由于在后续制备过程中，填充膜覆盖孔孔壁的部分会作为填充层保留在孔中。因此，填充膜的厚度会影响待形成的导电柱的电阻，填充膜的厚度太厚，会增大导电柱的电阻。采用原子层沉积工艺形成填充膜，可形成厚度较薄的填充膜，有利于降低导电柱的电阻。
在一种可能的实现方式中，对填充膜进行图案化，包括：采用干法刻蚀工艺，对填充膜进行图案化。这是一种技术成熟、成本低的工艺。
在一种可能的实现方式中，对填充膜进行图案化，包括：采用惰性原子轰击工艺，对填充膜进行图案化。这是一种技术成熟、成本低的工艺。
附图说明
图1为本申请实施例提供的一种电子设备的框架示意图；
图2A-图2D为本申请实施例提供的一种芯片的制备过程示意图；
图3A为本申请实施例提供的一种芯片的结构示意图；
图3B为本申请实施例提供的另一种芯片的结构示意图；
图4A-图4D为本申请实施例提供的另一种芯片的制备过程示意图；
图5A为本申请实施例提供的一种芯片的结构示意图；
图5B为本申请实施例提供的一种芯片的制备流程示意图；
图6A-图11B为本申请实施例提供的又一种芯片的制备过程示意图；
图12为本申请实施例提供的又一种芯片的结构示意图；
图13A-图13E为本申请实施例提供的又一种芯片的制备过程示意图；
图14为本申请实施例提供的又一种芯片的结构示意图；
图15A-图15F为本申请实施例提供的又一种芯片的制备过程示意图；
图16为本申请实施例提供的又一种芯片的结构示意图。
附图标记：
1-电子设备；2-显示模组；3-中框；4-壳体；5-盖板；200-衬底；10-电子元件；20-第一导电图案；30-介质层；301-第一介质层；302-第二介质层；31-孔；40-填充层； 41-填充膜；50-导电柱；51-导电柱本体；60-第二导电图案；61-第一重布线层；70-第一集成电路模块；80-第二重布线层；90-第二集成电路模块；100-第三重布线层；91-第一裸芯片；92-第二裸芯片；99-第四重布线层。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。
以下，本申请实施例中，术语“第一”、“第二”等仅用于描述方便，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”等的特征可以明示或者隐含地包括一个或者更多个该特征。在本申请的描述中，除非另有说明，“多个”的含义是两个或两个以上。
本申请实施例中，“上”、“下”、“左”以及“右不限于相对附图中的部件示意置放的方位来定义的，应当理解到，这些方向性术语可以是相对的概念，它们用于相对于的描述和澄清，其可以根据附图中部件附图所放置的方位的变化而相应地发生变化。
在本申请实施例中，除非上下文另有要求，否则，在整个说明书和权利要求书中，术语“包括”被解释为开放、包含的意思，即为“包含，但不限于”。在说明书的描述中，术语“一个实施例”、“一些实施例”、“示例性实施例”、“示例性地”或“一些示例”等旨在表明与该实施例或示例相关的特定特征、结构、材料或特性包括在本公开的至少一个实施例或示例中。上述术语的示意性表示不一定是指同一实施例或示例。此外，所述的特定特征、结构、材料或特点可以以任何适当方式包括在任何一个或多个实施例或示例中。
在描述一些实施例时，可能使用了“耦接”及其衍伸的表达。例如，描述一些实施例时可能使用了术语“耦接”以表明两个或两个以上部件有直接物理接触或电接触。然而，术语“耦接”也可能指两个或两个以上部件彼此间并无直接接触，但仍彼此协作或相互作用。这里所公开的实施例并不必然限制于本文内容。
在本申请实施例中，“和/或”，仅仅是一种描述关联对象的关联关系，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B这三种情况。另外，本文中字符“/”，一般表示前后关联对象是一种“或”的关系。
本申请实施例中参照作为理想化示例性附图的剖视图和/或平面图和/或等效电路图描述了示例性实施方式。在附图中，为了清楚，放大了层和区域的厚度。因此，可设想到由于例如制造技术和/或公差引起的相对于附图的形状的变动。因此，示例性实施方式不应解释为局限于本文示出的区域的形状，而是包括因例如制造而引起的形状偏差。例如，示为矩形的蚀刻区域通常将具有弯曲的特征。因此，附图中所示的区域本质上是示意性的，且它们的形状并非旨在示出设备的区域的实际形状，并且并非旨在限制示例性实施方式的范围。
本申请实施例提供一种的电子设备。该电子设备例如为消费性电子产品、家居式电子产品、车载式电子产品、金融终端产品、通信电子产品。其中，消费性电子产品如为手机(mobile phone)、平板电脑(pad)、笔记本电脑、电子阅读器、个人计算机(personal computer，PC)、个人数字助理(personal digital assistant，PDA)、桌 面显示器、智能穿戴产品(例如，智能手表、智能手环)、虚拟现实(virtual reality，VR)终端设备、增强现实(augmented reality，AR)终端设备、无人机等。家居式电子产品如为智能门锁、电视、遥控器、冰箱、充电家用小型电器(例如豆浆机、扫地机器人)等。车载式电子产品如为车载导航仪、车载高密度数字视频光盘(digital video disc，DVD)等。金融终端产品如为自动取款机(automated teller machine，ATM)机、自助办理业务的终端等。通信电子产品如为服务器、存储器、基站等通信设备。
本申请实施例对上述电子设备的具体形式不做特殊限制。以下实施例为了方便说明，均是以电子设备为手机为例进行举例说明。
在此情况下，如图1所示，电子设备1主要包括显示模组2、中框3、壳体(或者称为电池盖、后壳)4以及盖板5。
显示模组2具有能够看到显示画面的出光侧和与上述出光侧相对设置的背面，显示模组2的背面靠近中框3，盖板5设置在显示模组2的出光侧。
上述显示模组2，包括显示屏(display panel，DP)。
在本申请的一种可能的实施例中，显示模组2为液晶显示模组。在此情况下，上述显示屏为液晶显示屏(liquid crystal display，LCD)。基于此，显示模组2还包括位于液晶显示屏背面(远离LCD用于显示画面的一侧面)的背光模组(back light unit，BLU)。
背光模组可以向液晶显示屏提供光源，以使得液晶显示屏中的各个亚像素(sub pixel)能够发光以实现图像显示。
或者，在本申请的另一种可能的实施例中，显示模组2为有机发光二极管显示模组。在此情况下，上述显示屏为有机发光二极管(organic lightemitting diode，OLED)显示屏。由于OLED显示屏中每个亚像素内设置有电致发光层，所以可以使得OLED显示屏在接收到工作电压后，实现自发光。在此情况下，具有OLED显示屏的显示模组2中无需再设置上述背光模组。
盖板5位于显示模组2远离中框3一侧，盖板5例如可以是盖板玻璃(cover glass，CG)，该盖板玻璃可以具有一定的韧性。
中框3位于显示模组2和壳体4之间，中框3远离显示模组2的表面用于安装电池、印刷电路板(printed circuit board，PCB)、摄像头(camera)、天线等内部元件。壳体4与中框3盖合后，上述内部元件位于壳体4与中框3之间。
上述电子设备1还包括设置于PCB上的处理器(center processing unit，CPU)芯片、射频芯片、射频功率放大器((power amplifier，PA)芯片、系统级芯片(system on a chip，SOC)、电源管理芯片(power management integrated circuits，PMIC)、存储芯片(例如高带宽存储器(high bandwidth memory，HBM))、音频处理器芯片、触摸屏控制芯片、NAND flash(闪存)、图像传感器芯片、充电保护芯片等芯片，PCB用于承载上述芯片，并与上述芯片完成信号交互。
芯片(或者称之为逻辑集成器件，或者称之为集成电路器件)自身的可靠性等性能，对电子设备的使用寿命和性能有着直接的影响。
本申请实施例提供一种芯片，该芯片可以应用于上述电子设备中。
本申请实施例提供的芯片可以是未封装的裸芯片，未封装的裸芯片可以包括一个 集成电路模块(可以称为二维(2D)裸芯片)，未封装的裸芯片也可以包括多个集成电路模块(可以称为三维(3D)裸芯片)。本申请实施例提供的芯片也可以是封装后的芯片，封装后的芯片中可以包括一个裸芯片，也可以包括多个裸芯片。
以下，以几个示例，对本申请实施例提供的芯片进行示意说明。
示例一
本申请实施例提供一种芯片，芯片为2D裸芯片。
芯片制备过程通常包括前段制程(front end of line，FEOL)、中段制程(midend of line，MEOL)以及后段制程(back end of line，BEOL)。
如图2A所示，前段制程用于形成包括晶体管、电容、电感等电子元件的集成电路模块。其中，本申请实施例中的电子元件，可以是前段制程制备形成在衬底上、未独立封装的元件。当然，根据制备工艺的不同，包括晶体管、电容、电感等电子元件的集成电路模块也可以是后段制程中制备得到的，本申请实施例中仅为一种示意。图2A中以集成电路模块中的两个晶体管为例进行示意说明，晶体管包括源极S，漏极D以及栅极G。
如图2B所示，中段制程用于形成将多个电子元件中的导电图案引出至同一平面的转接层。转接层中的导电柱与电子元件的源极S、漏极D、栅极G耦接。转接层的形成，通常先形成具有孔的介质层，介质层中的孔位于导电图案上方，然后再用填孔技术形成导电柱。
其中，如图2C所示，在一些工艺节点中，中段制程形成的转接层包括两部分，第一部分为：设置在集成电路表面的底部金属和包裹在底部金属外围的第一中段介质层，底部金属与电子元件的源极S、漏极D、栅极G耦接。第二部分为：设置在底部金属表面的导电柱和包裹在导电柱外围的第二中段介质层，导电柱与底部金属耦接。底部金属例如为条状，导电柱例如为柱状。图2C的这种结构，可以优化后段制程中重布线层的排布。
以下为了便于说明，以中段制程形成的结构为图2C所示的结构为例进行示意。
如图2D所示，后段制程用于形成位于转接层上的重布线层。电子元件中的信号通过转接层传输至重布线层，从而引出至重布线层表面的信号端。芯片形成后，信号端暴露于芯片的表面。例如，信号端作为芯片的焊盘。
随着集成电路技术持续向前发展，芯片进一步向集成化、小型化发展，晶体管等电子元件的特征尺寸也随之缩小，对中段工艺中通过导电柱实现电子元件与重布线层的金属互连的填孔技术提出了新的挑战。
在一些技术中，采用电镀工艺形成铜(Cu)柱为导电柱。
在另一些技术中，采用化学气相沉积(chemical vapor deposition，CVD)形成钨(W)柱为导电柱。
但是采用电镀工艺通常需要阻挡层(或者粘附层)和电镀种子层，阻挡层覆盖导电柱的侧面和底面。采用化学气相沉积工艺通常需要成核层，成核层覆盖导电柱的侧面和底面。然而，阻挡层、种子层或者成核层会占据第二中段介质层中孔的孔隙空间，导致孔径减小、孔的深宽比增大，增大导电柱的工艺难度。而且，采用电镀工艺形成导电柱的过程中，是从孔的底部和侧面同时电镀金属柱，且在拐角处电镀的速率相对 较快，从而容易出现导电柱表面已经封闭，内部却留有孔隙的情况。同理，采用化学气相沉积工艺形成导电柱的过程中，也是从孔的底部和侧面同时沉积金属柱，且在拐角处沉积的速率相对较快，从而容易出现导电柱表面已经封闭，内部却留有孔隙的情况(如图3A所示)。而导电柱内部留有孔隙，会导致导电柱的电阻偏高，不能满足芯片微缩所需的性能。
基于此，在一些技术中，采用较薄的氮化钛(TiN)作为阻挡层，填孔钴(Co)作为导电柱。这样一来，可以增大导电柱的工艺窗口，降低导电柱的电阻。
然而，随着工艺节点进一步微缩，这种需要阻挡层的钴填充结构，依然无法满足高性能芯片要求。
基于此，在一些技术中，采用选择性生长的钨(W)化学气相沉积工艺形成导电柱。
选择性生长工艺从孔底部的底部金属的表面自下而上的沉积金属，不会在第二中段介质层中孔的孔壁上生长，无需阻挡层。这样一来，没有阻挡层占用孔隙空间，在孔中直接形成导电柱，可适用于高深宽比的芯片结构中。而且，由于金属钨是自下而上生长，因此，形成的导电柱内部不会成孔隙，可降低导电柱的电阻。再者，导电柱与底部金属之间没有阻挡层、成核层、填充层等膜层，可降低导电柱与底部金属之间的接触电阻。
但是，正因为金属钨不会在第二中段介质层中孔的孔壁上生长，采用选择性生长工艺生长的导电柱与第二中段介质层中孔壁的电介质之间没有阻挡层，这就容易在导电柱与第二中段介质层之间形成随机的、无规则的缝隙缺陷(如图3B所示)。这样一来，一方面，在后续填孔后的化学机械研磨(chemical mechanical polishing，CMP)，或者后续通过刻蚀工艺对膜层图案化等工艺中，容易从导电柱与第二中段介质层之间的缝隙处渗入酸性研磨液或者刻蚀液等溶液，导致导电柱底部的底部金属损伤，最终导致芯片失效。另一方面，由于导电柱与第二中段介质层之间的粘附效果差，在后续化学机械研磨过程中，容易出现将导电柱带走，导致导电柱缺失，从而导致芯片失效。
为了解决因导电柱与第二中段介质层未接触，导致导电柱底部的底部金属损伤和导电柱缺失，从而导致芯片失效的问题。
在一些技术中，如图4A所示，芯片的制备方法包括：
S1、如图4A所示，在第二中段介质层上形成孔，孔位于底部金属上方。
S2、如图4B所示，采用选择性生长工艺，形成导电柱本体。
S3、如图4C所示，重原子注入，减小导电柱本体与第二中段介质层之间的缝隙。
重原子可以是指原子序数大于硅的原子。重原子，例如可以是Ge(锗)、Ar(氩)、Si(硅)、Xe(氙)等重金属。
其中，如图4C所示，在注入重原子后，重原子进入第二中段介质层后，第二中段介质层体积增大发生膨胀，使得第二中段介质层朝向导电柱本体的表面会向导电柱本体一侧凸出，以缩小第二中段介质层与导电柱本体之间的缝隙。
S4、如图4D所示，化学机械研磨，形成导电柱。
通过该制备工艺形成的芯片，通过注入重原子，重原子进入第二中段介质层，使第二中段介质层体积增大发生膨胀，在第二中段介质层与导电柱之间具有缝隙的情况下， 第二中段介质层朝向导电柱本体的侧壁会向导电柱一侧凸出，以缩小第二中段介质层与导电柱之间的缝隙。从而解决因引第二中段介质层与导电柱之间存在缝隙，导致芯片失效的问题。
但是，注入重原子的过程中，很容易引起导电柱本体中的金属原子(例如W)溅射，导致金属原子溅射到第二中段介质层中。而金属原子溅射到第二中段介质层中后不易被去除，容易导致芯片失效。而且，如图4D中最右侧的导电柱所示，若缝隙位于靠近底部金属一侧，而缝隙顶部被封，采用上述方案无法对该缝隙进行填充。再者，若缝隙较大，采用上述方法无法完全消除缝隙。另外，采用上述方法，离子注入深度不太能满足需求，导致靠近底部金属处的缝隙的填充效果不理想。
因此，上述芯片及其制备方法，仍不能满足当下产品的需求。
基于此，本申请实施例还提供一种芯片及其制备方法，用于解决第二中段介质层与导电柱粘附性差的问题。
下面，结合芯片的结构，对导电柱的结构及制备方法进行示意说明。
如图5A所示，提供一种芯片，芯片包括介质层30和贯穿介质层30的导电柱50第一导电图案20、第二导电图案60及填充层40。第一导电图案20和第二导电图案60，分别位于介质层30的两边，导电柱50的两端分别与第一导电图案20接触、与第二导电图案60耦接；填充层40用于包裹导电柱50的至少部分侧面，以及填充导电柱50和介质层30之间的缝隙。
如图5B所示，芯片的制备方法，包括：
S10、提供介质层和位于介质层一边的第一导电图案。
在一些实施例中，如图6A所示，步骤S10包括：
S11、衬底200上形成电子元件10，以形成芯片的集成电路模块。
其中，在芯片作为射频器件应用于基站等电子设备中时，衬底200的材料为绝缘材料。在芯片作为功率器件应用于手机等电子设备中时，衬底200的材料为导电材料。
电子元件10是电子电路中的基本元素，具有至少一个引线接点，引线接点用于与布线互连耦接，以完成信号传输。电子元件10可以是电阻、电容、电感、晶体管、二极管等。例如，电子元件10为晶体管，电子元件10包括的引线接点为源极S、漏极D、栅极G。
芯片可以包括一个电子元件10，也可以包括多个电子元件10，本申请实施例提供的芯片的制备方法仅是以芯片中的一个电子元件10为例，对芯片中各部分的结构进行示意说明。芯片包括多个电子元件10的情况下，多个电子元件10可以是同一种类型的电子元件，也可以是不同种类型的电子元件。本申请实施例对芯片中的电子元件10的数量、种类、排布方式不做限定，根据需要合理设置即可。
示例的，如图6A所示，电子元件10包括互补金属氧化物半导体器件(complementary metal oxide semiconductor，CMOS)，CMOS的源极S、漏极D以及栅极G均为电子元件10的引线接点。其中，图6A中还示意出了位于栅极G下方的栅绝缘层和位于栅极G侧面的侧墙。图6A中示意的电子元件10的结构仅为一种示意，不做任何限定。
或者，示例的，电子元件10为高电子迁移率晶体管(high electron mobility transistor， HEMT)、异质结双极晶体管(heterojunction bipolar transistor，HBT)、双极结型晶体管(bipolar junction transistor，BJT)等。
S12、在电子元件10的表面形成底部金属(第一导电图案20)和包裹在底部金属外围的层间介质层(inter level dielectric，ILD)。
其中，不对底部金属俯视图的形状进行限定，例如可以为条状。底部金属可以作为本申请实施例中的第一导电图案20。当然，也可以是底部金属上的其他导电图案作为本申请实施例中的第一导电图案20，此处仅为一种示意。芯片包括的第一导电图案20可以是一个，也可以是多个。
S13、在层间介质层ILD上形成介质层30，介质层30具有孔31，孔31位于第一导电图案20上方，孔31与第一导电图案20接触。
本申请实施例不对孔31的形状和大小进行限定。孔31可以露出第一导电图案20远离衬底200的顶面的部分区域，孔31在衬底200上的投影可以位于第一导电图案20在衬底200上的投影内，孔31在衬底200上的投影也可以与第一导电图案20在衬底200上的投影重合。当然，孔31在衬底200上的投影也可以覆盖第一导电图案20在衬底200上的投影，只要确保后续形成在孔31内的导电柱50不会导致相邻第一导电图案20短路即可。或者理解为，孔31位于第一导电图案20的正上方，孔31的面积可以小于第一导电图案20的面积，孔31的面积也可以等于第一导电图案20的面积，孔31的面积也可以大于第一导电图案20的面积。本申请实施例以孔31的面积小于第一导电图案20的面积为例进行示意。
本申请实施例不对孔31的数量进行限定，孔31的数量与第一导电图案20的数量对应设置即可。需要强调的是，一个第一导电图案20可以与一个孔31对应设置，也就是说，一个第一导电图案20上方可以仅设置一个孔31。一个第一导电图案20也可以与多个孔31对应设置，也就是说，一个第一导电图案20上方可以设置多个孔31。也可以是多个第一导电图案20与同一个孔31对应设置，也就是说，多个第一导电图案20(例如该多个第一导电图案20例如传输同一信号)上方对应设置同一个孔31。
为了便于说明，如图6A所示，本申请实施例中以介质层30包括多个孔31，每个孔31露出一个第一导电图案20为例进行示意。
例如，可以采用化学气相沉积(chemical vapor deposition，CVD)、物理气相沉积或其它沉积方法形成中段介质膜，然后在中段介质膜上采用光刻和刻蚀的方法形成孔31，以制备得到介质层30。
介质层30的材料，例如可以包括硅的氧化物(例如，二氧化硅SiO 2)、硅的氮化物(例如，氮化硅SiN 4)、硅的掺杂氧化物、硅的氟化氧化物、硅的掺碳氧化物或者相关技术中已知的各种低介电常数(k)的电介质材料及其组合。
在一些实施例中，如图6A所示，介质层30为单层膜层。这样一来，结构简单，工艺步骤少。
在另一些实施例中，介质层30包括多层介质膜层。多层介质膜层的材料可以相同，多层介质膜层的材料也可以不相同。
示例的，如图6B所示，介质层30包括第一介质层301和第二介质层302，第一介质层301靠近第一导电图案20设置，第一介质层301的介电常数大于第二介质层 302的介电常数。
待形成的导电柱与第一导电图案20相距比较近的位置处设置为介电常数较大的第一介质层301，可提高第一导电图案20与待形成的导电柱之间的绝缘效果。
当然，介质层30也可以包括多层层叠设置的介质层，根据需要合理设置即可，本申请实施例中仅为一种示意。
在一些实施例中，如图6B所示，形成孔31后，第一导电图案20的表面为平面，步骤S10结束。
在另一些实施例中，如图6C所示，形成孔31后，步骤S10还包括：
S14、对第一导电图案20进行回刻蚀，在第一导电图案20的表面形成凹槽，凹槽与孔31联通。例如凹槽的开口大于或者等于孔31的开口。
当然，根据需要，可以在形成孔31后，先去除刻蚀副产物，然后再执行步骤S14。去除刻蚀副产物的方式，例如可以是先干法清洗，去除大部分刻蚀副产物；然后再湿法清洗，深度去除刻蚀副产物。
通过在第一导电图案20的表面回刻蚀形成凹槽，且凹槽的开口大于孔31的开口。可使后续形成的导电柱靠近第一导电图案20一侧的端部的横截面积大于其他位置处的横截面积，从而产生铆钉效应。这样一来，即使在后续制备过程中有酸性研磨液或者刻蚀液等溶液从导电柱与介质层30之间的缝隙处流入，也会先与导电柱端部位于凹槽内的部分接触，可降低酸性研磨液或者刻蚀液等溶液对第一导电图案20的损害。
S20、如图7所示，在介质层30上形成填充膜41。
其中，填充膜41覆盖介质层30远离第一导电图案20的表面、介质层30中孔31的孔壁以及第一导电图案20位于孔31下方的部分。
填充膜41的厚度，例如可以是
Figure PCTCN2022122024-appb-000001
例如，填充膜41的厚度为
Figure PCTCN2022122024-appb-000002
Figure PCTCN2022122024-appb-000003
或者
Figure PCTCN2022122024-appb-000004
其中，填充膜41的厚度，应当理解为是填充膜41的膜厚，或者理解为填充膜41与介质层30接触的表面到填充膜41远离介质层30的表面之间的距离。
例如，可以采用原子层沉积(atomic layer deposition，ALD)工艺形成填充膜41。
由于在后续制备过程中，填充膜41覆盖孔31孔壁的部分会作为填充层40保留在孔31中。因此，填充膜41的厚度会影响待形成的导电柱50的电阻，填充膜41的厚度太厚，会增大导电柱50的电阻。采用原子层沉积工艺形成填充膜41，可形成厚度较薄的填充膜41，有利于降低导电柱50的电阻。
本申请实施例对填充膜41的材料不做限定，能够与导电柱50和介质层30分别贴合接触即可。
在一些实施例中，填充膜41的材料包括金属。
示例的，填充膜41的材料包括Ti(钛)或者Ta(钽)中的至少一种。
在另一些实施例中，填充膜41的材料包括金属化合物。
示例的，填充膜41的材料包括TiN(氮化钛)、TiO x(氧化钛)、TaN(氮化钽)、Ta 2O 5(氧化钽)或者WO y(氧化钨)中的至少一种。其中，0<x<2，0<y<4。
通过将填充膜41的材料选择为金属或者金属化合物，可尽量降低通过填充膜41制备得到的填充层40的电阻，达到几乎可以忽略的程度，从而优化填充层40的存在 导致导电柱50电阻升高的问题。
在一些实施例中，填充膜41包括的金属与导电柱50包括的金属不同。
S30、如图8所示，对填充膜41进行图案化，去除填充膜41中覆盖介质层30和第一导电图案20的部分，形成填充层40。
填充膜41保留下来的部分为填充膜41覆盖孔31的孔壁的部分，因此，填充层40覆盖介质层30中孔31的孔壁，与孔31的孔壁接触。其中，根据需要，通过控制工艺，可使填充层40覆盖孔31的部分孔壁或者全部孔壁，图8中以填充层40覆盖孔31的全部孔壁为例进行示意。
示例的，采用干法刻蚀工艺，对填充膜41进行图案化。
或者，示例的，采用惰性原子轰击工艺，对填充膜41进行图案化。
S40、如图9所示，采用选择性生长(selectivedeposition)工艺，在孔31内形成导电柱本体51。
其中，选择性生长工艺形成的导电柱本体51与填充层40接触。
选择性生长工艺是指在衬底上限定的区域内进行的外延生长，应用在本申请中，就是在第一导电图案20的表面开始外延生长，不从介质层30的表面开始外延生长。由于本申请是通过选择性外延生长工艺直接在第一导电图案20这个金属结构的表面外延生长导电柱本体51的，因此，采用选择性生长工艺形成导电柱本体51，无需阻挡层、成核层等膜层。
那么，本申请采用选择性生长工艺最终形成的导电柱50，导电柱50的底面直接与第一导电图案20接触，导电柱50的侧面直接与填充层40接触，导电柱50为实心结构，导电柱50的内部没有孔隙。
在一些实施例中，采用选择性生长工艺，在孔31内从第一导电图案20的表面和填充层40的表面同步开始生长形成导电柱本体51。
这样一来，可以提高导电柱本体51与填充层40的接触效果，实现导电柱本体51与填充层40的贴合接触。
由于采用选择性生长工艺在不同材料表面的生长速率不同，因此，在一些实施例中，通过选择合适的填充层40的材料，以实现导电柱本体51在填充层40表面的生长速率，小于，导电柱本体51在第一导电图案20表面的生长速率。
其中，生长速率与外延生长过程中材料在第一导电图案20和填充层40表面的成核速率对应，成核速率越大，生长速率越大。
此处，填充层40的表面，可以理解为，填充层40与孔31的孔壁平行的表面。
导电柱本体51在填充层40表面的生长速率，小于，导电柱本体51在第一导电图案20表面的生长速率，那么，在导电柱本体51的生长过程中，导电柱本体51从填充层40表面生长的慢，从第一导电图案20表面自下而上生长的速度快。这样一来，可以避免因导电柱本体51在填充层40的表面生长速度过快，导致导电柱本体51顶部封口早，导电柱本体51内部存在缝隙的问题。
在一些实施例中，通过选择合适的填充层40的材料，以实现导电柱本体51在填充层40表面的生长速率，大于，导电柱本体51在介质层30表面的生长速率。
其中，导电柱本体51的高度，可以根据介质层30中孔31的深度以及后续化学机 械研磨工艺的研磨厚度调节。如图9所示，在同时形成多个导电柱本体51的情况下，多个导电柱本体51的高度可以相同，也可以不同。
在一些实施例中，如图9所示，导电柱本体51的表面低于介质层30的表面。也就是说，导电柱本体51的深度，小于孔31的深度。
这样一来，在后续化学机械研磨过程中，可减小被研磨掉的导电柱本体51的高度，减小材料浪费，降低成本。
其中，不对导电柱本体51的材料进行限定。导电柱本体51的材料可以包括铜(Cu)、铝(Al)、钛(Ti)、锆(Zr)、铪(Hf)、钒(V)、钌(Ru)、钴(Co)、镍(Ni)、钯(Pd)、铂(Pt)、钨(W)、银(Ag)、金(Au)、鎶(CN)等材料。
在一些实施例中，在孔31内形成导电柱本体51之前，先对介质层30中孔31进行表面处理，去除孔31的孔壁和第一导电图案20表面的化学残余物和悬挂键，提高选择性。
化学残余物例如可以是在介质层30上形成孔31的过程中残留下的化学物质，悬挂键例如可以是没有电子能配对的化学键。
对介质层30中孔31的表面进行处理的方式，例如可以是加热处理、等离子体处理、通入还原性气体(例如氢气)处理、通入氧化性气体(例如氧气和一氧化二氮)处理、通入惰性气体处理等方式进行表面处理。
其中，可以理解的是，在对填充膜41进行图案化与选择性生长导电柱本体51之间还包括其他步骤的情况下，上述对介质层30中孔31进行表面处理的步骤，可以在对填充膜41进行图案化之后进行。上述对介质层30中孔31进行表面处理的步骤，也可以在选择性生长导电柱本体51之前进行。上述对介质层30中孔31进行表面处理也可以在对填充膜41进行图案化之后合选择性生长导电柱本体51之前分别执行一次。本申请实施例对此不做限定，根据需要合理选择即可。
S50、如图10A所示，对导电柱本体51进行处理，形成导电柱50。
例如，可以采用化学机械研磨工艺，对导电柱本体51和介质层30进行研磨，形成导电柱50。
在一些实施例中，如图10B所示，步骤S50包括：
S51、在介质层30和导电柱本体51表面沉积成核层。
S52、采用金属氧化物化学气相沉积(metal oxide chemical vapor deposition，MOCVD)工艺，沉积牺牲层。
S53、采用化学机械研磨工艺，对牺牲层和导电柱本体51进行研磨，去除成核层和牺牲层，形成导电柱50。
通过沉积牺牲层，可使化学机械研磨的速率均匀，研磨效果好，导电柱50表面平整，多个导电柱50的表面平齐度高。
其中，导电柱50贯穿介质层30，与第一导电图案20接触；填充层40用于包裹导电柱50的至少部分侧面，以及填充导电柱50和介质层30之间的缝隙。
当然，在形成导电柱50的过程中，也可以不包括对导电柱本体51进行处理的步骤。直接采用选择性生长工艺，在孔31内形成导电柱50，导电柱50与填充层40接触。
S60、如图11A所示，在介质层30远离第一导电图案20一边形成第二导电图案60，第二导电图案60与导电柱50耦接。
本申请实施例对第二导电图案60的形状、作用、材料不做限定，根据应用场景合理设置即可。
在一些实施例中，如图11A所示，第二导电图案60为第一重布线层61中包括的导电图案。也就是说，第二导电图案60为后段工艺制备的重布线层中的导电图案。
例如，第二导电图案60为第一重布线层61中最靠近介质层30的一层布线层中的导电图案。其中，第二导电图案60可以为柱状，第二导电图案60也可以为线条状，第二导电图案60还可以是其他形状，本申请实施例对此不做限定。
其中，一个第二导电图案60可以与一个或多个导电柱50耦接。导电柱50两端分别耦接有第一导电图案20和第二导电图案60，导电柱50与第一导电图案20直接接触，导电柱50与第二导电图案60可以直接接触，也可以间接接触。
本申请实施例提供的芯片的制备方法，通过在选择性生长导电柱50之前，通过成膜及图案化工艺，在介质层30中孔31的侧壁附着填充层40，填充层40与介质层30和导电柱50分别接触，相当于通过填充层40消除了导电柱50与介质层30之间的缝隙。一方面，可以有效阻挡研磨液、清洗液或者刻蚀液等溶液通过上述缝隙对第一导电图案20的损伤。另一方面，由于导电柱50与填充层40的连接效果好，因此可以改善在化学机械研磨过程中，将导电柱带走，导致导电柱缺失，从而导致芯片失效的问题。而本申请实施例提供的芯片的制备方法，无需注入重原子来缩小导电柱50与介质层30之间的缝隙，因此不会出现在注入重原子的过程中，引起导电柱本体中的金属原子溅射，导致芯片失效的问题。
关于芯片的结构，请继续参考图11B，芯片包括介质层30、填充层40、导电柱50、第一导电图案20以及第二导电图案60。
介质层30具有孔31，孔31沿介质层30的厚度方向贯穿介质层30。导电柱50设置在介质层30的孔31内，导电柱50沿介质层30的厚度方向贯穿介质层30。导电柱50的深度(或者理解为高度)与介质层30的厚度可以相同。
填充层40包裹导电柱50的至少部分侧面，填充层40与导电柱50的侧壁和介质层30的孔壁分别接触。
其中，导电柱50可以为一个，也可以为多个。图11B中以芯片包括多个导电柱50为例进行示意。
另外，本申请实施例对导电柱50的形状不做限定，导电柱50的形状可以是圆柱状、矩形柱状、或者长方体形柱状等。
在一些实施例中，导电柱50通过选择性生长工艺形成。
在一些实施例中，导电柱50在填充层40表面的生长速率，小于，导电柱在第一导电图案20表面的生长速率。导电柱50在填充层40表面的生长速率，大于，导电柱在介质层30表面的生长速率。
这样一来，通过选择性生长工艺在第一导电图案20表面生长导电柱50的过程中，同时会沿着填充层40的表面开始生长。导电柱50与填充层40的之间没有缝隙，形成的导电柱50与填充层40的连接效果好。
示例的，填充层40的金属。
例如，填充层40的材料包括Ti、Ta中的至少一种。
或者，示例的，填充层40的材料包括属化合物。
例如，填充层40的材料包括TiN、TaN、TiOx、Ta 2O 5、WOy中的至少一种。其中，0<x<2，0<y<4。
在一些实施例中，填充层40包括的金属与导电柱50包括的金属不同。
例如，导电柱50包括W，填充层40包括Ti、Ta、TiN、TaN、TiOx或者Ta 2O 5。
关于介质层30，可参考上述芯片的制备方法中关于介质层30的相关描述，此处不再赘述。
第一导电图案20和第二导电图案60分别位于介质层30的两边。其中，介质层30的两边可以理解为垂直于介质层30厚度方向的上边和下边。或者理解为，第一导电图案20和第二导电图案60位于介质层30相对的两侧。其中，介质层30的两边可以理解为垂直于介质层30厚度方向的上侧和下侧。
第一导电图案20与导电柱50的一端直接接触，以实现第一导电图案20与导电柱50的电连接。第二导电图案60与导电柱50的另一端直接接触或者间接接触，以实现第二导电图案60与导电柱50的电连接。
本申请实施例不对第一导电图案20和第二导电图案60的形状进行限定，第一导电图案20和第二导电图案60能够导电即可。关于第一导电图案20和第二导电图案60在芯片中的具体结构，可以参考上述描述芯片的制备方法时，关于第一导电图案20和第二导电图案60的相关描述。
在一些实施例中，导电柱50的深宽比大于2:1。
例如，导电柱50的深宽比为3:1、4:1、5:1、6:1、7:1、8:1、9:1、10:1、11:1、12:1或者更大。导电柱50的深度，是指导电柱50沿垂直于介质层30方向上的尺寸。导电柱50的宽度，是指导电柱50沿平行于介质层30方向上的尺寸。
上述以第一导电图案20设置于导电柱50与电子元件20之间为例进行示意。当然，上述导电柱50也可以直接与电子元件20耦接，而无需上述底部金属，那么电子元件20的导电部为第一导电图案20。
本申请实施例提供的芯片，导电柱50与介质层30之间设置有填充层40，填充层40与导电柱50和介质层30分别接触。这样一来，一方面，填充层40填充导电柱50与介质层30之间的间隙，导电柱50与介质层30之间没有缝隙，导电柱50与填充层40之间也没有缝隙。从而几乎可以避免导电柱50与介质层30之间的缝隙处因渗入酸性研磨液、清洗液或者刻蚀液等溶液，导致导电柱50底部的第一导电图案20损伤，最终导致芯片失效的问题。另一方面，通过设置填充层40，可提高导电柱50与介质层30的粘附性，改善因导电柱50缺失导致芯片失效的问题。
另外，导电柱50与第一导电图案20直接接触，二者之间没有阻挡层、成核层等膜层，可降低导电柱50的接触电阻，满足芯片性能。
在一些实施例中，本申请实施例还提供一种芯片，该芯片为对上述2D裸芯片封装后的芯片。
示例二
本申请实施例提供一种芯片，芯片为3D裸芯片。
如图12所示，芯片包括依次层叠设置的第一集成电路模块70、第二重布线层80、第二集成电路模块90以及第三重布线层100。
第三重布线层100远离第二集成电路模块90的表面为芯片的有源面，第一集成电路模块70远离第二重布线层80的表面为芯片的非有源面。
其中，第一集成电路模块70和第二集成电路模块90可以理解为是通过前段制程制备形成的包括多个电路电子元件的结构。
本申请实施例对第一集成电路模块70用于实现的功能不做限定，那么，第一集成电路模块70包括的电子元件的结构也不做限定。例如，第一集成电路模块70包括多个电子元件，多个电子元件通过后续工艺制备的结构实现串联、并联耦接，以实现某些功能。同理，本申请实施例对第二集成电路模块90用于实现的功能不做限定，那么，第二集成电路模块90包括的电子元件的结构也不做限定。例如，第二集成电路模块90包括多个电子元件，多个电子元件通过后续工艺制备的结构实现串联、并联耦接，以实现某些功能。图12中仅是以第一集成电路模块70包括的一个CMOS为例进行示意，以第二集成电路模块90包括的一个CMOS为例进行示意。
示例的，第一集成电路模块70为逻辑区的电路结构，第二集成电路模块90为存储区的电路结构，或者，第一集成电路模块70为逻辑区的电路结构，第二集成电路模块90为探测器的电路结构。
需要说明的是，芯片中可以包括通过中段制程制备形成的转接层。当然，根据需要，芯片中也可以不包括通过中段制程制备形成的转接层。
请继续参考图12，第二重布线层80包括第一导电图案20，第一导电图案20与第一集成电路模块70耦接。例如，第二重布线层80中最靠近第二集成电路模块90的一层布线层包括第一导电图案20，第一导电图案20与第一集成电路模块70中电子元件的电极(例如源极S、漏极D、栅极D)接触。
第三重布线层100包括第二导电图案60，例如，第三重布线层100中最靠近第二集成电路模块90的一层布线层包括第二导电图案60。导电柱50贯穿第二集成电路模块90，导电柱50通过转接层中的导电柱与第二导电图案60耦接(在芯片不包括转接层的情况下，导电柱50可以直接与第二导电图案60接触)。第三重布线层100还与第二集成电路模块90耦接。
也就是说，本示例示意的芯片，包括至少两个集成电路模块，图12中仅是以第一集成电路模块70和第二集成电路模块90为例进行示意。图12所示的芯片的传输路径包括两条：芯片有源面的信号依次经第三重布线层100、导电柱50、第二重布线层80传输至第一集成电路模块70。芯片有源面的信号还经第三重布线层100传输至第二集成电路模块90。
请继续参考图12，导电柱50的至少部分侧面还包裹有填充层40(图12中以导电柱50的全部侧面包裹有填充层40为例进行示意)，填充层40与介质层30和导电柱50分别接触。填充层40和导电柱50的结构，可以与示例一中相同，可以参考示例一中的相关描述，此处不再赘述。
同理，上述导电柱50和填充层40设置在介质层30中。此处需要强调的是，示例一中的介质层30的材料为绝缘材料，本示例中导电柱50和第二导电柱32贯穿第二集成电路模块90，因此，包裹在导电柱50和第二导电柱32外围的介质层30为第二集成电路模块90的衬底。也就是说，介质层30的材料为半导体。
下面，对示意一种本申请实施例提供的芯片的制备方法，包括：
S10、如图13A所示，提供介质层30和位于介质层30一边的第一导电图案20。
本申请实施例对图13A所示结构的制备方法不做限定，例如可以先通过前段制程、中段制程以及后段制程形成包括第一集成电路模块70、转接层、第二布线层60的结构，然后在前述结构上再通过前段制程形成第二集成电路模块90。第二集成电路模块90包括介质层30，第二布线层60包括第一导电图案20。
其中，如图13A所示，介质层30包括孔31，孔31位于第一导电图案20上方，与第一导电图案20接触。
S20、如图13B所示，在介质层30上形成填充膜41。
S30、如图13C所示，对填充膜41进行图案化，去除填充膜41中覆盖介质层30和第一导电图案20的部分，形成填充层40。
S40、如图13D所示，采用选择性生长(selective deposition)工艺，在孔31内形成导电柱本体51。
S50、如图13E所示，对导电柱本体51进行处理，形成导电柱50。
其中，步骤S20、S30、S40以及S50可以参考示例一中的相关描述，此处不再赘述。
S60、如图12所示，在介质层30远离第一导电图案20一边形成第二导电图案60，第二导电图案60与导电柱50耦接。
例如，在介质层30上形成第三重布线层100，第三重布线层100包括第二导电图案60。例如，第三重布线层100中最靠近第二集成电路模块90的一层布线层包括第二导电图案60。
随着电子设备性能和集成度的提高，单一功能的芯片已经无法满足需求，3D裸芯片逐渐成为未来发展趋势。但是就会面临导电柱50的深宽比较大的问题。因此，本申请实施例提供的芯片中导电柱50通过选择性生长工艺形成，无需阻挡层等膜层。这样一来，一方面没有阻挡层等膜层占用空间，导电柱50的深宽比可以比较大，以满足3D裸芯片的需求。另一方面，没有阻挡层等膜层影响导电柱50与第一导电图案20的接触电阻，可有效降低导电柱50与第一导电图案20的接触电阻。
在此基础上，导电柱50与介质层30之间设置有粘附层40，粘附层40与导电柱50和介质层30均接触。因此，导电柱50与介质层30之间不存在缝隙。从而几乎可以避免导电柱50与介质层30之间的缝隙处因渗入酸性研磨液、清洗液或者刻蚀液等溶液，导致导电柱50底部的第一导电图案20损伤，最终导致芯片失效的问题。
在一些实施例中，本申请实施例还提供一种芯片，该芯片为对本示例中的上述3D裸芯片封装后的芯片。
示例三
本申请实施例提供一种芯片，芯片为封装后的芯片。
在一些实施例中，如图14所示，芯片包括第一裸芯片91、第二裸芯片92以及第四布线层99。
第一裸芯片91的焊盘为第一导电图案20，导电柱50从第一裸芯片91的非有源面贯穿至焊盘背面。第四重布线层99包括第二导电图案60，第二导电图案60与导电柱50耦接。第二裸芯片92位于第四重布线层99远离第一裸芯片91一侧，第二裸芯片92与第四重布线层99耦接。示例的，如图14所示，第二裸芯片92通过焊球与第四重布线层99键合耦接。
第一裸芯片91的信号经焊盘传输至与第一裸芯片91键合的基板(图14中未示意出)中。第二裸芯片92的信号传输至第四重布线层99，并经导电柱50传输至第一裸芯片91的焊盘，然后传输至与第一裸芯片91键合的基板中。
本申请实施例对第一裸芯片91和第二裸芯片92的结构不做限定，根据需要合理设置即可。
请继续参考图14，导电柱50的至少部分侧面还包裹有填充层40(图14中以导电柱50的全部侧面包裹有填充层40为例进行示意)，填充层40与介质层30和导电柱50分别接触。填充层40和导电柱50的结构，可以与示例一中相同，可以参考示例一中的相关描述，此处不再赘述。
同理，上述导电柱50和填充层40设置在介质层30中。此处需要强调的是，本示例中导电柱50从第一裸芯片91的非有源面贯穿至焊盘背面。因此，如图15A所示，本示例中的介质层30包括前段制程形成的集成电路模块中的衬底、中段制程形成的转接层中的绝缘层、后段制程形成的重布线层中的多层绝缘层。介质层30中的孔31位于第一裸芯片91中焊盘的上方。
下面，对示意一种本申请实施例提供的芯片的制备方法，包括：
S10、如图15A所示，提供介质层30和位于介质层30一边的第一导电图案20。
图12B所示的结构，例如可以先通过前段制程、中段制程和后段制程形成裸芯片，然后采用开孔工艺形成孔31，以得到本申请中的第一裸芯片91。
其中，如图15A所示，介质层30包括孔31，孔31位于第一导电图案20上方，与第一导电图案20接触。
S20、如图15B所示，在介质层30上形成填充膜41。
S30、如图15C所示，对填充膜41进行图案化，去除填充膜41中覆盖介质层30和第一导电图案20的部分，形成填充层40。
S40、如图15D所示，采用选择性生长(selective deposition)工艺，在孔31内形成导电柱本体51。
S50、如图15E所示，对导电柱本体51进行处理，形成导电柱50。
其中，步骤S20、S30、S40以及S50可以参考示例一中的相关描述，此处不再赘述。
S60、如图15F所示，在介质层30远离第一导电图案20一边形成第二导电图案60，第二导电图案60与导电柱50耦接。
示例的，在介质层30远离第一导电图案20一边形成第四重布线层99，第四重布 线层99包括第二导电图案60。
S70、如图14所示，将第二裸芯片92与第四重布线层99键合耦接。
芯片例如可以通过第一裸芯片91有源面上的焊球与基板键合。
在另一些实施例中，如图16所示，芯片包括第一裸芯片91、第二裸芯片92以及焊点。
第一裸芯片91的焊盘为第一导电图案20，导电柱50从第一裸芯片91的非有源面贯穿至焊盘背面。焊点为第二导电图案60，第二导电图案60与导电柱50耦接。
第一裸芯片91的信号经焊盘传输至导电柱50，然后传输至焊点(第二导电图案60)，然后传输至与第一裸芯片91键合的基板(图16中未示意出)中。
请继续参考图16，导电柱50的至少部分侧面还包裹有填充层40(图16中以导电柱50的全部侧面包裹有填充层40为例进行示意)，填充层40与介质层30和导电柱50分别接触。填充层40和导电柱50的结构，可以与示例一中相同，可以参考示例一中的相关描述，此处不再赘述。
同理，上述导电柱50和填充层40设置在介质层30中。此处需要强调的是，本示例中导电柱50从第一裸芯片91的非有源面贯穿至焊盘背面。因此，如图16所示，本示例中的介质层30包括前段制程形成的集成电路模块中的衬底、中段制程形成的转接层中的绝缘层、后段制程形成的重布线层中的多层绝缘层。介质层30中的孔31位于第一裸芯片91中焊盘的上方。
下面，对示意一种本申请实施例提供的芯片的制备方法，包括：
S10-S50与本示例中芯片包括第四重布线层99时芯片的制备方法相同，此处不再赘述。
S60、如图16所示，在介质层30远离第一导电图案20一边形成第二导电图案60，第二导电图案60与导电柱50耦接。
示例的，第二导电图案60为位于第一裸芯片91非有源面上的焊点。例如，第二导电图案60为焊球、微凸点等结构。
S70、将第二裸芯片92与第一裸芯片91的焊盘键合耦接。
其中，步骤S70还可以在步骤S10之前，或者在其他步骤之后，本申请实施例不限定为步骤S60在S50之后。
芯片例如可以通过第一裸芯片91非有源面上的焊点与基板键合。
随着电子设备性能和集成度的提高，单一功能的芯片已经无法满足需求，3D堆叠封装芯片逐渐成为未来发展趋势。但是就会面临导电柱50和第二导电柱32的深宽比较大的问题。因此，本申请实施例提供的芯片基于导电柱50的结构和制备方法，可以适用于对深宽比要求较高的芯片中。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到的变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。

Claims (15)

  1. 一种芯片，其特征在于，包括：
    介质层；
    第一导电图案和第二导电图案，分别位于所述介质层的两边；
    导电柱，贯穿所述介质层，所述导电柱的两端分别与第一导电图案接触、与所述第二导电图案耦接；
    填充层，用于包裹所述导电柱的至少部分侧面，以及填充所述导电柱和所述介质层之间的缝隙。
  2. 根据权利要求1所述的芯片，其特征在于，所述导电柱采用选择性生长工艺形成；
    所述导电柱在所述填充层表面的生长速率，小于，所述导电柱在所述第一导电图案表面的生长速率；
    所述导电柱在所述填充层表面的生长速率，大于，所述导电柱在所述介质层表面的生长速率。
  3. 根据权利要求1或2所述的芯片，其特征在于，所述填充层的材料包括金属或者金属化合物。
  4. 根据权利要求3所述的芯片，其特征在于，所述填充层包括的金属与所述导电柱包括的金属不同。
  5. 根据权利要求3所述的芯片，其特征在于，所述填充层的材料包括TiN、TaN、TiOx、Ta 2O 5、WOy、Ti、Ta中的至少一种；其中，0<x<2，0<y<4。
  6. 根据权利要求1-5任一项所述的芯片，其特征在于，所述芯片包括电子元件和第一重布线层；所述第一导电图案设置在所述导电柱与所述电子元件之间，所述第一重布线层包括所述第二导电图案。
  7. 根据权利要求1-5任一项所述的芯片，其特征在于，所述芯片包括依次层叠设置的第一集成电路模块、第二重布线层、第二集成电路模块以及第三重布线层；
    所述第二重布线层包括所述第一导电图案，所述第一导电图案与所述第一集成电路模块耦接；所述导电柱贯穿所述第二集成电路模块，所述第三重布线层包括所述第二导电图案；所述第三重布线层还与所述第二集成电路模块耦接。
  8. 根据权利要求1-5任一项所述的芯片，其特征在于，所述芯片包括裸芯片；
    所述裸芯片的焊盘为所述第一导电图案；所述导电柱从所述裸芯片的非有源面贯穿至所述焊盘背面；
    所述芯片还包括第四重布线层，所述第四重布线层包括所述第二导电图案。
  9. 根据权利要求1-5任一项所述的芯片，其特征在于，所述芯片包括裸芯片；
    所述裸芯片的焊盘为所述第一导电图案；所述导电柱从所述裸芯片的非有源面贯穿至所述焊盘背面；
    所述第二导电图案为位于所述裸芯片非有源面上的焊点。
  10. 一种电子设备，其特征在于，包括权利要求1-9任一项所述的芯片和电路板，所述芯片设置在所述电路板上。
  11. 一种芯片的制备方法，其特征在于，包括：
    提供介质层和位于所述介质层一边的第一导电图案；所述介质层具有孔，所述孔位于所述第一导电图案上方；
    形成填充膜，所述填充膜覆盖所述介质层远离所述第一导电图案的表面、所述孔的孔壁以及所述第一导电图案位于所述孔下方的部分；
    对所述填充膜进行图案化，去除所述填充膜中覆盖介质层和所述第一导电图案的部分，形成填充层；
    采用选择性生长工艺，在所述孔内形成导电柱；所述导电柱贯穿所述介质层，与所述第一导电图案接触；其中，所述填充层用于包裹所述导电柱的至少部分侧面，以及填充所述导电柱和所述介质层之间的缝隙；
    在所述介质层远离所述第一导电图案一边形成第二导电图案，所述第二导电图案与所述导电柱耦接。
  12. 根据权利要求11所述的芯片的制备方法，其特征在于，采用选择性生长工艺，在所述孔内形成导电柱，包括：
    采用选择性生长工艺，在所述孔内从所述第一导电图案的表面和所述填充层的表面同步开始生长形成所述导电柱；
    其中，所述导电柱在所述填充层表面的生长速率，小于，所述导电柱在所述第一导电图案表面的生长速率；
    所述导电柱在所述填充层表面的生长速率，大于，所述导电柱在所述介质层表面的生长速率。
  13. 根据权利要求11或12所述的芯片的制备方法，其特征在于，所述填充膜的材料包括金属或者金属化合物。
  14. 根据权利要求11-13任一项所述的芯片的制备方法，其特征在于，所述形成填充膜，包括：采用原子层沉积工艺形成所述填充膜。
  15. 根据权利要求11-14任一项所述的芯片的制备方法，其特征在于，所述对所述填充膜进行图案化，包括：
    采用干法刻蚀工艺或者惰性原子轰击工艺，对所述填充膜进行图案化。
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