WO2023201598A1 - 芯片及其制备方法、电子设备 - Google Patents

芯片及其制备方法、电子设备 Download PDF

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Publication number
WO2023201598A1
WO2023201598A1 PCT/CN2022/088028 CN2022088028W WO2023201598A1 WO 2023201598 A1 WO2023201598 A1 WO 2023201598A1 CN 2022088028 W CN2022088028 W CN 2022088028W WO 2023201598 A1 WO2023201598 A1 WO 2023201598A1
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WIPO (PCT)
Prior art keywords
metal
pillar
conductive
chip
dielectric layer
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PCT/CN2022/088028
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English (en)
French (fr)
Inventor
黄伟川
陈东奇
谢雨思
林军
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华为技术有限公司
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Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to PCT/CN2022/088028 priority Critical patent/WO2023201598A1/zh
Priority to CN202280083744.7A priority patent/CN118402058A/zh
Publication of WO2023201598A1 publication Critical patent/WO2023201598A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body

Definitions

  • the present application relates to the field of semiconductor technology, and in particular to a chip and its preparation method, and electronic equipment.
  • the reduction in the size of the conductive patterns will increase the difficulty of interconnection coupling between the conductive patterns.
  • the resistance, preparation process and other characteristics of the conductive pillars will have a direct impact on the interconnection coupling effect and the yield of the chip.
  • Embodiments of the present application provide a chip, a preparation method thereof, and electronic equipment to solve the problem of how to improve the interconnection coupling effect between conductive patterns in the chip.
  • a first aspect of the embodiment of the present application provides a chip.
  • the chip may be a bare chip or a packaged chip.
  • the chip includes: a first conductive pillar and a dielectric layer.
  • the first conductive pillar is arranged in the dielectric layer and penetrates the dielectric layer along the thickness direction of the dielectric layer, or it can be understood that the dielectric layer is wrapped around the periphery of the first conductive pillar; the first conductive pattern and The second conductive pattern is located on opposite sides of the first conductive pillar, and the first conductive pillar is correspondingly coupled to the first conductive pattern and the second conductive pattern; wherein the first conductive pillar includes a metal pillar and a metal compound layer, and the metal compound layer The first conductive pillar is located between the metal pillar and the dielectric layer and covers at least part of the side of the metal pillar; the first conductive pillar contacts the dielectric layer through the metal compound layer and the side of the metal pillar that is not covered by the metal compound layer.
  • the first conductive pillar is in contact with the dielectric layer. There is no barrier layer or other film layer between them. It should be understood that if all sides of the metal pillar are covered by the metal compound layer, then the portion of the metal pillar that is not covered by the metal compound layer does not exist, and the first conductive pillar contacts the dielectric layer through the metal compound layer. In addition, depending on the chip structure, the structures of the first conductive pattern and the second conductive pattern are also different.
  • the first conductive pattern and the second conductive pattern are coupled through the first conductive pillar, and the first conductive pillar is directly in contact with the dielectric layer without a barrier layer or other film layer.
  • no film layer such as a barrier layer occupies space, and the aspect ratio of the first conductive pillar can be increased.
  • the first conductive pillar includes a metal pillar and a metal compound layer. Based on process limitations, the gap defects existing between the formed metal pillar and the dielectric layer can be filled by the metal compound layer.
  • the first conductive pattern at the bottom of the first conductive pillar is damaged due to the penetration of acidic grinding fluid, cleaning fluid or etching solution into the gap between the first conductive pillar and the dielectric layer, and ultimately leads to chip failure.
  • the gap between the metal pillar and the dielectric layer is very small, the volume of the metal compound layer located in the gap is also very small. Therefore, the impact of the metal compound layer on the resistance of the first conductive pillar is very small and almost negligible, and the presence of the metal compound layer will not cause an increase in the resistance of the first conductive pillar.
  • the metal pillars are formed using a selective growth process.
  • the metal pillar is formed using a selective growth process without the need for film layers such as barrier layers, which can increase the width-to-length ratio of the metal pillar. Moreover, no pores will be formed inside the formed metal pillar, which can reduce the resistance of the metal pillar.
  • the metal compound layer includes a metal oxide material.
  • the metal compound layer includes metal nitride material.
  • the metal compound layer includes metal oxide materials and metal nitride materials. A simple implementation method.
  • the metal compound layer includes a metal oxynitride material.
  • the metal compound layer includes metal oxide materials and metal oxynitride materials. A simple implementation method.
  • the metal compound layer includes metal nitride materials and metal oxynitride materials. A simple implementation method.
  • the metal compound layer includes metal oxide materials, metal nitride materials, and metal oxynitride materials. A simple implementation method.
  • the metal compound layer is obtained by oxidizing the side surface of the metal pillar.
  • a simple implementation method is a simple implementation method.
  • the metal compound layer is obtained by nitriding the side surface of the metal pillar.
  • the metal compound layer is obtained by oxidizing and nitriding the side surfaces of the metal pillars. A simple implementation method.
  • the metal compound layer includes the same metal as the metal compound layer.
  • the surface of the metal compound layer facing the metal pillar is flat.
  • the metal compound layer is formed using process-controllable processing methods to improve the controllability of the chip structure.
  • the width of the metal compound layer is 0.5 nm to 5 nm in a direction parallel to the dielectric layer. Controlling the width of the metal oxide layer to less than 5 nm can not only fill the gap between the first conductive pillar and the dielectric layer, but also make the metal oxide layer have little impact on the resistance of the first conductive pillar, which is almost negligible. Thus, the problem that the presence of the metal oxide layer causes the resistance of the first conductive pillar to increase is optimized.
  • the material of the first conductive pattern includes metal, and the first conductive pillar is in contact with the first conductive pattern.
  • the metal pillar is formed using a selective growth process on the metal structure. The process is simple and easy to implement.
  • the chip includes an electronic component and a first redistribution layer; the first conductive pattern is disposed between the first conductive pillar and the electronic component, and the first redistribution layer includes a second conductive pattern.
  • the chip includes a first integrated circuit module, a second rewiring layer, a second integrated circuit module and a third rewiring layer that are stacked in sequence;
  • the second rewiring layer includes a first conductive pattern, The first conductive pattern is coupled to the first integrated circuit module; the first conductive pillar penetrates the second integrated circuit module; the third redistribution layer includes the second conductive pattern; the third redistribution layer is also coupled to the second integrated circuit module.
  • the chip includes a bare chip; the bonding pad of the bare chip is a first conductive pattern; the first conductive pillar penetrates from the non-active surface of the bare chip to the back of the bonding pad; the chip also includes a fourth layer of wiring layer, the fourth redistribution layer includes a second conductive pattern.
  • the chip includes a bare chip; the bonding pad of the bare chip is a first conductive pattern; the first conductive pillar penetrates from the non-active surface of the bare chip to the back of the bonding pad; the second conductive pattern is located on the bare chip Solder joints on the non-active side of the chip.
  • the chip includes a plurality of first conductive pillars, and the oxygen content, nitrogen content, or width of the metal compound layers included in the plurality of first conductive pillars are not exactly the same.
  • the chip further includes a second conductive pillar.
  • the second conductive pillar is a metal pillar.
  • the metal pillar is arranged in the dielectric layer and penetrates the dielectric layer along the thickness direction of the dielectric layer. The side surfaces of the metal pillar are in contact with the dielectric layer. layer contact.
  • the aspect ratio of the first conductive pillar is greater than 2:1.
  • the structure of the first conductive pillar provided by this application can be applied to structures with a large aspect ratio.
  • a second aspect of the embodiments of the present application provides an electronic device, including a chip according to any one of the first aspects and a circuit board, and the chip is disposed on the circuit board.
  • the electronic device provided by the embodiment of the present application includes the chip of any one of the first aspects, and its beneficial effects are the same as those of the chip, which will not be described again here.
  • a third aspect of the embodiment of the present application provides a method for preparing a chip, including: providing a dielectric layer and a first conductive pattern located on the side of the first middle dielectric layer; the dielectric layer has a hole, and the hole is located above the first conductive pattern; using The selective growth process starts from the surface of the first conductive pattern in the hole and grows from bottom to top to form the metal pillar body; the metal pillar body is chemically treated so that the side of the metal pillar body that is not in contact with the dielectric layer expands to contact with the dielectric layer.
  • the first conductive pillar includes a metal pillar and a metal compound layer, the part of the metal pillar body that has not been chemically treated is a metal pillar, and the side of the metal pillar body
  • the chemically treated part is the metal compound layer; the metal compound layer is in contact with the dielectric layer, and the side of the metal pillar that is not covered by the metal compound layer is also in contact with the dielectric layer; a second conductive pattern is formed on the side of the dielectric layer away from the first conductive pattern, The second conductive pattern is coupled to the first conductive pillar.
  • chemical treatment is performed on the metal column body, including: oxidizing the metal column body.
  • chemical treatment is performed on the metal pillar body, including: nitriding the metal pillar body.
  • oxidizing the metal column body includes: oxidizing the metal column body using a liquid containing oxygen or an oxidant solution. A simple implementation method.
  • nitriding the metal column body includes: using nitrogen-containing gas to nitridize the metal column body.
  • oxidizing and nitriding the metal column body includes: using gas containing oxygen and nitrogen to oxidize and nitride the metal column body.
  • the thickness of the metal compound formed on the top surface is less than 10 nm. In this way, the metal compound on the top surface of the metal pillar body can be removed using the existing chemical mechanical grinding process without changing the process and equipment.
  • the width of the metal compound layer is 0.5 nm to 5 nm in a direction parallel to the dielectric layer. Controlling the width of the metal oxide layer to less than 5 nm can not only fill the gap between the first conductive pillar and the dielectric layer, but also make the metal oxide layer have little impact on the resistance of the first conductive pillar, which is almost negligible. Thus, the problem that the presence of the metal oxide layer causes the resistance of the first conductive pillar to increase is optimized.
  • the dielectric layer has multiple holes, and a selective growth process is used to form multiple metal pillar bodies; while forming the first conductive pillar, a second conductive pillar is also formed; the metal on the side contacting the dielectric layer After the chemically treated portion of the top surface of the metal pillar body is removed from the pillar body, a second conductive pillar is formed, and the second conductive pillar is a metal pillar.
  • Figure 1 is a schematic framework diagram of an electronic device provided by an embodiment of the present application.
  • FIGS. 2A-2D are schematic diagrams of the preparation process of a bare chip provided by embodiments of the present application.
  • Figure 3A is a schematic structural diagram of a conductive pillar in a chip provided by an embodiment of the present application.
  • Figure 3B is a schematic structural diagram of another conductive pillar in a chip provided by an embodiment of the present application.
  • Figure 4 is a flow chart of a chip preparation method provided by an embodiment of the present application.
  • FIGS. 5A-9C are schematic diagrams of the preparation process of a chip provided by embodiments of the present application.
  • Figure 10A is a schematic structural diagram of another chip provided by an embodiment of the present application.
  • Figure 10B is a schematic diagram of the macro structure of a chip provided by an embodiment of the present application.
  • FIGS 11A-11D are schematic diagrams of the preparation process of another chip provided by the embodiment of the present application.
  • Figure 12A is a schematic structural diagram of another chip provided by an embodiment of the present application.
  • Figure 12B is a schematic structural diagram of a bare chip provided by an embodiment of the present application.
  • FIGS 12C-12F are schematic diagrams of the preparation process of another chip provided by the embodiment of the present application.
  • Figure 13 is a schematic structural diagram of another chip provided by an embodiment of the present application.
  • Coupled When describing some embodiments, the expression “coupled” and its derivatives may be used. For example, some embodiments may be described using the term “coupled” to indicate that two or more components are in direct physical or electrical contact. However, the term “coupled” may also refer to two or more components that are not in direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited by the content herein.
  • Exemplary embodiments are described in the embodiments of the present application with reference to cross-sectional views and/or plan views and/or equivalent circuit diagrams that are idealized exemplary drawings.
  • the thickness of layers and regions are exaggerated for clarity. Accordingly, variations from the shapes in the drawings due, for example, to manufacturing techniques and/or tolerances are contemplated.
  • example embodiments should not be construed as limited to the shapes of regions illustrated herein but are to include deviations in shapes that result from, for example, manufacturing. For example, an etched area shown as a rectangle will typically have curved features. Accordingly, the regions shown in the figures are schematic in nature and their shapes are not intended to illustrate the actual shapes of regions of the device and are not intended to limit the scope of the exemplary embodiments.
  • the electronic equipment is, for example, consumer electronic products, household electronic products, vehicle-mounted electronic products, financial terminal products, and communication electronic products.
  • consumer electronic products include mobile phones, tablets, laptops, e-readers, personal computers (PC), personal digital assistants (PDA), desktop monitors, Smart wearable products (such as smart watches, smart bracelets), virtual reality (VR) terminal devices, augmented reality (AR) terminal devices, drones, etc.
  • Home electronic products include smart door locks, TVs, remote controls, refrigerators, rechargeable small household appliances (such as soymilk machines, sweeping robots), etc.
  • Vehicle-mounted electronic products such as car navigation systems, vehicle-mounted high-density digital video discs (digital video discs, DVDs), etc.
  • Financial terminal products include automated teller machines (ATMs), self-service terminals, etc.
  • Communication electronic products include communication equipment such as servers, memories, and base stations.
  • the embodiments of the present application do not place special restrictions on the specific forms of the above-mentioned electronic devices.
  • the following embodiments take the electronic device as a mobile phone as an example.
  • the electronic device 1 mainly includes a display module 2 , a middle frame 3 , a case (also called a battery cover or a back case) 4 and a cover 5 .
  • the display module 2 has a light-emitting side from which the display screen can be seen and a backside opposite to the light-emitting side.
  • the backside of the display module 2 is close to the middle frame 3 , and the cover 5 is disposed on the light-emitting side of the display module 2 .
  • the above-mentioned display module 2 includes a display panel (DP).
  • the display module 2 is a liquid crystal display module.
  • the above-mentioned display screen is a liquid crystal display (LCD).
  • the display module 2 also includes a backlight module (back light unit, BLU) located on the back of the LCD screen (the side away from the LCD used to display the screen).
  • BLU backlight module
  • the backlight module can provide a light source to the LCD screen so that each sub-pixel in the LCD screen can emit light to achieve image display.
  • the display module 2 is an organic light-emitting diode display module.
  • the above-mentioned display screen is an organic light-emitting diode (OLED) display screen. Since each sub-pixel in the OLED display screen is provided with an electroluminescent layer, the OLED display screen can achieve self-luminescence after receiving the operating voltage. In this case, there is no need to provide the above-mentioned backlight module in the display module 2 with an OLED display screen.
  • OLED organic light-emitting diode
  • the cover plate 5 is located on the side of the display module 2 away from the middle frame 3.
  • the cover plate 5 can be, for example, cover glass (CG), and the cover glass can have a certain degree of toughness.
  • the middle frame 3 is located between the display module 2 and the housing 4.
  • the surface of the middle frame 3 away from the display module 2 is used to install internal components such as batteries, printed circuit boards (PCB), cameras, and antennas. .
  • internal components such as batteries, printed circuit boards (PCB), cameras, and antennas.
  • the above-mentioned electronic device 1 also includes a processor (center processing unit, CPU) chip, a radio frequency chip, a radio frequency power amplifier (PA) chip, a system on a chip (SOC), a power supply, which are provided on the PCB.
  • Management chips power management integrated circuits, PMIC), memory chips (such as high bandwidth memory (HBM)), audio processor chips, touch screen control chips, NAND flash (flash memory), image sensor chips, charging protection chips, etc.
  • HBM high bandwidth memory
  • PCB is used to carry the above-mentioned chip and complete signal interaction with the above-mentioned chip.
  • the reliability and other properties of the chip have a direct impact on the service life and performance of electronic equipment.
  • An embodiment of the present application provides a chip, which can be applied in the above-mentioned electronic device.
  • the chip provided in the embodiment of the present application may be an unpackaged bare chip.
  • the unpackaged bare chip may include an integrated circuit module (which may be called a two-dimensional (2D) bare chip).
  • the unpackaged bare chip may also include multiple integrated circuit modules.
  • Circuit modules (which may be called three-dimensional (3D) bare chips).
  • the chip provided in the embodiment of the present application may also be a packaged chip, and the packaged chip may include one bare chip or multiple bare chips.
  • An embodiment of the present application provides a chip, which is a 2D bare chip.
  • the chip preparation process usually includes front end of line (FEOL), midend of line (MEOL) and back end of line (BEOL).
  • FEOL front end of line
  • MEOL midend of line
  • BEOL back end of line
  • the front-end process is used to form integrated circuit modules including transistors, capacitors, inductors and other electronic components.
  • the electronic components in the embodiments of the present application may be components that are formed on the substrate through a previous process and are not independently packaged.
  • the integrated circuit module including transistors, capacitors, inductors and other electronic components can also be prepared in the subsequent process.
  • FIG. 2A takes two transistors in an integrated circuit module as an example for schematic illustration.
  • the transistors include a source S, a drain D and a gate G.
  • the middle process is used to form a transfer layer that leads the conductive patterns in multiple electronic components to the same plane.
  • the conductive pillars in the transfer layer are coupled to the source S, drain D and gate G of the electronic component.
  • a dielectric layer with holes is usually formed first. The holes in the dielectric layer are located above the conductive pattern, and then hole-filling technology is used to form conductive pillars.
  • the transfer layer formed in the middle process includes two parts.
  • the first part is: the bottom metal provided on the surface of the integrated circuit and the first middle dielectric layer wrapped around the periphery of the bottom metal.
  • the bottom metal is coupled to the source S, drain D, and gate G of the electronic component.
  • the second part is: a conductive pillar arranged on the surface of the bottom metal and a second middle dielectric layer wrapped around the periphery of the conductive pillar.
  • the conductive pillar is coupled to the bottom metal.
  • the bottom metal is in the shape of strips, for example, and the conductive pillars are in the shape of columns, for example.
  • the structure of Figure 2C can optimize the arrangement of the rewiring layer in the back-end process.
  • the structure formed in the middle process is the structure shown in FIG. 2C as an example for illustration.
  • the back-end process is used to form a redistribution layer located on the transfer layer.
  • the signal in the electronic component is transmitted to the redistribution layer through the transfer layer, and then led to the signal terminal on the surface of the redistribution layer.
  • the signal terminal is exposed to the surface of the chip.
  • the signal terminal serves as the pad of the chip.
  • an electroplating process is used to form copper (Cu) pillars as conductive pillars.
  • CVD chemical vapor deposition
  • the electroplating process usually requires a barrier layer (or adhesion layer) and an electroplating seed layer.
  • the barrier layer covers the sides and bottom of the conductive pillar.
  • Using chemical vapor deposition processes typically requires a nucleation layer that covers the sides and bottom of the conductive pillars.
  • the barrier layer, seed layer or nucleation layer will occupy the pore space of the holes in the second middle dielectric layer, resulting in a reduction in the pore diameter, an increase in the aspect ratio of the holes, and an increase in the process difficulty of the conductive pillars.
  • metal pillars are electroplated from the bottom and sides of the holes at the same time, and the electroplating rate is relatively fast at the corners, so it is easy to have the surface of the conductive pillars closed, but there are pores inside. situation (shown in Figure 3A).
  • metal pillars are deposited from the bottom and sides of the holes simultaneously, and the deposition rate at the corners is relatively fast. As a result, it is easy for the surface of the conductive pillars to be closed, but the inside of the conductive pillars remains. There are holes. However, there are pores inside the conductive pillars, which will cause the resistance of the conductive pillars to be high and cannot meet the performance required for chip shrinkage.
  • thinner titanium nitride (TiN) is used as the barrier layer, and hole-filled cobalt (Co) is used as the conductive pillar.
  • TiN titanium nitride
  • Co hole-filled cobalt
  • a selectively grown tungsten (W) chemical vapor deposition process is used to form the conductive pillars.
  • the selective growth process deposits metal from the bottom up on the surface of the bottom metal exposed at the bottom of the hole, and does not grow on the hole wall of the hole in the second middle dielectric layer, without the need for a barrier layer.
  • no barrier layer occupies the pore space, and conductive pillars are directly formed in the pores, which can be applied to high aspect ratio chip structures.
  • tungsten metal grows from bottom to top, there will be no pores inside the conductive pillar formed, which can reduce the resistance of the conductive pillar.
  • embodiments of the present application also provide a conductive pillar and a method of forming the conductive pillar.
  • the conductive pillar formed by the method provided by the embodiment of the present application is directly in contact with the second middle dielectric layer without leaving any gaps.
  • a chip preparation method including:
  • S10 Provide a dielectric layer and a first conductive pattern located on the side of the first middle dielectric layer.
  • step S10 includes:
  • Electronic components 20 are formed on the substrate 100 to form an integrated circuit module of the chip.
  • the material of the substrate 100 is an insulating material.
  • the material of the substrate 100 is a conductive material.
  • the electronic component 20 is a basic element in an electronic circuit and has at least one lead contact.
  • the lead contact is used for coupling with wiring interconnections to complete signal transmission.
  • the electronic component 20 may be a resistor, a capacitor, an inductor, a transistor, a diode, an operational amplifier, a resistor, a logic gate, etc.
  • the electronic component 20 is a transistor, and the lead contacts included in the electronic component 20 are the source S, the drain D, and the gate G.
  • the chip may include one electronic component 20 or multiple electronic components 20 .
  • the chip preparation method provided in the embodiment of the present application only takes one electronic component 20 in the chip as an example to schematically illustrate the structure of each part of the chip. .
  • the multiple electronic components 20 may be the same type of electronic components or may be different types of electronic components.
  • the embodiments of the present application do not limit the number, type, and arrangement of the electronic components 20 in the chip, and they can be set appropriately as needed.
  • Each electronic component 20 includes at least one first conductive pattern 21 .
  • the electronic component 20 includes a complementary metal oxide semiconductor device (CMOS).
  • CMOS complementary metal oxide semiconductor device
  • the source S, drain D, and gate G of the CMOS are all lead contacts of the electronic component 20 .
  • FIG. 5A also illustrates the gate insulating layer located below the gate G and the spacers located on the side of the gate G.
  • the structure of the electronic component 20 illustrated in FIG. 5A is only an illustration and is not limited in any way.
  • the electronic component 20 is a high electron mobility transistor (HEMT), a heterojunction bipolar transistor (HBT), a bipolar junction transistor (BJT), etc. .
  • HEMT high electron mobility transistor
  • HBT heterojunction bipolar transistor
  • BJT bipolar junction transistor
  • the shape of the bottom metal in the top view is not limited, and may be strip-shaped, for example.
  • the bottom metal can serve as the first conductive pattern 21 in this example.
  • other metal patterns on the bottom metal can also be used as the first conductive pattern 21 in this example. This is just an illustration.
  • the chip may include one first conductive pattern 21 or multiple first conductive patterns 21 .
  • the dielectric layer 10 has a hole 11. The hole 11 is located above the first conductive pattern 21 and in contact with the first conductive pattern 21.
  • the embodiment of the present application does not limit the shape and size of the hole 11 .
  • the hole 11 may expose a partial area of the first conductive pattern 21 away from the top surface of the substrate 100 , or the hole 11 may expose the entire area of the first conductive pattern 21 away from the top surface of the substrate 100 .
  • the projection of the hole 11 on the substrate 100 can be located within the projection of the first conductive pattern 21 on the substrate 100 , and the projection of the hole 11 on the substrate 100 can also be located within the projection of the first conductive pattern 21 on the substrate 100 The projections on the .
  • the projection of the hole 11 on the substrate 100 can also cover the projection of the first conductive pattern 21 on the substrate 100 , as long as it is ensured that the first conductive pillar subsequently formed in the hole 11 will not cause the adjacent first conductive pattern 21 Just short circuit.
  • the hole 11 is located above the first conductive pattern 21.
  • the area of the hole 11 can be smaller than the area of the first conductive pattern 21.
  • the area of the hole 11 can also be equal to the area of the first conductive pattern 21.
  • the area of the hole 11 can also be is larger than the area of the first conductive pattern 21 .
  • the area of the hole 11 is smaller than the area of the top surface of the first conductive pattern 21 as an example.
  • the embodiment of the present application does not limit the number of holes 11 , as long as the number of holes 11 corresponds to the number of first conductive patterns 21 .
  • one first conductive pattern 21 can be provided corresponding to one hole 11 , that is to say, only one hole 11 can be provided above one first conductive pattern 21 .
  • One first conductive pattern 21 can also be provided corresponding to a plurality of holes 11 , that is to say, a plurality of holes 11 can be provided above one first conductive pattern 21 .
  • a plurality of first conductive patterns 21 may also be provided corresponding to the same hole 11 , that is to say, the same hole may be provided above a plurality of first conductive patterns 21 (for example, the plurality of first conductive patterns 21 transmit the same signal, for example). 11.
  • the dielectric layer 10 includes a plurality of holes 11 , and each hole 11 is arranged corresponding to a first conductive pattern 21 .
  • CVD chemical vapor deposition
  • physical vapor deposition or other deposition methods can be used to form the middle dielectric film, and then photolithography and etching are used to form holes 11 on the middle dielectric film to prepare the dielectric layer 10.
  • the material of the dielectric layer 10 may include, for example, silicon oxide (for example, silicon dioxide SiO 2 ), silicon nitride (for example, silicon nitride SiN 4 ), silicon doped oxide, and silicon fluorinated oxide. , carbon-doped oxides of silicon, or various low dielectric constant (k) dielectric materials known in the related art and combinations thereof.
  • the dielectric layer 10 is a single film layer. In this way, the structure is simple and the process steps are few.
  • the dielectric layer 10 includes multiple dielectric film layers.
  • the materials of the multi-layer dielectric film layers may be the same, and the materials of the multi-layer dielectric film layers may also be different.
  • the dielectric layer 10 includes a first dielectric layer 101 and a second dielectric layer 102 .
  • the first dielectric layer 101 is disposed close to the first conductive pattern 21 .
  • the dielectric constant of the first dielectric layer 101 is greater than the second dielectric layer 102 .
  • the dielectric constant of the dielectric layer 102 is greater than the first dielectric layer 101 .
  • the first dielectric layer 101 with a larger dielectric constant is provided at a position closer to the conductive pillar to be formed and the first conductive pattern 21, which can improve the insulation effect between the first conductive pattern 21 and the conductive pillar to be formed.
  • a selective growth (selectivedeposition) process is used to grow the metal pillar body 30 in the hole 11 starting from the surface of the first conductive pattern 21 from bottom to top.
  • the selective growth process refers to epitaxial growth performed in a defined area on the substrate. As used in this application, epitaxial growth starts on the surface of the first conductive pattern 21 and does not start on the surface of the dielectric layer 10 . Since this application uses a selective epitaxial growth process to directly epitaxially grow the metal pillar body 30 on the surface of the metal structure of the first conductive pattern 21, therefore, the selective growth process is used to form the metal pillar body 30 without the need for a barrier layer or a nucleation layer. etc. film layer.
  • this application adopts the selective growth process to finally form the first conductive pillar.
  • the bottom surface of the first conductive pillar directly contacts the first conductive pattern 21, and the side surface of the first conductive pillar directly contacts the dielectric layer 10.
  • the first conductive pillar is Solid structure, there are no pores inside the first conductive pillar.
  • step S20 includes:
  • the chemical residue may be, for example, chemical substances remaining in the process of forming the hole 11 on the dielectric layer 10
  • the dangling bond may be, for example, a chemical bond that has no electron energy to pair.
  • the surface of the holes 11 in the dielectric layer 10 may be treated, for example, by chemical treatment such as heat treatment, plasma treatment, reducing gas treatment, oxidizing gas treatment, or the like.
  • the metal pillar body 30 formed by the selective growth process is a solid pillar, and no pores are formed inside the metal pillar body 30 like the electroplating or chemical vapor deposition process.
  • the metal pillar body 30 is formed using a selective growth process, eliminating the need for barrier layers, nucleation layers and other layers.
  • the height of the metal pillar body 30 can be adjusted according to the depth of the hole 11 and the grinding thickness of the subsequent chemical mechanical polishing process. As shown in FIG. 6B , when multiple metal pillar bodies 30 are formed at the same time, the heights of the multiple metal pillar bodies 30 may be the same or different.
  • irregular gaps may randomly appear between the metal pillar body 30 and the dielectric layer 10 .
  • the gap may be large or small, wide or narrow, high or low, the gap may circle around the metal pillar body 30, the gap may exist between the side surface of the metal pillar body 30 and the dielectric layer 10, and the same metal pillar body 30 may The gaps between the dielectric layers 10 are continuous, or the gaps between the same metal pillar body 30 and the dielectric layer 10 are discontinuous, etc. There are many possibilities.
  • FIG. 6A and FIG. 6B are only illustrative.
  • the material of the metal pillar body 30 is not limited.
  • the material of the metal pillar body 30 is a highly active material that is easily oxidized.
  • it may include copper (Cu), aluminum (Al), titanium (Ti), zirconium (Zr), hafnium (Hf), vanadium (V), ruthenium (Ru), cobalt (Co), nickel (Ni), palladium ( Pd), platinum (Pt), tungsten (W), silver (Ag), gold (Au), chromium (CN) and other materials.
  • the metal pillar body 30 is processed to cause a chemical reaction of the metal on the surface of the metal pillar body 30 .
  • the metal on the surface of the metal pillar body 30 will increase in volume after a chemical reaction, causing the metal pillar body 30 to expand until it contacts the dielectric layer 10 , thereby filling the above-mentioned gap.
  • step S30 includes: performing an oxidation treatment on the metal pillar body 30 so that the side surfaces of the metal pillar body 30 that are not in contact with the dielectric layer 10 are oxidized and then expanded to contact the dielectric layer 10 .
  • the outer surface of the metal pillar body 30 that is not in contact with the dielectric layer 10 includes the top surface of the metal pillar body 30 away from the first conductive pattern 21 and the portion of the side surface of the metal pillar body 30 that is not in contact with the dielectric layer 10 . Then, as shown in FIG. 7B , in the process of oxidizing the metal pillar body 30 , only the top surface and at least part of the side surfaces of the metal pillar body 30 are actually oxidized. The side surfaces of the metal pillar body 30 that are in contact with the dielectric layer 10 Will not be oxidized.
  • the material of the metal pillar body 30 includes W. After the side surface of the metal pillar body 30 is oxidized, the metal oxide formed is WOx (where 0 ⁇ x ⁇ 4).
  • oxygen-containing gas is used to oxidize the metal pillar body 30 .
  • the oxygen-containing gas may be, for example, oxygen (O 2 ), ozone (O 3 ), or a mixed gas thereof.
  • oxygen O 2
  • O 3 ozone
  • gaseous oxidation may be performed using plasma treatment or gaseous oxidation may be performed without plasma treatment.
  • an oxidizing agent solution is used to oxidize the metal pillar body 30 .
  • the oxidizing agent solution may be, for example, a hydrogen peroxide (H 2 O 2 ) solution.
  • Liquid oxidation treatment can be performed by soaking or rinsing.
  • the metal pillar body 30 is oxidized by placing the metal pillar body 30 in the atmospheric environment for a long time.
  • the oxide layer formed is smooth toward the inner surface of the metal pillar body 30 (the flatness here is not limited to absolutely flat, and may also have a certain fluctuation range) .
  • the oxide layer formed faces the surface inside the metal pillar body 30.
  • the oxide layer formed The surface of the layer towards the inside of the metal pillar body 30 is flat.
  • the oxidation treatment time of the metal pillar body 30 can be adjusted according to the selected oxidation process, oxidation rate and other factors. By controlling the oxidation treatment time, the oxidation thickness of the top surface of the metal pillar body 30 can be controlled. The thickness of the oxidized top surface of the metal pillar body 30 should be set in conjunction with the subsequent process of removing the oxidized portion of the top surface of the metal pillar body 30 to ensure that the metal pillar body 30 can be removed when the oxidized portion of the top surface of the metal pillar body 30 is subsequently removed. The oxidized part of the surface is completely removed.
  • the thickness of the metal oxide formed after the top surface of the metal pillar body 30 is oxidized is less than 10 nm.
  • the thickness of the metal oxide formed after the top surface of the metal pillar body 30 is oxidized is 9 nm, 8 nm, 7 nm, 6 nm, 5 nm, 4 nm, 3 nm, 2 nm or 1 nm.
  • the metal oxide formed by oxidation on the top surface of the metal pillar body 30 can be removed using the existing chemical mechanical grinding process without changing the process and equipment.
  • the thickness of the metallization formed is less than 10 nm, so as to ensure that the metallization on the top surface of the metal pillar body 30 can be completely removed in the subsequent removal process without affecting the to-be-formed The conductive properties of the first conductive pillar.
  • the thickness of the metallization formed after the top surface of the metal pillar body 30 is chemically treated is 9 nm, 8 nm, 7 nm, 6 nm, 5 nm, 4 nm, 3 nm, 2 nm or 1 nm.
  • the metal pillar body 30 will no longer be chemically treated after the side surface of the metal pillar body 30 expands to contact the dielectric layer 10 .
  • the width of the metal oxide layer formed after the side surfaces of the metal pillar body 30 are oxidized is 0.5 nm to 5 nm.
  • the thickness of the metal oxide layer formed after the side surfaces of the metal pillar body 30 are oxidized is measurable, and the thickness of the metal oxide layer is at least 0.5 nm.
  • the thickness of the metal oxide layer formed after the side surfaces of the metal pillar body 30 are oxidized is controlled to less than 5 nm, which can not only fill the gap between the metal pillar body 30 and the dielectric layer 10 , but also reduce the thickness of the metal oxide layer on the side surfaces of the metal pillar body 30 .
  • the effect of the metal oxide layer on the resistance of the metal pillar body 30 is very small and almost negligible. Thus, the problem that the presence of the metal oxide layer causes the resistance of the metal pillar body 30 to increase is optimized.
  • the width of the metal compound layer formed (the size in the direction parallel to the dielectric layer 10 ) is 0.5 nm to 5 nm to ensure that the metal pillar body 30 and the dielectric layer 10 are filled.
  • the influence of the metal oxide layer on the resistance of the first conductive pillar to be formed is reduced as much as possible.
  • step S30 includes: performing a nitriding treatment on the metal pillar body 30 to expand the side of the metal pillar body 30 that is not in contact with the dielectric layer 10 to contact the dielectric layer 10 .
  • the outer surface of the metal pillar body 30 that is not in contact with the dielectric layer 10 includes the top surface of the metal pillar body 30 away from the first conductive pattern 21 and the portion of the side surface of the metal pillar body 30 that is not in contact with the dielectric layer 10 .
  • FIG. 7B during the nitriding process of the metal pillar body 30 , only the top surface and at least part of the side surfaces of the metal pillar body 30 are actually nitrided, and the metal pillar body 30 is in contact with the dielectric layer 10 The sides will not be nitrided.
  • the material of the metal pillar body 30 includes W. After the side surface of the metal pillar body 30 is nitrided, the metal nitride formed is WNx (where, 0 ⁇ x ⁇ 4).
  • nitrogen-containing gas is used to nitride the metal pillar body 30 .
  • the nitrogen-containing gas may be, for example, nitrogen (N 2 ), ammonia (NH 3 ) or a mixed gas thereof.
  • gaseous nitridation may be performed using plasma treatment or gaseous nitriding may be performed without plasma treatment.
  • the nitride layer formed is smooth toward the inner surface of the metal pillar body 30 (the flatness here is not limited to absolutely flat, and may also have certain fluctuations. amplitude).
  • the nitriding time of the metal pillar body 30 can be adjusted according to the selected nitriding process, nitriding rate and other factors. By controlling the nitriding time, the nitrided thickness of the top surface of the metal pillar body 30 can be controlled. The thickness of the nitrided top surface of the metal pillar body 30 should be set in conjunction with the subsequent process of removing the nitrided portion of the top surface of the metal pillar body 30 to ensure that the metal pillar can be removed when the nitrided portion of the top surface of the metal pillar body 30 is subsequently removed. The nitrided portion of the top surface of the body 30 is completely removed.
  • the thickness of the metal nitride formed after the top surface of the metal pillar body 30 is nitrided is less than 10 nm.
  • the metal nitride formed by nitridation on the top surface of the metal pillar body 30 can be removed using the existing chemical mechanical polishing process without changing the process and equipment.
  • the width of the metal nitride layer formed after the side surfaces of the metal pillar body 30 are nitrided (dimension in the direction parallel to the dielectric layer 10 ) is 0.5 nm to 5 nm.
  • step S30 includes: performing an oxidation treatment and a nitridation treatment on the metal pillar body 30 so that the side surfaces of the metal pillar body 30 that are not in contact with the dielectric layer 10 are oxidized and nitrided, and then expanded to be in contact with the dielectric layer 10 .
  • the dielectric layer 10 is in contact.
  • the outer surface of the metal pillar body 30 that is not in contact with the dielectric layer 10 includes the top surface of the metal pillar body 30 away from the first conductive pattern 21 and the portion of the side surface of the metal pillar body 30 that is not in contact with the dielectric layer 10 .
  • FIG. 7B in the process of oxidizing and nitriding the metal pillar body 30 , only the top surface and at least part of the side surfaces of the metal pillar body 30 are actually oxidized and nitrided.
  • the metal pillar body 30 The side surface in contact with the dielectric layer 10 will not be oxidized or nitrided.
  • the material of the metal pillar body 30 includes W.
  • the metal oxynitride formed is WOxNy (where, 0 ⁇ x ⁇ 4, 0 ⁇ y ⁇ 4).
  • gases containing oxygen and nitrogen are used to oxidize and nitride the metal pillar body 30 .
  • the gas containing oxygen and nitrogen may be, for example, nitrous oxide (N 2 O), a mixed gas of nitrogen and oxygen, etc.
  • plasma treatment may be selected for gaseous oxidation and nitridation, or no plasma treatment may be selected for gaseous oxidation and nitridation. Oxidation and nitridation.
  • the time of oxidation treatment and nitridation treatment of the metal pillar body 30 can be adjusted according to the selected oxidation and nitridation process, oxidation and nitridation rate and other factors.
  • the metal pillar can be controlled.
  • the thickness of the top surface of the body 30 being oxidized and nitrided.
  • the thickness of the oxidized and nitrided top surface of the metal pillar body 30 should be set in conjunction with the subsequent process of removing the oxidized and nitrided portion of the top surface of the metal pillar body 30 to ensure that the subsequent removal of the top surface of the metal pillar body 30 is oxidized and nitrided.
  • the oxidized and nitrided portion of the top surface of the metal pillar body 30 can be completely removed.
  • the thickness of the metal oxynitride formed after the top surface of the metal pillar body 30 is oxidized and nitrided is less than 10 nm.
  • the metal oxynitride formed by oxidation and nitridation on the top surface of the metal pillar body 30 can be removed using the existing chemical mechanical grinding process without changing the process and equipment.
  • the width of the metal oxynitride layer formed after the side surfaces of the metal pillar body 30 are oxidized and nitrided (the size in the direction parallel to the dielectric layer 10 ) is 0.5 nm to 5 nm.
  • the metal pillar body 30 when chemically treating the metal pillar body 30 , the metal pillar body 30 can be oxidized, nitrided, or nitrided.
  • the metal pillar body 30 can also be subjected to other chemical treatments that can expand the metal pillar body 30 , and the embodiments of the present application are not limited to this.
  • the first conductive pillar 31 includes a metal pillar 311 and a metal compound layer 312 , and the metal compound layer 312 is located on the side of the metal pillar 311 .
  • the part of the metal pillar body 30 that has not been chemically treated is the metal pillar 311
  • the part of the side of the metal pillar body 30 that has been chemically treated is the metal compound layer 312 .
  • the metal included in the metal pillar 311 (such as the W pillar) formed through this process and the metal included in the metal compound layer 312 (such as the WOx layer, WNx layer or WOxNy layer) are the same, and they are both used when forming the metal pillar body 30.
  • the metal used e.g. W).
  • step S30 if the metal pillar body 30 is oxidized, the metal compound layer 312 is a metal oxide layer. In step S30, if the metal pillar body 30 is nitrided, the metal compound layer 312 is a metal nitride layer. In step S30, if the metal pillar body 30 is subjected to oxidation treatment and nitridation treatment, then the metal compound layer 312 is a metal oxynitride layer.
  • a chemical mechanical polishing process can be used to remove the chemically treated portion of the top surface of the metal pillar body 30 . Then, the thickness of the metal compound formed after the chemical treatment on the top surface of the metal pillar body 30 should be smaller than the thickness removed by the chemical mechanical polishing process.
  • other processes can also be used to remove the metal compound formed after the top surface of the metal pillar body 30 is chemically treated, and the embodiment of the present application is not limited to this.
  • a top metal layer is covered on the side of the dielectric layer 10 away from the first conductive pattern 21 , and the top metal layer covers the dielectric layer 10 and the conductive pillar body 30 .
  • the height ratio between the plurality of conductive pillar bodies 30 and between the conductive pillar bodies 30 and the dielectric layer 10 can be reduced, thereby adjusting the grinding speed and height, so that the metal pillar bodies 30 The chemically treated portion of the top surface is completely removed without excessive grinding of the conductive pillar body 30 .
  • the metal pillar body 30 usually needs to be chemically and mechanically polished to make the surfaces of all the metal pillar bodies 30 flush and flush with the surface of the dielectric layer 10 . Therefore, the chemical mechanical polishing process is used to remove the chemically treated portion of the top surface of the metal pillar body 30 without adding a new process. The process cost is low and the production efficiency is high.
  • the side surfaces of the formed first metal pillars 31 are in contact with the dielectric layer 10 , and there is no gap between the first metal pillars 31 and the dielectric layer 10 . It is explained here that the first metal pillar 31 is in contact with the dielectric layer 10, which should be understood to mean that all the side surfaces of the first metal pillar 31 are in contact with (or adhere to) the dielectric layer 10. Or it can be understood that all the side surfaces of the first metal pillar 31 are in contact with the hole walls of the corresponding holes 11 in the dielectric layer 10 .
  • the gap between some metal pillar bodies 30 and the dielectric layer 10 is particularly large.
  • the first metal pillar formed there may still be a gap between 31 and the dielectric layer 10, which also falls within the protection scope of the embodiments of the present application.
  • the possibility of the above situation occurring is relatively small and will almost never occur.
  • the side surfaces of the metal compound layer 312 and the metal pillar 311 that are not covered by the metal compound layer 312 are in contact with the dielectric layer 10 .
  • the contact between the first conductive pillar 31 and the dielectric layer 10 also different.
  • the metal pillar body 30 is grown on the surface of the first conductive pattern 21. Then, the formed first metal pillar 31 is in contact with the first conductive pattern 21.
  • part of the side surface of the metal pillar 311 on the left side of the viewing angle in FIG. 8B is covered by the metal compound layer 312 .
  • the side surface of the first conductive pillar 31 is composed of two parts, one part is the side surface of the metal pillar 311 that is not covered by the metal compound layer 312 , and the other part is the side surface of the metal compound layer 312 . Then, the first conductive pillar 31 is in contact with the dielectric layer 10 . It can be understood that the first conductive pillar 31 is in contact with the dielectric layer 10 through the side of the metal pillar 311 that is not covered by the metal compound layer 312 and the side of the metal compound layer 312 .
  • the area of the side of the metal pillar 311 that is not covered by the metal compound layer 312 is in direct contact with the dielectric layer 10
  • the area of the side of the metal pillar 311 that is covered by the metal compound layer 312 is in contact with the dielectric layer 10 through the metal compound layer 312 .
  • the entire area of the side surface of the first conductive pillar 31 is in contact with the dielectric layer 10 .
  • FIG. 8B all sides of the metal pillar 311 on the right side of the viewing angle are covered by the metal compound layer 312 .
  • the side of the metal pillar 31 that is not covered by the metal compound layer 312 does not exist, and the side of the metal compound layer 312 is the side of the first conductive pillar 31 .
  • the first conductive pillar 31 is in contact with the dielectric layer 10 , which can be understood as the first conductive pillar 31 is in contact with the dielectric layer 10 through the metal compound layer 312 , so that all areas of the side surfaces of the first conductive pillar 31 are in contact with the dielectric layer 10 .
  • the thickness of the metal compound layer 312 included in the first conductive pillar 31 may be the same at each position (for example, the metal compound layer 312 included in the first conductive pillar 31 on the left side of the viewing angle in FIG. 8B ).
  • the first conductive pillar 31 The thickness of the included metal compound layer 312 at each position may also be different (for example, the metal compound layer 312 included in the first conductive pillar 31 on the right side of the viewing angle in FIG. 8B ), which is not limited in the embodiment of the present application.
  • the material at each location of the metal compound layer 312 included in the first conductive pillar 31 may be the same, and the materials at each location of the metal compound layer 312 included in the first conductive pillar 31 may also be different.
  • the oxygen content and/or nitrogen content of the materials at each position of the metal compound layer 312 included in the first conductive pillar 31 can be the same, and the materials at each position of the metal oxide layer 312 included in the first conductive pillar 31 The oxygen content and/or nitrogen content may also be different.
  • the material of the metal compound layer 312 is WOx (where 0 ⁇ x ⁇ 4), and the value of x in WOx at each position of the metal compound layer 312 may be different.
  • the material of the metal compound layer 312 is WNx (where 0 ⁇ x ⁇ 4), and the value of x in WNx at each position of the metal compound layer 312 may be different.
  • the material of the metal compound layer 312 is WOxNy (where 0 ⁇ x ⁇ 4, 0 ⁇ y ⁇ 4), and the values of x and y in WOxNy at each position of the metal compound layer 312 may be different.
  • the dielectric layer 10 has a plurality of holes 11 , and after preparing the first conductive pillars 31 in the holes 11 through the above steps, the chip includes a plurality of the first conductive pillars 31 .
  • the plurality of metal compound layers 312 included in the plurality of first conductive pillars 31 have completely different widths.
  • the widths of the plurality of metal compound layers 312 included in the plurality of first conductive pillars 31 are not exactly the same. It can also be understood that among the plurality of metal compound layers 312 included in the plurality of first conductive pillars 31 , some of the metal compound layers 312 have the same thickness, and some of the metal compound layers 312 have different thicknesses.
  • the widths of the plurality of metal compound layers 312 included in the plurality of first conductive pillars 31 are exactly the same.
  • metal compound layer 312 When the metal pillar body 30 is formed due to the selective growth process, the width of the gap between the metal pillar body 30 and the dielectric layer 10 is random without any rules. Therefore, there is no limit to the width of the finally formed metal compound layer 312. There may be metal compound layers 312 of various thicknesses, various sizes, various shapes, and various positions. This is not limited in the embodiments of the present application. .
  • the materials of the plurality of metal compound layers 312 included in the plurality of first conductive pillars 31 are completely different.
  • the material of the metal compound layer 312 is WOx, and the value of x in WOx at each position of the metal compound layer 312 is completely different.
  • the materials of the plurality of metal compound layers 312 included in the plurality of first conductive pillars 31 are not exactly the same.
  • the material of the metal compound layer 312 is WOx, and the values of x in WOx at various positions of the metal compound layer 312 are not exactly the same.
  • the materials of the plurality of metal compound layers 312 included in the plurality of first conductive pillars 31 are exactly the same.
  • the material of the metal compound layer 312 is WOx, and the value of x in WOx is the same at each position of the metal compound layer 312 .
  • the dielectric layer 10 has a plurality of holes, and a selective growth process is used to form a plurality of metal pillar bodies 30 in step S20 . While the first conductive pillars 31 are formed, the second conductive pillars 32 are also formed.
  • the main difference between the second conductive pillar 32 and the first conductive pillar 31 is that the second conductive pillar 32 includes a metal pillar and does not include a metal compound layer.
  • the metal pillar is arranged in the hole 11 of the dielectric layer 10 , or it can be understood that the dielectric layer 10 is wrapped around the periphery of the metal pillar.
  • the side surfaces of the metal pillars are in contact with the hole walls of the holes 11 in the dielectric layer 10 , and the bottom surfaces of the second conductive pillars 32 are in contact with the first conductive patterns 21 .
  • one first conductive pattern 21 can be coupled only with one or more first conductive pillars 31 , and one first conductive pattern 21 can also be coupled with only one or more second conductive pillars 32 . 21 may also be coupled to one (or more) first conductive pillars 31 and one (or more) second conductive pillars 32 .
  • step S30 all outer surfaces of the metal pillar body 30 that are not in contact with the dielectric layer 10 will be chemically treated.
  • step S40 all metal compounds on the top surface of the metal pillar body 30 will be removed.
  • the second conductive pillar 32 is formed.
  • the first conductive pillar 31 is formed. Then, the metal included in the first conductive pillar 31 and the second conductive pillar 32 are the same as the metal included in the metal pillar body 30 .
  • first conductive pillars 31 and the second conductive pillars 32 are also randomly arranged without any arrangement rule. Even in chips of the same batch, the distribution of the first conductive pillars 31 and the second conductive pillars 32 may be different.
  • a second conductive pattern 41 is formed on the side of the dielectric layer 10 away from the first conductive pattern 21, and the second conductive pattern 41 is coupled to the first conductive pillar 31.
  • the embodiment of the present application does not limit the shape, function, and material of the second conductive pattern 41, and it can be set appropriately according to the application scenario.
  • the second conductive pattern 41 is a conductive pattern included in the first redistribution layer 40 . That is to say, the second conductive pattern 41 is a conductive pattern in the redistribution layer prepared in a later process.
  • the second conductive pattern 41 is a conductive pattern in a wiring layer of the first rewiring layer 40 that is closest to the dielectric layer 10 .
  • the second conductive pattern 41 may be in the shape of a column, the second conductive pattern 41 may also be in the shape of a line, and the second conductive pattern 41 may also be in other shapes, which are not limited in the embodiments of the present application.
  • the chip includes a plurality of second conductive patterns 41 , some of the second conductive patterns 41 in the plurality of second conductive patterns 41 are coupled to the first conductive pillars 31 , and the plurality of second conductive patterns 41 are coupled to the first conductive pillars 31 . Part of the second conductive pattern 41 in the conductive pattern 41 is coupled to the second conductive pillar 32 .
  • one second conductive pattern 41 can be coupled only with one or more first conductive pillars 31 , and one second conductive pattern 41 can also be coupled with only one or more second conductive pillars 32 . 41 may also be coupled to one (or more) first conductive pillars 31 and one (or more) second conductive pillars 32 .
  • first conductive pattern 21 and the second conductive pattern 41 are respectively coupled to both ends of the first conductive pillar 31
  • first conductive pattern 21 and the second conductive pattern 41 are coupled to both ends of the second conductive body 32 .
  • the metal pillar body 30 is formed through a selective growth process
  • chemical treatment methods such as oxidation treatment and/or nitridation treatment are used to remove irregularities between the metal pillar body 30 and the dielectric layer 10 Self-healing of gap defects.
  • the volume of the metal pillar body 30 will expand to produce a metal compound, and the metal compound will fill the gap between the metal pillar body 30 and the dielectric layer 10
  • Defects can effectively prevent the first conductive pattern 21 from being damaged by solutions such as polishing liquid, cleaning liquid or etching liquid.
  • the chip provided by the embodiment of the present application includes a first conductive pillar 31 , a dielectric layer 10 , a first conductive pattern 21 and a second conductive pattern 41 .
  • first conductive pillar 31 There may be one first conductive pillar 31 or multiple first conductive pillars.
  • a chip including multiple first conductive pillars is used as an example for illustration.
  • the dielectric layer 10 wraps around the periphery of each first conductive pillar 31 and contacts the side of each first conductive pillar 31 .
  • each first conductive pillar 31 is disposed in the dielectric layer 10 and also penetrates the dielectric layer 10 along the thickness direction of the dielectric layer 10 .
  • the embodiment of the present application does not limit the shape of the first conductive pillar 31.
  • the shape of the first conductive pillar 31 may be a cylindrical shape, a rectangular columnar shape, or a rectangular shape, etc.
  • the first conductive pattern 21 and the second conductive pattern 41 are located on opposite sides of the first conductive pillar 31 , or it can be understood that the first conductive pattern 21 and the second conductive pattern 41 are located on opposite sides of the dielectric layer 10 .
  • the first conductive pattern 21 and the second conductive pattern 41 are coupled correspondingly to both ends of the first conductive pillar 31 .
  • the embodiment of the present application does not limit the shapes of the first conductive pattern 21 and the second conductive pattern 41, as long as the first conductive pattern 21 and the second conductive pattern 41 can conduct electricity.
  • the first conductive pattern 21 is contact-coupled with the first conductive pillar 31 .
  • the second conductive pattern 41 and the first conductive pillar 31 may be in contact coupling, and the second conductive pattern 41 and the first conductive pillar 31 may also be in indirect coupling.
  • the specific structures of the first conductive pattern 21 and the second conductive pattern 41 in the chip please refer to the relevant description of the first conductive pattern 21 and the second conductive pattern 41 when describing the chip preparation method.
  • the first conductive pillar 31 includes a metal pillar 311 and a metal compound layer 312 .
  • the metal compound layer 312 is located between the metal pillar 311 and the dielectric layer 10 .
  • the metal compound layer 312 covers at least part of the side surfaces of the metal pillar 311 .
  • the first conductive pillar 31 contacts the dielectric layer 10 through the metal compound layer 312 and the side of the metal pillar 311 that is not covered by the metal compound layer 312 .
  • part of the side surface of the metal pillar 311 on the left side of the viewing angle in FIG. 9B is covered by the metal compound layer 312 .
  • the first conductive pillar 31 is in contact with the dielectric layer 10. It can be understood that the first conductive pillar 31 is in contact with the dielectric layer 10 through the side of the metal pillar 311 that is not covered by the metal compound layer 312 and the side of the metal compound layer 312. .
  • FIG. 9B In other embodiments, please continue to refer to FIG. 9B .
  • all sides of the metal pillar 311 on the right side of the viewing angle are covered by the metal compound layer 312 .
  • the metal pillar 311 does not have a side surface that is not covered by the metal compound layer 312 .
  • the first conductive pillar 31 is in contact with the dielectric layer 10 , which can be understood as the first conductive pillar 31 is in contact with the dielectric layer 10 through the metal compound layer 312 , so that all areas of the side surfaces of the first conductive pillar 31 are in contact with the dielectric layer 10 .
  • part of the side surfaces of the metal pillar 311 is covered by the metal compound layer 312. It is not limited to one or more of the four sides of the metal pillar 311 being covered by the metal compound layer 312. cover. As shown in FIG. 9C , part of a certain side surface of the metal pillar 311 may be covered by the metal compound layer 312 , and part of the part may not be covered by the metal compound layer 312 . Of course, other situations are possible, and the embodiments of this application are not exhaustive.
  • metal pillars 311 are formed using a selective growth process. In this way, the metal pillars 311 are grown from the bottom up on the surface of the first conductive pattern 21 , which can avoid the existence of pores inside the metal pillars 311 and eliminate the need for film layers such as barrier layers.
  • the metal compound layer 312 is obtained by chemically treating the side surface of the metal pillar 311 . Then, the metal included in the metal pillar 311 and the metal included in the metal compound layer 312 are the same.
  • the material properties of the metal pillar 311 and the metal compound layer 312 can be made similar, thereby improving the adhesion between the metal pillar 311 and the metal compound layer 312. Defects caused by separation of the metal compound layer 312 and the metal pillar 311 are reduced.
  • the metal pillar 311 includes a different metal than the metal compound layer 312 includes.
  • the metal compound layer 312 includes metal oxide material.
  • the metal compound layer 312 is obtained by oxidizing the side surface of the metal pillar 311 .
  • the metal compound layer 312 includes a metal nitride material.
  • the metal compound layer 312 is obtained by nitriding the side surface of the metal pillar 311 .
  • the metal compound layer 312 includes metal oxide materials and metal nitride materials.
  • the metal compound layer 312 is obtained by nitriding and nitriding the side surface of the metal pillar 311 .
  • the metal compound layer 312 includes a metal oxynitride material.
  • the metal compound layer 312 is obtained by subjecting the side surfaces of the metal pillars 311 to oxidation treatment and nitridation treatment.
  • the metal compound layer 312 includes metal oxide materials and metal oxynitride materials.
  • the metal compound layer 312 is obtained by subjecting the side surfaces of the metal pillars 311 to oxidation treatment and nitridation treatment.
  • the metal compound layer 312 includes metal nitride materials and metal oxynitride materials.
  • the metal compound layer 312 is obtained by subjecting the side surfaces of the metal pillars 311 to oxidation treatment and nitridation treatment.
  • the metal compound layer 312 includes metal oxide materials, metal oxynitride materials, and metal oxynitride materials.
  • the metal compound layer 312 is obtained by subjecting the side surfaces of the metal pillars 311 to oxidation treatment and nitridation treatment.
  • the metal compound layer 312 is formed by a separate process.
  • the embodiment of the present application does not limit the formation method of the metal compound layer 312.
  • the method of forming the metal compound layer 312 in the above-mentioned chip preparation method is only an illustration.
  • the width of the metal compound layer 312 included in the first conductive pillar 21 is 0.5 nm ⁇ 5 nm.
  • Controlling the width of the metal oxide layer 312 to less than 5 nm can not only fill the gap between the metal pillar body 30 and the dielectric layer 10 , but also make the metal oxide layer 312 have little impact on the resistance of the metal pillar body 30 , almost Can be ignored.
  • the problem that the presence of the metal oxide layer 312 causes the resistance of the first conductive pillar 21 to increase is optimized.
  • the chip preparation method it can be known that in the case where the chip includes a plurality of first conductive pillars 31, the oxygen content and/or nitrogen content of the metal compound layer 312 included in the plurality of first conductive pillars 31 It is not necessarily necessary to be the same.
  • the widths of the metal compound layers 312 included in the plurality of first conductive pillars 31 are not necessarily the same, nor are the widths of the metal compound layers 312 included in the same first conductive pillar 31 at each position.
  • the chip further includes a second conductive pillar 32 , the second conductive pillar 32 is a metal pillar 311 , and the second conductive pillar 32 does not include a metal compound layer 312 .
  • the second conductive pillar 32 is arranged parallel to the first conductive pillar 31 , and the first conductive pattern 31 and the second conductive pattern 32 are respectively coupled to both ends of the second conductive pillar 32 .
  • the second conductive pillar 32 is disposed in the dielectric layer 10 .
  • the second conductive pillar 32 penetrates the dielectric layer 10 along the thickness direction of the dielectric layer 10 .
  • the dielectric layer 10 is in contact with the side surface of the metal pillar 311 .
  • the aspect ratio of the first conductive pillar 31 and the second conductive pillar 32 is greater than 2:1.
  • the aspect ratios of the first conductive pillar 31 and the second conductive pillar 32 are 3:1, 4:1, 5:1, 6:1, 7:1, 8:1, 9:1, 10:1, 11:1, 12:1 or greater.
  • the depths of the first conductive pillars 31 and the second conductive pillars 32 refer to the dimensions of the deep edges of the first conductive pillars 31 and the second conductive pillars 32 in the direction perpendicular to the dielectric layer 10 .
  • the width of the first conductive pillar 31 and the second conductive pillar 32 refers to the size of the first conductive pillar 31 and the second conductive pillar 32 in the direction parallel to the dielectric layer 10 .
  • first conductive pattern 21 being disposed between the first conductive pillar 31 (or the second conductive pillar 32) and the electronic component 20 as an example.
  • first conductive pillar 31 and the second conductive pillar 32 can also be directly coupled to the electronic component 20 without the need for the bottom metal, then the conductive part of the electronic component 20 is the first conductive pattern 21 .
  • the first conductive pattern 21 and the second conductive pattern 41 are coupled through the first conductive pillar 31 , or part of the first conductive pattern 21 and the second conductive pattern 41 are coupled through the second conductive pillar 32 catch.
  • Both the first conductive pillar 31 and the second conductive pillar 32 are in direct contact with the dielectric layer 10 without any barrier layer or other film layers.
  • no film layer such as a barrier layer occupies space, and the aspect ratio of the first conductive pillar 31 and the second conductive pillar 32 can be increased.
  • there is no film layer such as a barrier layer that affects the resistance of the first conductive pillar 31 and the second conductive pillar 32 , which can effectively reduce the resistance of the first conductive pillar 31 and the second conductive pillar 32 .
  • the first conductive pillar 31 includes a metal pillar 311 and a metal compound layer 312. Based on process limitations, the gap defect existing between the formed metal pillar 311 and the dielectric layer 10 can be filled by the metal compound layer 312. Thereby, try to avoid the gap between the first conductive pillar 31 and the dielectric layer 10 from penetrating into the gap between the first conductive pillar 31 and the dielectric layer 10 with solutions such as acidic polishing fluid, cleaning fluid or etching fluid, causing damage to the first conductive pattern 21 at the bottom of the first conductive pillar 31 and ultimately causing chip damage. Failure problem.
  • the gap between the metal pillar 311 and the dielectric layer 10 is very small, the volume of the metal compound layer 312 located in the gap is also very small. Therefore, the impact of the metal compound layer 312 on the resistance of the first conductive pillar 31 is very small and almost negligible, and the presence of the metal compound layer 312 will not cause an increase in the resistance of the first conductive pillar 31 .
  • embodiments of the present application further provide a chip, which is a chip packaged by the above-mentioned 2D bare chip.
  • An embodiment of the present application provides a chip, which is a 3D bare chip.
  • the chip includes a first integrated circuit module 50 , a second rewiring layer 60 , a second integrated circuit module 70 and a third rewiring layer 80 that are stacked in sequence.
  • the surface of the third redistribution layer 80 away from the second integrated circuit module 70 is the active surface of the chip, and the surface of the first integrated circuit module 50 away from the second redistribution layer 60 is the non-active surface of the chip.
  • the first integrated circuit module 50 and the second integrated circuit module 70 can be understood as structures including a plurality of circuit electronic components prepared through a previous process.
  • the embodiments of the present application do not limit the functions implemented by the first integrated circuit module 50 , and neither do the structures of the electronic components included in the first integrated circuit module 50 .
  • the first integrated circuit module 50 includes a plurality of electronic components, and the plurality of electronic components are coupled in series and parallel through structures prepared in subsequent processes to implement certain functions.
  • the embodiment of the present application does not limit the functions implemented by the second integrated circuit module 70 , and the structure of the electronic components included in the second integrated circuit module 70 is not limited either.
  • the second integrated circuit module 70 includes a plurality of electronic components, and the plurality of electronic components are coupled in series or parallel through structures prepared in subsequent processes to implement certain functions.
  • a CMOS included in the first integrated circuit module 50 is used as an example for illustration
  • a CMOS included in the second integrated circuit module 70 is used as an example for illustration.
  • the first integrated circuit module 50 is a circuit structure of the logic area
  • the second integrated circuit module 70 is a circuit structure of the storage area
  • the first integrated circuit module 50 is a circuit structure of the logic area
  • the second integrated circuit module 70 is the circuit structure of the detector.
  • the chip may include a transfer layer formed through an intermediate process.
  • the chip may not include the transfer layer formed through the mid-end process.
  • the second redistribution layer 60 includes a first conductive pattern 21 , and the first conductive pattern 21 is coupled to the first integrated circuit module 50 .
  • the wiring layer in the second rewiring layer 60 that is closest to the second integrated circuit module 70 includes a first conductive pattern 21 , and the first conductive pattern 21 is connected with the electrode (such as a source electrode) of the electronic component in the first integrated circuit module 50 S, drain D, gate D) contact coupling.
  • the third rewiring layer 80 includes the second conductive pattern 41 .
  • a wiring layer in the third rewiring layer 80 that is closest to the second integrated circuit module 70 includes the second conductive pattern 41 .
  • the first conductive pillar 31 penetrates the second integrated circuit module 70 , and the first conductive pillar 31 is coupled to the second conductive pattern 41 through the conductive pillar in the transfer layer (in the case where the chip does not include a transfer layer, the first conductive pillar 31 may be directly contact-coupled with the second conductive pattern 41).
  • the third rewiring layer 80 is also coupled to the second integrated circuit module 70 .
  • the chip illustrated in this example includes at least two integrated circuit modules.
  • FIG. 10A only the first integrated circuit module 50 and the second integrated circuit module 70 are used as an example.
  • FIG. 10B from a macro perspective, signals on the active surface of the chip are sequentially transmitted to the first integrated circuit module 70 through the third rewiring layer 80 , the first conductive pillar 31 , and the second rewiring layer 60 . Signals on the active surface of the chip are also transmitted to the second integrated circuit module 70 through the third rewiring layer 80 .
  • the first conductive pillar 31 includes a metal pillar 311 and a metal compound layer 312 .
  • the metal compound layer 312 is located between the metal pillar 311 and the dielectric layer 10 .
  • the metal compound layer 312 covers at least part of the side surfaces of the metal pillar 311 .
  • the side surfaces of the compound layer 312 and the metal pillar 311 that are not covered by the metal compound layer 312 are in contact with the dielectric layer 10 .
  • the chip further includes second conductive pillars 32 , and the second conductive pillars 32 include metal pillars 311 and do not include the metal compound layer 312 .
  • the structure of the first conductive pillar 31 and the second conductive pillar 32 may be the same as the structure of the first conductive pillar 31 and the second conductive pillar 32 in Example 1. Please refer to the relevant description in Example 1, which will not be described again here. .
  • the material of the dielectric layer 10 in Example 1 is an insulating material.
  • the first conductive pillar 31 and the second conductive pillar 32 penetrate the second integrated circuit module 70 . Therefore, they are wrapped in the first conductive pillar. 31 and the dielectric layer 10 around the second conductive pillar 32 is the substrate of the second integrated circuit module 70 . That is to say, the material of the dielectric layer 10 is a semiconductor.
  • a dielectric layer 10 and a first conductive pattern 21 located on one side of the dielectric layer 10 are provided.
  • the embodiment of the present application does not limit the preparation method of the structure shown in Figure 11A.
  • the structure including the first integrated circuit module 50, the transfer layer, and the second wiring layer 60 can be formed through a front-end process, a middle-end process, and a back-end process. , and then the second integrated circuit module 70 is formed on the aforementioned structure through the previous process.
  • the second integrated circuit module 70 includes the dielectric layer 10
  • the second wiring layer 60 includes the first conductive pattern 21 .
  • the dielectric layer 10 includes a hole 11 , the hole 11 is located above the first conductive pattern 21 , and the hole 11 is in contact with the first conductive pattern 21 .
  • a selective growth process is used to grow the metal pillar body 30 in the hole 11 starting from the surface of the first conductive pattern 21 from bottom to top.
  • a second conductive pattern 41 is formed on the side of the dielectric layer 10 away from the first conductive pattern 21, and the second conductive pattern 41 is coupled to the first conductive pillar 31.
  • both the first conductive pillar 31 and the second conductive pillar 32 are in direct contact with the dielectric layer 10 without any barrier layer or other film layers.
  • no film layers such as barrier layers occupy space, and the aspect ratio of the first conductive pillar 31 and the second conductive pillar 32 can be relatively large to meet the needs of 3D bare chips.
  • there is no film layer such as a barrier layer that affects the resistance of the first conductive pillar 31 and the second conductive pillar 32 which can effectively reduce the resistance of the first conductive pillar 31 and the second conductive pillar 32 .
  • the first conductive pillar 31 includes a metal pillar 311 and a metal compound layer 312. Based on process limitations, the gap defect existing between the formed metal pillar 311 and the dielectric layer 10 can be filled by the metal compound layer 312. Thereby, try to avoid the gap between the first conductive pillar 31 and the dielectric layer 10 from penetrating into the gap between the first conductive pillar 31 and the dielectric layer 10 with solutions such as acidic polishing fluid, cleaning fluid or etching fluid, causing damage to the first conductive pattern 21 at the bottom of the first conductive pillar 31 and ultimately causing chip damage. Failure problem.
  • the gap between the metal pillar 311 and the dielectric layer 10 is very small, the volume of the metal compound layer 312 located in the gap is also very small. Therefore, the impact of the metal compound layer 312 on the resistance of the first conductive pillar 31 is very small and almost negligible, and the presence of the metal compound layer 312 will not cause an increase in the resistance of the first conductive pillar 31 .
  • embodiments of the present application further provide a chip, which is a chip that is packaged with the above-mentioned 3D bare chip in this example.
  • An embodiment of the present application provides a chip, which is a packaged chip.
  • the chip includes a first die 91 , a second die 92 , and a fourth wiring layer 99 .
  • the bonding pad of the first bare chip 91 is the first conductive pattern 21, and the first conductive pillar 31 penetrates from the non-active surface of the first bare chip 91 to the back of the bonding pad.
  • the fourth redistribution layer 99 includes a second conductive pattern 41 coupled to the first conductive pillar 31 .
  • the second bare chip 92 is located on the side of the fourth rewiring layer 99 away from the first bare chip 91 , and the second bare chip 92 is coupled to the fourth rewiring layer 99 .
  • the second bare chip 92 is bonded and coupled to the fourth rewiring layer 99 through solder balls.
  • the signal of the first bare chip 91 is transmitted to the substrate (not shown in FIG. 12A ) bonded to the first bare chip 91 through the bonding pad.
  • the signal of the second bare chip 92 is transmitted to the fourth rewiring layer 99 , and transmitted to the pad of the first bare chip 91 through the first conductive pillar 31 , and then transmitted to the substrate bonded to the first bare chip 91 .
  • the embodiment of the present application does not limit the structures of the first bare chip 91 and the second bare chip 92, and they can be set appropriately as needed.
  • the first conductive pillar 31 includes a metal pillar 311 and a metal compound layer 312.
  • the metal compound layer 312 is located between the metal pillar 311 and the dielectric layer 10.
  • the metal compound layer 312 covers at least part of the side surface of the metal pillar 311.
  • the side surfaces of the compound layer 312 and the metal pillar 311 that are not covered by the metal compound layer 312 are in contact with the dielectric layer 10 .
  • the chip further includes second conductive pillars 32 , and the second conductive pillars 32 include metal pillars 311 and do not include the metal compound layer 312 .
  • the structure of the first conductive pillar 31 and the second conductive pillar 32 may be the same as the structure of the first conductive pillar 31 and the second conductive pillar 32 in Example 1. Please refer to the relevant description in Example 1 and will not be repeated here. .
  • the dielectric layer 10 in this example includes the substrate in the integrated circuit module formed by the front-end process, the insulation layer in the transfer layer formed by the middle-end process, and the rewiring layer formed by the back-end process. Multiple layers of insulation.
  • the hole 11 in the dielectric layer 10 is located above the pad in the first bare chip 91 .
  • a dielectric layer 10 and a first conductive pattern 21 located on one side of the dielectric layer 10 are provided.
  • a bare chip can be formed through a front-end process, a middle-end process, and a back-end process, and then a hole 11 can be formed using a drilling process to obtain the first bare chip 91 in this application.
  • a selective growth process is used to grow the metal pillar body 30 in the hole 11 starting from the surface of the first conductive pattern 21 from bottom to top.
  • a second conductive pattern 41 is formed on the side of the dielectric layer 10 away from the first conductive pattern 21, and the second conductive pattern 41 is coupled to the first conductive pillar 31.
  • a fourth redistribution layer 99 is formed on the side of the dielectric layer 10 away from the first conductive pattern 21 , and the fourth redistribution layer 99 includes the second conductive pattern 41 .
  • the chip includes a first bare chip 91, a second bare chip 92 and solder joints.
  • the bonding pad of the first bare chip 91 is the first conductive pattern 21, and the first conductive pillar 31 penetrates from the non-active surface of the first bare chip 91 to the back of the bonding pad.
  • the soldering point is the second conductive pattern 41 , and the second conductive pattern 41 is coupled to the first conductive pillar 31 .
  • the signal of the first bare chip 91 is transmitted to the first conductive pillar 31 through the bonding pad, then to the soldering point (second conductive pattern 41), and then to the substrate bonded to the first bare chip 91 (not shown in FIG. 13 from.
  • the first conductive pillar 31 includes a metal pillar 311 and a metal compound layer 312 .
  • the metal compound layer 312 is located between the metal pillar 311 and the dielectric layer 10 .
  • the metal compound layer 312 covers at least part of the side surfaces of the metal pillar 311 .
  • the side surfaces of the compound layer 312 and the metal pillar 311 that are not covered by the metal compound layer 312 are in contact with the dielectric layer 10 .
  • the chip further includes second conductive pillars 32 , and the second conductive pillars 32 include metal pillars 311 and do not include the metal compound layer 312 . Both ends of the second conductive pillar 32 are respectively coupled to the solder pads of the first bare chip 91 and the solder joints (second conductive patterns 41 ) on the non-active surface of the first bare chip 91 .
  • the structure of the first conductive pillar 31 and the second conductive pillar 32 may be the same as the structure of the first conductive pillar 31 and the second conductive pillar 32 in Example 1. Please refer to the relevant description in Example 1, which will not be described again here. .
  • the dielectric layer 10 in this example includes the substrate in the integrated circuit module formed by the front-end process, the insulation layer in the transfer layer formed by the middle-end process, and the rewiring layer formed by the back-end process. Multiple layers of insulation.
  • the hole 11 in the dielectric layer 10 is located above the pad in the first bare chip 91 .
  • S10-S40 are the same as the preparation method of the chip when the chip includes the fourth rewiring layer 99 in this example, and will not be described again here.
  • a second conductive pattern 41 is formed on the side of the dielectric layer 10 away from the first conductive pattern 21, and the second conductive pattern 41 is coupled to the first conductive pillar 31.
  • the second conductive pattern 41 is a solder joint located on the non-active surface of the first bare chip 91 .
  • the second conductive pattern 41 is a structure such as a solder ball, a micro-bump, or the like.
  • Step S60 may also be before step S10 or after other steps.
  • the embodiment of the present application is not limited to step S60 after S50.
  • the chip provided by the embodiment of the present application is based on the structure and preparation method of the first conductive pillar 31 and the second conductive pillar 32, and can be suitable for chips with high aspect ratio requirements.

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Abstract

本申请实施例提供一种芯片及其制备方法、电子设备，涉及半导体技术领域，用于解决如何提高芯片中导电图案之间的互联耦接效果的问题。本申请提供的芯片可以是裸芯片，也可以是封装后的芯片。芯片包括：介质层和设置在介质层内的第一导电柱，第一导电柱沿介质层的厚度方向贯穿介质层；芯片还包括第一导电图案和第二导电图案位于第一导电柱相对的两侧，且与第一导电柱耦接；其中，第一导电柱包括金属柱和金属化合物层，金属化合物层位于金属柱与介质层之间、覆盖金属柱的至少部分侧面；第一导电柱直接与介质层接触，二者之间未设置阻挡层。芯片中的第一导电柱的电阻较小，且第一导电柱可以具有较大的深宽比。

Description

芯片及其制备方法、电子设备 技术领域
本申请涉及半导体技术领域，尤其涉及一种芯片及其制备方法、电子设备。
背景技术
随着电子技术的发展，用户对电子设备的性能要求越来越高，使得电子设备中芯片尺寸越来越大、数量越来越多。但随着电子设备不断向集成化、超薄化趋势发展，电子设备中的芯片也不得不向小型化发展。基于此，为了同时满足电子设备对芯片的性能需求和尺寸需求，不得不缩小芯片中导电图案的尺寸。
但是，导电图案尺寸的减小，会增加导电图案之间互连耦接的难度。而且，导电图案通过导电柱互连耦接时，导电柱的电阻、制备工艺等特性，会对互联耦接效果以及芯片的良率产生直接的影响。
发明内容
本申请实施例提供一种芯片及其制备方法、电子设备，用于解决如何提高芯片中导电图案之间的互联耦接效果的问题。
为达到上述目的，本申请采用如下技术方案：
本申请实施例的第一方面，提供一种芯片，芯片可以是裸芯片，也可以是封装后的芯片。芯片包括：第一导电柱和介质层，第一导电柱设置在介质层内，且沿介质层的厚度方向贯穿介质层，或者理解为介质层包裹在第一导电柱外围；第一导电图案和第二导电图案，位于第一导电柱相对的两侧，第一导电柱与第一导电图案和第二导电图案对应耦接；其中，第一导电柱包括金属柱和金属化合物层，金属化合物层位于金属柱与介质层之间、覆盖金属柱的至少部分侧面；第一导电柱通过金属化合物层，以及金属柱未被金属化合物层覆盖的侧面，与介质层接触，第一导电柱与介质层之间未设置阻挡层等膜层。应当理解的是，若金属柱的侧面全部被金属化合物层覆盖，那么金属柱未被金属化合物层覆盖的部分则不存在，第一导电柱通过金属化合物层与介质层接触。此外，根据芯片结构的不同，第一导电图案和第二导电图案的结构也不同。
本申请实施例提供的芯片中，第一导电图案和第二导电图案通过第一导电柱耦接，第一导电柱直接与介质层接触，没有阻挡层等膜层。这样一来，一方面没有阻挡层等膜层占用空间，可增大第一导电柱的深宽比。另一方面，没有阻挡层等膜层影响第一导电柱的电阻，可有效降低第一导电柱的电阻。在此基础上，第一导电柱包括金属柱和金属化合物层，在基于工艺限制，形成的金属柱与介质层之间存在的缝隙缺陷可以通过金属化合物层来填补。从而尽量避免第一导电柱与介质层之间的缝隙处因渗入酸性研磨液、清洗液或者刻蚀液等溶液，导致第一导电柱底部的第一导电图案损伤，最终导致芯片失效的问题。另外，由于金属柱与介质层之间的缝隙很小，因此，位于上述缝隙内的金属化合物层的体积也很小。因此，金属化合物层对第一导电柱的电阻的影响很小，几乎可以忽略，金属化合物层的存在不会导致第一导电柱的电阻升高。
在一种可能的实现方式中，金属柱采用选择性生长工艺形成。采用选择性生长工艺形成金属柱，无需阻挡层等膜层，可提高金属柱的宽长比。且形成的金属柱内部不会形成孔隙，可降低金属柱的电阻。
在一种可能的实现方式中，金属化合物层包括金属氧化物材料。一种工艺简单的实现方式。
在一种可能的实现方式中，金属化合物层包括金属氮化物材料。一种工艺简单的实现方式。
在一种可能的实现方式中，金属化合物层包括金属氧化物材料和金属氮化物材料。一种工艺简单的实现方式。
在一种可能的实现方式中，金属化合物层包括金属氮氧化物材料。一种工艺简单的实现方式。
在一种可能的实现方式中，金属化合物层包括金属氧化物材料和金属氮氧化物材料。一种工艺简单的实现方式。
在一种可能的实现方式中，金属化合物层包括金属氮化物材料和金属氮氧化物材料。一种工艺简单的实现方式。
在一种可能的实现方式中，金属化合物层包括金属氧化物材料、金属氮化物材料和金属氮氧化物材料。一种工艺简单的实现方式。
在一种可能的实现方式中，金属化合物层通过对金属柱侧面表面进行氧化处理后得到。一种工艺简单的实现方式。
在一种可能的实现方式中，金属化合物层通过对金属柱侧面表面进行氮化处理后得到。一种工艺简单的实现方式。
在一种可能的实现方式中，金属化合物层通过对金属柱侧面表面进行氧化处理和氮化处理后得到。一种工艺简单的实现方式。
在一种可能的实现方式中，金属化合物层包括的金属与金属化合物层包括的金属相同。
在一种可能的实现方式中，金属化合物层朝向金属柱的表面平整。采用工艺可控的处理方式形成金属化合物层，提高芯片结构的可控性。
在一种可能的实现方式中，沿平行于介质层的方向，金属化合物层的宽度为0.5nm～5nm。将金属氧化物层的宽度控制在小于5nm，既能填满第一导电柱与介质层之间的缝隙，又可以使金属氧化物层对第一导电柱的电阻影响很小，几乎可以忽略。从而优化金属氧化物层的存在导致第一导电柱电阻升高的问题。
在一种可能的实现方式中，第一导电图案的材料包括金属，第一导电柱与第一导电图案接触。在金属结构上采用选择性生长工艺形成金属柱，工艺简单，易于实现。
在一种可能的实现方式中，芯片包括电子元件和第一重布线层；第一导电图案设置在第一导电柱与电子元件之间，第一重布线层包括第二导电图案。一种应用场景。
在一种可能的实现方式中，芯片包括依次层叠设置的第一集成电路模块、第二重布线层、第二集成电路模块以及第三重布线层；第二重布线层包括第一导电图案，第一导电图案与第一集成电路模块耦接；第一导电柱贯穿第二集成电路模块，第三重布线层包括第二导电图案；第三重布线层还与第二集成电路模块耦接。一种应用场景。
在一种可能的实现方式中，芯片包括裸芯片；裸芯片的焊盘为第一导电图案；第一导电柱从裸芯片的非有源面贯穿至焊盘背面；芯片还包括第四重布线层，第四重布线层包括第二导电图案。一种应用场景。
在一种可能的实现方式中，芯片包括裸芯片；裸芯片的焊盘为第一导电图案；第一导电柱从裸芯片的非有源面贯穿至焊盘背面；第二导电图案为位于裸芯片非有源面上的焊点。一种应用场景。
在一种可能的实现方式中，芯片包括多个第一导电柱，多个第一导电柱包括的多个金属化合物层的含氧量、含氮量或者宽度不完全相同。
在一种可能的实现方式中，芯片还包括第二导电柱，第二导电柱为金属柱，金属柱设置在介质层内，且沿介质层的厚度方向贯穿介质层，金属柱的侧面与介质层接触。
在一种可能的实现方式中，第一导电柱的深宽比大于2:1。本申请提供的第一导电柱的结构，可应用于大深宽比的结构中。
本申请实施例的第二方面，提供一种电子设备，包括权利要求第一方面任一项的芯片和电路板，芯片设置在电路板上。
本申请实施例提供的电子设备包括第一方面任一项的芯片，其有益效果与芯片的有益效果相同，此处不再赘述。
本申请实施例的第三方面，提供一种芯片的制备方法，包括：提供介质层和位于第一中段介质层侧的第一导电图案；介质层具有孔，孔位于第一导电图案上方；采用选择性生长工艺，在孔内从第一导电图案的表面开始，自下而上生长形成金属柱本体；对金属柱本体进行化学处理，使金属柱本体未与介质层接触的侧面膨胀至与介质层接触；去除金属柱本体顶面被化学处理的部分，形成第一导电柱；第一导电柱包括金属柱和金属化合物层，金属柱本体未被化学处理的部分为金属柱，金属柱本体侧面被化学处理的部分为金属化合物层；金属化合物层与介质层接触，金属柱未被金属化合物层覆盖的侧面也与介质层接触；在介质层远离第一导电图案一侧形成第二导电图案，第二导电图案与第一导电柱耦接。
本申请实施例提供的芯片的制备方法的有益效果与芯片的有益效果相同，此处不再赘述。
在一种可能的实现方式中，对金属柱本体进行化学处理，包括：对金属柱本体进行氧化处理。一种工艺简单的实现方式。
在一种可能的实现方式中，对金属柱本体进行化学处理，包括：对金属柱本体进行氮化处理。一种工艺简单的实现方式。
在一种可能的实现方式中，对金属柱本体进行氧化处理，包括：使用含氧气或氧化剂溶液体对金属柱本体进行氧化。一种工艺简单的实现方式。
在一种可能的实现方式中，对金属柱本体进行氮化处理，包括：使用含氮气体对金属柱本体进行氮化。一种工艺简单的实现方式。
在一种可能的实现方式中，对金属柱本体进行氧化处理和氮化处理，包括：使用含氧和氮的气体对金属柱本体进行氧化和氮化。一种工艺简单的实现方式。
在一种可能的实现方式中，金属柱本体被化学处理后，顶面形成的金属化合物的厚度小于10nm。这样一来，采用现有的化学机械研磨工艺即可去除金属柱本体顶面的 金属化合物，无需改变工艺和设备。
在一种可能的实现方式中，沿平行于介质层的方向，金属化合物层的宽度为0.5nm～5nm。将金属氧化物层的宽度控制在小于5nm，既能填满第一导电柱与介质层之间的缝隙，又可以使金属氧化物层对第一导电柱的电阻影响很小，几乎可以忽略。从而优化金属氧化物层的存在导致第一导电柱电阻升高的问题。
在一种可能的实现方式中，介质层具有多个孔，采用选择性生长工艺形成多个金属柱本体；形成第一导电柱的同时，还形成第二导电柱；侧面与介质层接触的金属柱本体，在去除金属柱本体顶面被化学处理的部分后，形成第二导电柱，第二导电柱为金属柱。
附图说明
图1为本申请实施例提供的一种电子设备的框架示意图；
图2A-图2D为本申请实施例提供的一种裸芯片的制备过程示意图；
图3A为本申请实施例提供的一种芯片中导电柱的结构示意图；
图3B为本申请实施例提供的另一种芯片中导电柱的结构示意图；
图4为本申请实施例提供的一种芯片的制备方法的流程图；
图5A-图9C为本申请实施例提供的一种芯片的制备过程示意图；
图10A为本申请实施例提供的另一种芯片的结构示意图；
图10B为本申请实施例提供的一种芯片的宏观结构示意图；
图11A-图11D为本申请实施例提供的另一种芯片的制备过程示意图；
图12A为本申请实施例提供的又一种芯片的结构示意图；
图12B为本申请实施例提供的一种裸芯片的结构示意图；
图12C-图12F为本申请实施例提供的又一种芯片的制备过程示意图；
图13为本申请实施例提供的又一种芯片的结构示意图。
附图标记：
1-电子设备；2-显示模组；3-中框；4-壳体；5-盖板；100-衬底；10-介质层；101-第一介质层；102-第二介质层；11-孔；20-电子元件；21-第一导电图案；30-金属柱本体；31-第一导电柱；311-金属柱；312-金属化合物层；32-第二导电柱；40-第一重布线层；41-第二导电图案；50-第一集成电路模块；60-第二重布线层；70-第二集成电路模块；80-第三重布线层；91-第一裸芯片；92-第二裸芯片；99-第四重布线层。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。
以下，本申请实施例中，术语“第一”、“第二”等仅用于描述方便，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”等的特征可以明示或者隐含地包括一个或者更多个该特征。在本申请的描述中，除非另有说明，“多个”的含义是两个或两个以上。
本申请实施例中，“上”、“下”、“左”以及“右不限于相对附图中的部件示意置放的方位来定义的，应当理解到，这些方向性术语可以是相对的概念，它们用于相对于的描述和澄清，其可以根据附图中部件附图所放置的方位的变化而相应地发生变化。
在本申请实施例中，除非上下文另有要求，否则，在整个说明书和权利要求书中，术语“包括”被解释为开放、包含的意思，即为“包含，但不限于”。在说明书的描述中，术语“一个实施例”、“一些实施例”、“示例性实施例”、“示例性地”或“一些示例”等旨在表明与该实施例或示例相关的特定特征、结构、材料或特性包括在本公开的至少一个实施例或示例中。上述术语的示意性表示不一定是指同一实施例或示例。此外，所述的特定特征、结构、材料或特点可以以任何适当方式包括在任何一个或多个实施例或示例中。
在描述一些实施例时，可能使用了“耦接”及其衍伸的表达。例如，描述一些实施例时可能使用了术语“耦接”以表明两个或两个以上部件有直接物理接触或电接触。然而，术语“耦接”也可能指两个或两个以上部件彼此间并无直接接触，但仍彼此协作或相互作用。这里所公开的实施例并不必然限制于本文内容。
在本申请实施例中，“和/或”，仅仅是一种描述关联对象的关联关系，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B这三种情况。另外，本文中字符“/”，一般表示前后关联对象是一种“或”的关系。
本申请实施例中参照作为理想化示例性附图的剖视图和/或平面图和/或等效电路图描述了示例性实施方式。在附图中，为了清楚，放大了层和区域的厚度。因此，可设想到由于例如制造技术和/或公差引起的相对于附图的形状的变动。因此，示例性实施方式不应解释为局限于本文示出的区域的形状，而是包括因例如制造而引起的形状偏差。例如，示为矩形的蚀刻区域通常将具有弯曲的特征。因此，附图中所示的区域本质上是示意性的，且它们的形状并非旨在示出设备的区域的实际形状，并且并非旨在限制示例性实施方式的范围。
本申请实施例提供一种的电子设备。该电子设备例如为消费性电子产品、家居式电子产品、车载式电子产品、金融终端产品、通信电子产品。其中，消费性电子产品如为手机(mobile phone)、平板电脑(pad)、笔记本电脑、电子阅读器、个人计算机(personal computer，PC)、个人数字助理(personal digital assistant，PDA)、桌面显示器、智能穿戴产品(例如，智能手表、智能手环)、虚拟现实(virtual reality，VR)终端设备、增强现实(augmented reality，AR)终端设备、无人机等。家居式电子产品如为智能门锁、电视、遥控器、冰箱、充电家用小型电器(例如豆浆机、扫地机器人)等。车载式电子产品如为车载导航仪、车载高密度数字视频光盘(digital video disc，DVD)等。金融终端产品如为自动取款机(automated teller machine，ATM)机、自助办理业务的终端等。通信电子产品如为服务器、存储器、基站等通信设备。
本申请实施例对上述电子设备的具体形式不做特殊限制。以下实施例为了方便说明，均是以电子设备为手机为例进行举例说明。
在此情况下，如图1所示，电子设备1主要包括显示模组2、中框3、壳体(或者称为电池盖、后壳)4以及盖板5。
显示模组2具有能够看到显示画面的出光侧和与上述出光侧相对设置的背面，显示模组2的背面靠近中框3，盖板5设置在显示模组2的出光侧。
上述显示模组2，包括显示屏(display panel，DP)。
在本申请的一种可能的实施例中，显示模组2为液晶显示模组。在此情况下，上述显示屏为液晶显示屏(liquid crystal display，LCD)。基于此，显示模组2还包括位于液晶显示屏背面(远离LCD用于显示画面的一侧面)的背光模组(back light unit，BLU)。
背光模组可以向液晶显示屏提供光源，以使得液晶显示屏中的各个亚像素(sub pixel)能够发光以实现图像显示。
或者，在本申请的另一种可能的实施例中，显示模组2为有机发光二极管显示模组。在此情况下，上述显示屏为有机发光二极管(organic lightemitting diode，OLED)显示屏。由于OLED显示屏中每个亚像素内设置有电致发光层，所以可以使得OLED显示屏在接收到工作电压后，实现自发光。在此情况下，具有OLED显示屏的显示模组2中无需再设置上述背光模组。
盖板5位于显示模组2远离中框3一侧，盖板5例如可以是盖板玻璃(cover glass，CG)，该盖板玻璃可以具有一定的韧性。
中框3位于显示模组2和壳体4之间，中框3远离显示模组2的表面用于安装电池、印刷电路板(printed circuit board，PCB)、摄像头(camera)、天线等内部元件。壳体4与中框3盖合后，上述内部元件位于壳体4与中框3之间。
上述电子设备1还包括设置于PCB上的处理器(center processing unit，CPU)芯片、射频芯片、射频功率放大器((power amplifier，PA)芯片、系统级芯片(system on a chip，SOC)、电源管理芯片(power management integrated circuits，PMIC)、存储芯片(例如高带宽存储器(high bandwidth memory，HBM))、音频处理器芯片、触摸屏控制芯片、NAND flash(闪存)、图像传感器芯片、充电保护芯片等芯片，PCB用于承载上述芯片，并与上述芯片完成信号交互。
芯片(或者称之为逻辑集成器件，或者称之为集成电路器件)自身的可靠性等性能，对电子设备的使用寿命和性能有着直接的影响。
本申请实施例提供一种芯片，该芯片可以应用于上述电子设备中。
本申请实施例提供的芯片可以是未封装的裸芯片，未封装的裸芯片可以包括一个集成电路模块(可以称为二维(2D)裸芯片)，未封装的裸芯片也可以包括多个集成电路模块(可以称为三维(3D)裸芯片)。本申请实施例提供的芯片也可以是封装后的芯片，封装后的芯片中可以包括一个裸芯片，也可以包括多个裸芯片。
以下，以几个示例，对本申请实施例提供的芯片进行示意说明。
示例一
本申请实施例提供一种芯片，芯片为2D裸芯片。
芯片制备过程通常包括前段制程(front end of line，FEOL)、中段制程(midend of line，MEOL)以及后段制程(back end of line，BEOL)。
如图2A所示，前段制程用于形成包括晶体管、电容、电感等电子元件的集成电路模块。其中，本申请实施例中的电子元件，可以是前段工艺制备形成在衬底上、未独立封装的元件。当然，根据制备工艺的不同，包括晶体管、电容、电感等电子元件的集成电路模块也可以是后段制程中制备得到的，本申请实施例中仅为一种示意。图2A中以集成电路模块中的两个晶体管为例进行示意说明，晶体管包括源极S，漏极D 以及栅极G。
如图2B所示，中段制程用于形成将多个电子元件中的导电图案引出至同一平面的转接层。转接层中的导电柱与电子元件的源极S、漏极D、栅极G耦接。转接层的形成，通常先形成具有孔的介质层，介质层中的孔位于导电图案上方，然后再用填孔技术形成导电柱。
其中，如图2C所示，在一些工艺节点中，中段制程形成的转接层包括两部分，第一部分为：设置在集成电路表面的底部金属和包裹在底部金属外围的第一中段介质层，底部金属与电子元件的源极S、漏极D、栅极G耦接。第二部分为：设置在底部金属表面的导电柱和包裹在导电柱外围的第二中段介质层，导电柱与底部金属耦接。底部金属例如为条状，导电柱例如为柱状。图2C的这种结构，可以优化后段制程中重布线层的排布。
以下为了便于说明，以中段制程形成的结构为图2C所示的结构为例进行示意。
如图2D所示，后段制程用于形成位于转接层上的重布线层。电子元件中的信号通过转接层传输至重布线层，从而引出至重布线层表面的信号端。芯片形成后，信号端暴露于芯片的表面。例如，信号端作为芯片的焊盘。
随着集成电路技术持续向前发展，芯片进一步向集成化、小型化发展，晶体管等电子元件的特征尺寸也随之缩小，对中段工艺中通过导电柱实现电子元件与重布线层的金属互连的填孔技术提出了新的挑战。
在一些实施例中，采用电镀工艺形成铜(Cu)柱为导电柱。
在另一些实施例中，采用化学气相沉积(chemical vapor deposition，CVD)形成钨(W)柱为导电柱。
但是采用电镀工艺通常需要阻挡层(或者粘附层)和电镀种子层，阻挡层覆盖导电柱的侧面和底面。采用化学气相沉积工艺通常需要成核层，成核层覆盖导电柱的侧面和底面。然而，阻挡层、种子层或者成核层会占据第二中段介质层中孔的孔隙空间，导致孔径减小、孔的深宽比增大，增大导电柱的工艺难度。而且，采用电镀工艺形成导电柱的过程中，是从孔的底部和侧面同时电镀金属柱，且在拐角处电镀的速率相对较快，从而容易出现导电柱表面已经封闭，内部却留有孔隙的情况(如图3A所示)。同理，采用化学气相沉积工艺形成导电柱的过程中，也是从孔的底部和侧面同时沉积金属柱，且在拐角处沉积的速率相对较快，从而容易出现导电柱表面已经封闭，内部却留有孔隙的情况。而导电柱内部留有孔隙，会导致导电柱的电阻偏高，不能满足芯片微缩所需的性能。
基于此，在一些实施例中，采用较薄的氮化钛(TiN)作为阻挡层，填孔钴(Co)作为导电柱。这样一来，可以增大导电柱的工艺窗口，降低导电柱的电阻。
然而，随着工艺节点进一步微缩，这种需要阻挡层的钴填充结构，依然无法满足高性能芯片要求。
基于此，在一些实施例中，采用选择性生长的钨(W)化学气相沉积工艺形成导电柱。
选择性生长工艺从孔底部露出的底部金属的表面自下而上的沉积金属，不会在第二中段介质层中孔的孔壁上生长，无需阻挡层。这样一来，没有阻挡层占用孔隙空间， 在孔中直接形成导电柱，可适用于高深宽比的芯片结构中。而且，由于金属钨是自下而上生长，因此，形成的导电柱内部不会成孔隙，可降低导电柱的电阻。
但是，正因为金属钨不会在第二中段介质层中孔的孔壁上生长，采用选择性生长工艺生长的导电柱与第二中段介质层中孔壁的电介质之间没有阻挡层，这就容易在导电柱与第二中段介质层之间形成随机的、无规则的缝隙缺陷(如图3B所示)。这样一来，在后续填孔后的化学机械研磨(chemical mechanical polishing，CMP)，或者后续通过刻蚀工艺对膜层图案化等工艺中，容易从导电柱与第二中段介质层之间的缝隙处渗入酸性研磨液或者刻蚀液等溶液，导致导电柱底部的底部金属损伤，最终导致芯片失效。
基于此，本申请实施例还提供一种导电柱和形成导电柱的方法，采用本申请实施例提供的方法形成的导电柱直接与第二中段介质层贴合接触，不会残留缝隙。
下面，结合芯片的结构，对导电柱的结构及制备方法进行示意说明。
如图4所示，提供一种芯片的制备方法，包括：
S10、提供介质层和位于第一中段介质层侧的第一导电图案。
在一些实施例中，如图5A所示，步骤S10包括：
S11、衬底100上形成电子元件20，以形成芯片的集成电路模块。
其中，在芯片作为射频器件应用于基站等电子设备中时，衬底100的材料为绝缘材料。在芯片作为功率器件应用于手机等电子设备中时，衬底100的材料为导电材料。
电子元件20是电子电路中的基本元素，具有至少一个引线接点，引线接点用于与布线互连耦接，以完成信号传输。电子元件20可以是电阻、电容、电感、晶体管、二极管、运算放大器、排阻、逻辑门等。例如，电子元件20为晶体管，电子元件20包括的引线接点为源极S、漏极D、栅极G。
芯片可以包括一个电子元件20，也可以包括多个电子元件20，本申请实施例提供的芯片的制备方法仅是以芯片中的一个电子元件20为例，对芯片中各部分的结构进行示意说明。芯片包括多个电子元件20的情况下，多个电子元件20可以是同一种类型的电子元件，也可以是不同种类型的电子元件。本申请实施例对芯片中的电子元件20的数量、种类、排布方式不做限定，根据需要合理设置即可。每个电子元件20包括至少一个第一导电图案21。
示例的，如图5A所示，电子元件20包括互补金属氧化物半导体器件(complementary metal oxide semiconductor，CMOS)，CMOS的源极S、漏极D以及栅极G均为电子元件20的引线接点。其中，图5A中还示意出了位于栅极G下方的栅绝缘层和位于栅极G侧面的侧墙。图5A中示意的电子元件20的结构仅为一种示意，不做任何限定。
或者，示例的，电子元件20为高电子迁移率晶体管(high electron mobility transistor，HEMT)、异质结双极晶体管(heterojunction bipolar transistor，HBT)、双极结型晶体管(bipolar junction transistor，BJT)等。
S12、在电子元件20的表面形成底部金属(第一导电图案21)和包裹在底部金属外围的层间介质层(inter level dielectric，ILD)。
其中，不对底部金属俯视图的形状进行限定，例如可以为条状。底部金属可以作 为本示例中的第一导电图案21。当然，也可以是底部金属上的其他金属图案作为本示例中的第一导电图案21，此处仅为一种示意。芯片包括的第一导电图案21可以是一个，也可以是多个。
S13、在层间介质层ILD上形成介质层10，介质层10具有孔11，孔11位于第一导电图案21上方，与第一导电图案21接触。
本申请实施例不对孔11的形状和大小进行限定。孔11可以露出第一导电图案21远离衬底100的顶面的部分区域，孔11也可以露出第一导电图案21远离衬底100的顶面的全部区域。或者理解为，孔11在衬底100上的投影可以位于第一导电图案21在衬底100上的投影内，孔11在衬底100上的投影也可以与第一导电图案21在衬底100上的投影重合。当然，孔11在衬底100上的投影也可以覆盖第一导电图案21在衬底100上的投影，只要确保后续形成在孔11内的第一导电柱不会导致相邻第一导电图案21短路即可。或者理解为，孔11位于第一导电图案21的上方，孔11的面积可以小于第一导电图案21的面积，孔11的面积也可以等于第一导电图案21的面积，孔11的面积也可以大于第一导电图案21的面积。本申请实施例以孔11的面积小于第一导电图案21顶面的面积为例进行示意。
本申请实施例不对孔11的数量进行限定，孔11的数量与第一导电图案21的数量对应设置即可。需要强调的是，一个第一导电图案21可以与一个孔11对应设置，也就是说，一个第一导电图案21上方可以仅设置一个孔11。一个第一导电图案21也可以与多个孔11对应设置，也就是说，一个第一导电图案21上方可以设置多个孔11。也可以是多个第一导电图案21与同一个孔11对应设置，也就是说，多个第一导电图案21(例如该多个第一导电图案21例如传输同一信号)上方对应设置同一个孔11。
为了便于说明，如图5A所示，本申请实施例中以介质层10包括多个孔11，每个孔11与一个第一导电图案21对应设置为例进行示意。
例如，可以采用化学气相沉积(chemical vapor deposition，CVD)、物理气相沉积或其它沉积方法形成中段介质膜，然后在中段介质膜上采用光刻和刻蚀的方法形成孔11，以制备得到介质层10。
介质层10的材料，例如可以包括硅的氧化物(例如，二氧化硅SiO 2)、硅的氮化物(例如，氮化硅SiN 4)、硅的掺杂氧化物、硅的氟化氧化物、硅的掺碳氧化物或者相关技术中已知的各种低介电常数(k)的电介质材料及其组合。
在一些实施例中，如图5A所示，介质层10为单层膜层。这样一来，结构简单，工艺步骤少。
在另一些实施例中，介质层10包括多层介质膜层。多层介质膜层的材料可以相同，多层介质膜层的材料也可以不相同。
示例的，如图5B所示，介质层10包括第一介质层101和第二介质层102，第一介质层101靠近第一导电图案21设置，第一介质层101的介电常数大于第二介质层102的介电常数。
待形成的导电柱与第一导电图案21相距比较近的位置处设置为介电常数较大的第一介质层101，可提高第一导电图案21与待形成的导电柱之间的绝缘效果。
S20、如图6A和图6B所示，采用选择性生长(selectivedeposition)工艺，在孔 11内从第一导电图案21的表面开始，自下而上生长形成金属柱本体30。
选择性生长工艺是指在衬底上限定的区域内进行的外延生长，应用在本申请中，就是在第一导电图案21的表面开始外延生长，不从介质层10的表面开始外延生长。由于本申请是通过选择性外延生长工艺直接在第一导电图案21这个金属结构的表面外延生长金属柱本体30的，因此，采用选择性生长工艺形成金属柱本体30，无需阻挡层、成核层等膜层。
那么，本申请采用选择性生长工艺最终形成的第一导电柱，第一导电柱的底面直接与第一导电图案21接触，第一导电柱的侧面直接与介质层10接触，第一导电柱为实心结构，第一导电柱的内部没有孔隙。
在一些实施例中，步骤S20包括：
S21、对介质层10中孔11的表面进行处理，去除孔壁和第一导电图案21表面的化学残余物和悬挂键。
化学残余物例如可以是在介质层10上形成孔11的过程中残留下的化学物质，悬挂键例如可以是没有电子能配对的化学键。
对介质层10中孔11的表面进行处理的方式，例如可以是加热处理、等离子体处理、通入还原性的气体处理、通入氧化性的气体处理等方式进行化学处理。
S22、采用选择性生长工艺，在孔11内从第一导电图案21的表面开始，自下而上生长形成金属柱本体30。
其中，在选择性生长过程中，通过控制选择性生长的速率，使金属在孔11内从第一导电图案21的表面开始自下而上生长，而不会使金属同时从孔壁开始生长。因此，采用选择性生长工艺形成的金属柱本体30为实心柱，不会向采用电镀或者化学气相沉积工艺那样，在金属柱本体30内部形成孔隙。而且，采用选择性生长工艺形成金属柱本体30，无需阻挡层、成核层等膜层。
金属柱本体30的高度，可以根据孔11的深度以及后续化学机械研磨工艺的研磨厚度调节。如图6B所示，在同时形成多个金属柱本体30的情况下，多个金属柱本体30的高度可以相同，也可以不同。
此时，如图6A和图6B所示，基于选择性生长工艺的工艺限制，金属柱本体30与介质层10之间会随机出现不规则的缝隙。
即，有的金属柱本体30与介质层10之间会出现缝隙、有的金属柱本体30与介质层10之间不会出现缝隙。且缝隙有大有小、缝隙有宽有窄、缝隙有高有低、缝隙绕金属柱本体30一圈、缝隙存在于金属柱本体30部分侧面与介质层10之间、同一金属柱本体30与介质层10之间的缝隙是连续的，或者同一金属柱本体30与介质层10之间的缝隙是间断的等多种可能性。
当然，也有可能出现所有金属柱本体30与介质层10之间均具有缝隙的情况，图6A和图6B中的结构仅为一种示意。
其中，不对金属柱本体30的材料进行限定。可选的，金属柱本体30的材料为活性高易被氧化的材料。例如可以包括铜(Cu)、铝(Al)、钛(Ti)、锆(Zr)、铪(Hf)、钒(V)、钌(Ru)、钴(Co)、镍(Ni)、钯(Pd)、铂(Pt)、钨(W)、银(Ag)、金(Au)、鎶(CN)等材料。
S30、如图7A和图7B所示，对金属柱本体30进行化学处理，使金属柱本体30未与介质层10接触的侧面膨胀至与介质层10接触。
也就是说，对金属柱本体30进行处理，使金属柱本体30表面的金属发生化学反应。金属柱本体30表面的金属发生化学反应后体积会增大，使金属柱本体30膨胀至与介质层10接触，从而填充上述缝隙。
在一种可能的实现方式中，步骤S30包括：对金属柱本体30进行氧化处理，使金属柱本体30未与介质层10接触的侧面被氧化后，膨胀至与介质层10接触。
可以理解的是，对金属柱本体30进行氧化处理，仅会对金属柱本体30未与介质层10接触的表面进行氧化，金属柱本体30与介质层10接触的表面无法氧化。
参考图6B可知，金属柱本体30未与介质层10接触的外表面包括金属柱本体30远离第一导电图案21的顶面和金属柱本体30侧面中未与介质层10接触的部分。那么，如图7B所示，在对金属柱本体30进行氧化处理的过程中，实则仅会对金属柱本体30的顶面和至少部分侧面进行氧化，金属柱本体30与介质层10接触的侧面不会被氧化。
示例的，金属柱本体30的材料包括W，在金属柱本体30的侧面被氧化后，形成的金属氧化物为WOx(其中，0<x<4)。
关于对金属柱本体30进行氧化处理的方式，在一些实施例中，使用含氧气体对金属柱本体30进行氧化。
含氧气体，例如可以是氧气(O 2)、臭氧(O 3)或其混合气体等。根据氧化稳定性、金属柱本体30氧化的难易程度等因素的不同，可以选择等离子体处理的方式进行气态氧化，也可以选择无等离子体处理的方式进行气态氧化。
关于对金属柱本体30进行氧化处理的方式，在另一些实施例中，使用氧化剂溶液对金属柱本体30进行氧化。
氧化剂溶液，例如可以是过氧化氢(H 2O 2)等溶液。可以以浸润或冲洗等方式进行液态氧化处理。
关于对金属柱本体30进行氧化处理的方式，在又一些实施例中，通过将金属柱本体30久放于大气环境中，以对金属柱本体30进行氧化。
需要说明的是，采用化学工艺对金属柱本体30进行氧化后，形成的氧化层朝向金属柱本体30内部的表面平整(此处的平整不限定为绝对平整，也可以是有一定的波动幅度)。通过将金属柱本体30久放于大气环境中对金属柱本体30进行氧化后，形成的氧化层朝向金属柱本体30内部的表面，没有采用化学工艺对金属柱本体30进行氧化后，形成的氧化层朝向金属柱本体30内部的表面平整。
其中，可以根据选择的氧化工艺、氧化速率等因素来调整对金属柱本体30氧化处理(oxidation treatment)的时间，通过控制氧化处理的时间，可以控制金属柱本体30顶面被氧化的厚度。金属柱本体30顶面被氧化的厚度应结合后续去除金属柱本体30顶面被氧化部分的工艺来设定，以确保后续去除金属柱本体30顶面被氧化部分时可以将金属柱本体30顶面被氧化的部分完全去除。
在一些实施例中，金属柱本体30顶面被氧化后形成的金属氧化物的厚度(垂直于介质层10方向上的尺寸)小于10nm。
例如，金属柱本体30顶面被氧化后形成的金属氧化物的厚度为9nm、8nm、7nm、 6nm、5nm、4nm、3nm、2nm或1nm。
这样一来，采用现有的化学机械研磨工艺即可去除金属柱本体30顶面被氧化形成的金属氧化物，无需改变工艺和设备。
也就是说，金属柱本体30顶面被化学处理后，形成的金属化物的厚度小于10nm，以确保金属柱本体30顶面的金属化物在后续去除工艺中可以被完全去除，不影响待形成的第一导电柱的导电性能。
例如，金属柱本体30顶面被化学处理后形成的金属化物的厚度为9nm、8nm、7nm、6nm、5nm、4nm、3nm、2nm或1nm。
可以理解的是，无论金属柱本体30顶面被化学处理后形成的金属化物的厚度为多少，金属柱本体30侧面膨胀至与介质层10接触后，便不会再继续被化学处理了。
在一些实施例中，金属柱本体30侧面被氧化后形成的金属氧化物层的宽度(平行于介质层10方向上的尺寸)为0.5nm～5nm。
经过氧化工艺对金属柱本体30进行氧化后，金属柱本体30侧面被氧化后形成的金属氧化物层的厚度是可测的，金属氧化物层的厚度至少为0.5nm。根据选择性生长工艺所产生的缝隙的尺寸来看，通常情况下，金属氧化物层的厚度在5nm时，就可以填满上述缝隙。因此，将金属柱本体30侧面被氧化后形成的金属氧化物层的厚度控制在小于5nm，既能填满金属柱本体30与介质层10之间的缝隙，又可以使金属柱本体30侧面的金属氧化物层对金属柱本体30的电阻影响很小，几乎可以忽略。从而优化金属氧化物层的存在导致金属柱本体30电阻升高的问题。
也就是说，金属柱本体30侧面被化学处理后，形成的金属化合物层的宽度(平行于介质层10方向上的尺寸)为0.5nm～5nm，以确保填满金属柱本体30与介质层10之间的缝隙的同时，尽可能的降低金属氧化物层对待形成的第一导电柱电阻的影响。
在另一种可能的实现方式中，步骤S30包括：对金属柱本体30进行氮化处理，使金属柱本体30未与介质层10接触的侧面膨胀至与介质层10接触。
可以理解的是，对金属柱本体30进行氮化处理，仅会对金属柱本体30未与介质层10接触的表面进行氮化，金属柱本体30与介质层10接触的表面无法氮化。
参考图6B可知，金属柱本体30未与介质层10接触的外表面包括金属柱本体30远离第一导电图案21的顶面和金属柱本体30侧面中未与介质层10接触的部分。那么，如图7B所示，在对金属柱本体30进行氮化处理的过程中，实则仅会对金属柱本体30的顶面和至少部分侧面进行氮化，金属柱本体30与介质层10接触的侧面不会被氮化。
示例的，金属柱本体30的材料包括W，在金属柱本体30的侧面被氮化后，形成的金属氮化物为WNx(其中，0<x<4)。
关于对金属柱本体30进行氮化处理的方式，在一些实施例中，使用含氮气体对金属柱本体30进行氮化。
含氮气体，例如可以是氮气(N 2)、氨气(NH 3)或其混合气体等。根据氮化稳定性、金属柱本体30氮化的难易程度等因素的不同，可以选择等离子体处理的方式进行气态氮化，也可以选择无等离子体处理的方式进行气态氮化。
需要说明的是，采用化学工艺对金属柱本体30进行氮化后，形成的氮化层朝向金属柱本体30内部的表面平整(此处的平整不限定为绝对平整，也可以是有一定的波动 幅度)。
其中，可以根据选择的氮化工艺、氮化速率等因素来调整对金属柱本体30氮化处理的时间，通过控制氮化处理的时间，可以控制金属柱本体30顶面被氮化的厚度。金属柱本体30顶面被氮化的厚度应结合后续去除金属柱本体30顶面被氮化部分的工艺来设定，以确保后续去除金属柱本体30顶面被氮化部分时可以将金属柱本体30顶面被氮化的部分完全去除。
在一些实施例中，金属柱本体30顶面被氮化后形成的金属氮化物的厚度(垂直于介质层10方向上的尺寸)小于10nm。
这样一来，采用现有的化学机械研磨工艺即可去除金属柱本体30顶面被氮化形成的金属氮化物，无需改变工艺和设备。
在一些实施例中，金属柱本体30侧面被氮化后形成的金属氮化物层的宽度(平行于介质层10方向上的尺寸)为0.5nm～5nm。
这样一来，在确保金属氮化物层填满金属柱本体30与介质层10之间的缝隙的同时，尽可能的降低金属氮化物层对待形成的第一导电柱电阻的影响。
在又一种可能的实现方式中，步骤S30包括：对金属柱本体30进行氧化处理和氮化处理，使金属柱本体30未与介质层10接触的侧面被氧化和氮化后，膨胀至与介质层10接触。
可以理解的是，对金属柱本体30进行氧化处理和氮化处理，仅会对金属柱本体30未与介质层10接触的表面进行氧化和氮化，金属柱本体30与介质层10接触的表面无法氧化和氮化。
参考图6B可知，金属柱本体30未与介质层10接触的外表面包括金属柱本体30远离第一导电图案21的顶面和金属柱本体30侧面中未与介质层10接触的部分。那么，如图7B所示，在对金属柱本体30进行氧化处理和氮化处理的过程中，实则仅会对金属柱本体30的顶面和至少部分侧面进行氧化和氮化，金属柱本体30与介质层10接触的侧面不会被氧化和氮化。
示例的，金属柱本体30的材料包括W，在金属柱本体30的侧面被氧化和氮化后，形成的金属氮氧化物为WOxNy(其中，0<x<4，0<y<4)。
关于对金属柱本体30进行氧化处理和氮化处理的方式，在一些实施例中，使用含氧和氮的气体对金属柱本体30进行氧化和氮化。
含氧和氮的气体，例如可以是一氧化二氮(N 2O)、氮气和氧气混合气体等。根据氧化和氮化稳定性、金属柱本体30氧化和氮化的难易程度等因素的不同，可以选择等离子体处理的方式进行气态氧化和氮化，也可以选择无等离子体处理的方式进行气态氧化和氮化。
其中，可以根据选择的氧化和氮化工艺、氧化和氮化速率等因素来调整对金属柱本体30氧化处理和氮化处理的时间，通过控制氧化处理和氮化处理的时间，可以控制金属柱本体30顶面被氧化和氮化的厚度。金属柱本体30顶面被氧化和氮化的厚度应结合后续去除金属柱本体30顶面被氧化和氮化部分的工艺来设定，以确保后续去除金属柱本体30顶面被氧化和氮化部分时可以将金属柱本体30顶面被氧化和氮化的部分完全去除。
在一些实施例中，金属柱本体30顶面被氧化和氮化后形成的金属氮氧化物的厚度(垂直于介质层10方向上的尺寸)小于10nm。
这样一来，采用现有的化学机械研磨工艺即可去除金属柱本体30顶面被氧化和氮化形成的金属氮氧化物，无需改变工艺和设备。
在一些实施例中，金属柱本体30侧面被氧化和氮化后形成的金属氮氧化物层的宽度(平行于介质层10方向上的尺寸)为0.5nm～5nm。
这样一来，在确保金属氮氧化物层填满金属柱本体30与介质层10之间的缝隙的同时，尽可能的降低金属氮氧化物层对待形成的第一导电柱电阻的影响。
也就是说，对金属柱本体30进行化学处理时，可以对金属柱本体30进行氧化处理，也可以对金属柱本体30进行氮化处理，还可以对金属柱本体30进行氮氧化处理。当然，也可以是对金属柱本体30进行其他能使金属柱本体30膨胀的其他化学处理，本申请实施例对此不做限定。
S40、如图8A和图8B所示，去除金属柱本体30顶面被化学处理的部分，形成第一导电柱31。
其中，第一导电柱31包括金属柱311和金属化合物层312，金属化合物层312位于金属柱311的侧面。金属柱本体30未被化学处理的部分为金属柱311，金属柱本体30侧面被化学处理的部分为金属化合物层312。
那么，通过该工艺形成的金属柱311(例如W柱)所包括的金属和金属化合物层312(例如WOx层、WNx层或WOxNy层)所包括的金属相同，均为形成金属柱本体30时所采用的金属(例如W)。
应当理解的是，步骤S30中，若是对金属柱本体30进行氧化处理，那么金属化合物层312为金属氧化物层。步骤S30中，若是对金属柱本体30进行氮化处理，那么金属化合物层312为金属氮化物层。步骤S30中，若是对金属柱本体30进行氧化处理和氮化处理，那么金属化合物层312为金属氮氧化物层。
例如，可以采用化学机械研磨工艺，去除金属柱本体30顶面被化学处理的部分，那么，金属柱本体30顶面被化学处理后形成的金属化合物的厚度应小于化学机械研磨工艺除去的厚度。当然，也可以采用其他工艺去除金属柱本体30顶面被化学处理后形成的金属化合物，本申请实施例对此不做限定。
在一些实施例中，进行化学机械研磨工艺之前，在介质层10远离第一导电图案21的一侧覆盖顶部金属层，顶部金属层覆盖介质层10和导电柱本体30。
通过在介质层10表面设置顶部金属层，可减小多个导电柱本体30之间、导电柱本体30与介质层10之间的高度之比，从而调整研磨速度和高度，使金属柱本体30顶面被化学处理的部分被完全去除，但又不会对导电柱本体30研磨过多。
由于在芯片制备过程中，制备完金属柱本体30后，通常需要对金属柱本体30进行化学机械研磨，以使所有的金属柱本体30表面平齐，且与介质层10表面平齐。因此，采用化学机械研磨工艺去除金属柱本体30顶面被化学处理的部分，可以无需增加新的工艺，即可去除金属柱本体30顶面被化学处理的部分，工艺成本低，生产效率高。
请继续参考图8A和图8B，在执行步骤S40后，形成的第一金属柱31的侧面与介质层10接触，第一金属柱31与介质层10之间没有缝隙。此处释明的是，第一金属 柱31与介质层10接触，应当理解为，第一金属柱31的侧面全部与介质层10接触(或者贴合)。或者理解为，第一金属柱31的侧面全部与介质层10中对应的孔11的孔壁接触。
当然，在形成多个金属柱本体30的过程中，若出现特殊情况，某些金属柱本体30与介质层10之间的缝隙特别大，在执行步骤S30和S40后，形成的第一金属柱31与介质层10之间可能也依旧会存在缝隙，这也属于本申请实施例的保护范围。经过本申请实施例的制备方法形成的芯片，出现上述情况的可能性比较小，几乎不会出现。
金属化合物层312和金属柱311未被金属化合物层312覆盖的侧面与介质层10接触，根据金属化合物层312对金属柱311的覆盖程度的不同，第一导电柱31与介质层10的接触情况也不同。
另外，在第一导电图案21的表面生长金属柱本体30，那么，形成的第一金属柱31与第一导电图案21接触。
在一些实施例中，如图8B所示，图8B中视角左侧的金属柱311的部分侧面被金属化合物层312覆盖。
在这种情况下，第一导电柱31的侧面由两部分构成，一部分为金属柱311未被金属化合物层312覆盖的侧面，一部分为金属化合物层312的侧面。那么，第一导电柱31与介质层10接触，可以理解为，第一导电柱31通过金属柱311未被金属化合物层312覆盖的侧面和金属化合物层312的侧面与介质层10接触。
也就是说，金属柱311未被金属化合物层312覆盖的侧面所在区域直接与介质层10接触，金属柱311被金属化合物层312覆盖的侧面所在区域通过金属化合物层312与介质层10接触，以实现第一导电柱31的侧面的全部区域与介质层10接触。
在另一些实施例中，请继续参考图8B，图8B中视角右侧的金属柱311的全部侧面被金属化合物层312覆盖。
在这种情况下，金属柱31未被金属化合物层312覆盖的侧面不存在，金属化合物层312的侧面即为第一导电柱31的侧面。那么，第一导电柱31与介质层10接触，可以理解为，第一导电柱31通过金属化合物层312与介质层10接触，以实现第一导电柱31的侧面的全部区域与介质层10接触。
需要强调的是，第一导电柱31包括的金属化合物层312各位置处的厚度可以相同(例如图8B中视角左侧的第一导电柱31包括的金属化合物层312)，第一导电柱31包括的金属化合物层312各位置处的厚度也可以不相同(例如图8B中视角右侧的第一导电柱31包括的金属化合物层312)，本申请实施例对此不做限定。
另外，第一导电柱31包括的金属化合物层312各位置处的材料可以相同，第一导电柱31包括的金属化合物层312各位置处的材料也可以不相同。或者理解为，第一导电柱31包括的金属化合物层312各位置处的材料的含氧量和/或含氮量可以相同，第一导电柱31包括的金属氧化物层312各位置处的材料的含氧量和/或含氮量也可以不相同。
例如，金属化合物层312的材料为WOx(其中，0<x<4)，金属化合物层312各位置处WOx中x的值可能不同。或者，例如，金属化合物层312的材料为WNx(其中，0<x<4)，金属化合物层312各位置处WNx中x的值可能不同。或者，例如，金 属化合物层312的材料为WOxNy(其中，0<x<4，0<y<4)，金属化合物层312各位置处WOxNy中x和y的值可能不同。
在一些实施例中，请参考图8B，介质层10具有多个孔11，通过上述步骤在孔11中制备第一导电柱31后，芯片包括多个第一导电柱31。
那么，示例的，如图8B所示，多个第一导电柱31包括的多个金属化合物层312的宽度完全不同。
或者，示例的，多个第一导电柱31包括的多个金属化合物层312的宽度不完全相同。也可以理解为，多个第一导电柱31包括的多个金属化合物层312中，部分金属化合物层312的厚度相同，部分金属化合物层312的厚度不同。
或者，示例的，多个第一导电柱31包括的多个金属化合物层312的宽度完全相同。
由于选择性生长工艺形成金属柱本体30时，金属柱本体30与介质层10之间的缝隙的宽度是随机的，没有任何规律的。因此，最终形成的金属化合物层312的宽度也是没有任何限定的，可能会出现各种厚度、各种大小、各种形状、各种位置的金属化合物层312，本申请实施例对此不做限定。
示例的，多个第一导电柱31包括的多个金属化合物层312的材料完全不同。例如，金属化合物层312的材料为WOx，金属化合物层312各位置处WOx中x的值完全不同。
或者，示例的，多个第一导电柱31包括的多个金属化合物层312的材料不完全相同。例如，金属化合物层312的材料为WOx，金属化合物层312各位置处WOx中x的值不完全相同。
或者，示例的，多个第一导电柱31包括的多个金属化合物层312的材料完全相同。例如，金属化合物层312的材料为WOx，金属化合物层312各位置处WOx中x的值相同。
在金属柱本体30与介质层10之间的缝隙大小的不同、金属柱本体30化学处理方式的不同、化学处理时含氧量和/或含氮量的不同、化学处理时长的不同等因素的影响下，所形成的多个金属化合物层312的含氧量/或含氮量会有多种可能，本申请实施例对此不做限定。
请继续参考图8A和图8B，在一些实施例中，介质层10具有多个孔，步骤S20中采用选择性生长工艺形成多个金属柱本体30。形成第一导电柱31的同时，还形成第二导电柱32。
第二导电柱32与第一导电柱31的主要不同之处在于，第二导电柱32包括金属柱，不包括金属化合物层。
金属柱设置在介质层10的孔11内，或者理解为介质层10包裹在金属柱的外围。金属柱的侧面与介质层10中孔11的孔壁接触，第二导电柱32的底面与第一导电图案21接触。
其中，一个第一导电图案21可以仅与一个或多个第一导电柱31耦接，一个第一导电图案21也可以仅与一个或多个第二导电柱32耦接，一个第一导电图案21还可以与一个(或多个)第一导电柱31和一个(或多个)第二导电柱32耦接。
如图7A和图7B所示，在步骤S30中，所有的金属柱本体30未与介质层10接触 的外表面都会被化学处理。如图8A和图8B所示，在步骤S40后，所有金属柱本体30顶面的金属化合物会被去除。侧面未被化学处理的金属柱本体30，去除金属柱本体30顶面的金属化合物后，形成第二导电柱32。侧面被化学处理的金属柱本体30，去除金属柱本体30顶面的金属化合物后，形成第一导电柱31。那么，第一导电柱31包括的金属与第二导电柱32包括的金属相同，均与金属柱本体30包括的金属相同。
此处需要释明的是，由于形成多个金属柱本体30时，金属柱本体30与介质层10之间会随机出现不规则的缝隙。因此，金属化合物层312也是随机出现的，且不规则的。那么，第一导电柱31和第二导电柱32也是随机排布的，没有任何排布规律。甚至在同一批次的芯片中，第一导电柱31和第二导电柱32的分布也可能不相同。
S50、如图9A所示，在介质层10远离第一导电图案21一侧形成第二导电图案41，第二导电图案41与第一导电柱31耦接。
本申请实施例对第二导电图案41的形状、作用、材料不做限定，根据应用场景合理设置即可。
在一些实施例中，如图9B所示，第二导电图案41为第一重布线层40中包括的导电图案。也就是说，第二导电图案41为后段工艺制备的重布线层中的导电图案。
例如，第二导电图案41为第一重布线层40中最靠近介质层10的一层布线层中的导电图案。其中，第二导电图案41可以为柱状，第二导电图案41也可以为线条状，第二导电图案41还可以是其他形状，本申请实施例对此不做限定。
在一些实施例中，如图9B所示，芯片包括多个第二导电图案41，多个第二导电图案41中的部分第二导电图案41与第一导电柱31耦接，多个第二导电图案41中的部分第二导电图案41与第二导电柱32耦接。
其中，一个第二导电图案41可以仅与一个或多个第一导电柱31耦接，一个第二导电图案41也可以仅与一个或多个第二导电柱32耦接，一个第二导电图案41还可以与一个(或多个)第一导电柱31和一个(或多个)第二导电柱32耦接。
也就是说，第一导电柱31两端分别耦接有第一导电图案21和第二导电图案41，第二导电体32两端分别耦接有第一导电图案21和第二导电图案41。
本申请实施例提供的芯片的制备方法，通过选择性生长工艺形成金属柱本体30后，利用氧化处理和/或氮化处理等化学处理方式对金属柱本体30与介质层10之间的无规则缝隙缺陷进行自我修复。只要金属柱本体30与介质层10之间存在缝隙缺陷，通过化学处理自我修复后，金属柱本体30的体积会膨胀产生金属化合物，金属化合物会填充金属柱本体30与介质层10之间的缝隙缺陷，从而可以有效阻挡研磨液、清洗液或者刻蚀液等溶液对第一导电图案21的损伤。
下面对本申请实施例提供的芯片的结构进行示意说明，请参考图9B，本申请实施例提供的芯片包括第一导电柱31、介质层10、第一导电图案21以及第二导电图案41。
其中，第一导电柱31可以为一个，也可以为多个，图9B中以芯片包括多个第一导电柱为例进行示意。无论第一导电柱31为一个或者多个，介质层10包裹在每个第一导电柱31的外围，且与每个第一导电柱31的侧面接触。或者理解为每个第一导电柱31均设置在介质层10内，也沿介质层10的厚度方向贯穿介质层10。
另外，本申请实施例对第一导电柱31的形状不做限定，第一导电柱31的形状可 以是圆柱状、矩形柱状、或者长方形状等。
第一导电图案21和第二导电图案41位于第一导电柱31相对的两侧，或者理解为，第一导电图案21和第二导电图案41位于介质层10相对的两侧。第一导电图案21和第二导电图案41与第一导电柱31的两端对应耦接。
本申请实施例不对第一导电图案21和第二导电图案41的形状进行限定，第一导电图案21和第二导电图案41能够导电即可。
在一些实施例中，第一导电图案21与第一导电柱31接触耦接。第二导电图案41与第一导电柱31可以是接触耦接，第二导电图案41与第一导电柱31也可以是间接耦接。第一导电图案21和第二导电图案41在芯片中的具体结构，可以参考上述描述芯片的制备方法时，关于第一导电图案21和第二导电图案41的相关描述。
请继续参考图9B，第一导电柱31包括金属柱311和金属化合物层312，金属化合物层312位于金属柱311与介质层10之间，金属化合物层312覆盖金属柱311的至少部分侧面。第一导电柱31通过金属化合物层312，和，金属柱311未被金属化合物层312覆盖的侧面，与介质层10接触。
在一些实施例中，如图9B所示，图9B中视角左侧的金属柱311的部分侧面被金属化合物层312覆盖。那么，第一导电柱31与介质层10接触，可以理解为，第一导电柱31通过金属柱311未被金属化合物层312覆盖的侧面，和，金属化合物层312的侧面，与介质层10接触。
在另一些实施例中，请继续参考图9B，图9B中视角右侧的金属柱311的全部侧面被金属化合物层312覆盖。在这种情况下，金属柱311不存在未被金属化合物层312覆盖的侧面。那么，第一导电柱31与介质层10接触，可以理解为，第一导电柱31通过金属化合物层312与介质层10接触，以实现第一导电柱31的侧面的全部区域与介质层10接触。
需要说明的是，以金属柱311为矩形为例，金属柱311的部分侧面被金属化合物层312覆盖，并不限定为金属柱311的四个侧面中有一个或者多个侧面被金属化合物层312覆盖。如图9C所示，也可以是金属柱311的某一个侧面中的部分区域被金属化合物层312，部分区域未被金属化合物层312覆盖。当然，也有可能是其他情况，本申请实施例并未穷举。
在一些实施例中，金属柱311采用选择性生长工艺形成。这样一来，金属柱311从第一导电图案21的表面自下而上生长得到，可尽量避免金属柱311内部存在孔隙，且无需阻挡层等膜层。
在一些实施例中，金属化合物层312通过对金属柱311侧面表面进行化学处理后得到。那么，金属柱311包括的金属和金属化合物层312包括的金属相同。
通过将金属柱311包括的金属和金属化合物层312包括的金属设置为相同，可使金属柱311和金属化合物层312的材料特性相近，从而提高金属柱311和金属化合物层312的粘附性，降低因金属化合物层312与金属柱311分离而产生的缺陷。
或者，示例的，金属柱311包括的金属和金属化合物层312包括的金属不同。
可选的，金属化合物层312包括金属氧化物材料。例如，金属化合物层312通过对金属柱311侧面表面进行氧化处理后得到。
或者，可选的，金属化合物层312包括金属氮化物材料。例如，金属化合物层312通过对金属柱311侧面表面进行氮化处理后得到。
或者，可选的，金属化合物层312包括金属氧化物材料和金属氮化物材料。例如，金属化合物层312通过对金属柱311侧面表面进行氮化和氮化处理后得到。
或者，可选的，金属化合物层312包括金属氮氧化物材料。例如，金属化合物层312通过对金属柱311侧面表面进行氧化处理和氮化处理后得到。
或者，可选的，金属化合物层312包括金属氧化物材料和金属氮氧化物材料。例如，金属化合物层312通过对金属柱311侧面表面进行氧化处理和氮化处理后得到。
或者，可选的，金属化合物层312包括金属氮化物材料和金属氮氧化物材料。例如，金属化合物层312通过对金属柱311侧面表面进行氧化处理和氮化处理后得到。
或者，可选的，金属化合物层312包括金属氧化物材料、金属氮氧化物材料和金属氮氧化物材料。例如，金属化合物层312通过对金属柱311侧面表面进行氧化处理和氮化处理后得到。
在另一些实施例中，金属化合物层312通过独立工艺形成。
也就是说，本申请实施例对金属化合物层312的形成方式不做限定，上述示意的芯片的制备方法中形成金属化合物层312的方式仅为一种示意。
在一些实施例中，第一导电柱21包括的金属化合物层312的宽度为0.5nm～5nm。
将金属氧化物层312的宽度控制在小于5nm，既能填满金属柱本体30与介质层10之间的缝隙，又可以使金属氧化物层312对金属柱本体30的电阻影响很小，几乎可以忽略。从而优化金属氧化物层312的存在导致第一导电柱21电阻升高的问题。
其中，通过上述对芯片的制备方法的描述可知，在芯片包括多个第一导电柱31的情况下，多个第一导电柱31包括的金属化合物层312的含氧量和/或含氮量不限定为必须相同。多个第一导电柱31包括的金属化合物层312的宽度也不限定为必须相同，同一个第一导电柱31包括的金属化合物层312各位置处的宽度也不限定为必须相同。
请继续参考图9B，在一些实施例中，芯片还包括第二导电柱32，第二导电柱32为金属柱311，第二导电柱32不包括金属化合物层312。第二导电柱32与第一导电柱31平行设置，第二导电柱32的两端分别耦接有第一导电图案31和第二导电图案32。第二导电柱32设置在介质层10内，第二导电柱32沿介质层10的厚度方向贯穿介质层10，介质层10与金属柱311的侧面接触。
在一些实施例中，第一导电柱31和第二导电柱32的深宽比大于2:1。
例如，第一导电柱31和第二导电柱32的深宽比为3:1、4:1、5:1、6:1、7:1、8:1、9:1、10:1、11:1、12:1或者更大。第一导电柱31和第二导电柱32的深度，是指第一导电柱31和第二导电柱32的深沿垂直于介质层10方向上的尺寸。第一导电柱31和第二导电柱32的宽度，是指第一导电柱31和第二导电柱32沿平行于介质层10方向上的尺寸。
上述以第一导电图案21设置于第一导电柱31(或者第二导电柱32)与电子元件20之间为例进行示意。当然，上述第一导电柱31和第二导电柱32也可以直接与电子元件20耦接，而无需上述底部金属，那么电子元件20的导电部为第一导电图案21。
本申请实施例提供的芯片中，第一导电图案21和第二导电图案41通过第一导电 柱31耦接，或者，部分第一导电图案21和第二导电图案41通过第二导电柱32耦接。第一导电柱31和第二导电柱32均是直接与介质层10接触，没有阻挡层等膜层。这样一来，一方面没有阻挡层等膜层占用空间，可增大第一导电柱31和第二导电柱32的深宽比。另一方面，没有阻挡层等膜层影响第一导电柱31和第二导电柱32的电阻，可有效降低第一导电柱31和第二导电柱32的电阻。
在此基础上，第一导电柱31包括金属柱311和金属化合物层312，在基于工艺限制，形成的金属柱311与介质层10之间存在的缝隙缺陷可以通过金属化合物层312来填补。从而尽量避免第一导电柱31与介质层10之间的缝隙处因渗入酸性研磨液、清洗液或者刻蚀液等溶液，导致第一导电柱31底部的第一导电图案21损伤，最终导致芯片失效的问题。
另外，由于金属柱311与介质层10之间的缝隙很小，因此，位于上述缝隙内的金属化合物层312的体积也很小。因此，金属化合物层312对第一导电柱31的电阻的影响很小，几乎可以忽略，金属化合物层312的存在不会导致第一导电柱31的电阻升高。
在一些实施例中，本申请实施例还提供一种芯片，该芯片为对上述2D裸芯片封装后的芯片。
示例二
本申请实施例提供一种芯片，芯片为3D裸芯片。
如图10A所示，芯片包括依次层叠设置的第一集成电路模块50、第二重布线层60、第二集成电路模块70以及第三重布线层80。
第三重布线层80远离第二集成电路模块70的表面为芯片的有源面，第一集成电路模块50远离第二重布线层60的表面为芯片的非有源面。
其中，第一集成电路模块50和第二集成电路模量70可以理解为是通过前段制程制备形成的包括多个电路电子元件的结构。
本申请实施例对第一集成电路模块50用于实现的功能不做限定，那么，第一集成电路模块50包括的电子元件的结构也不做限定。例如，第一集成电路模块50包括多个电子元件，多个电子元件通过后续工艺制备的结构实现串联、并联的方式耦接，以实现某些功能。同理，本申请实施例对第二集成电路模块70用于实现的功能不做限定，那么，第二集成电路模块70包括的电子元件的结构也不做限定。例如，第二集成电路模块70包括多个电子元件，多个电子元件通过后续工艺制备的结构实现串联、并联的方式耦接，以实现某些功能。图10A中仅是以第一集成电路模块50包括的一个CMOS为例进行示意，以第二集成电路模块70包括的一个CMOS为例进行示意。
示例的，第一集成电路模块50为逻辑区的电路结构，第二集成电路模块70为存储区的电路结构，或者，第一集成电路模块50为逻辑区的电路结构，第二集成电路模块70为探测器的电路结构。
需要说明的是，芯片中可以包括通过中段制程制备形成的转接层。当然，根据需要，芯片中也可以不包括通过中段制程制备形成的转接层。
请继续参考图10A，第二重布线层60包括第一导电图案21，第一导电图案21与第一集成电路模块50耦接。例如，第二重布线层60中最靠近第二集成电路模块70的一层布线层包括第一导电图案21，第一导电图案21与第一集成电路模块50中电子 元件的电极(例如源极S、漏极D、栅极D)接触耦接。
第三重布线层80包括第二导电图案41，例如，第三重布线层80中最靠近第二集成电路模块70的一层布线层包括第二导电图案41。第一导电柱31贯穿第二集成电路模块70，第一导电柱31通过转接层中的导电柱与第二导电图案41耦接(在芯片不包括转接层的情况下，第一导电柱31可以直接与第二导电图案41接触耦接)。第三重布线层80还与第二集成电路模块70耦接。
也就是说，本示例示意的芯片，包括至少两个集成电路模块，图10A中仅是以第一集成电路模块50和第二集成电路模块70为例进行示意。其中，如图10B所示，从宏观上来看，芯片有源面的信号依次经第三重布线层80、第一导电柱31、第二重布线层60传输至第一集成电路模块70。芯片有源面的信号还经第三重布线层80传输至第二集成电路模块70。
请继续参考图10A，第一导电柱31包括金属柱311和金属化合物层312，金属化合物层312位于金属柱311与介质层10之间，金属化合物层312覆盖金属柱311的至少部分侧面，金属化合物层312和金属柱311未被金属化合物层312覆盖的侧面与介质层10接触。
在一些实施例中，芯片还包括第二导电柱32，第二导电柱32包括金属柱311，不包括金属化合物层312。
其中，第一导电柱31和第二导电柱32的结构，可以与示例一中第一导电柱31和第二导电柱32的结构相同，可以参考示例一中的相关描述，此处不再赘述。
此处需要强调的是，示例一中的介质层10的材料为绝缘材料，本示例中第一导电柱31和第二导电柱32贯穿第二集成电路模块70，因此，包裹在第一导电柱31和第二导电柱32外围的介质层10为第二集成电路模块70的衬底。也就是说，介质层10的材料为半导体。
下面，对示意一种本申请实施例提供的芯片的制备方法，包括：
S10、如图11A所示，提供介质层10和位于介质层10一侧的第一导电图案21。
本申请实施例对图11A所示结构的制备方法不做限定，例如可以先通过前段制程、中段制程以及后段制程形成包括第一集成电路模块50、转接层、第二布线层60的结构，然后在前述结构上再通过前段制程形成第二集成电路模块70。第二集成电路模块70包括介质层10，第二布线层60包括第一导电图案21。
其中，如图11A所示，介质层10包括孔11，孔11位于第一导电图案21上方，孔11与第一导电图案21接触。
S20、如图11B所示，采用选择性生长工艺，在孔11内从第一导电图案21的表面开始，自下而上生长形成金属柱本体30。
S30、如图11C所示，对金属柱本体30进行化学处理，使金属柱本体30未与介质层10接触的侧面膨胀至与介质层10接触。
S40、如图11D所示，去除金属柱本体30顶面被化学处理的部分，形成第一导电柱31。
其中，步骤S20、S30以及S40可以参考示例一中的相关描述，此处不再赘述。
S50、如图10A所示，在介质层10远离第一导电图案21一侧形成第二导电图案 41，第二导电图案41与第一导电柱31耦接。
随着电子设备性能和集成度的提高，单一功能的芯片已经无法满足需求，3D裸芯片逐渐成为未来发展趋势。但是就会面临第一导电柱31和第二导电柱32的深宽比较大的问题。因此，本申请实施例提供的芯片中第一导电柱31和第二导电柱32均是直接与介质层10接触，没有阻挡层等膜层。这样一来，一方面没有阻挡层等膜层占用空间，第一导电柱31和第二导电柱32的深宽比可以比较大，以满足3D裸芯片的需求。另一方面，没有阻挡层等膜层影响第一导电柱31和第二导电柱32的电阻，可有效降低第一导电柱31和第二导电柱32的电阻。
在此基础上，第一导电柱31包括金属柱311和金属化合物层312，在基于工艺限制，形成的金属柱311与介质层10之间存在的缝隙缺陷可以通过金属化合物层312来填补。从而尽量避免第一导电柱31与介质层10之间的缝隙处因渗入酸性研磨液、清洗液或者刻蚀液等溶液，导致第一导电柱31底部的第一导电图案21损伤，最终导致芯片失效的问题。
另外，由于金属柱311与介质层10之间的缝隙很小，因此，位于上述缝隙内的金属化合物层312的体积也很小。因此，金属化合物层312对第一导电柱31的电阻的影响很小，几乎可以忽略，金属化合物层312的存在不会导致第一导电柱31的电阻升高。
在一些实施例中，本申请实施例还提供一种芯片，该芯片为对本示例中的上述3D裸芯片封装后的芯片。
示例三
本申请实施例提供一种芯片，芯片为封装后的芯片。
在一些实施例中，如图12A所示，芯片包括第一裸芯片91、第二裸芯片92以及第四布线层99。
第一裸芯片91的焊盘为第一导电图案21，第一导电柱31从第一裸芯片91的非有源面贯穿至焊盘背面。第四重布线层99包括第二导电图案41，第二导电图案41与第一导电柱31耦接。第二裸芯片92位于第四重布线层99远离第一裸芯片91一侧，第二裸芯片92与第四重布线层99耦接。示例的，如图12A所示，第二裸芯片92通过焊球与第四重布线层99键合耦接。
第一裸芯片91的信号经焊盘传输至与第一裸芯片91键合的基板(图12A中未示意出)中。第二裸芯片92的信号传输至第四重布线层99，并经第一导电柱31传输至第一裸芯片91的焊盘，然后传输至与第一裸芯片91键合的基板中。
本申请实施例对第一裸芯片91和第二裸芯片92的结构不做限定，根据需要合理设置即可。
请继续参考图12A，第一导电柱31包括金属柱311和金属化合物层312，金属化合物层312位于金属柱311与介质层10之间，金属化合物层312覆盖金属柱311的至少部分侧面，金属化合物层312和金属柱311未被金属化合物层312覆盖的侧面与介质层10接触。
在一些实施例中，芯片还包括第二导电柱32，第二导电柱32包括金属柱311，不包括金属化合物层312。
其中，第一导电柱31和第二导电柱32的结构，可以与示例一中第一导电柱31 和第二导电柱32的结构相同，可以参考示例一中的相关描述，此处不再赘述。
此处需要强调的是，本示例中第一导电柱31和第二导电柱32从第一裸芯片91的非有源面贯穿至焊盘背面。因此，如图12B所示，本示例中的介质层10包括前段制程形成的集成电路模块中的衬底、中段制程形成的转接层中的绝缘层、后段制程形成的重布线层中的多层绝缘层。介质层10中的孔11位于第一裸芯片91中焊盘的上方。
下面，对示意一种本申请实施例提供的芯片的制备方法，包括：
S10、如图12B所示，提供介质层10和位于介质层10一侧的第一导电图案21。
图12B所示的结构，例如可以先通过前段制程、中段制程和后段制程形成裸芯片，然后采用开孔工艺形成孔11，以得到本申请中的第一裸芯片91。
S20、如图12C所示，采用选择性生长工艺，在孔11内从第一导电图案21的表面开始，自下而上生长形成金属柱本体30。
S30、如图12D所示，对金属柱本体30进行化学处理，使金属柱本体30未与介质层10接触的侧面膨胀至与介质层10接触。
S40、如图12E所示，去除金属柱本体30顶面被化学处理的部分，形成第一导电柱31。
其中，步骤S20、S30以及S40可以参考示例一中的相关描述，此处不再赘述。
S50、如图12F所示，在介质层10远离第一导电图案21一侧形成第二导电图案41，第二导电图案41与第一导电柱31耦接。
示例的，在介质层10远离第一导电图案21一侧形成第四重布线层99，第四重布线层99包括第二导电图案41。
S60、如图12A所示，将第二裸芯片92与第四重布线层99键合耦接。
在另一些实施例中，如图13所示，芯片包括第一裸芯片91、第二裸芯片92以及焊点。
第一裸芯片91的焊盘为第一导电图案21，第一导电柱31从第一裸芯片91的非有源面贯穿至焊盘背面。焊点为第二导电图案41，第二导电图案41与第一导电柱31耦接。
第一裸芯片91的信号经焊盘传输至第一导电柱31，然后传输至焊点(第二导电图案41)，然后传输至与第一裸芯片91键合的基板(图13中未示意出)中。
请继续参考图13，第一导电柱31包括金属柱311和金属化合物层312，金属化合物层312位于金属柱311与介质层10之间，金属化合物层312覆盖金属柱311的至少部分侧面，金属化合物层312和金属柱311未被金属化合物层312覆盖的侧面与介质层10接触。
在一些实施例中，芯片还包括第二导电柱32，第二导电柱32包括金属柱311，不包括金属化合物层312。第二导电柱32两端分别与第一裸芯片91的焊盘和第一裸芯片91非有源面的焊点(第二导电图案41)耦接。
其中，第一导电柱31和第二导电柱32的结构，可以与示例一中第一导电柱31和第二导电柱32的结构相同，可以参考示例一中的相关描述，此处不再赘述。
此处需要强调的是，本示例中第一导电柱31和第二导电柱32从第一裸芯片91的非有源面贯穿至焊盘背面。因此，如图12B所示，本示例中的介质层10包括前段 制程形成的集成电路模块中的衬底、中段制程形成的转接层中的绝缘层、后段制程形成的重布线层中的多层绝缘层。介质层10中的孔11位于第一裸芯片91中焊盘的上方。
下面，对示意一种本申请实施例提供的芯片的制备方法，包括：
S10-S40与本示例中芯片包括第四重布线层99时芯片的制备方法相同，此处不再赘述。
S50、如图12F所示，在介质层10远离第一导电图案21一侧形成第二导电图案41，第二导电图案41与第一导电柱31耦接。
示例的，第二导电图案41为位于第一裸芯片91非有源面上的焊点。例如，第二导电图案41为焊球、微凸点等结构。
S60、将第二裸芯片92与第一裸芯片91的焊盘键合耦接。
其中，步骤S60还可以在步骤S10之前，或者在其他步骤之后，本申请实施例不限定为步骤S60在S50之后。
随着电子设备性能和集成度的提高，单一功能的芯片已经无法满足需求，3D堆叠封装芯片逐渐成为未来发展趋势。但是就会面临第一导电柱31和第二导电柱32的深宽比较大的问题。因此，本申请实施例提供的芯片基于第一导电柱31和第二导电柱32的结构和制备方法，可以适用于对深宽比要求较高的芯片中。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。

Claims (20)

  1. 一种芯片，其特征在于，包括：
    第一导电柱和介质层，所述第一导电柱设置在所述介质层内，且沿所述介质层的厚度方向贯穿所述介质层；
    第一导电图案和第二导电图案，位于所述第一导电柱相对的两侧；所述第一导电柱与所述第一导电图案和所述第二导电图案对应耦接；
    其中，所述第一导电柱包括金属柱和金属化合物层，所述金属化合物层位于所述金属柱与所述介质层之间、覆盖所述金属柱的至少部分侧面；所述金属化合物层与所述介质层接触，所述金属柱未被所述金属化合物层覆盖的侧面也与所述介质层接触。
  2. 根据权利要求1所述的芯片，其特征在于，所述金属柱采用选择性生长工艺形成。
  3. 根据权利要求1或2所述的芯片，其特征在于，所述金属化合物层包括金属氧化物材料、金属氮化物材料或者金属氮氧化物材料中的至少一种。
  4. 根据权利要求1或2所述的芯片，其特征在于，所述金属化合物层通过对所述金属柱侧面表面进行氧化处理和/或氮化处理后得到。
  5. 根据权利要求1-4任一项所述的芯片，其特征在于，沿平行于所述介质层的方向，所述金属化合物层的宽度为0.5nm～5nm。
  6. 根据权利要求1-5任一项所述的芯片，其特征在于，所述第一导电图案的材料包括金属，所述第一导电柱与所述第一导电图案接触。
  7. 根据权利要求1-6任一项所述的芯片，其特征在于，所述芯片包括电子元件和第一重布线层；所述第一导电图案设置在所述第一导电柱与所述电子元件之间，所述第一重布线层包括所述第二导电图案。
  8. 根据权利要求1-6任一项所述的芯片，其特征在于，所述芯片包括依次层叠设置的第一集成电路模块、第二重布线层、第二集成电路模块以及第三重布线层；
    所述第二重布线层包括所述第一导电图案，所述第一导电图案与所述第一集成电路模块耦接；所述第一导电柱贯穿所述第二集成电路模块，所述第三重布线层包括所述第二导电图案；所述第三重布线层还与所述第二集成电路模块耦接。
  9. 根据权利要求1-6任一项所述的芯片，其特征在于，所述芯片包括裸芯片；
    所述裸芯片的焊盘为所述第一导电图案；所述第一导电柱从所述裸芯片的非有源面贯穿至所述焊盘背面；
    所述芯片还包括第四重布线层，所述第四重布线层包括所述第二导电图案。
  10. 根据权利要求1-6任一项所述的芯片，其特征在于，所述芯片包括裸芯片；
    所述裸芯片的焊盘为所述第一导电图案；所述第一导电柱从所述裸芯片的非有源面贯穿至所述焊盘背面；
    所述第二导电图案为位于所述裸芯片非有源面上的焊点。
  11. 根据权利要求1-10任一项所述的芯片，其特征在于，所述芯片包括多个所述第一导电柱，多个所述第一导电柱包括的多个所述金属化合物层的含氧量、含氮量或者宽度不完全相同。
  12. 根据权利要求1-11任一项所述的芯片，其特征在于，所述芯片还包括第二导 电柱，所述第二导电柱为所述金属柱；所述金属柱设置在所述介质层内，且沿所述介质层的厚度方向贯穿所述介质层，所述金属柱的侧面与所述介质层接触。
  13. 根据权利要求1-12任一项所述的芯片，其特征在于，所述第一导电柱的深宽比大于2:1。
  14. 一种电子设备，其特征在于，包括权利要求1-13任一项所述的芯片和电路板，所述芯片设置在所述电路板上。
  15. 一种芯片的制备方法，其特征在于，包括：
    提供介质层和位于所述第一中段介质层侧的第一导电图案；所述介质层具有孔，所述孔位于所述第一导电图案上方；
    采用选择性生长工艺，在所述孔内从所述第一导电图案的表面开始，自下而上生长形成金属柱本体；
    对所述金属柱本体进行化学处理，使所述金属柱本体未与所述介质层接触的侧面膨胀至与所述介质层接触；
    去除所述金属柱本体顶面被化学处理的部分，形成第一导电柱；所述第一导电柱包括金属柱和金属化合物层，所述金属柱本体未被化学处理的部分为所述金属柱，所述金属柱本体侧面被化学处理的部分为所述金属化合物层；所述金属化合物层与所述介质层接触，所述金属柱未被所述金属化合物层覆盖的侧面也与所述介质层接触；
    在所述介质层远离所述第一导电图案一侧形成第二导电图案，所述第二导电图案与所述第一导电柱耦接。
  16. 根据权利要求15所述的芯片的制备方法，其特征在于，对所述金属柱本体进行化学处理，包括：
    对所述金属柱本体进行氧化处理；
    和/或，
    对所述金属柱本体进行氮化处理。
  17. 根据权利要求16所述的芯片的制备方法，其特征在于，对所述金属柱本体进行氧化处理，包括：使用含氧气或氧化剂溶液体对所述金属柱本体进行氧化；
    或者，
    对所述金属柱本体进行氮化处理，包括：使用含氮气体对所述金属柱本体进行氮化；
    或者，
    对所述金属柱本体进行氧化处理和氮化处理，包括：使用含氧和氮的气体对所述金属柱本体进行氧化和氮化。
  18. 根据权利要求15-17任一项所述的芯片的制备方法，其特征在于，所述金属柱本体被化学处理后，顶面形成的金属化合物的厚度小于10nm。
  19. 根据权利要求15-18任一项所述的芯片的制备方法，其特征在于，沿平行于所述介质层的方向，所述金属化合物层的宽度为0.5nm～5nm。
  20. 根据权利要求15-19任一项所述的芯片的制备方法，其特征在于，所述介质层具有多个孔，采用选择性生长工艺形成多个所述金属柱本体；形成所述第一导电柱的同时，还形成第二导电柱；
    侧面与所述介质层接触的所述金属柱本体，在去除所述金属柱本体顶面被化学处理的部分后，形成所述第二导电柱，所述第二导电柱为所述金属柱。
PCT/CN2022/088028 2022-04-20 2022-04-20 芯片及其制备方法、电子设备 WO2023201598A1 (zh)

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