WO2024001801A1 - 集成电路及其制备方法、电子设备 - Google Patents

集成电路及其制备方法、电子设备 Download PDF

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Publication number
WO2024001801A1
WO2024001801A1 PCT/CN2023/100295 CN2023100295W WO2024001801A1 WO 2024001801 A1 WO2024001801 A1 WO 2024001801A1 CN 2023100295 W CN2023100295 W CN 2023100295W WO 2024001801 A1 WO2024001801 A1 WO 2024001801A1
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WIPO (PCT)
Prior art keywords
gate
substrate
sacrificial
trench
layer
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PCT/CN2023/100295
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English (en)
French (fr)
Inventor
张峰溢
吴耀政
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华为技术有限公司
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Publication of WO2024001801A1 publication Critical patent/WO2024001801A1/zh

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/7855—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with at least two independent gates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

Definitions

  • the present application relates to the field of semiconductor technology, and in particular to an integrated circuit, a preparation method thereof, and electronic equipment.
  • Fin Field-Effect Transistor Fin Field-Effect Transistor
  • HKMG high-k metal gate
  • the polycrystalline gate preparation process may include a polycrystalline gate line (Poly Line, POL) process, and a polycrystalline gate cutting (Poly Cut, POC) process, that is, the sacrificial gate is formed first, and then the gate cutting structure is formed. , the gate cutting structure can be used to cut the sacrificial gate.
  • a polycrystalline gate line Poly Line, POL
  • a polycrystalline gate cutting Poly Cut, POC
  • the preparation process of the metal gate may include a replacement metal gate (RMG) process and a multi-work function (MWF) process, that is, the sacrificial gate is first removed to form a gate line trench, and then the gate line is formed.
  • RMG replacement metal gate
  • MVF multi-work function
  • the sacrificial gate is first removed to form a gate line trench, and then the gate line is formed.
  • a work function layer and a mask layer are formed in the line trench, and the work function layer and the mask layer will cover the gate cutting structure. Then the parts of the work function layer and the mask layer located in the target area are removed, and finally the work function layer and the mask layer are removed in the gate line trench.
  • Conductive material is deposited within to form gate lines.
  • the opening size of the gate cutting trench is larger than the bottom size.
  • the gate formed The cut-off structure has an approximately inverse cone-shaped morphology, which makes it easy for the mask layer material to remain at the bottom angle near the gate cut-off structure during the removal of the mask layer, thus causing the work function layer material to remain. Therefore, an over-etching process needs to be used to completely remove the remaining mask layer material to prevent the work function layer material from remaining. However, the over-etching process can easily damage the fins of the transistor, resulting in device failure. Yield is reduced.
  • Some embodiments of the present application provide an integrated circuit, a manufacturing method thereof, and electronic equipment, aiming to improve the yield of integrated circuit devices.
  • an integrated circuit may be a wafer or a chip.
  • the integrated circuit may be a bare chip or a packaged chip.
  • a chip may include one or more bare chips.
  • the integrated circuit can be applied in logic devices (such as processors, controllers, sensors, etc.) and in storage devices (such as external memory, internal memory, etc.).
  • the integrated circuit includes a substrate, fins, gate lines and gate cut-off structures, wherein the fins are disposed on the substrate and extend along a first direction parallel to the substrate.
  • the gate line extends along a second direction parallel to the substrate, the second direction intersects the first direction, and the gate line spans the fin.
  • the gate cutting structure extends along the first direction and cuts the gate line into a plurality of sub-gate lines.
  • the gate cutting structure includes a first part and a second part connected, and the second part is located at a side of the first part away from the substrate. side.
  • the first part includes a first end surface connected to the second part
  • the second part includes a second end surface connected to the first part, an orthographic projection of the second end surface on the substrate, and an orthographic projection of the first end surface on the substrate.
  • the cross-sectional size of the second end face is smaller than or equal to the cross-sectional size of the first end face.
  • the cross section of the first part along the reference plane changes from small to large in the second direction, and the reference plane is perpendicular to the substrate and perpendicular to the first direction.
  • the integrated circuit further includes a dielectric layer disposed between the substrate and the gate line.
  • the side surface of the first part close to the sub-gate line and the section away from the edge of the second part are the same as the dielectric layer away from the substrate.
  • the angle between the side surfaces is an obtuse angle.
  • the cross-sectional shape of the first part along the reference plane is trapezoidal or tapered, or the side of the first part close to the sub-grid line is an arc surface convex toward the sub-grid line.
  • connection between the first portion and the second portion transitions smoothly.
  • the height of the first portion is less than or equal to the height of the second portion.
  • the gate cutting structure further includes a third part, the third part is located on a side of the first part close to the substrate and is connected to the first part, and the third part is located in the dielectric layer.
  • the third part of the gate cutting structure is embedded in the dielectric layer, ensuring that the gate cutting structure penetrates the gate line in the vertical direction to cut the gate line into multiple sub-gate lines.
  • the first part includes a third end surface connected to the third part, and the orthographic projection of the third part on the substrate is located within the range of the orthographic projection of the third end surface on the substrate, that is, the third part
  • the cross-sectional size is less than or equal to the cross-sectional size of the third end face.
  • the first portion has apertures therein, the apertures extending in the first direction.
  • the aperture is conducive to reducing the parasitic capacitance generated between the two sub-gate lines adjacent to the gate cutting structure where the aperture is located, thereby reducing the signal interference between the two adjacent sub-gate lines.
  • the integrated circuit includes a first device region configured to house a P-type transistor and a second device region configured to house an N-type transistor.
  • the integrated circuit also includes a work function layer.
  • the work function layer is disposed between the sub-gate line and the fin, and between the sub-gate line and the gate cut-off structure.
  • the thickness of the portion of the work function layer located in the first device region is greater than the work function layer.
  • the integrated circuit provided by some embodiments of the present application has a structural design of the gate cutting structure.
  • the cross-sectional shape of the first part of the gate cutting structure is a trapezoid or a cone, and the side surfaces of the first part are arcs protruding toward the sub-grid lines. surface, and the included angle is an obtuse angle (greater than 90°), so that there is no indentation in the included angle area.
  • the part of the work function film close to the included angle area can be removed cleanly to form a work function layer. Improve the yield of integrated circuit devices.
  • the part of the work function film close to the connection can be completely removed to form a work function layer, thereby improving the device yield of the integrated circuit.
  • a method for manufacturing an integrated circuit includes: forming fins on a substrate, the fins extending in a first direction parallel to the substrate.
  • a dielectric film is formed, covering the substrate and fins.
  • a sacrificial layer is formed on the dielectric film, the sacrificial layer includes a sacrificial gate, the sacrificial gate extends along a second direction parallel to the substrate, the second direction intersects the first direction, and the sacrificial gate spans the fin.
  • a gate cutting trench is formed in the sacrificial layer, and the gate cutting trench extends along the first direction.
  • a gate cutting structure is formed in the gate cutting trench.
  • forming the gate cut-off trench in the sacrificial layer includes forming a preformed trench in the sacrificial layer.
  • a protective layer is formed on the side wall of the prefabricated trench, and the protective layer exposes the bottom of the prefabricated trench.
  • the sacrificial gate is etched downward to the dielectric film, and the sacrificial gate is etched laterally to form a first cavity.
  • the first cavity includes a first opening connected to the prefabricated trench
  • the prefabricated trench includes a second opening connected to the first cavity
  • the orthographic projection of the second opening on the substrate is located at the position of the first opening on the substrate. within the range of the orthographic projection.
  • the cross-sectional size of the second opening of the prefabricated trench is less than or equal to the first
  • the cross-sectional size of the first opening of the cavity is such that the cross-sectional size of the second end surface of the second part is smaller than or equal to the cross-sectional size of the first end surface of the first part.
  • the depth of the first cavity along the third direction is set to be less than or equal to the depth along the edge of the prefabricated trench.
  • the depth in the third direction can simplify the preparation process and save process costs, so that the height of the first part is less than or equal to the height of the second part.
  • etching the sacrificial gate down to the dielectric film and etching the sacrificial gate laterally to form the first cavity includes: performing a first lateral etching on the sacrificial gate through the bottom of the prefabricated trench. . Etch the sacrificial gate down to the dielectric film. Perform a second lateral etch on the sacrificial gate.
  • the first lateral etching of the sacrificial gate removes the sacrificial gate that is in contact with the bottom of the protective layer so that the bottom of the protective layer is not in contact with the sacrificial gate. This step can ensure that the subsequently formed gate In the cut-off structure, the connection between the first part and the second part has a smooth transition.
  • a second lateral etching is performed on the sacrificial gate, so that the cross-sectional shape of the first cavity is trapezoidal or tapered, so that the cross-sectional shape of the first part is trapezoidal or tapered.
  • performing the first lateral etching on the sacrificial gate includes: using a dry etching process to perform the first lateral etching on the sacrificial gate.
  • the etching selectivity ratio of the etching gas used in the dry etching process to the sacrificial gate is greater than the etching selectivity ratio of the etching gas to the protective layer.
  • the above dry etching process is used to etch the sacrificial gate vertically downward along the third direction.
  • the etching by-products carry high-energy ions and cause lateral backsplash, which will etch the sacrificial gate laterally. .
  • the method further includes: etching the dielectric film to form a second cavity, and the second cavity exposes the sacrificial gate.
  • the gate is close to the surface of the side of the dielectric film.
  • the surface of the sacrificial gate close to the dielectric film is exposed through the second cavity, so that during the second lateral etching of the sacrificial gate, the exposure of the sacrificial gate to the second cavity can be improved.
  • the etching rate of the part makes the cross-sectional shape of the first cavity trapezoidal or tapered, so that the cross-sectional shape of the first part becomes trapezoidal or tapered.
  • forming a protective layer on the sidewalls of the prefabricated trench includes: forming a protective film that covers a side of the sacrificial layer away from the substrate, as well as the sidewalls and bottom of the prefabricated trench. Remove the portion of the protective film covering the bottom of the prefabricated trench to form a protective layer.
  • the protective layer can protect the sidewalls of the prefabricated trench and prevent subsequent etching processes from causing damage to the sidewalls of the prefabricated trench.
  • forming the gate cut-off structure in the gate cut-off trench includes: depositing a dielectric material in the gate cut-off trench and on a surface of the protective layer away from the substrate. Remove the dielectric material located on the surface of the protective layer away from the substrate, and the portion of the protective layer covering the surface of the sacrificial layer away from the substrate, the portion of the dielectric material remaining and the protection The portion of the layer covering the sidewalls of the preformed trench forms a gate cutout structure.
  • the deposition rate of the dielectric material on the sidewalls of the gate cutting trench is controlled to be greater than or equal to the deposition rate of the dielectric material on the bottom of the gate cutting trench, so that the gate cutting trench When the top of the gate is sealed by the dielectric material, the deposition amount of the dielectric material at the bottom of the gate cut-off trench is insufficient, thereby forming a void at the bottom of the gate cut-off trench.
  • the dielectric material located on the surface of the protective layer away from the substrate and the portion of the protective layer covering the surface of the sacrificial layer away from the substrate are removed to expose the top surface of the sacrificial layer to facilitate the subsequent metal gate replacement process and multiple functions. Function craft.
  • the method further includes: removing the sacrificial gate in the sacrificial layer to form a gate line trench in the insulating layer.
  • the gate line trench Through the gate line trench, the portion of the dielectric film covering the fins is removed to form a dielectric layer.
  • a work function layer is formed in the gate line trench, and the thickness of the part of the work function layer located in the first device region is greater than the thickness of the part of the work function layer located in the second device region.
  • Conductive material is filled in the gate line trench to form a gate line.
  • Some embodiments of the present application provide a preparation method.
  • the gate cut-off structure is prepared using this method.
  • the cross-sectional shape of the first part is a trapezoid or a cone, or the side surfaces of the first part are convex toward the sub-grid lines.
  • the arc surface has an obtuse angle, so that there is no indentation in the angle area, and the connection between the first part and the second part of the gate cutting structure has a smooth transition.
  • the parts of the work function film close to the angles and connections are easily removed to form the work function layer, thereby improving the device yield of the integrated circuit.
  • an electronic device is provided.
  • the electronic device is, for example, a consumer electronic product, a household electronic product, a vehicle-mounted electronic product, a financial terminal product, or a communication electronic product.
  • the electronic device includes a circuit board and the integrated circuit described in any of the above embodiments, and the integrated circuit is electrically connected to the circuit board.
  • Figure 1 is a structural diagram of an electronic device according to some embodiments.
  • Figures 2A to 2G are diagrams of steps for preparing integrated circuits in related technologies
  • Figure 3 is a structural diagram of an integrated circuit according to some embodiments.
  • Figure 4 is a cross-sectional view of the integrated circuit in Figure 3 along the reference plane P;
  • Figure 5 is a partial enlarged view of the integrated circuit in Figure 4 at position M;
  • Figures 6A to 6E are flow charts of a polycrystalline gate line process and a polycrystalline gate cutting process according to some embodiments
  • FIG. 7A to 7N are step diagrams of the polysilicon gate line process and the polysilicon gate cutting process according to some embodiments;
  • Figure 8 is a flow diagram of a replacement metal gate process and a multiple work function process according to some embodiments.
  • 9A-9H are step diagrams of a replacement metal gate process and a multiple work function process according to some embodiments.
  • first and second are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the quantity of indicated technical features. Therefore, features defined as “first” and “second” may explicitly or implicitly include one or more of these features. In the description of the embodiments of this application, unless otherwise specified, "plurality” means two or more.
  • connection and its derivatives may be used.
  • some embodiments may be described using the term “connected” to indicate that two or more components are in direct physical or electrical contact with each other.
  • a and/or B includes the following three combinations: A only, B only, and a combination of A and B.
  • Example embodiments are described herein with reference to cross-sectional illustrations and/or plan views that are idealized illustrations.
  • the thickness of layers and regions are exaggerated for clarity. Accordingly, variations from the shapes in the drawings due, for example, to manufacturing techniques and/or tolerances are contemplated.
  • example embodiments should not be construed as limited to the shapes of regions illustrated herein but are to include deviations in shapes that result from, for example, manufacturing. For example, an etched area shown as a rectangle will typically have curved features. Accordingly, the regions shown in the figures are schematic in nature and their shapes are not intended to illustrate the actual shapes of regions of the device and are not intended to limit the scope of the exemplary embodiments.
  • the electronic equipment is, for example, consumer electronic products, household electronic products, vehicle-mounted electronic products, financial terminal products, and communication electronic products.
  • consumer electronic products such as mobile phones, tablet computers, notebook computers, e-readers, personal computers, PC), personal digital assistant (Personal Digital Assistant, PDA), desktop monitor, smart wearable products (such as smart watches, smart bracelets), virtual reality (Virtual Reality, VR) terminal equipment, augmented reality (Augmented Reality, AR) Terminal equipment, drones, etc.
  • Home electronic products include smart door locks, TVs, remote controls, refrigerators, rechargeable small household appliances (such as soymilk machines, sweeping robots), etc.
  • Vehicle-mounted electronic products include vehicle navigation systems, vehicle-mounted high-density digital video discs, etc.
  • Financial terminal products include automatic teller machines, self-service terminals, etc.
  • Communication electronic products include communication equipment such as servers, memories, and base stations.
  • the embodiments of the present application do not place any special restrictions on the specific forms of the above-mentioned electronic devices.
  • the following embodiments take the electronic device as a mobile phone as an example.
  • Figure 1 is a structural diagram of an electronic device according to some embodiments.
  • the electronic device 1 mainly includes a cover 11 , a display screen 12 , a middle frame 13 and a rear case 14 .
  • the back shell 14 and the display screen 12 are respectively located on both sides of the middle frame 13 , and the middle frame 13 and the display screen 12 are arranged in the back shell 14 .
  • the cover plate 11 is disposed on the side of the display screen 12 away from the middle frame 13 .
  • the display screen 12 The display surface faces the cover 11.
  • the display screen 12 can be a liquid crystal display (Liquid Crystal Display, LCD).
  • the liquid crystal display screen includes a liquid crystal display panel and a backlight module.
  • the liquid crystal display panel is arranged between the cover 11 and the backlight module.
  • Backlight modules are used to provide light sources for LCD panels.
  • the above-mentioned display screen 12 may also be an organic light emitting diode (OLED) display screen. Since the OLED display is a self-luminous display, there is no need to set up a backlight module.
  • OLED organic light emitting diode
  • the above-mentioned middle frame 13 includes a bearing plate 131 and a frame 132 surrounding the bearing plate 131 .
  • the electronic device 1 also includes electronic components such as a circuit board 15 , a battery, and a camera, which are disposed on the carrier board 131 .
  • the above-mentioned electronic device 1 may further include an integrated circuit 10 disposed on a circuit board 15 , and the integrated circuit 10 is electrically connected to the circuit board 15 .
  • the integrated circuit 10 may be a wafer or a chip.
  • the integrated circuit 10 When the integrated circuit 10 is a chip, the chip may be a bare chip or a packaged chip.
  • the packaged chip may include one or more bare chips. chip.
  • the integrated circuit 10 can be applied in logic devices (such as processors, controllers, sensors, etc.) or in storage devices (such as external memory, internal memory, etc.). The embodiments of the present application do not do this. limited.
  • Figures 2A to 2G are diagrams of the steps for preparing integrated circuits in related technologies.
  • the transistor of the integrated circuit is a fin field effect transistor as an example for illustrative description, but it is not limited to this application scenario.
  • S10' Etch the substrate 100' to form the fin 101', and then form a dielectric film 102', and the dielectric film 102' covers the substrate 100' and the fin 101'. Finally, a sacrificial gate 103' is formed on the dielectric film 102', and the sacrificial gate 103' is disposed across the fin 101'.
  • S20' Form a first mask layer L1' on the side of the sacrificial gate 103' away from the substrate 100', and the first mask layer L1' has an opening. Then, the sacrificial gate 103' is etched through the opening of the first mask layer L1' to form a gate cutting trench H1'.
  • the thickness of the sacrificial gate 103' is relatively large.
  • an etching process with high directivity needs to be used to increase the vertical and downward etching rate and reduce the lateral etching rate.
  • the etching rate in the direction ensures that the gate cutting trench H1' penetrates the sacrificial gate 103' while avoiding the size of the top opening of the gate cutting trench H1'. Inch is too big.
  • the sacrificial gate 103' will also be etched laterally, so that the width of the gate cutting trench H1' gradually becomes larger from bottom to top. That is, the top opening size of the gate cutting trench H1' is larger than the bottom size, and the gate cutting trench H1' has an approximately inverse conical shape.
  • S30' Fill the gate cutting trench H1' with dielectric material to form a gate cutting structure 104'.
  • the morphology of the gate cutting structure 104' matches the morphology of the gate cutting trench H1'. , that is, the gate cutting structure 104' also has an approximately inverted cone shape, and there is a chamfer ⁇ between the side surface of the gate cutting structure 104' and the surface of the dielectric film 102' on the side away from the substrate 100'.
  • the chamfer ⁇ is an acute angle, for example, the chamfer angle ⁇ shown in Figure 2C is 87°.
  • S40' After removing the sacrificial gate 103' to form the gate line trench H2', a work function layer 105' and a second mask layer L2' are formed in the gate line trench H2', and the work function layer The layer 105' and the second mask layer L2' cover the gate cutting structure 104', and then a third mask layer L3' is formed on the side of the second mask layer L2' away from the substrate 100'.
  • the third mask layer L3′ blocks the portion of the second mask layer L2′ located outside the target area T′.
  • S50' Using the third mask layer L3' as a mask, etch and remove the portion of the second mask layer L2' located in the target area T', in order to expose the work function layer 105' located in the target area. The part within area T'.
  • S70' After removing the second mask layer L2' and the third mask layer L3', the material of the work function layer 105' remains in the area close to the chamfer ⁇ , causing defects in the product. question.
  • an over-etching process is usually used to completely remove the material of the second mask layer L2' in the area close to the chamfer ⁇ , so as to avoid the work function in the subsequent preparation process.
  • the material of the layer 105' remains.
  • the over-etching process can easily damage the top of the fin 101', resulting in reduced device yield.
  • Figure 3 is a structural diagram of an integrated circuit according to some embodiments;
  • Figure 4 is a diagram of the integrated circuit in Figure 3 along the reference plane P. Cross-sectional view;
  • Figure 5 is a partial enlarged view of the integrated circuit in Figure 4 at position M.
  • the integrated circuit 10 includes a substrate 100 and fins 101 disposed on the substrate 100 .
  • the fins 101 extend along a first direction X parallel to the substrate 100 .
  • the first direction X is parallel to the surface of the substrate 100 near the fin 101 .
  • the integrated circuit 10 further includes a gate line 103A disposed on the substrate 100 .
  • the gate line 103A extends along the second direction Y parallel to the substrate 100 and spans the fin 101 .
  • the second direction Y is parallel to the surface of the substrate 100 near the fin 101 .
  • the second direction Y intersects the first direction X.
  • the second direction Y and the first direction X are perpendicular to each other.
  • the integrated circuit 10 further includes a gate cutting structure 104 extending along the first direction X.
  • the gate cutting structure 104 can cut the gate line 103A into a plurality of sub-gate lines 103a.
  • the same gate line 103A spans multiple fins 101.
  • the gate line 103A and the fins 101 it spans form multiple transistors.
  • the gate line 103A is used to control the on or off of the multiple transistors.
  • the gate cutting structure 104 cuts the gate line 103A into multiple sub-gate lines 103 a.
  • the multiple sub-gate lines 103 a span across the multiple fins 101
  • each sub-gate line 103a and the fin 101 it spans form a transistor, so that the plurality of sub-gate lines 103a can respectively control the on or off of multiple transistors.
  • transistor strings connected in series with the fin 101.
  • the integrated circuit 10 includes a first device region A1 configured to provide a P-type transistor and a second device region A2 configured to provide an N-type transistor. That is, in the first device area A1, the gate line 103A and the fins 101 it spans form a P-type transistor; in the second device area A2, the gate line 103A and the fins 101 it spans form an N-type transistor.
  • FIG. 4 shows a cross-sectional view of the integrated circuit 10 along the reference plane P
  • FIG. 5 is a partial enlarged view of the integrated circuit in FIG. 4 at M, where the reference plane P is perpendicular to the substrate 100 and is The first direction X is vertical.
  • the gate cutting structure 104 includes a first portion 104 a and a second portion 104 b connected, and the second portion 104 b is located on a side of the first portion 104 a away from the substrate 100 .
  • the first part 104a includes a first end surface S1 connected to the second part 104b
  • the second part 104b includes a second end surface S2 connected to the first part 104a, wherein the orthographic projection of the second end surface S2 on the substrate 100 is located at
  • the first end surface S1 is within the range of the orthographic projection on the substrate 100 . That is, the cross-sectional size of the second end surface S2 is smaller than or equal to the cross-sectional size of the first end surface S1.
  • cross-sectional size of the second end surface S2 refers to the size of the cross-section of the second end surface S2 along the reference plane P in the second direction Y;
  • cross-sectional size of the first end surface S1 refers to the first The size of the cross section of the end surface S1 along the reference plane P in the second direction Y.
  • the "cross-sectional size" of the "target object” mentioned in the following content of this article is the size of the cross-section of the target object along the reference plane P in the second direction Y.
  • FIG. 5 shows a situation where the orthographic projection of the second end surface S2 on the substrate 100 coincides with the orthographic projection of the first end surface S1 on the substrate 100 , that is, the first end surface S1 is on the substrate 100
  • the orthographic projection of just covers the orthographic projection of the second end surface S2 on the substrate 100 , and the cross-sectional size of the first end surface S1 is equal to the cross-sectional size of the second end surface S2.
  • the size of the cross section of the first part 104a along the reference plane P in the second direction Y changes from small to large, that is, in In FIG. 5 , the width of the first portion 104a in the second direction Y increases from small to large along the direction U.
  • the integrated circuit 10 further includes a dielectric layer 102 disposed between the substrate 100 and the gate line 103A.
  • the first part 104a of the gate cutting structure 104 includes a side C close to the sub-gate line 103a.
  • the cross section D of the side C away from the edge of the second part 104b is the same as the side of the dielectric layer 102 away from the substrate 100.
  • the angle ⁇ between the surfaces is an obtuse angle, that is, there is no indentation in the area close to the angle ⁇ .
  • the cross-sectional shape of the first part 104a along the reference plane P is a trapezoid or a cone, or the side surface C of the first part 104a is an arc surface convex toward the sub-grid line 103a.
  • connection N between the first portion 104 a and the second portion 104 b of the gate cut-off structure 104 has a smooth transition.
  • the height H1 of the first portion 104a is less than or equal to that of the second portion 104b Height H2.
  • the first portion 104 a of the gate cutting structure 104 has a hole 109 , and the extending direction of the hole 109 is the same as the extending direction of the gate cutting structure 104 , both along the first Extend in direction X.
  • the aperture 109 is conducive to reducing the parasitic capacitance generated between the two sub-gate lines 103a adjacent to the gate cutting structure 104 where the aperture 109 is located, thereby reducing the parasitic capacitance between the two adjacent sub-gate lines 103a. Signal interference.
  • the integrated circuit 10 further includes a dielectric layer 102 disposed between the substrate 100 and the gate line 103A.
  • the gate cutting structure 104 also includes a third part 104c.
  • the third part 104c is located on the side of the first part 104a close to the substrate 100 and is connected to the first part 104a.
  • the third part 104c is located in the dielectric layer 102, which is equivalent to,
  • the third portion 104c of the gate cutting structure 104 is embedded in the dielectric layer 102 to ensure that the gate cutting structure 104 penetrates the gate line 103A along the third direction Z to cut the gate line 103A into a plurality of sub-gate lines 103a.
  • the first portion 104a of the gate cutting structure 104 includes a third end surface S3 connected to the third portion 104c.
  • the orthographic projection of the third portion 104c on the substrate 100 is located at the third end surface S3.
  • the end surface S3 is within the range of the orthographic projection on the substrate 100 , that is, the cross-sectional size of the third portion 104 c is smaller than or equal to the cross-sectional size of the third end surface S3 .
  • FIG. 5 shows a situation where the cross-sectional size of the third part 104c is smaller than the cross-sectional size of the third end surface S3.
  • the integrated circuit 10 further includes a work function layer 108 , the work function layer 108 is disposed between the sub-gate line 103 a and the fin 101 , and the work function layer 108 is also disposed on the sub-gate line 103 a and the gate cutting structure 104.
  • the thickness of the portion of the work function layer 108 located in the first device region A1 is greater than the thickness of the portion of the work function layer 108 located in the second device region A2. That is, the thickness of the work function layer 108 included in the P-type transistor in the first device region A1 is greater than the thickness of the work function layer 108 included in the N-type transistor in the second device region A2.
  • the work function layer 108 is disposed in the first device region A1 and is not disposed in the second device region A2. This is equivalent to the thickness of the portion of the work function layer 108 located in the second device region A2 being 0. .
  • the work function layer 108 may be disposed in the first device region A1 and the second device region A2, that is, the thickness of the portion of the work function layer 108 located in the second device region A2 is not 0, and the work function layer 108 is located in the second device region A2.
  • the thickness of the portion of the first device region A1 is greater than the thickness of the portion of the work function layer 108 located in the second device region A2.
  • the integrated circuit 10 provided by the above embodiments of the present application provides a structural design of the gate cut-off structure 104, which is beneficial to the multiple work function process steps in the process of preparing the integrated circuit 10.
  • the work function layer at the bottom chamfer of the gate cut-off structure 104 can be removed cleanly, thereby improving the device yield of the integrated circuit.
  • FIGS. 6A to 6E illustrate polycrystalline gate line (sacrificial gate) processes and polycrystalline gate cutting (gate cutting) processes according to some embodiments. (cutting off structure) process;
  • Figures 7A to 7N are step diagrams of a polycrystalline gate circuit process and a polycrystalline gate cutting process according to some embodiments.
  • the preparation method of the integrated circuit 10 includes the following steps S10 to S50:
  • a fin 101 is formed on the substrate 100, and the fin 101 extends along a first direction X parallel to the substrate.
  • an etching process may be used to form the fins 101 on the substrate 100, that is, the fins 101 and the substrate 100 may be integrally provided.
  • a dielectric film 102a is formed to cover the substrate 100 and the fins 101.
  • a sacrificial layer 103 is formed on the dielectric film 102a.
  • the sacrificial layer 103 includes a sacrificial gate 1031 and an insulating layer 1032. Multiple sacrificial gates 1031 are arranged along the first direction X, and the insulating layer 1032 is located on two adjacent sides. Between sacrificial gates 1031. Furthermore, each sacrificial gate 1031 extends along the second direction Y, and the sacrificial gate 1031 is disposed across the fin 101 .
  • the material of the sacrificial gate 1031 may include polysilicon
  • the material of the insulating layer 1032 may include silicon oxide.
  • a gate cutting trench 1033 is formed in the sacrificial layer 103, and the gate cutting trench 1033 extends along the first direction X.
  • FIGS. 7D to 7L are diagrams of steps for preparing and forming the gate cutting trench 1033. Therefore, the finally formed gate cutting trench 1033 is shown in FIG. 7L.
  • the above-mentioned S40 includes the following S401 ⁇ S403:
  • a prefabricated trench 1034 is formed in the sacrificial layer 103 , and the prefabricated trench 1034 extends along the first direction X.
  • FIG. 7F shows the finally formed prefabricated trench 1034 .
  • the second portion 104b of the gate cutting structure 104 is formed in the prefabricated trench 1034, and the position of the bottom of the prefabricated trench 1034 corresponds to the second portion 104b and the first portion. 104a connection.
  • the above S401 includes the following steps:
  • a hard mask layer L1 and a mask stack L2 are sequentially formed on the side of the sacrificial layer 103 away from the substrate 100 .
  • the material of the hard mask layer L1 may include silicon nitride, for example.
  • the mask stack L2 includes a first mask layer L21, a second mask layer L22, and a third mask layer L23 that are stacked in sequence.
  • the materials of the first mask layer L21 and the third mask layer L23 may include, for example.
  • the photoresist and the material of the second mask layer L22 may include, for example, polymer materials.
  • the third mask layer L23 is patterned, a via hole is formed through the third mask layer L23, and the first mask layer L21 and the second mask layer L22 are etched through the via hole.
  • the first mask layer L21 , the second mask layer L22 and the third mask layer L23 are stacked to form the mask stack L2. This structural design can improve the overall mask performance of the mask stack L2.
  • the hard mask layer L1 is etched to form a via hole penetrating the hard mask layer L1.
  • the sacrificial layer 103 is etched through the via hole of the hard mask layer L1 to form a prefabricated trench 1034 .
  • the above-mentioned embodiment of the present application first etches to form a prefabricated trench 1034 with a smaller depth, which reduces the amount of etching and reduces the difficulty of etching.
  • S402 As shown in Figure 7G and Figure 7H, form a protective layer K2 on the side wall of the prefabricated trench 1034.
  • the protective layer K2 exposes the bottom of the prefabricated trench 1034.
  • the above-mentioned S402 includes the following S4021 ⁇ S4022:
  • a protective film K1 is formed.
  • the protective film K1 covers the side of the sacrificial layer 103 away from the substrate 100.
  • the protective film K1 covers the surface of the hard mask layer L1 away from the substrate 100.
  • the protective film K1 also covers the side walls and bottom of the prefabricated trench 1034.
  • the protective layer K2 covers the surface of the hard mask layer L1 away from the substrate 100 and the sidewalls of the prefabricated trench 1034.
  • the protective layer K2 can play a role in protecting the sidewalls of the prefabricated trench 1034 to avoid subsequent
  • the etching process causes damage to the sidewalls of the prefabricated trench 1034 to maintain the morphology of the sidewalls of the prefabricated trench 1034.
  • the first cavity E1 includes a first opening V1 connected to the prefabricated trench 1034
  • the prefabricated trench 1034 includes a second opening V2 connected to the first cavity E1
  • the second opening V2 is on the substrate 100
  • the orthographic projection on the substrate 100 is within the range of the orthographic projection of the first opening V1 on the substrate 100 , that is, the cross-sectional size of the second opening V2 is smaller than or equal to the cross-sectional size of the first opening V1 .
  • first part 104a of the gate cutting structure 104 is formed in the first cavity E1
  • second part 104b is formed in the prefabricated trench 1034.
  • the cross-sectional size of the second opening V2 of the prefabricated trench 1034 is less than or equal to the cross-sectional size of the first opening V1 of the first cavity E1
  • the cross-sectional size of the second end surface S2 of the second part 104b is less than or equal to the second opening V2 of the first cavity E1.
  • the cross-sectional size of the first end surface S1 of the part 104a is less than or equal to the second opening V2 of the first cavity E1.
  • the depth of the first cavity E1 along the third direction Z is set to be less than or equal to The depth of the prefabricated trench 1034 along the third direction Z can simplify the preparation process and reduce the process difficulty, so that the height H1 of the first part 104a is less than or equal to the height H2 of the second part 104b.
  • the above-mentioned S403 includes the following S4031 ⁇ S4034:
  • S4031 As shown in FIG. 7I , perform the first lateral etching of the sacrificial gate 1031 through the bottom of the prefabricated trench 1034.
  • a dry etching process may be used to perform a first lateral etching on the sacrificial gate 1031.
  • the above dry etching process may have high directionality or no directionality, and the etching selectivity ratio of the etching gas used for the sacrificial gate 1031 (polysilicon) is greater than that of the etching gas.
  • the etching gas used in the dry etching process may be, for example, oxygen, methane, fluoromethane, difluoromethane or fluorine-containing hydrocarbons (CH x F y ).
  • Gate 1031 forms groove D shown in FIG. 7I.
  • the orthographic projection of the bottom of the prefabricated trench 1034 on the substrate 100 is located within the range of the orthographic projection of the groove D on the substrate 100, that is, the first lateral etching of the sacrificial gate 1031 will
  • the sacrificial gate 1031 in contact with the bottom of the protective layer K2 is removed so that the bottom of the protective layer K2 is not in contact with the sacrificial gate 1031.
  • This step can It is ensured that in the subsequently formed gate cutting structure 104, the connection between the first part 104a and the second part 104b has a smooth transition.
  • the embodiments of the present application are not limited to using a dry etching process to perform the first lateral etching on the sacrificial gate 1031.
  • a chemical etching process or a wet etching process may also be used.
  • S4032 As shown in FIG. 7J, along the third direction Z, etch the sacrificial gate 1031 downward to the dielectric film 102a to form a through hole F exposing the dielectric film 102a.
  • a dry etching process can be used to etch the sacrificial gate 1031 down to the dielectric film 102a.
  • the above dry etching process may have high directivity, and the etching gas used may be, for example, hydrogen bromide or chlorine.
  • the dielectric film 102a is etched to form a second cavity E2.
  • the second cavity E2 exposes the surface of the sacrificial gate 1031 close to the dielectric film 102a.
  • a dry etching process may be used to etch the dielectric film 102a downward while simultaneously etching the dielectric film 102a laterally to form the second cavity E2.
  • the above dry etching process may have low directivity or no directionality, and the etching gas used may be, for example, dilute hydrogen fluoride.
  • the embodiments of the present application are not limited to using a dry etching process to etch the dielectric film 102a.
  • a chemical etching process or a wet etching process may also be used.
  • the second cavity E2 is connected to the through hole F, and the orthographic projection of the opening connecting the through hole F and the second cavity E2 on the substrate 100 is located at the position of the second cavity E2 on the substrate 100 .
  • the surface of the sacrificial gate 1031 close to the dielectric film 102a is exposed through the second cavity E2, so that during the subsequent second lateral etching of the sacrificial gate 1031, the second lateral etching can be improved.
  • the etching rate of the portion of the sacrificial gate 1031 exposed by the cavity E2 is greater than the etching rate of the portion of the sacrificial gate 1031 exposed by the through hole F, so that the first cavity formed by the final etching is
  • the cross-sectional shape of the cavity E1 is trapezoidal or tapered, so that the cross-sectional shape of the first portion 104a is trapezoidal or tapered.
  • S4034 As shown in FIG. 7L, perform a second lateral etching on the sacrificial gate 1031 to form the first cavity E1.
  • a dry etching process may be used to perform a second lateral etching on the sacrificial gate 1031 to form the first cavity E1.
  • the above dry etching process may have low directivity or no directionality, and the etching gas used may be nitrogen trifluoride, for example.
  • the sacrificial gate 1031 is close to a part of the second cavity E2.
  • the contact area between the side and the etching gas is larger, so the etching rate of the part of the sacrificial gate 1031 exposed by the second cavity E2 is greater than the etching rate of the part of the sacrificial gate 1031 exposed by the through hole F, so that The cross-sectional shape of the first cavity E1 is trapezoidal or tapered.
  • the second cavity E2 is located on the side of the first cavity E1 close to the substrate 100 and is connected to the first cavity E1.
  • the first cavity E1 includes a third opening V3 connected to the second cavity E2, and the orthographic projection of the second cavity E2 on the substrate 100 is located within the range of the orthographic projection of the third opening V3 on the substrate 100, That is, the cross-sectional size of the second cavity E2 is smaller than or equal to the cross-sectional size of the third opening V3.
  • first portion 104a of the gate cutting structure 104 is formed in the first cavity E1
  • third portion 104c is formed in the second cavity E2.
  • cross-sectional size of the second cavity E2 is smaller than or equal to the first cavity E1
  • the cross-sectional size of the third opening V3 is such that the cross-sectional size of the third part 104c is smaller than or equal to the cross-sectional size of the third end surface S3 of the first part 104a.
  • the gate cutting structure 104 is formed in the gate cutting trench 1033.
  • the above-mentioned S50 may include the following S501 ⁇ S502:
  • the dielectric material 110 is deposited in the gate cutting trench 1033 and on the surface of the protective layer K2 away from the substrate 100.
  • the deposition rate of the dielectric material 110 on the sidewalls of the gate cutting trench 1033 to be greater than or equal to the deposition rate of the dielectric material 110 on the bottom of the gate cutting trench 1033.
  • the deposition amount of the dielectric material 110 at the bottom of the gate cutting trench 1033 is insufficient, thereby forming a void 109 at the bottom of the gate cutting trench 1033 .
  • CMP chemical mechanical polishing
  • the preparation method of the integrated circuit 10 provided in the above embodiments belongs to the polycrystalline gate line process and the polycrystalline gate cutting process of the integrated circuit 10, and describes the preparation method of the gate cutting structure 104.
  • Figure 8 shows the replacement metal gate process and multiple work function process according to some embodiments.
  • Figures 9A to 9H are step diagrams of the replacement metal gate process and the multiple work function process according to some embodiments.
  • the method of preparing the integrated circuit 10 also includes the following steps S60 to S90:
  • FIGS. 9C to 9G the work function layer 108 is formed in the gate line trench 1035 .
  • FIG. 9G shows the finally formed work function layer 108 .
  • the above S80 includes the following steps:
  • a functional stack is sequentially formed in the gate line trench 1035.
  • the functional stack includes an interlayer dielectric layer 105, a high dielectric constant layer 106, an etching stop layer 107 and a functional layer that are stacked in sequence.
  • Function film 1080 is sequentially formed in the gate line trench 1035.
  • a filling layer 111 is formed in the gate line trench 1035 , and then a fourth mask layer L4 is formed on the side of the filling layer 111 away from the substrate 100 , and the fourth mask layer L4 is located in the first device region. A1.
  • a Spin On Coating (SOC) process can be used to form the filling layer 111 in the gate line trench 1035.
  • SOC Spin On Coating
  • the material of the filling layer 111 may include polymer materials.
  • the material of the filling layer 111 may include Including photoresist.
  • the portion of the filling layer 111 located in the second device region A2 is removed by etching, leaving the portion of the filling layer 111 located in the first device region A1 to expose the work function film. 1080 is located in a portion of the second device area A2.
  • the cross-sectional shape of the first portion 104a of the gate cutting structure 104 is a trapezoid or a cone, or the side C of the first portion 104a is convex toward the sub-gate line 103a.
  • the arc surface, and the included angle ⁇ is an obtuse angle (greater than 90°), so that there is no indentation in the included angle ⁇ area, and the portion of the filling layer 111 close to the included angle ⁇ can be easily removed.
  • connection N between the first part 104a and the second part 104b of the gate cutting structure 104, the part of the filling layer 111 close to the connection N can be easily removed.
  • the portion of the work function film 1080 located in the second device region A2 is removed by etching, and the etching stops at the etching point.
  • the stop layer 107 is etched, and the portion of the work function film 1080 located in the first device region A1 is retained to obtain the work function layer 108 .
  • the portion of the filling layer 111 close to the included angle ⁇ and the connection N is completely removed, the portion of the work function film 1080 close to the included angle ⁇ and the connection N can be easily removed to form the work function layer 108.
  • the device yield of the integrated circuit 10 is improved.
  • the fourth mask layer L4 and the portion of the filling layer 111 located in the first device region A1 are removed to completely expose the gate line trench 1035 .
  • the electronic device 1 provided in some embodiments of the present application includes the integrated circuit 10 provided in any of the above embodiments.
  • the beneficial effects it can achieve can be referred to the beneficial effects of the integrated circuit 10 mentioned above, which will not be described again here.

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Abstract

本申请的一些实施例提供了一种集成电路及其制备方法、电子设备，涉及半导体技术领域，旨在提高集成电路的器件的良率。该集成电路可以为晶圆或芯片，包括衬底、鳍、栅线和栅切断结构，其中，鳍设置于衬底上，栅线跨设在鳍上，栅切断结构可将栅线切割成多条子栅线。栅切断结构包括相连的第一部和第二部，第二部位于第一部远离衬底的一侧。第一部包括与第二部相连的第一端面，第二部包括与第一部相连的第二端面，第二端面在衬底上的正投影，位于第一端面在衬底上的正投影的范围内。并且，沿由第二部指向第一部的方向，第一部的截面尺寸由小变大，使第一部的截面形状为梯形或锥形。上述集成电路可应用于逻辑器件中，也可应用于存储器件中。

Description

集成电路及其制备方法、电子设备
本申请要求于2022年07月01日提交国家知识产权局、申请号为202210775500.7、申请名称为“集成电路及其制备方法、电子设备”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及半导体技术领域，尤其涉及一种集成电路及其制备方法、电子设备。
背景技术
先进工艺技术中，集成电路的晶体管通常为鳍式场效应晶体管(Fin Field-Effect Transistor，FinFET)，该晶体管采用高介电常数金属栅(High K Metal Gate，HKMG)技术。
目前，在制备集成电路的过程中，可采用多次曝光显影工艺和刻蚀工艺，制备得到多晶闸极(包含多晶硅的牺牲栅)和金属闸极(包含导电材料的栅线)。具体地，多晶闸极的制备工艺可包括多晶闸极线路(Poly Line，POL)工艺，以及多晶闸极切断(Poly Cut，POC)工艺，即先形成牺牲栅，然后形成栅切断结构，栅切断结构可用于切割牺牲栅。并且，金属闸极的制备工艺可包括替代金属栅(Replacement Metal Gate，RMG)工艺，以及多重功函数(Multi Work Function，MWF)工艺，即先去除牺牲栅以形成栅线沟槽，然后在栅线沟槽内形成功函数层和掩膜层，且功函数层和掩膜层会覆盖栅切断结构，之后将功函数层和掩膜层位于目标区域内的部分去除，最后在栅线沟槽内沉积导电材料，以形成栅线。
然而，在牺牲栅中刻蚀形成栅切断沟槽的过程中，由于刻蚀特性使得栅切断沟槽的开口尺寸要大于底部尺寸，这样，在栅切断沟槽内填充电介质材料之后，形成的栅切断结构具有近似倒锥形的形貌，该形貌使得在去除掩膜层的过程中，靠近栅切断结构的底部夹角处易残留掩膜层材料，进而导致功函数层的材料残留。因此，需采用过刻蚀(over-etch)工艺，将残留的掩膜层材料完全去除，以避免功函数层的材料残留，但是，过刻蚀工艺易刻蚀损伤晶体管的鳍，导致器件的良率降低。
发明内容
本申请的一些实施例提供了一种集成电路及其制备方法、电子设备，旨在提高集成电路的器件的良率。
为达到上述目的，本申请的实施例采用如下技术方案：
第一方面，提供了一种集成电路，该集成电路可以为晶圆，也可以为芯片，在集成电路为芯片的情况下，芯片例如可以为裸芯片，也可以是经过封装的芯片，封装的芯片中可包括一个或多个裸芯片。该集成电路可应用于逻辑器件(例如，处理器、控制器、传感器等)中，也可应用于存储器件(例如，外存储器、内存储器等)中。
该集成电路包括衬底、鳍、栅线和栅切断结构，其中，鳍设置于衬底上，且沿平行于衬底的第一方向延伸。栅线沿平行于衬底的第二方向延伸，第二方向与第一方向相交叉，栅线跨设在鳍上。栅切断结构沿第一方向延伸，并将栅线切割成多条子栅线。
其中，栅切断结构包括相连的第一部和第二部，第二部位于第一部远离衬底的一 侧。第一部包括与第二部相连的第一端面，第二部包括与第一部相连的第二端面，第二端面在衬底上的正投影，位于第一端面在衬底上的正投影的范围内，即第二端面的截面尺寸小于或等于第一端面的截面尺寸。沿由第二部指向第一部的方向，第一部沿参考面的截面在第二方向上的尺寸由小变大，该参考面垂直于衬底，且与第一方向垂直。
在一些实施例中，集成电路还包括设置于衬底与栅线之间的介质层，第一部靠近子栅线的侧面中，远离第二部的边缘的切面，与介质层远离衬底一侧的表面之间的夹角为钝角。
在一些实施例中，第一部沿参考面的截面形状为梯形或锥形，或者，第一部靠近子栅线的侧面为向子栅线凸起的弧面。
在一些实施例中，第一部与第二部的连接处平滑过渡。
在一些实施例中，沿垂直于衬底的第三方向，第一部的高度小于或等于第二部的高度。
在一些实施例中，栅切断结构还包括第三部，该第三部位于第一部靠近衬底的一侧，且与第一部相连，第三部位于介质层内。
通过上述设置方式，栅切断结构的第三部嵌入介质层内，保证栅切断结构沿竖直方向贯穿栅线，以将栅线切割成多条子栅线。
在一些实施例中，第一部包括与第三部相连的第三端面，第三部在衬底上的正投影，位于第三端面在衬底上的正投影的范围内，即第三部的截面尺寸小于或等于第三端面的截面尺寸。
在一些实施例中，第一部中具有孔隙，该孔隙沿第一方向延伸。
通过上述设置方式，孔隙有利于减小，与该孔隙所在的栅切断结构相邻的两条子栅线之间产生的寄生电容，从而减小相邻两条子栅线之间的信号干扰。
在一些实施例中，集成电路包括第一器件区和第二器件区，第一器件区被配置为设置P型晶体管，第二器件区被配置为设置N型晶体管。集成电路还包括功函数层，该功函数层设置于子栅线与鳍之间，及子栅线与栅切断结构之间，功函数层中位于第一器件区的部分的厚度，大于功函数层中位于第二器件区的部分的厚度。
本申请的一些实施例所提供的集成电路，通过栅切断结构的结构设计，栅切断结构的第一部的截面形状为梯形或锥形，第一部的侧面为向子栅线凸起的弧面，且夹角为钝角(大于90°)，使得夹角区域没有内陷，在多重功函数工艺步骤中，可将功函数薄膜靠近夹角区域的部分去除干净，以形成功函数层，从而提高集成电路的器件的良率。
并且，通过设置栅切断结构的第一部与第二部的连接处平滑过渡，可将功函数薄膜靠近连接处的部分去除干净，以形成功函数层，从而提高集成电路的器件的良率。
第二方面，提供了一种集成电路的制备方法，该制备方法包括：在衬底上形成鳍，鳍沿平行于衬底的第一方向延伸。形成介质薄膜，介质薄膜覆盖衬底和鳍。在介质薄膜上形成牺牲层，牺牲层包括牺牲栅，牺牲栅沿平行于衬底的第二方向延伸，第二方向与第一方向相交叉，牺牲栅跨设在鳍上。在牺牲层中形成栅切断沟槽，栅切断沟槽沿第一方向延伸。在栅切断沟槽内形成栅切断结构。
在一些实施例中，在牺牲层中形成栅切断沟槽，包括：在牺牲层中形成预制沟槽。在预制沟槽的侧壁上形成保护层，保护层暴露预制沟槽的底部。经由预制沟槽的底部，向下刻蚀牺牲栅至介质薄膜，并侧向刻蚀牺牲栅以形成第一空腔。
其中，第一空腔包括与预制沟槽相连的第一开口，预制沟槽包括与第一空腔相连的第二开口，第二开口在衬底上的正投影，位于第一开口在衬底上的正投影的范围内。
上述实施例中，由于栅切断结构的第一部形成于第一空腔内，第二部形成于预制沟槽内，并且，由于预制沟槽的第二开口的截面尺寸小于或等于，第一空腔的第一开口的截面尺寸，使得第二部的第二端面的截面尺寸小于或等于第一部的第一端面的截面尺寸。
并且，由于刻蚀形成预制沟槽的工艺，相较于刻蚀形成第一空腔的工艺更为简化，因此，通过设置第一空腔沿第三方向的深度，小于或等于预制沟槽沿第三方向的深度，可简化制备工艺，节省工艺成本，从而使得第一部的高度小于或等于第二部的高度。
在一些实施例中，向下刻蚀牺牲栅至介质薄膜，并侧向刻蚀牺牲栅以形成第一空腔，包括：经由预制沟槽的底部，对牺牲栅进行第一次侧向刻蚀。向下刻蚀牺牲栅至介质薄膜。对牺牲栅进行第二次侧向刻蚀。
上述实施例中，对牺牲栅进行的第一次侧向刻蚀，将与保护层的底部接触的牺牲栅去除，使保护层的底部不与牺牲栅相接触，该步骤可保证后续形成的栅切断结构中，第一部与第二部的连接处平滑过渡。
并且，对牺牲栅进行第二次侧向刻蚀，使第一空腔的截面形状呈梯形或锥形，从而使第一部的截面形状为梯形或锥形。
在一些实施例中，对牺牲栅进行第一次侧向刻蚀，包括：采用干法刻蚀工艺，对牺牲栅进行第一次侧向刻蚀。其中，干法刻蚀工艺所采用的刻蚀气体对牺牲栅的刻蚀选择比，大于刻蚀气体对保护层的刻蚀选择比。
上述实施例中，采用上述干法刻蚀工艺，沿第三方向竖直向下刻蚀牺牲栅的过程中，刻蚀副产物携带高能离子发生侧向回溅，会沿侧向刻蚀牺牲栅。
在一些实施例中，向下刻蚀牺牲栅至介质薄膜之后，对牺牲栅进行第二次侧向刻蚀之前，还包括：刻蚀介质薄膜以形成第二空腔，第二空腔暴露牺牲栅靠近介质薄膜一侧的表面。
上述实施例中，通过第二空腔暴露牺牲栅靠近介质薄膜一侧的表面，以便于对牺牲栅进行第二次侧向刻蚀的过程中，可提高对第二空腔所暴露的牺牲栅的部分的刻蚀速率，使第一空腔的截面形状呈梯形或锥形，从而使第一部的截面形状为梯形或锥形。
在一些实施例中，在预制沟槽的侧壁上形成保护层，包括：形成保护薄膜，保护薄膜覆盖牺牲层远离衬底的一侧，以及预制沟槽的侧壁和底部。去除保护薄膜中覆盖预制沟槽的底部的部分，形成保护层。
上述实施例中，保护层可起到保护预制沟槽的侧壁的作用，避免后续的刻蚀工艺对预制沟槽的侧壁造成损伤。
在一些实施例中，在栅切断沟槽内形成栅切断结构，包括：在栅切断沟槽内，及保护层远离衬底的表面沉积电介质材料。去除位于保护层远离衬底的表面的电介质材料，以及保护层中覆盖牺牲层远离衬底的表面的部分，电介质材料保留的部分和保护 层中覆盖预制沟槽的侧壁的部分形成栅切断结构。
上述实施例中，在沉积电介质材料的过程中，通过控制电介质材料在栅切断沟槽的侧壁的沉积速率，大于或等于电介质材料在栅切断沟槽的底部的沉积速率，使得栅切断沟槽的顶部被电介质材料密封的情况下，电介质材料在栅切断沟槽的底部的沉积量不足，从而在栅切断沟槽的底部形成孔隙。
并且，去除位于保护层远离衬底的表面的电介质材料，以及保护层中覆盖牺牲层远离衬底的表面的部分，以暴露出牺牲层的顶面，以便于后续进行替代金属栅工艺和多重功函数工艺。
在一些实施例中，在栅切断沟槽内形成栅切断结构之后，还包括：去除牺牲层中的牺牲栅，以在绝缘层中形成栅线沟槽。经由栅线沟槽，去除介质薄膜的覆盖鳍的部分，形成介质层。在栅线沟槽内形成功函数层，功函数层中位于第一器件区的部分的厚度，大于功函数层中位于第二器件区的部分的厚度。在栅线沟槽内填充导电材料，以形成栅线。
本申请的一些实施例所提供的制备方法，采用该方法制备形成的栅切断结构，其第一部的截面形状为梯形或锥形，或者，第一部的侧面为向子栅线凸起的弧面，且夹角为钝角，使得夹角区域没有内陷，并且，栅切断结构的第一部与第二部的连接处平滑过渡。
在栅线沟槽内形成功函数层的过程中，功函数薄膜靠近夹角和连接处的部分易被去除干净，以形成功函数层，从而可提高集成电路的器件的良率。
第三方面，提供了一种电子设备，该电子设备例如为消费性电子产品、家居式电子产品、车载式电子产品、金融终端产品、通信电子产品。该电子设备包括电路板，以及上述任一实施例所述的集成电路，该集成电路与电路板电连接。
可以理解地，本申请的上述实施例提供的电子设备，其所能达到的有益效果可参考上文中集成电路的有益效果，此处不再赘述。
附图说明
为了更清楚地说明本申请中的技术方案，下面将对本申请一些实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例的附图，对于本领域普通技术人员来讲，还可以根据这些附图获得其他的附图。此外，以下描述中的附图可以视作示意图，并非对本申请实施例所涉及的产品的实际尺寸、方法的实际流程、信号的实际时序等的限制。
图1为根据一些实施例的电子设备的结构图；
图2A～图2G为相关技术中制备集成电路的各步骤图；
图3为根据一些实施例的集成电路的结构图；
图4为图3中的集成电路沿参考面P的剖视图；
图5为图4中的集成电路在M处的局部放大图；
图6A～图6E为根据一些实施例的多晶闸极线路工艺和多晶闸极切断工艺的各流程图；
图7A～图7N为根据一些实施例的多晶闸极线路工艺和多晶闸极切断工艺的各步骤图；
图8为根据一些实施例的替代金属栅工艺和多重功函数工艺的流程图；
图9A～图9H为根据一些实施例的替代金属栅工艺和多重功函数工艺的各步骤图。
具体实施方式
下面将结合附图，对本申请一些实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请所提供的实施例，本领域普通技术人员所获得的所有其他实施例，都属于本申请保护的范围。
在本申请的描述中，需要理解的是，术语“中心”、“上”、“下”、“前”、“后”、“左”、“右”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本申请和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。
除非上下文另有要求，否则，在整个说明书和权利要求书中，术语“包括”被解释为开放、包含的意思，即为“包含，但不限于”。在说明书的描述中，术语“一个实施例”、“一些实施例”、“示例性实施例”、“示例性地”或“一些示例”等旨在表明与该实施例或示例相关的特定特征、结构、材料或特性包括在本申请的至少一个实施例或示例中。上述术语的示意性表示不一定是指同一实施例或示例。此外，所述的特定特征、结构、材料或特点可以以任何适当方式包括在任何一个或多个实施例或示例中。
以下，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本申请实施例的描述中，除非另有说明，“多个”的含义是两个或两个以上。
在描述一些实施例时，可能使用了“连接”及其衍伸的表达。例如，描述一些实施例时可能使用了术语“连接”以表明两个或两个以上部件彼此间有直接物理接触或电接触。
“A和/或B”，包括以下三种组合：仅A，仅B，及A和B的组合。
另外，“基于”的使用意味着开放和包容性，因为“基于”一个或多个所述条件或值的过程、步骤、计算或其他动作在实践中可以基于额外条件或超出所述的值。
本文参照作为理想化示例性附图的剖视图和/或平面图描述了示例性实施方式。在附图中，为了清楚，放大了层和区域的厚度。因此，可设想到由于例如制造技术和/或公差引起的相对于附图的形状的变动。因此，示例性实施方式不应解释为局限于本文示出的区域的形状，而是包括因例如制造而引起的形状偏差。例如，示为矩形的蚀刻区域通常将具有弯曲的特征。因此，附图中所示的区域本质上是示意性的，且它们的形状并非旨在示出设备的区域的实际形状，并且并非旨在限制示例性实施方式的范围。
本申请的实施例提供一种电子设备。该电子设备例如为消费性电子产品、家居式电子产品、车载式电子产品、金融终端产品、通信电子产品。其中，消费性电子产品如为手机、平板电脑、笔记本电脑、电子阅读器、个人计算机(Personal Computer， PC)、个人数字助理(Personal Digital Assistant，PDA)、桌面显示器、智能穿戴产品(例如，智能手表、智能手环)、虚拟现实(Virtual Reality，VR)终端设备、增强现实(Augmented Reality，AR)终端设备、无人机等。家居式电子产品如为智能门锁、电视、遥控器、冰箱、充电家用小型电器(例如豆浆机、扫地机器人)等。车载式电子产品如为车载导航仪、车载高密度数字视频光盘等。金融终端产品如为自动取款机、自助办理业务的终端等。通信电子产品如为服务器、存储器、基站等通信设备。
本申请的实施例对上述电子设备的具体形式不做特殊限制。以下实施例为了方便说明，均是以电子设备为手机为例进行举例说明。
图1为根据一些实施例的电子设备的结构图。
如图1所示，电子设备1主要包括盖板11、显示屏12、中框13以及后壳14。后壳14和显示屏12分别位于中框13的两侧，且中框13和显示屏12设置于后壳14内，盖板11设置在显示屏12远离中框13的一侧，显示屏12的显示面朝向盖板11。
其中，显示屏12可以是液晶显示屏(Liquid Crystal Display，LCD)，在此情况下，液晶显示屏包括液晶显示面板和背光模组，液晶显示面板设置在盖板11和背光模组之间，背光模组用于为液晶显示面板提供光源。上述显示屏12也可以为有机发光二极管(Organic Light Emitting Diode，OLED)显示屏。由于OLED显示屏为自发光显示屏，因而无需设置背光模组。
上述中框13包括承载板131以及绕承载板131一周的边框132。电子设备1中还包括设置于承载板131上的电路板15、电池、摄像头等电子元器件。
如图1所示，上述电子设备1还可以包括设置于电路板15上的集成电路10，该集成电路10与电路板15电连接。
上述集成电路10可以为晶圆，也可以为芯片，在集成电路10为芯片的情况下，芯片例如可以为裸芯片，也可以是经过封装的芯片，封装的芯片中可包括一个或多个裸芯片。该集成电路10可应用于逻辑器件(例如，处理器、控制器、传感器等)中，也可应用于存储器件(例如，外存储器、内存储器等)中，本申请的实施例对此不做限定。
下面介绍相关技术中集成电路的制备方法，图2A～图2G为相关技术中制备集成电路的各步骤图。
本文的以下各实施例，均是以集成电路的晶体管为鳍式场效应晶体管为例，进行示例性说明，但是其不局限于此应用场景。
如图2A所示，S10＇：在衬底100＇上刻蚀形成鳍101＇，然后形成介质薄膜102＇，介质薄膜102＇覆盖衬底100＇和鳍101＇。最后，在介质薄膜102＇上形成牺牲栅103＇，该牺牲栅103＇跨设在鳍101＇上。
如图2B所示，S20＇：在牺牲栅103＇远离衬底100＇的一侧形成第一掩膜层L1＇，该第一掩膜层L1＇具有开口。然后，通过第一掩膜层L1＇的开口，刻蚀牺牲栅103＇以形成栅切断沟槽H1＇。
需要说明的是，牺牲栅103＇的厚度较大，在刻蚀牺牲栅103＇的过程中，需要采用具有高方向性的刻蚀工艺，来增加竖直向下的刻蚀速率，减小侧向的刻蚀速率，保证栅切断沟槽H1＇贯穿牺牲栅103＇的同时，避免栅切断沟槽H1＇的顶部开口的尺 寸过大。
但是，采用上述刻蚀工艺，在竖直向下刻蚀牺牲栅103＇的过程中，还会侧向刻蚀牺牲栅103＇，使得栅切断沟槽H1＇的宽度由下至上逐渐变大，即栅切断沟槽H1＇的顶部开口尺寸大于其底部尺寸，栅切断沟槽H1＇具有近似倒锥形的形貌。
如图2C所示，S30＇：在栅切断沟槽H1＇内填充电介质材料，以形成栅切断结构104＇，栅切断结构104＇的形貌与栅切断沟槽H1＇的形貌相适配，即栅切断结构104＇也具有近似倒锥形的形貌，且栅切断结构104＇的侧面与介质薄膜102＇远离衬底100＇一侧的表面之间具有倒角α，该倒角α为锐角，例如，图2C中示出的倒角α为87°。
如图2D所示，S40＇：去除牺牲栅103＇以形成栅线沟槽H2＇之后，在栅线沟槽H2＇内形成功函数层105＇和第二掩膜层L2＇，且功函数层105＇和第二掩膜层L2＇覆盖栅切断结构104＇，然后在第二掩膜层L2＇远离衬底100＇的一侧形成第三掩膜层L3＇，该第三掩膜层L3＇遮挡第二掩膜层L2＇位于目标区域T＇外的部分。
如图2E所示，S50＇：以第三掩膜层L3＇为掩膜，刻蚀去除第二掩膜层L2＇位于目标区域T＇内的部分，目的是暴露功函数层105＇位于目标区域T＇内的部分。
但是，受限于栅切断结构104＇的倒锥形的形貌，靠近倒角α的区域向内凹陷，第二掩膜层L2＇在该区域不易去除干净，导致材料的残留，如图2E所示。
基于此，如图2F所示，S60＇：在去除功函数层105＇位于目标区域T＇内的部分的过程中，由于靠近倒角α的区域有第二掩膜层L2＇的材料残留，导致其所覆盖的功函数层105＇的部分无法去除。
进而，如图2G所示，S70＇：去除第二掩膜层L2＇和第三掩膜层L3＇之后，在靠近倒角α的区域有功函数层105＇的材料残留，导致产品出现不良的问题。
因此，在相关技术中，在S50＇中，通常采用过刻蚀工艺，将靠近倒角α的区域的第二掩膜层L2＇的材料完全去除，从而在后续的制备过程中，避免功函数层105＇的材料残留，但是，过刻蚀工艺易刻蚀损伤鳍101＇的顶部，导致器件的良率降低。
为解决上述问题，本申请的一些实施例提供了一种集成电路及其制备方法，图3为根据一些实施例的集成电路的结构图；图4为图3中的集成电路沿参考面P的剖视图；图5为图4中的集成电路在M处的局部放大图。
参见图3和图4，集成电路10包括衬底100，以及设置于衬底100上的鳍101，该鳍101沿平行于衬底100的第一方向X延伸。例如，第一方向X与衬底100靠近鳍101一侧的表面平行。
继续参见图3和图4，集成电路10还包括设置于衬底100上的栅线103A，该栅线103A沿平行于衬底100的第二方向Y延伸，且跨设在鳍101上。例如，第二方向Y与衬底100靠近鳍101一侧的表面平行。
需要说明的是，第二方向Y与第一方向X相交叉，例如，第二方向Y与第一方向X相互垂直。
再次参见图3和图4，集成电路10还包括沿第一方向X延伸的栅切断结构104，栅切断结构104可将栅线103A切割成多条子栅线103a。
可以理解的是，在没有栅切断结构104切割栅线103A的情况下，沿第二方向Y， 同一条栅线103A跨设在多条鳍101上，该栅线103A与其所跨过的鳍101形成多个晶体管，该栅线103A用于控制该多个晶体管的导通或截止。
而在图3和图4中，栅切断结构104将栅线103A切割成多条子栅线103a，在此情况下，在同一条栅线103A中，多条子栅线103a跨设在多条鳍101上，每条子栅线103a与其所跨过的鳍101形成晶体管，以通过多条子栅线103a分别控制多个晶体管的导通或截止。
并且，沿第一方向X，多条子栅线103a跨设在同一条鳍101上，每条子栅线103a与该鳍101形成一个晶体管，因此，跨设在同一条鳍101上的多条子栅线103a，与该鳍101形成串联的多个晶体管(晶体管串)。
此外，如图4所示，集成电路10包括第一器件区A1和第二器件区A2，第一器件区A1被配置为设置P型晶体管，第二器件区A2被配置为设置N型晶体管。即，在第一器件区A1内，栅线103A与其所跨过的鳍101形成P型晶体管；在第二器件区A2内，栅线103A与其所跨过的鳍101形成N型晶体管。
根据前文所述，图4示出了集成电路10沿参考面P的剖视图，图5为图4中的集成电路在M处的局部放大图，其中，参考面P垂直于衬底100，且与第一方向X垂直。
参见图4和图5，栅切断结构104包括相连的第一部104a和第二部104b，且第二部104b位于第一部104a远离衬底100的一侧。第一部104a包括与第二部104b相连的第一端面S1，第二部104b包括与第一部104a相连的第二端面S2，其中，第二端面S2在衬底100上的正投影，位于第一端面S1在衬底100上的正投影的范围内。即，第二端面S2的截面尺寸小于或等于第一端面S1的截面尺寸。
需要说明的是，第二端面S2的“截面尺寸”是指，第二端面S2沿参考面P的截面在第二方向Y上的尺寸；第一端面S1的“截面尺寸”是指，第一端面S1沿参考面P的截面在第二方向Y上的尺寸。
并且，本文以下内容提到的“目标对象”的“截面尺寸”，均为该目标对象沿参考面P的截面在第二方向Y上的尺寸。
示例性地，图5示出了第二端面S2在衬底100上的正投影，与第一端面S1在衬底100上的正投影重合的情形，即，第一端面S1在衬底100上的正投影，刚好覆盖第二端面S2在衬底100上的正投影，第一端面S1的截面尺寸等于第二端面S2的截面尺寸。
并且，继续参见图4和图5，沿由第二部104b指向第一部104a的方向U，第一部104a沿参考面P的截面在第二方向Y上的尺寸由小变大，即在图5中，第一部104a在第二方向Y上的宽度沿方向U由小变大。
在一些实施例中，如图4和图5所示，集成电路10还包括设置于衬底100与栅线103A之间的介质层102。
如图5所示，栅切断结构104的第一部104a包括靠近子栅线103a的侧面C，该侧面C的远离第二部104b的边缘的切面D，与介质层102远离衬底100一侧的表面之间的夹角β为钝角，即靠近夹角β的区域没有内陷。
示例性地，第一部104a沿参考面P的截面形状为梯形或锥形，或者，第一部104a的侧面C为向子栅线103a凸起的弧面。
在一些实施例中，如图5所示，栅切断结构104的第一部104a与第二部104b的连接处N平滑过渡。
在一些实施例中，如图5所示，沿垂直于衬底100的第三方向Z(即第三方向Z垂直于X-Y平面)，第一部104a的高度H1小于或等于第二部104b的高度H2。
在一些实施例中，如图4和图5所示，栅切断结构104的第一部104a中具有孔隙109，该孔隙109的延伸方向与栅切断结构104的延伸方向相同，均为沿第一方向X延伸。
通过上述设置方式，孔隙109有利于减小，与该孔隙109所在的栅切断结构104相邻的两条子栅线103a之间产生的寄生电容，从而减小相邻两条子栅线103a之间的信号干扰。
在一些实施例中，如图4和图5所示，集成电路10还包括设置于衬底100与栅线103A之间的介质层102。栅切断结构104还包括第三部104c，该第三部104c位于第一部104a靠近衬底100的一侧，且与第一部104a相连，第三部104c位于介质层102内，相当于，栅切断结构104的第三部104c嵌入介质层102内，保证栅切断结构104沿第三方向Z贯穿栅线103A，以将栅线103A切割成多条子栅线103a。
在一些实施例中，如图5所示，栅切断结构104的第一部104a包括与第三部104c相连的第三端面S3，第三部104c在衬底100上的正投影，位于第三端面S3在衬底100上的正投影的范围内，即，第三部104c的截面尺寸小于或等于第三端面S3的截面尺寸。
示例性地，图5示出了第三部104c的截面尺寸小于第三端面S3的截面尺寸的情形。
在一些实施例中，如图4所示，集成电路10还包括功函数层108，功函数层108设置于子栅线103a与鳍101之间，且功函数层108还设置于子栅线103a与栅切断结构104之间。
并且，功函数层108位于第一器件区A1的部分的厚度，大于功函数层108位于第二器件区A2的部分的厚度。即，第一器件区A1内P型晶体管所包括的功函数层108的厚度，大于第二器件区A2内N型晶体管所包括的功函数层108的厚度。
示例性地，如图4所示，功函数层108设置于第一器件区A1，未设置于第二器件区A2，相当于，功函数层108位于第二器件区A2的部分的厚度为0。
在另一些示例中，功函数层108可设置于第一器件区A1和第二器件区A2，即功函数层108位于第二器件区A2的部分的厚度不为0，且功函数层108位于第一器件区A1的部分的厚度，大于功函数层108位于第二器件区A2的部分的厚度。
本申请的上述实施例所提供的集成电路10，集成电路10提供了一种栅切断结构104的结构设计，该结构设计益于在制备集成电路10的过程中，在多重功函数工艺步骤中，可将栅切断结构104的底部倒角处的功函数层去除干净，从而提高集成电路的器件的良率。
接下来，通过介绍该集成电路10的制备方法，来具体描述上述栅切断结构104是如何制备形成的，以及栅切断结构104在多重功函数工艺中的作用。
图6A～图6E为根据一些实施例的多晶闸极线路(牺牲栅)工艺和多晶闸极切断(栅 切断结构)工艺的各流程图；图7A～图7N为根据一些实施例的多晶闸极线路工艺和多晶闸极切断工艺的各步骤图。
参见图6A，集成电路10的制备方法包括如下S10～S50：
S10：如图7A所示，在衬底100上形成鳍101，该鳍101沿平行于衬底的第一方向X延伸。
示例性地，可采用刻蚀工艺，在衬底100上刻蚀形成鳍101，即鳍101与衬底100可一体设置。
S20：如图7B所示，形成介质薄膜102a，该介质薄膜102a覆盖衬底100和鳍101。
S30：如图7C所示，在介质薄膜102a上形成牺牲层103，该牺牲层103包括牺牲栅1031和绝缘层1032，多条牺牲栅1031沿第一方向X排列，绝缘层1032位于相邻两条牺牲栅1031之间。并且，每条牺牲栅1031沿第二方向Y延伸，且牺牲栅1031跨设在鳍101上。
示例性地，牺牲栅1031的材料可包括多晶硅，绝缘层1032的材料可包括氧化硅。
S40：如图7D～图7L所示，在牺牲层103中形成栅切断沟槽1033，该栅切断沟槽1033沿第一方向X延伸。
需要说明的是，图7D～图7L为制备形成栅切断沟槽1033的各步骤图，因此，图7L中示出了最终形成的栅切断沟槽1033。
在一些实施例中，参见图6B，上述S40包括如下S401～S403：
S401：如图7D～图7F所示，在牺牲层103中形成预制沟槽1034，该预制沟槽1034沿第一方向X延伸，图7F示出了最终形成的预制沟槽1034。
需要说明的是，在后续形成栅切断结构104之后，栅切断结构104的第二部104b形成于预制沟槽1034内，预制沟槽1034的底部所在的位置即对应第二部104b与第一部104a的连接处。
示例性地，上述S401包括如下步骤：
如图7D所示，在牺牲层103远离衬底100的一侧依次形成硬掩膜层L1和掩膜叠层L2。
其中，硬掩膜层L1的材料例如可包括氮化硅。掩膜叠层L2包括依次层叠设置的第一掩膜层L21、第二掩膜层L22和第三掩膜层L23，第一掩膜层L21和第三掩膜层L23的材料例如均可包括光刻胶，第二掩膜层L22的材料例如可包括高分子材料。
然后，图案化第三掩膜层L23，形成贯穿第三掩膜层L23的过孔，并经由该过孔刻蚀第一掩膜层L21和第二掩膜层L22，第一掩膜层L21、第二掩膜层L22和第三掩膜层L23层叠形成掩膜叠层L2，采用该结构设计可提高掩膜叠层L2整体的掩膜性能。
如图7D和图7E所示，以掩膜叠层L2为掩膜，刻蚀硬掩膜层L1，以形成贯穿硬掩膜层L1的过孔。
最后，如图7F所示，经由硬掩膜层L1的过孔，刻蚀牺牲层103，以形成预制沟槽1034。
相较于现有技术中采用一步刻蚀形成栅切断沟槽，本申请的上述实施例先刻蚀形成深度较小的预制沟槽1034，减少了刻蚀量，降低了刻蚀难度。
S402：如图7G和图7H，在预制沟槽1034的侧壁上形成保护层K2，该保护层 K2暴露预制沟槽1034的底部。
示例性地，参见图6C，上述S402包括如下S4021～S4022：
S4021：如图7G所示，形成保护薄膜K1，该保护薄膜K1覆盖牺牲层103远离衬底100的一侧，例如，保护薄膜K1覆盖硬掩膜层L1的远离衬底100的表面。并且，保护薄膜K1还覆盖预制沟槽1034的侧壁和底部。
S4022：如图7G和图7H所示，去除保护薄膜K1中覆盖预制沟槽1034的底部的部分，形成保护层K2。
可以理解的是，保护层K2覆盖硬掩膜层L1的远离衬底100的表面，以及预制沟槽1034的侧壁，保护层K2可起到保护预制沟槽1034的侧壁的作用，避免后续的刻蚀工艺对预制沟槽1034的侧壁造成损伤，以保持预制沟槽1034的侧壁的形貌。
S403：如图7I～图7L所示，经由预制沟槽1034的底部，向下刻蚀牺牲栅1031至介质薄膜102a，并侧向刻蚀牺牲栅1031以形成第一空腔E1，图7L示出了最终形成的第一空腔E1。
如图7L所示，第一空腔E1包括与预制沟槽1034相连的第一开口V1，预制沟槽1034包括与第一空腔E1相连的第二开口V2，第二开口V2在衬底100上的正投影，位于第一开口V1在衬底100上的正投影的范围内，即第二开口V2的截面尺寸要小于或等于第一开口V1的截面尺寸。
需要说明的是，栅切断结构104的第一部104a形成于第一空腔E1内，第二部104b形成于预制沟槽1034内。并且，由于预制沟槽1034的第二开口V2的截面尺寸小于或等于，第一空腔E1的第一开口V1的截面尺寸，使得第二部104b的第二端面S2的截面尺寸小于或等于第一部104a的第一端面S1的截面尺寸。
并且，由于刻蚀形成预制沟槽1034的工艺，相较于刻蚀形成第一空腔E1的工艺更为简化，因此，通过设置第一空腔E1沿第三方向Z的深度，小于或等于预制沟槽1034沿第三方向Z的深度，可简化制备工艺，降低工艺难度，从而使得第一部104a的高度H1小于或等于第二部104b的高度H2。
示例性地，参见图6D，上述S403包括如下S4031～S4034：
S4031：如图7I所示，经由预制沟槽1034的底部，对牺牲栅1031进行第一次侧向刻蚀。
例如，可采用干法刻蚀工艺，对牺牲栅1031进行第一次侧向刻蚀。
需要说明的是，上述干法刻蚀工艺可具有较高的方向性，也可无方向性，其所采用的刻蚀气体对牺牲栅1031(多晶硅)的刻蚀选择比，大于该刻蚀气体对保护层K2的刻蚀选择比。该干法刻蚀工艺所采用的刻蚀气体例如可以是氧气、甲烷、氟甲烷、二氟甲烷或含氟烃类化合物(CHxFy)。
基于此，采用上述干法刻蚀工艺，沿第三方向Z，竖直向下刻蚀牺牲栅1031的过程中，刻蚀副产物携带高能离子发生侧向回溅，会沿侧向刻蚀牺牲栅1031，形成图7I示出的凹槽D。
并且，预制沟槽1034的底部在衬底100上的正投影，位于该凹槽D在衬底100上的正投影的范围内，即对牺牲栅1031进行的第一次侧向刻蚀，将与保护层K2的底部接触的牺牲栅1031去除，使保护层K2的底部不与牺牲栅1031相接触，该步骤可 保证后续形成的栅切断结构104中，第一部104a与第二部104b的连接处平滑过渡。
此外，本申请的实施例不局限于采用干法刻蚀工艺，对牺牲栅1031进行第一次侧向刻蚀，例如，还可采用化学刻蚀工艺，或采用湿法刻蚀工艺。
S4032：如图7J所示，沿第三方向Z，向下刻蚀牺牲栅1031至介质薄膜102a，以形成暴露介质薄膜102a的通孔F。
例如，可采用干法刻蚀工艺，向下刻蚀牺牲栅1031至介质薄膜102a。
需要说明的是，上述干法刻蚀工艺可具有较高的方向性，其所采用的刻蚀气体例如可以是溴化氢或氯气。
S4033：如图7K所示，刻蚀介质薄膜102a以形成第二空腔E2，第二空腔E2暴露牺牲栅1031靠近介质薄膜102a一侧的表面。
例如，可采用干法刻蚀工艺，向下刻蚀介质薄膜102a的同时，侧向刻蚀介质薄膜102a，以形成第二空腔E2。
需要说明的是，上述干法刻蚀工艺可具有较低的方向性，也可无方向性，其所采用的刻蚀气体例如可以是稀释的氟化氢。
此外，本申请的实施例不局限于采用干法刻蚀工艺刻蚀介质薄膜102a，例如，还可采用化学刻蚀工艺，或采用湿法刻蚀工艺。
继续参见图7K，第二空腔E2与通孔F相连，且通孔F与第二空腔E2相连的开口在衬底100上的正投影，位于第二空腔E2在衬底100上的正投影的范围内，以通过第二空腔E2暴露牺牲栅1031靠近介质薄膜102a一侧的表面，以便于后续对牺牲栅1031进行第二次侧向刻蚀的过程中，可提高对第二空腔E2所暴露的牺牲栅1031的部分的刻蚀速率，且该刻蚀速率大于，对通孔F所暴露的牺牲栅1031的部分的刻蚀速率，从而使最终刻蚀形成的第一空腔E1的截面形状呈梯形或锥形，使第一部104a的截面形状为梯形或锥形。
S4034：如图7L所示，对牺牲栅1031进行第二次侧向刻蚀，以形成第一空腔E1。
例如，可采用干法刻蚀工艺，对牺牲栅1031进行第二次侧向刻蚀，以形成第一空腔E1。
需要说明的是，上述干法刻蚀工艺可具有较低的方向性，也可无方向性，其所采用的刻蚀气体例如可以是三氟化氮。
结合图7K和图7L，由于第二空腔E2暴露牺牲栅1031更多的表面，在对牺牲栅1031进行第二次侧向刻蚀的过程中，牺牲栅1031靠近第二空腔E2的一侧与刻蚀气体的接触面积较大，从而对第二空腔E2所暴露的牺牲栅1031的部分的刻蚀速率，大于对通孔F所暴露的牺牲栅1031的部分的刻蚀速率，使第一空腔E1的截面形状呈梯形或锥形。
并且，如图7L所示，该第二空腔E2位于第一空腔E1靠近衬底100的一侧，且与第一空腔E1相连。第一空腔E1包括与第二空腔E2相连的第三开口V3，第二空腔E2在衬底100上的正投影，位于第三开口V3在衬底100上的正投影的范围内，即第二空腔E2的截面尺寸小于或等于第三开口V3的截面尺寸。
需要说明的是，栅切断结构104的第一部104a形成于第一空腔E1内，第三部104c形成于第二空腔E2内。并且，由于第二空腔E2的截面尺寸小于或等于第一空腔E1 的第三开口V3的截面尺寸，使得第三部104c的截面尺寸小于或等于第一部104a的第三端面S3的截面尺寸。
S50：如图7M和图7N所示，在栅切断沟槽1033内形成栅切断结构104。
示例性地，参见图6E，上述S50可包括如下S501～S502：
S501：如图7M所示，在栅切断沟槽1033内，及保护层K2远离衬底100的表面沉积电介质材料110。
需要说明的是，在沉积电介质材料110的过程中，通过控制电介质材料110在栅切断沟槽1033的侧壁的沉积速率，大于或等于电介质材料110在栅切断沟槽1033的底部的沉积速率，使得栅切断沟槽1033的顶部被电介质材料110密封的情况下，电介质材料110在栅切断沟槽1033的底部的沉积量不足，从而在栅切断沟槽1033的底部形成孔隙109。
S502：结合图7M和图7N，去除位于保护层K2远离衬底100的表面的电介质材料110，保护层K2中覆盖牺牲层103远离衬底100的表面的部分，以及硬掩膜层L1，以将牺牲层103的顶面暴露，电介质材料110保留的部分和保护层K2中覆盖预制沟槽1034的侧壁的部分共同形成栅切断结构104。
例如，可采用化学机械研磨(Chemical Mechanical Polishing，CMP)工艺，研磨图7M中示出的结构的顶部，以将位于结构顶部的电介质材料110、保护层K2和硬掩膜层L1去除，暴露出牺牲层103的顶面。
以上各实施例所提供的集成电路10的制备方法，属于集成电路10的多晶闸极线路工艺和多晶闸极切断工艺，描述了栅切断结构104的制备方法。
接下来，本申请的一些实施例所提供的集成电路10的制备方法，将描述集成电路10的替代金属栅工艺和多重功函数工艺，图8为根据一些实施例的替代金属栅工艺和多重功函数工艺的流程图；图9A～图9H为根据一些实施例的替代金属栅工艺和多重功函数工艺的各步骤图。
参见图8，集成电路10的制备方法还包括如下S60～S90：
S60：如图9A所示，去除牺牲层103中的牺牲栅1031，以在绝缘层1032中形成栅线沟槽1035，该栅线沟槽1035暴露介质薄膜102a。
S70：如图9B所示，经由栅线沟槽1035，去除介质薄膜102a的覆盖鳍101的部分，形成介质层102。
S80：如图9C～图9G所示，在栅线沟槽1035内形成功函数层108，图9G示出了最终形成的功函数层108。
示例性地，上述S80包括如下步骤：
如图9C所示，在栅线沟槽1035内依次形成功能叠层，例如，该功能叠层包括依次层叠设置的层间介质层105、高介电常数层106、刻蚀停止层107和功函数薄膜1080。
如图9D所示，在栅线沟槽1035内形成填充层111，然后在填充层111远离衬底100的一侧形成第四掩膜层L4，且第四掩膜层L4位于第一器件区A1。
示例性地，可采用旋转镀膜(Spin On Coating，SOC)工艺，在栅线沟槽1035内形成填充层111。
示例性地，填充层111的材料可包括高分子材料，例如，填充层111的材料可包 括光刻胶。
如图9E所示，以第四掩膜层L4为掩膜，刻蚀去除填充层111位于第二器件区A2的部分，保留填充层111位于第一器件区A1的部分，以暴露功函数薄膜1080位于第二器件区A2的部分。
可以理解的是，通过栅切断结构104的结构设计，栅切断结构104的第一部104a的截面形状为梯形或锥形，或者，第一部104a的侧面C为向子栅线103a凸起的弧面，且夹角β为钝角(大于90°)，使得夹角β区域没有内陷，填充层111靠近夹角β的部分易被去除干净。
并且，通过设置栅切断结构104的第一部104a与第二部104b的连接处N平滑过渡，使得填充层111靠近连接处N的部分易被去除干净。
如图9F所示，以第四掩膜层L4和填充层111位于第一器件区A1的部分为掩膜，刻蚀去除功函数薄膜1080位于第二器件区A2的部分，刻蚀停止于刻蚀停止层107，保留功函数薄膜1080位于第一器件区A1的部分，得到功函数层108。
可以理解的是，由于填充层111靠近夹角β和连接处N的部分被去除干净，使得功函数薄膜1080靠近夹角β和连接处N的部分易被去除干净，以形成功函数层108，从而提高集成电路10的器件的良率。
如图9G所示，去除第四掩膜层L4和填充层111位于第一器件区A1的部分，以将栅线沟槽1035完全暴露。
S90：如图9H所示，在栅线沟槽1035内填充导电材料，以形成栅线103A。
本申请的一些实施例所提供的电子设备1，包括上述任一实施例所提供的集成电路10，其所能达到的有益效果可参考上文中集成电路10的有益效果，此处不再赘述。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。

Claims (18)

  1. 一种集成电路，其特征在于，包括：
    衬底；
    鳍，设置于所述衬底上，且沿平行于所述衬底的第一方向延伸；
    栅线，沿平行于所述衬底的第二方向延伸，所述第二方向与所述第一方向相交叉；所述栅线跨设在所述鳍上；
    栅切断结构，沿所述第一方向延伸，并将所述栅线切割成多条子栅线；
    其中，所述栅切断结构包括相连的第一部和第二部，所述第二部位于所述第一部远离所述衬底的一侧；
    所述第一部包括与所述第二部相连的第一端面，所述第二部包括与所述第一部相连的第二端面，所述第二端面在所述衬底上的正投影，位于所述第一端面在所述衬底上的正投影的范围内；
    沿由所述第二部指向所述第一部的方向，所述第一部沿参考面的截面在所述第二方向上的尺寸由小变大；所述参考面垂直于所述衬底，且与所述第一方向垂直。
  2. 根据权利要求1所述的集成电路，其特征在于，所述集成电路还包括设置于所述衬底与所述栅线之间的介质层；
    所述第一部靠近所述子栅线的侧面中，远离所述第二部的边缘的切面，与所述介质层远离所述衬底一侧的表面之间的夹角为钝角。
  3. 根据权利要求1或2所述的集成电路，其特征在于，所述第一部沿所述参考面的截面形状为梯形或锥形；或者，
    所述第一部靠近所述子栅线的侧面为向所述子栅线凸起的弧面。
  4. 根据权利要求1～3中任一项所述的集成电路，其特征在于，所述第一部与所述第二部的连接处平滑过渡。
  5. 根据权利要求1～4中任一项所述的集成电路，其特征在于，沿垂直于所述衬底的第三方向，所述第一部的高度小于或等于所述第二部的高度。
  6. 根据权利要求1～5中任一项所述的集成电路，其特征在于，所述第一部中具有孔隙，所述孔隙沿所述第一方向延伸。
  7. 根据权利要求1～6中任一项所述的集成电路，其特征在于，所述集成电路还包括设置于所述衬底与所述栅线之间的介质层；
    所述栅切断结构还包括第三部，所述第三部位于所述第一部靠近所述衬底的一侧，且与所述第一部相连；所述第三部位于所述介质层内。
  8. 根据权利要求7所述的集成电路，其特征在于，所述第一部包括与所述第三部相连的第三端面，所述第三部在所述衬底上的正投影，位于所述第三端面在所述衬底上的正投影的范围内。
  9. 根据权利要求1～8中任一项所述的集成电路，其特征在于，所述集成电路包括第一器件区和第二器件区，所述第一器件区被配置为设置P型晶体管，所述第二器件区被配置为设置N型晶体管；
    所述集成电路还包括功函数层，所述功函数层设置于所述子栅线与所述鳍之间， 及所述子栅线与所述栅切断结构之间；
    所述功函数层中位于所述第一器件区的部分的厚度，大于所述功函数层中位于所述第二器件区的部分的厚度。
  10. 一种集成电路的制备方法，其特征在于，包括：
    在衬底上形成鳍，所述鳍沿平行于所述衬底的第一方向延伸；
    形成介质薄膜，所述介质薄膜覆盖所述衬底和所述鳍；
    在所述介质薄膜上形成牺牲层，所述牺牲层包括牺牲栅，所述牺牲栅沿平行于所述衬底的第二方向延伸，所述第二方向与所述第一方向相交叉；所述牺牲栅跨设在所述鳍上；
    在所述牺牲层中形成栅切断沟槽，所述栅切断沟槽沿所述第一方向延伸；
    在所述栅切断沟槽内形成栅切断结构；
    其中，所述栅切断结构包括相连的第一部和第二部，所述第二部位于所述第一部远离所述衬底的一侧；
    所述第一部包括与所述第二部相连的第一端面，所述第二部包括与所述第一部相连的第二端面，所述第二端面在所述衬底上的正投影，位于所述第一端面在所述衬底上的正投影的范围内；
    沿由所述第二部指向所述第一部的方向，所述第一部沿参考面的截面在所述第二方向上的尺寸由小变大；所述参考面垂直于所述衬底，且与所述第一方向垂直。
  11. 根据权利要求10所述的制备方法，其特征在于，所述在所述牺牲层中形成栅切断沟槽，包括：
    在所述牺牲层中形成预制沟槽；
    在所述预制沟槽的侧壁上形成保护层，所述保护层暴露所述预制沟槽的底部；
    经由所述预制沟槽的底部，向下刻蚀所述牺牲栅至所述介质薄膜，并侧向刻蚀所述牺牲栅以形成第一空腔；
    其中，所述第一空腔包括与所述预制沟槽相连的第一开口，所述预制沟槽包括与所述第一空腔相连的第二开口，所述第二开口在所述衬底上的正投影，位于所述第一开口在所述衬底上的正投影的范围内。
  12. 根据权利要求11所述的制备方法，其特征在于，所述向下刻蚀所述牺牲栅至所述介质薄膜，并侧向刻蚀所述牺牲栅以形成第一空腔，包括：
    经由所述预制沟槽的底部，对所述牺牲栅进行第一次侧向刻蚀；
    向下刻蚀所述牺牲栅至所述介质薄膜；
    对所述牺牲栅进行第二次侧向刻蚀。
  13. 根据权利要求12所述的制备方法，其特征在于，所述对所述牺牲栅进行第一次侧向刻蚀，包括：
    采用干法刻蚀工艺，对所述牺牲栅进行第一次侧向刻蚀；
    其中，所述干法刻蚀工艺所采用的刻蚀气体对所述牺牲栅的刻蚀选择比，大于所述刻蚀气体对所述保护层的刻蚀选择比。
  14. 根据权利要求12或13所述的制备方法，其特征在于，所述向下刻蚀所述牺牲栅至所述介质薄膜之后，所述对所述牺牲栅进行第二次侧向刻蚀之前，还包括：
    刻蚀所述介质薄膜以形成第二空腔，所述第二空腔暴露所述牺牲栅靠近所述介质薄膜一侧的表面。
  15. 根据权利要求11～14中任一项所述的制备方法，其特征在于，所述在所述预制沟槽的侧壁上形成保护层，包括：
    形成保护薄膜，所述保护薄膜覆盖所述牺牲层远离所述衬底的一侧，以及所述预制沟槽的侧壁和底部；
    去除所述保护薄膜中覆盖所述预制沟槽的底部的部分，形成所述保护层。
  16. 根据权利要求15所述的制备方法，其特征在于，所述在所述栅切断沟槽内形成栅切断结构，包括：
    在所述栅切断沟槽内，及所述保护层远离所述衬底的表面沉积电介质材料；
    去除位于所述保护层远离所述衬底的表面的电介质材料，以及所述保护层中覆盖所述牺牲层远离所述衬底的表面的部分，所述电介质材料保留的部分和所述保护层中覆盖所述预制沟槽的侧壁的部分形成所述栅切断结构。
  17. 根据权利要求10～16中任一项所述的制备方法，其特征在于，所述集成电路包括第一器件区和第二器件区，所述第一器件区被配置为设置P型晶体管，所述第二器件区被配置为设置N型晶体管；
    所述牺牲层包括所述牺牲栅和绝缘层，多条所述牺牲栅沿第一方向排列，所述绝缘层位于相邻两条牺牲栅之间；
    所述在所述栅切断沟槽内形成栅切断结构之后，还包括：
    去除所述牺牲层中的牺牲栅，以在所述绝缘层中形成栅线沟槽；
    经由所述栅线沟槽，去除所述介质薄膜的覆盖所述鳍的部分，形成介质层；
    在所述栅线沟槽内形成功函数层；所述功函数层中位于所述第一器件区的部分的厚度，大于所述功函数层中位于所述第二器件区的部分的厚度；
    在所述栅线沟槽内填充导电材料，以形成栅线。
  18. 一种电子设备，其特征在于，包括：
    电路板；
    如权利要求1～9中任一项所述的集成电路，所述集成电路设置于所述电路板上，且与所述电路板电连接。
PCT/CN2023/100295 2022-07-01 2023-06-14 集成电路及其制备方法、电子设备 WO2024001801A1 (zh)

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