WO2023216285A1 - 显示面板 - Google Patents

显示面板 Download PDF

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Publication number
WO2023216285A1
WO2023216285A1 PCT/CN2022/093553 CN2022093553W WO2023216285A1 WO 2023216285 A1 WO2023216285 A1 WO 2023216285A1 CN 2022093553 W CN2022093553 W CN 2022093553W WO 2023216285 A1 WO2023216285 A1 WO 2023216285A1
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WO
WIPO (PCT)
Prior art keywords
display panel
signal line
gate
transistor
metal
Prior art date
Application number
PCT/CN2022/093553
Other languages
English (en)
French (fr)
Inventor
鲁凯
Original Assignee
武汉华星光电半导体显示技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 武汉华星光电半导体显示技术有限公司 filed Critical 武汉华星光电半导体显示技术有限公司
Priority to US17/789,558 priority Critical patent/US20230380217A1/en
Publication of WO2023216285A1 publication Critical patent/WO2023216285A1/zh

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1216—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/126—Shielding, e.g. light-blocking means over the TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals

Definitions

  • the present application relates to the field of display technology, and in particular, to a display panel.
  • OLED Organic Light-Emitting Diode, organic light-emitting diode
  • OLED display devices are widely used due to their advantages of self-luminescence and flexibility.
  • Existing OLED display devices use drive circuits based on LTPS (Low Temperature Poly-silicon) technology to drive pixels.
  • LTPS Low Temperature Poly-silicon
  • the transistor connected to the gate of the drive transistor is a double-gate design.
  • Transistors, the semiconductor pattern located between the double-gate structure is easily coupled by other signals, resulting in a higher potential, leakage to the driving transistor during the light-emitting phase, resulting in changes in display brightness within one frame, and obvious flickering during low-frequency display.
  • An embodiment of the present application provides a display panel. It is used to alleviate the technical problem in existing OLED display devices that leakage of the double-gate transistor connected to the gate of the driving transistor causes display flicker in the OLED display device.
  • An embodiment of the present application provides a display panel, which includes a plurality of light-emitting devices arranged in an array and a pixel driving circuit that drives the light-emitting devices.
  • the pixel driving circuit includes:
  • the first initialization transistor is connected to the first initialization signal line and is used to input the first initialization signal to the first node under the control of the first scan signal;
  • a switching transistor used to input a data signal to the second node under the control of the second scan signal
  • a driving transistor used to drive the light-emitting device to emit light under the control of the potential of the first node and the second node;
  • a compensation transistor connected to the driving transistor through the first node and the third node, for compensating the threshold voltage of the driving transistor under the control of the third scan signal
  • the compensation transistor includes a connected first gate and a second gate
  • the first initialization transistor includes a connected third gate and a fourth gate
  • the display panel further includes a shielding metal located on the A shield is provided on at least one of the first active pattern between the first gate and the second gate and the second active pattern between the third gate and the fourth gate. Metal.
  • a shielding metal is provided on the first active pattern between the first gate electrode and the second gate electrode, or between the third gate electrode and the fourth gate electrode.
  • a shielding metal is provided on the second active pattern between the two active patterns.
  • a shielding metal is provided on the first active pattern between the first gate electrode and the second gate electrode.
  • a shielding metal is provided on the second active pattern between the third gate and the fourth gate.
  • a first shielding metal is disposed on the first active pattern between the first gate and the second gate, and a first shielding metal is disposed on the third gate and the fourth gate.
  • a second shielding metal is disposed on the second active pattern therebetween.
  • the display panel further includes a ground terminal, and at least one of the first shielding metal and the second shielding metal is connected to the ground terminal.
  • the first shield metal is connected to the ground terminal.
  • the second shield metal is connected to the ground terminal.
  • the first shielding metal is connected to the ground terminal, and the second shielding metal is connected to the ground terminal.
  • the pixel driving circuit further includes a second initialization transistor, the second initialization transistor is connected to a second initialization signal line, and is used to input an anode to the light-emitting device under the control of a fourth scan signal. second initialization signal;
  • the first light-emitting control transistor is connected to the driving transistor through the second node, and is used to conduct current from the high-potential signal line of the power supply to the driving transistor under the control of the light-emitting control signal;
  • a second light-emitting control transistor is connected to the driving transistor through a third node, and is used to conduct the current flowing from the driving transistor to the anode of the light-emitting device under the control of the light-emitting control signal;
  • the first shielding metal is connected to one of the first initialization signal line and the second initialization signal line
  • the second shielding metal is connected to the first initialization signal line and the second initialization signal line. A connection in the line.
  • the first shielding metal is connected to the second initialization signal line, and the second shielding metal is connected to the first initialization signal line.
  • the display panel includes:
  • the pixel driving circuit layer includes multiple pixel driving circuits
  • the pixel driving circuit includes a semiconductor layer, a first metal layer, a second metal layer and a third metal layer that are sequentially stacked on the substrate, and the display panel further includes a semiconductor layer located on the semiconductor layer and the a first interlayer dielectric layer between the first metal layer, a second interlayer dielectric layer between the first metal layer and the second metal layer, a second interlayer dielectric layer between the second metal layer and the third metal layer.
  • An interlayer insulating layer between metal layers, the semiconductor layer includes the first active pattern and the second active pattern, the first metal layer includes a first gate, a second gate, a third At least one of the gate electrode and the fourth gate electrode, the second metal layer and the third metal layer is provided with a shielding metal.
  • the display panel is provided with a first via hole passing through the interlayer insulating layer, the second metal layer includes a first portion of a second initialization signal line and a first shielding metal, and the second The three-metal layer includes a second portion of the second initialization signal line;
  • the first shielding metal passes through the first via hole and is connected to the second part of the second initialization signal line
  • the second part of the second initialization signal line passes through the first through hole and is connected to the second part of the second initialization signal line.
  • the first part of the second initialization signal line is connected.
  • the display panel is provided with a second via hole passing through the first interlayer dielectric layer, the second interlayer dielectric layer and the interlayer insulating layer, and the second initialization signal A second portion of the line passes through the second via hole and is connected to the second active pattern.
  • the display panel is provided with a third via hole passing through the interlayer insulation layer, the second metal layer includes a second shielding metal, and the third metal layer includes a first initialization signal line. ;
  • the first initialization signal line passes through the third via hole and is connected to the second shielding metal.
  • the display panel is provided with a fourth via hole passing through the interlayer insulating layer, the second metal layer includes a first part of a second initialization signal line, and the third metal layer includes a two initializing the second part of the signal line and the first shielding metal;
  • the first shielding metal is connected to the second part of the second initialization signal line, and the second part of the second initialization signal line passes through the fourth via hole and the second initialization signal line.
  • the first part connects.
  • the third metal layer forms a source electrode and a drain electrode.
  • the pixel driving circuit further includes a storage capacitor, one end of the storage capacitor is connected to the power high potential signal line, and the other end of the storage capacitor is connected to the first node.
  • the first initialization transistor is a low-temperature polysilicon thin film transistor
  • the compensation transistor is a low-temperature polysilicon thin film transistor
  • the first gate and the second gate are on the first active pattern. There is a spacing between projections of the third gate electrode and the fourth gate electrode on the second active pattern.
  • adjacent pixel driving circuits arranged laterally are arranged symmetrically, the first initialization transistors in the adjacent pixel driving circuits are connected to the same initialization signal line, and the compensation transistors in the adjacent pixel driving circuits are connected to the same scan line.
  • the present application provides a display panel; the display panel includes a plurality of light-emitting devices arranged in an array and a pixel driving circuit for driving the light-emitting devices.
  • the pixel driving circuit includes a first initialization transistor, a switching transistor, a driving transistor and a compensation transistor.
  • the first initialization transistor Connected to the first initialization signal line, used to input the first initialization signal to the first node under the control of the first scan signal, and the switching transistor is used to input the data signal to the second node under the control of the second scan signal,
  • the driving transistor is used to drive the light-emitting device to emit light under the control of the potential of the first node and the second node
  • the compensation transistor is connected to the driving transistor through the first node and the third node, and is used to compensate for driving under the control of the third scan signal.
  • the threshold voltage of the transistor wherein the compensation transistor includes a connected first gate and a second gate, the first initialization transistor includes a connected third gate and a fourth gate, and the display panel also includes a shielding metal located on the first gate
  • a shielding metal is provided on at least one of the first active pattern between the gate electrode and the second gate electrode and the second active pattern between the third gate electrode and the fourth gate electrode.
  • the present application provides a shielding metal on at least one of the first active pattern located between the first gate electrode and the second gate electrode and the second active pattern located between the third gate electrode and the fourth gate electrode,
  • the shielding metal can shield the coupling effect of other signals on the first active pattern and the second active pattern, and increase the parasitic capacitance of the first active pattern and the second active pattern. Even if the first active pattern and the second active pattern
  • the active pattern can also reduce potential changes due to coupling effects, thereby reducing leakage to the gate of the driving transistor and improving the problem of display flicker.
  • FIG. 1 is a circuit diagram of a display panel provided by an embodiment of the present application.
  • Figure 2 is a first perspective view of a display panel provided by an embodiment of the present application.
  • FIG. 3 is a cross-sectional view of the perspective view in FIG. 2 .
  • FIG. 4 is an exploded view of the semiconductor layer of the display panel in FIG. 2 .
  • FIG. 5 is an exploded view of the first metal layer of the display panel in FIG. 2 .
  • FIG. 6 is an exploded view of the second metal layer of the display panel in FIG. 2 .
  • FIG. 7 is an exploded view of the third metal layer of the display panel in FIG. 2 .
  • FIG. 8 is a second perspective view of the display panel provided by the embodiment of the present application.
  • Figure 9 is a third perspective view of a display panel provided by an embodiment of the present application.
  • Embodiments of the present application address the technical problem that existing OLED display devices have leakage from the double-gate transistor connected to the gate of the driving transistor, causing display flicker in the OLED display device.
  • a display panel and a display device are provided to alleviate the above technical problem.
  • embodiments of the present application provide a display panel, which includes a plurality of light-emitting devices LED arranged in an array and a pixel driving circuit that drives the light-emitting device LEDs.
  • the pixel driving circuit Circuit includes:
  • the first initialization transistor T4 is connected to the first initialization signal line and is used to input the first initialization signal to the first node Q under the control of the first scan signal;
  • the switching transistor T2 is used to input a data signal to the second node A under the control of the second scan signal;
  • the drive transistor Drive TFT is used to drive the light-emitting device LED to emit light under the control of the potential of the first node Q and the second node A;
  • the compensation transistor T3 is connected to the drive transistor Drive TFT through the first node Q and the third node B, and is used to compensate the threshold voltage of the drive transistor Drive TFT under the control of the third scan signal;
  • the compensation transistor T3 includes a connected first gate and a second gate
  • the first initialization transistor T4 includes a connected third gate and a fourth gate
  • the display panel also includes a shielding metal (eg The first shield metal 161 in FIG. 2), the first active pattern 121 between the first gate electrode and the second gate electrode and the first active pattern 121 between the third gate electrode and the fourth gate electrode.
  • a shielding metal is provided on at least one of the second active patterns 122 (for example, a first shielding metal 161 is provided on the first active pattern 121 in FIG. 3 ).
  • Embodiments of the present application provide a display panel, which uses a first active pattern located between a first gate electrode and a second gate electrode and a second active pattern located between a third gate electrode and a fourth gate electrode.
  • a shielding metal is provided on at least one of the source patterns, so that the shielding metal can shield the coupling effect of other signals on the first active pattern and the second active pattern, and increase the parasitic capacitance of the first active pattern and the second active pattern. , even if the first active pattern and the second active pattern are coupled, the potential change can be reduced, thereby reducing leakage to the gate of the driving transistor and improving the problem of display flicker.
  • the two gates of the compensation transistor T3 are connected. Therefore, in Figures 1 and 2, the first gate and the second gate are actually one gate. Take Figure 2 as an example.
  • the first gate and the second gate are two parts of the gate that are perpendicular to each other. Therefore, the first gate and the second gate are not specifically marked.
  • the third gate electrode and the fourth gate electrode of the first initialization transistor T4 are also two parts of the gate electrode that are perpendicular to each other.
  • the active pattern includes two portions that overlap with the projection of the gate of the transistor and a portion between the overlapping portions.
  • the projections of the first active pattern and the gate of the compensation transistor T3 overlap, and it can be known that the first active pattern between the first gate and the second gate
  • the source pattern refers to another part located between the two parts where the projection of the first active pattern coincides with the gate of the compensation transistor T3; similarly, it can be seen that the second active pattern located between the third gate and the fourth gate
  • the source pattern refers to another part located between two parts of the second active pattern that coincide with the projection of the gate of the first initialization transistor T4.
  • a shielding metal is provided on the first active pattern between the first gate and the second gate, or a shielding metal is provided on the third gate and the fourth gate. A shielding metal is provided on the second active pattern between them.
  • a shielding metal 26 is provided on the first active pattern between the first gate and the second gate.
  • a shielding metal is provided on the first active pattern between them, so that the shielding metal shields the coupling effect of other signals on the first active pattern, and at the same time increases the parasitic capacitance of the first active pattern, so that even if other signals occur, the coupling effect on the first active pattern will be increased.
  • the coupling effect of the pattern can also reduce the potential change, reduce the leakage of the compensation transistor to the gate of the driving transistor, reduce the display brightness change within one frame, and improve the problem of low-frequency display flicker.
  • a shielding metal 26 is provided on the second active pattern between the third gate and the fourth gate.
  • a shielding metal is provided on the second active pattern between them, so that the shielding metal shields the coupling effect of other signals on the second active pattern, and at the same time increases the parasitic capacitance of the second active pattern, so that even if other signals occur, the coupling effect of the second active pattern on the second active pattern will be increased.
  • the coupling effect of the pattern can also reduce the potential change, reduce the leakage of the first initialization transistor to the gate of the driving transistor, reduce the display brightness change within one frame, and improve the problem of low-frequency display flicker.
  • a first shielding metal 161 is provided on the first active pattern 121 between the first gate and the second gate.
  • a second shielding metal 163 is provided on the second active pattern 122 between the third gate electrode and the fourth gate electrode.
  • the display panel further includes a ground terminal, and at least one of the first shielding metal and the second shielding metal is connected to the ground terminal.
  • the first shielding metal is connected to the ground terminal, or the second shielding metal is connected to the ground terminal, or the first shielding metal is connected to the ground terminal, and the second shielding metal is connected to the ground terminal. to the ground terminal.
  • the potential of the second active pattern prevents the potential there from being coupled too high or too low by other signals, thereby reducing the voltage difference between the source and drain of the drive transistor and reducing the leakage current; by reducing the drive
  • the leakage current of the transistor and the first initialization transistor reduces the brightness change of the display panel in one frame and improves display flicker.
  • the pixel driving circuit further includes a second initialization transistor T7, and the second initialization transistor T7 is connected to the second initialization signal line VI-2, For inputting a second initialization signal to the LED anode of the light-emitting device under the control of the fourth scan signal;
  • the first light-emitting control transistor T5 is connected to the drive transistor Drive TFT through the second node A, and is used to conduct the current of the power high-potential signal line VDD to the drive transistor Drive TFT under the control of the light-emitting control signal;
  • the second light emitting control transistor T6 is connected to the driving transistor Drive TFT through the third node B, and is used to turn on the driving transistor Drive under the control of the light emitting control signal.
  • the first shielding metal 161 is connected to one of the first initialization signal line 191 and the second initialization signal line
  • the second shielding metal is connected to the first initialization signal line 191 and the second initialization signal line.
  • the first initialization signal line is labeled VI-1, and in the cross-sectional view shown in Figure 3, the first initialization signal line is labeled 191.
  • VI-1 the first initialization signal line
  • the first initialization signal line in the circuit diagram shown in Figure 1 corresponds to the first initialization signal line in the cross-sectional view shown in Figure 3.
  • other circuit diagrams and cross-sectional diagrams Components with different marking methods are also the same component and will not be described again here.
  • Figure 4 is a perspective view of the semiconductor layer in Figure 3
  • Figure 5 is a perspective view of the first metal layer in Figure 3
  • Figure 6 is a perspective view of the second metal layer in Figure 3
  • Figure 7 is a perspective view of the third metal layer in Figure 3.
  • the first shielding metal 161 is connected to the second initialization signal line VI-2, and the second shielding metal 163 is connected to the first initialization signal line VI-2. -1 connection. Since the compensation transistor in a single sub-pixel is close to the second initialization signal line, the first initialization transistor is close to the first initialization signal line, so that the first shielding metal is connected to the second initialization signal line, and the first initialization transistor is connected to the first initialization signal line, Therefore, the length of the first shield metal connection trace can be shortened, and the complexity of the film layer structure and the film layer connection structure can be reduced.
  • the display panel includes:
  • the pixel driving circuit layer includes multiple pixel driving circuits
  • the pixel driving circuit includes a semiconductor layer, a first metal layer, a second metal layer and a third metal layer that are sequentially stacked on the substrate, and the semiconductor layer includes the first active pattern and the The second active pattern, the first metal layer includes a first gate, a second gate, a third gate and a fourth gate, the display panel further includes a shielding metal layer, the shielding metal layer forms There is shielding metal.
  • the display panel includes:
  • the pixel driving circuit layer includes multiple pixel driving circuits
  • the pixel driving circuit includes a semiconductor layer 12, a first metal layer 14, a second metal layer 16 and a third metal layer 19 that are sequentially stacked on the substrate 11.
  • the display panel also includes a semiconductor layer located on the substrate 11.
  • the interlayer insulating layer 17 between the second metal layer 16 and the third metal layer 19, the semiconductor layer 12 includes the first active pattern 121 and the second active pattern 122, the
  • the first metal layer 14 includes a first gate, a second gate, a third gate and a fourth gate, and at least one of the second metal layer 16 and the third metal layer 19 is provided with a shielding metal.
  • the display panel is provided with a first via hole 181 that passes through the interlayer insulating layer 17, so
  • the second metal layer 16 includes a first portion 162 of the second initialization signal line VI-2 and a first shielding metal 161, and the third metal layer 19 includes a second portion of the second initialization signal line VI-2;
  • the first shielding metal 161 passes through the first via hole 181 and is connected to the second part of the second initialization signal line VI-2, and the second part of the second initialization signal line VI-2 passes through The first via hole 181 is connected to the first part 181 of the second initialization signal line VI-2.
  • FIG. 3 is a cross-sectional view from the compensation transistor to the second initialization signal line in Figure 2. Therefore, (a) in Figure 3 does not show the source and drain of the compensation transistor, and Regarding the first gate electrode and the second gate electrode of the compensation transistor, due to the cross-section, only a part of the first gate electrode and the second gate electrode can be shown with the reference numeral 141, and the light emission control signal line EM(n) is marked with the reference numeral 142. ). Similarly, (b) in FIG. 3 only shows a part of the third gate and the fourth gate with reference numeral 143, and since (a) in FIG. 3 only shows a part of the third metal layer 19, the The portion is a connecting portion between the first shielding metal and the first portion of the second initialization signal line. Therefore, this portion can serve as the second portion of the second initialization signal line.
  • the display panel is provided with an interlayer through the first interlayer dielectric layer 13, the second The second via hole 182 of the interlayer dielectric layer 15 and the interlayer insulating layer 17, the second part of the second initialization signal line VI-2 passes through the second via hole 182 and the second active pattern 122 connections.
  • the second initialization signal line can reset the gate of the first initialization transistor, thereby preventing the first initialization transistor from causing a high gate potential caused by the first initialization transistor.
  • the initialization transistor remains on, affecting the gate potential of the drive transistor.
  • the display panel is provided with a third via hole 183 that passes through the interlayer insulating layer 17.
  • the second metal layer includes a second shielding metal 163, and the third metal layer includes a first initialization signal line 191;
  • the first initialization signal line 191 passes through the third via hole 183 and is connected to the second shielding metal 163 .
  • the distance between the second shielding metal and the second active pattern of the first initialization transistor is closer, so that the formed capacitance is larger, and the second shielding metal is more sensitive to the second active pattern.
  • the shielding effect of the pattern is better, reducing the leakage of the first initialization transistor and improving the flicker of the display panel.
  • the display panel is provided with a fourth via hole passing through the interlayer insulating layer, the second metal layer includes a first part of the second initialization signal line, and the third metal layer includes a second portion of the second initialization signal line and the first shield metal;
  • the first shielding metal is connected to the second part of the second initialization signal line, and the second part of the second initialization signal line passes through the fourth via hole and the second initialization signal line.
  • the first part connects.
  • the passing third metal layer forms the first shielding metal, so that the first shielding metal can be directly connected to the second initialization signal line without forming a via hole, and does not need to occupy the space of the second metal layer, reducing process difficulty.
  • the first initialization transistor is a low-temperature polysilicon thin film transistor
  • the compensation transistor is a low-temperature polysilicon thin film transistor
  • the first gate and the second gate are in the first active pattern.
  • adjacent pixel drive circuits arranged laterally are arranged symmetrically, the first initialization transistor in the adjacent pixel drive circuit is connected to the same initialization signal line, and the compensation transistor in the adjacent pixel drive circuit is connected to the same scan line. .
  • the horizontally arranged pixel driving circuits are arranged symmetrically, sharing some electrodes and metal wiring in the two pixel driving circuits, reducing the space occupied by a single sub-pixel, and reducing the display cost.
  • the process difficulty of the panel is a simple matter of the panel.
  • the first metal layer forms a gate electrode
  • the second metal layer forms a plate of a capacitor
  • the third metal layer forms a source electrode and a drain electrode
  • the pixel driving circuit further includes a storage capacitor Cst.
  • One end of the storage capacitor Cst is connected to the power high potential signal line VDD, and the other end of the storage capacitor Cst is connected to the power supply high potential signal line VDD.
  • the first node Q connection is not limited to the storage capacitor Cst.
  • the data line Data transmits data signals
  • the first initialization signal line VI-1 transmits the first initialization signal
  • the second initialization signal line VI-2 transmits the second Initialization signal
  • the first scanning signal line Scan2(n-1) transmits the first scanning signal
  • the second scanning signal line Scan1(n-1) transmits the second scanning signal
  • the third scanning signal line Scan2(n) transmits the third scanning signal
  • the fourth scanning signal line Scan1(n) transmits the fourth scanning signal
  • the luminescence control signal line EM(n) transmits the luminescence control signal
  • the power supply low potential signal line VSS transmits low potential.
  • Scan1 and Scan2 represent two sets of scan lines, and Scan(n-1) and Scan(n) represent two levels of scan lines.
  • each sub-pixel in Figure 2 only includes one first initialization transistor.
  • Figures 4 to 7 are exploded views of Figure 2, so they are also shown in two sub-pixels, and partially show the next structure.
  • Figure 4 shows the design of the active pattern of each transistor
  • Figure 5 shows the design of the gate of each transistor and the wiring of the first metal layer
  • Figure 6 shows the wiring design of the second metal layer
  • Figure 7 shows the wiring design of the second metal layer. The design of the source, drain and traces of the three metal layers.
  • Drive TFT, T2, T3, T4, T5, T6, and T7 respectively represent the arrangement positions of the active patterns of each transistor, and you can see the first active pattern and the second active pattern.
  • the pattern has a bent structure; as shown in Figure 5, the gates of each transistor are represented by Drive TFT, T2, T3, T4, T5, T6, and T7 respectively.
  • the first gate of the compensation transistor T3 and the second gate are two parts that are perpendicular to each other
  • the third gate and the fourth gate of the first initialization transistor T4 are two parts that are perpendicular to each other; as shown in Figure 6 and Figure 7, the layout of each trace is shown.
  • the second initialization signal line VI-2 includes a first part located on the second metal layer and a second part located on the third metal layer, and from Figures 6 and 7 it can be It can be seen that in Figure 2, components located in different film layers can be connected through via holes and through the metal of the corresponding film layer. Therefore, there are unlabeled parts in Figures 6 and 7. This unlabeled part indicates that there are Via-hole connection, this trace can be used as a connecting trace.
  • the pixel driving circuit uses other Design method, for example, if there are other double-gate design transistors connected to the driving transistor, the active patterns of other double-gate design transistors can also be shielded, or when the display panel also includes other metal layers (for example, including source and drain layers and When the transition metal layer is located on the source and drain layer, the transition metal layer can be used to form the shielding metal), or the shielding metal can be provided using the above design method, so that the shielding metal shields the first active pattern and the second active pattern. , reduce the leakage current to the drive transistor and improve display flicker.
  • Design method for example, if there are other double-gate design transistors connected to the driving transistor, the active patterns of other double-gate design transistors can also be shielded, or when the display panel also includes other metal layers (for example, including source and drain layers and When the transition metal layer is located on the source and drain layer, the transition metal layer can be used to form the shielding metal), or the shielding metal can be provided using the above design method, so that the shielding
  • the display panel shown in Figures 8 and 9 is different from the display panel in Figure 2 only in the placement position of the shielding metal and the connection position of the shielding metal.
  • the display panel shown in Figures 8 and 9 The exploded view of can be determined by analogy with the exploded view of the display panel in Figure 2, and will not be described again here.
  • embodiments of the present application provide a display device, which includes the display panel and electronic components described in any of the above embodiments.
  • Embodiments of the present application provide a display panel and a display device; the display panel includes a plurality of light-emitting devices arranged in an array and a pixel driving circuit for driving the light-emitting devices.
  • the pixel driving circuit includes a first initialization transistor, a switching transistor, a driving transistor and a compensation transistor. , the first initialization transistor is connected to the first initialization signal line and is used to input the first initialization signal to the first node under the control of the first scan signal, and the switching transistor is used to input the first initialization signal to the second node under the control of the second scan signal.
  • the node inputs the data signal
  • the driving transistor is used to drive the light-emitting device to emit light under the control of the potential of the first node and the second node
  • the compensation transistor is connected to the driving transistor through the first node and the third node, and is used to control the third scanning signal.
  • the threshold voltage of the driving transistor is compensated, wherein the compensation transistor includes a connected first gate and a second gate, the first initialization transistor includes a connected third gate and a fourth gate, and the display panel also includes a shielding metal , a shielding metal is provided on at least one of the first active pattern located between the first gate electrode and the second gate electrode and the second active pattern located between the third gate electrode and the fourth gate electrode.
  • the present application provides a shielding metal on at least one of the first active pattern located between the first gate electrode and the second gate electrode and the second active pattern located between the third gate electrode and the fourth gate electrode,
  • the shielding metal can shield the coupling effect of other signals on the first active pattern and the second active pattern, and increase the parasitic capacitance of the first active pattern and the second active pattern. Even if the first active pattern and the second active pattern The active pattern can also reduce potential changes due to coupling effects, thereby reducing leakage to the gate of the driving transistor and improving the problem of display flicker.

Abstract

一种显示面板，显示面板通过在位于第一栅极和第二栅极之间的第一有源图案(121)与位于第三栅极和第四栅极之间的第二有源图案(122)中的至少一个上设置屏蔽金属(26,161,163)，使得屏蔽金属(26,161,163)能够屏蔽其他信号对第一有源图案(121)和第二有源图案(122)的耦合作用，且增加第一有源图案(121)和第二有源图案(122)的寄生电容，减小电位变化，改善显示闪烁的问题。

Description

显示面板 技术领域
本申请涉及显示技术领域，尤其是涉及一种显示面板。
 背景技术
OLED（Organic Light-Emitting Diode，有机发光二极管）显示器件由于自发光、可实现柔性等优点被广泛应用。现有OLED显示器件会采用基于LTPS（Low Temperature Poly-silicon，低温多晶硅）技术的驱动电路对像素进行驱动，但在实际使用过程中，由于与驱动晶体管的栅极连接的晶体管为双栅设计的晶体管，位于双栅结构之间的半导体图案容易受到其他信号的耦合，导致电位较高，在发光阶段向驱动晶体管漏电，导致一帧内显示亮度变化，且在低频显示时出现明显的闪烁现象。
所以，现有OLED显示器件存在与驱动晶体管的栅极连接的双栅晶体管漏电导致OLED显示器件出现显示闪烁的技术问题。
 技术问题
本申请实施例提供一种显示面板。用以缓解现有OLED显示器件存在与驱动晶体管的栅极连接的双栅晶体管漏电导致OLED显示器件出现显示闪烁的技术问题。
 技术解决方案
为解决上述问题，本申请提供的技术方案如下：
本申请实施例提供一种显示面板，该显示面板包括阵列设置的多个发光器件和驱动所述发光器件的像素驱动电路，所述像素驱动电路包括：
第一初始化晶体管，与第一初始化信号线连接，用于在第一扫描信号的控制下，向第一节点输入第一初始化信号；
开关晶体管，用于在第二扫描信号的控制下，向第二节点输入数据信号；
驱动晶体管，用于在第一节点和第二节点电位的控制下，驱动所述发光器件发光；
补偿晶体管，通过所述第一节点和第三节点与所述驱动晶体管相连，用于在第三扫描信号的控制下，补偿所述驱动晶体管的阈值电压；
其中，所述补偿晶体管包括相连的第一栅极和第二栅极，所述第一初始化晶体管包括相连的第三栅极和第四栅极，所述显示面板还包括屏蔽金属，位于所述第一栅极和所述第二栅极之间的第一有源图案与位于所述第三栅极和所述第四栅极之间的第二有源图案中的至少一个上设有屏蔽金属。
在一些实施例中，位于所述第一栅极和所述第二栅极之间的第一有源图案上设有屏蔽金属，或者位于所述第三栅极和所述第四栅极之间的第二有源图案上设有屏蔽金属。
在一些实施例中，位于所述第一栅极和所述第二栅极之间的第一有源图案上设有屏蔽金属。
在一些实施例中，位于所述第三栅极和所述第四栅极之间的第二有源图案上设有屏蔽金属。
在一些实施例中，位于所述第一栅极和所述第二栅极之间的第一有源图案上设有第一屏蔽金属，位于所述第三栅极和所述第四栅极之间的第二有源图案上设有第二屏蔽金属。
在一些实施例中，所述显示面板还包括接地端，所述第一屏蔽金属和所述第二屏蔽金属中的至少一个连接所述接地端。
在一些实施例中，所述第一屏蔽金属连接至所述接地端。
在一些实施例中，所述第二屏蔽金属连接至所述接地端。
在一些实施例中，所述第一屏蔽金属连接至所述接地端，所述第二屏蔽金属连接至所述接地端。
在一些实施例中，所述像素驱动电路还包括第二初始化晶体管，所述第二初始化晶体管与第二初始化信号线连接，用于在第四扫描信号的控制下，向所述发光器件阳极输入第二初始化信号；
第一发光控制晶体管，通过第二节点与所述驱动晶体管相连，用于在发光控制信号的控制下，导通电源高电位信号线向所述驱动晶体管的电流；
第二发光控制晶体管，通过第三节点与所述驱动晶体管相连，用于在发光控制信号的控制下，导通所述驱动晶体管流向所述发光器件阳极的电流；
其中，所述第一屏蔽金属与所述第一初始化信号线和所述第二初始化信号线中的一个连接，所述第二屏蔽金属与所述第一初始化信号线和所述第二初始化信号线中的一个连接。
在一些实施例中，所述第一屏蔽金属与所述第二初始化信号线连接，所述第二屏蔽金属与所述第一初始化信号线连接。
在一些实施例中，所述显示面板包括：
衬底；
像素驱动电路层，包括多个像素驱动电路；
其中，所述像素驱动电路包括依次层叠设置在所述衬底上的半导体层、第一金属层、第二金属层和第三金属层，所述显示面板还包括位于所述半导体层和所述第一金属层之间的第一层间介质层、位于所述第一金属层和所述第二金属层之间的第二层间介质层、位于所述第二金属层和所述第三金属层之间的层间绝缘层，所述半导体层包括所述第一有源图案和所述第二有源图案，所述第一金属层包括第一栅极、第二栅极、第三栅极和第四栅极，所述第二金属层和所述第三金属层中的至少一个设有屏蔽金属。
在一些实施例中，所述显示面板设置有穿过所述层间绝缘层的第一过孔，所述第二金属层包括第二初始化信号线的第一部分和第一屏蔽金属，所述第三金属层包括第二初始化信号线的第二部分；
其中，所述第一屏蔽金属穿过所述第一过孔与所述第二初始化信号线的第二部分连接，所述第二初始化信号线的第二部分穿过所述第一过孔与所述第二初始化信号线的第一部分连接。
在一些实施例中，所述显示面板设置有穿过所述第一层间介质层、所述第二层间介质层和所述层间绝缘层的第二过孔，所述第二初始化信号线的第二部分穿过所述第二过孔与所述第二有源图案连接。
在一些实施例中，所述显示面板设置有穿过所述层间绝缘层的第三过孔，所述第二金属层包括第二屏蔽金属，所述第三金属层包括第一初始化信号线；
其中，所述第一初始化信号线穿过所述第三过孔与所述第二屏蔽金属连接。
在一些实施例中，所述显示面板设置有穿过所述层间绝缘层的第四过孔，所述第二金属层包括第二初始化信号线的第一部分，所述第三金属层包括第二初始化信号线的第二部分和第一屏蔽金属；
其中，所述第一屏蔽金属与所述第二初始化信号线的第二部分连接，所述第二初始化信号线的第二部分穿过所述第四过孔与所述第二初始化信号线的第一部分连接。
在一些实施例中，所述第三金属层形成有源极和漏极。
在一些实施例中，所述像素驱动电路还包括存储电容，所述存储电容一端与电源高电位信号线连接，所述存储电容另一端与所述第一节点连接。
在一些实施例中，所述第一初始化晶体管为低温多晶硅薄膜晶体管，所述补偿晶体管为低温多晶硅薄膜晶体管，所述第一栅极和所述第二栅极在所述第一有源图案上的投影存在间距，所述第三栅极和所述第四栅极在所述第二有源图案上的投影存在间距。
在一些实施例中，横向设置的相邻像素驱动电路对称设置，相邻像素驱动电路中的第一初始化晶体管连接至同一初始化信号线，相邻像素驱动电路中的补偿晶体管连接至同一扫描线。
 有益效果
本申请提供一种显示面板；该显示面板包括阵列设置的多个发光器件和驱动发光器件的像素驱动电路，像素驱动电路包括第一初始化晶体管、开关晶体管、驱动晶体管和补偿晶体管，第一初始化晶体管与第一初始化信号线连接，用于在第一扫描信号的控制下，向第一节点输入第一初始化信号，开关晶体管用于在第二扫描信号的控制下，向第二节点输入数据信号，驱动晶体管用于在第一节点和第二节点电位的控制下，驱动发光器件发光，补偿晶体管通过第一节点和第三节点与驱动晶体管相连，用于在第三扫描信号的控制下，补偿驱动晶体管的阈值电压，其中，补偿晶体管包括相连的第一栅极和第二栅极，第一初始化晶体管包括相连的第三栅极和第四栅极，显示面板还包括屏蔽金属，位于第一栅极和第二栅极之间的第一有源图案与位于第三栅极和第四栅极之间的第二有源图案中的至少一个上设有屏蔽金属。本申请通过在位于第一栅极和第二栅极之间的第一有源图案与位于第三栅极和第四栅极之间的第二有源图案中的至少一个上设置屏蔽金属，使得屏蔽金属能够屏蔽其他信号对第一有源图案和第二有源图案的耦合作用，且增加第一有源图案和第二有源图案的寄生电容，则即使第一有源图案和第二有源图案受到耦合作用，也能减小电位变化，从而减小对驱动晶体管的栅极的漏电，改善显示闪烁的问题。
 附图说明
图1为本申请实施例提供的显示面板的电路图。
图2为本申请实施例提供的显示面板的第一种透视图。
图3为图2中的透视图的截面图。
图4为图2中的显示面板的半导体层的分解图。
图5为图2中的显示面板的第一金属层的分解图。
图6为图2中的显示面板的第二金属层的分解图。
图7为图2中的显示面板的第三金属层的分解图。
图8为本申请实施例提供的显示面板的第二种透视图。
图9为本申请实施例提供的显示面板的第三种透视图。
 本发明的实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
本申请实施例针对现有OLED显示器件存在与驱动晶体管的栅极连接的双栅晶体管漏电导致OLED显示器件出现显示闪烁的技术问题，提供一种显示面板和显示装置，用以缓解上述技术问题。
如图1、图2、图3所示，本申请实施例提供一种显示面板，该显示面板包括阵列设置的多个发光器件LED和驱动所述发光器件LED的像素驱动电路，所述像素驱动电路包括：
第一初始化晶体管T4，与第一初始化信号线连接，用于在第一扫描信号的控制下，向第一节点Q输入第一初始化信号；
开关晶体管T2，用于在第二扫描信号的控制下，向第二节点A输入数据信号；
驱动晶体管Drive TFT，用于在第一节点Q和第二节点A电位的控制下，驱动所述发光器件LED发光；
补偿晶体管T3，通过所述第一节点Q和第三节点B与所述驱动晶体管Drive TFT相连，用于在第三扫描信号的控制下，补偿所述驱动晶体管Drive TFT的阈值电压；
其中，所述补偿晶体管T3包括相连的第一栅极和第二栅极，所述第一初始化晶体管T4包括相连的第三栅极和第四栅极，所述显示面板还包括屏蔽金属（例如图2中的第一屏蔽金属161），位于所述第一栅极和所述第二栅极之间的第一有源图案121与位于所述第三栅极和所述第四栅极之间的第二有源图案122中的至少一个上设有屏蔽金属（例如图3中第一有源图案121上设有第一屏蔽金属161）。
本申请实施例提供一种显示面板，该显示面板通过在位于第一栅极和第二栅极之间的第一有源图案与位于第三栅极和第四栅极之间的第二有源图案中的至少一个上设置屏蔽金属，使得屏蔽金属能够屏蔽其他信号对第一有源图案和第二有源图案的耦合作用，且增加第一有源图案和第二有源图案的寄生电容，则即使第一有源图案和第二有源图案受到耦合作用，也能减小电位变化，从而减小对驱动晶体管的栅极的漏电，改善显示闪烁的问题。
需要说明的是，从图1、图2均可以看到，补偿晶体管T3的两个栅极会连接，因此，在图1、图2中第一栅极和第二栅极实际是一个栅极的两个部分，以图2为例，第一栅极和第二栅极是栅极中相互垂直的两个部分，因此，未具体标注第一栅极和第二栅极，同理可知，第一初始化晶体管T4的第三栅极和第四栅极也是栅极中相互垂直的两个部分。
需要说明的是，从图1的电路图以及图2中的透视图可以看到，在半导体层中，有源图案包括与晶体管的栅极的投影存在重合的两个部分以及位于重合部分之间的另一部分，以图2位于，可以看到第一有源图案与补偿晶体管T3的栅极的投影存在投影重合的部分，则可以知道位于第一栅极和第二栅极之间的第一有源图案是指位于第一有源图案与补偿晶体管T3的栅极的投影重合的两个部分之间的另一部分；同理可知，位于第三栅极和第四栅极之间的第二有源图案是指位于第二有源图案与第一初始化晶体管T4的栅极的投影重合的两个部分之间的另一部分。
在一种实施例中，位于所述第一栅极和所述第二栅极之间的第一有源图案上设有屏蔽金属，或者位于所述第三栅极和所述第四栅极之间的第二有源图案上设有屏蔽金属。
具体的，如图8所示，位于所述第一栅极和所述第二栅极之间的第一有源图案上设有屏蔽金属26，通过在位于第一栅极和第二栅极之间的第一有源图案上设置屏蔽金属，使屏蔽金属屏蔽其他信号对第一有源图案的耦合作用，同时增加第一有源图案的寄生电容，使即使出现其他信号对第一有源图案的耦合作用，也可以减小电位变化，减小补偿晶体管对驱动晶体管的栅极的漏电，减小一帧内的显示亮度变化，改善低频显示闪烁的问题。
具体的，如图9所示，位于所述第三栅极和所述第四栅极之间的第二有源图案上设有屏蔽金属26，通过在位于第三栅极和第四栅极之间的第二有源图案上设置屏蔽金属，使屏蔽金属屏蔽其他信号对第二有源图案的耦合作用，同时增加第二有源图案的寄生电容，使即使出现其他信号对第二有源图案的耦合作用，也可以减小电位变化，减小第一初始化晶体管对驱动晶体管的栅极的漏电，减小一帧内的显示亮度变化，改善低频显示闪烁的问题。
针对补偿晶体管和第一初始化晶体管均会对驱动晶体管漏电导致显示闪烁的问题。在一种实施例中，如图2、图3所示，位于所述第一栅极和所述第二栅极之间的第一有源图案121上设有第一屏蔽金属161，位于所述第三栅极和所述第四栅极之间的第二有源图案122上设有第二屏蔽金属163。通过在位于第一栅极和第二栅极之间的第一有源图案上设置第一屏蔽金属，在位于第三栅极和第四栅极之间的第二有源图案上设置第二屏蔽金属，使第一屏蔽金属对第一有源图案进行屏蔽，减小补偿晶体管的漏电，使第二屏蔽金属对第二有源图案进行屏蔽，减小第一初始化晶体管的漏电，减小一帧内的显示亮度变化，改善低频显示闪烁的问题。
针对屏蔽金属的电位变化会导致屏蔽效果较差的问题。在一种实施例中，所述显示面板还包括接地端，所述第一屏蔽金属和所述第二屏蔽金属中的至少一个连接所述接地端。
具体，所述第一屏蔽金属连接至所述接地端，或者所述第二屏蔽金属连接至所述接地端，或者所述第一屏蔽金属连接至所述接地端，所述第二屏蔽金属连接至所述接地端。通过将第一屏蔽金属和第二屏蔽金属连接至接地端，保持第一屏蔽金属和第二屏蔽金属的电位稳定，则可以通过第一屏蔽金属稳定补偿晶体管的第一有源图案的电位，避免该处的电位被其他信号耦合过高或者耦合过低，从而减小了驱动晶体管的源极和漏极之间的压差，减小漏电流；通过第二屏蔽金属稳定第一初始化晶体管的第二有源图案的电位，避免该处的电位被其他信号耦合过高或者耦合过低，从而减小了驱动晶体管的源极和漏极之间的压差，减小漏电流；通过减小驱动晶体管和第一初始化晶体管的漏电流，减小了显示面板一帧的亮度变化，改善显示闪烁。
在一种实施例中，如图1、图2、图3所示，所述像素驱动电路还包括第二初始化晶体管T7，所述第二初始化晶体管T7与第二初始化信号线VI-2连接，用于在第四扫描信号的控制下，向所述发光器件LED阳极输入第二初始化信号；
第一发光控制晶体管T5，通过第二节点A与所述驱动晶体管Drive TFT相连，用于在发光控制信号的控制下，导通电源高电位信号线VDD向所述驱动晶体管Drive TFT的电流；
第二发光控制晶体管T6，通过第三节点B与所述驱动晶体管Drive TFT相连，用于在发光控制信号的控制下，导通所述驱动晶体管Drive TFT流向所述发光器件LED阳极的电流；
其中，所述第一屏蔽金属161与所述第一初始化信号线191和所述第二初始化信号线中的一个连接，所述第二屏蔽金属与所述第一初始化信号线191和所述第二初始化信号线中的一个连接。通过将第一屏蔽金属与第一初始化信号线和第二初始化信号线中的一个连接，使第二屏蔽金属与第一初始化信号线和第二初始化信号线中的一个连接，由于第一初始化信号线和第二初始化信号线的电位稳定，则可以使得第一屏蔽金属和第二屏蔽金属的电位稳定，进而使得补偿晶体管的第一有源图案和第一初始化晶体管的第二有源图案的电位稳定，使得补偿晶体管和第一初始化晶体管的漏电减小或者消除补偿晶体管和第一初始化晶体管的漏电，减小一帧内的显示亮度变化，改善显示闪烁的问题。
需要说明的是，在图1所示的电路图中，对第一初始化信号线以VI-1进行标示，在图3所示的截面图中，对第一初始化信号线以标号191进行标示，此处仅为不同图示中不同的标示方式，实际上图1所示的电路图中第一初始化信号线对应图3所示的截面图中的第一初始化信号线，同理，其他电路图与截面图中存在不同标示方式的元件也是同一元件，在此不再赘述。
如图4至图7所示，图4为图3中半导体层的透视图，图5为图3中的第一金属层的透视图，图6为图3中的第二金属层的透视图，图7为图3中的第三金属层透视图。
针对第一屏蔽金属与第二屏蔽金属连接的走线较远会导致膜层结构和膜层连接结构较为复杂。在一种实施例中，如图2至图7，所述第一屏蔽金属161与所述第二初始化信号线VI-2连接，所述第二屏蔽金属163与所述第一初始化信号线VI-1连接。由于单个子像素中补偿晶体管靠近第二初始化信号线，第一初始化晶体管靠近第一初始化信号线，使得第一屏蔽金属与第二初始化信号线连接，第一初始化晶体管与第一初始化信号线连接，则可以缩短第一屏蔽金属连接的走线的长度，降低膜层结构和膜层连接结构的复杂性。
在一种实施例中，所述显示面板包括：
衬底；
像素驱动电路层，包括多个像素驱动电路；
其中，所述像素驱动电路包括依次层叠设置在所述衬底上的半导体层、第一金属层、第二金属层和第三金属层，所述半导体层包括所述第一有源图案和所述第二有源图案，所述第一金属层包括第一栅极、第二栅极、第三栅极和第四栅极，所述显示面板还包括屏蔽金属层，所述屏蔽金属层形成有屏蔽金属。通过设置屏蔽金属层，使屏蔽金属层形成屏蔽金属，则可以避免屏蔽金属影响其他膜层的结构设计。
针对设置屏蔽金属层会导致显示面板的厚度较大的技术问题。在一种实施例中，如图3所示，所述显示面板包括：
衬底11；
像素驱动电路层，包括多个像素驱动电路；
其中，所述像素驱动电路包括依次层叠设置在所述衬底11上的半导体层12、第一金属层14、第二金属层16和第三金属层19，所述显示面板还包括位于所述半导体层12和所述第一金属层14之间的第一层间介质层13，位于所述第一金属层14和所述第二金属层16之间的第二层间介质层15、位于所述第二金属层16和所述第三金属层19之间的层间绝缘层17，所述半导体层12包括所述第一有源图案121和所述第二有源图案122，所述第一金属层14包括第一栅极、第二栅极、第三栅极和第四栅极，所述第二金属层16和所述第三金属层19中的至少一个设有屏蔽金属。通过在第二金属层和第三金属层设置屏蔽金属，无需另外设置屏蔽金属层，减小显示面板的厚度。
针对屏蔽金属与半导体层的距离较远会导致屏蔽效果较差的问题。在一种实施例中，如图2、图3中的（a），图4至图7所示，所述显示面板设置有穿过所述层间绝缘层17的第一过孔181，所述第二金属层16包括第二初始化信号线VI-2的第一部分162和第一屏蔽金属161，所述第三金属层19包括第二初始化信号线VI-2的第二部分；
其中，所述第一屏蔽金属161穿过所述第一过孔181与所述第二初始化信号线VI-2的第二部分连接，所述第二初始化信号线VI-2的第二部分穿过所述第一过孔181与所述第二初始化信号线VI-2的第一部分181连接。通过将第一屏蔽金属设置在第二金属层，使得第一屏蔽金属与补偿晶体管的第一有源图案的距离较近，使得形成的电容较大，第一屏蔽金属对第一有源图案的屏蔽效果较好，减小补偿晶体管的漏电，改善显示面板的闪烁。
需要说明的是，图3中的（a）为图2中补偿晶体管至第二初始化信号线的截面图，因此，图3中的（a）未示出补偿晶体管的源极、漏极，且对于补偿晶体管的第一栅极和第二栅极，由于采用截面，仅能以标号141示出第一栅极和第二栅极中的一部分，且以标号142标示发光控制信号线EM（n）。同理，图3中的（b）仅以标号143示出第三栅极和第四栅极中的一部分，且由于图3中的（a）仅示出第三金属层19的一部分，该部分为第一屏蔽金属与第二初始化信号线的第一部分之间的连接部分，因此，该部分可以作为第二初始化信号线的第二部分。
针对第一初始化晶体管的电位较高会影响驱动晶体管的栅极电位的问题。在一种实施例中，如图2、图3中的（a）、图4至图7所示，所述显示面板设置有穿过所述第一层间介质层13、所述第二层间介质层15和所述层间绝缘层17的第二过孔182，所述第二初始化信号线VI-2的第二部分穿过所述第二过孔182与所述第二有源图案122连接。通过将第二初始化信号线的第二部分与第二有源图案连接，使得第二初始化信号线能够将第一初始化晶体管的栅极复位，避免第一初始化晶体管的栅极电位较高导致第一初始化晶体管保持开启状态，影响驱动晶体管的栅极电位。
针对屏蔽金属与半导体层的距离较远会导致屏蔽效果较差的问题。在一种实施例中，如图2、图3中的（b）、图4至图7，所述显示面板设置有穿过所述层间绝缘层17的第三过孔183，所述第二金属层包括第二屏蔽金属163，所述第三金属层包括第一初始化信号线191；
其中，所述第一初始化信号线191穿过所述第三过孔183与所述第二屏蔽金属163连接。通过将第二屏蔽金属设置在第二金属层，使得第二屏蔽金属与第一初始化晶体管的第二有源图案的距离较近，使得形成的电容较大，第二屏蔽金属对第二有源图案的屏蔽效果较好，减小第一初始化晶体管的漏电，改善显示面板的闪烁。
在一种实施例中，所述显示面板设置有穿过所述层间绝缘层的第四过孔，所述第二金属层包括第二初始化信号线的第一部分，所述第三金属层包括第二初始化信号线的第二部分和第一屏蔽金属；
其中，所述第一屏蔽金属与所述第二初始化信号线的第二部分连接，所述第二初始化信号线的第二部分穿过所述第四过孔与所述第二初始化信号线的第一部分连接。通过的第三金属层形成第一屏蔽金属，使得第一屏蔽金属可以直接与第二初始化信号线连接，无需形成过孔，且无需占用第二金属层的空间，减小工艺难度。
在一种实施例中，所述第一初始化晶体管为低温多晶硅薄膜晶体管，所述补偿晶体管为低温多晶硅薄膜晶体管，所述第一栅极和所述第二栅极在所述第一有源图案上的投影存在间距，所述第三栅极和所述第四栅极在所述第二有源图案上的投影存在间距。本申请针对低温多晶硅薄膜晶体管会采用双栅设计，双栅之间的半导体图案容易受到其他信号的耦合，导致电位较高，在发光阶段向驱动晶体管漏电，通过设置屏蔽金属，减小对驱动晶体管的栅极的漏电，改善显示闪烁。
在一种实施例中，横向设置的相邻像素驱动电路对称设置，相邻像素驱动电路中的第一初始化晶体管连接至同一初始化信号线，相邻像素驱动电路中的补偿晶体管连接至同一扫描线。通过将相邻像素驱动电路中的第一初始化晶体管连接至同一初始化信号线，使相邻像素驱动电路中的补偿晶体管连接至同一扫描线，减小子像素的占用空间，可以提高显示面板的开口率，且由于无需将两个子像素之间的部分走线断开，降低了工艺难度，提高了显示面板的良率。
具体的，从图2至图7可以看到，横向设置的像素驱动电路对称设置，将两个像素驱动电路中的部分电极和金属走线共用，减少单个子像素的占用空间，且减少了显示面板的工艺难度。
在一种实施例中，所述第一金属层形成有栅极，所述第二金属层形成有电容的极板，所述第三金属层形成有源极和漏极。
在一种实施例中，如图1所示，所述像素驱动电路还包括存储电容Cst，所述存储电容Cst一端与所述电源高电位信号线VDD连接，所述存储电容Cst另一端与所述第一节点Q连接。
可以理解的是，在本申请实施例中，如图1所示，数据线Data传输数据信号，第一初始化信号线VI-1传输第一初始化信号、第二初始化信号线VI-2传输第二初始化信号，第一扫描信号线Scan2（n-1）传输第一扫描信号，第二扫描信号线Scan1（n-1）传输第二扫描信号，第三扫描信号线Scan2（n）传输第三扫描信号，第四扫描信号线Scan1（n）传输第四扫描信号，发光控制信号线EM（n）传输发光控制信号，电源低电位信号线VSS传输低电位。
需要说明的是，Scan1和Scan2表示两组扫描线，Scan（n-1）和Scan（n）表示两级扫描线。
需要说明的是，图2中以两个子像素中的像素驱动电路示出各元件的设置以及连接关系，且为了说明重复单元的设置方式，每个子像素示出了下一级的第一初始化晶体管，因此，在图2中会存在4个T4，实际上图2中各子像素仅包括一个第一初始化晶体管。而图4至图7为图2的分解图，因此也是以两个子像素示出，且部分示出了下一次的结构。
具体的，图4为各晶体管的有源图案的设计，图5为各晶体管的栅极和第一金属层的走线的设计，图6为第二金属层的走线设计，图7为第三金属层的源漏极和走线的设计。
具体的，如图4所示，分别以Drive TFT、T2、T3、T4、T5、T6、T7表示各晶体管的有源图案的设置位置，且可以看到第一有源图案和第二有源图案具有弯折结构；如图5所示，分别以Drive TFT、T2、T3、T4、T5、T6、T7表示各晶体管的栅极，从图5可以看到，补偿晶体管T3的第一栅极和第二栅极为相互垂直的两个部分，第一初始化晶体管T4的第三栅极和第四栅极为相互垂直的两个部分；如图6、图7所示，示出了各走线的结构以及设置位置，从图6和图7可以看到，第二初始化信号线VI-2包括位于第二金属层的第一部分和位于第三金属层第二部分，且从图6和图7可以看到，在图2中，位于不同膜层的元件可以通过过孔并通过对应膜层的金属连接，因此，图6、图7中存在未标示的部分，该未标示的部分标示此处存在过孔连接，此走线可以作为连接走线。
需要说明的是，上述实施例以图1所示的像素驱动电路和图2中的透视图对屏蔽金属的设置方式进行了详细说明，但本申请实施例不限于此，例如像素驱动电路采用其他设计方式，例如还有其他双栅设计的晶体管连接至驱动晶体管，也可以对其他双栅设计的晶体管的有源图案进行屏蔽，或者显示面板还包括其他金属层时（例如包括源漏极层和位于源漏极层上的过渡金属层时，可以采用过渡金属层形成屏蔽金属），也可以采用上述设计方式设置屏蔽金属，以使屏蔽金属对第一有源图案和第二有源图案进行屏蔽，减小对驱动晶体管的漏电流，改善显示闪烁。
需要说明的是，图8、图9中示出的显示面板与图2中的显示面板仅存在屏蔽金属的设置位置以及屏蔽金属的连接位置存在区别，图8、图9中示出的显示面板的分解图可以类比图2中的显示面板的分解图确定，在此不再赘述。
同时，本申请实施例提供一种显示装置，该显示装置包括上述实施例任一所述的显示面板和电子元件。
根据上述实施例可知：
本申请实施例提供一种显示面板和显示装置；该显示面板包括阵列设置的多个发光器件和驱动发光器件的像素驱动电路，像素驱动电路包括第一初始化晶体管、开关晶体管、驱动晶体管和补偿晶体管，第一初始化晶体管与第一初始化信号线连接，用于在第一扫描信号的控制下，向第一节点输入第一初始化信号，开关晶体管用于在第二扫描信号的控制下，向第二节点输入数据信号，驱动晶体管用于在第一节点和第二节点电位的控制下，驱动发光器件发光，补偿晶体管通过第一节点和第三节点与驱动晶体管相连，用于在第三扫描信号的控制下，补偿驱动晶体管的阈值电压，其中，补偿晶体管包括相连的第一栅极和第二栅极，第一初始化晶体管包括相连的第三栅极和第四栅极，显示面板还包括屏蔽金属，位于第一栅极和第二栅极之间的第一有源图案与位于第三栅极和第四栅极之间的第二有源图案中的至少一个上设有屏蔽金属。本申请通过在位于第一栅极和第二栅极之间的第一有源图案与位于第三栅极和第四栅极之间的第二有源图案中的至少一个上设置屏蔽金属，使得屏蔽金属能够屏蔽其他信号对第一有源图案和第二有源图案的耦合作用，且增加第一有源图案和第二有源图案的寄生电容，则即使第一有源图案和第二有源图案受到耦合作用，也能减小电位变化，从而减小对驱动晶体管的栅极的漏电，改善显示闪烁的问题。
在上述实施例中，对各个实施例的描述都各有侧重，某个实施例中没有详述的部分，可以参见其他实施例的相关描述。
以上对本申请实施例所提供的一种显示面板和显示装置进行了详细介绍，本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本申请的技术方案及其核心思想；本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例的技术方案的范围。

Claims (20)

  1. 一种显示面板，其中，所述显示面板包括阵列设置的多个发光器件和驱动所述发光器件的像素驱动电路，所述像素驱动电路包括：
    第一初始化晶体管，与第一初始化信号线连接，用于在第一扫描信号的控制下，向第一节点输入第一初始化信号；
    开关晶体管，用于在第二扫描信号的控制下，向第二节点输入数据信号；
    驱动晶体管，用于在第一节点和第二节点电位的控制下，驱动所述发光器件发光；
    补偿晶体管，通过所述第一节点和第三节点与所述驱动晶体管相连，用于在第三扫描信号的控制下，补偿所述驱动晶体管的阈值电压；
    其中，所述补偿晶体管包括相连的第一栅极和第二栅极，所述第一初始化晶体管包括相连的第三栅极和第四栅极，所述显示面板还包括屏蔽金属，位于所述第一栅极和所述第二栅极之间的第一有源图案与位于所述第三栅极和所述第四栅极之间的第二有源图案中的至少一个上设有屏蔽金属。
  2. 如权利要求1所述的显示面板，其中，位于所述第一栅极和所述第二栅极之间的第一有源图案上设有屏蔽金属，或者位于所述第三栅极和所述第四栅极之间的第二有源图案上设有屏蔽金属。
  3. 如权利要求2所述的显示面板，其中，位于所述第一栅极和所述第二栅极之间的第一有源图案上设有屏蔽金属。
  4. 如权利要求2所述的显示面板，其中，位于所述第三栅极和所述第四栅极之间的第二有源图案上设有屏蔽金属。
  5. 如权利要求1所述的显示面板，其中，位于所述第一栅极和所述第二栅极之间的第一有源图案上设有第一屏蔽金属，位于所述第三栅极和所述第四栅极之间的第二有源图案上设有第二屏蔽金属。
  6. 如权利要求5所述的显示面板，其中，所述显示面板还包括接地端，所述第一屏蔽金属和所述第二屏蔽金属中的至少一个连接所述接地端。
  7. 如权利要求6所述的显示面板，其中，所述第一屏蔽金属连接至所述接地端。
  8. 如权利要求6所述的显示面板，其中，所述第二屏蔽金属连接至所述接地端。
  9. 如权利要求6所述的显示面板，其中，所述第一屏蔽金属连接至所述接地端，所述第二屏蔽金属连接至所述接地端。
  10. 如权利要求5所述的显示面板，其中，所述像素驱动电路还包括第二初始化晶体管，所述第二初始化晶体管与第二初始化信号线连接，用于在第四扫描信号的控制下，向所述发光器件阳极输入第二初始化信号；
    第一发光控制晶体管，通过第二节点与所述驱动晶体管相连，用于在发光控制信号的控制下，导通电源高电位信号线向所述驱动晶体管的电流；
    第二发光控制晶体管，通过第三节点与所述驱动晶体管相连，用于在发光控制信号的控制下，导通所述驱动晶体管流向所述发光器件阳极的电流；
    其中，所述第一屏蔽金属与所述第一初始化信号线和所述第二初始化信号线中的一个连接，所述第二屏蔽金属与所述第一初始化信号线和所述第二初始化信号线中的一个连接。
  11. 如权利要求10所述的显示面板，其中，所述第一屏蔽金属与所述第二初始化信号线连接，所述第二屏蔽金属与所述第一初始化信号线连接。
  12. 如权利要求10所述的显示面板，其中，所述显示面板包括：
    衬底；
    像素驱动电路层，包括多个像素驱动电路；
    其中，所述像素驱动电路包括依次层叠设置在所述衬底上的半导体层、第一金属层、第二金属层和第三金属层，所述显示面板还包括位于所述半导体层和所述第一金属层之间的第一层间介质层、位于所述第一金属层和所述第二金属层之间的第二层间介质层、位于所述第二金属层和所述第三金属层之间的层间绝缘层，所述半导体层包括所述第一有源图案和所述第二有源图案，所述第一金属层包括第一栅极、第二栅极、第三栅极和第四栅极，所述第二金属层和所述第三金属层中的至少一个设有屏蔽金属。
  13. 如权利要求12所述的显示面板，其中，所述显示面板设置有穿过所述层间绝缘层的第一过孔，所述第二金属层包括第二初始化信号线的第一部分和第一屏蔽金属，所述第三金属层包括第二初始化信号线的第二部分；
    其中，所述第一屏蔽金属穿过所述第一过孔与所述第二初始化信号线的第二部分连接，所述第二初始化信号线的第二部分穿过所述第一过孔与所述第二初始化信号线的第一部分连接。
  14. 如权利要求13所述的显示面板，其中，所述显示面板设置有穿过所述第一层间介质层、所述第二层间介质层和所述层间绝缘层的第二过孔，所述第二初始化信号线的第二部分穿过所述第二过孔与所述第二有源图案连接。
  15. 如权利要求12所述的显示面板，其中，所述显示面板设置有穿过所述层间绝缘层的第三过孔，所述第二金属层包括第二屏蔽金属，所述第三金属层包括第一初始化信号线；
    其中，所述第一初始化信号线穿过所述第三过孔与所述第二屏蔽金属连接。
  16. 如权利要求12所述的显示面板，其中，所述显示面板设置有穿过所述层间绝缘层的第四过孔，所述第二金属层包括第二初始化信号线的第一部分，所述第三金属层包括第二初始化信号线的第二部分和第一屏蔽金属；
    其中，所述第一屏蔽金属与所述第二初始化信号线的第二部分连接，所述第二初始化信号线的第二部分穿过所述第四过孔与所述第二初始化信号线的第一部分连接。
  17. 如权利要求12所述的显示面板，其中，所述第三金属层形成有源极和漏极。
  18. 如权利要求1所述的显示面板，其中，所述像素驱动电路还包括存储电容，所述存储电容一端与电源高电位信号线连接，所述存储电容另一端与所述第一节点连接。
  19. 如权利要求1所述的显示面板，其中，所述第一初始化晶体管为低温多晶硅薄膜晶体管，所述补偿晶体管为低温多晶硅薄膜晶体管，所述第一栅极和所述第二栅极在所述第一有源图案上的投影存在间距，所述第三栅极和所述第四栅极在所述第二有源图案上的投影存在间距。
  20. 如权利要求1所述的显示面板，其中，横向设置的相邻像素驱动电路对称设置，相邻像素驱动电路中的第一初始化晶体管连接至同一初始化信号线，相邻像素驱动电路中的补偿晶体管连接至同一扫描线。
PCT/CN2022/093553 2022-05-07 2022-05-18 显示面板 WO2023216285A1 (zh)

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