WO2023213189A1 - 半导体工艺设备及形成叠层薄膜结构的方法 - Google Patents

半导体工艺设备及形成叠层薄膜结构的方法 Download PDF

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Publication number
WO2023213189A1
WO2023213189A1 PCT/CN2023/089151 CN2023089151W WO2023213189A1 WO 2023213189 A1 WO2023213189 A1 WO 2023213189A1 CN 2023089151 W CN2023089151 W CN 2023089151W WO 2023213189 A1 WO2023213189 A1 WO 2023213189A1
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Prior art keywords
wafer
process chamber
chamber
sputtering
dielectric
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PCT/CN2023/089151
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English (en)
French (fr)
Inventor
丁培军
张同文
郭宏瑞
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Beijing Naura Microelectronics Equipment Co Ltd
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Beijing Naura Microelectronics Equipment Co Ltd
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Priority to KR1020247030408A priority Critical patent/KR20240148409A/ko
Publication of WO2023213189A1 publication Critical patent/WO2023213189A1/zh
Anticipated expiration legal-status Critical
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    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/22—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the process of coating
    • C23C14/34—Sputtering
    • C23C14/35—Sputtering by application of a magnetic field, e.g. magnetron sputtering
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/22—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the process of coating
    • C23C14/34—Sputtering
    • C23C14/35—Sputtering by application of a magnetic field, e.g. magnetron sputtering
    • C23C14/354—Introduction of auxiliary energy into the plasma
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/06—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the coating material
    • C23C14/14—Metallic material, boron or silicon
    • C23C14/18—Metallic material, boron or silicon on other inorganic substrates
    • C23C14/185—Metallic material, boron or silicon on other inorganic substrates by cathodic sputtering
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/22—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the process of coating
    • C23C14/54—Controlling or regulating the coating process
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/22—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the process of coating
    • C23C14/56—Apparatus specially adapted for continuous coating; Arrangements for maintaining the vacuum, e.g. vacuum locks
    • C23C14/568—Transferring the substrates through a series of coating stations

Definitions

  • the present application relates to the field of semiconductor processing technology. Specifically, the present application relates to a semiconductor processing equipment and a method for forming a laminated thin film structure.
  • NAND flash memory is a non-volatile storage technology that can still save data after power outage. Its development goal is to reduce the cost of storage per bit and increase storage capacity. Planar structure NAND flash memory is approaching its actual expansion limit, posing severe challenges to the semiconductor memory industry.
  • the new 3D NAND flash memory technology stacks multiple layers of data storage cells in a vertical direction. It not only has excellent accuracy, but also can create storage devices with up to three times the storage capacity of planar structure NAND flash memory technology, thus achieving the goal of The higher storage capacity in a smaller space results in significant cost savings and reduced energy consumption, resulting in significant performance improvements that can fully meet the needs of many consumer mobile devices and the most demanding enterprise deployments.
  • the specific process is to first use CVD to form a stack of silicon nitride (SiNx) and silicon dioxide, and then use dry etching to carve out a specific pattern, and then Wet etching is used to remove silicon nitride, and then CVD is used to form a metal tungsten film layer to fill the silicon nitride position, thereby forming a laminated film structure composed of metal tungsten material and silicon dioxide material.
  • the process of forming a laminated thin film structure in the existing technology is relatively complicated, resulting in low product yield and affecting production capacity; in addition, due to the large difference in thermal expansion coefficients between metallic tungsten materials and silicon dioxide materials, and the formation of The process requires a high-temperature environment and needs to be lowered to room temperature after completion, resulting in the use of existing technology. Large thermal stress will be generated in the laminated film structure, which will further affect product yield.
  • this application proposes a semiconductor process equipment and a method of forming a laminated thin film structure to solve the technical problems of low product yield and affecting production capacity in the existing technology.
  • embodiments of the present application provide a method for forming a laminated thin film structure on the surface of a wafer.
  • the method includes: a first sputtering step, transferring the wafer to on the first base in the first process chamber; a mixed gas of the first inert gas and the first process gas is introduced into the first process chamber, and a first sputtering power is applied to the dielectric target, so that the first sputtering power is applied to the first process chamber.
  • An inert gas forms a plasma, the plasma causes the first process gas to generate free radicals, the free radicals react with the dielectric target material, and the plasma bombards the dielectric target material to produce on the wafer Deposition to form a dielectric film;
  • the wafer is transferred to the second base in the second process chamber; a second inert gas is introduced into the second process chamber, and a second sputtering power is applied to the metal target, so that The second inert gas forms a plasma that bombards the metal target to form a metal film on the wafer;
  • the first sputtering step and the second sputtering step are repeatedly performed to deposit alternately stacked dielectric films and metal films on the surface of the wafer to form the stacked film structure.
  • the second sputtering step further includes: applying bias power to the second base to attract ions escaped from the metal target to bombard the wafer to adjust The stress of the metal film.
  • a degassing step before performing the first sputtering step for the first time, a degassing step is further included: transferring the wafer to the third base of the degassing chamber, and placing the wafer on the third base of the degassing chamber.
  • the wafer is heated to 100°C to 500°C and maintained for 10 seconds to 200 seconds to remove water vapor on the wafer.
  • a pre-cleaning step is further included: transporting the wafer from the degassing chamber. to preclear
  • a third inert gas is introduced into the pre-cleaning chamber, and radio frequency power is applied to the fourth base to attract the plasma generated by the third inert gas to bombard the The surface of the wafer is used to remove impurities on the surface of the wafer.
  • the dielectric film deposited through the first sputtering step serves as the last layer of the laminated thin film structure. film.
  • the first inert gas is argon
  • the first process gas is oxygen
  • the proportion of oxygen in the mixed gas is It is more than 30%
  • the material of the dielectric target is silicon
  • the dielectric film is a silicon dioxide film.
  • the first sputtering power is pulsed DC power, and the pulsed DC power is 0.01kW ⁇ 10kW; the process pressure in the first process chamber is 0.01mTorr ⁇ 100mTorr; the single layer The thickness of the dielectric film is 3 nm to 100 nm.
  • the second inert gas is argon
  • the material of the metal target is tungsten
  • the metal film is a tungsten film.
  • the second sputtering power is DC power, and the DC power is 0.01kW ⁇ 20kW; the bias power is radio frequency power, and the radio frequency power is 0.01kW ⁇ 2kW; so
  • the process pressure in the second process chamber is 0.01mTorr ⁇ 100mTorr; the thickness of a single layer of the metal film is 3nm ⁇ 1000nm.
  • embodiments of the present application provide a semiconductor process equipment for forming a laminated thin film structure on the surface of a wafer, including: a transfer chamber, a first process chamber, and a second process chamber; The first process chamber and the second process chamber are connected to the transfer chamber, and the transfer chamber is used to transfer the wafer into the first process chamber or the second process chamber; The first process chamber is used to form a dielectric film on the surface of the wafer and the surface of the metal film.
  • the first process chamber includes a first base, a first sputtering power supply and a first magnetron mechanism.
  • the first base is used to carry the wafer, and the first sputtering power supply is used to provide first sputtering power to the dielectric target so that the first The first inert gas and the first process gas in a process chamber form plasma, and the first magnetron mechanism is used to guide the plasma in the first process chamber to bombard the dielectric target; the second The process chamber is used to form the metal film on the dielectric film.
  • the second process chamber includes a second base, a second sputtering power supply and a second magnetron mechanism.
  • the second base is When carrying the wafer, the second sputtering power supply is used to provide a second sputtering power to the metal target so that the second inert gas in the second process chamber forms a plasma, and the second magnetron The mechanism is used to guide the plasma in the second process chamber to bombard the metal target.
  • the wafer is transported between the first process chamber and the second process chamber through the transport chamber, and a dielectric film is formed on the wafer through the first process chamber, and the dielectric film is formed on the wafer through the second process chamber.
  • a metal film is formed on the circle, thereby forming one or more pairs of laminated film structures on the surface of the wafer. Since both process chambers use the physical vapor deposition process to deposit thin films, and both are connected to the transmission chamber, the integration difficulty of the semiconductor process equipment in the embodiment of the present application is low, and due to the simple process flow, the production capacity is greatly improved while also It can prevent the wafer from being contaminated by the external environment to ensure product yield, and also facilitates commercial mass production. In addition, because the physical vapor deposition process is used to deposit the film, the temperature of the dielectric film and the metal film can be controlled near room temperature during the deposition process, preventing large thermal stress within the laminated film structure, thereby further improving the product yield.
  • Figure 1 is a schematic top structural view of a semiconductor process equipment provided by an embodiment of the present application.
  • Figure 2 is a schematic cross-sectional structural diagram of a first process chamber provided by an embodiment of the present application
  • Figure 3 is a schematic cross-sectional structural diagram of a second process chamber provided by an embodiment of the present application.
  • Figure 4 is a schematic flow chart of a method for preparing a laminated thin film structure provided by an embodiment of the present application
  • Figure 5 is a schematic cross-sectional view of a laminated film structure provided by an embodiment of the present application.
  • the embodiment of the present application provides a semiconductor process equipment.
  • the structural schematic diagram of the semiconductor process equipment is shown in Figures 1 to 3. It is used to form a laminated thin film structure on the surface of a wafer, including: a transmission chamber 1, a first The process chamber 2 and the second process chamber 3; the first process chamber 2 and the second process chamber 3 are connected to the transfer chamber 1, and the transfer chamber 1 is used to provide the first process chamber 2 or the second process chamber with The wafer is transported in the chamber 3; the first process chamber 2 is used to form a dielectric film on the wafer surface and the metal film surface.
  • the first process chamber 2 includes a first base 21, a first sputtering power supply and a first magnetron.
  • the tube mechanism 23, the first base 21 is used to carry the wafer, and the first sputtering power supply is used to provide the first sputtering power to the dielectric target 22, so that the first inert gas in the first process chamber 2 forms plasma.
  • the first magnetron mechanism 23 is used to guide the plasma in the first process chamber 2 to bombard the dielectric target 22; the second process chamber 3 is used to form a metal film on the dielectric film, and the second process chamber 3 It includes a second base 31, a second sputtering power supply and a second magnetron mechanism 33.
  • the second base 31 is used to carry the wafer, and the second sputtering power supply is used to provide the second sputtering power to the metal target 32. , so that the second inert gas in the second process chamber 3 forms a plasma, and the second magnetron mechanism 33 is used to guide the plasma in the second process chamber 3 to bombard the metal target 32 .
  • the semiconductor process equipment may be, for example, physical vapor deposition equipment.
  • the transfer chamber 1 may adopt a polygonal cavity structure.
  • the first process chamber 2 and the second process chamber 3 are arranged around the periphery of the transfer chamber 1, and the two process chambers are sequentially surrounded on both sides of the transfer chamber 1. on two sides, and are all connected to the transmission chamber 1.
  • a robot 11 is provided in the transfer chamber 1 for transferring wafers between the first process chamber 2 and the second process chamber 3 .
  • a front-end module 7 is also provided on one side of the transfer chamber 1.
  • the front-end module 7 can transfer the wafer into the transfer chamber 1, and the robot 11 in the transfer chamber 1 then transfers the wafer to the first In the process chamber 2 or the second process chamber 3.
  • the first process chamber 2 can accommodate and carry a wafer.
  • the first process chamber 2 can use a physical vapor deposition process to form a dielectric film 101 on the surface of the wafer. After the dielectric film 101 is formed on the surface of the wafer, the transmission
  • the manipulator 11 in the chamber 1 can transport the wafer from the first process chamber 2 to the second process chamber 3.
  • the second process chamber 3 also uses a physical vapor deposition process to form a dielectric film 101 on the surface of the wafer.
  • the metal film 102 is used to form a pair of laminated film structures 100 on the wafer surface.
  • the embodiment of the present application does not limit the number of dielectric films 101 and metal films 102 included in the laminated thin film structure 100.
  • the above process is alternately performed multiple times to form multiple pairs of laminated thin film structures 100 on the wafer surface.
  • the dielectric film 101 is first deposited on the wafer surface, and then the metal film 102 is formed on the surface of the dielectric film 101 on the wafer surface.
  • the embodiment of the present application is not limited to the deposition of the dielectric film 101 and the metal film 102
  • the metal film 102 can also be deposited on the wafer surface first, and then the dielectric film 101 can be formed on the metal film 102 on the wafer surface. Therefore, the embodiments of the present application are not limited to this. Those skilled in the art can decide according to the actual situation. Adjust the settings accordingly.
  • the specific structure of the first process chamber 2 is as follows: a first shield 24, a first shielding ring 25 and a first deposition ring 26 are provided in the first chamber 20, wherein the first A shielding member 24 is an annular sleeve structure and is nested in the first cavity 20 to prevent contamination of the inner wall of the first cavity 20 during the process.
  • the outer peripheral edge of the first shielding ring 25 overlaps the bottom end of the first shielding member 24, and the inner peripheral edge of the first shielding ring 25 overlaps the outer peripheral edge of the first deposition ring 26; the first deposition ring 26 is sleeved on the first On the base 21, the first base 21 is used to carry the wafer.
  • the dielectric target 22 covers the top of the first cavity 20
  • the first cover 28 is made of an insulating material (for example, G10 material) as a shell structure to cover the top of the dielectric target 22 .
  • the space between the first cover plate 28 and the dielectric target 22 is filled with deionized water for cooling the dielectric target 22 and the first magnetron mechanism 23 .
  • the first magnetron mechanism 23 is connected to the first rotating mechanism 27 and is fixedly arranged between the first cover plate 28 and the dielectric target 22.
  • the first magnetron mechanism 23 rotates around its own central axis to guide plasma bombardment. Dielectric target 22.
  • the first sputtering power supply (not shown in the figure) is connected to the dielectric target 22 and is used to provide the first sputtering power to the dielectric target 22 so that the first inert gas in the first process chamber 2 forms a plasma.
  • the bottom of the first chamber 20 may be connected to a vacuum system for maintaining the process pressure in the first process chamber 2 .
  • An air inlet is also provided on the wall of the first cavity 20 for introducing the first inert gas and the first process gas into the first cavity 20 .
  • the first inert gas is, for example, argon
  • the first process gas is, for example, oxygen.
  • the bombardment kinetic energy of the dielectric target 22 in the embodiment of the present application is relatively large, which not only greatly improves the density of the deposited film, but also greatly increases the productivity.
  • the above design can also significantly reduce the temperature during the process, thereby reducing the thermal stress inside the laminated thin film structure 100 to further improve the product yield.
  • the specific structure of the second process chamber 3 is that a second shield 34, a second shielding ring 35 and a second deposition ring 36 are provided in the second chamber 30, wherein
  • the second shielding member 34 has a ring sleeve structure and is nested in the second cavity 30 to prevent contamination of the inner wall of the second cavity 30 during the process.
  • the outer peripheral edge of the second shielding ring 35 overlaps the bottom end of the second shielding member 34
  • the inner peripheral edge of the second shielding ring 35 overlaps the outer peripheral edge of the second deposition ring 36 .
  • the second deposition ring 36 is sleeved on the second base 31 , and the second base 31 is used to carry the wafer.
  • the metal target 32 covers the top of the second cavity 30 , and the second cover 38 adopts a shell structure made of insulating material (for example, G10 material) to cover the top of the metal target 32 .
  • the space between the second cover plate 38 and the metal target 32 is filled with deionized water for cooling the metal target 32 and the second magnetron mechanism 33 .
  • the second magnetron mechanism 33 is connected to the second rotating mechanism 37 and is fixedly arranged between the second cover plate 38 and the metal target 32.
  • the second magnetron mechanism 33 rotates around its own central axis to guide the plasma bombardment. Metal target32.
  • the second sputtering power supply (not shown in the figure) is connected to the metal target 32 and is used to provide the second sputtering power to the metal target 32 so that the second inert gas in the second process chamber 3 forms a plasma.
  • the bottom of the second chamber 30 may be connected to a vacuum system for maintaining the process pressure in the second process chamber 3 .
  • An air inlet is also provided on the wall of the second cavity 30 for introducing a second inert gas into the second cavity 30 .
  • the second inert gas is, for example, argon gas.
  • the above design can also significantly reduce the temperature during the process, thereby reducing the thermal stress inside the laminated thin film structure 100 to further improve the product yield.
  • the embodiment of the present application has higher integration, not only It can reduce application and maintenance costs, and is also suitable for industrialization and large-scale production.
  • the wafer is transported between the first process chamber and the second process chamber through the transport chamber, and a dielectric film is formed on the wafer through the first process chamber, and the dielectric film is formed on the wafer through the second process chamber.
  • a metal film is formed on the circle, thereby forming one or more pairs of laminated film structures on the surface of the wafer. It should be noted that forming a dielectric film or a metal film on a wafer includes forming a dielectric film or a metal film on the surface of the wafer, and also includes forming a metal film on the surface of the dielectric film on the wafer. And the case where a dielectric film is formed on the surface of the metal film on the wafer.
  • both process chambers use the physical vapor deposition process to deposit thin films, and both are connected to the transmission chamber, the integration difficulty of the semiconductor process equipment in the embodiment of the present application is low, and due to the simple process flow, the production capacity is greatly improved while also It can prevent the wafer from being contaminated by the external environment to ensure product yield, and also facilitates commercial mass production.
  • the physical vapor deposition process is used to deposit the film, the temperature of the dielectric film and the metal film can be controlled near room temperature during the deposition process, preventing large thermal stress within the laminated film structure, thereby further improving the product yield.
  • the first sputtering power supply is a pulsed DC power supply
  • the material of the dielectric target 22 is silicon, silicon dioxide, silicon nitride or silicon oxynitride.
  • the dielectric target 22 is made of silicon, silicon dioxide, silicon nitride or silicon oxynitride, silicon dioxide will be formed on the surface of the dielectric target 22 during the physical vapor deposition process, so during the process During the process, it is easy to accumulate charges on the surface of the dielectric target 22 (actually the silicon dioxide on the surface of the dielectric target 22), thereby causing arc ignition (arc) on the surface of the dielectric target 22, resulting in excessive particles on the wafer surface.
  • arc arc ignition
  • the first sputtering power supply is connected to the dielectric target 22 using a pulsed DC power supply, and a mixed gas of argon and oxygen is introduced into the first cavity 20, and the first sputtering power supply intermittently applies a bias voltage to the dielectric target 22.
  • the dielectric target 22 becomes a negative voltage relative to the grounded first cavity 20, and a high voltage is generated at the moment when the first sputtering power supply is loaded to break down the argon gas in the first cavity 20 to generate plasma, thereby generating
  • the plasma activates the oxygen in the first cavity 20 to generate oxygen free radicals, which react with the silicon on the surface of the dielectric target 22 to generate silicon dioxide, and the positively charged argon ions are
  • the dielectric target 22 is attracted to the negative voltage, causing the first inert gas and the first process gas in the first cavity 20 to form plasma, bombarding the silicon dioxide formed on the surface of the dielectric target 22, and the bombarded silicon dioxide is deposited
  • a silicon dioxide film is generated on the wafer, that is, the dielectric film 101 is formed on the surface of the wafer.
  • parameters such as the power of the first sputtering power supply and the pressure of the first inert gas and the first process gas can also be adjusted.
  • the first sputtering power is 1kW to 5kW
  • the first process The process pressure in the chamber is 5 mTorr to 10 mTorr, which can reduce the accumulation of charges on the surface of the dielectric target 22 and avoid arc ignition on the surface of the dielectric target 22, thereby achieving the purpose of controlling particles.
  • the first sputtering power supply uses a pulsed DC power supply, arc ignition on the surface of the dielectric target 22 can be avoided to achieve the purpose of particle control, thereby improving the product yield of the wafer.
  • the embodiment of the present application does not limit the specific material of the dielectric target 22.
  • the dielectric target 22 can also be made of low-dielectric materials such as silicon nitride (SiNx) or silicon oxynitride. Therefore, the embodiments of the present application are not limited to this, and those skilled in the art can adjust the settings by themselves according to the actual situation.
  • the second process chamber 3 also includes a radio frequency power supply (not shown in the figure), and the radio frequency power supply is connected to the second base 31 for controlling the second process chamber 3 .
  • the second base 31 applies bias power.
  • the second sputtering power supply is a DC power supply
  • the material of the metal target 32 is tungsten or molybdenum.
  • the second sputtering power source can be a DC power source, and the second inert gas is argon.
  • the second sputtering power supply applies a bias voltage to the metal target 32 so that the metal target 32 becomes a negative voltage relative to the grounded second cavity 30, and a high voltage is generated at the moment when the second sputtering power supply is applied. , can break down the argon gas to generate plasma. The positively charged argon ions in the plasma are attracted to the metal target 32 with negative voltage.
  • a radio frequency power supply is connected below the second base 31.
  • the radio frequency power can form a negative voltage on the second base 31 to attract the metal target.
  • the escaped ions or argon ions in the plasma bombard the metal film on the wafer, which can adjust the stress of the film.
  • the second sputtering power supply uses a DC power supply, application and maintenance costs can be greatly reduced, and the applicability and scope of application of the embodiment of the present application can be greatly improved; in addition, the second base 31 is loaded with a radio frequency power supply, and also It can make the film stress more uniform, thereby improving the film deposition yield.
  • the embodiment of the present application does not limit the specific material of the metal target 32.
  • the metal target 32 can also be made of metal molybdenum or other materials with higher conductivity. Therefore, the embodiments of the present application are not limited to this, and those skilled in the art can adjust the settings by themselves according to the actual situation.
  • the semiconductor process equipment also includes a degassing chamber 4, a pre-cleaning chamber 5 and a preparation chamber 6.
  • the chamber 4 and a plurality of preparation chambers 6 are all arranged around the periphery of the transfer chamber 1.
  • the transfer chamber 1 is used for degassing chamber 4, pre-cleaning chamber 5, first process chamber 2 and second process chamber. Wafers are transferred between chambers 3; a plurality of preparation chambers 6 are of the same type as the first process chamber 2 and/or the second process chamber 3.
  • the transmission chamber 1 can specifically adopt an octagonal cavity structure, in which two adjacent sides can be provided with a front-end module 7, a degassing chamber 4, a pre-cleaning chamber 5,
  • the first process chamber 2 , the second process chamber 3 and the preparation chamber 6 are sequentially surrounded by the other six sides of the transfer chamber 1 , of which two preparation chambers 6 can be provided.
  • the degassing chamber 4 can be used to perform a degassing process on the wafer, that is, to remove water vapor on the wafer surface; and then the manipulator 11 in the transfer chamber 1 transfers the wafer to the pre-cleaning chamber 5.
  • the cleaning chamber 5 is used to perform a pre-cleaning process on the wafer surface to clean the organic matter and impurities on the wafer surface; at this time, the robot 11 in the transfer chamber 1 transfers the wafer to the first process chamber 2 to A dielectric film 101 is formed on the surface of the wafer, and then the robot 11 transports the wafer to the second process chamber 3 to form a metal film 102 on the dielectric film 101 on the surface of the wafer to form a laminated film structure 100 .
  • preparation chambers 6 There may be two preparation chambers 6 , one of which may be of the same type as the first process chamber 2 , and the other preparation chamber 6 may be of the same type as the second process chamber 3 , so that Improve the preparation of laminated thin films in the embodiments of this application
  • the efficiency of the membrane structure 100 is further improved, thereby further improving production capacity.
  • Adopting the above design makes the wafer transfer process in the embodiment of the present application simple and fast, thereby greatly improving work efficiency and production capacity.
  • the embodiment of the present application does not limit the specific type and quantity of the preparation chamber 6.
  • the preparation chamber 6 can also be configured as a degassing chamber 4 or a pre-cleaning chamber 5. Therefore, the embodiments of the present application are not limited to this, and those skilled in the art can adjust the settings by themselves according to the actual situation.
  • embodiments of the present application provide a method for forming a laminated thin film structure on the surface of a wafer.
  • the schematic flow chart of the method for forming a laminated thin film structure is shown in Figure 4. Includes the following steps:
  • the wafer can be transferred to the first base in the first process chamber through the transfer chamber; a mixed gas of the first inert gas and the first process gas is introduced into the first process chamber. , apply the first sputtering power to the dielectric target, causing the first inert gas to form a plasma.
  • the plasma causes the first process gas to generate free radicals.
  • the free radicals react with the dielectric target.
  • the plasma bombards the dielectric target. , to deposit a dielectric film on the wafer.
  • the wafer can be transferred from the first process chamber to the second base in the second process chamber through the transfer chamber; the second inert gas is introduced into the second process chamber to A second sputtering power is applied to the metal target to cause the second inert gas to form a plasma, and the plasma bombards the metal target to form a metal film on the wafer.
  • the first sputtering step and the second sputtering step are repeatedly performed to deposit alternately stacked dielectric films and metal films on the surface of the wafer to form a stacked film structure.
  • the embodiment of the present application does not limit the order in which the dielectric film 101 and the metal film 102 are deposited.
  • the dielectric film 101 can be deposited on the wafer surface first, and then the metal film 102 can be formed on the dielectric film 101 on the wafer surface, or the metal film 102 can be formed first.
  • a metal film 102 is deposited on the wafer surface, and then a dielectric film 101 is formed on the metal film 102 on the wafer surface.
  • the dielectric film 101 deposited through the first sputtering step serves as the last film of the laminated thin film structure 100 .
  • the semiconductor process equipment may include a lower computer.
  • the lower computer may control the movement of the robot 11 in the transfer chamber 1 .
  • the robot 11 in the transfer chamber 1 transfers the wafer to the first process.
  • the first base 21 is used to hold the wafer.
  • a mixed gas of argon and oxygen is introduced into the first chamber 20 , that is, a mixed gas of the first inert gas and the first process gas is introduced into the first process chamber 2 , and the first sputtering power supply supplies the dielectric target to the dielectric target. 22. Apply the first sputtering power to form a plasma from the first inert gas in the first cavity 20.
  • the generated plasma activates the oxygen in the first cavity 20 to generate oxygen radicals.
  • the oxygen radicals interact with the dielectric target.
  • the silicon on the surface of the material 22 reacts to generate silicon dioxide.
  • the silicon dioxide formed on the surface of the dielectric target 22 is bombarded.
  • the bombarded silicon dioxide is deposited on the wafer to form a silicon dioxide film to form a dielectric film 101 on the wafer. That is, the first sputtering step is performed.
  • the robot 11 then transfers the wafer to the second process chamber 3 , and the second base 31 is used to carry the wafer.
  • Argon gas is introduced into the second chamber 30, that is, the second inert gas is introduced into the second process chamber 3, and the second sputtering power supply applies the second sputtering power to the metal target 32, which can penetrate the argon gas.
  • a second sputtering step is performed on the wafer to form the metal thin film 102 on the wafer.
  • the first sputtering step and the second sputtering step are alternately performed according to actual needs to obtain different pairs of laminated thin film structures 100 .
  • the number of pairs of the laminated thin film structure 100 can be two pairs, four pairs, or even one hundred pairs. , specifically, as shown in FIG.
  • the overall thickness of the laminated thin film structure 100 can be set to 15 nm to 100,000 nm, preferably 1,000 nm to 10,000 nm, but the embodiments of the present application are not limited to this.
  • the first process chamber 2 can be used to form a dielectric film 101 on the surface of the metal film 102 as the uppermost layer of the laminated thin film structure 100 as a protective film. That is, when the laminated thin film structure 100 is formed on the wafer surface, the first process chamber 2 is used to form the dielectric film 101 on the surface of the metal film 102.
  • the dielectric film 101 deposited in a sputtering step serves as the last film of the stacked film structure 100 .
  • the laminated thin film structure 100 is prepared using a physical vapor deposition process, the temperature of the laminated thin film structure 100 is lower, thereby avoiding the occurrence of large thermal shock in the laminated thin film structure 100. Thermal stress, thereby improving product yield.
  • the transfer chamber 1 is used to transfer the wafer in the first process chamber 2 and the second process chamber 3, contamination caused by contact between the wafer and the external environment can be avoided, thereby further improving product yield.
  • the second sputtering step further includes: applying bias power to the second base 31 to attract ions escaped from the metal target 32 to bombard the wafer. , to adjust the stress of the metal film 102.
  • a radio frequency power supply is connected below the second base 31.
  • the radio frequency power supply can form a negative voltage on the second base 31 to attract ions escaped from the metal target 32 or argon ions in the plasma to bombard the crystal.
  • the metal film 102 on the circle can adjust the film stress, making the film stress more uniform, thereby improving the film deposition yield.
  • a degassing step is also included: transferring the wafer to the third base of the degassing chamber. , heat the wafer to 100°C to 500°C and maintain it for 10 seconds to 200 seconds to remove water vapor on the wafer.
  • the lower computer can control the movement of the manipulator 11 in the transfer chamber 1.
  • the manipulator 11 can transfer the wafers in the front-end module 7 to the degassing chamber 4.
  • the third base in the degassing chamber 4 can Used to carry the wafer, the third base can heat the wafer to between 100°C and 500°C and maintain it for 10 seconds to 200 seconds to remove water vapor on the wafer surface.
  • the wafer that has completed the degassing step is then transferred to the first process chamber 2 for performing the first sputtering step.
  • the embodiments of the present application do not limit the specific process parameters of the degassing step, and those skilled in the art can adjust the settings by themselves according to the actual situation.
  • a pre-cleaning step is also included: the wafer is removed from the degassing chamber. Transfer to the fourth base of the pre-cleaning chamber, introduce a third inert gas into the pre-cleaning chamber, and apply radio frequency power to the fourth base to attract the plasma generated by the third inert gas to bombard the surface of the wafer , to remove impurities from the surface of the wafer.
  • the lower computer can control the movement of the manipulator 11 in the transfer chamber 1, and the manipulator 11 can transfer the wafers in the degassing chamber 4 to the pre-cleaning chamber.
  • the fourth base in the pre-cleaning chamber 5 can be used to carry the wafer, and a third inert gas can be introduced into the pre-cleaning chamber 5.
  • the third inert gas can be argon, but this The application embodiment is not limited to this.
  • the fourth base can apply radio frequency power to the wafer to attract the plasma generated by the third inert gas, so that the plasma can bombard the surface of the wafer, that is, the pre-cleaning chamber 5 can perform pre-cleaning on the wafer surface.
  • the wafer that has completed the pre-cleaning step is transferred to the first process chamber 2 for performing the first sputtering step.
  • the wafer surface is relatively clean, it can effectively avoid film deposition defects caused by organic matter and impurities, thus greatly improving the yield of wafer film deposition.
  • the embodiments of the present application do not limit the specific type of the third inert gas, and those skilled in the art can adjust the settings by themselves according to the actual situation.
  • the first inert gas is argon
  • the first process gas is oxygen
  • the proportion of oxygen in the mixed gas is More than 30%
  • the material of the dielectric target is silicon
  • the dielectric film is a silicon dioxide film.
  • the first sputtering power is pulsed DC power, and the pulsed DC power is 0.01kW ⁇ 10kW; the process pressure in the first process chamber is 0.01mTorr ⁇ 100mTorr; and the thickness of the single-layer dielectric film is 3nm ⁇ 100nm.
  • the mixed gas introduced through the air inlet of the first process chamber 2 is argon and oxygen, and the proportion of oxygen in the mixed gas is 30%
  • the above means that the first inert gas is argon, the first process gas is oxygen, and the proportion of oxygen in the mixed gas is more than 30%.
  • the first sputtering power supply is a pulsed DC power supply, and the specific value of the first sputtering power is 0.01kW to 10kW, which is used to apply a bias voltage to the dielectric target 22.
  • the material of the dielectric target 22 is, for example, silicon, so that the dielectric
  • the film 101 is a silicon dioxide film.
  • the vacuum system can control the process pressure of the first process chamber 2 between 0.01mTorr and 100mTorr.
  • the specific time for performing sputtering is not limited, as long as the thickness of the single-layer dielectric film 101 reaches 3nm to 100nm.
  • the laminated film structure 100 prepared in the embodiment of the present application is not only suitable for 3D NAND flash memory field, and can also be applied to other fields, thereby greatly improving the applicability and application scope of the embodiments of the present application.
  • the first sputtering power of the first sputtering power supply can be set to 1kW to 5kW, and the process pressure in the first process chamber 2 can be adjusted to 5mTorr to 10mTorr through the vacuum system, thereby controlling the dielectric film 101 Between 5 nm and 10 nm, using this process environment can reduce the accumulation of charges on the surface of the dielectric target 22 , thereby preventing arc ignition (arc) from occurring on the surface of the dielectric target 22 .
  • arc arc ignition
  • the second inert gas is argon
  • the material of the dielectric target is tungsten
  • the metal film is a tungsten film.
  • the second sputtering power is DC power, and the DC power is 0.01kW ⁇ 20kW; the bias power is RF power, and the RF power is 0.01kW ⁇ 2kW; the process pressure in the second process chamber is 0.01mTorr ⁇ 100mTorr;
  • the thickness of a single-layer metal film is 3nm to 1000nm.
  • the second sputtering step argon gas is introduced into the air inlet of the second process chamber 3 , that is, the second inert gas is argon gas.
  • the second sputtering power supply is a DC power supply, and the specific value of the second sputtering power is 0.01kW to 20kW, which is used to apply a bias voltage to the metal target 32.
  • the material of the metal target 32 is, for example, tungsten, so that the metal target 32 is made of tungsten.
  • the film is a tungsten film. Due to the characteristics of the metal target 32 itself, the second sputtering power of the second sputtering power source needs to be set relatively high to ensure the deposition rate.
  • the second sputtering power can be set between 0.01kW and 20kW, but The embodiments of the present application are not limited to this.
  • the second base 31 can load radio frequency power on the wafer, that is, the bias power is radio frequency power, and the radio frequency power is 0.01kW ⁇ 2kW, but the embodiment of the present application is not limited to this.
  • the vacuum system can control the process pressure of the second process chamber 3 at 0.01mTorr ⁇ 100mTorr, but the time for performing sputtering is not limited, as long as the thickness of the single-layer metal film 102 reaches 3nm ⁇ 1000nm, since it needs to be
  • the metal film 102 is etched with patterns, so the metal film 102 is thicker than the dielectric film 101 .
  • the stack prepared in the embodiment of the present application The thin film structure 100 can not only be applied in the field of 3D NAND flash memory, but also can be applied in other fields, thereby greatly improving the applicability and scope of the embodiments of the present application.
  • the second sputtering power can be set to 1kW to 5kW
  • the RF power loaded by the second base 31 to the wafer is 1kW to 2kW
  • the process pressure in the second process chamber 3 is adjusted through the vacuum system to 5mTorr ⁇ 10mTorr, thereby controlling the dielectric film 101 to be 10nm ⁇ 100nm.
  • the deposition rate can be adjusted, but also the film deposition thickness can be accurately controlled, thereby improving the work efficiency and improving the yield of the dielectric film 101.
  • the wafer is transported between the first process chamber and the second process chamber through the transport chamber, and a dielectric film is formed on the wafer through the first process chamber, and the dielectric film is formed on the wafer through the second process chamber.
  • a metal film is formed on the circle, thereby forming one or more pairs of laminated film structures on the surface of the wafer. Since both process chambers use the physical vapor deposition process to deposit thin films, and both are connected to the transmission chamber, the integration difficulty of the semiconductor process equipment in the embodiment of the present application is low, and due to the simple process flow, the production capacity is greatly improved while also It can prevent the wafer from being contaminated by the external environment to ensure product yield, and also facilitates commercial mass production. In addition, because the physical vapor deposition process is used to deposit the film, the temperature of the dielectric film and the metal film can be controlled near room temperature during the deposition process, preventing large thermal stress within the laminated film structure, thereby further improving the product yield.
  • steps, measures, and solutions in the various operations, methods, and processes that have been discussed in this application can be alternated, changed, combined, or deleted.
  • steps, measures, and solutions in the various operations, methods, and processes that have been discussed in this application can also be alternated, changed, rearranged, decomposed, combined, or deleted.
  • steps, measures, and solutions in the various operations, methods, and processes disclosed in this application can also be alternated, changed, rearranged, decomposed, combined, or deleted.
  • first and second are used for descriptive purposes only and shall not be understood as indicating or implying relative importance or implicitly indicating the quantity of indicated technical features. Therefore, features defined as “first” and “second” may explicitly or implicitly include one or more of these features. In the description of the present invention, unless otherwise specified, "plurality" means two or more.
  • connection should be understood in a broad sense.
  • connection or integral connection; it can be directly connected, or indirectly connected through an intermediary, or it can be internal connection between two components.
  • connection or integral connection; it can be directly connected, or indirectly connected through an intermediary, or it can be internal connection between two components.

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Abstract

本申请实施例提供了一种半导体工艺设备及形成叠层薄膜结构的方法。该形成叠层薄膜结构的方法包括：第一溅射步骤，将待沉积薄膜的晶圆传输至第一工艺腔室内的第一基座上，对介质靶材施加第一溅射功率，以在晶圆的表面沉积形成介质薄膜；第二溅射步骤，将溅射有介质薄膜的晶圆由第一工艺腔室内传输至第二工艺腔室内的第二基座上，对金属靶材施加第二溅射功率，以在介质薄膜上形成金属薄膜；重复执行第一溅射步骤及第二溅射步骤，以在晶圆的表面沉积交替叠层的介质薄膜和金属薄膜，形成叠层薄膜结构。本申请实施例实现了大幅提升产能的同时，还能确保产品的良率，并且还能避免叠层薄膜结构内部产生较大的热应力，从而进一步提高产品的良率。

Description

半导体工艺设备及形成叠层薄膜结构的方法 技术领域
本申请涉及半导体加工技术领域，具体而言，本申请涉及一种半导体工艺设备及形成叠层薄膜结构的方法。
背景技术
目前，NAND闪存是一种非易失性存储技术，即断电后仍能保存数据，它的发展目标就是降低每比特存储成本以及提高存储容量。平面结构的NAND闪存已接近其实际扩展极限，给半导体存储器行业带来严峻挑战。新的3D NAND闪存技术是在垂直方向上堆叠多层数据存储单元，其不仅具备卓越的精度，而且还可打造出存储容量比平面结构的NAND闪存技术高达三倍的存储设备，从而实现了在更小的空间内容纳更高存储容量，进而带来很大的成本节约及能耗降低，因此大幅的性能提升能全面满足众多消费类移动设备和要求最严苛的企业部署的需求。
现有技术中，3D NAND闪存的制备工艺十分复杂，需要采用化学气相沉积工艺(Chemical Vapor Deposition，CVD)在晶圆表面形成由金属钨材质及二氧化硅材质构成的叠层薄膜结构，该叠层薄膜结构在3D NAND闪存中作为控制栅(Control Gate)，具体流程为先使用CVD方式形成氮化硅(SiNx)及二氧化硅叠层，再使用干法刻蚀方式刻出特定图形，然后使用湿法刻蚀将氮化硅去除，再用CVD方式形成金属钨膜层填充氮化硅的位置，从而形成金属钨材质及二氧化硅材质构成的叠层薄膜结构。但是，现有技术中形成叠层薄膜结构由于其本身工艺过程较为复杂，导致产品良率较低且影响产能；另外，由于金属钨材质和二氧化硅材质的热膨胀系数差异较大，以及在形成过程中需要高温环境且完成后需要降低至室温，因此导致采用现有技术制成 的叠层薄膜结构内会产生较大的热应力，从而进一步影响产品良率。
发明内容
本申请针对现有方式的缺点，提出一种半导体工艺设备及形成叠层薄膜结构的方法，用以解决现有技术存在的产品良率较低且影响产能的技术问题。
第一个方面，本申请实施例提供了一种形成叠层薄膜结构的方法，用于在晶圆的表面形成叠层薄膜结构，所述方法包括：第一溅射步骤，将晶圆传输至第一工艺腔室内的第一基座上；向所述第一工艺腔室内通入第一惰性气体和第一工艺气体的混合气体，对介质靶材施加第一溅射功率，使所述第一惰性气体形成等离子体，该等离子体使所述第一工艺气体产生自由基，该自由基与所述介质靶材发生反应，该等离子体轰击所述介质靶材，以在所述晶圆上沉积形成介质薄膜；
第二溅射步骤，将晶圆传输至第二工艺腔室内的第二基座上；向所述第二工艺腔室内通入第二惰性气体，对金属靶材施加第二溅射功率，使所述第二惰性气体形成等离子体，该等离子体轰击所述金属靶材，以在所述晶圆上形成金属薄膜；
重复执行所述第一溅射步骤及所述第二溅射步骤，以在所述晶圆的表面沉积交替叠层的所述介质薄膜和所述金属薄膜，形成所述叠层薄膜结构。
于本申请的一实施例中，所述第二溅射步骤还包括：对所述第二基座施加偏压功率，吸引所述金属靶材上逸出的离子轰击所述晶圆，以调整所述金属薄膜的应力。
于本申请的一实施例中，在执行第一次所述第一溅射步骤之前还包括去气步骤：将所述晶圆传输至去气腔室的第三基座上，将所述晶圆加热至100℃～500℃，并维持10秒～200秒，以去除所述晶圆上的水汽。
于本申请的一实施例中，在所述去气步骤之后，且在执行第一次所述第一溅射步骤之前还包括预清洗步骤：将所述晶圆由所述去气腔室传输至预清 洗腔室的第四基座上，向所述预清洗腔室中通入第三惰性气体，并对所述第四基座施加射频功率，吸引所述第三惰性气体产生的等离子体轰击所述晶圆的表面，以去除所述晶圆的表面的杂质。
于本申请的一实施例中，在所述晶圆表面形成所述叠层薄膜结构时，通过所述第一溅射步骤所沉积的所述介质薄膜作为所述叠层薄膜结构的最后一层薄膜。
于本申请的一实施例中，在所述第一溅射步骤中：所述第一惰性气体为氩气，所述第一工艺气体为氧气，所述氧气在所述混合气体中的占比为30％以上，所述介质靶材的材料为硅，所述介质薄膜为二氧化硅薄膜。
于本申请的一实施例中，所述第一溅射功率为脉冲直流功率，所述脉冲直流功率为0.01kW～10kW；所述第一工艺腔室内的工艺压力为0.01mTorr～100mTorr；单层所述介质薄膜的厚度为3nm～100nm。
于本申请的一实施例中，在所述第二溅射步骤中，所述第二惰性气体为氩气，所述金属靶材的材料为钨，所述金属薄膜为钨薄膜。
于本申请的一实施例中，所述第二溅射功率为直流功率，所述直流功率为0.01kW～20kW；所述偏压功率为射频功率，所述射频功率为0.01kW～2kW；所述第二工艺腔室内的工艺压力为0.01mTorr～100mTorr；单层所述金属薄膜的厚度为3nm～1000nm。
第二个方面，本申请实施例提供了一种半导体工艺设备，用于在晶圆的表面形成叠层薄膜结构，包括：传输腔室、第一工艺腔室、第二工艺腔室；所述第一工艺腔室及所述第二工艺腔室与所述传输腔室连接，所述传输腔室用于向所述第一工艺腔室或者所述第二工艺腔室内传输所述晶圆；所述第一工艺腔室用于在所述晶圆表面及金属薄膜表面形成介质薄膜，所述第一工艺腔室包括第一基座、第一溅射电源及第一磁控管机构，所述第一基座用于承载所述晶圆，所述第一溅射电源用于向介质靶材提供第一溅射功率，以使第 一工艺腔室内的第一惰性气体及第一工艺气体形成等离子体，所述第一磁控管机构用于引导所述第一工艺腔室内的等离子体轰击所述介质靶材；所述第二工艺腔室用于在所述介质薄膜上形成所述金属薄膜，所述第二工艺腔室包括第二基座、第二溅射电源及第二磁控管机构，所述第二基座用于承载所述晶圆，所述第二溅射电源用于向金属靶材提供第二溅射功率，以使第二工艺腔室内的第二惰性气体形成等离子体，所述第二磁控管机构用于引导所述第二工艺腔室内的等离子体轰击所述金属靶材。
本申请实施例提供的技术方案带来的有益技术效果是：
本申请实施例通过传输腔室在第一工艺腔室及第二工艺腔室之间传输晶圆，并且通过第一工艺腔室在晶圆上形成介质薄膜，以及通过第二工艺腔室在晶圆上形成金属薄膜，从而实现在晶圆表面形成一对或多对的叠层薄膜结构。由于两个工艺腔室均采用物理气相沉积工艺沉积薄膜，并且均与传输腔室连接，使得本申请实施例的半导体工艺设备集成难度低，并且由于工艺流程简单，从而大幅提升产能的同时，还能避免晶圆受到外界环境的污染以确保产品的良率，并且还便于商业化量产。另外，由于采用物理气相沉积工艺沉积薄膜，使得介质薄膜及金属薄膜在沉积过程中温度可以控制在室温附近，防止叠层薄膜结构内部产生较大的热应力，从而进一步提高产品的良率。
本申请附加的方面和优点将在下面的描述中部分给出，这些将从下面的描述中变得明显，或通过本申请的实践了解到。
附图说明
本申请上述的和/或附加的方面和优点从下面结合附图对实施例的描述中将变得明显和容易理解，其中：
图1为本申请实施例提供的一种半导体工艺设备的俯视结构示意图；
图2为本申请实施例提供的一种第一工艺腔室的剖视结构示意图；
图3为本申请实施例提供的一种第二工艺腔室的剖视结构示意图；
图4为本申请实施例提供的一种叠层薄膜结构制备方法中的流程示意图；
图5为本申请实施例提供的一种叠层薄膜结构的剖视示意图。
具体实施方式
下面详细描述本申请，本申请的实施例的示例在附图中示出，其中自始至终相同或类似的标号表示相同或类似的部件或具有相同或类似功能的部件。此外，如果已知技术的详细描述对于示出的本申请的特征是不必要的，则将其省略。下面通过参考附图描述的实施例是示例性的，仅用于解释本申请，而不能解释为对本申请的限制。
本技术领域技术人员可以理解，除非另外定义，这里使用的所有术语(包括技术术语和科学术语)，具有与本申请所属领域中的普通技术人员的一般理解相同的意义。还应该理解的是，诸如通用字典中定义的那些术语，应该被理解为具有与现有技术的上下文中的意义一致的意义，并且除非像这里一样被特定定义，否则不会用理想化或过于正式的含义来解释。
本技术领域技术人员可以理解，除非特意声明，这里使用的单数形式“一”、“一个”、“所述”和“该”也可包括复数形式。应该进一步理解的是，本申请的说明书中使用的措辞“包括”是指存在所述特征、整数、步骤、操作、元件和/或组件，但是并不排除存在或添加一个或多个其他特征、整数、步骤、操作、元件、组件和/或它们的组。应该理解，当我们称元件被“连接”或“耦接”到另一元件时，它可以直接连接或耦接到其他元件，或者也可以存在中间元件。此外，这里使用的“连接”或“耦接”可以包括无线连接或无线耦接。这里使用的措辞“和/或”包括一个或更多个相关联的列出项的全部或任一单元和全部组合。
下面以具体地实施例对本申请的技术方案以及本申请的技术方案如何解决上述技术问题进行详细说明。
本申请实施例提供了一种半导体工艺设备，该半导体工艺设备的结构示意图如图1至图3所示，用于在晶圆的表面形成叠层薄膜结构，包括：传输腔室1、第一工艺腔室2、第二工艺腔室3；第一工艺腔室2及第二工艺腔室3与传输腔室1连接，传输腔室1用于向第一工艺腔室2或者第二工艺腔室3内传输晶圆；第一工艺腔室2用于在晶圆表面及金属薄膜表面形成介质薄膜，第一工艺腔室2包括第一基座21、第一溅射电源及第一磁控管机构23，第一基座21用于承载晶圆，第一溅射电源用于向介质靶材22提供第一溅射功率，以使第一工艺腔室2内的第一惰性气体形成等离子体，第一磁控管机构23用于引导第一工艺腔室2内的等离子体轰击介质靶材22；第二工艺腔室3用于在介质薄膜上形成金属薄膜，第二工艺腔室3包括第二基座31、第二溅射电源及第二磁控管机构33，第二基座31用于承载晶圆，第二溅射电源用于向金属靶材32提供第二溅射功率，以使第二工艺腔室3内的第二惰性气体形成等离子体，第二磁控管机构33用于引导第二工艺腔室3内的等离子体轰击金属靶材32。
如图1及图5所示，半导体工艺设备例如可以是物理气相沉积设备，但是本申请实施例并不限定半导体工艺设备的具体类型，只要其可以执行物理气相沉积工艺即可，因此本申请实施例并不以此为限。传输腔室1可以采用多边形的腔体结构，第一工艺腔室2及第二工艺腔室3环绕于传输腔室1的外周设置，并且两个工艺腔室依次环绕在传输腔室1的两个侧边上，并且均与传输腔室1连通设置。传输腔室1内设置有机械手11，用于在第一工艺腔室2及第二工艺腔室3之间传输晶圆。可选地，传输腔室1的一侧边还设置有前端模块7，前端模块7可以将晶圆传输至传输腔室1内，传输腔室1内的机械手11再将晶圆传输至第一工艺腔室2或者第二工艺腔室3内。第一工艺腔室2内可以容置并承载晶圆，第一工艺腔室2可以采用物理气相沉积工艺在晶圆表面形成介质薄膜101，待晶圆的表面形成介质薄膜101后，传输 腔室1内的机械手11能将晶圆由第一工艺腔室2传输至第二工艺腔室3内，第二工艺腔室3同样采用物理气相沉积工艺在晶圆表面的介质薄膜101表面形成金属薄膜102，以在晶圆表面形成成对的叠层薄膜结构100。但是本申请实施例并不限定叠层薄膜结构100包括的介质薄膜101及金属薄膜102的数量，例如多次交替执行上述工艺，以在晶圆表面形成多对的叠层薄膜结构100。在上述实施例中，先在晶圆表面沉积形成介质薄膜101，后在晶圆表面的介质薄膜101表面形成金属薄膜102，但是，本申请实施例并不限定介质薄膜101和金属薄膜102的沉积先后顺序，也可以先在晶圆表面沉积形成金属薄膜102，后在晶圆表面的金属薄膜102沉积形成介质薄膜101，因此本申请实施例并不以此为限，本领域技术人员可以根据实际情况自行调整设置。
如图1、图2及图5所示，第一工艺腔室2具体结构为，第一腔体20内设置有第一屏蔽件24、第一遮蔽环25及第一沉积环26，其中第一屏蔽件24为圆环套筒结构，嵌套于第一腔体20内，用于防止工艺过程中污染第一腔体20的内壁。第一遮蔽环25的外周缘搭接于第一屏蔽件24的底端，第一遮蔽环25的内周缘搭接于第一沉积环26的外周缘；第一沉积环26套设于第一基座21上，第一基座21用于承载晶圆。介质靶材22盖合于第一腔体20的顶端，第一盖板28采用绝缘材料制成(例如为G10材料)壳体结构，以盖合于介质靶材22的顶部。在第一盖板28与介质靶材22之间充满去离子水，用于冷却介质靶材22和第一磁控管机构23。第一磁控管机构23与第一旋转机构27连接，固定设置于第一盖板28与介质靶材22之间，第一磁控管机构23绕其自身中心轴转动，以引导等离子体轰击介质靶材22。第一溅射电源(图中未示出)与介质靶材22连接，用于向介质靶材22提供第一溅射功率，以使第一工艺腔室2内的第一惰性气体形成等离子体。第一腔体20的底部可以与真空系统连接，以用于保持第一工艺腔室2内的工艺压力。第一腔体20的壁上还开设有进气口，用于向第一腔体20内通入第一惰性及第一工艺气 体，该第一惰性气体例如是氩气，该第一工艺气体例如是氧气。采用上述设计，使得本申请实施例对于介质靶材22的轰击动能较大，不仅能大幅提高沉积薄膜的致密性，而且还能大幅提高产能。此外采用上述设计还能大幅降低工艺过程中的温度，从而降低叠层薄膜结构100内部的热应力，以进一步提高要产品良率。
如图1、图3及图5所示，第二工艺腔室3的具体结构为，第二腔体30内设置有第二屏蔽件34、第二遮蔽环35及第二沉积环36，其中第二屏蔽件34为圆环套筒结构，嵌套于第二腔体30内，用于防止工艺过程中污染第二腔体30的内壁。第二遮蔽环35的外周缘搭接于第二屏蔽件34的底端，第二遮蔽环35的内周缘搭接于第二沉积环36的外周缘。第二沉积环36套设于第二基座31上，第二基座31用于承载晶圆。金属靶材32盖合于第二腔体30的顶端，第二盖板38采用绝缘材料制成(例如为G10材料)的壳体结构，以盖合于金属靶材32的顶部。第二盖板38与金属靶材32之间充满去离子水，用于冷却金属靶材32和第二磁控管机构33。第二磁控管机构33与第二旋转机构37连接，固定设置于第二盖板38与金属靶材32之间，第二磁控管机构33绕其自身中心轴转动，以引导等离子体轰击金属靶材32。第二溅射电源(图中未示出)与金属靶材32连接，用于向金属靶材32提供第二溅射功率，以使第二工艺腔室3内的第二惰性气体形成等离子体。第二腔体30的底部可以与真空系统连接，以用于保持第二工艺腔室3内的工艺压力。第二腔体30的壁上还开设有进气口，用于向第二腔体30内通入第二惰性气体，该第二惰性气体例如是氩气。采用上述设计，使得本申请实施例对于金属靶材32的轰击动能较大，不仅能大幅提高沉积薄膜的致密性，而且还能大幅提高产能。此外采用上述设计还能大幅降低工艺过程中的温度，从而降低叠层薄膜结构100内部的热应力，以进一步提高要产品良率。进一步的，由于第二工艺腔室3与第一工艺腔室2采用类似结构，使得本申请实施例集成性较高，不仅 能降低应用及维护成本，而且还能适用于产业化及规模化生产。
本申请实施例通过传输腔室在第一工艺腔室及第二工艺腔室之间传输晶圆，并且通过第一工艺腔室在晶圆上形成介质薄膜，以及通过第二工艺腔室在晶圆上形成金属薄膜，从而实现在晶圆表面形成一对或多对的叠层薄膜结构。需要说明的是，在晶圆上形成介质薄膜或金属薄膜，包含了在晶圆表面上形成介质薄膜或金属薄膜的情况，也包含了在晶圆上的介质薄膜的表面形成金属薄膜的情况，以及在晶圆上的金属薄膜的表面形成介质薄膜的情况。
由于两个工艺腔室均采用物理气相沉积工艺沉积薄膜，并且均与传输腔室连接，使得本申请实施例的半导体工艺设备集成难度低，并且由于工艺流程简单，从而大幅提升产能的同时，还能避免晶圆受到外界环境的污染以确保产品的良率，并且还便于商业化量产。另外，由于采用物理气相沉积工艺沉积薄膜，使得介质薄膜及金属薄膜在沉积过程中温度可以控制在室温附近，防止叠层薄膜结构内部产生较大的热应力，从而进一步提高产品的良率。
于本申请的一实施例，如图1及图2所示，第一溅射电源为脉冲直流电源，介质靶材22的材质为硅、二氧化硅、氮化硅或者氮氧化硅。
如图1及图2所示，由于介质靶材22采用硅、二氧化硅、氮化硅或者氮氧化硅，在采用物理气相沉积过程中介质靶材22表面会形成二氧化硅，所以在工艺过程中容易在介质靶材22表面(实际为介质靶材22表面的二氧化硅)产生电荷的累积，从而在介质靶材22表面发生电弧打火(arc)，导致晶圆表面的颗粒超标。因此采用第一溅射电源采用脉冲直流电源与介质靶材22连接，并且在第一腔体20内通入氩气和氧气的混合气体，第一溅射电源间歇式施加偏压至介质靶材22上，使介质靶材22相对于接地的第一腔体20成为负电压，第一溅射电源加载的瞬间产生高压，以击穿第一腔体20内的氩气而产生等离子体，产生的等离子体将第一腔体20中的氧气活化以产生氧自由基，氧自由基与介质靶材22表面的硅反应生成二氧化硅，带正电的氩离子被 吸引向负电压的介质靶材22，即使第一腔体20内的第一惰性气体及第一工艺气体形成等离子体，轰击介质靶材22表面形成的二氧化硅，轰击下来的二氧化硅沉积在晶圆上生成二氧化硅薄膜，即在晶圆表面形成介质薄膜101。可选地，在本实施例中还可以通过调整第一溅射电源的功率和第一惰性气体及第一工艺气体的压力等参数，例如，第一溅射功率为1kW～5kW，第一工艺腔室内的工艺压力为5mTorr～10mTorr，可减少电荷在介质靶材22表面的累积，避免介质靶材22表面发生电弧打火，从而达到控制颗粒的目的。采用上述设计，由于第一溅射电源采用脉冲直流电源，能避免介质靶材22表面发生电弧打火以达到控制颗粒的目的，从而提高晶圆的产品良率。
需要说明的是，本申请实施例并不限定介质靶材22的具体材质，例如介质靶材22还可以采用氮化硅(SiNx)或者氮氧化硅等低介质材料。因此本申请实施例并不以此为限，本领域技术人员可以根据实际情况自行调整设置。
于本申请的一实施例中，如图1及图3所示，第二工艺腔室3还包括射频电源(图中未示出)，射频电源与第二基座31连接，用于对第二基座31施加偏压功率。可选地，第二溅射电源为直流电源，金属靶材32的材质为钨或者钼。
如图1及图3所示，由于金属靶材32采用金属钨材质制成，因此第二溅射电源可以采用直流电源，并且第二惰性气体为氩气。在实际应用时，第二溅射电源将偏压施加至金属靶材32上，以使得金属靶材32相对于接地的第二腔体30成为负电压，第二溅射电源加载的瞬间产生高压，可击穿氩气而产生等离子体，等离子体中带正电的氩离子被吸引至负电压的金属靶材32，当氩离子的能量足够高时，会使金属靶材32上的粒子或离子逸出并沉积在晶圆表面上，即在晶圆表面的介质薄膜上形成金属薄膜。在第二基座31的下方连接有射频电源，射频电源能在第二基座31上形成负电压，以吸引金属靶材 32逸出的离子或等离子体中的氩离子轰击晶圆上的金属薄膜，可以起到调整薄膜应力的作用。采用上述设计，由于第二溅射电源采用直流电源能大幅降低应用及维护成本，并且还能大幅提高本申请实施例的适用性及适用范围；另外第二基座31上加载有射频电源，还能使得薄膜应力较为均匀，从而提高薄膜沉积良率。
需要说明的是，本申请实施例并不限定金属靶材32的具体材质，例如金属靶材32还可以采用金属钼材质或者其它较高导电系数的材质。因此本申请实施例并不以此为限，本领域技术人员可以根据实际情况自行调整设置。
于本申请的一实施例中，如图1及图5所示，半导体工艺设备还包括有去气腔室4、预清洗腔室5及预备腔室6，预清洗腔室5、去气腔室4及多个预备腔室6均环绕设置于传输腔室1的外周，传输腔室1用于在去气腔室4、预清洗腔室5、第一工艺腔室2及第二工艺腔室3之间传输晶圆；多个预备腔室6与第一工艺腔室2和/或第二工艺腔室3的类型相同。
如图1及图5所示，传输腔室1具体可以采用八边形的腔体结构，其中两相邻的侧边可以设置有前端模块7，去气腔室4、预清洗腔室5、第一工艺腔室2、第二工艺腔室3及预备腔室6依次环绕于传输腔室1的其它六个侧边，其中预备腔室6可以设置为两个。去气腔室4可以用于对晶圆执行去汽工艺，即对晶圆表面的水汽进行去除；然后再由传输腔室1内的机械手11将晶圆传输至预清洗腔室5内，预清洗腔室5用于对晶圆表面进行预清洗工艺，以将晶圆表面的有机物及杂质进行清洗；此时传输腔室1内的机械手11将晶圆传输至第一工艺腔室2，以在晶圆表面形成介质薄膜101，然后再由机械手11将晶圆传输至第二工艺腔室3，以在晶圆表面的介质薄膜101上形成金属薄膜102以形成的叠层薄膜结构100。预备腔室6可以为两个，其中一个预备腔室6可以设置为与第一工艺腔室2的类型相同，另一个预备腔室6可以设置为与第二工艺腔室3的类型相同，以提高本申请实施例制备叠层薄 膜结构100的效率，从而进一步提高产能。采用上述设计，使得本申请实施例的晶圆传输过程简便快捷，从而大幅提高工作效率及产能。
需要说明的是，本申请实施例并不限定预备腔室6的具体类型及数量，例如预备腔室6还可以设置为去气腔室4或预清洗腔室5。因此本申请实施例并不以此为限，本领域技术人员可以根据实际情况自行调整设置。
基于同一发明构思，本申请实施例提供了一种形成叠层薄膜结构的方法，用于在晶圆的表面形成叠层薄膜结构，该形成叠层薄膜结构的方法流程示意图如图4所示，包括以下步骤：
S1：第一溅射步骤，将晶圆可以通过传输腔室传输至第一工艺腔室内的第一基座上；向第一工艺腔室内通入第一惰性气体和第一工艺气体的混合气体，对介质靶材施加第一溅射功率，使第一惰性气体形成等离子体，该等离子体使第一工艺气体产生自由基，该自由基与介质靶材发生反应，该等离子体轰击介质靶材，以在晶圆上沉积形成介质薄膜。
S2：第二溅射步骤，将晶圆由第一工艺腔室内可以通过传输腔室传输至第二工艺腔室内的第二基座上；向第二工艺腔室内通入第二惰性气体，对金属靶材施加第二溅射功率，使第二惰性气体形成等离子体，该等离子体轰击金属靶材，以在晶圆上形成金属薄膜。
重复执行第一溅射步骤及第二溅射步骤，以在晶圆的表面沉积交替叠层的介质薄膜和金属薄膜，形成叠层薄膜结构。本申请实施例并不限定介质薄膜101和金属薄膜102的沉积先后顺序，可以先在晶圆表面沉积形成介质薄膜101，后在晶圆表面的介质薄膜101表面形成金属薄膜102，或者也可以先在晶圆表面沉积形成金属薄膜102，后在晶圆表面的金属薄膜102沉积形成介质薄膜101。
可选地，在晶圆表面形成叠层薄膜结构100时，通过第一溅射步骤所沉积的介质薄膜101作为叠层薄膜结构100的最后一层薄膜。
结合参照如图1至图5所示，半导体工艺设备可以包括有下位机，下位机可以控制传输腔室1内的机械手11运动，传输腔室1内的机械手11将晶圆传输至第一工艺腔室2，第一基座21用于承载晶圆。向第一腔体20内通入氩气和氧气的混合气体，即向第一工艺腔室2内通入第一惰性气体和第一工艺气体的混合气体，第一溅射电源向介质靶材22施加第一溅射功率，使第一腔体20内的第一惰性气体形成等离子体，产生的等离子体将第一腔体20中的氧气活化以产生氧自由基，氧自由基与介质靶材22表面的硅反应生成二氧化硅，轰击介质靶材22表面形成的二氧化硅，轰击下来的二氧化硅沉积在晶圆上生成二氧化硅薄膜，以在晶圆上形成介质薄膜101，即执行第一溅射步骤。然后再由机械手11将晶圆传输至第二工艺腔室3，第二基座31用于承载晶圆。向第二腔体30内通入氩气，即向第二工艺腔室3内通入第二惰性气体，第二溅射电源对金属靶材32施加第二溅射功率，可击穿氩气而产生等离子体，等离子体中带正电的氩离子被吸引至负电压的金属靶材32，当氩离子的能量足够高时，会使金属靶材32上的粒子或离子逸出并沉积在晶圆上，以在晶圆上形成金属薄膜102，即执行第二溅射步骤。根据实际需求交替执行第一溅射步骤及第二溅射步骤，以得到不同对数的叠层薄膜结构100，例如叠层薄膜结构100的对数可为两对、四对、甚至一百对，具体可以参照如图5所示，叠层薄膜结构100的总体厚度可以设置为15nm～100000nm，优选的1000nm～10000nm，但是本申请实施例并不以此为限。进一步的，叠层薄膜结构100最上层可以采用第一工艺腔室2在金属薄膜102的表面形成有介质薄膜101，以作为保护薄膜，即在晶圆表面形成叠层薄膜结构100时，通过第一溅射步骤所沉积的介质薄膜101作为叠层薄膜结构100的最后一层薄膜。
采用上述设计，由于采用物理气相沉积工艺制备叠层薄膜结构100，使得叠层薄膜结构100的温度较低，从而避免叠层薄膜结构100内产生较大的 热应力，进而提高产品良率。此外，由于采用传输腔室1在第一工艺腔室2及第二工艺腔室3内传输晶圆，可以避免晶圆与外界环境接触造成的污染，从而进一步提高产品良率。
于本申请的一实施例中，如图1至图5所示，第二溅射步骤还包括：对第二基座31施加偏压功率，吸引金属靶材32上逸出的离子轰击晶圆，以调整金属薄膜102的应力。具体来说，在第二基座31的下方连接有射频电源，射频电源能在第二基座31上形成负电压，以吸引金属靶材32逸出的离子或等离子体中的氩离子轰击晶圆上的金属薄膜102，可以起到调整薄膜应力的作用，使得薄膜应力较为均匀，从而提高薄膜沉积良率。
于本申请的一实施例中，如图1至图5所示，在执行第一次第一溅射步骤之前还包括去气步骤：将晶圆传输至去气腔室的第三基座上，将晶圆加热至100℃～500℃，并维持10秒～200秒，以去除晶圆上的水汽。具体来说，下位机可以控制传输腔室1内的机械手11运动，机械手11能将前端模块7内的晶圆传输至去气腔室4内，去气腔室4内的第三基座可以用于承载晶圆，第三基座可以将晶圆加热至100℃～500℃之间，并且维持10秒～200秒的时间，以对晶圆表面的水汽进行去除。当晶圆完成去气步骤之后，再将该完成去气步骤的晶圆传输至第一工艺腔室2内，以用于执行第一溅射步骤。需要说明的是，本申请实施例并不限定去气步骤的具体工艺参数，本领域技术人员可以根据实际情况自行调整设置。
于本申请的一实施例中，如图1至图5所示，在去气步骤之后，且在执行第一次第一溅射步骤之前还包括预清洗步骤：将晶圆由去气腔室传输至预清洗腔室的第四基座上，向预清洗腔室中通入第三惰性气体，并对第四基座施加射频功率，吸引第三惰性气体产生的等离子体轰击晶圆的表面，以去除晶圆的表面的杂质。具体来说，当完成去气步骤之后，下位机可以控制传输腔室1内的机械手11运动，机械手11能将去气腔室4内的晶圆传输至预清 洗腔室5内，预清洗腔室5内的第四基座可以用于承载晶圆，预清洗腔室5内可以通入第三惰性气体，该第三惰性气体可以采用氩气，但是本申请实施例并不以此为限。第四基座可以对晶圆施加射频功率，以用于吸引第三惰性气体产生的等离子体，以使等离子体能够轰击晶圆的表面，即预清洗腔室5能对晶圆表面执行预清洗步骤，以将晶圆表面的有机物及杂质进行清洗。当晶圆完成预清洗步骤之后，再将该完成预清洗步骤的晶圆传输至第一工艺腔室2内，以用于执行第一溅射步骤。采用上述设计，由于晶圆表面较为清洁，能有效避免有机物及杂质造成薄膜沉积缺陷，从而大幅提高晶圆薄膜沉积的良率。需要说明的是，本申请实施例并不限定第三惰性气体的具体类型，本领域技术人员可以根据实际情况自行调整设置。
于本申请的一实施例中，如图1至图5所示，在第一溅射步骤中：第一惰性气体为氩气，第一工艺气体为氧气，氧气在混合气体中的占比为30％以上，介质靶材的材料为硅，介质薄膜为二氧化硅薄膜。
可选地，第一溅射功率为脉冲直流功率，脉冲直流功率为0.01kW～10kW；第一工艺腔室内的工艺压力为0.01mTorr～100mTorr；单层介质薄膜的厚度为3nm～100nm。
如图1至图5所示，在第一溅射步骤中，第一工艺腔室2的进气口通入的混合气体为氩气和氧气，并且氧气在混合气体中的占比为30％以上，即第一惰性气体为氩气，第一工艺气体为氧气，氧气在混合气体中的占比为30％以上。第一溅射电源为脉冲直流电源，并且第一溅射功率具体数值为0.01kW～10kW，以用于向介质靶材22施加偏压，该介质靶材22的材质例如为硅，以使得介质薄膜101为二气化硅薄膜。真空系统可以将第一工艺腔室2的工艺压力控制在0.01mTorr～100mTorr之间，具体执行溅射的时间并不进行限定，只要确保单层介质薄膜101的厚度达到3nm～100nm即可。采用上述设计，使得本申请实施例制备的叠层薄膜结构100不仅能适用于3D  NAND闪存领域，而且还能应用于其它领域，从而大幅提高本申请实施例适用性及适用范围。进一步的，可以将第一溅射电源的第一溅射功率设置为1kW～5kW，以及通过真空系统将第一工艺腔室2内的工艺压力调整为5mTorr～10mTorr，从而实现将介质薄膜101控制在5nm～10nm之间，采用此工艺环境能够减少介质靶材22的表面产生电荷的积累，从而防止在介质靶材22的表面发生电弧打火(arc)。采用上述设计，不仅可以调节沉积速率，而且还能精确控制薄膜沉积厚度，从而在提高工作效率的同时提高介质薄膜的良率。
于本申请的一实施例中，如图1至图5所示，在第二溅射步骤中，第二惰性气体为氩气，介质靶材的材料为钨，金属薄膜为钨薄膜。
可选地，第二溅射功率为直流功率，直流功率为0.01kW～20kW；偏压功率为射频功率，射频功率为0.01kW～2kW；第二工艺腔室内的工艺压力为0.01mTorr～100mTorr；单层金属薄膜的厚度为3nm～1000nm。
如图1至图5所示，在第二溅射步骤中，向第二工艺腔室3的进气口通入氩气，即第二惰性气体为氩气。第二溅射电源为直流电源，并且第二溅射功率的具体数值为0.01kW～20kW，以用于向金属靶材32施加偏压，该金属靶材32的材质例如为钨，以使得金属薄膜为钨薄膜。由于金属靶材32本身的特点，需要将第二溅射电源的第二溅射功率设置的相对较高，从而确保沉积速率，例如第二溅射功率可以设置为0.01kW～20kW之间，但是本申请实施例并不以此为限。第二基座31可以对晶圆加载射频功率，即偏压功率为射频功率，该射频功率为0.01kW～2kW，但是本申请实施例并不以此为限。真空系统可以将第二工艺腔室3的工艺压力控制在0.01mTorr～100mTorr，但是执行溅射的时间并不进行限定，只要确保单层金属薄膜102的厚度达到3nm～1000nm即可，由于需要在金属薄膜102刻蚀图形，因此金属薄膜102厚度相较于介质薄膜101较厚。采用上述设计，使得本申请实施例制备的叠 层薄膜结构100不仅能适用于3D NAND闪存领域，而且还能应用于其它领域，从而大幅提高本申请实施例适用性及适用范围。进一步的，可以将第二溅射功率设置为1kW～5kW，第二基座31对晶圆加载的射频功率为1kW～2kW，再通过真空系统将第二工艺腔室3内的工艺压力调整为5mTorr～10mTorr，从而实现将介质薄膜101控制在10nm～100nm。采用上述设计，不仅可以调节沉积速率，而且还能精确控制薄膜沉积厚度，从而在提高工作效率的同时提高介质薄膜101的良率。
应用本申请实施例，至少能够实现如下有益效果：
本申请实施例通过传输腔室在第一工艺腔室及第二工艺腔室之间传输晶圆，并且通过第一工艺腔室在晶圆上形成介质薄膜，以及通过第二工艺腔室在晶圆上形成金属薄膜，从而实现在晶圆表面形成一对或多对的叠层薄膜结构。由于两个工艺腔室均采用物理气相沉积工艺沉积薄膜，并且均与传输腔室连接，使得本申请实施例的半导体工艺设备集成难度低，并且由于工艺流程简单，从而大幅提升产能的同时，还能避免晶圆受到外界环境的污染以确保产品的良率，并且还便于商业化量产。另外，由于采用物理气相沉积工艺沉积薄膜，使得介质薄膜及金属薄膜在沉积过程中温度可以控制在室温附近，防止叠层薄膜结构内部产生较大的热应力，从而进一步提高产品的良率。
可以理解的是，以上实施方式仅仅是为了说明本发明的原理而采用的示例性实施方式，然而本发明并不局限于此。对于本领域内的普通技术人员而言，在不脱离本发明的精神和实质的情况下，可以做出各种变型和改进，这些变型和改进也视为本发明的保护范围。
本技术领域技术人员可以理解，本申请中已经讨论过的各种操作、方法、流程中的步骤、措施、方案可以被交替、更改、组合或删除。进一步地，具有本申请中已经讨论过的各种操作、方法、流程中的其他步骤、措施、方案也可以被交替、更改、重排、分解、组合或删除。进一步地，现有技术中的 具有与本申请中公开的各种操作、方法、流程中的步骤、措施、方案也可以被交替、更改、重排、分解、组合或删除。
在本申请的描述中，需要理解的是，术语“中心”、“上”、“下”、“前”、“后”、“左”、“右”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本发明和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本发明的限制。
术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本发明的描述中，除非另有说明，“多个”的含义是两个或两个以上。
在本申请的描述中，需要说明的是，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解，例如，可以是固定连接，也可以是可拆卸连接，或一体地连接；可以是直接相连，也可以通过中间媒介间接相连，可以是两个元件内部的连通。对于本领域的普通技术人员而言，可以具体情况理解上述术语在本发明中的具体含义。
在本说明书的描述中，具体特征、结构、材料或者特点可以在任何的一个或多个实施例或示例中以合适的方式结合。
应该理解的是，虽然附图的流程图中的各个步骤按照箭头的指示依次显示，但是这些步骤并不是必然按照箭头指示的顺序依次执行。除非本文中有明确的说明，这些步骤的执行并没有严格的顺序限制，其可以以其他的顺序执行。而且，附图的流程图中的至少一部分步骤可以包括多个子步骤或者多个阶段，这些子步骤或者阶段并不必然是在同一时刻执行完成，而是可以在不同的时刻执行，其执行顺序也不必然是依次进行，而是可以与其他步骤或者其他步骤的子步骤或者阶段的至少一部分轮流或者交替地执行。
以上所述仅是本申请的部分实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本申请原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本申请的保护范围。

Claims (10)

  1. 一种形成叠层薄膜结构的方法，用于在晶圆的表面形成叠层薄膜结构，其特征在于，所述方法包括：
    第一溅射步骤，将晶圆传输至第一工艺腔室内的第一基座上；向所述第一工艺腔室内通入第一惰性气体和第一工艺气体的混合气体，对介质靶材施加第一溅射功率，使所述第一惰性气体形成等离子体，该等离子体使所述第一工艺气体产生自由基，该自由基与所述介质靶材发生反应，该等离子体轰击所述介质靶材，以在所述晶圆上沉积形成介质薄膜；
    第二溅射步骤，将晶圆传输至第二工艺腔室内的第二基座上；向所述第二工艺腔室内通入第二惰性气体，对金属靶材施加第二溅射功率，使所述第二惰性气体形成等离子体，该等离子体轰击所述金属靶材，以在所述晶圆上形成金属薄膜；
    重复执行所述第一溅射步骤及所述第二溅射步骤，以在所述晶圆的表面沉积交替叠层的所述介质薄膜和所述金属薄膜，形成所述叠层薄膜结构。
  2. 如权利要求1所述的形成叠层薄膜结构的方法，其特征在于，所述第二溅射步骤还包括：对所述第二基座施加偏压功率，吸引所述金属靶材上逸出的离子轰击所述晶圆，以调整所述金属薄膜的应力。
  3. 如权利要求1所述的形成叠层薄膜结构的方法，其特征在于，在执行第一次所述第一溅射步骤之前还包括去气步骤：将所述晶圆传输至去气腔室的第三基座上，将所述晶圆加热至100℃～500℃，并维持10秒～200秒，以去除所述晶圆上的水汽。
  4. 如权利要求3所述的形成叠层薄膜结构的方法，其特征在于，在所述去气步骤之后，且在执行第一次所述第一溅射步骤之前还包括预清洗步骤： 将所述晶圆由所述去气腔室传输至预清洗腔室的第四基座上，向所述预清洗腔室中通入第三惰性气体，并对所述第四基座施加射频功率，吸引所述第三惰性气体产生的等离子体轰击所述晶圆的表面，以去除所述晶圆的表面的杂质。
  5. 如权利要求1所述的形成叠层薄膜结构的方法，其特征在于，在所述晶圆表面形成所述叠层薄膜结构时，通过所述第一溅射步骤所沉积的所述介质薄膜作为所述叠层薄膜结构的最后一层薄膜。
  6. 如权利要求1所述的形成叠层薄膜结构的方法，其特征在于，在所述第一溅射步骤中：所述第一惰性气体为氩气，所述第一工艺气体为氧气，所述氧气在所述混合气体中的占比为30％以上，所述介质靶材的材料为硅，所述介质薄膜为二氧化硅薄膜。
  7. 如权利要求1所述的形成叠层薄膜结构的方法，其特征在于，所述第一溅射功率为脉冲直流功率，所述脉冲直流功率为0.01kW～10kW；所述第一工艺腔室内的工艺压力为0.01mTorr～100mTorr；单层所述介质薄膜的厚度为3nm～100nm。
  8. 如权利要求1所述的形成叠层薄膜结构的方法，其特征在于，在所述第二溅射步骤中，所述第二惰性气体为氩气，所述金属靶材的材料为钨，所述金属薄膜为钨薄膜。
  9. 如权利要求2所述的形成叠层薄膜结构的方法，其特征在于，所述第二溅射功率为直流功率，所述直流功率为0.01kW～20kW；所述偏压功率为射频功率，所述射频功率为0.01kW～2kW；所述第二工艺腔室内的工艺压力为0.01mTorr～100mTorr；单层所述金属薄膜的厚度为3nm～1000nm。
  10. 一种半导体工艺设备，用于在晶圆的表面形成叠层薄膜结构，其特征在于，包括：传输腔室、第一工艺腔室、第二工艺腔室；
    所述第一工艺腔室及所述第二工艺腔室与所述传输腔室连接，所述传输腔室用于向所述第一工艺腔室或者所述第二工艺腔室内传输所述晶圆；
    所述第一工艺腔室用于在所述晶圆表面及金属薄膜表面形成介质薄膜，所述第一工艺腔室包括第一基座、第一溅射电源及第一磁控管机构，所述第一基座用于承载所述晶圆，所述第一溅射电源用于向介质靶材提供第一溅射功率，以使第一工艺腔室内的第一惰性气体及第一工艺气体形成等离子体，所述第一磁控管机构用于引导所述第一工艺腔室内的等离子体轰击所述介质靶材；
    所述第二工艺腔室用于在所述介质薄膜上形成所述金属薄膜，所述第二工艺腔室包括第二基座、第二溅射电源及第二磁控管机构，所述第二基座用于承载所述晶圆，所述第二溅射电源用于向金属靶材提供第二溅射功率，以使第二工艺腔室内的第二惰性气体形成等离子体，所述第二磁控管机构用于引导所述第二工艺腔室内的等离子体轰击所述金属靶材。
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