WO2023206802A1 - 半导体结构及其形成方法 - Google Patents

半导体结构及其形成方法 Download PDF

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Publication number
WO2023206802A1
WO2023206802A1 PCT/CN2022/102861 CN2022102861W WO2023206802A1 WO 2023206802 A1 WO2023206802 A1 WO 2023206802A1 CN 2022102861 W CN2022102861 W CN 2022102861W WO 2023206802 A1 WO2023206802 A1 WO 2023206802A1
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Prior art keywords
substrate
top surface
bit
lines
word lines
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PCT/CN2022/102861
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English (en)
French (fr)
Inventor
刘佑铭
肖德元
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长鑫存储技术有限公司
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Priority to US17/934,189 priority Critical patent/US20230020883A1/en
Publication of WO2023206802A1 publication Critical patent/WO2023206802A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices

Definitions

  • the present disclosure relates to the field of semiconductor manufacturing technology, and in particular, to a semiconductor structure and a method of forming the same.
  • DRAM Dynamic Random Access Memory
  • each storage unit usually includes a transistor and a capacitor.
  • the gate of the transistor is electrically connected to the word line
  • the source is electrically connected to the bit line
  • the drain is electrically connected to the capacitor.
  • the word line voltage on the word line can control the turning on and off of the transistor, so that the memory can be read through the bit line. Data information in the capacitor, or writing data information into the capacitor.
  • multiple word lines are located at the same level, which results in a strong capacitive coupling effect between adjacent word lines, thus affecting the electrical performance of the semiconductor structure.
  • the semiconductor structure and its formation method provided by some embodiments of the present disclosure are used to solve the problem of strong capacitive coupling effect between adjacent word lines, so as to improve the electrical performance of the semiconductor structure.
  • the present disclosure provides a semiconductor structure including:
  • a plurality of word lines are located on the top surface of the substrate. Each of the word lines extends in a direction perpendicular to the top surface of the substrate. The plurality of word lines are spaced apart along the first direction. Along the first direction, any two adjacent word lines are at least partially staggered, and the first direction is a direction parallel to the top surface of the substrate.
  • any two adjacent word lines are completely staggered along the first direction.
  • the projections of any two adjacent word lines partially overlap.
  • a plurality of the word lines are ordered sequentially, and any two adjacent odd-numbered word lines are in a second direction and perpendicular to the substrate.
  • the projections on the plane formed by the directions of the top surface overlap, and the plane formed by any two adjacent even-numbered word lines in the second direction and the direction perpendicular to the top surface of the substrate.
  • the projections on the substrate overlap, the second direction is a direction parallel to the top surface of the substrate, and the first direction is orthogonal to the second direction.
  • a plurality of the word lines are ordered sequentially, and any two adjacent 3n-bit word lines are in a second direction and perpendicular to the substrate.
  • the projections on the plane overlap, and the projections of any two adjacent 3n+2-bit word lines on the plane formed by the second direction and the direction perpendicular to the top surface of the substrate overlap, Wherein, n is an integer, the second direction is a direction parallel to the top surface of the substrate, and the first direction is orthogonal to the second direction.
  • it also includes:
  • a plurality of semiconductor layers are located on the top surface of the substrate, each of the semiconductor layers includes a plurality of active pillars spaced apart along the first direction, and the plurality of semiconductor layers are along a direction perpendicular to the The direction of the top surface of the substrate is spaced apart, and each of the active pillars includes a channel region, and a source region and a drain region distributed on opposite sides of the channel region along the second direction, each strip
  • the word lines continuously cover a plurality of the channel areas spaced apart in a direction perpendicular to the top surface of the substrate, the second direction is a direction parallel to the top surface of the substrate, and The first direction is orthogonal to the second direction;
  • a plurality of bit lines are located on the top surface of the substrate, each of the bit lines extends along the first direction, and the plurality of bit lines are spaced apart in a direction perpendicular to the top surface of the substrate. , and one of the bit lines is electrically connected to all of the source regions in one of the semiconductor layers;
  • a plurality of bit line leads are located on the top surface of the substrate, each of the bit line leads extends in a direction perpendicular to the top surface of the substrate, and the plurality of bit line leads are respectively connected to the plurality of bit line leads.
  • the bit lines are electrically connected.
  • each of the bit lines includes a first end and a second end opposite to the first end along the first direction, and any two adjacent bit lines , the first end of one of the bit lines closer to the substrate protrudes from the first end of the other bit line along the first direction;
  • the plurality of bit line leads are electrically connected to the first ends of the plurality of bit lines respectively.
  • each of the bit lines includes a first end and a second end opposite to the first end along the first direction;
  • bit line lead electrically connected to one of the bit lines is located on the side of one of the bit lines.
  • the first end portion is electrically connected to the other bit line, and the bit line lead is located at the second end portion of the other bit line.
  • a plurality of the bit lines are arranged sequentially in a direction perpendicular to the top surface of the substrate, and the bit line leads electrically connected to the bit lines at odd-numbered bits are located at odd-numbered bits.
  • the first end of the bit line and the bit line lead electrically connected to the bit line of the even-numbered bit are located at the second end of the bit line of the even-numbered bit.
  • each of the bit lines includes a first end surface and a second end surface opposite to the first end surface along the first direction;
  • the first end surfaces of all the bit lines spaced apart in a direction perpendicular to the top surface of the substrate are flush, and the second end surfaces of all the bit lines are flush.
  • a plurality of the bit lines are arranged sequentially in a direction perpendicular to the top surface of the substrate. Among any two adjacent odd-numbered bit lines, the one closer to the substrate is The first end of one bit line protrudes from the first end of the other bit line along the first direction;
  • the second end of the bit line closer to the substrate protrudes from the other bit line along the first direction. the second end.
  • each of the bit lines includes a third end and a fourth end opposite to the third end along the second direction.
  • the third end of one of the bit lines closer to the substrate protrudes from the third end of the other bit line along the second direction;
  • the plurality of bit line leads are electrically connected to the third end portions of the plurality of bit lines respectively.
  • the widths of any two adjacent word lines along the second direction are equal.
  • each of the word lines includes a fifth end and a sixth end opposite to the fifth end along the second direction; the semiconductor structure further includes:
  • a plurality of word line leads are located on the top surface of the substrate. Each of the word line leads extends in a direction perpendicular to the top surface of the substrate. The plurality of word line leads are respectively connected to a plurality of the word line leads. Word lines are electrically connected;
  • the word line lead electrically connected to one of the word lines is located at the fifth end of one of the word lines and connected to the other word line.
  • the word line lead to which the word line is electrically connected is located at the sixth end of the other word line.
  • the present disclosure also provides a method for forming a semiconductor structure as described above, including the following steps:
  • a plurality of word lines are formed on the top surface of the substrate, each of the word lines extends in a direction perpendicular to the top surface of the substrate, and the plurality of word lines extend along a direction parallel to the top surface of the substrate.
  • the word lines are arranged at intervals in the direction of the surface, and any two adjacent word lines are at least partially staggered in a direction parallel to the top surface of the substrate.
  • each word line extends in a direction perpendicular to the top surface of the substrate, and in a first direction parallel to the top surface of the substrate, any phase
  • the two adjacent word lines are at least partially staggered, which can reduce the facing area between the two adjacent word lines, thereby reducing the capacitive coupling effect between the two adjacent word lines and achieving electrical control of the semiconductor structure.
  • the present disclosure reduces the capacitive coupling effect by reducing the facing area between two adjacent word lines, and the distance between the two adjacent word lines in a direction parallel to the top surface of the substrate does not need to be increase, thereby helping to control the size of the semiconductor structure.
  • FIG. 1 is a first top structural schematic diagram of a semiconductor structure in a specific embodiment of the present disclosure
  • FIG. 2 is a schematic diagram of a first three-dimensional structure of a semiconductor structure in a specific embodiment of the present disclosure
  • Figure 3 is a second top structural schematic diagram of a semiconductor structure in a specific embodiment of the present disclosure.
  • FIG. 4 is a schematic diagram of a second three-dimensional structure of a semiconductor structure in a specific embodiment of the present disclosure
  • Figure 5 is a third top structural schematic diagram of a semiconductor structure in a specific embodiment of the present disclosure.
  • FIG. 6 is a schematic diagram of a third three-dimensional structure of a semiconductor structure in a specific embodiment of the present disclosure.
  • FIG. 7 is a flow chart of a method for forming a semiconductor structure in an embodiment of the present disclosure.
  • Figure 1 is a first top view structural schematic diagram of the semiconductor structure in the specific embodiment of the present disclosure.
  • Figure 2 is a first three-dimensional structural schematic diagram of the semiconductor structure in the specific embodiment of the present disclosure.
  • Figure 2 is a first three-dimensional structural schematic diagram of a semiconductor structure in a specific embodiment of the present disclosure.
  • the semiconductor structure described in this specific embodiment may be, but is not limited to, DRAM.
  • the semiconductor structure includes:
  • a plurality of word lines 15 are located on the top surface of the substrate. Each of the word lines 15 extends along a direction D3 perpendicular to the top surface of the substrate. The plurality of word lines 15 extend along a first direction D1 Arranged at intervals, any two adjacent word lines 15 are at least partially staggered along the first direction D1, which is a direction parallel to the top surface of the substrate.
  • the substrate may be, but is not limited to, a silicon substrate.
  • the substrate is a silicon substrate as an example for description.
  • the substrate may also be a semiconductor substrate such as gallium nitride, gallium arsenide, gallium carbide, silicon carbide, or SOI.
  • the substrate is used to support device structures thereon.
  • the word line 15 can be made of conductive materials such as metallic tungsten or TiN.
  • each word line 15 extends in a direction D3 perpendicular to the top surface of the substrate, forming a vertical word line structure.
  • a plurality of word lines 15 are arranged at intervals along the first direction D1.
  • the adjacent first word line 151 and the second word line 152 are at least partially offset.
  • the projection of the first word line 151 on the plane formed by the second direction D2 and the direction D3 perpendicular to the top surface of the substrate is the same as the projection of the second word line 152 on the second direction D2 and the direction D3 perpendicular to the top surface of the substrate.
  • the projections on the plane formed by the direction D3 perpendicular to the top surface of the substrate are at least partially staggered, so that the first word line 151 and the second word line 152 face each other along the first direction D1
  • the area is reduced, thereby reducing the capacitive coupling effect between the first word line 151 and the second word line 152 .
  • the first direction D1 and the second direction D2 are both directions parallel to the top surface of the substrate, and the first direction D1 is orthogonal to the second direction D2.
  • this specific embodiment reduces the capacitive coupling effect between word lines by staggering adjacent word lines, so there is no need to increase the length of the first word line 151 and the second word line 152 along the first word line.
  • the spacing in one direction D1 eliminates the need to increase the size of the semiconductor structure and helps the semiconductor structure further improve the integration level of the semiconductor structure.
  • any two adjacent word lines 15 are completely staggered.
  • any two adjacent word lines 15 being completely staggered means that any two adjacent word lines 15 are arranged at intervals along the first direction D1.
  • the projections of the two word lines 15 on the plane formed by the second direction D2 and the direction D3 perpendicular to the top surface of the substrate are separated from each other (ie do not overlap with each other).
  • the widths of any two adjacent word lines 15 are equal to simplify the formation process of the word lines in the semiconductor structure, and also enable multiple word lines to be formed.
  • the resistance of 15 is equal, simplifying the word line driving operation of the semiconductor structure.
  • any two adjacent word lines 15 are in the second direction D2 and perpendicular to the top surface of the substrate.
  • the gap width between the projections on the plane formed by the directions D3 together is 1/4 to 1/2 of the width of the word line 15 .
  • the adjacent first word line 151 and the second word line 152 are completely staggered, and the first word line 151 is in the second direction D2 and perpendicular to the top surface of the substrate.
  • the gap width between the projection of the second word line 152 on the plane jointly formed by the direction D3 and the projection of the second word line 152 on the plane jointly formed by the second direction D2 and the direction D3 perpendicular to the top surface of the substrate is 1/4 to 1/2 of the width of the first word line 151 along the second direction D2, so that when the adjacent first word line 151 and the second word line 152 are eliminated, At the same time, the capacitive coupling effect will not lead to an increase in the size of the semiconductor structure.
  • any two adjacent word lines 15 are completely staggered in a direction parallel to the top surface of the substrate.
  • any two adjacent word lines 15 in a direction parallel to the top surface of the substrate, can also be only partially staggered, thereby helping to reduce the noise between adjacent word lines.
  • the capacitive coupling effect between the two elements further reduces the size of the semiconductor structure.
  • the projections of any two adjacent word lines 15 partially overlap.
  • the first word line 151 is in the first direction D1 and is perpendicular to the first word line 151 and the second word line 152.
  • the projection on the plane formed by the direction D3 of the top surface of the substrate partially overlaps with the second word line 152 on the plane formed by the first direction D1 and the direction D3 perpendicular to the top surface of the substrate, This helps to reduce the distance between the first word line 151 and the second word line 152 in the first direction D1 to further improve the storage density of the semiconductor structure.
  • a plurality of the word lines 15 are arranged in sequence in a direction parallel to the top surface of the substrate, and any two adjacent odd-numbered word lines 15 are arranged along the direction parallel to the top surface of the substrate.
  • Direction D2 is orthogonal.
  • a plurality of the word lines are ordered in sequence, that is, along the first direction D1, the odd-numbered words Lines 15 (for example, the first word line 151) and the word lines 15 (for example, the second word line 152) of even-numbered bits are alternately arranged, and any adjacent word lines 15 of odd-numbered bits and The even-numbered word lines 15 are at least partially staggered along the first direction D1.
  • the projection overlap of any two adjacent odd-numbered word lines 15 on the plane formed by the second direction D2 and the direction D3 perpendicular to the top surface of the substrate means that any adjacent two The word lines 15 of the odd-numbered bits are aligned in the first direction D1.
  • the projection overlap of any two adjacent even-numbered word lines 15 on the plane formed by the second direction D2 and the direction D3 perpendicular to the top surface of the substrate means that any adjacent The two even-numbered word lines 15 are aligned in the first direction D1.
  • the projections of any two adjacent odd-numbered word lines 15 on the plane formed by the second direction D2 and the direction D3 perpendicular to the top surface of the substrate overlap.
  • the projection overlap of any two adjacent even-numbered word lines 15 on the plane formed by the second direction D2 and the direction D3 perpendicular to the top surface of the substrate can reduce the number of masks. quantity, thereby simplifying the manufacturing process of the semiconductor structure and reducing the manufacturing cost of the semiconductor structure.
  • a plurality of the word lines 15 are arranged in sequence along the first direction D1, and any two adjacent 3nth bits of the word lines 15 are arranged in sequence.
  • the projection of the word line 15 on the plane formed by the second direction D2 and the direction D3 perpendicular to the top surface of the substrate overlaps, and any two adjacent word lines 15 of the 3n+1th bit are in the The projections on the plane formed by the second direction D2 and the direction D3 perpendicular to the top surface of the substrate overlap, and any two adjacent 3n+2-th word lines are in the second direction D2 and
  • the semiconductor structure further includes:
  • a plurality of semiconductor layers are located on the top surface of the substrate, each of the semiconductor layers includes a plurality of active pillars 131 spaced apart along the first direction D1, and the plurality of semiconductor layers are along a vertical axis perpendicular to The top surface of the substrate is arranged at intervals in the direction D3.
  • Each of the active pillars includes a channel region, and source regions and drain electrodes distributed on opposite sides of the channel region along the second direction D2. area, each word line 15 continuously covers a plurality of channel areas arranged at intervals in a direction perpendicular to the top surface of the substrate, and the second direction D2 is parallel to the substrate.
  • the direction of the top surface, and the first direction D1 is orthogonal to the second direction D2;
  • a plurality of bit lines 17 are located on the top surface of the substrate. Each bit line 17 extends along the first direction D1. The plurality of bit lines 17 extend along a direction perpendicular to the top surface of the substrate. The bit lines 17 are arranged at intervals in the direction D3, and one bit line 17 is electrically connected to all the source regions in one semiconductor layer;
  • a plurality of bit line leads 18 are located on the top surface of the substrate. Each of the bit line leads 18 extends in a direction perpendicular to the top surface D3 of the substrate, and the plurality of bit line leads 18 are respectively It is electrically connected to a plurality of bit lines 17 .
  • each of the bit lines 17 includes a first end 171 and a second end 172 opposite to the first end 171 along the first direction D1. Any two adjacent ones Among the bit lines 17 , the first end 171 of the bit line 17 closer to the substrate protrudes from the first end 171 of the other bit line 17 along the first direction D1 . end 171;
  • the plurality of bit line leads 18 are electrically connected to the first end portions 171 of the plurality of bit lines 17 respectively.
  • the material of the semiconductor layer may be but is not limited to silicon.
  • the top surface of the substrate includes a transistor region 11 and a bit line region 10 and a capacitor region 12 distributed on opposite sides of the transistor region 11 along the second direction D2.
  • a plurality of the semiconductor layers are spaced apart along the direction D3 perpendicular to the top surface of the substrate, and each semiconductor layer includes a plurality of semiconductor pillars 13 spaced apart along the first direction D1, so
  • the semiconductor pillar 13 includes an active pillar 131 located in the transistor area 11 and a conductive pillar 132 located in the capacitor area 12 .
  • the active pillar 131 includes a channel region, and a source region and a drain region located on opposite sides of the channel region along the second direction D2.
  • the drain region is electrically connected to the conductive pillar 132 , and the drain region and the conductive pillar 132 have the same doping ions to further reduce the gap between the drain region and the conductive pillar 132 . contact resistance.
  • the capacitive region 12 also includes a plurality of capacitors 14 distributed around the conductive pillars 132 .
  • the capacitor 14 includes a lower electrode layer covering the surface of the conductive pillar 132 , a dielectric layer covering the surface of the lower electrode layer, and an upper electrode layer covering the surface of the dielectric layer.
  • a plurality of bit lines 17 are located in the bit line area.
  • a plurality of bit lines 17 are arranged at intervals along the direction D3 perpendicular to the top surface of the substrate, and one bit line 17 is connected to one of the bit lines 17 . All said source regions in the semiconductor layer are electrically
  • Each of the bit lines 17 extends along the first direction D1.
  • the first end 171 of the bit line 17 that is closer to the substrate The first end portion 171 of another bit line 17 protrudes along the first direction D1, so that the first end portions 171 of the plurality of bit lines 17 form a step-like structure.
  • the plurality of bit line leads 18 are electrically connected to the first ends 171 of the plurality of bit lines 17 respectively, so that the signals of all the bit lines 17 can be led out on the same side, thereby helping to reduce the
  • the occupied area of the bit line leads 18 improves the space utilization inside the semiconductor structure.
  • FIG. 3 is a second schematic structural diagram of a top view of a semiconductor structure in a specific embodiment of the present disclosure
  • FIG. 4 is a second schematic three-dimensional structural diagram of a semiconductor structure in a specific embodiment of the present disclosure.
  • each bit line 17 includes a first end 171 and a second end 171 opposite to the first end 171 along the first direction D1 . end 172;
  • bit line leads 18 is electrically connected to one of the bit lines 17
  • the first end 171 of 17 is electrically connected to the other bit line 17
  • the bit line lead 18 is located at the second end 172 of the other bit line 17 .
  • bit lines 17 are arranged sequentially along the direction D3 perpendicular to the top surface of the substrate, and the bit line leads 18 electrically connected to the odd-numbered bit lines 17 are all
  • the first end 171 of the bit line 17 at the odd-numbered bit and the bit line lead 18 electrically connected to the bit line 17 at the even-numbered bit are both located at the bit line 17 at the even-numbered bit. the second end 172 .
  • the bit line leads 18 electrically connected to the bit line 17 of the odd-numbered bit are located at the first end of the bit line 17 of the odd-numbered bit. 171.
  • the bit line leads 18 electrically connected to the even-numbered bit line 17 are all located at the second end 172 of the even-numbered bit line 17, that is, with any two adjacent ones.
  • the two bit line leads 18 connected to the bit line 17 are distributed at opposite ends of the bit line area 10, thereby increasing the distance between the two adjacent bit line leads 18 and reducing
  • the capacitive coupling effect between adjacent bit line leads 18 further improves the electrical properties of the semiconductor structure, increases the process window when forming the bit line leads 18, and reduces the manufacturing difficulty of the semiconductor structure.
  • each of the bit lines 17 includes a first end surface and a second end surface opposite to the first end surface along the first direction D1;
  • the first end surfaces of all the bit lines 17 arranged at intervals along the direction D3 perpendicular to the top surface of the substrate are flush, and the second end surfaces of all the bit lines 17 are flush.
  • bit line leads 18 electrically connected to the bit line 17 of the odd-numbered bit are located at the first end 171 of the bit line 17 of the odd-numbered bit, they are connected to the bit line 17 of the even-numbered bit.
  • the bit line leads 18 electrically connected to the bit lines 17 are all located at the second end portions 172 of the even-numbered bit lines 17. Therefore, the first end surfaces of multiple bit lines 17 can The plurality of bit lines 17 are all aligned, and the second end surfaces of the plurality of bit lines 17 are also aligned, so that the plurality of bit lines 17 do not need to form a step-like structure, which simplifies the manufacturing process of the semiconductor structure.
  • bit line lead 18 electrically connected to the lower bit line 17 needs to penetrate the upper bit line 17
  • the side walls of the bit line lead 18 need to be covered with an isolation layer to isolate all The sidewalls of the bit line lead 18 and the upper layer of the bit line 17.
  • a plurality of the bit lines 17 are arranged sequentially along the direction D3 perpendicular to the top surface of the substrate. Among any two adjacent odd-numbered bit lines 17 , the one closer to the The first end 171 of one bit line 17 of the substrate protrudes from the first end 171 of the other bit line 17 along the first direction D1;
  • the second end 172 of the bit line 17 closer to the substrate protrudes from the other bit line 17 along the first direction D1.
  • the second end of the bit line 17 is described.
  • the first end portions 171 of the bit lines 17 of the odd-numbered bits jointly form a step-like structure, and the second end portions 172 of the bit lines 17 of the even-numbered bits are also formed.
  • the stepped structure is jointly formed, so that the bit line leads 18 connected to the bit lines 17 of the lower layer do not need to pass through the bit lines 17 of the upper layer, thereby simplifying the formation process of the bit line leads 18 .
  • FIG. 5 is a third schematic top view of the semiconductor structure in the specific embodiment of the present disclosure
  • FIG. 6 is a third schematic three-dimensional structural diagram of the semiconductor structure in the specific embodiment of the present disclosure.
  • each bit line 17 extends along the first direction D1
  • each bit line 17 includes a third end portion 173 and a third end portion 173 .
  • the fourth end portion 174 opposite to the third end portion 173 in the second direction D2, among any two adjacent bit lines 17, the one of the bit line 17 that is closer to the substrate
  • the third end portion 173 protrudes from the third end portion 173 of the other bit line 17 along the second direction D2;
  • the plurality of bit line leads 18 are electrically connected to the third end portions 173 of the plurality of bit lines 17 respectively.
  • each bit line 17 extends along the first direction D1 , and each bit line 17 includes a third end portion 173 and a second end portion 173 along the second direction D1 .
  • the fourth end 174 of each bit line 17 in the direction D2 is opposite to the third end 173 and is electrically connected to all the source regions in one of the semiconductor layers.
  • the third end portions 173 of the plurality of bit lines form a stepped structure, so that the plurality of bit line leads 18 are electrically connected to the third end portions 173 of the plurality of bit lines 17 respectively.
  • each of the word lines 15 includes a fifth end and a sixth end opposite to the fifth end along the second direction D2; the semiconductor structure further includes:
  • a plurality of word line leads 16 are located on the top surface of the substrate. Each of the word line leads 16 extends in a direction D3 perpendicular to the top surface of the substrate. The plurality of word line leads 16 are respectively connected to A plurality of the word lines 15 are electrically connected;
  • the word line lead 16 electrically connected to one of the word lines 15 is located at the fifth end of one of the word lines 15,
  • the word line lead 16 electrically connected to the other word line 15 is located at the sixth end of the other word line 15 .
  • the word line lead 16 is used to transmit external control signals to the word line 15 .
  • Each of the word lines 15 includes a fifth end portion and a sixth end portion relatively distributed along the second direction D2, and two adjacent word lines 15 are respectively connected to the fifth end portion and the sixth end portion.
  • the word line leads 16 are distributed at opposite ends, thereby increasing the distance between two adjacent word line leads 16 and helping to reduce the capacitive coupling effect between multiple word line leads 16. Thereby further improving the electrical properties of the semiconductor structure.
  • a plurality of the word line leads 16 are electrically connected to the fifth ends of a plurality of the word lines 15 respectively, so that the signals of all the word lines 15 are led out on the same side, so that This helps to reduce the occupied area of the word line lead 16 and improve the space utilization inside the semiconductor structure.
  • This specific embodiment also provides a method for forming a semiconductor structure as described in any one of the above.
  • 7 is a flow chart of a method for forming a semiconductor structure in an embodiment of the present disclosure. Schematic diagrams of the semiconductor structure formed in this specific embodiment can be seen in Figures 1-6. As shown in Figures 1-7, the method for forming the semiconductor structure includes the following steps:
  • Step S71 provide a substrate
  • Step S72 Form a plurality of word lines 15 on the top surface of the substrate.
  • Each of the word lines 15 extends in the direction D3 perpendicular to the top surface of the substrate.
  • the plurality of word lines 15 extend along the direction D3 perpendicular to the top surface of the substrate. They are arranged at intervals in one direction D1.
  • any two adjacent word lines 15 are at least partially staggered.
  • the first direction is a direction parallel to the top surface of the substrate. .
  • each word line extends in a direction perpendicular to the top surface of the substrate, and in a first direction parallel to the top surface of the substrate, Any two adjacent word lines are at least partially staggered, which can reduce the facing area between the two adjacent word lines, thereby reducing the capacitive coupling effect between the two adjacent word lines and achieving semiconductor Improvement of structural electrical properties.
  • the present disclosure reduces the capacitive coupling effect by reducing the facing area between two adjacent word lines, and the distance between the two adjacent word lines in a direction parallel to the top surface of the substrate does not need to be increase, thereby helping to control the size of the semiconductor structure.

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Abstract

本公开涉及一种半导体结构及其形成方法。所述半导体结构，包括：衬底；多条字线，位于所述衬底的顶面上，每条所述字线沿垂直于所述衬底的顶面的方向延伸，多条所述字线沿第一方向间隔排布，在沿所述第一方向上，任意相邻的两条所述字线至少部分错开设置，所述第一方向为平行于所述衬底的顶面的方向。本公开能够降低相邻两条字线之间的电容耦合效应，实现对半导体结构电性能的改善。

Description

半导体结构及其形成方法
相关申请引用说明
本申请要求于2022年04月24日递交的中国专利申请号202210433936.8、申请名为“半导体结构及其形成方法”的优先权，其全部内容以引用的形式附录于此。
技术领域
本公开涉及半导体制造技术领域，尤其涉及一种半导体结构及其形成方法。
背景技术
动态随机存储器(Dynamic Random Access Memory，DRAM)是计算机等电子设备中常用的半导体装置，其由多个存储单元构成，每个存储单元通常包括晶体管和电容器。所述晶体管的栅极与字线电连接、源极与位线电连接、漏极与电容器电连接，字线上的字线电压能够控制晶体管的开启和关闭，从而通过位线能够读取存储在电容器中的数据信息，或者将数据信息写入到电容器中。
在DRAM等半导体结构中，多条字线是位于同一水平高度，这样导致相邻字线之间的电容耦合效应较强，从而影响半导体结构的电性能。
因此，如何降低相邻字线之间的电容耦合效应，从而改善半导体结构的性能，是当前亟待解决的技术问题。
发明内容
本公开一些实施例提供的半导体结构及其形成方法，用于解决相邻字线之间的电容耦合效应较强的问题，以改善半导体结构的电性能。
根据一些实施例，本公开提供了一种半导体结构，包括：
衬底；
多条字线，位于所述衬底的顶面上，每条所述字线沿垂直于所述衬底的顶面的方向延伸，多条所述字线沿第一方向间隔排布，在沿所述第一方向上，任意相邻的两条所述字线至少部分错开设置，所述第一方向为平行于所述衬底的顶面的方向。
在一些实施例中，在沿所述第一方向上，任意相邻的两条所述字线完全错开设置。
在一些实施例中，在所述第一方向和垂直于所述衬底的顶面的方向共同构成的平面上，任意相邻的两条所述字线的投影部分重叠。
在一些实施例中，在沿所述第一方向上，多条所述字线依次排序，且任意相邻的两条第奇数位的所述字线在第二方向和垂直于所述衬底的顶面的方向共同构成的平面上的投影重叠，任意相邻的两条第偶数位的所述字线在所述第二方向和垂直于所述衬底的顶面的方向共同构成的平面上的投影重叠，所述第二方向为平行于所述衬底的顶面的方向，且所述第一方向与所述第二方向正交。
在一些实施例中，在沿所述第一方向上，多条所述字线依次排序，且任意相邻的两条第3n位的所述字线在第二方向和垂直于所述衬底的顶面的方向共同构成的平面上的投影重叠，任意相邻的两条第3n+1位的所述字线在所述第二方向和垂直于所述衬底的顶面的方向共同构成的平面上的投影重叠，任意相邻的两条第3n+2位的所述字线在所述第二方向和垂直于所述衬底的顶面的方向共同构成的平面上的投影重叠，其中，n为整数，所述第二方向为平行于所述衬底的顶面的方向，且所述第一方向与所述第二方向正交。
在一些实施例中，还包括：
多个半导体层，位于所述衬底的顶面上，每个所述半导体层包括沿所述第一方向间隔排布的多个有源柱，且多个所述半导体层沿垂直于所述衬底的顶面的方向间隔排布，每个所述有源柱包括沟道区域、以及沿第二方向分布于所述沟道区域的相对两侧的源极区域和漏极区域，每条所述字线连续包覆沿垂直于所述衬底的顶面的方向间隔排布的多个所述沟道区域，所述第二方向为平行于所述衬底的顶面的方向，且所述第一方向与所述第二方向正交；
多条位线，位于所述衬底的顶面上，每条所述位线沿所述第一方向延伸，多条所述位线沿垂直于所述衬底的顶面的方向间隔排布，且一条所述位线与一个所述半导体层中的所有所述源极区域电连接；
多条位线引线，位于所述衬底的顶面上，每条所述位线引线沿垂直于所述衬底的顶面的方向延伸，且多条所述位线引线分别与多条所述位线电连接。
在一些实施例中，每条所述位线包括第一端部、以及沿所述第一方向与所述第一端部相对的所第二端部，任意相邻的两条所述位线中，较靠近所述衬底 的一条所述位线的所述第一端部沿所述第一方向突出于另一条所述位线的所述第一端部；
多条所述位线引线分别与多条所述位线的所述第一端部电连接。
在一些实施例中，每条所述位线包括第一端部、以及沿所述第一方向与所述第一端部相对的第二端部；
在沿垂直于所述衬底的顶面的方向上任意相邻的两条所述位线中，与其中一条所述位线电连接的所述位线引线位于一条所述位线的所述第一端部，与另一条所述位线电连接所述位线引线位于另一条所述位线的所述第二端部。
在一些实施例中，多条所述位线沿垂直于所述衬底的顶面的方向依次排序，与第奇数位的所述位线电连接的所述位线引线均位于第奇数位的所述位线的所述第一端部，与第偶数位的所述位线电连接的所述位线引线均位于第偶数位的所述位线的所述第二端部。
在一些实施例中，每条所述位线包括第一端面、以及沿所述第一方向与所述第一端面相对的第二端面；
沿垂直于所述衬底的顶面的方向间隔排布的所有所述位线的所述第一端面平齐、且所有所述位线的所述第二端面平齐。
在一些实施例中，多条所述位线沿垂直于所述衬底的顶面的方向依次排序，任意相邻的两条第奇数位的所述位线中，较靠近所述衬底的一条所述位线的所述第一端部沿所述第一方向突出于另一条所述位线的所述第一端部；
任意相邻的两条第偶数位的所述位线中，较靠近所述衬底的一条所述位线的所述第二端部沿所述第一方向突出于另一条所述位线的所述第二端部。
在一些实施例中，每条所述位线包括第三端部、以及沿所述第二方向与所述第三端部相对的第四端部，任意相邻的两条所述位线中，较靠近所述衬底的一条所述位线的所述第三端部沿所述第二方向突出于另一条所述位线的所述第三端部；
多条所述位线引线分别与多条所述位线的所述第三端部电连接。
在一些实施例中，在沿所述第二方向上，任意相邻的两条所述字线的宽度相等。
在一些实施例中，每条所述字线包括第五端部、以及沿所述第二方向与所 述第五端部相对的第六端部；所述半导体结构还包括：
多条字线引线，位于所述衬底的顶面上，每条所述字线引线沿垂直于所述衬底的顶面的方向延伸，多条所述字线引线分别与多条所述字线电连接；
任意沿所述第一方向相邻的两条所述字线，与其中一条所述字线电连接的所述字线引线位于一条所述字线的所述第五端部，与另一条所述字线电连接的所述字线引线位于另一条所述字线的所述第六端部。
根据另一些实施例，本公开还提供了一种如上所述的半导体结构的形成方法，包括如下步骤：
提供衬底；
形成多条字线于所述衬底的顶面上，每条所述字线沿垂直于所述衬底的顶面的方向延伸，多条所述字线沿平行于所述衬底的顶面的方向间隔排布，在沿平行于所述衬底的顶面的方向上，任意相邻的两条所述字线至少部分错开设置。
本公开一些实施例提供的半导体结构及其形成方法，每条字线沿垂直于衬底的顶面的方向延伸，且在沿平行于所述衬底的顶面的第一方向上，任意相邻的两条所述字线至少部分错开设置，能够减少相邻两条所述字线之间的正对面积，从而降低相邻两条字线之间的电容耦合效应，实现对半导体结构电性能的改善。另外，本公开通过减少相邻两条所述字线之间的正对面积来降低电容耦合效应，相邻两条所述字线沿平行于所述衬底的顶面的方向上的距离无需增大，从而有助于控制所述半导体结构的尺寸。
附图说明
附图1是本公开具体实施方式中半导体结构的第一种俯视结构示意图；
附图2是本公开具体实施方式中半导体结构的第一种立体结构示意图；
附图3是本公开具体实施方式中半导体结构的第二种俯视结构示意图；
附图4是本公开具体实施方式中半导体结构的第二种立体结构示意图；
附图5是本公开具体实施方式中半导体结构的第三种俯视结构示意图；
附图6是本公开具体实施方式中半导体结构的第三种立体结构示意图；
附图7是本公开具体实施方式中半导体结构的形成方法流程图。
具体实施方式
下面结合附图对本公开提供的半导体结构及其形成方法的具体实施方式做详细说明。
本具体实施方式提供了一种半导体结构，附图1是本公开具体实施方式中半导体结构的第一种俯视结构示意图，附图2是本公开具体实施方式中半导体结构的第一种立体结构示意图，附图2是本公开具体实施方式中半导体结构的第一种立体结构示意图。本具体实施方式中所述的半导体结构可以是但不限于DRAM。如图1和图2所示，所述半导体结构，包括：
衬底；
多条字线15，位于所述衬底的顶面上，每条所述字线15沿垂直于所述衬底的顶面的方向D3延伸，多条所述字线15沿第一方向D1间隔排布，在沿所述第一方向D1上，任意相邻的两条所述字线15至少部分错开设置，所述第一方向为平行于所述衬底的顶面的方向。
具体来说，所述衬底可以是但不限于硅衬底，本具体实施方式以所述衬底为硅衬底为例进行说明。在其他实施例中，所述衬底还可以为氮化镓、砷化镓、碳化镓、碳化硅或SOI等半导体衬底。所述衬底用于支撑在其上的器件结构。所述字线15可以采用金属钨或者TiN等导电材料制成。
具体来说，如图1和图2所示，每条所述字线15沿垂直于所述衬底的顶面的方向D3延伸，形成垂直字线结构。多条所述字线15沿第一方向D1间隔排布。以相邻的第一字线151和第二字线152为例，在沿所述第一方向D1上，相邻的所述第一字线151与所述第二字线152至少部分错开设置，即所述第一字线151在第二方向D2和垂直于所述衬底的顶面的方向D3共同构成的平面上的投影与所述第二字线152在所述第二方向D2和垂直于所述衬底的顶面的方向D3共同构成的平面上的投影至少部分错开，从而使得所述第一字线151和所述第二字线152沿所述第一方向D1的正对面积减小，从而降低了所述第一字线151与所述第二字线152之间的电容耦合效应。其中，所述第一方向D1和所述第二方向D2均为平行于所述衬底的顶面的方向，且所述第一方向D1与所述第二方向D2正交。另外，本具体实施方式通过相邻的字线错开设置的方式来降低字线之间的电容耦合效应，因而无需增大所述第一字线151和所述第二字线152沿所述第一方向D1的间距，从而无需增大所述半导体结构的 尺寸，有助于使得所述半导体结构进一步提高所述半导体结构的集成度。
在一些实施例中，在沿所述第一方向D1上，任意相邻的两条所述字线15完全错开设置。
以多条所述字线15沿所述第一方向D1间隔排布为例，任意相邻的两条所述字线15完全错开设置是指，在沿所述第一方向D1上任意相邻的两条所述字线15，在所述第二方向D2和垂直于所述衬底的顶面的方向D3共同构成的平面上的投影相互分离(即互不重叠)。通过将两条相邻的所述字线15完全错开设置，可以充分消除相邻两条所述字线15之间的电容耦合效应，从而更好的改善半导体结构的性能。
在一些实施例中，在沿第二方向D2上，任意相邻的两条所述字线15的宽度相等，以简化所述半导体结构中字线的形成工艺，也能够使得多条所述字线15的电阻相等，简化所述半导体结构的字线驱动操作。
在一些实施例中，在沿平行于所述衬底的顶面的方向D3上，任意相邻的两条所述字线15在所述第二方向D2和垂直于所述衬底的顶面的方向D3共同构成的平面上的投影之间的间隙宽度为所述字线15的宽度的1/4～1/2。
举例来说，相邻的所述第一字线151与所述第二字线152完全错开设置，所述第一字线151在所述第二方向D2和垂直于所述衬底的顶面的方向D3共同构成的平面上的投影与所述第二字线152在所述第二方向D2和垂直于所述衬底的顶面的方向D3共同构成的平面上的投影之间的间隙宽度为所述第一字线151沿所述第二方向D2上的宽度的1/4～1/2，从而使得在消除相邻的所述第一字线151与所述第二字线152之间的电容耦合效应的同时，不会导致所述半导体结构的尺寸的增加。
本具体实施方式是以在沿平行于所述衬底的顶面的方向上，任意相邻的两条所述字线15完全错开设置为例进行说明。在其他具体实施方式中，在沿平行于所述衬底的顶面的方向上，任意相邻的两条所述字线15也可以仅部分错开设置，从而有助于在降低相邻字线之间的电容耦合效应的同时，进一步缩小所述半导体结构的尺寸。
在一实施例中，在所述第一方向D1和垂直于所述衬底的顶面的方向D3共同构成的平面上，任意相邻的两条所述字线15的投影部分重叠。
举例来说，对于在所述第一方向D1上相邻的所述第一字线151和所述第二字线152，所述第一字线151在所述第一方向D1和垂直于所述衬底的顶面的方向D3构成的平面上的投影与所述第二字线152在所述第一方向D1和垂直于所述衬底的顶面的方向D3构成的平面上部分重叠，从而有助于减小所述第一字线151与所述第二字线152在所述第一方向D1上的间距，以进一步提高所述半导体结构的存储密度。
在一些实施例中，在沿平行于所述衬底的顶面的方向上，多条所述字线15依次排序，且任意相邻的两条第奇数位的所述字线15在沿第二方向D2和垂直于所述衬底的顶面的方向D3共同构成的平面上的投影重叠，任意相邻的两条第偶数位的所述字线15在所述第二方向D2和垂直于所述衬底的顶面的方向D3共同构成的平面上的投影重叠，所述第二方向D2为平行于所述衬底的顶面的方向，且所述第一方向D1与所述第二方向D2正交。
具体来说，如图1和图2所示，在沿所述第一方向D1上，多条所述字线依次排序，即在沿所述第一方向D1上，第奇数位的所述字线15(例如所述第一字线151)与第偶数位的所述字线15(例如所述第二字线152)交替排布，任意相邻的第奇数位的所述字线15与第偶数位的所述字线15在沿所述第一方向D1上至少部分错开设置。任意相邻的两条第奇数位的所述字线15在第二方向D2和垂直于所述衬底的顶面的方向D3共同构成的平面上的投影重叠是指，任意相邻的两条第奇数位的所述字线15在所述第一方向D1上对准。任意相邻的两条第偶数位的所述字线15在所述第二方向D2和垂直于所述衬底的顶面的方向D3共同构成的平面上的投影重叠是指，任意相邻的两条第偶数位的所述字线15在所述第一方向D1上对准。通过设置奇偶字线，且任意相邻的两条第奇数位的所述字线15在所述第二方向D2和垂直于所述衬底的顶面的方向D3共同构成的平面上的投影重叠，任意相邻的两条第偶数位的所述字线15在所述第二方向D2和垂直于所述衬底的顶面的方向D3共同构成的平面上的投影重叠，能够减少掩膜版的数量，从而简化所述半导体结构的制程工艺，降低半导体结构的制造成本。
为了进一步提高所述半导体结构的集成度，在一些实施例中，在沿所述第一方向D1上，多条所述字线15依次排序，且任意相邻的两条第3n位的所述 字线15在第二方向D2和垂直于所述衬底的顶面的方向D3共同构成的平面上的投影重叠，任意相邻的两条第3n+1位的所述字线15在所述第二方向D2和垂直于所述衬底的顶面的方向D3共同构成的平面上的投影重叠，任意相邻的两条第3n+2位的所述字线在所述第二方向D2和垂直于所述衬底的顶面的方向D3共同构成的平面上的投影重叠，其中，n为整数，所述第二方向为平行于所述衬底的顶面的方向，且所述第一方向与所述第二方向正交。
在一些实施例中，所述半导体结构还包括：
多个半导体层，位于所述衬底的顶面上，每个所述半导体层包括沿所述第一方向D1间隔排布的多个有源柱131，且多个所述半导体层沿垂直于所述衬底的顶面的方向D3间隔排布，每个所述有源柱包括沟道区域、以及沿第二方向D2分布于所述沟道区域的相对两侧的源极区域和漏极区域，每条所述字线15连续包覆沿垂直于所述衬底的顶面的方向间隔排布的多个所述沟道区域，所述第二方向D2为平行于所述衬底的顶面的方向，且所述第一方向D1与所述第二方向D2正交；
多条位线17，位于所述衬底的顶面上，每条所述位线17沿所述第一方向D1延伸，多条所述位线17沿垂直于所述衬底的顶面的方向D3间隔排布，且一条所述位线17与一个所述半导体层中的所有所述源极区域电连接；
多条位线引线18，位于所述衬底的顶面上，每条所述位线引线18沿垂直于所述衬底的顶面D3的方向延伸，且多条所述位线引线18分别与多条所述位线17电连接。
在一些实施例中，每条所述位线17包括第一端部171、以及沿所述第一方向D1与所述第一端部171相对的所第二端部172，任意相邻的两条所述位线17中，较靠近所述衬底的一条所述位线17的所述第一端部171沿所述第一方向D1突出于另一条所述位线17的所述第一端部171；
多条所述位线引线18分别与多条所述位线17的所述第一端部171电连接。
具体来说，所述半导体层的材料可以是但不限于硅。如图1和图2所示，所述衬底的顶面上包括晶体管区域11、以及沿所述第二方向D2分布于所述晶体管区域11相对两侧的位线区域10和电容区域12。多个所述半导体层沿垂直于所述衬底的顶面的方向D3间隔排布，且每个所述半导体层中包括沿所述第 一方向D1间隔排布的多个半导体柱13，所述半导体柱13包括位于所述晶体管区域11的有源柱131和位于所述电容区域12的导电柱132。所述有源柱131包括沟道区域、以及沿所述第二方向D2位于所述沟道区域相对两侧的源极区域和漏极区域。所述漏极区域与所述导电柱132接触电连接，且所述漏极区域与所述导电柱132具有相同的掺杂离子，以进一步降低所述漏极区域与所述导电柱132之间的接触电阻。所述电容区域12还包括多个围绕所述导电柱132分布的电容器14。所述电容器14包括覆盖于所述导电柱132表面的下电极层、覆盖于所述下电极层表面的电介质层、以及覆盖于所述电介质层表面的上电极层。多条所述位线17均位于所述位线区域，多条所述位线17沿垂直于所述衬底的顶面的方向D3间隔排布，且一条所述位线17与一个所述半导体层中的所有所述源极区域电连接。
每条所述位线17沿所述第一方向D1延伸，任意相邻的两条所述位线17中，较靠近所述衬底的一条所述位线17的所述第一端部171沿所述第一方向D1突出于另一条所述位线17的所述第一端部171，从而多条所述位线17的所述第一端部171形成台阶状结构。多条所述位线引线18分别与多条所述位线17的所述第一端部171电连接，以便于同一侧将所有所述位线17的信号引出，从而有助于减少所述位线引线18的占用面积，提高所述半导体结构内部的空间利用率。
附图3是本公开具体实施方式中半导体结构的第二种俯视结构示意图，附图4是本公开具体实施方式中半导体结构的第二种立体结构示意图。在另一些实施例中，如图3和图4所示，每条所述位线17包括第一端部171、以及沿所述第一方向D1与所述第一端部171相对的第二端部172；
在沿垂直于所述衬底的顶面的方向D3上任意相邻的两条所述位线17中，与其中一条所述位线17电连接的所述位线引线18一条所述位线17的所述第一端部171，与另一条所述位线17电连接所述位线引线18位于另一条所述位线17的所述第二端部172。
在另一些实施例中，多条所述位线17沿垂直于所述衬底的顶面的方向D3依次排序，与第奇数位的所述位线17电连接的所述位线引线18均位于第奇数位的所述位线17的所述第一端部171，与第偶数位的所述位线17电连接的所 述位线引线18均位于第偶数位的所述位线17的所述第二端部172。
具体来说，如图3和图4所示，与第奇数位的所述位线17电连接的所述位线引线18均位于第奇数位的所述位线17的所述第一端部171，与第偶数位的所述位线17电连接的所述位线引线18均位于第偶数位的所述位线17的所述第二端部172，即与任意相邻的两条所述位线17连接的两条所述位线引线18分布于所述位线区域10的相对两端，从而增大了相邻的两条所述位线引线18之间的距离，减小了相邻的所述位线引线18之间的电容耦合效应，从而进一步改善了半导体结构的电性能，而且还能够增大形成所述位线引线18时的工艺窗口，降低半导体结构的制造难度。
在一些实施例中，每条所述位线17包括第一端面、以及沿所述第一方向D1与所述第一端面相对的第二端面；
沿垂直于所述衬底的顶面的方向D3间隔排布的所有所述位线17的所述第一端面平齐、且所有所述位线17的所述第二端面平齐。
具体来说，由于将与第奇数位的所述位线17电连接的所述位线引线18均位于第奇数位的所述位线17的所述第一端部171，与第偶数位的所述位线17电连接的所述位线引线18均位于第偶数位的所述位线17的所述第二端部172，因此，多条所述位线17的所述第一端面可以均对齐、多条所述位线17的所述第二端面也均对齐，从而多条所述位线17无需形成台阶状结构，简化了半导体结构的制造工艺。此时，由于与下层所述位线17电连接的所述位线引线18需要贯穿上层的所述位线17，因此，所述位线引线18的侧壁还需覆盖隔离层，以隔离所述位线引线18的侧壁与上层的所述位线17。
在一些实施例中，多条所述位线17沿垂直于所述衬底的顶面的方向D3依次排序，任意相邻的两条第奇数位的所述位线17中，较靠近所述衬底的一条所述位线17的所述第一端部171沿所述第一方向D1突出于另一条所述位线17的所述第一端部171；
任意相邻的两条第偶数位的所述位线17中，较靠近所述衬底的一条所述位线17的所述第二端部172沿所述第一方向D1突出于另一条所述位线17的所述第二端部。
具体来说，多条第奇数位的所述位线17的所述第一端部171共同形成台 阶状结构，且多条第偶数位的所述位线17的所述第二端部172也共同形成台阶状结构，从而使得与下层的所述位线17连接的所述位线引线18无需穿过上层的所述位线17，以简化所述位线引线18的形成工艺。
附图5是本公开具体实施方式中半导体结构的第三种俯视结构示意图，附图6是本公开具体实施方式中半导体结构的第三种立体结构示意图。在另一些实施例中，如图5和图6所示，每条所述位线17沿所述第一方向D1延伸，且每条所述位线17包括第三端部173、以及沿所述第二方向D2与所述第三端部173相对的第四端部174，任意相邻的两条所述位线17中，较靠近所述衬底的一条所述位线17的所述第三端部173沿所述第二方向D2突出于另一条所述位线17的所述第三端部173；
多条所述位线引线18分别与多条所述位线17的所述第三端部173电连接。
具体来说，如图5和图6所示，每条所述位线17沿所述第一方向D1延伸，且每条所述位线17包括第三端部173、以及沿所述第二方向D2与所述第三端部173相对的第四端部174，每条所述位线17的所述第四端部174与一个所述半导体层中所有的源极区域电连接。多条所述位线的所述第三端部173构成台阶状结构，使得多条所述位线引线18分别与多条所述位线17的所述第三端部173电连接。
在一些实施例中，每条所述字线15包括第五端部、以及沿所述第二方向D2与所述第五端部相对的第六端部；所述半导体结构还包括：
多条字线引线16，位于所述衬底的顶面上，每条所述字线引线16沿垂直于所述衬底的顶面的方向D3延伸，多条所述字线引线16分别与多条所述字线15电连接；
任意沿所述第一方向相邻的两条所述字线15，与其中一条所述字线15电连接的所述字线引线16位于一条所述字线15的所述第五端部，与另一条所述字线15电连接的所述字线引线16位于另一条所述字线15的所述第六端部。
具体来说，所述字线引线16用于将外部控制信号传输至所述字线15。每条所述字线15包括沿所述第二方向D2相对分布的所述第五端部和所述第六端部，与相邻的两条所述字线15分别连接的两条所述字线引线16分布于相对的两端，从而能够增大相邻的两条所述字线引线16之间的距离，有助于降低多 条所述字线引线16之间的电容耦合效应，从而进一步改善所述半导体结构的电性能。
在另一实施例中，多条所述字线引线16分别与多条所述字线15的所述第五端部电连接，以便于同一侧将所有所述字线15的信号引出，从而有助于减少所述字线引线16的占用面积，提高所述半导体结构内部的空间利用率。
本具体实施方式还提供了一种如上任一项所述的半导体结构的形成方法。附图7是本公开具体实施方式中半导体结构的形成方法流程图。本具体实施方式形成的半导体结构的示意图可以参见图1-图6。如图1-图7所示，所述半导体结构的形成方法，包括如下步骤：
步骤S71，提供衬底；
步骤S72，形成多条字线15于所述衬底的顶面上，每条所述字线15沿垂直于所述衬底的顶面的方向D3延伸，多条所述字线15沿第一方向D1间隔排布，在沿所述第一方向D1上，任意相邻的两条所述字线15至少部分错开设置，所述第一方向为平行于所述衬底的顶面的方向。
本具体实施方式一些实施例提供的半导体结构及其形成方法，每条字线沿垂直于衬底的顶面的方向延伸，且在沿平行于所述衬底的顶面的第一方向上，任意相邻的两条所述字线至少部分错开设置，能够减少相邻两条所述字线之间的正对面积，从而降低相邻两条字线之间的电容耦合效应，实现对半导体结构电性能的改善。另外，本公开通过减少相邻两条所述字线之间的正对面积来降低电容耦合效应，相邻两条所述字线沿平行于所述衬底的顶面的方向上的距离无需增大，从而有助于控制所述半导体结构的尺寸。
以上所述仅是本公开的优选实施方式，应当指出，对于本技术领域的普通技术人员，在不脱离本公开原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本公开的保护范围。

Claims (15)

  1. 一种半导体结构，包括：
    衬底；
    多条字线，位于所述衬底的顶面上，每条所述字线沿垂直于所述衬底的顶面的方向延伸，多条所述字线沿第一方向间隔排布，在沿所述第一方向上，任意相邻的两条所述字线至少部分错开设置，所述第一方向为平行于所述衬底的顶面的方向。
  2. 根据权利要求1所述的半导体结构，其中，在沿所述第一方向上，任意相邻的两条所述字线完全错开设置。
  3. 根据权利要求2所述的半导体结构，其中，在所述第一方向和垂直于所述衬底的顶面的方向共同构成的平面上，任意相邻的两条所述字线的投影部分重叠。
  4. 根据权利要求1所述的半导体结构，其中，在沿所述第一方向上，多条所述字线依次排序，且任意相邻的两条第奇数位的所述字线在第二方向和垂直于所述衬底的顶面的方向共同构成的平面上的投影重叠，任意相邻的两条第偶数位的所述字线在所述第二方向和垂直于所述衬底的顶面的方向共同构成的平面上的投影重叠，所述第二方向为平行于所述衬底的顶面的方向，且所述第一方向与所述第二方向正交。
  5. 根据权利要求1所述的半导体结构，其中，在沿所述第一方向上，多条所述字线依次排序，且任意相邻的两条第3n位的所述字线在第二方向和垂直于所述衬底的顶面的方向共同构成的平面上的投影重叠，任意相邻的两条第3n+1位的所述字线在所述第二方向和垂直于所述衬底的顶面的方向共同构成的平面上的投影重叠，任意相邻的两条第3n+2位的所述字线在第二方向和垂直于所述衬底的顶面的方向共同构成的平面上的投影重叠，其中，n为整数，所述第二方向为平行于所述衬底的顶面的方向，且所述第一方向与所述第二方向正交。
  6. 根据权利要求1所述的半导体结构，还包括：
    多个半导体层，位于所述衬底的顶面上，每个所述半导体层包括沿所述第 一方向间隔排布的多个有源柱，且多个所述半导体层沿垂直于所述衬底的顶面的方向间隔排布，每个所述有源柱包括沟道区域、以及沿第二方向分布于所述沟道区域的相对两侧的源极区域和漏极区域，每条所述字线连续包覆沿垂直于所述衬底的顶面的方向间隔排布的多个所述沟道区域，所述第二方向为平行于所述衬底的顶面的方向，且所述第一方向与所述第二方向正交；
    多条位线，位于所述衬底的顶面上，每条所述位线沿所述第一方向延伸，多条所述位线沿垂直于所述衬底的顶面的方向间隔排布；
    多条位线引线，位于所述衬底的顶面上，每条所述位线引线沿垂直于所述衬底的顶面的方向延伸，且多条所述位线引线分别与多条所述位线电连接。
  7. 根据权利要求6所述的半导体结构，其中，每条所述位线包括第一端部、以及沿所述第一方向与所述第一端部相对的第二端部，任意相邻的两条所述位线中，较靠近所述衬底的一条所述位线的所述第一端部沿所述第一方向突出于另一条所述位线的所述第一端部；
    多条所述位线引线分别与多条所述位线的所述第一端部电连接。
  8. 根据权利要求6所述的半导体结构，其中，每条所述位线包括第一端部、以及沿所述第一方向与所述第一端部相对的第二端部；
    在沿垂直于所述衬底的顶面的方向上任意相邻的两条所述位线中，与其中一条所述位线电连接的所述位线引线位于一条所述位线的所述第一端部，与另一条所述位线电连接所述位线引线位于另一条所述位线的所述第二端部。
  9. 根据权利要求8所述的半导体结构，其中，多条所述位线沿垂直于所述衬底的顶面的方向依次排序，与第奇数位的所述位线电连接的所述位线引线均位于第奇数位的所述位线的所述第一端部，与第偶数位的所述位线电连接的所述位线引线均位于第偶数位的所述位线的所述第二端部。
  10. 根据权利要求9所述的半导体结构，其中，每条所述位线包括第一端面、以及沿所述第一方向与所述第一端面相对的第二端面；
    沿垂直于所述衬底的顶面的方向间隔排布的所述位线的所述第一端面平 齐、且所述位线的所述第二端面平齐。
  11. 根据权利要求9所述的半导体结构，其中，多条所述位线沿垂直于所述衬底的顶面的方向依次排序，任意相邻的两条第奇数位的所述位线中，较靠近所述衬底的一条所述位线的所述第一端部沿所述第一方向突出于另一条所述位线的所述第一端部；
    任意相邻的两条第偶数位的所述位线中，较靠近所述衬底的一条所述位线的所述第二端部沿所述第一方向突出于另一条所述位线的所述第二端部。
  12. 根据权利要求6所述的半导体结构，其中，每条所述位线包括第三端部、以及沿所述第二方向与所述第三端部相对的第四端部，任意相邻的两条所述位线中，较靠近所述衬底的一条所述位线的所述第三端部沿所述第二方向突出于另一条所述位线的所述第三端部；
    多条所述位线引线分别与多条所述位线的所述第三端部电连接。
  13. 根据权利要求6所述的半导体结构，其中，在沿所述第二方向上，任意相邻的两条所述字线的宽度相等。
  14. 根据权利要求6所述的半导体结构，其中，每条所述字线包括第五端部、以及沿所述第二方向与所述第五端部相对的第六端部；所述半导体结构还包括：
    多条字线引线，位于所述衬底的顶面上，每条所述字线引线沿垂直于所述衬底的顶面的方向延伸，多条所述字线引线分别与多条所述字线电连接；
    任意沿所述第一方向相邻的两条所述字线，与其中一条所述字线电连接的所述字线引线位于一条所述字线的所述第五端部，与另一条所述字线电连接的所述字线引线位于另一条所述字线的所述第六端部。
  15. 一种如权利要求1所述的半导体结构的形成方法，包括如下步骤：
    提供衬底；
    形成多条字线于所述衬底的顶面上，每条所述字线沿垂直于所述衬底的顶面的方向延伸，多条所述字线沿第一方向间隔排布，在沿所述第一方向上，任意相邻的两条所述字线至少部分错开设置，所述第一方向为平行于所述衬底的顶面的方向。
PCT/CN2022/102861 2022-04-24 2022-06-30 半导体结构及其形成方法 WO2023206802A1 (zh)

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US20120119286A1 (en) * 2010-11-11 2012-05-17 Samsung Electronics Co., Ltd. Semiconductor devices having vertical channel transistors and methods for fabricating the same
US20130099305A1 (en) * 2011-10-19 2013-04-25 Sua KIM Semiconductor devices including a vertical channel transistor and methods of fabricating the same
CN112750829A (zh) * 2019-10-29 2021-05-04 三星电子株式会社 三维半导体存储器装置
CN112837723A (zh) * 2019-11-22 2021-05-25 上海磁宇信息科技有限公司 错层式金属位线走线的磁性随机存储器存储阵列

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* Cited by examiner, † Cited by third party
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US20090166872A1 (en) * 2007-12-26 2009-07-02 Taiwan Semiconductor Manufacturing Co., Ltd. Memory Word lines with Interlaced Metal Layers
US20120119286A1 (en) * 2010-11-11 2012-05-17 Samsung Electronics Co., Ltd. Semiconductor devices having vertical channel transistors and methods for fabricating the same
US20130099305A1 (en) * 2011-10-19 2013-04-25 Sua KIM Semiconductor devices including a vertical channel transistor and methods of fabricating the same
CN112750829A (zh) * 2019-10-29 2021-05-04 三星电子株式会社 三维半导体存储器装置
CN112837723A (zh) * 2019-11-22 2021-05-25 上海磁宇信息科技有限公司 错层式金属位线走线的磁性随机存储器存储阵列

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