WO2023206159A1 - 覆晶薄膜及显示装置 - Google Patents

覆晶薄膜及显示装置 Download PDF

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Publication number
WO2023206159A1
WO2023206159A1 PCT/CN2022/089641 CN2022089641W WO2023206159A1 WO 2023206159 A1 WO2023206159 A1 WO 2023206159A1 CN 2022089641 W CN2022089641 W CN 2022089641W WO 2023206159 A1 WO2023206159 A1 WO 2023206159A1
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Prior art keywords
dielectric
chip
layer
strip
length
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PCT/CN2022/089641
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English (en)
French (fr)
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WO2023206159A9 (zh
Inventor
冯博
杨炜帆
刘磊
尹晓峰
Original Assignee
京东方科技集团股份有限公司
北京京东方显示技术有限公司
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Application filed by 京东方科技集团股份有限公司, 北京京东方显示技术有限公司 filed Critical 京东方科技集团股份有限公司
Priority to CN202280000951.1A priority Critical patent/CN117337632A/zh
Priority to PCT/CN2022/089641 priority patent/WO2023206159A1/zh
Publication of WO2023206159A1 publication Critical patent/WO2023206159A1/zh
Publication of WO2023206159A9 publication Critical patent/WO2023206159A9/zh

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  • the present disclosure relates to the field of display technology, and specifically to a chip-on-chip film and a display device.
  • the purpose of the present disclosure is to overcome the above-mentioned shortcomings of the prior art and provide a chip-on-chip film and a display device.
  • a chip-on-chip film including:
  • a conductor layer is provided on one side of the base layer, the conductor layer includes a plurality of connecting wires arranged along the first direction, and a gap is provided between two adjacent connecting wires;
  • dielectric strips There are a plurality of dielectric strips, the dielectric strips are disposed in at least part of the gap, and the length of the dielectric strips in the second direction is less than or equal to the length of the gap in the second direction, and the third The two directions intersect with the first direction;
  • a protective layer is provided on the side of the conductor layer and the dielectric strip away from the base layer, and the dielectric constant of the dielectric strip is greater than the dielectric constant of the protective layer.
  • a plurality of the connecting wires are arranged axially symmetrically, and a plurality of the dielectric strips are arranged axially symmetrically, and the symmetry axis is the central axis of the base layer extending along the second direction. .
  • the length of the plurality of dielectric strips in the second direction decreases as the distance between the dielectric strips and the symmetry axis increases.
  • one ends of the plurality of dielectric strips are flush.
  • the height of the dielectric strip in the third direction is the same as the height of the connecting wire in the third direction, and the third direction is close to the conductor with the base layer.
  • One side of the layer is vertical, and the chip-on-chip film also includes:
  • a dielectric layer is provided between the conductor layer and the protective layer, and the orthographic projection of the protective layer on the base layer covers and is larger than the orthographic projection of the dielectric layer on the base layer, so The orthographic projection of the dielectric layer on the base layer covers the orthographic projection of the dielectric strip on the base layer, and the dielectric constant of the dielectric layer is greater than the dielectric constant of the protective layer.
  • the dielectric constant of the dielectric layer is the same as the dielectric constant of the dielectric strips, and the dielectric layer is connected to a plurality of the dielectric strips as one body.
  • the outermost edge line of the orthographic projection of the plurality of dielectric strips on the base layer is consistent with the orthographic projection of the dielectric layer on the base layer.
  • the edge lines coincide.
  • the chip-on-chip film further includes:
  • An integrated circuit is provided on the side of the protective layer away from the base layer and is electrically connected to the conductor layer;
  • a first binding pin is provided on one side of the integrated circuit and is used to connect the output signal terminal;
  • the second binding pin is provided on the side of the integrated circuit away from the first binding pin and is used to connect the input signal terminal.
  • the dielectric strip and the dielectric layer are provided on a side of the integrated circuit close to the first binding pin.
  • a plurality of the connecting wires are arranged axially symmetrically, the dielectric layer is arranged axially symmetrically, a plurality of the dielectric strips are arranged axially symmetrically, and the axis of symmetry is along the axis of the integrated circuit. a central axis extending in the second direction.
  • the length of the dielectric layer in the second direction decreases as the distance between the dielectric layer and the symmetry axis increases.
  • one end of the plurality of dielectric strips close to the integrated circuit is flush, and the side of the dielectric layer close to the integrated circuit is flush with the plurality of dielectric strips.
  • One end of the strip close to the integrated circuit is coplanar, and a side of the dielectric layer away from the integrated circuit intersects with the first direction.
  • the dielectric layer does not cover the outermost connecting wire, and there is no gap between the outermost connecting wire and its adjacent connecting wire. Set up dielectric strips.
  • the two connecting wires adjacent to the symmetry axis are completely covered by the dielectric layer, and the two connecting wires adjacent to the symmetry axis
  • the length of the dielectric strip between them in the second direction is equal to the length of the connecting wire in the second direction; or, the connecting wire penetrated by the symmetry axis is completely covered by the dielectric layer and is connected with the The length of the two dielectric strips adjacent to the symmetry axis in the second direction is equal to the length of the connecting wire in the second direction.
  • the dielectric constant of the dielectric layer and the dielectric strip increases with the increase of the minimum target compensation capacitance of the flip-chip film, and/or, the The lengths of the dielectric layer and the dielectric strip in the second direction increase as the minimum target compensation capacitance of the flip-chip film increases.
  • the dielectric constant of the dielectric layer and the dielectric strip is greater than or equal to 60.
  • the sum of the thickness of the dielectric layer and the thickness of the dielectric strip is greater than or equal to 10 microns; or, when the minimum target compensation capacitance of the chip-on-chip film is greater than or equal to 2 times the original capacitance, the dielectric
  • the dielectric constant of the electrical layer and the dielectric strip is greater than or equal to 30, and the sum of the thickness of the dielectric layer and the thickness of the dielectric strip is greater than or equal to 10 microns.
  • materials of the dielectric strip and the dielectric layer include TiO2.
  • a display device including:
  • Display panel including multiple data lines
  • the chip-on-chip film is the chip-on-chip film described in any one of the above, and is connected between the display panel and the circuit board, and the connecting wire is connected to the data line.
  • the lengths of the plurality of dielectric strips in the second direction increase as the length of the data lines decreases, and the data lines are located on the intermediary
  • the connecting wires are connected to the same side of the electrical strip.
  • the length of the dielectric layer in the second direction increases as the length of the data line connected by the connecting wire it covers decreases.
  • Figure 1 is a schematic structural diagram of a display panel.
  • Figure 2 is a schematic diagram of the equivalent circuit structure of the display panel.
  • FIG. 3 is a schematic structural diagram of an exemplary embodiment of the chip-on-chip film of the present disclosure.
  • Figure 4 is a schematic structural diagram of the chip-on-chip film in Figure 3 after forming a conductor layer on the base layer.
  • FIG. 5 is a schematic structural diagram after forming dielectric strips on the basis of FIG. 4 .
  • FIG. 6 is a schematic cross-sectional view cut along line A-A in FIG. 3 .
  • FIG. 7 is a schematic cross-sectional view cut along line B-B in FIG. 3 .
  • FIG. 8 is a schematic structural diagram of another exemplary embodiment of the chip-on-chip film of the present disclosure.
  • FIG. 9 is a schematic structural diagram after forming a dielectric layer on the basis of FIG. 5 .
  • FIG. 10 is a schematic cross-sectional view taken along line C-C in FIG. 8 .
  • T thin film transistor
  • C capacitor
  • Second substrate 22. Translucent part; 23. Light-shielding part; 24. Spacer;
  • Conductor layer 321. Connecting wire; 321z, first left connecting wire; 322z, second left connecting wire; 323z, third left connecting wire; 324z, fourth left connecting wire; 325z, fifth left connecting wire; 321y, first right connecting wire; 322y, second right connecting wire; 323y, third right connecting wire; 324y, fourth right connecting wire; 325y, fifth right connecting wire; 322, gap; 323, first wire; 324. Second wire;
  • L axis of symmetry
  • X first direction
  • Y second direction
  • Z third direction.
  • Example embodiments will now be described more fully with reference to the accompanying drawings.
  • Example embodiments may, however, be embodied in various forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concepts of the example embodiments.
  • the same reference numerals in the drawings indicate the same or similar structures, and thus their detailed descriptions will be omitted.
  • the drawings are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale.
  • Example embodiments of the present disclosure provide a chip-on-chip film 30.
  • the chip-on-chip film 30 may include a base layer 31, a conductor layer 32, a protective layer 35 and a plurality of dielectric strips 33; conductors
  • the layer 32 is provided on one side of the base layer 31.
  • the conductor layer 32 includes a plurality of connecting wires 321 arranged along the first direction X.
  • a gap 322 is provided between two adjacent connecting wires 321; at least part of the gap 322 is provided with an
  • the length of the dielectric strip 33 in the second direction Y is less than or equal to the length of the gap 322 in the second direction Y, and the second direction Y intersects the first direction X;
  • the protective layer 35 is provided between the conductor layer 32 and the dielectric layer 32 .
  • the dielectric constant of the dielectric strip 33 is greater than the dielectric constant of the protective layer 35 .
  • the chip-on-chip film 30 of the present disclosure is provided with a dielectric strip 33 in at least part of the gap 322.
  • the dielectric constant of the dielectric strip 33 is greater than the dielectric constant of the protective layer 35, so that the connecting wires 321 provided with the dielectric strip 33
  • the capacitance of the signal line connected to the connection wire 321 can be compensated, so that the display panel is fully charged when the refresh rate is increased, thereby reducing display defects.
  • Chip On Flex, or Chip On Film Compared with the traditional chip on substrate package (Chip On Glass, COG for short), the biggest improvement of COF is to fix the touch chip and other chips on the flexible circuit
  • the die on the board is constructed with a soft film, and a soft additional circuit board is used as a package chip carrier to connect the chip to the flexible substrate circuit.
  • a more intuitive expression is that the IC (chip) is embedded on a flexible printed circuit (FPC). And it can be folded to the back, can be applied to full-screen, and can better achieve the anti-static performance of full-screen.
  • the chip-on-chip film 30 is connected to the display panel.
  • an example of the display panel is given below.
  • the display panel may be a liquid crystal display panel.
  • the display panel may include an array substrate 10 and a color filter substrate 20 arranged opposite to the array substrate 10 .
  • the array substrate 10 and the color filter substrate 20 are provided with a plastic frame and a liquid crystal. layer, the liquid crystal layer is located in the plastic frame.
  • the array substrate 10 may include a first substrate substrate 11, and the first substrate substrate 11 may be a glass substrate; of course, in some other example embodiments of the present disclosure, the first substrate substrate 11 may also be quartz, etc.; A substrate substrate 11 may also include an organic insulating material layer.
  • the organic insulating material layer may be disposed on one side of the glass substrate.
  • the organic insulating material layer may be polyimide, polycarbonate, polyacrylate, or polyetherimide. Resin materials such as amine, polyethersulfone, polyethylene terephthalate and polyethylene naphthalate.
  • a gate layer 12 may be provided on one side of the first substrate 11 .
  • the gate layer 12 may include a plurality of gate lines 131 , a plurality of gate electrodes and a plurality of sub-common electrodes.
  • the gate lines 131 extend along the second direction Y.
  • a plurality of sub-common electrodes are arranged in an array, and the plurality of sub-common electrodes arranged along the first direction One side of the first direction X.
  • two adjacent sub-common electrodes arranged along the second direction Y are connected as a whole.
  • the common electrode is provided in the entire layer, and the sub-common electrodes need to be connected as a whole.
  • the gate layer 12 may be made of metal.
  • a gate insulation layer 13 is provided on the side of the gate layer 12 away from the first base substrate 11 .
  • An active layer 14 is provided on the side of the gate insulating layer 13 away from the first substrate 11 .
  • the active layer 14 may include a channel portion and a conductor portion.
  • the channel portion is provided on the side of the gate line 131 away from the first substrate 11 .
  • On one side of 11, a part of the gate line 131 opposite to the channel portion can serve as a gate electrode.
  • Two conductor parts are connected to both ends of the channel part in one-to-one correspondence.
  • An active drain layer 15 is provided on a side of the active layer 14 away from the first base substrate 11.
  • the source and drain layer 15 may include a source electrode 151, a drain electrode 152, a connection portion and a data line 153.
  • the data line 153 is along the first One direction extends to X.
  • the second direction Y intersects the first direction X.
  • the second direction Y may be perpendicular to the first direction X.
  • One end of the source electrode 151 is connected to the data line 153 and the other end is connected to a conductor part; one end of the drain electrode 152 is connected to another conductor part.
  • the gate electrode, channel portion, source electrode 151, drain electrode 152, and two conductor portions form one thin film transistor T.
  • the thin film transistor T described in this specification is a bottom gate thin film transistor T.
  • the thin film transistor T may also be a top gate type or a double gate type.
  • the specific structure of the thin film transistor T is as follows: This will not be described again.
  • the functions of the "source electrode 151" and the “drain electrode” may be interchanged with each other. Therefore, in this specification, “source electrode 151" and “drain electrode” may be interchanged with each other.
  • a planarization layer 16 is provided on the side of the source and drain layer 15 away from the first base substrate 11 .
  • a via hole is provided on the planarization layer 16 .
  • a planarization layer 16 is provided on the side away from the first base substrate 11 .
  • the pixel electrode 17 is connected to the other end of the drain electrode 152 through a via hole.
  • the pixel electrode 17 and the common electrode form a capacitor C to drive the rotation of liquid crystal molecules in the liquid crystal layer.
  • the color filter substrate 20 may include a second base substrate 21, a light-transmitting portion 22, and a light-shielding portion 23.
  • the light-transmitting portion 22 is provided on a side of the second base substrate 21 close to the array substrate 10.
  • the light-transmitting part 22 is arranged opposite to the pixel area; the light-shielding part 23 is arranged on the side of the second base substrate 21 close to the array substrate 10 , and the gap between the light-shielding part 23 and the pixel area is arranged opposite.
  • a plurality of spacers 24 are also provided on the color filter substrate 20 and the array substrate 10 .
  • a data line 153 connects the sources 151 of a plurality of thin film transistors T arranged along the first direction X.
  • the thin film transistors T When the thin film transistors T are turned on, one end of the data line 153 is connected to the pixel electrode 17 of the capacitor C. , the other end of the data line 153 is connected to the chip-on-chip film 30 , and the length of the data line 153 will affect the capacitor C.
  • the lengths of the data lines 153 connected to the thin film transistors T in each row are inconsistent, resulting in differences in display effects.
  • the length of the data line 153 has little impact on the charging effect of the capacitor C; when the refresh rate is high, since the charging time of the capacitor C is short, the length of the data line 153 has a significant impact on the capacitor C. C has a greater impact on the charging effect.
  • the display panel can also be an OLED (Organic Electroluminescence Display, organic light-emitting semiconductor) display substrate, QLED (Quantum Dot Light Emitting Diodes, quantum dot light-emitting diode) display substrate, etc.
  • OLED Organic Electroluminescence Display, organic light-emitting semiconductor
  • QLED Quantantum Dot Light Emitting Diodes, quantum dot light-emitting diode
  • FIGS. 3 to 10 The structure of the chip-on-chip film 30 is illustrated below. Referring to FIGS. 3 to 10 , several representative connecting wires 321 , first wires 323 and second wires 324 are illustrated in the figures only.
  • the material of the base layer 31 may be a flexible insulating material.
  • the material of the base layer 31 may be PI (polyimide).
  • the material of the base layer 31 may also be polycarbonate or polyacrylate. , polyetherimide, polyethersulfone, polyethylene terephthalate and polyethylene naphthalate and other resin materials.
  • the dielectric constant of the base layer 31 is approximately 3.0.
  • the thickness of the base layer 31 is greater than or equal to 33 microns and less than or equal to 35 microns, for example, it can be 34 microns. Of course, the thickness of the base layer 31 can be set to another value as needed.
  • a conductor layer 32 is provided on one side of the base layer 31 .
  • the conductor layer 32 may include a plurality of connecting wires 321 , and a gap 322 is provided between two adjacent connecting wires 321 . .
  • the plurality of connecting wires 321 are arranged in sequence along the first direction X. One end of the plurality of connection wires 321 may be used to connect to the data line 153, and the other end may be connected to the integrated circuit 36 (Integrated Circuit, IC).
  • the first binding pins 371 can be used to connect the output signal terminal and can be used for input.
  • the display signal for example, can be connected to the data line 153.
  • one end of the plurality of connection wires 321 connected to the data line 153 extends to one edge of the base layer 31 in the second direction Y, and is not covered by the dielectric layer 34 and the protective layer 35 to form a plurality of first binding wires. Feet371.
  • the plurality of first binding pins 371 are used for binding with the binding area of the display panel.
  • the other ends of the plurality of connecting wires 321 are connected to the integrated circuit 36. Since the length of the integrated circuit 36 in the first direction X is less than the length of the base layer in the first direction X, and the integrated circuit 36 is in the second direction Pins connected to the connecting wires 321 are provided on both sides of Y, and the pins in the middle part of the integrated circuit 36 are not connected to the connecting wires 321. Therefore, the connecting wires 321 need to be arranged in a bent shape.
  • connection wires 321 One part of the plurality of connection wires 321 is a first connection wire, and the other part is a second connection wire.
  • the first connection wire is connected to a side of the integrated circuit 36 close to the first binding pin 371
  • the second connection wire is connected to a side of the integrated circuit 36 away from the first binding pin 371 .
  • the first connecting wire may be provided in a bent shape with two corners.
  • the second connecting wire may be provided in a bent shape with four or five corners.
  • the plurality of connecting wires 321 are arranged symmetrically, and the symmetry axis L is the central axis of the base layer 31 extending along the second direction Y. Furthermore, the data lines 153 connected to the connecting wires 321 are also arranged symmetrically. Moreover, to avoid line crossing and facilitate control, the outermost connecting wire 321 is generally connected to the outermost data line 153, and the innermost connecting wire 321 is connected to the outermost data line 153. It is connected to the innermost data line 153, and the middle connecting wire 321 is connected to the data line in sequence.
  • inside and outside are relative terms.
  • the one close to the display area of the display panel is the inside, and the one far away from the display area of the display panel is the outside.
  • the connecting wire 321 the one close to the display area is the outside.
  • the integrated circuit 36 of the flip-chip film 30 is on the inner side, and the integrated circuit 36 away from the flip-chip film 30 is on the outer side.
  • the plurality of connection wires 321 may all be connected to a side of the integrated circuit 36 close to the first binding pin 371 , and the plurality of connection wires 321 may not be configured to be bent. shape, and is arranged in a linear shape; in addition, the number of corners of the multiple connecting wires 321 can also be set as needed; the multiple connecting wires 321 can also be arranged asymmetrically.
  • the conductor layer 32 may also include a plurality of first conductors 323 arranged at intervals.
  • the second binding pins 372 are used to connect input signal terminals, for example , can be connected to VGH, VGL, GND, etc., specifically, the other ends of the plurality of first wires 323 extend to the edge of the base layer 31 away from the first binding pin 371, and are not covered by the protective layer 35.
  • the conductor layer 32 may also include a plurality of second conductors 324 arranged at intervals. One end of the plurality of second conductors 324 extends to one edge of the base layer 31 in the second direction Y, and is exposed to form a plurality of third binding pins 373 . , the plurality of third binding pins 373 and the plurality of first binding pins 371 are arranged in a row; the other ends of the plurality of second wires 324 extend to the opposite edge of the base layer 31 in the second direction Y, Moreover, a plurality of fourth binding pins 374 are formed and exposed, and the plurality of fourth binding pins 374 and the plurality of second binding pins 372 are arranged to form a row.
  • the first conductor 323 and the second conductor 324 can also be arranged in a bent shape, and the specific number of corners can also be set as needed.
  • the material of the conductor layer 32 can be copper. Of course, the material of the conductor layer 32 can also be other metals with good electrical conductivity.
  • the thickness of the conductor layer 32 is greater than or equal to 6.5 microns and less than or equal to 9.5 microns, for example, it can be 7 microns, 8 microns, 9 microns, etc. Of course, the thickness of the conductor layer 32 can be set to another value as needed.
  • a dividing line connecting the wire 321 and the first binding pin 371 is shown in FIG. 5 with a dotted line.
  • a dielectric strip 33 is disposed in at least part of the gap 322 , the length of the dielectric strip 33 is less than or equal to the length of the gap 322 , and the width of the dielectric strip 33 is equal to the width of the gap 322 .
  • the dielectric constant of the dielectric strip 33 is greater than the dielectric constant of the protective layer 35 , thus increasing the capacitance between two adjacent connecting wires 321 .
  • the outermost connection wire 321 is correspondingly connected to the outermost data line 153, and the outermost data line 153 has the longest length and the largest capacitance, the length of the inner data line 153 gradually shortens, and the capacitance also gradually decreases; therefore, the most The outer data line 153 does not need capacitance compensation.
  • the outermost data line 153 can be used as a reference.
  • the other data lines 153 need to be compensated to have substantially the same capacitance as the outermost data line 153 .
  • the length of the connected data lines 153 is sequentially shortened. Starting from the right side of the first direction The lengths are gradually shortened.
  • the two outermost connecting wires 321 (the first left connecting wire 321z and the first right connecting wire 321y) are not provided with dielectric strips 33 on both sides; therefore, no dielectric strips 33 are provided on the two connecting wires 321.
  • a first left dielectric strip 331z is disposed between the second left connecting conductor 322z and the third left connecting conductor 323z, and a second left dielectric strip is disposed between the third left connecting conductor 323z and the fourth left connecting conductor 324z.
  • a third left dielectric strip 333z is provided between the fourth left connecting wire 324z and the fifth left connecting wire 325z,...; that is, the first left dielectric strip 331z is arranged sequentially on the left side of the first direction X , the second left dielectric strip 332z, the third left dielectric strip 333z...; Moreover, the lengths of these dielectric strips 33 gradually increase, because the ones located on the same side (left or right side) of these dielectric strips 33 The length of the data line 153 connected to the connecting wire 321 gradually decreases, and the capacitance that needs to be supplemented gradually increases. Increasing the length of the dielectric strip 33 can increase the capacitance of the connecting wire 321, thereby increasing the capacitance of the data line 153.
  • a first right dielectric bar 331y is provided between the second right connecting wire 322y and the third right connecting wire 323y
  • a second right dielectric strip 331y is provided between the third right connecting wire 323y and the fourth right connecting wire 324y.
  • the dielectric strip 332y is provided with a third right dielectric strip 333y,... between the fourth right connecting wire 324y and the fifth right connecting wire 325y; that is, the first right dielectric strip is arranged sequentially on the right side of the first direction X.
  • Increasing the length of the dielectric strip 33 can increase the capacitance of the connecting wire 321, thereby increasing the capacitance of the data line 153.
  • the plurality of dielectric strips 33 can also be arranged symmetrically. Specifically, the positions of the first left dielectric strip 331z and the first right dielectric strip 331y are symmetrical to each other, and the length of the first left dielectric strip 331z and the length of the first right dielectric strip 331y are the same; The positions of the two left dielectric strips 332z and the second right dielectric strip 332y are symmetrical to each other, and the lengths of the second left dielectric strips 332z and the second right dielectric strips 332y are the same; the third left dielectric strip 332z is the same as the length of the second right dielectric strip 332y.
  • the positions of the strip 333z and the third right dielectric strip 333y are symmetrical to each other, and the length of the third left dielectric strip 333z is the same as the length of the third right dielectric strip 333y.
  • the axis of symmetry L is the central axis of the integrated circuit 36 extending in the second direction Y. Furthermore, the length of the plurality of dielectric strips 33 in the second direction Y decreases as the distance between the dielectric strips 33 and the axis of symmetry L increases.
  • the symmetrical arrangement not only facilitates calculation during design, but also facilitates process operations during the preparation process; furthermore, when the pin densities on the first binding pin 371 and the integrated circuit 36 are different, the two adjacent connecting wires 321 The spacing between them is not always constant, but gradually widens from the integrated circuit 36 to the first binding pin 371. As a result, the width of the connecting wire 321 is not always constant, but becomes wider from the integrated circuit 36 to the first binding pin 371. The binding pin 371 gradually becomes wider. In this case, it is more convenient to calculate and operate multiple dielectric strips 33 symmetrically, and has high accuracy.
  • the spacing between two adjacent connecting wires 321 may remain constant, and the positions of the first left dielectric strip 331z and the first right dielectric strip 331y may not change. Symmetry, as long as the length of the first left dielectric strip 331z is the same as the length of the first right dielectric strip 331y, the same capacitance compensation effect on the data line 153 can be achieved.
  • the spacing between two adjacent connecting wires 321 is not always constant, the positions of the first left dielectric strip 331z and the first right dielectric strip 331y can be asymmetrical, as long as they can respectively achieve the desired Just add the capacitor.
  • FIG. 3 and 5 Please continue to refer to Figures 3 and 5.
  • multiple dielectric strips 33 are provided on the side of the integrated circuit 6 close to the first binding pin 371. Since the side of the integrated circuit 6 close to the first binding pin 371 is connected The arrangement of the wires is relatively neat, which facilitates calculation during design and facilitates process operations during the preparation process.
  • One end of the plurality of dielectric strips 33 close to the integrated circuit 6 is flush, which facilitates calculation and drawing during design and facilitates process operations during the preparation process.
  • one end of the plurality of dielectric strips 33 close to the integrated circuit 6 is substantially coplanar with the side of the integrated circuit 6 close to the first binding pin 371 .
  • one end of the plurality of dielectric strips 33 close to the integrated circuit 6 may not be flush.
  • the plurality of dielectric strips 33 may be disposed with a symmetry axis extending along the second direction. Due to the symmetrical structure, both ends of the plurality of dielectric strips 33 are not flush; the ends of the plurality of dielectric strips 33 that are far away from the integrated circuit 6 can also be arranged flush.
  • the dielectric constant of the dielectric strip 33 increases with the increase of the minimum target compensation capacitance of the flip-chip film 30 and/or the length of the dielectric strip 33 in the second direction Y increases with the minimum target compensation capacitance of the flip-chip film 30 increases with the increase. That is, when the minimum target compensation capacitance of the chip-on-chip film 30 increases, it can be achieved by increasing the dielectric constant of the dielectric strip 33 or by increasing the length of the dielectric strip 33 in the second direction Y; it can also be achieved by increasing While increasing the dielectric constant of the dielectric strip 33 , the length of the dielectric strip 33 in the second direction Y is also increased.
  • the target compensation capacitor is the capacitance that the flip-chip film 30 needs to compensate for the data line. However, since the capacitance that needs to be compensated for each data line is different, some are large and some are small. Therefore, there are multiple target compensation capacitors for the flip-chip film 30, including There are big ones and small ones; for ease of comparison, the minimum target compensation capacitance is used as the benchmark. Since the gap 322 between two adjacent connecting wires 321 is closely related to the size of the display panel, the size of the integrated circuit 36 and the pixel density of the display panel, etc., the gap 322 between the two adjacent connecting wires 321 is cannot be changed at will, resulting in that the width of the dielectric strip 33 in the second direction Y is fixed.
  • the minimum target compensation capacitance of the chip-on-chip film 30 It is necessary to increase the minimum target compensation capacitance of the chip-on-chip film 30. This can be done by increasing the length of the dielectric strip 33, or by increasing The dielectric constant of the dielectric strip 33 reaches; however, the length of the dielectric strip 33 is related to the length of the connecting wire 321. When the minimum target compensation capacitance is large and the length of the connecting wire 321 is short, by increasing the dielectric If the length of the electrical strip 33 cannot meet the requirement of the target compensation capacitance, it can be achieved by increasing the dielectric constant of the dielectric strip 33 .
  • the height of the dielectric strip 33 in the third direction Z is the same as the height of the connecting wire 321 in the third direction Z.
  • the third direction Z is close to the base layer 31 and the conductor layer 32 .
  • One side is vertical, that is, the dielectric strip 33 fills the gap 322 between two adjacent connecting wires 321, so that the side of the dielectric strip 33 facing away from the base layer 31 and the side of the connecting wire 321 facing away from the base layer 31 are basically coplanar, which is convenient.
  • the protective layer 35 is prepared so that the protective layer 35 can be completely attached to the side of the dielectric strip 33 facing away from the base layer 31 and the side of the connecting wire 321 facing away from the base layer 31 without gaps 322 to prevent water vapor from entering the flip-chip film from the gaps 322 After 30 seconds, the damage caused by corrosion to the dielectric strip 33 and the connecting wire 321 is ensured to ensure the sealing effect of the protective layer 35 on the dielectric strip 33 and the connecting wire 321.
  • the height of the dielectric strip 33 in the third direction Z may also be smaller than the height of the connecting wire 321 in the third direction Z, and the height of the dielectric strip 33 in the third direction Z may be smaller. It can be greater than the height of the connecting wire 321 in the third direction Z.
  • a filling glue layer can be provided on the side of the protective layer 35 and the dielectric strip 33 facing away from the base layer 31 and the side of the connecting wire 321 facing away from the base layer 31.
  • the sealing effect on the dielectric strip 33 and the connecting wire 321 is achieved by filling the glue layer, thereby preventing water vapor from entering the chip-on film 30 from the gap 322 and causing damage to the dielectric strip 33 and the connecting wire 321 due to corrosion.
  • a protective layer 35 is provided on the side of the dielectric strip 33 facing away from the base layer 31 and the side of the connecting wire 321 facing away from the base layer 31 .
  • a protective layer 35 is also provided between two adjacent connecting wires 321 without a dielectric strip 33 , so that only a dielectric strip 33 is provided between a part of two adjacent connecting wires 321 .
  • a dielectric strip 33 and a protective layer 35 are disposed between a portion of two adjacent connecting wires 321 .
  • the protective layer 35 not only protects the connecting wires 321 and the dielectric strips 33 , but also isolates two adjacent connecting wires 321 .
  • the material of the protective layer 35 may be SR (Solder Resist, solder resist).
  • the solder resist is a coating used to provide dielectric and mechanical shielding during and after welding.
  • the solder resist film can be in the form of liquid or dry film, that is, the liquid material of the solder resist film can be coated on the side of the dielectric strip 33 facing away from the base layer 31 and the side of the connecting wire 321 facing away from the base layer 31.
  • the dry film-forming protective layer 35 can also be directly attached to the side of the dielectric strip 33 facing away from the base layer 31 and the side of the connecting wire 321 facing away from the base layer 31 .
  • the dielectric constant of the protective layer 35 is approximately 3.0. If the dielectric strip 33 is not provided, the capacitance formed between the connecting wires 321 is on the order of 10 -1 pF, and it is difficult to compensate for the pF level.
  • the chip-on-chip film 30 may also include The dielectric layer 34 is disposed between the conductor layer 32 and the dielectric strip 33 and the protective layer 35, that is, the dielectric layer 34 is disposed on the side of the conductor layer 32 and the dielectric strip 33 away from the base layer 31 to protect The layer 35 is provided on the side of the dielectric layer 34 away from the base layer 31 ; the orthographic projection of the protective layer 35 on the base layer 31 covers and is larger than the orthographic projection of the dielectric layer 34 on the base layer 31 .
  • the dielectric constant of the dielectric layer 34 is the same as that of the dielectric strips 33 , and the dielectric layer 34 and the plurality of dielectric strips 33 are connected as one body.
  • connection wires 321 are not provided with the dielectric layer 34 on the side facing away from the base layer 31; therefore, the dielectric layer 34 is not provided for these two connections.
  • Wire 321 is not capacitively compensated.
  • a dielectric layer 34 is provided on the side of the second left connecting wire 322z to the second right connecting wire 322y away from the base layer 31, and the dielectric strip between the second left connecting wire 322z and the second right connecting wire 322y
  • a dielectric layer 34 is provided on each side of the substrate 33 away from the base layer 31; and the dielectric layers 34 are connected to form one piece.
  • the length of the dielectric layer 34 in the first direction In an extended strip shape, the length of the dielectric layer 34 located on the side of the dielectric strip 33 away from the base layer 31 in the second direction Y is the same as the length of the dielectric strip 33 , so that the plurality of dielectric strips 33 are positioned on the base layer 31
  • the outermost edge line of the orthographic projection coincides with the edge line of the orthographic projection of the dielectric layer 34 on the base layer 31; and the length of the dielectric layer 34 located on the side of the connecting wire 321 away from the base layer 31 in the first direction X can be equal to
  • the adjacent dielectric layers 34 have the same length, so that one side of the dielectric layer 34 forms a step shape.
  • the step-shaped dielectric layer 34 requires higher precision in the process. However, since the width of the connecting wire 321 is thin and the length of the dielectric strip 33 is also thin, one side of the dielectric layer 34 can be set in an inclined shape, which facilitates subsequent process operations and has low process requirements. ,cut costs
  • the dielectric layer 34 may also be arranged symmetrically.
  • the symmetry axis L is the central axis of the integrated circuit 36 extending along the second direction Y
  • the central axis extending along the second direction Y of the integrated circuit 36 is collinear with the central axis extending along the second direction Y of the base layer 31 .
  • the symmetrical setting not only facilitates calculations during design, but also facilitates process operations during the preparation process.
  • the length of the dielectric layer 34 in the second direction Y decreases as the distance between the dielectric layer 34 and the symmetry axis L increases. Furthermore, the side of the dielectric layer 34 close to the integrated circuit 36 is set as a plane parallel to the first direction The side of the dielectric layer 34 close to the integrated circuit 36 is in contact with the side of the integrated circuit 36 to ensure the sealing effect of the integrated circuit 36; the side of the dielectric layer 34 far away from the integrated circuit 36 intersects with the first direction, and the dielectric The side of layer 34 remote from integrated circuit 36 is coplanar with the side of plurality of dielectric strips 32 remote from integrated circuit 36 .
  • y is the length of the dielectric layer 34 covered by the connecting wire 321 in the second direction Y
  • x is the order of the connecting wires 321, and its value is a natural number, for example, the second left connecting wire 322z and the second right connecting wire 322y
  • the corresponding value is 0, the corresponding value of the third left connecting wire 323z and the third right connecting wire 323y is 1, the corresponding value of the fourth left connecting wire 321 and the fourth right connecting wire 321 is 2, and so on until
  • b is the length of the first left dielectric strip 331z or the length of the first right dielectric strip 331y.
  • a is the slope of the straight line, that is, the ratio of the difference in the length of the dielectric layer 34 covered by two adjacent connecting wires 321 in the first direction X to the spacing between the two adjacent connecting wires 321 .
  • the dielectric constant of the dielectric layer 34 increases with the increase of the minimum target compensation capacitance of the flip-chip film 30 , and/or the length of the dielectric layer 34 in the second direction Y increases with the minimum target compensation of the flip-chip film 30 increases with increasing capacitance. That is, when the minimum target compensation capacitance of the flip-chip film 30 increases, it can be achieved by increasing the dielectric constant of the dielectric layer 34 or by increasing the length of the dielectric layer 34 in the second direction Y; it can also be achieved by increasing While increasing the dielectric constant of the dielectric layer 34 , the length of the dielectric layer 34 in the second direction Y is also increased.
  • the dielectric of the dielectric layer 34 and the dielectric strip 33 can often be greater than or equal to 60; the thickness of the dielectric layer 34 and the dielectric strip 33 The sum of the thicknesses is greater than or equal to 10 microns.
  • the dielectric of the dielectric layer 34 and the dielectric strip 33 can often be greater than or equal to 30, and the thickness of the dielectric layer 34 is equal to the thickness of the dielectric strip 33 The sum is greater than or equal to 10 microns.
  • the dotted line in the figure is mainly to distinguish the dielectric layer 34 and the dielectric strip 33 .
  • the dielectric layer 34 and the dielectric strip 33 can be formed through the same patterning process, so that the dielectric layer 34 and the dielectric strip 33 can be formed through the same patterning process.
  • the dielectric constant of 34 is the same as that of the dielectric strips 33 , and the dielectric layer 34 is connected to a plurality of dielectric strips 33 as a whole.
  • the material of the dielectric layer 34 and the dielectric strip 33 can be TiO2, or other materials with a relatively large dielectric constant.
  • the dielectric layer 34 may not cover the second left connection wire 322z and the second right connection wire 322y, so that the orthographic projection of the plurality of dielectric strips 33 on the base layer 31
  • the outermost edge line coincides with the edge line of the orthographic projection of the dielectric layer 34 on the base layer 31 .
  • the dielectric layer 34 may be formed after the dielectric strips 33 are formed.
  • the dielectric layer 34 may also cover the longer connection wires 321 so that the orthographic projection of the dielectric layer 34 on the base layer 31 covers and is larger than multiple dielectric strips. Orthographic projection of 33 on the basal layer 31.
  • the axis of symmetry L does not penetrate the connecting wire 321 , but is provided with two connecting wires 321 adjacent to the axis of symmetry L on both sides of the axis of symmetry L.
  • the two connecting wires 321 adjacent to the axis of symmetry L 321 is completely covered by the dielectric layer 34, and the length of the dielectric strip 33 in the second direction Y between the two connecting wires 321 adjacent to the symmetry axis L is equal to the length of the connecting wire 321 in the second direction Y, that is, with
  • the gap 322 between the two connecting wires 321 adjacent to the symmetry axis L is filled by the dielectric strip 33 .
  • the symmetry axis L may penetrate a connecting wire 321 , then the connecting wire 321 penetrated by the symmetry axis L may be completely covered by the dielectric layer 34 and be adjacent to the symmetry axis L.
  • the length of the two dielectric strips 33 in the second direction Y is equal to the length of the connecting wire 321 in the second direction Y.
  • the experimental conditions are: two connections 321 with a length of 100 microns, the width of the connecting wire 321 is approximately 13 microns, and the width of the gap 322 between two adjacent connecting wires 321 is approximately 12 microns; without setting In the case of the dielectric strip 33 and the dielectric layer 34 (that is, only the base layer 31 and the protective layer 35 are provided), the capacitance between the two connecting wires 321 is approximately 11.6fF; In the case of layer 34, the capacitance between the two connecting wires 321 is approximately 66.2fF. After the dielectric strip 33 and the dielectric layer 34 are provided, the capacitance between the two connecting wires 321 increases to about 6 times. Therefore, the compensation capacitance can be increased to the pF level, and the capacitance compensation of the data line 153 can be realized.
  • a protective layer 35 is provided on a side of the dielectric layer 34 away from the base layer 31.
  • the specific structure of the protective layer 35 has been described in detail above, and therefore will not be described again here.
  • the display device may include a display panel, a chip-on-chip film 30 and a circuit board; the display panel may include a plurality of data lines 153; the chip-on-chip film 30 may be any of the above.
  • the chip-on-chip film 30 described in one item is connected between the display panel and the circuit board, and the connecting wire 321 is connected to the data line 153 .
  • the specific structure of the chip-on-chip film 30 has been described in detail above, and therefore will not be described again here.
  • the specific type of the display device is not particularly limited. Any type of display device commonly used in the field can be used, such as mobile devices such as mobile phones, wearable devices such as watches, VR devices, etc. Those skilled in the art can use the display device according to the The specific use should be selected accordingly and will not be described again here.
  • the display device may also include other necessary components and components, taking a computer monitor as an example, such as a casing, a circuit board, a power cord, etc. Those skilled in the art can determine the specific usage requirements of the display device. Supplement accordingly and will not go into details here.
  • the beneficial effects of the display device provided by the exemplary embodiments of the present invention are the same as the beneficial effects of the chip-on film 30 provided by the above exemplary embodiments, and will not be described again here.

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  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

一种覆晶薄膜(30)及显示装置，覆晶薄膜(30)包括基底层(31)、导体层(32)、保护层(35)以及多根介电条(33)；导体层(32)设于基底层(31)的一侧，导体层(32)包括多根沿第一方向排列的连接导线(321)，相邻两根连接导线(321)之间设置有间隙(322)；至少部分间隙(322)内设有介电条(33)，且介电条(33)的在第二方向长度小于或等于间隙(322)在第二方向的长度，第二方向与第一方向相交；保护层(35)设于导体层(32)和介电条(33)远离基底层(31)的一侧，介电条(33)的介电常数大于保护层(35)的介电常数。该覆晶薄膜(30)可以进行电容补偿。 (图3)

Description

覆晶薄膜及显示装置 技术领域
本公开涉及显示技术领域，具体而言，涉及一种覆晶薄膜及显示装置。
背景技术
随着科技的发展，客户对显示产品的要求越来越高，刷新率从120Hz不断提升，甚至高达500/1000Hz，刷新率提高后，导致显示画质不良。
需要说明的是，在上述背景技术部分公开的信息仅用于加强对本公开的背景的理解，因此可以包括不构成对本领域普通技术人员已知的现有技术的信息。
发明内容
本公开的目的在于克服上述现有技术的不足，提供一种覆晶薄膜及显示装置。
根据本公开的一个方面，提供了一种覆晶薄膜，包括：
基底层；
导体层，设于所述基底层的一侧，所述导体层包括多根沿第一方向排列的连接导线，相邻两根所述连接导线之间设置有间隙；
多根介电条，至少部分所述间隙内设有所述介电条，且所述介电条的在第二方向长度小于或等于所述间隙在所述第二方向的长度，所述第二方向与所述第一方向相交；
保护层，设于所述导体层和所述介电条远离所述基底层的一侧，所述介电条的介电常数大于所述保护层的介电常数。
在本公开的一种示例性实施例中，多根所述连接导线轴对称设置，多根所述介电条轴对称设置，对称轴为所述基底层沿所述第二方向延伸的中心轴。
在本公开的一种示例性实施例中，多根所述介电条在第二方向的长 度随着所述介电条与所述对称轴的距离的增加而减小。
在本公开的一种示例性实施例中，多根所述介电条的一端平齐。
在本公开的一种示例性实施例中，所述介电条在第三方向的高度与所述连接导线在第三方向的高度相同，所述第三方向与所述基底层靠近所述导体层的一面垂直，所述覆晶薄膜还包括：
介电层，设于所述导体层与所述保护层之间，所述保护层在所述基底层上的正投影覆盖且大于所述介电层在所述基底层上的正投影，所述介电层在所述基底层上的正投影覆盖所述介电条在所述基底层上的正投影，所述介电层的介电常数大于所述保护层的介电常数。在本公开的一种示例性实施例中，所述介电层的介电常数与所述介电条的介电常数相同，所述介电层与多根所述介电条连接为一体。
在本公开的一种示例性实施例中，多根所述介电条在所述基底层上的正投影的最外侧边沿线与所述介电层在所述基底层上的正投影的边沿线重合。
在本公开的一种示例性实施例中，所述覆晶薄膜还包括：
集成电路，设于所述保护层远离所述基底层的一侧，且与所述导体层电连接；
第一绑定引脚，设于所述集成电路的一侧，且用于连接输出信号端；
第二绑定引脚，设于所述集成电路远离所述第一绑定引脚的一侧，且用于连接输入信号端。
在本公开的一种示例性实施例中，所述介电条和所述介电层设于所述集成电路靠近所述第一绑定引脚的一侧。
在本公开的一种示例性实施例中，多根所述连接导线轴对称设置，所述介电层轴对称设置，多根所述介电条轴对称设置，对称轴为所述集成电路沿所述第二方向延伸的中心轴。
在本公开的一种示例性实施例中，所述介电层在第二方向的长度随着所述介电层与所述对称轴的距离的增加而减小。
在本公开的一种示例性实施例中，多根所述介电条的靠近所述集成电路的一端平齐，所述介电层的靠近所述集成电路的侧面与多根所述介电条的靠近所述集成电路的一端面共面，所述介电层的远离所述集成电 路的侧面与第一方向相交。
在本公开的一种示例性实施例中，所述介电层未覆盖位于最外侧的所述连接导线，在最外侧的所述连接导线与其相邻的所述连接导线之间的间隙内没有设置介电条。
在本公开的一种示例性实施例中，与所述对称轴相邻的两根所述连接导线被所述介电层完全覆盖，且与所述对称轴相邻的两根所述连接导线之间的介电条在第二方向的长度等于所述连接导线在第二方向的长度；或，被所述对称轴贯穿的所述连接导线被所述介电层完全覆盖，且与所述对称轴相邻的两根所述介电条在第二方向的长度等于所述连接导线在第二方向的长度。
在本公开的一种示例性实施例中，所述介电层和所述介电条的介电常数随着所述覆晶薄膜的最小目标补偿电容的增加而增加，和/或，所述介电层和所述介电条的在第二方向的长度随着所述覆晶薄膜的最小目标补偿电容的增加而增加。
在本公开的一种示例性实施例中，所述覆晶薄膜的所述最小目标补偿电容大于等于原电容的5倍时，所述介电层和所述介电条的介电常数大于等于60，所述介电层的厚度与所述介电条的厚度之和大于等于10微米；或，所述覆晶薄膜的所述最小目标补偿电容大于等于原电容的2倍时，所述介电层和所述介电条的介电常数大于等于30，所述介电层的厚度与所述介电条的厚度之和大于等于10微米。
在本公开的一种示例性实施例中，所述介电条和所述介电层的材料包括TiO2。
根据本公开的另一个方面，提供了一种显示装置，包括：
显示面板，包括多根数据线；
电路板；
覆晶薄膜，为上述任意一项所述的覆晶薄膜，连接于所述显示面板与所述电路板之间，连接导线连接于所述数据线。
在本公开的一种示例性实施例中，多根所述介电条在所述第二方向的长度随着所述数据线的长度的减小而增加，所述数据线与位于所述介电条的同一侧的所述连接导线连接。
在本公开的一种示例性实施例中，所述介电层的在第二方向的长度随着其覆盖的所述连接导线连接的所述数据线的长度的减小而增加。
应当理解的是，以上的一般描述和后文的细节描述仅是示例性和解释性的，并不能限制本公开。
附图说明
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合本公开的实施例，并与说明书一起用于解释本公开的原理。显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为显示面板的结构示意图。
图2为显示面板的等效电路结构示意图。
图3为本公开覆晶薄膜一示例实施方式的结构示意图。
图4为图3中覆晶薄膜在基底层上形成导体层后的结构示意图。
图5为在图4的基础上形成介电条后的结构示意图。
图6为按照图3中的A-A剖切后的剖视示意图。
图7为按照图3中的B-B剖切后的剖视示意图。
图8为本公开覆晶薄膜另一示例实施方式的结构示意图。
图9为在图5的基础上形成介电层后的结构示意图。
图10为按照图8中的C-C剖切后的剖视示意图。
附图标记说明：
10、阵列基板；20、彩膜基板；30、覆晶薄膜；
11、第一衬底基板；12、栅极层；13、栅绝缘层；131、栅线；14、有源层；15、源漏极层；151、源极；152、漏极；153、数据线；16、平坦化层；17、像素电极；
T、薄膜晶体管；C、电容器；
21、第二衬底基板；22、透光部；23、遮光部；24、隔垫物；
31、基底层；
32、导体层；321、连接导线；321z、第一左连接导线；322z、第二 左连接导线；323z、第三左连接导线；324z、第四左连接导线；325z、第五左连接导线；321y、第一右连接导线；322y、第二右连接导线；323y、第三右连接导线；324y、第四右连接导线；325y、第五右连接导线；322、间隙；323、第一导线；324、第二导线；
33、介电条；331z、第一左介电条；332z、第二左介电条；333z、第三左介电条；331y、第一右介电条；332y、第二右介电条；333y、第三右介电条；
34、介电层；35、保护层；36、集成电路；
371、第一绑定引脚；372、第二绑定引脚；373、第三绑定引脚；372、第四绑定引脚；
L、对称轴；X、第一方向；Y、第二方向；Z、第三方向。
具体实施方式
现在将参考附图更全面地描述示例实施方式。然而，示例实施方式能够以多种形式实施，且不应被理解为限于在此阐述的实施方式；相反，提供这些实施方式使得本公开将全面和完整，并将示例实施方式的构思全面地传达给本领域的技术人员。图中相同的附图标记表示相同或类似的结构，因而将省略它们的详细描述。此外，附图仅为本公开的示意性图解，并非一定是按比例绘制。
虽然本说明书中使用相对性的用语，例如“上”“下”来描述图标的一个组件对于另一组件的相对关系，但是这些术语用于本说明书中仅出于方便，例如根据附图中所述的示例的方向。能理解的是，如果将图标的装置翻转使其上下颠倒，则所叙述在“上”的组件将会成为在“下”的组件。当某结构在其它结构“上”时，有可能是指某结构一体形成于其它结构上，或指某结构“直接”设置在其它结构上，或指某结构通过另一结构“间接”设置在其它结构上。
用语“一个”、“一”、“该”、“所述”和“至少一个”用以表示存在一个或多个要素/组成部分/等；用语“包括”和“具有”用以表示开放式的包括在内的意思并且是指除了列出的要素/组成部分/等之外还可存在另外的要素/组成部分/等；用语“第一”、“第二”和“第三”等仅作为标记使用， 不是对其对象的数量限制。
发明人发现：刷新率提高后，导致显示画质不良的主要原因在于：刷新率提高，显示面板内的电容充电时间较短，导致电容充电不足，从而在显示时导致显示不良。
本公开示例实施方式提供了一种覆晶薄膜30，参照图3-图10所示，该覆晶薄膜30可以包括基底层31、导体层32、保护层35以及多根介电条33；导体层32设于基底层31的一侧，导体层32包括多根沿第一方向X排列的连接导线321，相邻两根连接导线321之间设置有间隙322；至少部分间隙322内设有介电条33，且介电条33的在第二方向Y长度小于或等于间隙322在第二方向Y的长度，第二方向Y与第一方向X相交；保护层35设于导体层32和介电条33远离基底层31的一侧，介电条33的介电常数大于保护层35的介电常数。
本公开的覆晶薄膜30，在至少部分间隙322内设置有介电条33，介电条33的介电常数大于保护层35的介电常数，使得设置有介电条33的连接导线321之间的电容增大，可以对与该连接导线321连接的信号线的电容进行补偿，使得在刷新率提高的情况下显示面板充电较足，从而减少显示不良。
覆晶薄膜30(Chip On Flex,or,Chip On Film，COF)与传统的基板上芯片封装(Chip On Glass，简称COG)相比，COF最大的改进就是将触控芯片等芯片固定于柔性线路板上的晶粒软膜构装，并且运用了软质附加电路板作封装芯片载体将芯片与软性基板电路接合的技术。更直观的表述就是IC(芯片)被镶嵌在了柔性电路板(Flexible Printed Circuit，简称FPC)上。而且可以实现向背面翻折，能够应用于全面屏，且能够较好地实现全面屏的防静电性能。
覆晶薄膜30连接于显示面板，为了更清楚的说明覆晶薄膜30，下面对显示面板进行举例说明。
参照图1所示，显示面板可以是液晶显示面板，显示面板可以包括阵列基板10，以及与阵列基板10相对设置的彩膜基板20，在阵列基板10和彩膜基板20设置有胶框和液晶层，液晶层位于胶框内。
阵列基板10可以包括第一衬底基板11，第一衬底基板11可以是玻 璃基板；当然，在本公开的其他一些示例实施方式中，第一衬底基板11还可以是石英等等；第一衬底基板11还可以包括有机绝缘材料层，有机绝缘材料层可以设置在玻璃基板的一侧，该有机绝缘材料层可以为聚酰亚胺、聚碳酸酯、聚丙烯酸酯、聚醚酰亚胺、聚醚砜、聚对苯二甲酸乙二醇酯和聚萘二甲酸乙二醇酯等树脂类材料。
在第一衬底基板11的一侧可以设置有栅极层12，栅极层12可以包括多根栅线131、多个栅极和多个子公共电极，栅线131沿第二方向Y延伸。多个子公共电极呈阵列排布，且沿第一方向X排列的多个子公共电极形成一行，相邻两行子公共电极之间设置有一根栅线131，即栅线131设置在子公共电极的第一方向X的一侧。而且沿第二方向Y排列的相邻两个子公共电极连接为一体，公共电极是整层设置的，子公共电极需要连接为一体。栅极层12的材质可以是金属。
在栅极层12远离第一衬底基板11的一侧设置有栅绝缘层13。在栅绝缘层13远离第一衬底基板11的一侧设置有有源层14，有源层14可以包括沟道部和导体部，沟道部设于栅线131的远离第一衬底基板11的一侧，与沟道部相对的栅线131的一部分可以作为栅极。在沟道部两端一一对应地连接有两个导体部。
在有源层14远离第一衬底基板11的一侧设置有源漏极层15，源漏极层15可以包括源极151、漏极152、连接部和数据线153，数据线153沿第一方向X延伸。第二方向Y与所述第一方向X相交，例如，可以是第二方向Y与所述第一方向X垂直。
源极151的一端连接于数据线153，另一端连接于一个导体部；漏极152的一端连接于另一个导体部。栅极、沟道部、源极151、漏极152以及两个导体部形成一个薄膜晶体管T。
需要说明的是，本说明书中说明的薄膜晶体管T为底栅型薄膜晶体管T，在本公开的其他示例实施方式中，薄膜晶体管T还可以是顶栅型或双栅型，对其具体结构在此不再赘述。而且，在使用极性相反的薄膜晶体管T的情况或电路工作中的电流方向变化的情况等下，“源极151”及“漏极”的功能有时互相调换。因此，在本说明书中，“源极151”和“漏极”可以互相调换。
在源漏极层15远离第一衬底基板11的一侧设置有平坦化层16，平坦化层16上设置有过孔，在平坦化层16远离第一衬底基板11的一侧设置有像素电极17，像素电极17通过过孔与漏极152的另一端连接。像素电极17与公共电极形成一个电容器C，驱动液晶层中液晶分子的转动。
在本示例实施方式中，彩膜基板20可以包括第二衬底基板21、透光部22和遮光部23，透光部22设于第二衬底基板21的靠近阵列基板10的一侧，透光部22与像素区相对设置；遮光部23设于第二衬底基板21的靠近阵列基板10的一侧，遮光部23与像素区之间的间隙相对设置。
在彩膜基板20与阵列基板10还设置有多个隔垫物24。
参照图2所示，一条数据线153连接沿第一方向X排列的多个薄膜晶体管T的源极151，在薄膜晶体管T打开的情况下，数据线153的一端连接至电容器C的像素电极17，数据线153的另一端连接至覆晶薄膜30，数据线153的长度会对电容器C产生影响。与各行薄膜晶体管T连接的数据线153的长度不一致，导致显示效果的差异。在刷新率较低的情况下，数据线153的长度对电容器C的充电效果影响不大；在刷新率较高的情况下，由于电容器C的充电时间较短，使得数据线153的长度对电容器C的充电效果影响较大。
当然，显示面板还可以是OLED(Organic Electroluminescence Display，有机发光半导体)显示基板、QLED(Quantum Dot Light Emitting Diodes，量子点发光二极管)显示基板等等。
下面对覆晶薄膜30的结构进行举例说明。参照图3-图10所示，图中只是示例性的画出若干条具有代表性的连接导线321、第一导线323和第二导线324。
在本示例实施方式中，基底层31的材质可以是柔性绝缘材料，例如，基底层31的材质可以是PI(聚酰亚胺)，基底层31的材质也可以是聚碳酸酯、聚丙烯酸酯、聚醚酰亚胺、聚醚砜、聚对苯二甲酸乙二醇酯和聚萘二甲酸乙二醇酯等树脂类材料。基底层31的介电常数大约为3.0。基底层31的厚度大于等于33微米且小于等于35微米，例如，可以是34微米，当然，基底层31的厚度可以根据需要设置为另外的值。
在本示例实施方式中，参照图4所示，在基底层31的一侧设置有导 体层32，导体层32可以包括多根连接导线321，相邻两根连接导线321之间设置有间隙322。多根连接导线321沿第一方向X依次排列。多根连接导线321的一端可以用于连接于数据线153，另一端连接于集成电路36(Integrated Circuit，IC)。
参照图3所示，多根连接导线321的与数据线153连接的一端裸露形成多个第一绑定引脚371，第一绑定引脚371可以用于连接输出信号端，可以用于输入显示信号，例如，可以连接数据线153。具体地，多根连接导线321的与数据线153连接的一端延伸至基底层31第二方向Y的一侧边沿，而且没有被介电层34和保护层35覆盖形成多个第一绑定引脚371。多个第一绑定引脚371用于与显示面板的绑定区绑定。
参照图4所示，多根连接导线321的另一端连接于集成电路36，由于集成电路36在第一方向X的长度小于底基层在第一方向X的长度，而且集成电路36在第二方向Y的两侧均设置有与连接导线321连接的引脚，还有集成电路36的中间部分的引脚不与连接导线321连接，因此，连接导线321需要设置为折弯状。
多根连接导线321中的一部分为第一连接导线，另一部分为第二连接导线。第一连接导线连接于集成电路36的靠近第一绑定引脚371的一侧，第二连接导线连接于集成电路36的背离第一绑定引脚371的一侧。
具体地，第一连接导线可以设置为具有两个拐角的折弯状。第二连接导线可以设置为具有四个或五个拐角的折弯状。
而且多根连接导线321是对称设置的，对称轴L是基底层31沿第二方向Y延伸的中心轴。再有，与连接导线321连接的数据线153也是对称设置的，而且，避免线路交叉和方便控制，一般位于最外侧的连接导线321与位于最外侧数据线153连接，位于最内侧的连接导线321与位于最内侧数据线153连接，中间的连接导线321与数据线依次连接。
需要说明的是，“内侧”和“外侧”均是相对而言的，对于数据线153来说，靠近显示面板显示区为内侧，远离显示面板显示区为外侧；对于连接导线321来说，靠近覆晶薄膜30的集成电路36为内侧，远离覆晶薄膜30的集成电路36为外侧。
当然，在本公开的其他示例实施方式中，多根连接导线321可以均 连接于集成电路36的靠近第一绑定引脚371的一侧，而且，多根连接导线321可以不设置为折弯状，而设置为直线状；另外，多根连接导线321的拐角个数也可以根据需要设置；多根连接导线321也可以不对称设置。请继续参照图3和图4所示，导体层32还可以包括多根间隔设置的第一导线323。多根第一导线323的一端连接于集成电路36，多根第一导线323的另一端裸露形成多个第二绑定引脚372，第二绑定引脚372用于连接输入信号端，例如，可以连接VGH、VGL、GND等等，具体地，多根第一导线323的另一端延伸至基底层31的背离第一绑定引脚371的一侧边沿，而且没有被保护层35覆盖形成多个第二绑定引脚372；使得第一绑定引脚371和第二绑定引脚372位于集成电路36第二方向Y的相对两侧。
导体层32还可以包括多根间隔设置的第二导线324，多根第二导线324的一端延伸至基底层31第二方向Y的一侧边沿，而且裸露形成多个第三绑定引脚373，多个第三绑定引脚373与多个第一绑定引脚371排列形成一排；多根第二导线324的另一端延伸至基底层31第二方向Y的相对另一侧边沿，而且裸露形成多个第四绑定引脚374，多个第四绑定引脚374与多个第二绑定引脚372排列形成一排。
而且，为了避让集成电路36第一导线323和第二导线324也可以设置为折弯状，具体的拐角个数也可以根据需要设置。
导体层32的材质可以是铜，当然，导体层32的材质还可以是其他导电性能较好的金属。导体层32的厚度大于等于6.5微米且小于等于9.5微米，例如，可以是7微米、8微米、9微米等等，当然，导体层32的厚度可以根据需要设置为另外的值。
在本示例实施方式中，参照图3和图5所示，图5中用虚线表示出连接导线321和第一绑定引脚371的分割线。在至少部分间隙322内设置有介电条33，介电条33的长度小于或等于间隙322的长度，介电条33的宽度等于间隙322的宽度。介电条33的介电常数大于保护层35的介电常数，因此，使得相邻两根连接导线321之间的电容增大。
由于最外侧的连接导线321对应连接最外侧的数据线153，而最外侧的数据线153的长度最长，电容最大，内侧的数据线153的长度逐渐 缩短，电容也逐渐减小；因此，最外侧数据线153不需要进行电容补偿，最外侧数据线153可以作为基准，其他数据线153需要补偿至与最外侧数据线153的电容基本相同。
为了方便后续说明，从第一方向X的左侧开始多根连接导线321依次为第一左连接导线321z、第二左连接导线322z、第三左连接导线323z……；而且与这些连接导线321连接的数据线153的长度依次缩短。从第一方向X的右侧开始多根连接导线321依次为第一右连接导线321y、第二右连接导线322y、第三右连接导线323y……；而且与这些连接导线321连接的数据线153的长度依次缩短。
具体来讲，位于最外侧的两根连接导线321(第一左连接导线321z和第一右连接导线321y)的两侧均没有设置介电条33；因此，对这两根连接导线321没有进行电容补偿。在第二左连接导线322z与第三左连接导线323z之间设置有第一左介电条331z，在第三左连接导线323z与第四左连接导线324z之间设置有第二左介电条332z，在第四左连接导线324z与第五左连接导线325z之间设置有第三左介电条333z，……；即在第一方向X的左侧依次设置有第一左介电条331z、第二左介电条332z、第三左介电条333z……；而且，这些介电条33的长度逐渐增加，因为，与位于这些介电条33同一侧(左侧或右侧)的连接导线321连接的数据线153的长度逐渐减小，需要补充的电容逐渐增加，增加介电条33的长度即可增加连接导线321的电容，从而增加数据线153的电容。
同理，在第二右连接导线322y与第三右连接导线323y之间设置有第一右介电条331y，在第三右连接导线323y与第四右连接导线324y之间设置有第二右介电条332y，在第四右连接导线324y与第五右连接导线325y之间设置有第三右介电条333y，……；即在第一方向X的右侧依次设置有第一右介电条331y、第二右介电条332y、第三右介电条333y……；而且，这些介电条33的长度逐渐增加，因为，与位于这些介电条33同一侧(左侧或右侧)的连接导线321连接的数据线153的长度逐渐减小，需要补充的电容逐渐增加，增加介电条33的长度即可增加连接导线321的电容，从而增加数据线153的电容。
而且，在第一方向X上，数据线153可以是对称设置的，连接数据 线153的连接导线321也可以是对称设置的。因此，多根介电条33也可以对称设置。具体地，第一左介电条331z与第一右介电条331y的位置是相互对称的，且第一左介电条331z的长度与第一右介电条331y的长度是相同的；第二左介电条332z与第二右介电条332y的位置是相互对称的，且第二左介电条332z的长度与第二右介电条332y的长度是相同的；第三左介电条333z与第三右介电条333y的位置是相互对称的，且第三左介电条333z的长度与第三右介电条333y的长度是相同的。对称轴L是集成电路36沿第二方向Y延伸的中心轴。而且，多根介电条33在第二方向Y的长度随着介电条33与对称轴L的距离的增加而减小。
对称设置不仅方便设计时的计算，而且方便制备过程中的工艺操作；再有，在第一绑定引脚371与集成电路36上的引脚密度不同的情况下，相邻两个连接导线321之间的间距不是一直不变的，而是从集成电路36到第一绑定引脚371逐渐变宽的，导致连接导线321的宽度也不是一直不变的，而是从集成电路36到第一绑定引脚371逐渐变宽的，这种情况下，将多根介电条33对称设置更方便计算和操作，而且准确度高。
当然，在本公开的其他一些示例实施方式中，相邻两个连接导线321之间的间距可以是一直不变的，第一左介电条331z与第一右介电条331y的位置可以不对称，只要第一左介电条331z的长度与第一右介电条331y的长度的相同即可达到对数据线153进行相同的电容补偿的作用。另外，在相邻两个连接导线321之间的间距不是一直不变的情况下，第一左介电条331z与第一右介电条331y的位置可以不对称，只要保证他们分别能够达到所要补充的电容即可。
请继续参照图3和图5所示，多根介电条33设置在集成电路6靠近第一绑定引脚371的一侧，由于集成电路6靠近第一绑定引脚371的一侧连接导线的排列较为整齐，方便设计时的计算，而且方便制备过程中的工艺操作。多根介电条33的靠近集成电路6的一端平齐，也是方便设计时的计算、画图，而且方便制备过程中的工艺操作。而且多根介电条33的靠近集成电路6的一端基本与集成电路6靠近第一绑定引脚371的一面共面。当然，在本公开的另一些示例实施方式中，多根介电条33的靠近集成电路6的一端可以不平齐，例如，多根介电条33可以设置为 沿第二方向沿伸的对称轴对称的结构，使得多根介电条33的两端均不是平齐的；还可以多根介电条33的远离集成电路6的一端平齐设置。
介电条33的介电常数随着覆晶薄膜30的最小目标补偿电容的增加而增加和/或，介电条33的在第二方向Y的长度随着覆晶薄膜30的最小目标补偿电容的增加而增加。即覆晶薄膜30的最小目标补偿电容增加的情况下，可以通过增加介电条33的介电常数，也可以通过增加介电条33的在第二方向Y的长度来达到；还可以在增加介电条33的介电常数的同时，增加介电条33的在第二方向Y的长度。
目标补偿电容为覆晶薄膜30需要给数据线补偿的电容，但是由于每根数据线需要补偿的电容是不同的，有大有小，因此，覆晶薄膜30的目标补偿电容也有多个，有大有小；为了便于比较，以最小目标补偿电容为基准。由于相邻两根连接导线321之间的间隙322与显示面板的尺寸、集成电路36的尺寸以及显示面板的像素密度等等密切相关，因此，相邻两根连接导线321之间的间隙322是不能够随意改变的，导致介电条33在第二方向Y的宽度是固定不变的，需要增加覆晶薄膜30的最小目标补偿电容，可以通过增加介电条33的长度，也可以通过增加介电条33的介电常数达到；但是，介电条33的长度又与连接导线321的长度相关，在最小目标补偿电容较大而连接导线321的长度又较短的情况下，通过增加介电条33的长度不能达到目标补偿电容的要求，可以通过增加介电条33的介电常数达到。
在本示例实施方式中，参照图6所示，介电条33在第三方向Z的高度与连接导线321在第三方向Z的高度相同，第三方向Z与基底层31靠近导体层32的一面垂直，即介电条33将相邻两根连接导线321之间的间隙322填满，使得介电条33背离基底层31的一面与连接导线321背离基底层31的一面基本共面，方便保护层35的制备，而且使得保护层35能够与介电条33背离基底层31的一面和连接导线321背离基底层31的一面完全贴合，没有间隙322，避免水汽从间隙322进入覆晶薄膜30后对介电条33和连接导线321的腐蚀造成的损伤，保证保护层35对介电条33和连接导线321的密封效果。
当然，在本公开的另一些示例实施方式中，介电条33在第三方向Z 的高度也可以小于连接导线321在第三方向Z的高度，介电条33在第三方向Z的高度还可以大于连接导线321在第三方向Z的高度，这种情况下，可以通过在保护层35与介电条33背离基底层31的一面和连接导线321背离基底层31的一面设置填充胶层，通过填充胶层达到对介电条33和连接导线321的密封效果，避免水汽从间隙322进入覆晶薄膜30后对介电条33和连接导线321的腐蚀造成的损伤。
在本示例实施方式中，请继续参照图3所示，在介电条33背离基底层31的一侧和连接导线321背离基底层31的一侧设置有保护层35。参照图7所示，而且在没有设置介电条33的相邻两根连接导线321之间也设置有保护层35，使得一部分相邻两根连接导线321之间仅设置有介电条33，一部分相邻两根连接导线321之间设置有介电条33和保护层35。使得保护层35不仅起到保护连接导线321和介电条33的作用，而且起到隔离相邻两根连接导线321的作用。
保护层35的材质可以是SR(Solder Resist，阻焊膜)，阻焊膜是用于在焊接过程中及焊接之后提供介质和机械屏蔽的一种覆膜。阻焊膜可以采用液体的或干膜形式，即可以将阻焊膜的液体材料涂覆在介电条33背离基底层31的一侧和连接导线321背离基底层31的一侧，烘干后形成保护层35，也可以直接将形成干膜的保护层35贴附在介电条33背离基底层31的一侧和连接导线321背离基底层31的一侧。保护层35的介电常数大约为3.0，如果不设置介电条33，连接导线321之间形成的电容在10 -1pF量级，而要补偿pF量级，比较困难。
参照图8和图9所示，图9中中用虚线表示出连接导线321和第一绑定引脚371的分割线，在本公开的另一示例实施方式中，覆晶薄膜30还可以包括介电层34，介电层34设于导体层32和介电条33与保护层35之间，即介电层34设于导体层32和介电条33背离基底层31的一侧，保护层35设于介电层34背离基底层31的一侧；保护层35在基底层31上的正投影覆盖且大于介电层34在基底层31上的正投影。介电层34的介电常数与介电条33的介电常数相同，介电层34与多根介电条33连接为一体。
具体来讲，位于最外侧的两根连接导线321(第一左连接导线321z 和第一右连接导线321y)背离基底层31的一侧均没有设置介电层34；因此，对这两根连接导线321没有进行电容补偿。在第二左连接导线322z至第二右连接导线322y背离基底层31的一侧均设置有介电层34，而且在第二左连接导线322z至第二右连接导线322y之间的介电条33的背离基底层31的一侧均设置有介电层34；而且上述介电层34连接形成一片。
介电层34的在第一方向X的长度随着其覆盖的连接导线321连接的所述数据线153的长度的减小而增加，可以将介电层34分割成多个沿第二方向Y延伸的条状，位于介电条33背离基底层31一面的介电层34在第二方向Y的长度与介电条33的长度相同，从而使得多根介电条33在基底层31上的正投影的最外侧边沿线与介电层34在基底层31上的正投影的边沿线重合；而位于连接导线321背离基底层31一面的介电层34在第一方向X的长度可以与相邻的介电层34的长度相同，这样使得介电层34的一侧边形成阶梯状，阶梯状的介电层34使得对工艺要求的精度较高。但是，由于连接导线321的宽度较细，介电条33的长度也较细，因此，可以将介电层34的一侧设置为倾斜状，这样方便后续的工艺操作，而且对工艺要求不高、降低成本。
而且，在第一方向X上，由于数据线153可以是对称设置的，连接数据线153的连接导线321也可以是对称设置的，多根介电条33也可以对称设置。因此，介电层34也可以是对称设置的。具体地，对称轴L是集成电路36沿第二方向Y延伸的中心轴，集成电路36沿第二方向Y延伸的中心轴与基底层31沿第二方向Y延伸的中心轴共线。对称设置不仅方便设计时的计算，而且方便制备过程中的工艺操作。
介电层34在第二方向Y的长度随着介电层34与对称轴L的距离的增加而减小。而且，介电层34的靠近集成电路36的侧面设置为与第一方向X平行的平面，且介电层34的靠近集成电路36的侧面与多个介电条32靠近集成电路36的侧面共面，介电层34的靠近集成电路36的侧面与集成电路36的侧面贴合，保证集成电路36的密封效果；介电层34的远离集成电路36的侧面与第一方向相交，且介电层34的远离集成电路36的侧面与多个介电条32远离集成电路36的侧面共面。
介电层34可以满足以下关系：y＝ax+b。其中，y是连接导线321覆 盖的介电层34在第二方向Y的长度；x是连接导线321的排序，其取值为自然数，例如，第二左连接导线322z和第二右连接导线322y对应的取值为0，第三左连接导线323z和第三右连接导线323y对应的取值为1，第四左连接导线321和第四右连接导线321对应的取值为2，依次类推直至最中间的一根连接导线321；b为第一左介电条331z的长度或第一右介电条331y的长度。a是直线斜率，即相邻两根连接导线321覆盖的介电层34在第一方向X的长度之差与相邻两根连接导线321之间的间距的比值。
介电层34的介电常数随着覆晶薄膜30的最小目标补偿电容的增加而增加，和/或，介电层34的在第二方向Y的长度随着覆晶薄膜30的最小目标补偿电容的增加而增加。即覆晶薄膜30的最小目标补偿电容增加的情况下，可以通过增加介电层34的介电常数，也可以通过增加介电层34的在第二方向Y的长度来达到；还可以在增加介电层34的介电常数的同时，增加介电层34的在第二方向Y的长度。
例如，在覆晶薄膜30的最小目标补偿电容是原电容的5倍以上时，介电层34和介电条33的介电常可以大于等于60；介电层34的厚度与介电条33的厚度之和大于等于10微米。在覆晶薄膜30的最小目标补偿电容是原电容的2倍以上时，介电层34和介电条33的介电常可以大于等于30，介电层34的厚度与介电条33的厚度之和大于等于10微米。
在本示例实施方式中，参照图10所示，图中虚线主要为了区分介电层34和介电条33，介电层34和介电条33可以通过同一次构图工艺形成，使得介电层34的介电常数与介电条33的介电常数相同，介电层34与多根介电条33连接为一体。介电层34和介电条33的材质可以是TiO2，还可以是其他介电常数较大的材料。
当然，在本公开的其他一些示例实施方式中，介电层34也可以不覆盖第二左连接导线322z和第二右连接导线322y，使得多根介电条33在基底层31上的正投影的最外侧边沿线与介电层34在基底层31上的正投影的边沿线重合。可以在形成介电条33之后在形成介电层34，介电层34还可以覆盖更长的连接导线321，使得介电层34在基底层31上的正投影覆盖且大于多根介电条33在基底层31上的正投影。
在本示例实施方式中，对称轴L没有贯穿连接导线321，而是在对称轴L两侧设置有两根与对称轴L相邻的连接导线321，与对称轴L相邻的两根连接导线321被介电层34完全覆盖，且与对称轴L相邻的两根连接导线321之间的介电条33在第二方向Y的长度等于连接导线321在第二方向Y的长度，即与对称轴L相邻的两根连接导线321之间的间隙322被介电条33填满。如此设置，方便设计时的计算、画图；而且方便后续制备工艺的简单化。
当然，在本公开的其他一些示例实施方式中，对称轴L可能贯穿一条连接导线321，那么，被对称轴L贯穿的连接导线321可以被介电层34完全覆盖，且与对称轴L相邻的两根介电条33在第二方向Y的长度等于连接导线321在第二方向Y的长度。
经过多次试验，实验条件为：100微米长的两根连接321，连接导线321的宽度大约为13微米，相邻两根连接导线321之间的间隙322的宽度大约为12微米；在没有设置介电条33和介电层34的情况下(即仅设置有底基层31和保护层35)，两根连接导线321之间的电容大约为11.6fF；在设置有介电条33和介电层34的情况下，两根连接导线321之间的电容大约为66.2fF。设置介电条33和介电层34后两根连接导线321之间的电容增大至原来的大约6倍，因此，可以增加补偿电容到pF量级，可以实现对数据线153的电容补偿。
在介电层34的远离基底层31的一侧设置有保护层35，保护层35的具体结构上述已经进行了详细说明，因此，此处不再赘述。
基于同一发明构思，本公开示例实施方式提供了一种显示装置，该显示装置可以包括显示面板、覆晶薄膜30以及电路板；显示面板可以包括多根数据线153；覆晶薄膜30为上述任意一项所述的覆晶薄膜30，连接于显示面板与电路板之间，连接导线321连接于数据线153。覆晶薄膜30的具体结构上述已经进行了详细说明，因此，此处不再赘述。
显示面板的具体结构以及显示面板与覆晶薄膜30的连接关系上述也已经进行了详细说明，因此，此处不再赘述。
而该显示装置的具体类型不受特别的限制，本领域常用的显示装置类型均可，具体例如手机等移动装置、手表等可穿戴设备、VR装置等 等，本领域技术人员可根据该显示设备的具体用途进行相应地选择，在此不再赘述。
需要说明的是，该显示装置还可以包括其他必要的部件和组成，以电脑显示器为例，具体例如外壳、电路板、电源线，等等，本领域技术人员可根据该显示装置的具体使用要求进行相应地补充，在此不再赘述。
与现有技术相比，本发明示例实施方式提供的显示装置的有益效果与上述示例实施方式提供的覆晶薄膜30的有益效果相同，在此不做赘述。
本领域技术人员在考虑说明书及实践这里公开的发明后，将容易想到本公开的其它实施方案。本申请旨在涵盖本公开的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本公开的一般性原理并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本公开的真正范围和精神由所附的权利要求指出。

Claims (20)

  1. 一种覆晶薄膜，其中，包括：
    基底层；
    导体层，设于所述基底层的一侧，所述导体层包括多根沿第一方向排列的连接导线，相邻两根所述连接导线之间设置有间隙；
    多根介电条，至少部分所述间隙内设有所述介电条，且所述介电条的在第二方向长度小于或等于所述间隙在所述第二方向的长度，所述第二方向与所述第一方向相交；
    保护层，设于所述导体层和所述介电条远离所述基底层的一侧，所述介电条的介电常数大于所述保护层的介电常数。
  2. 根据权利要求1所述的覆晶薄膜，其中，多根所述连接导线轴对称设置，多根所述介电条轴对称设置，对称轴为所述基底层沿所述第二方向延伸的中心轴。
  3. 根据权利要求2所述的覆晶薄膜，其中，多根所述介电条在第二方向的长度随着所述介电条与所述对称轴的距离的增加而减小。
  4. 根据权利要求1所述的覆晶薄膜，其中，多根所述介电条的一端平齐。
  5. 根据权利要求1所述的覆晶薄膜，其中，所述介电条在第三方向的高度与所述连接导线在第三方向的高度相同，所述第三方向与所述基底层靠近所述导体层的一面垂直，所述覆晶薄膜还包括：
    介电层，设于所述导体层与所述保护层之间，所述保护层在所述基底层上的正投影覆盖且大于所述介电层在所述基底层上的正投影，所述介电层在所述基底层上的正投影覆盖所述介电条在所述基底层上的正投影，所述介电层的介电常数大于所述保护层的介电常数。
  6. 根据权利要求5所述的覆晶薄膜，其中，所述介电层的介电常数与所述介电条的介电常数相同，所述介电层与多根所述介电条连接为一体。
  7. 根据权利要求6所述的覆晶薄膜，其中，多根所述介电条在所述基底层上的正投影的最外侧边沿线与所述介电层在所述基底层上的正投影的边沿线重合。
  8. 根据权利要求5所述的覆晶薄膜，其中，所述覆晶薄膜还包括：
    集成电路，设于所述保护层远离所述基底层的一侧，且与所述导体层电连接；
    第一绑定引脚，设于所述集成电路的一侧，且用于连接输出信号端；
    第二绑定引脚，设于所述集成电路远离所述第一绑定引脚的一侧，且用于连接输入信号端。
  9. 根据权利要求8所述的覆晶薄膜，其中，所述介电条和所述介电层设于所述集成电路靠近所述第一绑定引脚的一侧。
  10. 根据权利要求9所述的覆晶薄膜，其中，多根所述连接导线轴对称设置，所述介电层轴对称设置，多根所述介电条轴对称设置，对称轴为所述集成电路沿所述第二方向延伸的中心轴。
  11. 根据权利要求10所述的覆晶薄膜，其中，所述介电层在第二方向的长度随着所述介电层与所述对称轴的距离的增加而减小。
  12. 根据权利要求11所述的覆晶薄膜，其中，多根所述介电条的靠近所述集成电路的一端平齐，所述介电层的靠近所述集成电路的侧面与多根所述介电条的靠近所述集成电路的一端面共面，所述介电层的远离所述集成电路的侧面与第一方向相交。
  13. 根据权利要求10所述的覆晶薄膜，其中，所述介电层未覆盖位于最外侧的所述连接导线，在最外侧的所述连接导线与其相邻的所述连接导线之间的间隙内没有设置介电条。
  14. 根据权利要求10所述的覆晶薄膜，其中，与所述对称轴相邻的两根所述连接导线被所述介电层完全覆盖，且与所述对称轴相邻的两根所述连接导线之间的介电条在第二方向的长度等于所述连接导线在第二方向的长度；或，被所述对称轴贯穿的所述连接导线被所述介电层完全覆盖，且与所述对称轴相邻的两根所述介电条在第二方向的长度等于所述连接导线在第二方向的长度。
  15. 根据权利要求5所述的覆晶薄膜，其中，所述介电层和所述介电条的介电常数随着所述覆晶薄膜的最小目标补偿电容的增加而增加，和/或，所述介电层和所述介电条的在第二方向的长度随着所述覆晶薄膜的最小目标补偿电容的增加而增加。
  16. 根据权利要求15所述的覆晶薄膜，其中，所述覆晶薄膜的所述最小目标补偿电容大于等于原电容的5倍时，所述介电层和所述介电条的介电常数大于等于60，所述介电层的厚度与所述介电条的厚度之和大于等于10微米；或，所述覆晶薄膜的所述最小目标补偿电容大于等于原电容的2倍时，所述介电层和所述介电条的介电常数大于等于30，所述介电层的厚度与所述介电条的厚度之和大于等于10微米。
  17. 根据权利要求5所述的覆晶薄膜，其中，所述介电条和所述介电层的材料包括TiO2。
  18. 一种显示装置，其中，包括：
    显示面板，包括多根数据线；
    电路板；
    覆晶薄膜，为权利要求1～17任意一项所述的覆晶薄膜，连接于所述显示面板与所述电路板之间，连接导线连接于所述数据线。
  19. 根据权利要求18所述的显示装置，其中，多根所述介电条在所述第二方向的长度随着所述数据线的长度的减小而增加，所述数据线与位于所述介电条的同一侧的所述连接导线连接。
  20. 根据权利要求18所述的显示装置，其中，所述覆晶薄膜为权利要求5～17任意一项所述的覆晶薄膜，所述介电层在第二方向的长度随着其覆盖的所述连接导线连接的所述数据线的长度的减小而增加。
PCT/CN2022/089641 2022-04-27 2022-04-27 覆晶薄膜及显示装置 WO2023206159A1 (zh)

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101777524A (zh) * 2009-01-14 2010-07-14 瑞鼎科技股份有限公司 芯片封装结构以及导线架构
CN103269563A (zh) * 2013-04-27 2013-08-28 合肥京东方光电科技有限公司 覆晶薄膜柔性电路板及显示装置
CN113589893A (zh) * 2021-07-28 2021-11-02 Tcl华星光电技术有限公司 覆晶薄膜以及显示装置

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101777524A (zh) * 2009-01-14 2010-07-14 瑞鼎科技股份有限公司 芯片封装结构以及导线架构
CN103269563A (zh) * 2013-04-27 2013-08-28 合肥京东方光电科技有限公司 覆晶薄膜柔性电路板及显示装置
CN113589893A (zh) * 2021-07-28 2021-11-02 Tcl华星光电技术有限公司 覆晶薄膜以及显示装置

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