WO2023195174A1 - 配線基板及びその製造方法、並びに半導体装置 - Google Patents

配線基板及びその製造方法、並びに半導体装置 Download PDF

Info

Publication number
WO2023195174A1
WO2023195174A1 PCT/JP2022/017402 JP2022017402W WO2023195174A1 WO 2023195174 A1 WO2023195174 A1 WO 2023195174A1 JP 2022017402 W JP2022017402 W JP 2022017402W WO 2023195174 A1 WO2023195174 A1 WO 2023195174A1
Authority
WO
WIPO (PCT)
Prior art keywords
wiring
wiring board
layer
insulating resin
electrode pad
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2022/017402
Other languages
English (en)
French (fr)
Japanese (ja)
Inventor
寿枝 平野
正也 鳥羽
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Resonac Corp
Original Assignee
Resonac Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Resonac Corp filed Critical Resonac Corp
Priority to JP2024514137A priority Critical patent/JPWO2023195174A1/ja
Priority to PCT/JP2022/017402 priority patent/WO2023195174A1/ja
Priority to CN202280094498.5A priority patent/CN118975415A/zh
Publication of WO2023195174A1 publication Critical patent/WO2023195174A1/ja
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistors
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits by soldering

Definitions

  • the present disclosure relates to a wiring board, a connection method thereof, and a semiconductor device.
  • One aspect of the present disclosure relates to suppressing the occurrence of defects in the insulating resin layer due to temperature changes with respect to a wiring board having an electrode pad exposed within an opening in the insulating resin layer.
  • One aspect of the present disclosure relates to a wiring board that includes a wiring section including a wiring layer, and an electrode pad provided on the wiring section and connected to the wiring layer.
  • a connection surface of the electrode pad opposite to the wiring portion has an arithmetic mean roughness Ra of 0.5 ⁇ m or more and 2.0 ⁇ m or less.
  • Another aspect of the present disclosure relates to a semiconductor device including the wiring board and a semiconductor chip mounted on the wiring board.
  • Yet another aspect of the present disclosure is to prepare a wiring structure including a wiring part including a wiring layer, and an electrode pad provided on the wiring part;
  • the present invention relates to a method for manufacturing a wiring board, including processing a connection surface, which is a side surface, to have an arithmetic mean roughness Ra of 0.5 ⁇ m or more and 2.0 ⁇ m or less.
  • FIG. 3 is a process diagram showing an example of a method for manufacturing a wiring board.
  • FIG. 3 is a process diagram showing an example of a method for manufacturing a wiring board.
  • FIG. 1 is a cross-sectional view showing an example of a semiconductor device.
  • the present invention is not limited to the following examples. In the following description, the same or corresponding parts are given the same reference numerals, and overlapping description may be omitted.
  • the vertical, horizontal, etc. positional relationships are based on the positional relationships shown in the drawings unless otherwise specified.
  • the dimensional ratios in the drawings are not limited to the ratios shown. Terms such as “left”, “right”, “front”, “back”, “top”, “bottom”, “above”, “bottom”, etc. do not necessarily imply that their relative positions do not change.
  • the term “layer” includes a structure formed on the entire surface as well as a structure formed on a part of the layer when observed in a plan view.
  • FIGS. 1 and 2 are process diagrams showing an example of a method for manufacturing a wiring board.
  • the method shown in FIGS. 1 and 2 includes a base material 1, a wiring part 3 provided on the base material 1, and an electrode pad 5 provided on the surface of the wiring part 3 opposite to the base material 1.
  • a wiring board 10 (wiring structure) is prepared, and a connection surface 5S of the electrode pad 5 opposite to the wiring portion 3 has an arithmetic mean roughness of 0.5 ⁇ m or more and 2.0 ⁇ m or less.
  • the method may include processing to obtain a surface having Ra.
  • a wiring board before a connection surface is processed may be referred to as a wiring structure.
  • Preparing the wiring board 10 involves forming the wiring part 3 including an insulating resin layer and a wiring layer on the main surface of the base material 1, and forming the wiring part 3 on the opposite side of the base material 1 of the wiring part 3. This includes forming electrode pads 5.
  • the base material 1 may be, for example, a silicon substrate, a glass substrate, a stainless steel substrate, or a glass cloth, or may be a semiconductor package having a semiconductor chip and a sealing resin layer for sealing the semiconductor chip.
  • the thickness of the base material 1 may be, for example, 0.2 mm or more and 2.0 mm or less.
  • a base material having a thickness of 0.2 mm or more tends to have good handling properties.
  • Substrates having a thickness of 2.0 mm or less are often advantageous in terms of manufacturing costs.
  • the substrate 1 may be a wafer with a circular main surface or a panel with a rectangular main surface.
  • the base material 1 may be a wafer having a circular main surface having a diameter of 200 mm or more and 450 mm or less, or a panel having a rectangular main surface having a width of 300 mm or more and 700 mm or less.
  • the wiring portion 3 can be formed by a method including forming an insulating resin layer and a wiring layer provided within the insulating resin layer by a normal method.
  • the wiring section 3 may have a multilayer wiring structure including two or more wiring layers.
  • the electrode pad 5 is formed by, for example, forming a seed layer on the surface of the wiring part 3 opposite to the base material 1, and forming a resist layer 4 on the seed layer, which has an opening 4a through which a part of the seed layer is exposed. forming an electrode pad 5 including an electrolytic plated layer filling the opening 4a, removing the resist layer 4, and removing a portion of the seed layer that is not covered by the electrolytic plated layer. It can include.
  • the method for forming the seed layer may include cleaning the surface of the wiring section 3 with a pretreatment liquid and adsorbing a palladium catalyst onto the surface of the wiring section 3.
  • the seed layer may be formed by sputtering.
  • the seed layer can be a metal layer containing metal species such as copper or titanium.
  • the thickness of the seed layer may be 20 nm or more and 200 nm or less, 40 nm or more and 200 nm or less, or 60 nm or more and 200 nm or less.
  • the electrode pad 5 may be a copper pad containing copper.
  • the thickness of the electrode pad 5 may be 1 ⁇ m or more and 20 ⁇ m or less, 3 ⁇ m or more and 15 ⁇ m or less, or 5 ⁇ m or more and 15 ⁇ m or less.
  • connection surface 5S of the electrode pad 5 or the opening 4a for forming this may be circular or elliptical.
  • the maximum width of the electrode pad 5 (connection surface 5S) and the opening 4a may be 5 ⁇ m or more, or 20 ⁇ m or more, or 400 ⁇ m or less, or 300 ⁇ m or less, or 10 ⁇ m or less.
  • the electrode pad 5 (connection surface 5S) and the opening 4a may have an area corresponding to the area of a circle having a diameter of 5 ⁇ m or more and 400 ⁇ m or less, or 5 ⁇ m or more and 10 ⁇ m or less.
  • connection surface 5S of the prepared wiring board 10 is treated so as to have an arithmetic mean roughness Ra of 0.5 ⁇ m or more and 2.0 ⁇ m or less.
  • a large arithmetic mean roughness Ra is advantageous in terms of improving adhesion due to the anchor effect, but according to the findings of the present inventors, when the arithmetic mean roughness Ra exceeds 2.0 ⁇ m, the connection surface Defects such as cracks are likely to occur in the insulating resin layer (particularly the surface insulating resin layer 7 described below) in contact with the 5S.
  • Arithmetic mean roughness Ra can be measured by a method according to JIS B0601-1994.
  • the connecting surface 5S before being processed has an arithmetic mean roughness Ra of less than 0.5 ⁇ m
  • the connecting surface 5S is roughened so that the arithmetic mean roughness Ra is 0.5 ⁇ m or more and 2.0 ⁇ m or less.
  • the connecting surface 5S before being processed has an arithmetic mean roughness Ra exceeding 2.0 ⁇ m
  • the connecting surface 5S is smoothed so that the arithmetic mean roughness Ra is 0.5 ⁇ m or more and 2.0 ⁇ m or less.
  • the roughening treatment and the smoothing treatment may include bringing the connection surface 5S into contact with a treatment liquid.
  • the treatment liquid for roughening treatment may be, for example, an acidic aqueous solution.
  • the acidic aqueous solution may include an organic or inorganic acid, a source of cupric ions, a source of halide ions, and a polymer.
  • the organic acid may be, for example, formic acid, acetic acid, propionic acid, butyric acid or a combination thereof.
  • the inorganic acid may be, for example, sulfuric acid, hydrochloric acid or a combination thereof.
  • the halide may be, for example, hydrochloric acid, hydrobromic acid, sodium chloride, potassium chloride, calcium chloride, potassium bromide or combinations thereof.
  • the cupric ion source may be, for example, cupric chloride, cupric bromide, cupric hydroxide, cupric oxide, or combinations thereof.
  • the polymer may have polyamine chains or cationic groups (eg quaternary ammonium groups).
  • the treatment liquid for smoothing treatment includes, for example, a treatment liquid containing an imidazole compound and a sugar alcohol, an aromatic compound having an amino group and an aromatic ring, a polybasic acid, and a halide ion or an oxidizing agent (hypochlorous acid, Processing liquids containing chlorous acid, chloric acid, perchloric acid, persulfuric acid, percarbonic acid, hydrogen peroxide, organic peroxides, etc.); processing liquids containing aromatic compounds having amino groups and aromatic rings; and thio compounds. , and a treatment liquid containing a silane coupling agent, a metal ion, and a halide ion.
  • the number of convex portions having a height exceeding 3 ⁇ m may be 5 or less per 15 ⁇ m of the in-plane length of the connection surface 5S. Relatively large protrusions with a height of more than 3 ⁇ m can become a starting point for defects such as cracks in the surface insulating resin layer.
  • the height of the convex portion is the height based on the deeper one of the bottoms of the concave portions on both sides of the convex portion, when the unevenness of the connecting surface 5S is measured along the in-plane direction of the connecting surface 5S.
  • the number of convex portions having a height exceeding 3 ⁇ m may be 4 or less, 3 or less, 2 or less, or 1 or less per 15 ⁇ m of the in-plane length of the connection surface 5S.
  • a surface insulating resin layer 7 is formed on the surface of the wiring portion 3 opposite to the base material 1, and has an opening 7a through which the central portion of the electrode pad 5 is exposed.
  • the surface insulating resin layer 7 is formed so as to be in contact with the peripheral edge of the connection surface 5S.
  • the thickness of the portion of the surface insulating resin layer 7 that is in contact with the wiring portion 3 may be 15 ⁇ m or more and 30 ⁇ m or less.
  • the surface insulating resin layer 7 can be formed of, for example, a resist material commonly used to form a solder resist.
  • the opening 7a can be formed, for example, by laser ablation, photolithography (exposure and development), or imprinting.
  • the material for forming the surface insulating resin layer 7 may be a thermosetting or photocuring resist material. In the case of photolithography, a photocurable resist material is used.
  • the thermosetting resist material may include a thermosetting resin that is cured by heating to form a cured product exhibiting electrical insulation properties.
  • thermosetting resins include epoxy resins, phenol resins, triazine ring-containing resins, unsaturated polyester resins, bismaleimide resins, diallyl phthalate resins, silicone resins, benzoxazine ring-containing resins, norbornene resins, cyanate resins, and isocyanates. It may be a resin, a urethane resin, a benzocyclobutene resin, a maleimide resin, a bismaleimide triazine resin, a polyazomethine resin, a thermosetting polyimide, or a combination thereof.
  • epoxy resins include bisphenol A epoxy resin, bisphenol F epoxy resin, bisphenol S epoxy resin, bisphenol E epoxy resin, bisphenol M epoxy resin, bisphenol P epoxy resin, and bisphenol Z epoxy resin.
  • Bisphenol-type epoxy resins, bisphenol A novolac-type epoxy resins, phenol novolac-type epoxy resins, and novolak-type epoxy resins such as cresol novolak epoxy resins, biphenyl-type epoxy resins, biphenylaralkyl-type epoxy resins, arylalkylene-type epoxy resins, tetraphenylene Roll ethane epoxy resin, naphthalene epoxy resin, anthracene epoxy resin, phenoxy epoxy resin, dicyclopentadiene epoxy resin, norbornene epoxy resin, adamantane epoxy resin, fluorene epoxy resin, glycidyl methacrylate copolymer epoxy Resin, copolymer of cyclohexylmaleimide and glycidyl methacrylate, epoxy-mod
  • phenolic resins include novolac-type phenolic resins such as phenol novolac resins, cresol novolac resins, and bisphenol A novolac resins, unmodified resol phenolic resins, and oil-modified resols modified with tung oil, linseed oil, walnut oil, etc.
  • examples include resol type phenolic resins such as phenolic resins.
  • triazine ring-containing resins include urea resins and melamine resins.
  • the photocurable resist material may include, for example, a photocurable resin that is an epoxy resin (such as an alicyclic epoxy resin), an oxetane compound, a vinyl ether compound, or a combination thereof.
  • a photocurable resin that is an epoxy resin (such as an alicyclic epoxy resin), an oxetane compound, a vinyl ether compound, or a combination thereof.
  • cycloaliphatic epoxy resins include 3,4,3',4'-diepoxybicyclohexyl, 2,2-bis(3,4-epoxycyclohexyl)propane, 2,2-bis(3,4- epoxycyclohexyl)-1,3-hexafluoropropane, bis(3,4-epoxycyclohexyl)methane, 1-[1,1-bis(3,4-epoxycyclohexyl)]ethylbenzene, bis(3,4-epoxycyclohexyl) ) adipate
  • the material for forming the surface insulating resin layer 7 may include a thermoplastic resin.
  • the thermoplastic resin can be a commodity plastic, an engineering plastic, a thermoplastic elastomer, or a combination thereof.
  • general-purpose plastics include acrylic resin, modified acrylic resin, low-density polyethylene, high-density polyethylene, ethylene-vinyl acetate copolymer, polyethylene terephthalate, polypropylene, modified polypropylene, polystyrene, acrylonitrile-butadiene-styrene copolymer, and acrylonitrile.
  • - Styrene copolymers cellulose acetate, polyvinyl alcohol, polyvinyl chloride, polyvinylidene chloride, and polylactic acid.
  • Engineering examples include polyamide, thermoplastic polyurethane, polyacetal, polycarbonate, ultra-high molecular weight polyethylene, polybutylene terephthalate, modified polyphenylene ether, polysulfone, polyphenylene sulfide, polyether sulfone, polyether ether ketone, polyarylate, polyetherimide. , polyamideimide, liquid crystal polymer, polyamide 6T, polyamide 9T, polytetrafluoroethylene, polyvinylidene fluoride, polyesterimide, and thermoplastic polyimide.
  • thermoplastic elastomers examples include olefin thermoplastic elastomers, styrene thermoplastic elastomers, polyester thermoplastic elastomers, urethane thermoplastic elastomers, amide thermoplastic elastomers, vinyl chloride thermoplastic elastomers, and hydrogenated thermoplastic elastomers.
  • thermoplastic elastomers include olefin thermoplastic elastomers, styrene thermoplastic elastomers, polyester thermoplastic elastomers, urethane thermoplastic elastomers, amide thermoplastic elastomers, vinyl chloride thermoplastic elastomers, and hydrogenated thermoplastic elastomers.
  • plastic elastomers examples include plastic elastomers.
  • the material for forming the surface insulating resin layer 7 may include an inorganic filler.
  • the inorganic filler can contribute to improving the reliability and rigidity of the surface insulating resin layer 7.
  • the inorganic filler can be, for example, silica, barium sulfate, barium titanate, talc, clay, calcined kaolin, magnesium carbonate, calcium carbonate, aluminum oxide, aluminum hydroxide, mica powder, or combinations thereof.
  • FIG. 3 is a cross-sectional view showing an example of a semiconductor device.
  • a semiconductor device 100 shown in FIG. 3 is provided between a wiring board 10, a semiconductor chip 20 mounted on the wiring board 10, and an electrode pad 5 of the semiconductor chip 20 and the wiring board 10 to electrically connect them. It includes connecting solder bumps 25 and an insulating resin layer 30 (adhesive layer) filled between the semiconductor chip 20 and the wiring board 10.
  • a semiconductor device may include an interposer including a fine wiring layer for mounting different types of semiconductor chips together.
  • the interval between pins provided on a semiconductor chip may be 200 ⁇ m or less, 100 ⁇ m or less, or 30 ⁇ m or more.
  • the number of pins provided on the semiconductor chip may be 500 or more, 1000 or more, or 10000 or less.
  • the present invention is not limited to the following examples.
  • a wiring board was prepared that had a copper pad having a connection surface (width 260 ⁇ m) with an arithmetic mean roughness Ra of 0.03 ⁇ m and a surface insulating resin layer (solder resist) having an opening through which the copper pad was exposed.
  • the connection surface of the copper pad was roughened using a roughening treatment solution to form a surface having an arithmetic mean roughness Ra of 0.5 ⁇ m, 1.0 ⁇ m, 2.0 ⁇ m, 3.0 ⁇ m, or 5.0 ⁇ m.
  • the arithmetic mean roughness Ra was measured using a laser microscope (OLS4100, manufactured by Olympus Corporation).
  • a semiconductor chip was mounted on a wiring board using a nitrogen reflow oven so as to be connected to the processed connection surface via solder bumps.
  • the temperature of the nitrogen reflow oven was set at 260°C.
  • an insulating resin layer was filled between the semiconductor chip and the wiring board, and this was thermally cured.
  • the formed semiconductor device was placed in a temperature cycle tester and heat-treated for 400 cycles at a temperature of 165° C. on the high temperature side, -65° C. on the low temperature side, and a holding time of 15 minutes.
  • the cross section of the surface insulating resin layer near the copper pad of the heat-treated semiconductor device was observed to confirm the presence or absence of cracks.
  • the results are shown in Table 1. It was confirmed that by forming a connection surface having an Ra of 0.5 ⁇ m or more and 2.0 ⁇ m or less, the occurrence of cracks in the surface insulating resin layer was effectively suppressed. When Ra was 0.03 ⁇ m, interfacial peeling was observed between the connection surface and the surface insulating resin layer, suggesting insufficient adhesion.

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Wire Bonding (AREA)
  • Manufacturing Of Printed Wiring (AREA)
PCT/JP2022/017402 2022-04-08 2022-04-08 配線基板及びその製造方法、並びに半導体装置 Ceased WO2023195174A1 (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2024514137A JPWO2023195174A1 (https=) 2022-04-08 2022-04-08
PCT/JP2022/017402 WO2023195174A1 (ja) 2022-04-08 2022-04-08 配線基板及びその製造方法、並びに半導体装置
CN202280094498.5A CN118975415A (zh) 2022-04-08 2022-04-08 配线基板及其制造方法以及半导体装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2022/017402 WO2023195174A1 (ja) 2022-04-08 2022-04-08 配線基板及びその製造方法、並びに半導体装置

Publications (1)

Publication Number Publication Date
WO2023195174A1 true WO2023195174A1 (ja) 2023-10-12

Family

ID=88242598

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2022/017402 Ceased WO2023195174A1 (ja) 2022-04-08 2022-04-08 配線基板及びその製造方法、並びに半導体装置

Country Status (3)

Country Link
JP (1) JPWO2023195174A1 (https=)
CN (1) CN118975415A (https=)
WO (1) WO2023195174A1 (https=)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008244000A (ja) * 2007-03-26 2008-10-09 Ngk Spark Plug Co Ltd 配線基板の製造方法
JP2011181629A (ja) * 2010-02-26 2011-09-15 Kyocer Slc Technologies Corp 配線基板およびその製造方法
JP2012209418A (ja) * 2011-03-30 2012-10-25 Kyocer Slc Technologies Corp 配線基板およびその製造方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008244000A (ja) * 2007-03-26 2008-10-09 Ngk Spark Plug Co Ltd 配線基板の製造方法
JP2011181629A (ja) * 2010-02-26 2011-09-15 Kyocer Slc Technologies Corp 配線基板およびその製造方法
JP2012209418A (ja) * 2011-03-30 2012-10-25 Kyocer Slc Technologies Corp 配線基板およびその製造方法

Also Published As

Publication number Publication date
CN118975415A (zh) 2024-11-15
JPWO2023195174A1 (https=) 2023-10-12

Similar Documents

Publication Publication Date Title
JP6217165B2 (ja) プライマー層付きプリプレグ、プライマー層付き金属箔、金属張積層板、プリント配線基板、半導体パッケージおよび半導体装置
CN101652401B (zh) 环氧树脂组合物、预浸料坯、层叠板、多层印刷线路板、半导体器件、绝缘树脂片、和制造多层印刷线路板的方法
KR101195408B1 (ko) 반도체 장치
KR102293385B1 (ko) 프린트 배선판의 절연층용 수지 조성물
WO2018003590A1 (ja) 熱硬化性樹脂組成物、キャリア付樹脂膜、プリント配線基板および半導体装置
KR20190020622A (ko) 수지 조성물
TWI752246B (zh) 樹脂組成物
TW201812939A (zh) 半導體裝置的製造方法
JP6425062B2 (ja) 絶縁樹脂シート、並びにそれを用いた回路基板および半導体パッケージ
JP2020136542A (ja) プリント配線板の製造方法
WO2023195174A1 (ja) 配線基板及びその製造方法、並びに半導体装置
TWI906389B (zh) 樹脂組成物，及印刷配線板之製造方法
JP2020128046A (ja) プリプレグ、プリント配線基板、及び、半導体装置
WO2018088345A1 (ja) 金属箔付き樹脂膜、構造体、配線基板の製造方法、半導体装置の製造方法
JP6439315B2 (ja) 粗化硬化体
CN109423012B (zh) 树脂组合物
TWI898077B (zh) 電路基板之製造方法
JP6217870B2 (ja) 構造体、配線基板および配線基板の製造方法
JP5233066B2 (ja) 電子材料用接着剤シート
KR20240136339A (ko) 회로 기판의 제조방법 및 이에 사용하는 수지 시트
JP2019121793A (ja) ソルダーレジスト樹脂組成物、樹脂シート、梱包体及び回路基板
JP2015176894A (ja) 積層板の製造方法、プリント配線基板の製造方法、絶縁層付きプラスチックフィルム、積層板、プリント配線基板および半導体装置
KR20160150032A (ko) 빌드업재, 적층판, 프린트 배선 기판 및 반도체 장치와 적층판의 제조 방법
JP7409558B2 (ja) 回路基板の製造方法
JP7816223B2 (ja) 回路基板の製造方法

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 22936571

Country of ref document: EP

Kind code of ref document: A1

WWE Wipo information: entry into national phase

Ref document number: 202280094498.5

Country of ref document: CN

WWE Wipo information: entry into national phase

Ref document number: 2024514137

Country of ref document: JP

WWE Wipo information: entry into national phase

Ref document number: 18854547

Country of ref document: US

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 22936571

Country of ref document: EP

Kind code of ref document: A1