WO2023193515A1 - 芯片及其制备方法、终端 - Google Patents

芯片及其制备方法、终端 Download PDF

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Publication number
WO2023193515A1
WO2023193515A1 PCT/CN2023/074804 CN2023074804W WO2023193515A1 WO 2023193515 A1 WO2023193515 A1 WO 2023193515A1 CN 2023074804 W CN2023074804 W CN 2023074804W WO 2023193515 A1 WO2023193515 A1 WO 2023193515A1
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Prior art keywords
spacer layer
dummy gate
electrode
layer
source electrode
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PCT/CN2023/074804
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English (en)
French (fr)
Inventor
万光星
高健
陈尚志
刘燕翔
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华为技术有限公司
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Publication of WO2023193515A1 publication Critical patent/WO2023193515A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823468—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/0886—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K10/00—Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having potential barriers
    • H10K10/40—Organic transistors
    • H10K10/46—Field-effect transistors, e.g. organic thin-film transistors [OTFT]

Definitions

  • the present application relates to the field of semiconductor technology, and in particular, to a chip and its preparation method and terminal.
  • Fin field-effect transistor is a new type of transistor.
  • the performance of FinFET is related to the parasitic capacitance generated in the middle end of line (MEOL) of the integrated circuit. The smaller the parasitic capacitance generated by the middle end of line, the better the performance of FinFET.
  • Fringe parasitic capacitance refers to the parasitic capacitance between the gate, source and drain of FinFET. It is the main component of the parasitic capacitance generated in the middle process. Therefore, how to reduce edge parasitic capacitance is an issue that needs to be solved urgently.
  • This application provides a chip, a preparation method thereof, and a terminal, which can reduce the edge parasitic capacitance by reducing the comprehensive dielectric constant of the first spacer layer and the second spacer layer to improve the performance of FinFET.
  • the present application provides a method of manufacturing a chip.
  • the chip includes a fin field effect transistor.
  • the method of manufacturing a fin field effect transistor includes: sequentially forming a dummy gate and a first spacer layer on a substrate; A spacer layer is disposed on opposite sides of the dummy gate. Next, a source electrode and a drain electrode are formed; along the direction of the first spacer layer toward the dummy gate electrode, the source electrode and the drain electrode are arranged on opposite sides of the channel region of the fin field effect transistor.
  • a second spacer layer is formed on the side of the first spacer layer away from the dummy gate; the dielectric constant of the second spacer layer is smaller than the dielectric constant of the first spacer layer.
  • remove the dummy gate is performed by sequentially forming a dummy gate and a first spacer layer on a substrate; A spacer layer is disposed on opposite sides of the dummy gate. Next, a source electrode and a drain electrode are formed; along the direction of the first space
  • edge parasitic capacitance is the parasitic capacitance between the gate and the source and drain.
  • the dummy gate electrode is arranged at the same position as the gate electrode to be formed, the source electrode is used to form the source electrode, and the drain electrode is used to form the drain electrode. Therefore, the structure between the false gate, the source and the drain is related to the parasitic capacitance between the gate, the source and the drain.
  • a first spacer layer and a second spacer layer are provided between the dummy gate electrode, the source electrode and the drain electrode, and the dielectric constant of the second spacer layer is smaller than the dielectric constant of the first spacer layer, thereby reducing the false The average dielectric constant of the structure between the gate and source and drain to reduce edge parasitic capacitance and improve FinFET AC performance.
  • the second spacer layer since this application forms the second spacer layer after the source and drain are formed, the second spacer layer will not affect the distance from the source and drain to the channel region, and will not affect the DC current of the FinFET. parameter.
  • the preparation method of the fin field effect transistor further includes: removing part of the first spacer layer in a direction toward the dummy gate electrode. spacer layer. Since the FinFET of this application adds a second spacer layer, part of the first spacer layer can also be removed to avoid Avoid adding a second spacer layer to affect the overall size of the FinFET.
  • the edge of the second spacer layer away from the dummy gate may be flush with the edges of the source and drain electrodes facing the dummy gate.
  • the orthographic projection of the second spacer layer on the substrate can be aligned with the source and drain electrodes on the substrate.
  • the orthographic projections on the base are at least partially coincident.
  • the method further includes: forming a contact metal etching barrier layer on the side of the second spacer layer facing away from the dummy gate, and the contact metal etching barrier layer is located on the source and drain electrodes. On the side away from the substrate; the dielectric constant of the second spacer layer is smaller than the dielectric constant of the contact metal etching barrier layer.
  • the FinFET does not include a second spacer layer
  • the gate electrode to be formed forms a capacitor with the source electrode and drain electrode, a first spacer layer and a contact metal etching barrier layer are spaced between them.
  • the second spacer layer is provided between the contact metal etching barrier layer and the first spacer layer, the structure between the gate electrode, the source electrode, and the drain electrode to be formed is formed from the first spacer layer and the contact layer.
  • the metal etching barrier layer becomes a first spacer layer, a second spacer layer, and a partial contact metal etching barrier layer.
  • the dielectric constant of the second spacer layer is smaller than the dielectric constant of the contact metal etching barrier layer and the first spacer layer, the overall dielectric constant between the gate electrode to be formed, the source electrode and the drain electrode is reduced. , the edge parasitic capacitance between the gate to be formed and the source and drain is reduced.
  • the method of preparing the fin field effect transistor before forming the dummy gate and the first spacer layer on the substrate, the method of preparing the fin field effect transistor further includes: forming fins on the substrate. Afterwards, forming the source electrode and the drain electrode may include: using dry etching to etch parts of the fin located on opposite sides of the channel region to obtain a channel layer. Next, a source electrode and a drain electrode are formed at the etched positions in the channel layer. Since the source and drain are formed before the second spacer layer is formed, the second spacer layer will not affect the distance from the source and drain to the channel region, and thus will not affect the DC parameters of the FinFET.
  • the etching selectivity ratio between the first spacer layer and the dummy gate is greater than the etching selectivity ratio between the second spacer layer and the dummy gate; removing the dummy gate includes: using wet etching to The dummy gate is etched to remove the dummy gate. After removing the dummy gate, the method for preparing the fin field effect transistor further includes: forming a gate on the side of the first spacer layer away from the second spacer layer.
  • wet etching is used to remove the dummy gate and oxidation
  • wet etching is isotropic
  • the first spacer layer on the side causes damage. Therefore, a material with a larger etching selectivity ratio compared to the material of the dummy gate and the oxide layer can be selected as the material of the first spacer layer to avoid causing the first spacer layer when etching the first spacer layer of the dummy gate.
  • the layer is damaged by the etching liquid.
  • the first spacer layer can also better protect the second spacer layer.
  • the material of the first spacer layer includes SiOCN with a small dielectric constant
  • a special machine is required because the etching selectivity of SiOCN is relatively small compared to the etching selectivity of the dummy gate (the material may include polysilicon, for example). to protect the first spacer layer from being damaged by the etching liquid.
  • the etching selectivity ratio between the first spacer layer and the dummy gate is greater than the etching selectivity ratio between the second spacer layer and the dummy gate.
  • the material of the first spacer layer includes a material that has a greater affinity with the dummy gate.
  • the first spacer layer can be used to protect the second spacer layer. Function, no special machine is needed to protect the first spacer layer and the second spacer layer, saving preparation costs.
  • the dielectric constant of the second spacer layer is less than or equal to 5.5.
  • the first interval The material of the layer includes at least one of silicon nitride and silicon carbon nitride; the material of the second spacer layer includes at least one of silicon oxide and silicon oxycarbonitride.
  • inventions of the present application provide a chip.
  • the chip includes a fin field effect transistor.
  • the fin field effect transistor includes a gate, a first spacer layer, a second spacer layer, a source electrode and a drain electrode; a first spacer layer Disposed on opposite sides of the gate, the second spacer layer is provided on the opposite sides of the first spacer layer away from the gate; the dielectric constant of the second spacer layer is smaller than the dielectric constant of the first spacer layer; directed along the first spacer layer In the direction of the second spacer layer, the source electrode and the drain electrode are respectively arranged on opposite sides of the channel region of the fin field effect transistor.
  • the edge of the second spacer layer away from the dummy gate may be flush with the edges of the source and drain electrodes facing the dummy gate.
  • the orthographic projection of the second spacer layer on the substrate can be aligned with the source and drain electrodes on the substrate.
  • the orthographic projections on the base are at least partially coincident.
  • the fin field effect transistor further includes a contact metal etching barrier layer; the contact metal etching barrier layer is disposed on the side of the second spacer layer away from the gate, and the dielectric constant of the second spacer layer is smaller than the contact metal The dielectric constant of the etch barrier layer.
  • the FinFET does not include a second spacer layer
  • the gate electrode to be formed forms a capacitor with the source electrode and drain electrode, a first spacer layer and a contact metal etching barrier layer are spaced between them.
  • the second spacer layer is provided between the contact metal etching barrier layer and the first spacer layer, the structure between the gate electrode, the source electrode, and the drain electrode to be formed is formed from the first spacer layer and the contact layer.
  • the metal etching barrier layer becomes a first spacer layer, a second spacer layer, and a partial contact metal etching barrier layer.
  • the dielectric constant of the second spacer layer is smaller than the dielectric constant of the contact metal etching barrier layer and the first spacer layer, the overall dielectric constant between the gate electrode, the source electrode, and the drain electrode is reduced, and the dielectric constant to be formed is The edge parasitic capacitance between the gate and the source and drain is reduced.
  • the dielectric constant of the second spacer layer is less than or equal to 5.5.
  • the material of the first spacer layer includes at least one of silicon nitride and silicon carbon nitride; the material of the second spacer layer includes at least one of silicon oxide and silicon oxycarbonitride.
  • the present application provides a terminal, which includes a circuit board and the chip described in the second aspect, and the chip is disposed on the circuit board.
  • the third aspect and any implementation manner of the third aspect respectively correspond to the second aspect and any implementation manner of the second aspect.
  • the technical effects corresponding to the third aspect and any implementation manner of the third aspect please refer to the technical effects corresponding to the above-mentioned second aspect and any implementation manner of the second aspect, which will not be described again here.
  • Figure 1 is a connection diagram of various structures in the terminal provided by the embodiment of the present application.
  • Figure 2 is a top view of a chip provided by an embodiment of the present application.
  • Figure 3a is a schematic structural diagram of a FinFET provided by an embodiment of the present application.
  • Figure 3b is a schematic cross-sectional view along the A1-A2 direction in Figure 3a;
  • Figure 4 is a schematic flow chart of preparing FinFET provided by the embodiment of the present application.
  • FIG. 5a is a preparation process diagram of the fin provided by the embodiment of the present application.
  • Figure 5b is another preparation process diagram of the fin provided by the embodiment of the present application.
  • Figure 5c is another preparation process diagram of the fin provided by the embodiment of the present application.
  • Figure 5d is another preparation process diagram of the fin provided by the embodiment of the present application.
  • Figure 5e is another preparation process diagram of the fin provided by the embodiment of the present application.
  • Figure 5f is another preparation process diagram of the fin provided by the embodiment of the present application.
  • Figure 5g is another preparation process diagram of the fin provided by the embodiment of the present application.
  • Figure 5h is another preparation process diagram of the fin provided by the embodiment of the present application.
  • Figure 5i is another preparation process diagram of the fin provided by the embodiment of the present application.
  • Figure 5j is another preparation process diagram of the fin provided by the embodiment of the present application.
  • Figure 5k is another preparation process diagram of the fin provided by the embodiment of the present application.
  • Figure 6a is a diagram of the preparation process of the dummy gate provided by the embodiment of the present application.
  • Figure 6b is a diagram of the preparation process of the first spacer layer provided by the embodiment of the present application.
  • Figure 6c is a cross-sectional view along the A1-A2 direction in Figure 6b;
  • Figure 7a is a preparation process diagram of the source electrode and the drain electrode provided in the embodiment of the present application.
  • Figure 7b is another preparation process diagram of the source and drain electrodes provided in the embodiment of the present application.
  • Figure 7c is another preparation process diagram of the source electrode and the drain electrode provided by the embodiment of the present application.
  • Figure 7d is another preparation process diagram of the source electrode and the drain electrode provided by the embodiment of the present application.
  • Figure 8 is a preparation process diagram of the second spacer layer provided by the embodiment of the present application.
  • Figure 9 is a preparation process diagram of 18 provided by the embodiment of the present application.
  • Figure 10 is a preparation process diagram of 19 and the connecting electrode provided by the embodiment of the present application.
  • Figure 11a is a schematic diagram of removing a false gate provided by an embodiment of the present application.
  • Figure 11b is a preparation process diagram of a gate provided by an embodiment of the present application.
  • Figure 12 is another schematic flow diagram of preparing FinFET provided by the embodiment of the present application.
  • Figure 13 is a schematic diagram of removing part of the first spacer layer according to an embodiment of the present application.
  • Figure 14a is another preparation process diagram for forming a second spacer layer provided by an embodiment of the present application.
  • Figure 14b is another preparation process diagram for forming the second spacer layer provided by the embodiment of the present application.
  • Figure 15 is a preparation process diagram of 18 provided by the embodiment of the present application.
  • Figure 16 is a preparation process diagram of 19 and the connecting electrode provided by the embodiment of the present application.
  • Figure 17a is a schematic diagram of removing the false gate provided by the embodiment of the present application.
  • Figure 17b is a diagram of a preparation process of a gate provided by an embodiment of the present application.
  • it can be a fixed connection, a detachable connection, or an integral connection; it can be a direct connection, or an indirect connection through an intermediary, or it can be It is the internal connection between two components.
  • the terms “including” and “having” and any variations thereof are intended to cover a non-exclusive inclusion, for example, the inclusion of a series of steps or units. Methods, systems, products or devices are not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such processes, methods, products or devices. "Up”, “down”, “left”, “right”, etc. are only used relative to the orientation of the components in the drawings. These directional terms are relative concepts and are used for relative description and clarification. , which may change accordingly according to changes in the orientation in which the components in the drawings are placed.
  • Embodiments of the present application provide a terminal, which may also be a mobile phone, computer, tablet, personal digital assistant (personal digital assistant, PDA for short), smart wearable device, smart home device and other devices including a chip.
  • a terminal which may also be a mobile phone, computer, tablet, personal digital assistant (personal digital assistant, PDA for short), smart wearable device, smart home device and other devices including a chip.
  • PDA personal digital assistant
  • a mobile phone can include a circuit board, display screen, battery, camera, etc.
  • the circuit board can be integrated with a processor, internal memory, charging circuit, etc.
  • the mobile phone may also include other components, and other circuit structures may be integrated on the circuit board, which is not limited in the embodiments of the present application.
  • the processor may include one or more processing units.
  • the processor may include an application processor (application processor, AP), a modem processor, a graphics processing unit (GPU), an image signal processor (image signal processor (ISP), controller, memory, video codec, digital signal processor (digital signal processor, DSP), baseband processor, and/or neural-network processing unit (NPU), etc.
  • application processor application processor, AP
  • modem processor graphics processing unit
  • GPU graphics processing unit
  • ISP image signal processor
  • controller memory
  • video codec digital signal processor
  • DSP digital signal processor
  • NPU neural-network processing unit
  • different processing units can be independent devices or integrated in one or more processors.
  • GPU is an image processing microprocessor that connects the display and application processor. GPUs are used to perform mathematical and geometric calculations for graphics rendering. This enables the mobile phone to achieve display functions through the GPU, display screen, and application processor.
  • the charging circuit of a mobile phone includes a power management circuit and a charging management circuit.
  • the power management circuit connects the battery, the charge management circuit, and the processor.
  • the charge management circuit can receive charging input from the charger to charge the battery. While the charging management circuit charges the battery, it can also provide power to the mobile phone through the power management circuit.
  • the power management circuit receives input from the battery and/or charge management module to power the processor, internal memory, display, camera, etc.
  • Mobile phones can also achieve shooting functions through cameras, GPUs, displays, and application processors.
  • the internal memory in the mobile phone can be used to store computer executable program code, which includes instructions.
  • the processor executes the various functional applications and data of the mobile phone by running instructions stored in the internal memory. deal with.
  • the above-mentioned processor, internal memory, charging circuit, etc. integrated on the circuit board all include one or more chips.
  • the chip can be coupled to the circuit board through pins.
  • the chip can be coupled with an external circuit through the circuit board.
  • the chip can be coupled with the power circuit through the circuit board.
  • the power circuit can provide DC voltage to the chip through the circuit board to power the chip.
  • some of the multiple chips can be coupled through traces in the circuit board to work together to achieve specific functions.
  • a plurality of transistors 10 are provided in the chip 1 , and the transistors 10 may include FinFETs.
  • the preparation process of chip 1 can be divided into the front end of line (FEOL), the middle process, and the back end of line (BEOL).
  • the front-end process includes but is not limited to forming the above-mentioned transistor 10 on the substrate.
  • the transistor 10 serves as an important component of one or more logic circuits.
  • the middle process includes but is not limited to forming a contact electrode (CT).
  • CT contact electrode
  • the subsequent process includes but is not limited to forming metal lines on the transistor 10.
  • the metal lines can be electrically connected to one or more logic circuits through connecting electrodes, and the one or more logic circuits can transmit signals with external circuits through the metal lines.
  • Chip 1 can be a monolithic three-dimensional (3D) integrated circuit (IC) or a monolithic two-dimensional (two-dimensional). ,2D)IC.
  • FinFET includes a channel layer 15, a gate electrode 11, a source electrode 12 and a drain electrode 13.
  • the channel layer 15 is disposed on the substrate 20; the source electrode 12 and the drain electrode 13 are disposed on the side of the channel layer 15 facing away from the substrate 20; along the direction perpendicular to the direction in which the source electrode 12 points to the drain electrode 13, the gate electrode 11 spans the channel layer 15, and a gate insulation layer is also provided between the gate electrode 11 and the channel layer 15.
  • an insulating spacer layer 14 is also provided between the gate 11 and the source 12 and the drain 13. .
  • Embodiments of the present application provide a method for preparing FinFET, which reduces edge parasitic capacitance and even edge parasitic capacitance by reducing the comprehensive dielectric constant of the spacer layer 14, thereby improving the performance of FinFET.
  • the preparation process of FinFET is described in detail below with reference to the accompanying drawings.
  • the embodiment of the present application provides a method for preparing FinFET, as shown in Figure 4, which can be achieved through the following steps:
  • Figures 5a to 5k show the preparation process of the fins, taking the formation of four fins at the same time as an example.
  • a first film layer 151, a first mask layer 31 and a photoresist 32 may be formed sequentially on the substrate 20.
  • the photoresist 32 is exposed and developed to obtain a photoresist pattern 321.
  • the first mask layer 31 is etched to obtain the first mask pattern 311, and the photoresist pattern 321 is removed.
  • FIG. 5a to 5k show the preparation process of the fins, taking the formation of four fins at the same time as an example.
  • a first film layer 151, a first mask layer 31 and a photoresist 32 may be formed sequentially on the substrate 20.
  • the photoresist 32 is exposed and developed to obtain a photoresist pattern 321.
  • the first mask layer 31 is etched to obtain the first mask pattern 311, and the photoresist pattern 321 is removed.
  • FIG. 5c and FIG. 5d under the protection of the
  • a second mask layer 33 is formed on the side of the first mask pattern 311 facing away from the substrate 20 .
  • dry etching is used to etch the second mask layer 33 to obtain a second mask pattern 331.
  • the second mask pattern 331 They are located on opposite sides of each first mask pattern 311 and are disconnected between adjacent second mask patterns 331 .
  • the first mask pattern 311 is removed.
  • the first film layer 151 is etched to obtain the fin pattern 152, and the second mask pattern 331 is removed.
  • a second film layer 161 may be formed on the side of the fin pattern 152 facing away from the substrate 20 , and the material of the second film layer 161 may include an oxidized material.
  • the second film layer 161 can also be Perform chemical mechanical polishing (CMP) treatment.
  • the fin pattern 152 may be doped to obtain the fins 153 . It should be noted here that if the FinFET is an N-type transistor, the fin pattern 152 can be doped with P-type; if the FinFET is a P-type transistor, the fin pattern 152 can be doped with N-type. Afterwards, the fin pattern 152 may also be annealed.
  • embodiments of the present application do not limit the doping manner of the fin pattern 152 .
  • ion implantation IMP
  • the second film layer 161 can also be etched back to remove the portion of the second film layer 161 located on the side of the fin 153 away from the substrate 20 , so as to A shallow trench isolation layer (STI) 16 is obtained, and the fins 153 are exposed. Wherein, the shallow trench isolation layer 16 is located between adjacent fins 153 .
  • STI shallow trench isolation layer
  • the dummy gate 111 and the first spacer layer 141 are formed on the side of the fin 153 away from the substrate 20 .
  • the first spacer layer 141 is located on opposite sides of the dummy gate electrode 111 .
  • the FinFET preparation method may further include: forming an oxide layer 17 between the fin 153 and the dummy gate 111 . Afterwards, it may also be determined as needed whether to further dope the portion of the fin 153 located in the channel region.
  • the portion of the fin 153 located in the channel region refers to: the portion of the fin 153 that overlaps with the orthographic projection of the gate electrode 11 to be formed on the substrate 20 and is located between the source electrode 12 to be formed and the source electrode 12 to be formed. formed between the drain electrodes 13 .
  • the embodiments of the present application do not limit the material of the dummy gate 111, as long as the material of the dummy gate 111 does not affect the properties of other layers in the previous process during the formation of the dummy gate 111.
  • the material of the dummy gate 111 may include polysilicon (PO).
  • the embodiments of the present application do not limit the material of the first spacer layer 141 , as long as the first spacer layer 141 can be between the gate electrode 11 to be formed and the source electrode 12 and drain electrode 13 to be formed. , it can play an insulating role.
  • the material of the first spacer layer 141 and the material of the dummy gate 111 and the material of the oxide layer 17 may have a larger etching selectivity ratio.
  • the process of forming the first spacer layer 141 may include: forming a third film layer on the fins 153, the shallow trench isolation layer 16 and the dummy gate 111; and then using a photolithography process to The film layer is etched to obtain the first spacer layer 141 located on opposite sides of the dummy gate 111 .
  • S130 form a source electrode 12 and a drain electrode 13 on the substrate 20 , and the source electrode 12 and the drain electrode 13 are respectively located on opposite sides of the channel region of the fin field effect transistor.
  • the process of forming the source electrode 12 and the drain electrode 13 may include the following steps:
  • S131 as shown in FIG. 7a and FIG. 7c, use dry etching to etch the portion of the fin 153 located on the side of the first spacer layer 141 away from the dummy gate 111 to obtain the channel layer 15.
  • embodiments of the present application do not limit the thickness of the etched portion of the fin 153 .
  • the thickness of the etched part in the fin 153 is different from the source electrode formed in step S132. 12 is related to the thickness of the drain electrode 13, and the thickness of the etched portion of the fin 153 can be designed according to actual requirements.
  • step S131 may also include: Dry etching is used to etch the portions of the fin located on opposite sides of the channel area to obtain the channel layer 15 .
  • the source electrode 12 and the drain electrode 13 are formed at the etched positions in the channel layer 15.
  • the etched position in the channel layer 15 refers to the etched position of the fin 153 in step S13.
  • the source electrode 12 and the drain electrode 13 can be grown directly. If the N-type FinFET is an N-type transistor, the materials of the source electrode 12 and the drain electrode 13 may include silicon phosphide (SiP); if the FinFET is a P-type transistor, the materials of the source electrode 12 and the drain electrode 13 may include silicon germanium (SiGe) .
  • the process of preparing FinFET in the embodiment of the present application is to form multiple FinFETs on a motherboard, and the multiple FinFETs include both N-type transistors and P-type transistors. Then forming the source electrode 12 and the drain electrode 13 may include the following steps:
  • a first hard mask may be formed first, and the first hard mask covers the area where the P-type transistor to be formed is located. Afterwards, in the area where the N-type transistor to be formed is located, the source electrode 12 and the drain electrode 13 are formed at the etched positions in the channel layer 15, and the first hard mask is removed.
  • a second hard mask is formed, and the second hard mask covers the area where the N-type transistor to be formed is located. Afterwards, in the area where the P-type transistor is to be formed, the source electrode 12 and the drain electrode 13 are formed at the etched positions in the channel layer 15, and the second hard mask is removed.
  • the above example is based on the example of forming the source electrode 12 and the drain electrode 13 of the N-type transistor first, and then forming the source electrode 12 and the drain electrode 13 of the P-type transistor.
  • the source electrode 12 and the drain electrode 13 of the P-type transistor may be formed first, and then the source electrode 12 and the drain electrode 13 of the N-type transistor may be formed, which is not limited in the embodiment of the present application.
  • the embodiments of the present application do not limit the specific sizes and positions of the source electrode 12 and the drain electrode 13 , as long as the source electrode 12 and the drain electrode 13 are located on opposite sides of the channel region.
  • the relative positions of the source electrode 12 and the drain electrode 13 and the first spacer layer 141 are related to the etching degree of the fin 153 in step S131.
  • the source electrode 12 and the drain electrode 13 face the edge of the dummy gate electrode 111 and can be away from the first spacer layer 141 The edges of the dummy gate 111 are flush.
  • the fins 153 can be over-engraved in a direction in which the dummy gate 111 points to the first spacer layer 141 .
  • the first spacer layer 141 can protrude from the edge of the dummy gate 111 away from the dummy gate 111 .
  • the source electrode 12 and the drain electrode 13 face the edges of the dummy gate electrode 111 .
  • a second spacer layer 142 is formed on the side of the first spacer layer 141 away from the dummy gate 111.
  • the second spacer layer 142 may be in contact with the first spacer layer 141 .
  • the distance from the surface of the dummy gate 111 away from the substrate 20 to the substrate 20 is greater than the distance from the surface of the source electrode 12 and the drain electrode 13 away from the substrate 20 to the substrate 20 . Therefore, the second spacer layer 142 formed after the source electrode 12 and the drain electrode 13 may be respectively located on the side of the source electrode 12 and the drain electrode 13 facing away from the substrate 20 . It can also be said that along the direction perpendicular to the direction in which the source electrode 12 points to the drain electrode 13, the second spacer layer 142 can span across the Source 12 and drain 13. In other words, the orthographic projection of the second spacer layer 142 on the substrate 20 is located within the range of the orthographic projection of the source electrode 12 and the drain electrode 13 on the substrate 20 .
  • the embodiment of the present application does not limit the thickness of the second spacer layer 142, as long as it does not affect the original arrangement between the source electrode 12 and the drain electrode 142. 13 can be other structures on the side facing away from the substrate 20.
  • the embodiments of the present application do not limit the material of the second spacer layer 142 , as long as the second spacer layer 142 is an insulating material, and the dielectric constant of the second spacer layer 142 is smaller than that of the first spacer layer 141 The dielectric constant is enough.
  • the dielectric constant of the material of the second spacer layer 142 may be less than or equal to 5.5.
  • the material of the first spacer layer 141 may include at least one of silicon nitride (SiN) and silicon carbon nitride (SiCN).
  • the material of the second spacer layer 142 may include at least one of silicon oxide (Si 2 O 3 ) and silicon oxycarbonitride (SiOCN).
  • the dielectric constant of SiN is 7
  • the dielectric constant of SiOCN is 5.5
  • the dielectric constant of Si 2 O 3 is 3.9.
  • the edge parasitic capacitance is the parasitic capacitance between the gate electrode 11 and the source electrode 12 and the drain electrode 13.
  • the dummy gate electrode 111 is located at the same location as the gate electrode 11 to be formed.
  • the source electrode 12 is used to form the source electrode 12
  • the drain electrode 13 is used to form the drain electrode 13 . Therefore, the structure between the dummy gate 111 and the source electrode 12 and the drain electrode 13 is related to the parasitic capacitance between the gate electrode 11 and the source electrode 12 and the drain electrode 13 .
  • a first spacer layer 141 and a second spacer layer 142 are provided between the dummy gate 111 and the source electrode 12 and the drain electrode 13 , and the dielectric constant of the second spacer layer 142 is smaller than that of the first spacer layer 141
  • the dielectric constant thereby reduces the average dielectric constant of the structure between the dummy gate 111 and the source 12 and drain 13 to reduce edge parasitic capacitance and improve the AC performance of the FinFET.
  • this application forms the second spacer layer 142 after the source electrode 12 and the drain electrode 13 are formed, the second spacer layer 142 will not affect the distance from the source electrode 12 and the drain electrode 13 to the channel region, and further Does not affect FinFET DC parameters.
  • a contact etch stop layer (CESL) 18 is formed on the side of the second spacer layer 142 away from the dummy gate 111.
  • the contact etch stop layer 18 is located between the source electrode 12 and the drain electrode.
  • the pole 13 is on the side facing away from the substrate 20 .
  • the dielectric constant of the second spacer layer 142 is smaller than the dielectric constant of the contact metal etching barrier layer 18 .
  • the second spacer layer 142 is provided between the contact metal etching barrier layer 18 and the first spacer layer 141, the structure between the gate electrode 11 to be formed, the source electrode 12 and the drain electrode 13 is from The first spacer layer 141 and the contact metal etching barrier layer 18 become the first spacer layer 141 , the second spacer layer 142 , and the partial contact metal etching barrier layer 18 .
  • the dielectric constant of the second spacer layer 142 is smaller than the dielectric constant of the contact metal etching barrier layer 18 and the first spacer layer 141 , the gap between the gate electrode 11 to be formed, the source electrode 12 and the drain electrode 13 As the overall dielectric constant decreases, the edge parasitic capacitance between the gate electrode 11 to be formed, the source electrode 12 and the drain electrode 13 decreases.
  • the preparation method of FinFET may also include: sequentially forming a contact layer dielectric (interlayer dielectric, ILD) 19 and the aforementioned connection on the side of the contact metal etching barrier layer 18 away from the dummy gate 111 Electrode 20.
  • ILD interlayer dielectric
  • the FinFET preparation method may also include: forming an ohmic contact layer, the ohmic contact layer is at least between the source electrode 12 and the drain electrode 13 and the connection electrode 20 to reduce the impedance. .
  • the dummy gate 111 is removed, and the gate 11 is formed at the position of the dummy gate 111. It can also be said that the dummy gate 111 is removed, and the gate 11 is formed on the side of the first spacer layer 141 away from the second spacer layer 142 .
  • wet etching can be used to remove the dummy gate 111 and the oxide layer 17 . Since wet etching is isotropic, during the process of etching the dummy gate 111 and the oxide layer 17 , the first spacer layer 141 located on both sides of the dummy gate 111 and the oxide layer 17 may be damaged. . Therefore, a material with a larger etching selectivity ratio than the material of the dummy gate 111 and the oxide layer 17 can be selected as the material of the first spacer layer 141 to avoid etching the first spacer layer 141 of the dummy gate 111 , causing the first spacer layer 141 to be damaged by the etching liquid. Moreover, since the first spacer layer 141 will not be damaged by the etching liquid, the first spacer layer 141 can also better protect the second spacer layer 142 .
  • the material of the first spacer layer 141 includes SiOCN with a small dielectric constant
  • the etching selectivity of SiOCN is relatively small compared with the etching selectivity of the dummy gate 111 (the material may include polysilicon, for example)
  • special machinery is required. stage to protect the first spacer layer 141 from being damaged by the etching liquid.
  • the etching selectivity ratio between the first spacer layer 141 and the dummy gate electrode 111 is greater than the etching selectivity ratio between the second spacer layer 142 and the dummy gate electrode 11.
  • the material of the first spacer layer 141 includes and the dummy gate electrode 111.
  • the gate electrode 111 has SiN with a larger etching selectivity ratio, and the material of the second spacer layer 142 includes SiOCN with a smaller etching selectivity ratio than the dummy gate electrode 111 and a smaller dielectric constant, then the first spacer layer can be used 141 protects the second spacer layer 142, and no special machine is needed to protect the first spacer layer 141 and the second spacer layer 142, thereby saving production costs.
  • the preparation method of FinFET may also include the following steps:
  • FIG. 5 a - FIG. 5 k illustrate the preparation process of the fins 153 by taking the formation of four fins 153 at the same time as an example.
  • a first film layer 151, a first mask layer 31 and a photoresist 32 may be formed sequentially on the substrate 20.
  • the photoresist 32 is exposed and developed to obtain a photoresist pattern 321.
  • the first mask layer 31 is etched to obtain the first mask pattern 311, and the photoresist pattern 321 is removed.
  • FIG. 5 a - FIG. 5 k illustrate the preparation process of the fins 153 by taking the formation of four fins 153 at the same time as an example.
  • a first film layer 151, a first mask layer 31 and a photoresist 32 may be formed sequentially on the substrate 20.
  • the photoresist 32 is exposed and developed to obtain a photoresist pattern 321.
  • the first mask layer 31 is etched to obtain the first mask pattern 311, and the photoresist pattern 321 is
  • a second mask layer 33 is formed on the side of the first mask pattern 311 facing away from the substrate 20 .
  • dry etching is used to etch the second mask layer 33 to obtain a second mask pattern 331.
  • the second mask pattern 331 They are located on opposite sides of each first mask pattern 311 and are disconnected between adjacent second mask patterns 331 .
  • the first mask pattern 311 is removed.
  • the first film layer 151 is etched to obtain the fin pattern 152, and the second mask pattern 331 is removed.
  • a second film layer 161 may be formed on the side of the fin pattern 152 facing away from the substrate 20 , and the material of the second film layer 161 may include an oxidized material.
  • the second film layer 161 may also be subjected to chemical mechanical polishing.
  • the fin pattern 152 may be doped to obtain the fins 153 . It should be noted here that if the FinFET is an N-type transistor, the fin pattern 152 can be doped with P-type; if the FinFET is a P-type transistor, the fin pattern 152 can be doped with N-type. Afterwards, the fin pattern 152 may also be annealed.
  • embodiments of the present application do not limit the doping manner of the fin pattern 152 .
  • ion implantation may be used to dope the fin pattern 152 .
  • the second film layer 161 can also be etched back to remove the portion of the second film layer 161 located on the side of the fin 153 away from the substrate 20 , so as to The shallow trench isolation layer 16 is obtained, and the fins 153 are exposed. Wherein, the shallow trench isolation layer 16 is located between adjacent fins 153 .
  • the dummy gate 111 and the first spacer layer 141 are formed on the side of the fin 153 facing away from the substrate 20 .
  • the first spacer layer 141 is located on opposite sides of the dummy gate electrode 111 .
  • the FinFET preparation method may further include: forming an oxide layer 17 between the fin 153 and the dummy gate 111 . Afterwards, it may also be determined as needed whether to further dope the portion of the fin 153 located in the channel region.
  • the portion of the fin 153 located in the channel region refers to: the portion of the fin 153 that overlaps with the orthographic projection of the gate electrode 11 to be formed on the substrate 20 and is located between the source electrode 12 to be formed and the source electrode 12 to be formed. formed between the drain electrodes 13 .
  • the embodiments of the present application do not limit the material of the dummy gate 111, as long as the material of the dummy gate 111 does not affect the properties of other layers in the previous process during the formation of the dummy gate 111.
  • the material of the dummy gate 111 may include polysilicon.
  • the embodiments of the present application do not limit the material of the first spacer layer 141 , as long as the first spacer layer 141 can be between the gate electrode 11 to be formed and the source electrode 12 and drain electrode 13 to be formed. , it can play an insulating role.
  • the material of the first spacer layer 141 and the material of the dummy gate 111 and the material of the oxide layer 17 may have a larger etching selectivity ratio.
  • the process of forming the first spacer layer 141 may include: forming a third film layer after the fins 153, the shallow trench isolation layer 16 and the dummy gate 111; and then using a photolithography process to The third film layer is etched to obtain the first spacer layer 141 located on opposite sides of the dummy gate 111 .
  • S230 form a source electrode 12 and a drain electrode 13 on the substrate 20.
  • the source electrode 12 and the drain electrode 13 are located on opposite sides of the channel region of the fin field effect transistor.
  • the process of forming the source electrode 12 and the drain electrode 13 may include the following steps:
  • embodiments of the present application do not limit the thickness of the etched portion of the fin 153 .
  • the thickness of the etched portion of the fin 153 is related to the thickness of the source electrode 12 and the drain electrode 13 formed in step S132.
  • the thickness of the etched portion of the fin 153 can be designed according to actual requirements.
  • step S231 may also include: Dry etching is used to etch the portions of the fin located on opposite sides of the channel area to obtain the channel layer 15 .
  • the source electrode 12 and the drain electrode 13 are formed at the etched positions in the channel layer 15.
  • the etched position in the channel layer 15 refers to the etched position of the fin 153 in step S13.
  • the source electrode 12 and the drain electrode 13 can be grown directly. If the N-type FinFET is an N-type transistor, the materials of the source electrode 12 and the drain electrode 13 may include SiP; if the FinFET is a P-type transistor, the materials of the source electrode 12 and the drain electrode 13 may include SiGe.
  • the process of preparing FinFET in the embodiment of the present application is to form multiple FinFETs on a motherboard, and the multiple FinFETs include both N-type transistors and P-type transistors. Then forming the source electrode 12 and the drain electrode 13 may include the following steps:
  • a first hard mask may be formed first, and the first hard mask covers the area where the P-type transistor to be formed is located. Afterwards, in the area where the N-type transistor to be formed is located, the source electrode 12 and the drain electrode 13 are formed at the etched positions in the channel layer 15, and the first hard mask is removed.
  • a second hard mask is formed, and the second hard mask covers the area where the N-type transistor to be formed is located. Afterwards, in the area where the P-type transistor is to be formed, the source electrode 12 and the drain electrode 13 are formed at the etched positions in the channel layer 15, and the second hard mask is removed.
  • the above example is based on the example of forming the source electrode 12 and the drain electrode 13 of the N-type transistor first, and then forming the source electrode 12 and the drain electrode 13 of the P-type transistor.
  • the source electrode 12 and the drain electrode 13 of the P-type transistor may be formed first, and then the source electrode 12 and the drain electrode 13 of the N-type transistor may be formed, which is not limited in the embodiment of the present application.
  • the embodiments of the present application do not limit the specific sizes and positions of the source electrode 12 and the drain electrode 13 , as long as the source electrode 12 and the drain electrode 13 are located on opposite sides of the channel region.
  • the relative positions of the source electrode 12 and the drain electrode 13 and the first spacer layer 141 are related to the etching degree of the fin 153 in step S131.
  • the source electrode 12 and the drain electrode 13 face the edge of the dummy gate electrode 111 and can be away from the first spacer layer 141 The edges of the dummy gate 111 are flush.
  • the fins 153 can be over-engraved in a direction in which the dummy gate 111 points to the first spacer layer 141 .
  • the first spacer layer 141 can protrude from the edge of the dummy gate 111 away from the dummy gate 111 .
  • the source electrode 12 and the drain electrode 13 face the edges of the dummy gate electrode 111 .
  • step S250 adds step S250 to form the second spacer layer 142
  • part of the first spacer layer 141 can also be removed to avoid adding the second spacer layer 142 from affecting the overall size of the FinFET.
  • the embodiment of the present application does not limit the thickness of the removed portion of the first spacer layer 141 , as long as the remaining first spacer layer 141 is sufficient when the dummy gate 111 is removed in step S270 It is sufficient to protect the second spacer layer 142 .
  • a second spacer layer 142 is formed on the side of the first spacer layer 141 away from the dummy gate 111.
  • the second spacer layer 142 may be in contact with the first spacer layer 141 .
  • the orthographic projection of the second spacer layer 142 on the substrate 20 can be equal to The orthographic projections of the source electrode 12 and the drain electrode 13 on the substrate 20 partially overlap.
  • the second spacer layer 142 faces away from the false The edge of the gate electrode 111 is flush with the edges of the source electrode 12 and the drain electrode 13 facing the dummy gate electrode 111 .
  • the embodiment of the present application does not limit the thickness of the second spacer layer 142, as long as it does not affect the original arrangement between the source electrode 12 and the drain electrode 142. 13 can be other structures on the side facing away from the substrate 20.
  • the embodiments of the present application do not limit the material of the second spacer layer 142 , as long as the second spacer layer 142 is an insulating material, and the dielectric constant of the second spacer layer 142 is smaller than that of the first spacer layer 141 The dielectric constant is sufficient.
  • the dielectric constant of the material of the second spacer layer 142 may be less than or equal to 5.5.
  • the material of the first spacer layer 141 may include at least one of SiN and SiCN.
  • the material of the second spacer layer 142 may include at least one of Si 2 O 3 and SiOCN. Among them, the dielectric constant of SiN is 7, the dielectric constant of SiOCN is 5.5, and the dielectric constant of Si 2 O 3 is 3.9.
  • the edge parasitic capacitance is the parasitic capacitance between the gate electrode 11 and the source electrode 12 and the drain electrode 13.
  • the dummy gate electrode 111 is located at the same location as the gate electrode 11 to be formed.
  • the source electrode 12 is used to form the source electrode 12
  • the drain electrode 13 is used to form the drain electrode 13 . Therefore, the structure between the dummy gate 111 and the source electrode 12 and the drain electrode 13 is related to the parasitic capacitance between the gate electrode 11 and the source electrode 12 and the drain electrode 13 .
  • a first spacer layer 141 and a second spacer layer 142 are provided between the dummy gate 111 and the source electrode 12 and the drain electrode 13 , and the dielectric constant 142 of the second spacer layer 142 is smaller than the first spacer layer 141
  • the dielectric constant of the structure between the dummy gate 111 and the source electrode 12 and the drain electrode 13 is reduced to reduce edge parasitic capacitance and improve the AC performance of the FinFET.
  • this application forms the second spacer layer 142 after the source electrode 12 and the drain electrode 13 are formed, the second spacer layer 142 will not affect the distance from the source electrode 12 and the drain electrode 13 to the channel region, and further Does not affect FinFET DC parameters.
  • a contact metal etching barrier layer 18 is formed on the side of the second spacer layer 142 facing away from the dummy gate electrode 111.
  • the contact metal etching barrier layer 18 is located on the side of the source electrode 12 and the drain electrode 13 facing away from the substrate 20. .
  • the dielectric constant of the second spacer layer 142 is smaller than the dielectric constant of the contact metal etching barrier layer 18 .
  • the second spacer layer 142 is provided between the contact metal etching barrier layer 18 and the first spacer layer 141, the structure between the gate electrode 11 to be formed, the source electrode 12 and the drain electrode 13 is from The first spacer layer 141 and the contact metal etching barrier layer 18 become the first spacer layer 141 , the second spacer layer 142 , and the partial contact metal etching barrier layer 18 .
  • the dielectric constant of the second spacer layer 142 is smaller than the dielectric constant of the contact metal etching barrier layer 18 and the first spacer layer 141 , the gap between the gate electrode 11 to be formed, the source electrode 12 and the drain electrode 13 As the overall dielectric constant decreases, the edge parasitic capacitance between the gate electrode 11 to be formed, the source electrode 12 and the drain electrode 13 decreases.
  • the FinFET preparation method may also include: sequentially forming the contact layer dielectric 19 and the aforementioned connection electrode 20 on the side of the contact metal etching barrier layer 18 away from the dummy gate electrode 111 .
  • the FinFET preparation method may also include: forming an ohmic contact layer, the ohmic contact layer is at least between the source electrode 12 and the drain electrode 13 and the connection electrode 20 to reduce the impedance. .
  • the dummy gate 111 is removed, and the gate 11 is formed at the position of the dummy gate 111. It can also be said that the dummy gate 111 is removed and a gate is formed on the side of the first spacer layer 141 away from the second spacer layer 142 11.
  • wet etching can be used to remove the dummy gate 111 and the oxide layer 17 . Since wet etching is isotropic, during the process of etching the dummy gate 111 and the oxide layer 17 , the first spacer layer 141 located on both sides of the dummy gate 111 and the oxide layer 17 may be damaged. . Therefore, a material with a larger etching selectivity ratio than the material of the dummy gate 111 and the oxide layer 17 can be selected as the material of the first spacer layer 141 to avoid etching the first spacer layer 141 of the dummy gate 111 , causing the first spacer layer 141 to be damaged by the etching liquid. Moreover, since the first spacer layer 141 will not be damaged by the etching liquid, the first spacer layer 141 can also better protect the second spacer layer 142 .
  • the material of the first spacer layer 141 includes SiOCN with a small dielectric constant
  • the etching selectivity of SiOCN is relatively small compared with the etching selectivity of the dummy gate 111 (the material may include polysilicon, for example)
  • special machinery is required. stage to protect the first spacer layer 141 from being damaged by the etching liquid.
  • the etching selectivity ratio between the first spacer layer 141 and the dummy gate electrode 111 is greater than the etching selectivity ratio between the second spacer layer 142 and the dummy gate electrode 11.
  • the material of the first spacer layer 141 includes and the dummy gate electrode 111.
  • the gate electrode 111 has SiN with a larger etching selectivity ratio, and the material of the second spacer layer 142 includes SiOCN with a smaller etching selectivity ratio than the dummy gate electrode 111 and a smaller dielectric constant, then the first spacer layer can be used 141 protects the second spacer layer 142, and no special machine is needed to protect the first spacer layer 141 and the second spacer layer 142, thereby saving production costs.
  • An embodiment of the present application also provides a chip, as shown in Figure 11b and Figure 17b.
  • the chip includes a FinFET.
  • the FinFET of the embodiment of the present application can be prepared by any of the foregoing embodiments.
  • the FinFET includes a gate electrode 11, a first spacer layer 141, a second spacer layer 142, a source electrode 12 and a drain electrode 13.
  • the first spacer layer 141 is provided on opposite sides of the gate electrode 11
  • the second spacer layer 142 is provided on the opposite sides of the first spacer layer 141 away from the gate electrode 11 .
  • the dielectric constant of the second spacer layer 142 is smaller than the dielectric constant of the first spacer layer 141 .
  • the source electrode 12 and the drain electrode 13 are disposed on opposite sides of the channel region of the fin field effect transistor.
  • the distance from the surface of the gate 11 away from the substrate 20 to the substrate 20 is larger than that of the source 12 and the drain.
  • the orthographic projection of the second spacer layer 142 on the substrate 20 may partially overlap with the orthographic projection of the source electrode 12 and the drain electrode 13 on the substrate 20.
  • the edge of the second spacer layer 142 away from the gate electrode 11 is flush with the edges of the source electrode 12 and the drain electrode 13 facing the gate electrode 11 .
  • the edge parasitic capacitance is the parasitic capacitance between the gate electrode 11 and the source electrode 12 and the drain electrode 13.
  • the structure between the gate electrode 11 and the source electrode 12 and the drain electrode 13 is related to the parasitic capacitance between the gate electrode 11 and the source electrode 12 and the drain electrode 13.
  • a first spacer layer 141 and a second spacer layer 142 are provided between the gate electrode 11 and the source electrode 12 and the drain electrode 13 , and the dielectric constant 142 of the second spacer layer 142 is smaller than that of the first spacer layer 141 dielectric constant, thereby reducing the average dielectric constant of the structure between gate 111 and source 12 and drain 13 to reduce edge parasitic capacitance and improve FinFET AC performance.
  • the second spacer layer 142 will not affect the distance from the source electrode 12 and the drain electrode 13 to the channel region, and further Does not affect FinFET DC parameters.
  • the FinFET further includes a contact metal etching barrier layer 18.
  • the contact metal etching barrier layer 18 is disposed on the side of the second spacer layer 142 away from the gate 11.
  • the dielectric constant of the second spacer layer 142 is smaller than the contact metal etching barrier layer 18.
  • the gate electrode 11 forms a capacitor with the source electrode 12 and the drain electrode 13, a first spacer layer 141 and a contact metal etching barrier layer 18 are spaced between them.
  • the second spacer layer 142 is provided between the contact metal etching barrier layer 18 and the first spacer layer 141, the structure between the gate electrode 11, the source electrode 12 and the drain electrode 13 is separated from the first spacer layer 142.
  • the layer 141 and the contact metal etching barrier layer 18 become the first spacer layer 141, the second spacer layer 142, and the partial contact metal etching barrier layer 18.
  • the dielectric constant of the second spacer layer 142 is smaller than the dielectric constant of the contact metal etching barrier layer 18 and the first spacer layer 141 , the combined dielectric between the gate electrode 11 and the source electrode 12 and the drain electrode 13 The constant decreases, and the edge parasitic capacitance between the gate 11 and the source 12 and drain 13 decreases.
  • the embodiment of the present application does not limit the material of the second spacer layer 142, as long as the second spacer layer 142 is an insulating material, and the dielectric constant of the second spacer layer 142 is smaller than the first spacer layer 141 and the first spacer layer 142.
  • the dielectric constant of the contact metal etching barrier layer 18 is sufficient.
  • the dielectric constant of the material of the second spacer layer 142 may be less than or equal to 5.5.
  • the material of the first spacer layer 141 may include at least one of SiN and SiCN.
  • the material of the second spacer layer 142 may include at least one of Si 2 O 3 and SiOCN. Among them, the dielectric constant of SiN is 7, the dielectric constant of SiOCN is 5.5, and the dielectric constant of Si 2 O 3 is 3.9.
  • the FinFET may also include an ohmic contact layer located at least between the source electrode 12 and the drain electrode 13 and the connection electrode 20 , and the ohmic contact layer may be used to reduce the impedance.
  • FinFET may also include a contact layer dielectric 19 and a connection electrode 20 disposed on the side of the contact metal etching barrier layer 18 away from the gate electrode 11 .

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Abstract

本申请提供一种芯片及其制备方法、终端，涉及半导体技术领域，可以通过降低第一间隔层和第二间隔层的综合介电常数，来降低边缘寄生电容，以提高FinFET的性能。该芯片包括鳍式场效应晶体管，鳍式场效应晶体管的制备方法，包括：在衬底上依次形成假栅极和第一间隔层；第一间隔层设置于假栅极的相对两侧。接着，形成源极和漏极；沿第一间隔层指向假栅极的方向，源极和漏极分设于鳍式场效应晶体管的沟道区域的相对两侧。在第一间隔层背离假栅极侧，形成第二间隔层；第二间隔层的介电常数小于第一间隔层的介电常数。接着，去除假栅极。

Description

芯片及其制备方法、终端
本申请要求于2022年04月06日提交中国专利局、申请号为202210355856.5、申请名称为“芯片及其制备方法、终端”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及半导体技术领域，尤其涉及一种芯片及其制备方法、终端。
背景技术
鳍式场效应晶体管(fin field-effect transistor，FinFET)是一种新的晶体管。随着集成电路工艺的持续演进，FinFET的性能与集成电路的中段制程(the middle end of line，MEOL)中产生的寄生电容有关，中段制程产生的寄生电容越小，FinFET的性能越好。
边缘寄生电容(fringe capacitance)是指FinFET的栅极与源极和漏极之间的寄生电容，是中段制程产生的寄生电容的主要组成部分。因此，如何降低边缘寄生电容是目前亟待解决的问题。
发明内容
本申请提供一种芯片及其制备方法、终端，可以通过降低第一间隔层和第二间隔层的综合介电常数，来降低边缘寄生电容，以提高FinFET的性能。
第一方面，本申请提供一种芯片的制备方法，该芯片包括鳍式场效应晶体管，鳍式场效应晶体管的制备方法，包括：在衬底上依次形成假栅极和第一间隔层；第一间隔层设置于假栅极的相对两侧。接着，形成源极和漏极；沿第一间隔层指向假栅极的方向，源极和漏极分设于鳍式场效应晶体管的沟道区域的相对两侧。在第一间隔层背离假栅极侧，形成第二间隔层；第二间隔层的介电常数小于第一间隔层的介电常数。接着，去除假栅极。
本申请中，边缘寄生电容是栅极与源极和漏极之间的寄生电容。而假栅极的设置位置与待形成的栅极的设置位置相同，源极用于形成源极，漏极用于形成漏极。因此，假栅极与源极和漏极之间的结构，关系着栅极与源极和漏极之间的寄生电容。在本申请中，假栅极与源极和漏极之间设置有第一间隔层和第二间隔层，且第二间隔层的介电常数小于第一间隔层的介电常数，从而降低假栅极与源极和漏极之间的结构的平均介电常数，以降低边缘寄生电容，改善FinFET的交流性能。并且，由于本申请是在形成源极和漏极之后，才形成第二间隔层，因此，第二间隔层不会影响源极和漏极到沟道区域的距离，进而不会影响FinFET的直流参数。
在一些可能实现的方式中，形成源极和漏极之后，形成第二间隔层之前，鳍式场效应晶体管的制备方法还包括：沿第一间隔层指向假栅极的方向，去除部分第一间隔层。由于本申请的FinFET增加了第二间隔层，因此，还可以去除第一间隔层中的一部分，避 免因增加第二间隔层影响FinFET的整体尺寸。
在一些可能实现的方式中，在去除部分第一间隔层的情况下，第二间隔层背离假栅极的边沿，可以与源极和漏极朝向假栅极的边沿齐平。
在另一些可能实现的方式中，在去除部分第一间隔层，或者不去除部分第一间隔层的情况下，第二间隔层在衬底上的正投影，可以与源极和漏极在衬底上的正投影至少部分重合。
在一些可能实现的方式中，依次形成第二间隔层之后，方法还包括：在第二间隔层背离假栅极侧形成接触金属刻蚀阻挡层，接触金属刻蚀阻挡层位于源极和漏极背离衬底一侧；第二间隔层的介电常数小于接触金属刻蚀阻挡层的介电常数。
相关技术中，在FinFET不包括第二间隔层的情况下，待形成的栅极与源极和漏极构成电容时，二者之间间隔有第一间隔层和接触金属刻蚀阻挡层。
而本申请中，由于在接触金属刻蚀阻挡层与第一间隔层之间设置了第二间隔层，待形成的栅极与源极和漏极之间的结构，从第一间隔层和接触金属刻蚀阻挡层，变为第一间隔层、第二间隔层、以及部分接触金属刻蚀阻挡层。并且，由于第二间隔层的介电常数小于接触金属刻蚀阻挡层和第一间隔层的介电常数，因此，待形成的栅极与源极和漏极之间的综合介电常数减小，待形成的栅极与源极和漏极之间的边缘寄生电容减小。
在一些可能实现的方式中，在衬底上形成假栅极和第一间隔层之前，鳍式场效应晶体管的制备方法还包括：在衬底上形成鳍。之后，形成源极和漏极，可以包括：采用干法刻蚀对鳍中位于沟道区域相对两侧的部分进行刻蚀，得到沟道层。接着，在沟道层中被刻蚀的位置处形成源极和漏极。由于在形成第二间隔层之前形成源极和漏极，因此，第二间隔层不会影响源极和漏极到沟道区域的距离，进而不会影响FinFET的直流参数。
在一些可能实现的方式中，第一间隔层与假栅极的刻蚀选择比，大于第二间隔层与假栅极的刻蚀选择比；去除假栅极，包括：采用湿法刻蚀对假栅极进行刻蚀，以去除假栅极。去除假栅极之后，鳍式场效应晶体管的制备方法还包括：在第一间隔层背离第二间隔层侧形成栅极。
在采用湿法刻蚀去除假栅极和氧化时，由于湿法刻蚀具有各向同性，因此，在刻蚀假栅极和氧化层的过程中，可能会对位于假栅极和氧化层两侧的第一间隔层造成损伤。因此，可以选取与假栅极和氧化层的材料具有较大的刻蚀选择比的材料，作为第一间隔层的材料，以避免刻蚀假栅极的第一间隔层时，导致第一间隔层被刻蚀液损伤。并且，由于第一间隔层不会被刻蚀液损伤，因此，第一间隔层还可以更好地保护第二间隔层。
并且，若第一间隔层的材料包括介电常数较小的SiOCN，由于SiOCN的刻蚀选择比与假栅极(材料例如可以包括多晶硅)的刻蚀选择比较小，则还需要特殊机台，来保护第一间隔层不被刻蚀液损伤。而本申请通过使第一间隔层与假栅极的刻蚀选择比，大于第二间隔层与假栅极的刻蚀选择比，例如，第一间隔层的材料包括与假栅极具有较大刻蚀选择比的SiN，第二间隔层的材料包括与假栅极具有较小刻蚀选择比、且介电常数较小的SiOCN，则可以利用第一间隔层对第二间隔层起到保护作用，不需要特殊机台对第一间隔层和第二间隔层进行保护，节省制备成本。
在一些可能实现的方式中，第二间隔层的介电常数小于或等于5.5。例如，第一间隔 层的材料包括氮化硅、硅碳氮中的至少一种；第二间隔层的材料包括氧化硅、氧碳氮化硅中的至少一种。
第二方面，本申请实施例提供一种芯片，芯片包括鳍式场效应晶体管，鳍式场效应晶体管包括栅极、第一间隔层、第二间隔层、源极和漏极；第一间隔层设置于栅极相对两侧，第二间隔层设置于第一间隔层背离栅极的相对两侧；第二间隔层的介电常数小于第一间隔层的介电常数；沿第一间隔层指向第二间隔层的方向，源极和漏极分设于鳍式场效应晶体管的沟道区域的相对两侧。
在一些可能实现的方式中，在去除部分第一间隔层的情况下，第二间隔层背离假栅极的边沿，可以与源极和漏极朝向假栅极的边沿齐平。
在另一些可能实现的方式中，在去除部分第一间隔层，或者不去除部分第一间隔层的情况下，第二间隔层在衬底上的正投影，可以与源极和漏极在衬底上的正投影至少部分重合。
在一些可能实现的方式中，鳍式场效应晶体管还包括接触金属刻蚀阻挡层；接触金属刻蚀阻挡层设置于第二间隔层背离栅极侧，第二间隔层的介电常数小于接触金属刻蚀阻挡层的介电常数。
相关技术中，在FinFET不包括第二间隔层的情况下，待形成的栅极与源极和漏极构成电容时，二者之间间隔有第一间隔层和接触金属刻蚀阻挡层。
而本申请中，由于在接触金属刻蚀阻挡层与第一间隔层之间设置了第二间隔层，待形成的栅极与源极和漏极之间的结构，从第一间隔层和接触金属刻蚀阻挡层，变为第一间隔层、第二间隔层、以及部分接触金属刻蚀阻挡层。并且，由于第二间隔层的介电常数小于接触金属刻蚀阻挡层和第一间隔层的介电常数，因此，栅极与源极和漏极之间的综合介电常数减小，待形成的栅极与源极和漏极之间的边缘寄生电容减小。
在一些可能实现的方式中，第二间隔层的介电常数小于或等于5.5。例如，第一间隔层的材料包括氮化硅、硅碳氮中的至少一种；第二间隔层的材料包括氧化硅、氧碳氮化硅中的至少一种。
第三方面，本申请提供一种终端，该终端包括电路板和第二方面所述的芯片，所述芯片设置于所述电路板上。
第三方面以及第三方面的任意一种实现方式分别与第二方面以及第二方面的任意一种实现方式相对应。第三方面以及第三方面的任意一种实现方式所对应的技术效果可参见上述第二方面以及第二方面的任意一种实现方式所对应的技术效果，此处不再赘述。
附图说明
图1为本申请实施例提供的终端中各结构的连接图；
图2为本申请实施例提供的芯片的俯视图；
图3a为本申请实施例提供的一种FinFET的结构示意图；
图3b为图3a中A1-A2向的剖视示意图；
图4为本申请实施例提供的制备FinFET的一种流程示意图；
图5a为本申请实施例提供的鳍的一个制备过程图；
图5b为本申请实施例提供的鳍的另一制备过程图；
图5c为本申请实施例提供的鳍的又一制备过程图；
图5d为本申请实施例提供的鳍的又一制备过程图；
图5e为本申请实施例提供的鳍的又一制备过程图；
图5f为本申请实施例提供的鳍的又一制备过程图；
图5g为本申请实施例提供的鳍的又一制备过程图；
图5h为本申请实施例提供的鳍的又一制备过程图；
图5i为本申请实施例提供的鳍的又一制备过程图；
图5j为本申请实施例提供的鳍的又一制备过程图；
图5k为本申请实施例提供的鳍的又一制备过程图；
图6a为本申请实施例提供的假栅极的制备过程图；
图6b为本申请实施例提供的第一间隔层的制备过程图；
图6c为图6b中A1-A2向的剖视图；
图7a为本申请实施例提供的源极和漏极的一个制备过程图；
图7b为本申请实施例提供的源极和漏极的另一制备过程图；
图7c为本申请实施例提供的源极和漏极的又一制备过程图；
图7d为本申请实施例提供的源极和漏极的又一制备过程图；
图8为本申请实施例提供的第二间隔层的一种制备过程图；
图9为本申请实施例提供的18的一种制备过程图；
图10为本申请实施例提供的19和连接电极的一种制备过程图；
图11a为本申请实施例提供的去除假栅极的一种示意图；
图11b为本申请实施例提供的栅极的一种制备过程图；
图12为本申请实施例提供的制备FinFET的另一种流程示意图；
图13为本申请实施例提供的去除部分第一间隔层的示意图；
图14a为本申请实施例提供的形成第二间隔层的另一种制备过程图；
图14b为本申请实施例提供的形成第二间隔层的又一种制备过程图；
图15为本申请实施例提供的18的一种制备过程图；
图16为本申请实施例提供的19和连接电极的一种制备过程图；
图17a为本申请实施例提供的去除假栅极的一种示意图；
图17b为本申请实施例提供的栅极的一种制备过程图。
附图标记：
1-芯片；10-晶体管；11-栅极；111-假栅极；12-源极；13-漏极；141-第一间隔层；142-
第二间隔层；15-沟道层；151-第一膜层；152-鳍图案；153-鳍；16-浅槽隔离层；161-第二膜层；17-氧化层；18-接触金属刻蚀阻挡层；19-接触层介质；20-连接电极；31-第一掩模层；311-第一掩模图案；32-光刻胶；321-光刻胶图案；33-第二掩模层；331-第二掩模图案。
具体实施方式
为使本申请的目的、技术方案和优点更加清楚，下面将结合本申请中的附图，对本申请中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
本申请的说明书实施例和权利要求书及附图中的术语“第一”、“第二”等仅用于区分描述的目的，而不能理解为指示或暗示相对重要性，也不能理解为指示或暗示顺序。“和/或”，用于描述关联对象的关联关系，表示可以存在三种关系，例如，“A和/或B”可以表示：只存在A，只存在B以及同时存在A和B三种情况，其中A，B可以是单数或者复数。字符“/”一般表示前后关联对象是一种“或”的关系。“安装”、“连接”、“相连”等应做广义理解，例如可以是固定连接，也可以是可拆卸连接，或者一体地连接；可以是直接连接，也可以是通过中间媒介间接，也可以是两个元件内部的连通。此外，术语“包括”和“具有”以及他们的任何变形，意图在于覆盖不排他的包含，例如，包含了一系列步骤或单元。方法、系统、产品或设备不必限于清楚地列出的那些步骤或单元，而是可包括没有清楚地列出的或对于这些过程、方法、产品或设备固有的其它步骤或单元。“上”、“下”、“左”、“右”等仅用于相对于附图中的部件的方位而言的，这些方向性术语是相对的概念，它们用于相对于的描述和澄清，其可以根据附图中的部件所放置的方位的变化而相应地发生变化。
本申请实施例提供一种终端，该终端还可以是手机、电脑、平板电脑、个人数字助理(personal digital assistant，简称PDA)、智能穿戴式设备、智能家居设备等包括芯片的设备，本申请实施例对此不作限定。为了方便说明，下文以手机为例进行举例说明。
如图1所示，手机可以包括电路板、显示屏、电池、摄像头等。其中，电路板上可以集成有处理器、内部存储器、充电电路等。当然，手机还可以包括其他组成器件，电路板上还可以集成其他电路结构，本申请实施例对此不作限定。
处理器可以包括一个或多个处理单元，例如：处理器可以包括应用处理器(application processor，AP)，调制解调处理器，图形处理器(graphics processing unit，GPU)，图像信号处理器(image signal processor，ISP)，控制器，存储器，视频编解码器，数字信号处理器(digital signal processor，DSP)，基带处理器，和/或神经网络处理器(neural-network processing unit，NPU)等。其中，不同的处理单元可以是独立的器件，也可以集成在一个或多个处理器中。
GPU为图像处理的微处理器，连接显示屏和应用处理器。GPU用于执行数学和几何计算，用于图形渲染。从而使手机通过GPU、显示屏、以及应用处理器等实现显示功能。
手机的充电电路包括电源管理电路和充电管理电路。电源管理电路连接电池、充电管理电路、以及处理器。充电管理电路可以从充电器接收充电输入，为电池充电。充电管理电路为电池充电的同时，还可以通过电源管理电路为手机供电。电源管理电路接收电池和/或充电管理模块的输入，为处理器、内部存储器、显示屏、摄像头等供电。
手机还可以通过摄像头、GPU、显示屏、以及应用处理器等实现拍摄功能。
手机中的内部存储器可以用于存储计算机可执行程序代码，可执行程序代码包括指令。处理器通过运行存储在内部存储器的指令，从而执行手机的各种功能应用以及数据 处理。
上述集成在电路板上的处理器、内部存储器、充电电路等，均包括一个或多个芯片。芯片可以通过引脚与电路板耦合。芯片可以通过电路板与外部电路耦合，例如，芯片可以通过电路板与电源电路耦合，电源电路可以通过电路板为芯片提供直流电压，以实现为芯片供电。或者，以多个芯片为例，多个芯片中的部分芯片之间可以通过电路板中的走线耦合，以共同协作实现特定功能。
如图2所示，芯片1中设置有多个晶体管10，晶体管10可以包括FinFET。芯片1的制备工艺可以分为前道制程(the front end of line，FEOL)、中道制程、后道制程(the back end of line，BEOL)。前道制程包括但不限于在衬底上形成上述晶体管10，晶体管10作为一个或多个逻辑电路的重要组成器件。中道制程包括但不限于形成连接电极(contact，CT)。后道制程包括但不限于在晶体管10上形成金属线，金属线可以通过连接电极与一个或多个逻辑电路电连接，一个或多个逻辑电路通过金属线可以与外部电路传输信号。
此处需要说明的是，本申请实不对芯片1的类型进行限定，芯片1可以是单片三维(three dimensional，3D)集成电路(integrated circuit，IC)，也可以是单片二维(two dimensional，2D)IC。
如图3a所示，FinFET包括沟道层15、栅极11、源极12和漏极13。其中，沟道层15设置于衬底20上；源极12和漏极13设置于沟道层15背离衬底20一侧；沿与源极12指向漏极13的方向垂直的方向，栅极11横跨沟道层15，且栅极11与沟道层15之间还设置有栅绝缘层。
如图3a和图3b所示，为了避免栅极11与源极12和漏极13直接接触，导致FinFET短路，栅极11与源极12和漏极13之间还设置有绝缘的间隔层14。
本申请实施例提供了一种FinFET的制备方法，通过减小间隔层14的综合介电常数，来减小边缘寄生电容，乃至边缘寄生电容，从而提高FinFET的性能。下面结合附图，详细描述FinFET的制备过程。
本申请实施例提供一种FinFET的制备方法，如图4所示，可以通过如下步骤实现：
S110，在衬底上形成鳍(Fin)。
具体的，图5a-图5k以同时形成4个鳍为例，示出了鳍的制备过程。如图5a所示，可以先在衬底20上依次形成第一膜层151、第一掩模层31和光刻胶32。如图5b所示，对光刻胶32进行曝光，显影后得到光刻胶图案321。如图5c和图5d所示，在光刻胶图案321的保护下，对第一掩模层31进行刻蚀，得到第一掩模图案311，并去除光刻胶图案321。之后，如图5e所示，在第一掩模图案311背离衬底20一侧形成第二掩模层33。如图5f所示，采用干法刻蚀，对第二掩模层33进行刻蚀，得到第二掩模图案331，沿相邻第一掩模图案311的距离方向，第二掩模图案331位于每个第一掩模图案311的相对两侧，且相邻第二掩模图案331之间断开。如图5g所示，去除第一掩模图案311。如图5h和图5i所示，在第二掩模图案331的保护下，对第一膜层151进行刻蚀，得到鳍图案152，并去除第二掩模图案331。
接着，如图5j所示，可以在鳍图案152背离衬底20一侧形成第二膜层161，第二膜层161的材料可以包括氧化材料。在一些可能实现的方式中，还可以对第二膜层161进 行化学机械抛光(chemical mechanical polishing，CMP)处理。
接着，可以对鳍图案152进行掺杂，以得到鳍153。此处需要说明的是，若FinFET为N型晶体管，则可以对鳍图案152进行P型掺杂；若FinFET为P型晶体管，则可以对鳍图案152进行N型掺杂。之后，还可以对鳍图案152进行退火处理。
在一些可能实现的方式中，本申请实施例不对鳍图案152的掺杂方式进行限定。可选的，可以采用离子注入(implant，IMP)方式，对鳍图案152进行掺杂。
如图5k所示，对鳍图案152进行掺杂得到鳍153之后，还可以对第二膜层161进行回刻，去除第二膜层161中位于鳍153背离衬底20一侧的部分，以得到浅槽隔离层(shallow trench isolation，STI)16，露出鳍153。其中，浅槽隔离层16位于相邻鳍153之间。
S120，如图6a-图6c所示，在鳍153背离衬底20一侧形成假栅极111和第一间隔层141。沿待形成的源极12指向待形成的漏极13的方向，第一间隔层141位于假栅极111的相对两侧。
在一些实施例中，如图6a和图6c所示，在步骤步骤S110之后，在步骤S120之前，FinFET的制备方法还可以包括：在鳍153与假栅极111之间形成氧化层17。之后，还可以根据需要，确定是否继续对鳍153中位于沟道区域的部分进行进一步掺杂。
此处需要说明的是，鳍153中位于沟道区域的部分，是指：鳍153中与待形成的栅极11在衬底20上的正投影重叠、且位于待形成的源极12与待形成的漏极13之间的部分。
在一些可能实现的方式中，本申请实施例不对假栅极111的材料进行限定，只要在形成假栅极111的过程中，不因假栅极111的材料影响前道制程中其他膜层的性能即可。例如，假栅极111的材料可以包括多晶硅(polysilicon，PO)。
在一些可能实现的方式中，本申请实施例不对第一间隔层141的材料进行限定，只要第一间隔层141可以在待形成的栅极11与待形成的源极12和漏极13之间，起到绝缘作用即可。
考虑到步骤S170还需去除假栅极111，为了防止因去除假栅极111和氧化层17，导致第一间隔层141损伤。可选的，第一间隔层141的材料与假栅极111的材料和氧化层17的材料可以具有较大的刻蚀选择比。
在一些可能实现的方式中，形成第一间隔层141的过程可以包括：在鳍153、浅槽隔离层16和假栅极111上形成第三膜层；之后，采用光刻工艺，对第三膜层进行刻蚀，以得到位于假栅极111相对两侧的第一间隔层141。
S130，在衬底20上形成源极12和漏极13，源极12和漏极13分设于鳍式场效应晶体管的沟道区域的相对两侧。
具体的，形成源极12和漏极13的过程可以包括如下步骤：
S131，如图7a和图7c所示，采用干法刻蚀对鳍153中位于第一间隔层141背离假栅极111侧的部分进行刻蚀，得到沟道层15。
在一些可能实现的方式中，沿鳍153指向衬底20的方向，本申请实施例不对鳍153中被刻蚀部分的厚度进行限定。鳍153中被刻蚀部分的厚度，与步骤S132中形成的源极 12和漏极13的厚度有关，可以根据实际需求设计鳍153中被刻蚀部分的厚度。
在一些可能实现的方式中，由于沿与第一间隔层141指向假栅极111的方向垂直的方向，第一间隔层141还分设于鳍153的相对两侧，因此，步骤S131还可以包括：采用干法刻蚀对鳍中位于沟道区域相对两侧的部分进行刻蚀，得到沟道层15。
由于干法刻蚀具有各向异性，因此，沿鳍153指向衬底20的方向，对鳍153中位于沟道区域相对两侧的部分进行刻蚀时，不会影响到已形成的其他结构。
S132，如图7b和图7d所示，在沟道层15中被刻蚀的位置处形成源极12和漏极13。
此处需要说明的是，沟道层15中被刻蚀的位置，是指：鳍153在步骤S13中，被刻蚀的位置。
在一些可能实现的方式中，可以直接生长源极12和漏极13。若N型FinFET为N型晶体管，源极12和漏极13的材料可以包括磷化硅(SiP)；拖FinFET为P型晶体管，源极12和漏极13的材料可以包括锗硅(SiGe)。
在一些可能实现的方式中，若本申请实施例制备FinFET的过程，是在一张母板上形成多个FinFET，且多个FinFET既包括N型晶体管，也包括P型晶体管。则形成源极12和漏极13可以包括以下步骤：
以先形成N型晶体管的源极12和漏极13为例，可以先形成第一硬掩模，第一硬掩模覆盖待形成的P型晶体管所在的区域。之后，在待形成的N型晶体管所在的区域，在沟道层15中被刻蚀的位置处形成源极12和漏极13，并去除第一硬掩膜。
接着，形成第二硬掩模，第二硬掩模覆盖待形成的N型晶体管所在的区域。之后，在待形成的P型晶体管所在的区域，在沟道层15中被刻蚀的位置处形成源极12和漏极13，并去除第二硬掩膜。
上述示例是以先形成N型晶体管的源极12和漏极13，后形成P型晶体管的源极12和漏极13为例进行说明。在另一些可能实现的方式中，也可以先形成P型晶体管的源极12和漏极13，后形成N型晶体管的源极12和漏极13，本申请实施例对此不作限定。
在一些可能实现的方式中，本申请实施例不对源极12和漏极13的具体尺寸和位置进行限定，只要源极12和漏极13分设于沟道区域的相对两侧即可。对于源极12和漏极13与第一间隔层141的相对位置，与步骤S131中对鳍153的刻蚀程度有关。
如图7a和图7b所示，对鳍153进行刻蚀，并形成源极12和漏极13后，源极12和漏极13朝向假栅极111的边沿，可以与第一间隔层141背离假栅极111的边沿齐平。
或者，如图7c和图7d所示，可以对鳍153进行过刻，沿假栅极111指向第一间隔层141的方向，第一间隔层141背离假栅极111的边沿，可以凸出于源极12和漏极13朝向假栅极111的边沿。
S140，如图8所示，在第一间隔层141背离假栅极111侧，形成第二间隔层142。第二间隔层142可以与第一间隔层141接触。
在一些可能实现的方式中，由于假栅极111背离衬底20一侧的表面到衬底20的距离，大于源极12和漏极13背离衬底20一侧表面到衬底20的距离。因此，在源极12和漏极13之后形成的第二间隔层142，可以分别位于源极12和漏极13背离衬底20一侧。也可以说，沿与源极12指向漏极13的方向垂直的方向，第二间隔层142可以分别横跨 源极12和漏极13。或者说，第二间隔层142在衬底20上的正投影，位于源极12和漏极13在衬底20上的正投影的范围内。
在一些可能实现的方式中，沿与源极12指向漏极13的方向垂直的方向，本申请实施例不对第二间隔层142的厚度进行限定，只要不影响原本设置在源极12和漏极13背离衬底20一侧的其他结构即可。
在一些可能实现的方式中，本申请实施例不对第二间隔层142的材料进行限定，只要第二间隔层142为绝缘材料，且第二间隔层142的介电常数小于第一间隔层141的介电常数即可。
可选的，第二间隔层142的材料的介电常数可以小于或等于5.5。例如，第一间隔层141的材料可以包括氮化硅(SiN)、硅碳氮(SiCN)中的至少一种。第二间隔层142的材料可以包括氧化硅(Si2O3)、氧碳氮化硅(SiOCN)中的至少一种。其中，SiN的介电常数为7，SiOCN的介电常数为5.5，Si2O3的介电常数为3.9。
前文提到，边缘寄生电容是栅极11与源极12和漏极13之间的寄生电容。而假栅极111的设置位置与待形成的栅极11的设置位置相同，源极12用于形成源极12，漏极13用于形成漏极13。因此，假栅极111与源极12和漏极13之间的结构，关系着栅极11与源极12和漏极13之间的寄生电容。在本申请中，假栅极111与源极12和漏极13之间设置有第一间隔层141和第二间隔层142，且第二间隔层142的介电常数小于第一间隔层141的介电常数，从而降低假栅极111与源极12和漏极13之间的结构的平均介电常数，以降低边缘寄生电容，改善FinFET的交流性能。并且，由于本申请是在形成源极12和漏极13之后，才形成第二间隔层142，因此，第二间隔层142不会影响源极12和漏极13到沟道区域的距离，进而不会影响FinFET的直流参数。
S150，如图9所示，在第二间隔层142背离假栅极111侧形成接触金属刻蚀阻挡层(contact etch stop layer，CESL)18，接触金属刻蚀阻挡层18位于源极12和漏极13背离衬底20一侧。第二间隔层142的介电常数小于接触金属刻蚀阻挡层18的介电常数。
相关技术中，在FinFET不包括第二间隔层142的情况下，待形成的栅极11与源极12和漏极13构成电容时，二者之间间隔有第一间隔层141和接触金属刻蚀阻挡层18。
而本申请中，由于在接触金属刻蚀阻挡层18与第一间隔层141之间设置了第二间隔层142，待形成的栅极11与源极12和漏极13之间的结构，从第一间隔层141和接触金属刻蚀阻挡层18，变为第一间隔层141、第二间隔层142、以及部分接触金属刻蚀阻挡层18。并且，由于第二间隔层142的介电常数小于接触金属刻蚀阻挡层18和第一间隔层141的介电常数，因此，待形成的栅极11与源极12和漏极13之间的综合介电常数减小，待形成的栅极11与源极12和漏极13之间的边缘寄生电容减小。
此外，如图10所示，在步骤S150之后，FinFET的制备方法还可以包括：依次在接触金属刻蚀阻挡层18背离假栅极111侧形成接触层介质(interlayer dielectric，ILD)19和前述连接电极20。
在一些可能实现的方式中，在形成连接电极20之前，FinFET的制备方法还可以包括：形成欧姆接触层，欧姆接触层至少位于源极12和漏极13与连接电极20之间，以降低阻抗。
S160，如图11a和图11b所示，去除假栅极111，并在假栅极111位置处形成栅极11。也可以说，去除假栅极111，并在第一间隔层141背离第二间隔层142侧形成栅极11。
在一些可能实现的方式中，可以采用湿法刻蚀，去除假栅极111和氧化层17。而由于湿法刻蚀具有各向同性，因此，在刻蚀假栅极111和氧化层17的过程中，可能会对位于假栅极111和氧化层17两侧的第一间隔层141造成损伤。因此，可以选取与假栅极111和氧化层17的材料具有较大的刻蚀选择比的材料，作为第一间隔层141的材料，以避免刻蚀假栅极111的第一间隔层141时，导致第一间隔层141被刻蚀液损伤。并且，由于第一间隔层141不会被刻蚀液损伤，因此，第一间隔层141还可以更好地保护第二间隔层142。
并且，若第一间隔层141的材料包括介电常数较小的SiOCN，由于SiOCN的刻蚀选择比与假栅极111(材料例如可以包括多晶硅)的刻蚀选择比较小，则还需要特殊机台，来保护第一间隔层141不被刻蚀液损伤。而本申请通过使第一间隔层141与假栅极111的刻蚀选择比，大于第二间隔层142与假栅极11的刻蚀选择比，例如，第一间隔层141的材料包括与假栅极111具有较大刻蚀选择比的SiN，第二间隔层142的材料包括与假栅极111具有较小刻蚀选择比、且介电常数较小的SiOCN，则可以利用第一间隔层141对第二间隔层142起到保护作用，不需要特殊机台对第一间隔层141和第二间隔层142进行保护，节省制备成本。
另一个实施例中，如图12所示，FinFET的制备方法还可以包括如下步骤：
S210，在衬底上形成鳍153。
具体的，图5a-图5k以同时形成4个鳍153为例，示出了鳍153的制备过程。如图5a所示，可以先在衬底20上依次形成第一膜层151、第一掩模层31和光刻胶32。如图5b所示，对光刻胶32进行曝光，显影后得到光刻胶图案321。如图5c和图5d所示，在光刻胶图案321的保护下，对第一掩模层31进行刻蚀，得到第一掩模图案311，并去除光刻胶图案321。之后，如图5e所示，在第一掩模图案311背离衬底20一侧形成第二掩模层33。如图5f所示，采用干法刻蚀，对第二掩模层33进行刻蚀，得到第二掩模图案331，沿相邻第一掩模图案311的距离方向，第二掩模图案331位于每个第一掩模图案311的相对两侧，且相邻第二掩模图案331之间断开。如图5g所示，去除第一掩模图案311。如图5h和图5i所示，在第二掩模图案331的保护下，对第一膜层151进行刻蚀，得到鳍图案152，并去除第二掩模图案331。
接着，如图5j所示，可以在鳍图案152背离衬底20一侧形成第二膜层161，第二膜层161的材料可以包括氧化材料。在一些可能实现的方式中，还可以对第二膜层161进行化学机械抛光处理。
接着，可以对鳍图案152进行掺杂，以得到鳍153。此处需要说明的是，若FinFET为N型晶体管，则可以对鳍图案152进行P型掺杂；若FinFET为P型晶体管，则可以对鳍图案152进行N型掺杂。之后，还可以对鳍图案152进行退火处理。
在一些可能实现的方式中，本申请实施例不对鳍图案152的掺杂方式进行限定。可选的，可以采用离子注入方式，对鳍图案152进行掺杂。
如图5k所示，对鳍图案152进行掺杂得到鳍153之后，还可以对第二膜层161进行回刻，去除第二膜层161中位于鳍153背离衬底20一侧的部分，以得到浅槽隔离层16，露出鳍153。其中，浅槽隔离层16位于相邻鳍153之间。
S220，如图6a-图6c所示，在鳍153背离衬底20一侧形成假栅极111和第一间隔层141。沿待形成的源极12指向待形成的漏极13的方向，第一间隔层141位于假栅极111的相对两侧。
在一些实施例中，如图6a和图6c所示，在步骤步骤S110之后，在步骤S120之前，FinFET的制备方法还可以包括：在鳍153与假栅极111之间形成氧化层17。之后，还可以根据需要，确定是否继续对鳍153中位于沟道区域的部分进行进一步掺杂。
此处需要说明的是，鳍153中位于沟道区域的部分，是指：鳍153中与待形成的栅极11在衬底20上的正投影重叠、且位于待形成的源极12与待形成的漏极13之间的部分。
在一些可能实现的方式中，本申请实施例不对假栅极111的材料进行限定，只要在形成假栅极111的过程中，不因假栅极111的材料影响前道制程中其他膜层的性能即可。例如，假栅极111的材料可以包括多晶硅。
在一些可能实现的方式中，本申请实施例不对第一间隔层141的材料进行限定，只要第一间隔层141可以在待形成的栅极11与待形成的源极12和漏极13之间，起到绝缘作用即可。
考虑到步骤S170还需去除假栅极111，为了防止因去除假栅极111和氧化层17，导致第一间隔层141损伤。可选的，第一间隔层141的材料与假栅极111的材料和氧化层17的材料可以具有较大的刻蚀选择比。
在一些可能实现的方式中，形成第一间隔层141的过程可以包括：在鳍153、浅槽隔离层16和假栅极111之后，可以形成第三膜层；之后，采用光刻工艺，对第三膜层进行刻蚀，以得到位于假栅极111相对两侧的第一间隔层141。
S230，在衬底20上形成源极12和漏极13，源极12和漏极13位于鳍式场效应晶体管的沟道区域的相对两侧。
具体的，形成源极12和漏极13的过程可以包括如下步骤：
S231，如图7a和图7c所示，采用干法刻蚀对鳍153中位于第一间隔层141背离假栅极111侧的部分进行刻蚀，得到沟道层15。
在一些可能实现的方式中，沿鳍153指向衬底20的方向，本申请实施例不对鳍153中被刻蚀部分的厚度进行限定。鳍153中被刻蚀部分的厚度，与步骤S132中形成的源极12和漏极13的厚度有关，可以根据实际需求设计鳍153中被刻蚀部分的厚度。
在一些可能实现的方式中，由于沿与第一间隔层141指向假栅极111的方向垂直的方向，第一间隔层141还分设于鳍153的相对两侧，因此，步骤S231还可以包括：采用干法刻蚀对鳍中位于沟道区域相对两侧的部分进行刻蚀，得到沟道层15。
由于干法刻蚀具有各向异性，因此，沿鳍153指向衬底20的方向，对鳍153中位于沟道区域相对两侧的部分进行刻蚀时，不会影响到已形成的其他结构。
S232，如图7b和图7d所示，在沟道层15中被刻蚀的位置处形成源极12和漏极13。
此处需要说明的是，沟道层15中被刻蚀的位置，是指：鳍153在步骤S13中，被刻蚀的位置。
在一些可能实现的方式中，可以直接生长源极12和漏极13。若N型FinFET为N型晶体管，源极12和漏极13的材料可以包括SiP；拖FinFET为P型晶体管，源极12和漏极13的材料可以包括SiGe。
在一些可能实现的方式中，若本申请实施例制备FinFET的过程，是在一张母板上形成多个FinFET，且多个FinFET既包括N型晶体管，也包括P型晶体管。则形成源极12和漏极13可以包括以下步骤：
以先形成N型晶体管的源极12和漏极13为例，可以先形成第一硬掩模，第一硬掩模覆盖待形成的P型晶体管所在的区域。之后，在待形成的N型晶体管所在的区域，在沟道层15中被刻蚀的位置处形成源极12和漏极13，并去除第一硬掩膜。
接着，形成第二硬掩模，第二硬掩模覆盖待形成的N型晶体管所在的区域。之后，在待形成的P型晶体管所在的区域，在沟道层15中被刻蚀的位置处形成源极12和漏极13，并去除第二硬掩膜。
上述示例是以先形成N型晶体管的源极12和漏极13，后形成P型晶体管的源极12和漏极13为例进行说明。在另一些可能实现的方式中，也可以先形成P型晶体管的源极12和漏极13，后形成N型晶体管的源极12和漏极13，本申请实施例对此不作限定。
在一些可能实现的方式中，本申请实施例不对源极12和漏极13的具体尺寸和位置进行限定，只要源极12和漏极13分设于沟道区域的相对两侧即可。对于源极12和漏极13与第一间隔层141的相对位置，与步骤S131中对鳍153的刻蚀程度有关。
如图7a和图7b所示，对鳍153进行刻蚀，并形成源极12和漏极13后，源极12和漏极13朝向假栅极111的边沿，可以与第一间隔层141背离假栅极111的边沿齐平。
或者，如图7c和图7d所示，可以对鳍153进行过刻，沿假栅极111指向第一间隔层141的方向，第一间隔层141背离假栅极111的边沿，可以凸出于源极12和漏极13朝向假栅极111的边沿。
S240，如图13所示，沿第一间隔层141指向假栅极111的方向，去除部分第一间隔层141。沿第一间隔层141指向假栅极111的方向，保留下来的第一间隔层141的厚度小于第一间隔层141原本的厚度。
由于本申请的FinFET增加了步骤S250形成第二间隔层142，因此，还可以去除第一间隔层141中的一部分，避免因增加第二间隔层142影响FinFET的整体尺寸。
在一些可能实现的方式中，本申请实施例不对第一间隔层141中被去除掉的部分的厚度进行限定，只要在步骤S270中去除假栅极111时，保留下来的第一间隔层141足以保护第二间隔层142即可。
S250，如图14a和图14b所示，在第一间隔层141背离假栅极111侧，形成第二间隔层142。第二间隔层142可以与第一间隔层141接触。
在一些可能实现的方式中，基于第一间隔层141中保留部分的厚度、以及第二间隔层142的厚度，如图14a所示，第二间隔层142在衬底20上的正投影可以与源极12和漏极13在衬底20上的正投影部分重合。或者，如图14b所示，第二间隔层142背离假 栅极111的边沿，与源极12和漏极13朝向假栅极111的边沿齐平。
在一些可能实现的方式中，沿与源极12指向漏极13的方向垂直的方向，本申请实施例不对第二间隔层142的厚度进行限定，只要不影响原本设置在源极12和漏极13背离衬底20一侧的其他结构即可。
在一些可能实现的方式中，本申请实施例不对第二间隔层142的材料进行限定，只要第二间隔层142为绝缘材料，且第二间隔层142的介电常数小于第一间隔层141的介电常数即可。
可选的，第二间隔层142的材料的介电常数可以小于或等于5.5。例如，第一间隔层141的材料可以包括SiN、SiCN中的至少一种。第二间隔层142的材料可以包括Si2O3、SiOCN中的至少一种。其中，SiN的介电常数为7，SiOCN的介电常数为5.5，Si2O3的介电常数为3.9。
前文提到，边缘寄生电容是栅极11与源极12和漏极13之间的寄生电容。而假栅极111的设置位置与待形成的栅极11的设置位置相同，源极12用于形成源极12，漏极13用于形成漏极13。因此，假栅极111与源极12和漏极13之间的结构，关系着栅极11与源极12和漏极13之间的寄生电容。在本申请中，假栅极111与源极12和漏极13之间设置有第一间隔层141和第二间隔层142，且第二间隔层142的介电常数142小于第一间隔层141的介电常数，从而降低假栅极111与源极12和漏极13之间的结构的平均介电常数，以降低边缘寄生电容，改善FinFET的交流性能。并且，由于本申请是在形成源极12和漏极13之后，才形成第二间隔层142，因此，第二间隔层142不会影响源极12和漏极13到沟道区域的距离，进而不会影响FinFET的直流参数。
S260，如图15所示，在第二间隔层142背离假栅极111侧形成接触金属刻蚀阻挡层18，接触金属刻蚀阻挡层18位于源极12和漏极13背离衬底20一侧。第二间隔层142的介电常数小于接触金属刻蚀阻挡层18的介电常数。
相关技术中，在FinFET不包括第二间隔层142的情况下，待形成的栅极11与源极12和漏极13构成电容时，二者之间间隔有第一间隔层141和接触金属刻蚀阻挡层18。
而本申请中，由于在接触金属刻蚀阻挡层18与第一间隔层141之间设置了第二间隔层142，待形成的栅极11与源极12和漏极13之间的结构，从第一间隔层141和接触金属刻蚀阻挡层18，变为第一间隔层141、第二间隔层142、以及部分接触金属刻蚀阻挡层18。并且，由于第二间隔层142的介电常数小于接触金属刻蚀阻挡层18和第一间隔层141的介电常数，因此，待形成的栅极11与源极12和漏极13之间的综合介电常数减小，待形成的栅极11与源极12和漏极13之间的边缘寄生电容减小。
此外，如图16所示，在步骤S260之后，FinFET的制备方法还可以包括：依次在接触金属刻蚀阻挡层18背离假栅极111侧形成接触层介质19和前述连接电极20。
在一些可能实现的方式中，在形成连接电极20之前，FinFET的制备方法还可以包括：形成欧姆接触层，欧姆接触层至少位于源极12和漏极13与连接电极20之间，以降低阻抗。
S270，如图17a和图17b所示，去除假栅极111，并在假栅极111位置处形成栅极11。也可以说，去除假栅极111，并在第一间隔层141背离第二间隔层142侧形成栅极 11。
在一些可能实现的方式中，可以采用湿法刻蚀，去除假栅极111和氧化层17。而由于湿法刻蚀具有各向同性，因此，在刻蚀假栅极111和氧化层17的过程中，可能会对位于假栅极111和氧化层17两侧的第一间隔层141造成损伤。因此，可以选取与假栅极111和氧化层17的材料具有较大的刻蚀选择比的材料，作为第一间隔层141的材料，以避免刻蚀假栅极111的第一间隔层141时，导致第一间隔层141被刻蚀液损伤。并且，由于第一间隔层141不会被刻蚀液损伤，因此，第一间隔层141还可以更好地保护第二间隔层142。
并且，若第一间隔层141的材料包括介电常数较小的SiOCN，由于SiOCN的刻蚀选择比与假栅极111(材料例如可以包括多晶硅)的刻蚀选择比较小，则还需要特殊机台，来保护第一间隔层141不被刻蚀液损伤。而本申请通过使第一间隔层141与假栅极111的刻蚀选择比，大于第二间隔层142与假栅极11的刻蚀选择比，例如，第一间隔层141的材料包括与假栅极111具有较大刻蚀选择比的SiN，第二间隔层142的材料包括与假栅极111具有较小刻蚀选择比、且介电常数较小的SiOCN，则可以利用第一间隔层141对第二间隔层142起到保护作用，不需要特殊机台对第一间隔层141和第二间隔层142进行保护，节省制备成本。
本申请实施例还提供一种芯片，如图11b和图17b所示，该芯片包括FinFET，本申请实施例的FinFET可以通过前述任一实施例制备得到。FinFET包括栅极11、第一间隔层141、第二间隔层142、源极12和漏极13。第一间隔层141设置于栅极11相对两侧，第二间隔层142设置于第一间隔层141背离栅极11的相对两侧。第二间隔层142的介电常数小于第一间隔层141的介电常数。沿第一间隔层141指向第二间隔层142的方向，源极12和漏极13分设于鳍式场效应晶体管的沟道区域的相对两侧。
在一些可能实现的方式中，如图8所示，若采用前述步骤S110-S160形成FinFET，则由于栅极11背离衬底20一侧的表面到衬底20的距离，大于源极12和漏极13背离衬底20一侧表面到衬底20的距离。因此，在源极12和漏极13之后形成的第二间隔层142，可以分别位于源极12和漏极13背离衬底20一侧。也可以说，沿与源极12指向漏极13的方向垂直的方向，第二间隔层142可以分别横跨源极12和漏极13。或者说，第二间隔层142在衬底20上的正投影，位于源极12和漏极13在衬底20上的正投影的范围内。
若采用前述步骤S210-S270形成FinFET，则如图14a所示，第二间隔层142在衬底20上的正投影可以与源极12和漏极13在衬底20上的正投影部分重合。或者，如图14b所示，第二间隔层142背离栅极11的边沿，与源极12和漏极13朝向栅极11的边沿齐平。
前文提到，边缘寄生电容是栅极11与源极12和漏极13之间的寄生电容。栅极11与源极12和漏极13之间的结构，关系着栅极11与源极12和漏极13之间的寄生电容。在本申请中，栅极11与源极12和漏极13之间设置有第一间隔层141和第二间隔层142，且第二间隔层142的介电常数142小于第一间隔层141的介电常数，从而降低栅极111与源极12和漏极13之间的结构的平均介电常数，以降低边缘寄生电容，改善FinFET的 交流性能。并且，由于本申请是在形成源极12和漏极13之后，才形成第二间隔层142，因此，第二间隔层142不会影响源极12和漏极13到沟道区域的距离，进而不会影响FinFET的直流参数。
在一些实施例中，FinFET还包括接触金属刻蚀阻挡层18，接触金属刻蚀阻挡层18设置于第二间隔层142背离栅极11侧，第二间隔层142的介电常数小于接触金属刻蚀阻挡层18的介电常数。
相关技术中，栅极11与源极12和漏极13构成电容时，二者之间间隔有第一间隔层141和接触金属刻蚀阻挡层18。
而本申请中，由于在接触金属刻蚀阻挡层18与第一间隔层141之间设置了第二间隔层142，栅极11与源极12和漏极13之间的结构，从第一间隔层141和接触金属刻蚀阻挡层18，变为第一间隔层141、第二间隔层142、以及部分接触金属刻蚀阻挡层18。并且，由于第二间隔层142的介电常数小于接触金属刻蚀阻挡层18和第一间隔层141的介电常数，因此，栅极11与源极12和漏极13之间的综合介电常数减小，栅极11与源极12和漏极13之间的边缘寄生电容减小。
在一些可能实现的方式中，本申请实施例不对第二间隔层142的材料进行限定，只要第二间隔层142为绝缘材料，且第二间隔层142的介电常数小于第一间隔层141和接触金属刻蚀阻挡层18的介电常数即可。
可选的，第二间隔层142的材料的介电常数可以小于或等于5.5。例如，第一间隔层141的材料可以包括SiN、SiCN中的至少一种。第二间隔层142的材料可以包括Si2O3、SiOCN中的至少一种。其中，SiN的介电常数为7，SiOCN的介电常数为5.5，Si2O3的介电常数为3.9。
在一些可能实现的方式中，FinFET还可以包括至少位于源极12和漏极13与连接电极20之间的欧姆接触层，可以利用欧姆接触层降低阻抗。
此外，如图10所示，FinFET还可以包括设置于接触金属刻蚀阻挡层18背离栅极11侧的接触层介质19和连接电极20。
对于芯片的其他解释说明和有益效果，与前述任一实施例的解释说明和有益效果相同，在此不再赘述。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。

Claims (17)

  1. 一种芯片的制备方法，其特征在于，所述芯片包括鳍式场效应晶体管，所述鳍式场效应晶体管的制备方法，包括：
    在衬底上依次形成假栅极和第一间隔层；所述第一间隔层设置于所述假栅极的相对两侧；
    形成源极和漏极；沿所述第一间隔层指向所述假栅极的方向，所述源极和所述漏极分设于所述鳍式场效应晶体管的沟道区域的相对两侧；
    在所述第一间隔层背离所述假栅极侧，形成第二间隔层；所述第二间隔层的介电常数小于所述第一间隔层的介电常数；
    去除所述假栅极。
  2. 根据权利要求1所述的芯片的制备方法，其特征在于，所述形成源极和漏极之后，所述形成第二间隔层之前，所述鳍式场效应晶体管的制备方法还包括：
    沿所述第一间隔层指向所述假栅极的方向，去除部分所述第一间隔层。
  3. 根据权利要求2所述的芯片的制备方法，其特征在于，所述第二间隔层背离所述假栅极的边沿，与所述源极和所述漏极朝向所述假栅极的边沿齐平。
  4. 根据权利要求1或2所述的芯片的制备方法，其特征在于，所述第二间隔层在所述衬底上的正投影，与所述源极和所述漏极在所述衬底上的正投影至少部分重合。
  5. 根据权利要求4所述的芯片的制备方法，其特征在于，所述依次形成第二间隔层之后，所述方法还包括：
    在所述第二间隔层背离所述假栅极侧形成接触金属刻蚀阻挡层，所述接触金属刻蚀阻挡层位于所述源极和所述漏极背离所述衬底一侧；所述第二间隔层的介电常数小于所述接触金属刻蚀阻挡层的介电常数。
  6. 根据权利要求1所述的芯片的制备方法，其特征在于，所述在衬底上形成假栅极 和第一间隔层之前，所述鳍式场效应晶体管的制备方法还包括：
    在所述衬底上形成鳍。
  7. 根据权利要求6所述的芯片的制备方法，其特征在于，所述形成源极和所述漏极，包括：
    采用干法刻蚀对所述鳍中位于所述沟道区域相对两侧的部分进行刻蚀，得到沟道层；
    在所述沟道层中被刻蚀的位置处形成所述源极和所述漏极。
  8. 根据权利要求1所述的芯片的制备方法，其特征在于，所述第一间隔层与所述假栅极的刻蚀选择比，大于所述第二间隔层与所述假栅极的刻蚀选择比；
    所述去除所述假栅极，包括：
    采用湿法刻蚀对所述假栅极进行刻蚀，以去除所述假栅极。
  9. 根据权利要求8所述的芯片的制备方法，其特征在于，所述第二间隔层的介电常数小于或等于5.5。
  10. 根据权利要求9所述的芯片的制备方法，其特征在于，所述第一间隔层的材料包括氮化硅、硅碳氮中的至少一种；所述第二间隔层的材料包括氧化硅、氧碳氮化硅中的至少一种。
  11. 根据权利要求1所述的芯片的制备方法，其特征在于，所述去除所述假栅极之后，所述鳍式场效应晶体管的制备方法还包括：
    在所述第一间隔层背离所述第二间隔层侧形成栅极。
  12. 一种芯片，其特征在于，所述芯片包括鳍式场效应晶体管，所述鳍式场效应晶体管包括栅极、第一间隔层、第二间隔层、源极和漏极；
    所述第一间隔层设置于所述栅极相对两侧，所述第二间隔层设置于所述第一间隔层背离所述栅极的相对两侧；所述第二间隔层的介电常数小于所述第一间隔层的介电常数；
    沿所述第一间隔层指向所述第二间隔层的方向，所述源极和所述漏极分设于所述鳍式场效应晶体管的沟道区域的相对两侧。
  13. 根据权利要求12所述的芯片，其特征在于，所述第二间隔层在所述衬底上的正投影，与所述源极和所述漏极在所述衬底上的正投影至少部分重合。
  14. 根据权利要求13所述的芯片，其特征在于，所述鳍式场效应晶体管还包括接触金属刻蚀阻挡层；
    所述接触金属刻蚀阻挡层设置于所述第二间隔层背离所述栅极侧，所述第二间隔层的介电常数小于所述接触金属刻蚀阻挡层的介电常数。
  15. 根据权利要求14所述的芯片，其特征在于，所述第二间隔层的介电常数小于或等于5.5。
  16. 根据权利要求15所述的芯片，其特征在于，所述第一间隔层的材料包括氮化硅、硅碳氮中的至少一种；所述第二间隔层的材料包括氧化硅、氧碳氮化硅中的至少一种。
  17. 一种终端，其特征在于，包括电路板和权利要求12-16任一项所述的芯片，所述芯片设置于所述电路板上。
PCT/CN2023/074804 2022-04-06 2023-02-07 芯片及其制备方法、终端 WO2023193515A1 (zh)

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CN103928327A (zh) * 2013-01-10 2014-07-16 中芯国际集成电路制造(上海)有限公司 鳍式场效应晶体管及其形成方法
CN104425594A (zh) * 2013-08-20 2015-03-18 中芯国际集成电路制造(上海)有限公司 鳍式场效应晶体管及其形成方法
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Publication number Priority date Publication date Assignee Title
CN103928327A (zh) * 2013-01-10 2014-07-16 中芯国际集成电路制造(上海)有限公司 鳍式场效应晶体管及其形成方法
CN104425594A (zh) * 2013-08-20 2015-03-18 中芯国际集成电路制造(上海)有限公司 鳍式场效应晶体管及其形成方法
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