WO2017156913A1 - FinFET及其制造方法和包括其的电子设备 - Google Patents

FinFET及其制造方法和包括其的电子设备 Download PDF

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WO2017156913A1
WO2017156913A1 PCT/CN2016/087240 CN2016087240W WO2017156913A1 WO 2017156913 A1 WO2017156913 A1 WO 2017156913A1 CN 2016087240 W CN2016087240 W CN 2016087240W WO 2017156913 A1 WO2017156913 A1 WO 2017156913A1
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gate
finfet
gate stack
substrate
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PCT/CN2016/087240
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English (en)
French (fr)
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朱慧珑
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中国科学院微电子研究所
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Priority to US16/083,744 priority Critical patent/US10497809B2/en
Publication of WO2017156913A1 publication Critical patent/WO2017156913A1/zh

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Definitions

  • the present disclosure relates to semiconductor technology and, more particularly, to a FinFET capable of reducing capacitance between components and a method of fabricating the same, and an electronic device including such a FinFET.
  • FinFET fin field effect transistor
  • a FinFET comprising: a fin formed on a substrate; a gate stack formed on the substrate intersecting the fin; a gate spacer formed on a sidewall of the gate stack, wherein The gate spacer includes both a dielectric material and a negative capacitance material.
  • a method of fabricating a FinFET comprising: forming a fin on a substrate; forming a gate stack intersecting the fin on the substrate; and utilizing a dielectric material and a negative capacitance material Both, a gate spacer is formed on the sidewall of the gate stack.
  • an electronic device including the integrated circuit formed by the FinFET described above is provided.
  • the gate spacer includes both a dielectric material and a negative capacitance material such that both a positive capacitance and a negative capacitance may be caused between the gate electrode in the gate stack and the adjacent contact portion. Due to the presence of a negative capacitance (especially in the case where both positive and negative capacitances are connected in parallel), the total capacitance between the gate electrode and the contact portion can be reduced.
  • FIG. 1 is a schematic circuit diagram showing capacitance between a pair of components in accordance with an embodiment of the present disclosure
  • FIGS. 2(a)-8(b) are cross-sectional views showing partial stages in a process of fabricating a FinFET in accordance with an embodiment of the present disclosure
  • 9(a)-11(b) are cross-sectional views showing a partial stage in a process of fabricating a FinFET according to another embodiment of the present disclosure.
  • a layer/element when referred to as being "on" another layer/element, the layer/element may be directly on the other layer/element, or there may be a central layer between them/ element. In addition, if a layer/element is "on” another layer/element, the layer/element may be "under” the other layer/element when the orientation is reversed.
  • FIG. 1 is a schematic circuit diagram showing capacitance between a pair of components in accordance with an embodiment of the present disclosure.
  • member M 1 and M 2 which may be electrically conductive member, for example, comprise a metal or metallic material.
  • component M 1 may be a gate electrode (eg, a polysilicon gate electrode or a metal gate electrode)
  • component M 2 may be an adjacent contact (eg, a contact to a source/drain region corresponding to the gate electrode).
  • conductive regions are filled with a dielectric material. Due to this dielectric material, a (positive) capacitance can be generated between the components M 1 and M 2 .
  • the capacitor includes a plate-dielectric material-plate configuration in which the dielectric material can store charge.
  • Conventional capacitors have a "positive" capacitance characteristic, that is, as the charge stored in the dielectric material increases, the voltage between the two plates increases.
  • a dielectric material is referred to as a conventional dielectric material, or simply referred to as a dielectric material, as the term is conventional in the art.
  • certain materials can exhibit a "negative" capacitance characteristic under certain conditions, that is, as the charge stored therein increases, the voltage between the plates decreases.
  • This material is called a "negative capacitance material.”
  • certain ferroelectric materials eg, materials containing Hf, Zr, Ba, or Sr, such as HfZrO 2 , BaTiO 3 , KH 2 PO 4 , or NBT, or any combination thereof
  • Polarization causes a large amount of bound charge to accumulate instantaneously on the surface of the material, causing the voltage across the ferroelectric material to decrease.
  • such a positive capacitance can be compensated with a negative capacitance to reduce the total capacitance between components.
  • Figure 1 shows positive capacitances C 1 , ..., C m' between components M 1 and M 2 due to dielectric material and negative capacitances C n_1 , ..., C n_m for compensating for this, where m Is a positive integer greater than or equal to 1, and m' is a positive integer greater than or equal to 1.
  • This negative capacitance for example, by introducing a negative capacitance material between the member M 1 and M 2 (e.g., as described below, by introducing a negative capacitance material in the gate sidewall spacer (spacer)) is obtained.
  • these capacitances are shown as configurations that are connected in parallel.
  • the total capacitance C t can be reduced, even close to 0 (zero), compared to the case where the dielectric material between the components M 1 and M 2 is completely.
  • C t ⁇ 0 to keep the device electrically stable.
  • the capacitance between the components can be suppressed.
  • the gate electrode and the contact portion particularly in the case where the self-aligned contact portion is formed so that the contact portion is in physical contact with the gate spacer, the gate spacer is sandwiched between the gate electrode and the contact portion, so that A negative capacitance material is introduced into the gate spacer.
  • the positive capacitance and the negative capacitance are preferably connected in parallel with each other.
  • a portion of the gate spacers made of a dielectric material may be formed on a portion of the sidewalls of the gate stack and another portion of the gate spacers formed of a negative capacitance material may be formed on the sidewalls of the other portion of the gate stack.
  • a portion of the gate spacers of the dielectric material and another portion of the gate spacers of the negative capacitance material may be stacked one on top of the sidewalls of the gate stack.
  • part of the gate spacer of the dielectric material and another portion of the gate spacer of the negative capacitance material are sandwiched between the gate electrode and the contact portion, and the positive and negative capacitances respectively caused by the gate electrode and the contact portion are the plates. That is, the positive and negative capacitors can share the same plates and thus be connected in parallel with each other.
  • Such a FinFET can be manufactured, for example, as follows. Specifically, fins may be formed on the substrate. For example, a protruding linearly extending fin can be formed by patterning the substrate. A gate stack that intersects the fins can then be formed on the substrate. For example, the gate stack can be formed by forming a gate dielectric layer on a substrate and forming a gate electrode layer on the gate dielectric layer. Thereafter, a gate spacer can be formed on the sidewalls of the gate stack. As described above, both the dielectric material and the negative capacitance material can be utilized herein to form the gate spacers.
  • a portion of the gate spacers may be formed from a portion of the sidewalls of the gate stack using a dielectric material, and another portion of the sidewall spacers may be formed on the sidewalls of another portion of the gate stack using a negative capacitance material.
  • the two side wall spacers can be stacked one on top of the other.
  • This type of gate spacer can be manufactured, for example, as follows.
  • the preliminary sidewalls may be formed from the sidewalls of the gate stack (eg, along substantially the entire height thereof) using a dielectric material. Thereafter, a certain height of the upper portion of the preliminary spacer can be removed to obtain the portion of the gate spacer. Then, the other portion of the gate spacers may be formed using a negative capacitance material on the partial gate side wall.
  • a shielding layer may be formed on the substrate, the shielding layer may expose a preliminary sidewall of a certain height, and shield the preliminary sidewall. The rest.
  • the exposed portion of the preliminary spacer can be removed by selective etching.
  • the negative capacitance material spacer can be formed while the shielding layer is left.
  • it may be like this Side wall material: for the side wall above the fin, it can be formed by a negative capacitance material, and for the side wall on both sides of the fin (or the side wall above the dielectric layer at the bottom), the upper and lower parts can be included. They can be side walls of negative capacitance materials and side walls of common dielectric materials.
  • FIGS. 2(a)-8(b) are cross-sectional views showing a partial stage in a flow of fabricating a semiconductor device in accordance with an embodiment of the present disclosure.
  • Fig. 2(a), 2(b), 2(c) (Fig. 2(a) is a plan view, Fig. 2(b) is a cross-sectional view taken along line AA' in Fig. 2(a), and Fig. 2(c)
  • the substrate 1001 is provided as shown in the cross-sectional view taken along line BB' in Fig. 2(a).
  • a silicon wafer will be described as an example.
  • the present disclosure is not limited thereto, but can be applied to other various forms of substrates such as a germanium substrate, a semiconductor-on-insulator (SOI) substrate, a compound semiconductor substrate, and the like.
  • a shallow trench isolation (STI) 1003 for defining an active region may be formed in the substrate 1001.
  • a desired device such as a fin field effect transistor (FinFET) T1 or the like can be formed on the substrate 1001.
  • the FinFET T1 may include a fin F formed on the substrate 1001 extending in a first direction (in this example, a horizontal direction shown by 2(a) in the drawing) and a portion intersecting with the first direction (for example, vertical) The two directions (in this example, the vertical direction shown by 2(a) in the figure) extend so as to intersect the fin F.
  • the gate stack may include a gate dielectric layer 1005 and a gate electrode layer (G) 1007 which are sequentially stacked on the surface of the substrate.
  • the gate dielectric layer 1005 may include an oxide (eg, silicon oxide) or a high-k gate dielectric such as HfO 2 ; the gate electrode layer 1007 may include polysilicon or a metal gate dielectric.
  • source/drain regions (S/D) may be formed at opposite ends of the fin F (on opposite sides of the gate stack position, respectively).
  • a dielectric (preparatory) spacer 1009 can be formed on the sidewalls of the gate stack.
  • a dielectric layer of a certain thickness may be deposited in a substantially conformal manner on a substrate formed with a gate stack (which may be a sacrificial gate stack in the case of a gate-last process), and then substantially perpendicular to the surface of the substrate.
  • the deposited dielectric layer is subjected to reactive ion etching (RIE) to remove its laterally extending portion leaving its vertical extension, thereby obtaining a spacer.
  • the sidewall 1009 can include a nitride (eg, silicon nitride).
  • dummy devices Td1 and Td2 may be formed on opposite sides (left and right sides in the drawing) of the device T1.
  • a pseudo device Td1, Td2 may be formed on the STI 1003 and may include substantially the same configuration as the device T1.
  • These dummy devices Td1, Td2 may be formed on the substrate 1001 in the same process as the device T1.
  • a portion of the sidewall 1009 (in this example, the upper portion thereof) may be removed to form a positive capacitive sidewall.
  • a shielding layer 1011 may be formed on the substrate.
  • the masking material may be formed by a deposition process, for example, including an oxide.
  • the deposited masking material may be planarized such as CMP, and the CMP may stop at the gate electrode G.
  • the shielding material of the electrode can be etched back to obtain the shielding layer 1011.
  • it can be etched back by selective etching such as RIE. The amount of etch back is controlled so that the side wall portion shielded by the shielding layer 1011 after eclipse has a desired height.
  • Fig. 4(a) a cross-sectional view taken along line AA' in Fig. 2(a)
  • 4(b) a cross-sectional view taken along line BB' in Fig. 2(a)
  • Etching eg, wet etching, such as with hot phosphoric acid
  • the remaining side wall 1009 may have a certain height (dimension in the vertical direction in the drawing) Hp and a certain width (dimension in the horizontal direction in the drawing) Wp.
  • This height Hp and width Wp can be adjusted by adjusting the process parameters.
  • the height Hp can be controlled by controlling the amount of etchback of the shielding layer 1011, and the width Wp can be adjusted by the thickness of the dielectric layer deposited in the sidewall forming process.
  • the sidewall 1009 is no longer present on the sidewall of the gate stack.
  • the present disclosure is not limited thereto.
  • a sidewall 1009 may also remain on the sidewalls of the gate stack above the top surface of the fin F.
  • a negative capacitance spacer can be formed on the side wall of the positive capacitor thus formed.
  • the side can be passed
  • the wall forming process forms a spacer 1013 on the exposed sidewall of the gate stack using a negative capacitance material such as HfZrO 2 .
  • a layer of negative capacitance material may be deposited in a substantially conformal manner on the structures illustrated in Figures 4(a) and 4(b), and then the negative capacitance material deposited in a direction substantially perpendicular to the surface of the substrate.
  • the negative capacitance spacer 1013 may have a certain height (dimension in the vertical direction in the drawing) Hn and a certain width (dimension in the horizontal direction in the drawing) Wn.
  • This height Hn and width Wn can be adjusted by adjusting the process parameters.
  • the height Hp can be controlled by controlling the etching amount of the RIE, and the width Wp can be adjusted by the thickness of the deposited negative capacitance dielectric layer.
  • a final gate spacer is formed on the sidewalls of the gate stack, the gate spacers including sidewalls 1009 of dielectric material and spacers 1013 of negative capacitance material.
  • the sidewall of the dielectric material is formed first and then the sidewall of the negative capacitance material is formed
  • the present disclosure is not limited thereto.
  • the sidewalls of the negative capacitive material may be formed first (eg, the preliminary sidewall spacers 1009 are made of a negative capacitive material) and then the sidewalls of the dielectric material are formed (eg, the sidewall spacers 1013 are made of a dielectric material).
  • the gate spacers including the positive capacitor side wall and the negative capacitor spacer can also be formed, except that the stacking order of the positive capacitor sidewall and the negative capacitor sidewall is different.
  • a contact portion can be formed.
  • the contact portion is formed in a self-aligned manner, but the present disclosure is not limited thereto.
  • an interlayer dielectric layer 1015 is deposited on the structures shown in 5(a) and 5(b).
  • the interlayer dielectric layer 1015 can include an oxide.
  • the shielding layer 1011 also includes an oxide as described above, the shielding layer 1011 may be left as an interlayer dielectric layer, and then they are collectively shown as 1015.
  • FIG. 2(f) since the interlayer dielectric layer 1015 and the shielding layer 1011 are both oxides, the interface between them is shown as a broken line.
  • the masking layer 1011 can be removed first (eg, by selective etching) and then the interlayer dielectric layer 1015 can be deposited.
  • the deposited interlayer dielectric layer 1015 may be subjected to a planarization process such as chemical mechanical polishing (CMP), and the CMP may be stopped at the gate electrode G.
  • CMP chemical mechanical polishing
  • the shielding layer 1017 may be formed on the planarized interlayer dielectric layer 1015.
  • the masking layer 1017 can include a nitride having a thickness of about 20 to 30 nm.
  • FIG. 7(a) a cross-sectional view taken along line AA' in FIG. 2(a)
  • 7(b) a cross-sectional view taken along line BB' in FIG. 2(a)
  • light can be passed.
  • Holes are formed in the shielding layer 1017 corresponding to the source/drain regions (S/D) to expose the space between the gate spacers.
  • the sidewalls of the holes in the shielding layer 1017 may be located on the side wall of the grid.
  • the sidewalls of the holes extend outwardly relative to the respective gate stack, An unnecessary short circuit between the contact portion and the gate electrode which are subsequently formed at the position of the hole is avoided.
  • the interlayer dielectric layer 1015 can be selectively etched, such as RIE, to remove the interlayer dielectric layer between the gate spacers, thereby forming contact between adjacent gate spacers. Hole R.
  • the shielding layer 1017 can shield an area where it is not necessary to form a contact portion.
  • the shielding layer 1017 may not be provided, but the interlayer dielectric layer 1015 may be selectively etched directly.
  • contact holes are also formed on both sides of the dummy devices Td1, Td2.
  • the interlayer dielectric layer 1015 may not be formed, but after the gate spacers are formed (the mask layer 1011 is removed), a contact portion may be formed directly between the gate stacks, and the contacts may be electrically isolated if necessary. .
  • a contact hole may be formed.
  • a conductive material such as a metal such as W is filled in R to form a contact portion 1019.
  • the contact portions CT1 and CT2 corresponding to the source/drain regions (S/D) are shown.
  • Filling the contact hole R with a conductive material may, for example, deposit a conductive material on the structure shown in FIGS. 7(a) and 7(b) to at least completely fill the contact hole R, and then planarize the deposited conductive material. Processing such as CMP (CMP can be stopped at the masking layer 1017) is implemented.
  • a diffusion barrier such as TiN may also be formed on the inside of the contact hole.
  • the gate electrode G and the contact portion CT1 are considered. Since they are opposite each other and there is a dielectric material and a negative capacitance material between them, a capacitance C t will be generated between them.
  • the capacitance value can be adjusted by adjusting at least one of the height Hp and the width Wp of the side wall of the dielectric material and the height Hn and the width Wn of the side wall of the negative capacitance material such that C t is close to zero (but preferably Greater than zero).
  • C t is close to zero (but preferably Greater than zero).
  • Td1 and Td2 are illustrated as dummy devices in the above description, the present disclosure is not limited thereto.
  • at least one of Td1 and Td2 may be a device that actually functions like T1.
  • the contact portions formed in the space between Td1 (and/or Td2) and T1 are shared by them, so that their source/drain regions are connected to each other through the common contact portion.
  • the contact portion is illustrated as a self-aligned contact portion above, the present disclosure is not limited thereto.
  • the contact portion may be formed by filling a conductive material such as a metal in a via hole formed in the dielectric layer.
  • the gate spacer configuration according to an embodiment of the present disclosure can also reduce the parasitic capacitance between the contact portion and the gate electrode.
  • FIGS. 9(a)-11(b) are cross-sectional views showing a partial stage in the flow of fabricating a FinFET according to another embodiment of the present disclosure, wherein the same as in Figs. 2(a)-8(b) The figure marks are used to indicate the same parts.
  • This embodiment is substantially the same as the above embodiment, the main difference being that a layer of negative capacitance material is also formed on top of the gate stack.
  • the mask layer 1017 can be removed by selective etching as shown in (a) a cross-sectional view of the AA' line) and 9 (b) (a cross-sectional view taken along line BB' in FIG. 2(a)).
  • the gate electrode G is exposed.
  • the shielding layer 1017 above the device T1 is removed is shown (for example, this can be achieved by covering the shielding layer 1017 with a photoresist, but exposing the shielding layer portion above the T1, and performing selective etching. ).
  • the remainder of the masking layer 1017 eg, the portion above Td1 and/or Td2 can also be removed.
  • the gate electrode may be further recessed.
  • FIG. 10(a) a cross-sectional view taken along line AA' in FIG. 2(a)
  • 10(b) a cross-sectional view taken along line BB' in FIG. 2(a)
  • Selective etching causes the gate electrode G to be recessed downward to a certain extent.
  • a negative dielectric layer 1021 is formed in the space left by the removal of the layer 1017 (and the recess caused by the gate electrode). For example, this can be achieved by depositing a negative dielectric material on the structures shown in Figures 10(a) and 10(b) and planarizing it such as CMP (CMP can be stopped at the contact).
  • the thickness of the negative capacitance material layer 1021 may be adjusted (this may be, for example, by adjusting the gate The degree of depression of the electrode is adjusted) to adjust the capacitance value such that Ct is close to zero (but preferably greater than zero).
  • the capacitance value such that Ct is close to zero (but preferably greater than zero).
  • the FinFET according to an embodiment of the present disclosure can be applied to various electronic devices. For example, by integrating a plurality of such FinFETs and other devices (eg, other forms of transistors, etc.), an integrated circuit (IC) can be formed and electronic devices can be constructed therefrom. Accordingly, the present disclosure also provides an electronic device including the above semiconductor device.
  • the electronic device can also include a display screen that mates with the integrated circuit and a wireless transceiver that mates with the integrated circuit.
  • Such electronic devices are, for example, smart phones, tablet computers (PCs), personal digital assistants (PDAs), and the like.

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Abstract

提供一种鳍式场效应晶体管（FinFET）及其制造方法和包括其的电子设备。上述FinFET可以包括：在衬底（1001）上形成的鳍（F）；在衬底（1001）上形成的与鳍（F）相交的栅堆叠；在栅堆叠的侧壁上形成的栅侧墙（1009），其中，栅侧墙（1009）包括电介质材料和负电容材料二者。

Description

FinFET及其制造方法和包括其的电子设备
相关申请的引用
本申请要求于2016年3月17日递交的题为“FinFET及其制造方法和包括其的电子设备”的中国专利申请201610153719.8的优先权，其内容一并于此用作参考。
技术领域
本公开涉及半导体技术，更具体地，涉及一种能够降低部件间电容的FinFET及其制造方法以及包括这种FinFET的电子设备。
背景技术
随着集成电路(IC)中器件密度的不断增加，部件间的间隔越来越小。这使得IC中各部件之间例如栅电极和接触部之间的寄生电容增加，并因此使IC性能劣化。另一方面，即便对于性能要求不高的器件，也期望获得低功耗，并因此希望降低电容。抑制这种电容增加的一种方法是在部件之间使用气隙，但是其机械和电学稳定性存在问题。
因此，需要能够在部件之间的间隔不断变小的趋势下降低它们之间的电容。
发明内容
本公开的目的至少部分地在于提供一种能够降低部件间电容特别是栅电极和接触部间电容的鳍式场效应晶体管(FinFET)及其制造方法以及包括这种FinFET的电子设备。
根据本公开的一个方面，提供了一种FinFET，包括：在衬底上形成的鳍；在衬底上形成的与鳍相交的栅堆叠；在栅堆叠的侧壁上形成的栅侧墙，其中，栅侧墙包括电介质材料和负电容材料二者。
根据本公开的另一方面，提供了一种制造FinFET的方法，包括：在衬底上形成鳍；在衬底上形成与鳍相交的栅堆叠；以及利用电介质材料和负电容材 料二者，在栅堆叠的侧壁上形成栅侧墙。
根据本公开的又一方面，提供了一种电子设备，包括上述FinFET形成的集成电路。
根据本公开的实施例，栅侧墙包括电介质材料和负电容材料二者，从而在栅堆叠中的栅电极与邻近的接触部之间可以导致正电容和负电容二者。由于负电容的存在(特别是正电容与负电容二者并联的情况下)，可以降低栅电极与接触部之间的总电容。
附图说明
通过以下参照附图对本公开实施例的描述，本公开的上述以及其他目的、特征和优点将更为清楚，在附图中：
图1是示出了根据本公开实施例的一对部件之间的电容的示意电路图；
图2(a)-8(b)是示出了根据本公开实施例的制造FinFET的流程中部分阶段的截面图；
图9(a)-11(b)是示出了根据本公开另一实施例的制造FinFET的流程中部分阶段的截面图。
具体实施方式
以下，将参照附图来描述本公开的实施例。但是应该理解，这些描述只是示例性的，而并非要限制本公开的范围。此外，在以下说明中，省略了对公知结构和技术的描述，以避免不必要地混淆本公开的概念。
在附图中示出了根据本公开实施例的各种结构示意图。这些图并非是按比例绘制的，其中为了清楚表达的目的，放大了某些细节，并且可能省略了某些细节。图中所示出的各种区域、层的形状以及它们之间的相对大小、位置关系仅是示例性的，实际中可能由于制造公差或技术限制而有所偏差，并且本领域技术人员根据实际所需可以另外设计具有不同形状、大小、相对位置的区域/层。
在本公开的上下文中，当将一层/元件称作位于另一层/元件“上”时，该层/元件可以直接位于该另一层/元件上，或者它们之间可以存在居中层/元件。 另外，如果在一种朝向中一层/元件位于另一层/元件“上”，那么当调转朝向时，该层/元件可以位于该另一层/元件“下”。
图1是示出了根据本公开实施例的一对部件之间的电容的示意电路图。
如图1所示，在半导体器件如鳍式场效应晶体管(FinFET)中，可以形成部件M1和M2，这些部件可以是导电的，例如包括金属或金属性材料。例如，部件M1可以是栅电极(例如，多晶硅栅电极或者金属栅电极)，部件M2可以是邻近的接触部(例如，到与该栅电极相对应的源/漏区的接触部)。一般地，在半导体器件中，导电区域之间均被电介质材料填充。由于这种电介质材料，部件M1和M2之间可以产生(正)电容。
一般地，电容器包括极板-电介质材料-极板的配置，电介质材料可以储存电荷。常规的电容器呈“正”电容特性，即，当电介质材料中储存的电荷增多时，两个极板间的电压增大。在本公开中，将这种电介质材料称作常规电介质材料，或者直接简称为电介质材料，这与该术语在本领域的常规含义相同。与此不同，某些材料在一定状态下，可以呈现“负”电容特性，即，随着其中储存的电荷增多，极板间的电压反而表现为降低。这种材料称作“负电容材料”。例如，某些铁电材料(例如含Hf、Zr、Ba或Sr的材料，如HfZrO2、BaTiO3、KH2PO4或NBT或其任意组合等)在到达某一临界电场时，可发生极化现象。极化使得大量的束缚电荷瞬间积累在材料的表面，使铁电材料两端的电压减小。
根据本公开的实施例，可以用负电容来补偿这种正电容，以降低部件之间的总电容。图1示出了部件M1和M2之间由于电介质材料而导致的正电容C1、…、Cm′以及用于对此进行补偿的负电容Cn_1、…、Cn_m，其中，m是大于等于1的正整数，m′是大于等于1的正整数。这种负电容例如可以通过在部件M1和M2之间引入负电容材料(例如，如下所述，通过在栅侧墙(spacer)中引入负电容材料)而得到。在该示例中，将这些电容示出为并联连接的配置。
由于并联关系，部件M1和M2之间的总电容Ct可以表示为：
Figure PCTCN2016087240-appb-000001
可以看出，由于负电容的存在，相比于部件M1和M2之间完全是电介质 材料的情况，总电容Ct可以降低，甚至可以接近0(零)。优选地，Ct≥0以保持器件在电学上稳定。
根据以上分析可以看出，通过在部件之间的电介质材料中引入负电容材料，可以抑制部件之间的电容。在栅电极和接触部的情况下，特别是如下所述在形成自对准接触部从而接触部与栅侧墙物理接触的情况下，栅侧墙夹于栅电极和接触部之间，从而可以在栅侧墙中引入负电容材料。为了有效确保这种电容抑制效果，正电容与负电容优选地彼此并联。例如，可以在栅堆叠的一部分侧壁上形成由电介质材料构成的部分栅侧墙以及在栅堆叠的另一部分侧壁上形成由负电容材料构成的另一部分栅侧墙。例如，电介质材料的部分栅侧墙和负电容材料的另一部分栅侧墙可以沿着栅堆叠的侧壁上下叠置。这样，电介质材料的部分栅侧墙和负电容材料的另一部分栅侧墙均夹在栅电极和接触部之间，它们分别导致的正电容和负电容均以栅电极和接触部为极板。也即，正电容和负电容可以共享相同的极板，从而彼此并联。
这种FinFET例如可以如下制造。具体地，可以在衬底上形成鳍。例如，可以通过对衬底进行构图来形成突出的线状延伸的鳍。然后，可以在衬底上形成与鳍相交的栅堆叠。例如，可以通过在衬底上形成栅介质层，并在栅介质层上形成栅电极层来形成栅堆叠。之后，可以在栅堆叠的侧壁上形成栅侧墙。如上所述，在此可以利用电介质材料和负电容材料二者，来形成栅侧墙。例如，可以在栅堆叠的一部分侧壁上利用电介质材料形成一部分栅侧墙，且在栅堆叠的另一部分侧壁上利用负电容材料形成另一部分栅侧墙。这两部分的栅侧墙可以上下叠置。
这种形式的栅侧墙例如可以如下制造。具体地，可以先沿栅堆叠的侧壁(例如，沿其大致整个高度)，利用电介质材料形成预备侧墙。之后，可以去除该预备侧墙的上部的一定高度，得到所述一部分栅侧墙。接着，可以在该部分栅侧墙上，利用负电容材料来形成所述另一部分栅侧墙。为便于预备侧墙的去除以及负电容材料侧墙的形成，可以在形成预备侧墙之后，在衬底上形成遮蔽层，该遮蔽层可以露出一定高度的预备侧墙，而遮蔽预备侧墙的其余部分。然后，可以通过选择性刻蚀，去除预备侧墙的露出部分。接着，可以在保留遮蔽层的情况下，来形成负电容材料侧墙。根据本发明的一个实施例，例如可以这样处 理侧墙材料：对于鳍片上面的侧墙，可以由负电容材料形成，而对于位于鳍片两侧的侧墙(或者说底部位于介质层之上的侧墙)，则可以包括上下部分，它们可以分别是负电容材料侧墙和普通电介质材料侧墙。
本公开的技术可以各种方式来呈现，以下将描述其中一些示例。
图2(a)-8(b)是示出了根据本公开实施例的制造半导体器件的流程中部分阶段的截面图。
如图2(a)、2(b)、2(c)(图2(a)是俯视图，图2(b)是沿图2(a)中AA′线的截面图，以及图2(c)是沿图2(a)中BB′线的截面图)所示，提供衬底1001。在此，以硅晶片为例进行描述。但是，本公开不限于此，而是可以适用于其他各种形式的衬底，例如，锗衬底、绝缘体上半导体(SOI)衬底、化合物半导体衬底等。在衬底1001中可以形成有用于限定有源区的浅沟槽隔离(STI)1003。
在衬底1001上可以形成所需的器件，如鳍式场效应晶体管(FinFET)T1等。FinFETT1可以包括在衬底1001上形成的沿第一方向(在该示例中，图中2(a)所示的水平方向)延伸的鳍F以及沿与第一方向相交(例如，垂直)的第二方向(在该示例中，图中2(a)所示的竖直方向)延伸从而与鳍F相交的栅堆叠。栅堆叠可以包括在衬底表面上依次堆叠的栅介质层1005和栅电极层(G)1007。例如，栅介质层1005可以包括氧化物(例如，氧化硅)或高K栅介质如HfO2；栅电极层1007可以包括多晶硅或金属栅介质。此外，在鳍F的相对两端(分别位于栅堆叠位的相对两侧)，可以形成源/漏区(S/D)。
本领域技术人员知道多种方式来形成这种FinFET，例如前栅工艺或后栅工艺。
在栅堆叠的侧壁上，可以形成电介质的(预备)侧墙1009。本领域存在多种方式来形成侧墙。例如，可以在形成有栅堆叠(在后栅工艺的情况下，可以是牺牲栅堆叠)的衬底上以大致共形的方式淀积一定厚度的电介质层，然后以大致垂直于衬底表面的方向对淀积的电介质层进行反应离子刻蚀(RIE)，以去除其横向延伸部分而留下其竖直延伸部分，从而得到侧墙。例如，侧墙1009可以包括氮化物(例如，氮化硅)。
在该实施例中，为了与下述的自对准接触部的工艺相适合，还可以在器件T1的相对两侧(图中左右两侧)形成伪器件Td1和Td2。例如，这种伪器件 Td1、Td2可以形成于STI 1003上，且可以包括与器件T1实质上相同的构造。这些伪器件Td1、Td2可以与器件T1一起按照相同的工艺形成于衬底1001上。
接着，可以去除侧墙1009的一部分(在该示例中，其上部)，来形成正电容侧墙。
为此，如图3(沿图2(a)中BB′线的截面图)所示，可以在衬底上形成遮蔽层1011。例如，可以通过淀积工艺来形成遮蔽材料，遮蔽材料例如包括氧化物。可以对淀积的遮蔽材料进行平坦化处理如CMP，CMP可以停止于栅电极G。于是，所淀积的遮蔽材料可以填充各栅堆叠之间的空间。接着，可以回蚀电极的遮蔽材料，得到遮蔽层1011。例如，可以通过选择性刻蚀如RIE来回蚀。控制回蚀的量，使得回蚀后被遮蔽层1011遮蔽的侧墙部分具有所需的高度。
然后，如图4(a)(沿图2(a)中AA′线的截面图)和4(b)(沿图2(a)中BB′线的截面图)所示，可以通过选择性刻蚀(例如，湿法腐蚀，如利用热磷酸)，去除侧墙1009的露出部分。这样，在栅堆叠的侧壁上留下一部分侧墙1009，该部分侧墙形成正电容侧墙。如图中所示，留下的侧墙1009可以具有一定的高度(图中竖直方向上的维度)Hp以及一定的宽度(图中水平方向上的维度)Wp。这种高度Hp和宽度Wp可以通过调整工艺参数来予以调整。例如，可以通过控制遮蔽层1011的回蚀量来控制高度Hp，可以通过侧墙形成工艺中所淀积电介质层的厚度来调整宽度Wp。
在该示例中，示出了在鳍F的顶面上方，栅堆叠的侧壁上已经不存在侧墙1009。但是，本公开不限于此。取决于高度Hp(或者说，遮蔽层1011的高度)，在鳍F的顶面上方，栅堆叠的侧壁上也可能还留有侧墙1009。
接着，可以在如此形成的正电容侧墙上方形成负电容侧墙。
为此，如图5(a)(沿图2(a)中AA′线的截面图)和5(b)(沿图2(a)中BB′线的截面图)所示，可以通过侧墙形成工艺，利用负电容材料如HfZrO2，在栅堆叠的露出部分侧壁上形成侧墙1013。例如，可以在图4(a)和4(b)所示的结构上以大致共形的方式淀积一层负电容材料，然后以大致垂直于衬底表面的方向对淀积的负电容材料进行RIE，以去除其横向延伸部分而留下其竖直延伸部分，从而得到侧墙1013。如图中所示，该负电容侧墙1013可以具有一定的高 度(图中竖直方向上的维度)Hn以及一定的宽度(图中水平方向上的维度)Wn。这种高度Hn和宽度Wn可以通过调整工艺参数来予以调整。例如，在形成侧墙时，可以通过控制RIE的刻蚀量来控制高度Hp，可以通过所淀积的负电容电介质层的厚度来调整宽度Wp。
这样，就在栅堆叠的侧壁上形成了最终的栅侧墙，该栅侧墙包括电介质材料的侧墙1009以及负电容材料的侧墙1013。
尽管在该示例中，先形成了电介质材料的侧墙然后再形成负电容材料的侧墙，但是本公开不限于此。例如，可以先形成负电容材料的侧墙(例如，预备侧墙1009由负电容材料制成)，然后再形成电介质材料的侧墙(例如，侧墙1013由电介质材料制成)。这样，同样可以形成包括正电容侧墙和负电容侧墙的栅侧墙，只是正电容侧墙和负电容侧墙的叠置顺序不同。
之后，可以形成接触部。在此，以自对准方式来形成接触部，但是本公开不限于此。
为此，如图6(a)(沿图2(a)中AA′线的截面图)和6(b)(沿图2(a)中BB′线的截面图)所示，可以在图5(a)和5(b)所示的结构上淀积层间电介质层1015。例如，层间电介质层1015可以包括氧化物。在遮蔽层1011如上所述同样包括氧化物的情况下，可以保留遮蔽层1011用作层间电介质层，之后将它们统一示出为1015。在图2(f)中，由于层间电介质层1015和遮蔽层1011均为氧化物，因此将它们之间的界面示出为虚线。但是，需要指出的是，本公开不限于此。例如，遮蔽层1011可以被先行去除(例如，通过选择性刻蚀)，然后再淀积层间电介质层1015。可以对淀积的层间电介质层1015进行平坦化处理如化学机械抛光(CMP)，CMP可以停止于栅电极G。
在该示例中，由于伪器件Td1、Td2的存在，为了避免在不必要之处形成接触部，可以在平坦化的层间电介质层1015上，形成遮蔽层1017。例如，遮蔽层1017可以包括氮化物，厚度为约20～30nm。
之后，如图7(a)(沿图2(a)中AA′线的截面图)和7(b)(沿图2(a)中BB′线的截面图)所示，可以通过例如光刻，在遮蔽层1017中与源/漏区(S/D)相对应之处形成孔，以露出栅侧墙之间的空间。例如，遮蔽层1017中孔的侧壁可以位于栅侧墙上方。优选地，孔的侧壁相对于相应的栅堆叠向外侧伸出， 以避免随后在孔的位置处形成的接触部与栅电极之间不必要的短路。然后，经由遮蔽层1017中的孔，可以对层间电介质层1015进行选择性刻蚀如RIE，以去除栅侧墙之间的层间电介质层，从而在相邻的栅侧墙之间形成接触孔R。
对于伪器件Td1、Td2，由于其并不真正形成源/漏区，从而事实上无需接触部。遮蔽层1017可以遮蔽无需形成接触部的区域。当然，也可以不设置遮蔽层1017，而是可以直接对层间电介质层1015进行选择性刻蚀。这样，也会在伪器件Td1、Td2两侧形成接触孔。或者，甚至可以不形成层间电介质层1015，而是在形成栅侧墙之后(去除遮蔽层1011)，可以直接在各栅堆叠之间形成接触部，并在必要之处对接触部进行电隔离。
然后，如图8(a)(沿图2(a)中AA′线的截面图)和8(b)(沿图2(a)中BB′线的截面图)所示，可以在接触孔R中填充导电材料例如金属如W，来形成接触部1019。在此，示出了与源/漏区(S/D)相对应的接触部CT1和CT2。在接触孔R中填充导电材料例如可以通过在图7(a)和7(b)所示的结构上淀积导电材料以至少完全填满接触孔R、然后对淀积的导电材料进行平坦化处理如CMP(CMP可以停止于遮蔽层1017)来实现。在填充导电材料之后，还可以在接触孔的内部上形成扩散阻挡层如TiN。
在此，考虑栅电极G和接触部CT1。由于它们彼此相对且彼此之间存在电介质材料和负电容材料，从而在它们之间将产生电容Ct。在此，该电容Ct包括负电容材料侧墙所导致的负电容Cn_1以及电介质材料侧墙所导致的正电容C1。而且，由于这些电容均共享相同的极板G和CT1，所以它们呈并联关系。因此，如上所述，总电容Ct＝C1-|Cn_1|，相比栅侧墙全部为电介质材料的情况，得以降低。在该示例中，可以通过调节电介质材料侧墙的高度Hp和宽度Wp以及负电容材料侧墙的高度Hn和宽度Wn中至少一项，来调节电容值，使得Ct接近于零(但优选地大于零)。当然，也可以选择具有适当(正/负)介电常数的材料，来调节电容值。在栅电极G和接触部CT2之间，同样如此。
尽管在以上描述中将Td1和Td2示出为伪器件，但是本公开不限于此。例如，Td1和Td2中的至少一个可以是如同T1那样真正起作用的器件。此时，Td1(和/或Td2)与T1之间的空间中形成的接触部由它们共享，从而它们的源/漏区通过该公共接触部而彼此连接在一起。
此外，尽管在以上将接触部示出为自对准接触部，但是本公开不限于此。例如，接触部可以通过在电介质层中形成的通孔中填充导电材料如金属来形成。即便在这种情况下，根据本公开实施例的栅侧墙配置同样可以降低接触部与栅电极之间的寄生电容。
图9(a)-11(b)是示出了根据本公开另一实施例的制造FinFET的流程中部分阶段的截面图，其中，与图2(a)-8(b)中相同的附图标记用以表示相同的部件。该实施例与上述实施例大致相同，区别主要在于还在栅堆叠的顶部形成了负电容材料层。
具体地，可以按照以上参照图2(a)-8(b)描述的流程，在得到如图8(a)和8(b)所示的结构之后，如图9(a)(沿图2(a)中AA′线的截面图)和9(b)(沿图2(a)中BB′线的截面图)所示，可以通过选择性刻蚀，去除遮蔽层1017。这样，就露出了栅电极G。在此，仅示出了器件T1上方的遮蔽层1017被去除的情况(例如，这可以通过利用光刻胶覆盖遮蔽层1017，但露出T1上方的遮蔽层部分，并进行选择性刻蚀来实现)。当然，遮蔽层1017的其余部分(例如，Td1和/或Td2上方的部分)也可以被去除。
优选地，为了避免接触部与栅电极之间不必要的短路，还可以使栅电极进一步下凹。具体地，如图10(a)(沿图2(a)中AA′线的截面图)和10(b)(沿图2(a)中BB′线的截面图)所示，可以通过例如选择性刻蚀，使栅电极G向下凹入一定程度。
接着，如图11(a)(沿图2(a)中AA′线的截面图)和11(b)(沿图2(a)中BB′线的截面图)所示，可以在由于遮蔽层1017的去除而留下的空间(以及栅电极导致的凹入)中形成负电介质层1021。例如，这可以通过在图10(a)和10(b)所示的结构上淀积负电介质材料并对其进行平坦化处理如CMP(CMP可以停止于接触部)来实现。
如上所述，在栅电极G和接触部CT1之间，由于栅侧墙的形式，存在负电容Cn_1以及正电容C1。此外，由于负电容材料层1021，它们之间还存在负电容Cn_2。因此，总电容Ct＝C1-|Cn_1|-|Cn_2|，相比栅侧墙全部为电介质材料且顶部存在电介质材料(如上述遮蔽层1017)的情况，得以降低。在此，除了可以如上调整Hp、Wp、Hn和Wn中一项或多项之外，还可以调整负电容 材料层1021的厚度(图中竖直方向上的维度)(这例如可以通过调节栅电极下凹的程度来调节)，来调节电容值，使得Ct接近于零(但优选地大于零)。当然，也可以选择具有适当(正/负)介电常数的材料，来调节电容值。
在该示例中，由于栅电极G相对于侧墙下凹，可以有效避免栅电极与接触部之间不必要的短路。
根据本公开实施例的FinFET可以应用于各种电子设备。例如，通过集成多个这样的FinFET以及其他器件(例如，其他形式的晶体管等)，可以形成集成电路(IC)，并由此构建电子设备。因此，本公开还提供了一种包括上述半导体器件的电子设备。电子设备还可以包括与集成电路配合的显示屏幕以及与集成电路配合的无线收发器等部件。这种电子设备例如智能电话、平板电脑(PC)、个人数字助手(PDA)等。
在以上的描述中，对于各层的构图、刻蚀等技术细节并没有做出详细的说明。但是本领域技术人员应当理解，可以通过各种技术手段，来形成所需形状的层、区域等。另外，为了形成同一结构，本领域技术人员还可以设计出与以上描述的方法并不完全相同的方法。另外，尽管在以上分别描述了各实施例，但是这并不意味着各个实施例中的措施不能有利地结合使用。
以上对本公开的实施例进行了描述。但是，这些实施例仅仅是为了说明的目的，而并非为了限制本公开的范围。本公开的范围由所附权利要求及其等价物限定。不脱离本公开的范围，本领域技术人员可以做出多种替代和修改，这些替代和修改都应落在本公开的范围之内。

Claims (22)

  1. 一种鳍式场效应晶体管(FinFET)，包括：
    在衬底上形成的鳍；
    在衬底上形成的与鳍相交的栅堆叠；
    在栅堆叠的侧壁上形成的栅侧墙，其中，栅侧墙包括电介质材料和负电容材料二者。
  2. 根据权利要求1所述的FinFET，其中，栅侧墙包括在栅堆叠的一部分侧壁上形成的电介质材料层以及在栅堆叠的另一部分侧壁上形成的负电容材料层。
  3. 根据权利要求2所述的FinFET，其中，所述一部分侧壁相对于所述另一部分侧壁更靠近衬底，或反之亦然。
  4. 根据权利要求3所述的FinFET，其中，栅侧墙位于鳍顶面上方的部分均由负电容材料构成，而栅侧墙的其余部分在下部由电介质材料构成而上部由负电容材料构成。
  5. 根据权利要求1所述的FinFET，还包括：在栅堆叠顶部形成的负电容材料层。
  6. 根据权利要求5所述的FinFET，其中，栅堆叠中的栅电极相对于栅侧墙的顶端向着衬底一侧凹入，且在栅堆叠顶部形成的负电容材料层填充该凹入。
  7. 根据权利要求1所述的FinFET，还包括：
    分别在鳍的相对两端形成的源区和漏区；以及
    分别到源区和漏区的接触部。
  8. 根据权利要求7所述的FinFET，其中，接触部至少部分地由栅侧墙限定边界。
  9. 根据权利要求7所述的FinFET，其中，电介质材料和负电容材料在接触部与栅堆叠中的栅电极之间导致的总电容小于栅侧墙完全由电介质材料的情况下所导致的电容，且大于零。
  10. 根据权利要求1所述的FinFET，其中，负电容材料是含Hf、Zr、Ba 或Sr的材料。
  11. 根据权利要求10所述的FinFET，其中，负电容材料包括HfZrO2、BaTiO3、KH2PO4或NBT或其任意组合。
  12. 一种制造鳍式场效应晶体管(FinFET)的方法，包括：
    在衬底上形成鳍；
    在衬底上形成与鳍相交的栅堆叠；以及
    利用电介质材料和负电容材料二者，在栅堆叠的侧壁上形成栅侧墙。
  13. 根据权利要求12所述的方法，其中，形成栅侧墙包括：
    在栅堆叠的一部分侧壁上利用电介质材料形成一部分栅侧墙；以及
    在栅堆叠的另一部分侧壁上利用负电容材料形成另一部分栅侧墙。
  14. 根据权利要求13所述的方法，其中，
    形成所述一部分栅侧墙包括：
    沿栅堆叠的侧壁，利用电介质材料形成预备侧墙；以及
    去除该预备侧墙的上部的一定高度，得到所述一部分栅侧墙，
    形成所述另一部分栅侧墙包括：
    在所述一部分栅侧墙上，利用负电容材料形成所述另一部分栅侧墙。
  15. 根据权利要求14所述的方法，其中，去除预备侧墙的上部的一定高度包括：
    在衬底上形成遮蔽层，该遮蔽层露出所述高度的预备侧墙，而遮蔽预备侧墙的其余部分；以及
    通过选择性刻蚀，去除预备侧墙的露出部分。
  16. 根据权利要求15所述的方法，其中，形成遮蔽层包括：
    在衬底上淀积遮蔽材料，并对所淀积的遮蔽材料进行平坦化处理，其中，平坦化处理停止于栅堆叠顶部；以及
    对平坦化后的遮蔽材料进行回蚀，以露出所述高度的预备侧墙。
  17. 根据权利要求12所述的方法，还包括：
    在栅堆叠的顶部形成负电容材料层。
  18. 根据权利要求17所述的方法，还包括：
    使栅堆叠中的栅电极相对于栅侧墙的顶端向着衬底一侧凹入，其中，在栅 堆叠的顶部形成负电容材料层填充该凹入。
  19. 根据权利要求12所述的方法，其中，在衬底上存在多个这种栅堆叠，该方法还包括：
    通过在相邻栅堆叠的相对栅侧墙之间的空间内淀积导电材料，形成接触部。
  20. 根据权利要求19所述的方法，其中，相邻的栅堆叠之一是伪栅堆叠。
  21. 一种电子设备，包括如权利要求1至11中任一项所述的FinFET形成的集成电路。
  22. 根据权利要求21所述的电子设备，还包括：与所述集成电路配合的显示器以及与所述集成电路配合的无线收发器。
PCT/CN2016/087240 2016-03-17 2016-06-27 FinFET及其制造方法和包括其的电子设备 WO2017156913A1 (zh)

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