WO2023189448A1 - 積層セラミックコンデンサ、積層セラミックコンデンサの製造方法および積層セラミックコンデンサの実装構造 - Google Patents

積層セラミックコンデンサ、積層セラミックコンデンサの製造方法および積層セラミックコンデンサの実装構造 Download PDF

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WO2023189448A1
WO2023189448A1 PCT/JP2023/009471 JP2023009471W WO2023189448A1 WO 2023189448 A1 WO2023189448 A1 WO 2023189448A1 JP 2023009471 W JP2023009471 W JP 2023009471W WO 2023189448 A1 WO2023189448 A1 WO 2023189448A1
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Prior art keywords
electrode
electrode layer
plating
main surface
plating electrode
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English (en)
French (fr)
Japanese (ja)
Inventor
俊之 中村
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Murata Manufacturing Co Ltd
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Murata Manufacturing Co Ltd
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Priority to CN202380026469.XA priority Critical patent/CN118922899A/zh
Priority to JP2024511676A priority patent/JP7740521B2/ja
Publication of WO2023189448A1 publication Critical patent/WO2023189448A1/ja
Priority to US18/788,314 priority patent/US20240387112A1/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/30—Stacked capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G2/00—Details of capacitors not covered by a single one of groups H01G4/00-H01G11/00
    • H01G2/02—Mountings
    • H01G2/06—Mountings specially adapted for mounting on a printed-circuit support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/002—Details
    • H01G4/005—Electrodes
    • H01G4/012—Form of non-self-supporting electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/002—Details
    • H01G4/018—Dielectrics
    • H01G4/06—Solid dielectrics
    • H01G4/08—Inorganic dielectrics
    • H01G4/12—Ceramic dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/002—Details
    • H01G4/228—Terminals
    • H01G4/232—Terminals electrically connecting two or more layers of a stacked or rolled capacitor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/002—Details
    • H01G4/228—Terminals
    • H01G4/232—Terminals electrically connecting two or more layers of a stacked or rolled capacitor
    • H01G4/2325—Terminals electrically connecting two or more layers of a stacked or rolled capacitor characterised by the material of the terminals
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/181—Printed circuits structurally associated with non-printed electric components associated with surface mounted components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10007—Types of components
    • H05K2201/10015—Non-printed capacitor

Definitions

  • the present invention relates to a multilayer ceramic capacitor, and more particularly to a multilayer ceramic capacitor including a first end surface electrode, a second end surface electrode, a first side surface electrode, and a second side surface electrode.
  • the present invention also relates to a method of manufacturing a multilayer ceramic capacitor, which is suitable for manufacturing the multilayer ceramic capacitor of the present invention.
  • the present invention relates to a multilayer ceramic capacitor mounting structure that can be implemented using the multilayer ceramic capacitor of the present invention.
  • Multilayer ceramic capacitors called 3-terminal type are widely used for noise countermeasures and other purposes.
  • Patent Document 1 Japanese Patent Application No. 2020-167236 discloses a three-terminal multilayer ceramic capacitor.
  • the multilayer ceramic capacitor disclosed in Patent Document 1 includes a multilayer body (capacitive element) in which a plurality of ceramic layers, a plurality of first internal electrodes, and a plurality of second internal electrodes are stacked.
  • the laminate has a first main surface, a second main surface, a first end surface, a second end surface, a first side surface, and a second side surface.
  • the first main surface is a mounting surface of the multilayer ceramic capacitor on a substrate or the like.
  • the multilayer ceramic capacitor disclosed in Patent Document 1 is formed on a first end surface of a multilayer body, and extends from the first end surface to include a first main surface, a second main surface, a first side surface, and a part of the second side surface.
  • a first end surface electrode formed to cover the second end surface and extending from the second end surface to cover a portion of the first main surface, the second main surface, the first side surface, and the second side surface.
  • a second end surface electrode formed as shown in FIG. , a second side electrode formed on the second side surface and extending from the second side surface so as to cover part of the first main surface and the second main surface.
  • the first internal electrode is connected to the first end electrode and the second end electrode
  • the second internal electrode is connected to the first side electrode and the second side electrode.
  • the first end electrode, the second end electrode, the first side electrode, and the second side electrode are all formed in a multilayer structure having the same structure, and the material and thickness of each layer are different. The dimensions are also the same. Therefore, the first end electrode, the second end electrode, the first side electrode, and the second side electrode have the same thickness dimension. Therefore, the multilayer ceramic capacitor disclosed in Patent Document 1 is mounted on a substrate having a first land electrode to a fourth land electrode, a first land electrode and a first end surface electrode, a second land electrode and a second end surface electrode, and a second land electrode and a second end surface electrode.
  • the multilayer ceramic capacitor disclosed in Patent Document 1 has a first end surface electrode and a second end surface electrode connected in the middle of a power supply line or a signal line, and a first side surface electrode and a second side surface electrode connected to a ground potential. , unnecessary noise flowing through the line can be removed.
  • an object of the present invention is to provide a multilayer ceramic capacitor in which cracks and chips are suppressed from occurring in the multilayer body even when stress is applied to the mounted board and the board is bent.
  • a multilayer ceramic capacitor according to an embodiment of the present invention includes a plurality of ceramic layers laminated in the height direction. It has a plurality of first internal electrodes and a plurality of second internal electrodes, and has a first main surface and a second main surface located opposite to each other in the height direction, and opposite to each other in the length direction perpendicular to the height direction.
  • a laminate having a first end surface and a second end surface located at the same angle, and a first side surface and a second side surface located opposite to each other in the width direction perpendicular to the height direction and the length direction; , a first end surface electrode extending from the first end surface and formed to cover a portion of the first main surface, the second main surface, the first side surface, and the second side surface; a second end surface electrode extending from the two end surfaces and formed to cover the first main surface, the second main surface, the first side surface, and a part of the second side surface; a first side electrode formed on the second side surface and extending from the second side surface to cover a portion of the first main surface and the second main surface; a second side electrode formed to cover a part of the second main surface, the first internal electrode is connected to the first end surface electrode and the second end surface electrode, and the second internal electrode is connected to the first end surface electrode.
  • a multilayer ceramic capacitor connected to a side electrode and a second side electrode, wherein the first end electrode and the second end electrode are connected to a first base electrode layer and a first base electrode layer formed on the first base electrode layer, respectively.
  • the first side electrode and the second side electrode each have a second base electrode layer and a second base electrode layer.
  • a sixth plating electrode layer formed on the fifth plating electrode layer.
  • a mounting structure of a multilayer ceramic capacitor is a mounting structure of a multilayer ceramic capacitor in which a multilayer ceramic capacitor is mounted on a substrate, and the multilayer ceramic capacitor is stacked in a height direction. It has a plurality of ceramic layers, a plurality of first internal electrodes, and a plurality of second internal electrodes, and has a first main surface and a second main surface located opposite to each other in the height direction, and a length perpendicular to the height direction.
  • a laminate having a first end surface and a second end surface located opposite to each other in the width direction, and a first side surface and a second side surface located opposite to each other in the width direction perpendicular to the height direction and the length direction;
  • a first end surface electrode formed on one end surface and extending from the first end surface to cover a portion of the first main surface, second main surface, first side surface, and second side surface, and a second end surface.
  • a second end surface electrode formed on the first side surface and extending from the second end surface to cover a portion of the first main surface, the second main surface, the first side surface, and the second side surface; a first side electrode extending from the first side surface and formed to cover a portion of the first main surface and the second main surface; a first side electrode formed on the second side surface and extending from the second side surface; a first main surface and a second side electrode formed to cover a part of the second main surface, the first internal electrode is connected to the first end surface electrode and the second end surface electrode, and the second internal electrode is connected to the first end surface electrode and the second end surface electrode.
  • the electrode is connected to a first side electrode and a second side electrode, and the first end electrode and the second end electrode are connected to a first base electrode layer and a first plating layer formed on the first base electrode layer, respectively.
  • the first side electrode and the second side electrode each have a second base electrode layer, a third plating electrode layer formed on the second base electrode layer, and a third plating electrode layer.
  • the substrate has a fourth plating electrode layer formed on the top and a fifth plating electrode layer formed on the fourth plating electrode layer, and the substrate has a first land electrode and a second land electrode on the main surface.
  • a third land electrode, and a fourth land electrode are formed, a first end surface electrode and a first land electrode, a second end surface electrode and a second land electrode, a first side surface electrode and a third land electrode, and a second side surface electrode.
  • the fourth land electrodes are each bonded by a bonding material, and the thickness dimension of the bonding material existing between the first end surface electrode and the first land electrode, and the distance between the second end surface electrode and the second land electrode.
  • the thickness dimension of the bonding material existing between the first side electrode and the third land electrode and the thickness dimension of the bonding material existing between the second side electrode and the fourth land electrode are respectively It shall be larger than the thickness of the existing bonding material.
  • the multilayer ceramic capacitor according to one embodiment of the present invention even if stress is applied to the board on which it is mounted and the board is bent, the occurrence of cracks or chips in the laminate is suppressed.
  • FIG. 1 is a perspective view of a multilayer ceramic capacitor 100.
  • FIG. 2 is a cross-sectional view of a multilayer ceramic capacitor 100, showing a section XX indicated by a dashed-dotted line arrow in FIG. 1.
  • FIG. 1 is an exploded perspective view of a main part of a multilayer ceramic capacitor 100.
  • FIG. FIG. 2 is an explanatory diagram (cross-sectional view) of a mounting structure 200.
  • FIG. 5A to 5C are explanatory diagrams showing steps performed in the first manufacturing method of the multilayer ceramic capacitor 100, respectively.
  • FIGS. 6(D) to 6(F) are continuations of FIG. 5(C), and are explanatory diagrams showing steps performed in the first manufacturing method of the multilayer ceramic capacitor 100, respectively.
  • 7A to 7C are explanatory diagrams showing steps performed in the second manufacturing method of the multilayer ceramic capacitor 100, respectively.
  • 8(D) and (E) are continuations of FIG. 7(C), and are explanatory diagrams showing steps performed in the second manufacturing method of the multilayer ceramic capacitor 100, respectively.
  • 9(F) and (G) are continuations of FIG. 8(E), and are explanatory diagrams showing steps performed in the second manufacturing method of the multilayer ceramic capacitor 100, respectively.
  • FIG. 1 to 3 show a multilayer ceramic capacitor 100 according to an embodiment.
  • FIG. 1 is a perspective view of the multilayer ceramic capacitor 100.
  • FIG. 2 is a cross-sectional view of the multilayer ceramic capacitor 100, showing the section XX indicated by the dashed-dotted line arrow in FIG.
  • FIG. 3 is an exploded perspective view of essential parts of the multilayer ceramic capacitor 100.
  • the height direction T, length direction L, and width direction W of the multilayer ceramic capacitor 100 are shown in these figures, and these directions may be referred to in the following description.
  • the lamination direction of the ceramic layer 1a mentioned later is defined as the height direction T of the multilayer ceramic capacitor 100.
  • the multilayer ceramic capacitor 100 includes a multilayer body 1 having a rectangular parallelepiped shape.
  • the laminate 1 has a first main surface 1A and a second main surface 1B that face each other in the height direction T, and a first end face 1C and a second end face that face each other in the length direction L that is perpendicular to the height direction T. It has an end surface 1D, and a first side surface 1E and a second side surface 1F that face each other in the width direction W that is orthogonal to both the height direction T and the length direction L.
  • Each dimension of the laminate 1 is arbitrary, but for example, the dimension in the length direction L is about 100 ⁇ m to 5700 ⁇ m, the dimension in the width direction W is about 100 ⁇ m to 5000 ⁇ m, and the dimension in the height direction T is about 100 ⁇ m to 2500 ⁇ m. be able to.
  • the laminate 1 is composed of a plurality of ceramic layers 1a, a plurality of first internal electrodes 2, and a plurality of second internal electrodes 3 stacked together.
  • the material of the laminate 1 is arbitrary, for example, dielectric ceramics containing BaTiO 3 as a main component can be used.
  • dielectric ceramics containing other materials as main components such as CaTiO 3 , SrTiO 3 , CaZrO 3 , etc. may be used.
  • the thickness of the ceramic layer 1a is arbitrary, it can be, for example, about 0.3 ⁇ m to 2.0 ⁇ m in the effective region of capacitance formation where the first internal electrode 2 and the second internal electrode 3 are formed.
  • the number of ceramic layers 1a is arbitrary, and can be, for example, 1 to 6,000 layers in the effective region of capacitance formation where the first internal electrode 2 and second internal electrode 3 are formed.
  • the first internal electrode 2 and the second internal electrode 3 are not formed, and an outer layer (protective layer) consisting only of the ceramic layer 1a is provided.
  • the thickness of the outer layer is arbitrary, it can be, for example, 15 ⁇ m to 150 ⁇ m.
  • the thickness of the ceramic layer 1a in the outer layer region may be larger than the thickness of the ceramic layer 1a in the effective region of capacitance formation where the first internal electrode 2 and the second internal electrode 3 are formed (however, In FIGS. 1 to 3, the thickness of the ceramic layer 1a is shown to be the same in the outer layer region and the effective region).
  • the material of the ceramic layer 1a in the outer layer region may be different from the material of the ceramic layer 1a in the effective region.
  • the exploded perspective view of the main parts in FIG. 3 shows the laminate 1 disassembled into each ceramic layer 1a.
  • the first internal electrode 2 extends in the length direction L of the multilayer ceramic capacitor 100, and is drawn out to the first end surface 1C and the second end surface 1D of the multilayer body 1.
  • the second internal electrode 3 extends in the length direction L of the multilayer ceramic capacitor 100 and is drawn out to the first side surface 1E and the second side surface 1F of the multilayer body 1. Note that the first internal electrodes 2 and the second internal electrodes 3 are, in principle, alternately stacked.
  • Ni was used.
  • other metals such as Cu, Ag, Pd, and Au may be used instead of Ni.
  • Ni, Cu, Ag, Pd, Au, etc. may be alloyed with other metals.
  • the thickness of the first internal electrode 2 and the second internal electrode 3 is arbitrary, and can be, for example, about 0.3 ⁇ m to 1.5 ⁇ m.
  • a first end surface electrode 4, a second end surface electrode 5, a first side surface electrode 6, and a second side surface electrode 7 are formed on the outer surface of the laminate 1 as external electrodes.
  • the first end surface electrode 4 is formed on the first end surface 1C, extends from the first end surface 1C, and covers part of the first main surface 1A, the second main surface 1B, the first side surface 1E, and the second side surface 1F. It is formed like this.
  • the second end surface electrode 5 is formed on the second end surface 1D, extends from the second end surface 1D, and covers part of the first main surface 1A, the second main surface 1B, the first side surface 1E, and the second side surface 1F. It is formed like this.
  • the first side electrode 6 is formed on the first side surface 1E, extends from the first side surface 1E, and is formed to cover part of the first main surface 1A and the second main surface 1B.
  • the second side electrode 7 is formed on the second side surface 1F, extends from the second side surface 1F, and is formed to cover part of the first main surface 1A and the second main surface 1B.
  • the first internal electrode 2 drawn out to the first end surface 1C of the laminate 1 is connected to the first end surface electrode 4.
  • the first internal electrode 2 drawn out to the second end surface 1D of the laminate 1 is connected to the second end surface electrode 5.
  • the second internal electrode 3 drawn out to the first side surface 1E of the laminate 1 is connected to the first side electrode 6.
  • the second internal electrode 3 drawn out to the second side surface 1F of the laminate 1 is connected to the second side electrode 7.
  • the multilayer ceramic capacitor 100 includes, for example, a circuit in which a power supply line or a signal line is divided in the middle, a first end face electrode 4 is connected to one of the divided parts, a second end face electrode 5 is connected to the other part of the divided part, and the second end face electrode 5 is connected to the other divided part.
  • a circuit in which a power supply line or a signal line is divided in the middle a first end face electrode 4 is connected to one of the divided parts
  • a second end face electrode 5 is connected to the other part of the divided part
  • the second end face electrode 5 is connected to the other divided part.
  • the first end electrode 4 and the second end electrode 5 have the same multilayer structure. Specifically, as shown in FIG. 2, the first end electrode 4 and the second end electrode 5 each include a first base electrode layer 11 and a first base electrode layer formed on the outer surface of the laminate 1. 11, and a second plating electrode layer 22 formed on the outer surface of the first plating electrode layer 21.
  • Ni was used.
  • other metals such as Cu, Ag, Pd, and Au may be used instead of Ni.
  • Ni, Cu, Ag, Pd, Au, etc. may be alloyed with other metals.
  • the thickness of the first base electrode layer 11 is arbitrary, but for example, in the portion formed on the first main surface 1A or the second main surface 1B, the thickness is about 3.0 ⁇ m to 150.0 ⁇ m. It can be done. In this embodiment, the thickness dimension of the first base electrode layer 11 on the first main surface 1A or the second main surface 1B was set to 9.0 ⁇ m.
  • the thickness dimension of the first base electrode layer 11 on the first main surface 1A or the second main surface 1B is determined by the following method.
  • a completed multilayer ceramic capacitor 100 is prepared.
  • the multilayer ceramic capacitor 100 is cut at a half dimension in the width direction W, and a cross section parallel to the first side surface 1E and the second side surface 1F is observed.
  • a first end surface electrode 4 and a second end surface electrode 5 are formed at both ends in a C-shape of an alphabetic character (which may also be referred to as a C-shape of a Japanese katakana character). That is, the first end surface electrode 4 is formed on the first main surface 1A, the first end surface 1C, and the second main surface 1B.
  • the second end surface electrode 5 is formed on the first main surface 1A, the second end surface 1D, and the second main surface 1B.
  • the maximum dimension of the first base electrode layer 11 formed on the first main surface 1A of the first end surface electrode 4 and the maximum dimension of the first base electrode layer 11 formed on the second main surface 1B of the first end surface electrode 4 are determined.
  • the maximum dimension of the first base electrode layer 11 is determined.
  • the average value of these four maximum dimensions is determined, and the average value is taken as the thickness dimension on the first main surface 1A or the second main surface 1B of the first base electrode layer 11.
  • the thickness dimension of the first plating electrode layer 21 at the first main surface 1A or the second main surface 1B and the thickness dimension of the second plating electrode layer 22 at the first main surface 1A or the second main surface 1B are also the same. Find it using the following method.
  • the material of the main component of the first plating electrode layer 21 is arbitrary, in this embodiment, Ni was used.
  • the first plated electrode layer 21 mainly functions to improve solder heat resistance and bondability.
  • the thickness of the first plating electrode layer 21 is arbitrary, but for example, the thickness in the portion formed on the first main surface 1A or the second main surface 1B is about 1.0 ⁇ m to 6.0 ⁇ m. It can be done. In this embodiment, the thickness dimension of the first plating electrode layer 21 on the first main surface 1A or the second main surface 1B was set to 3.0 ⁇ m.
  • the second plated electrode layer 22 mainly functions to improve solderability.
  • the thickness of the second plating electrode layer 22 is arbitrary, but for example, in the portion formed on the first main surface 1A or the second main surface 1B, the thickness is about 1.5 ⁇ m to 6.0 ⁇ m. It can be done. In this embodiment, the thickness dimension of the first plating electrode layer 21 on the first main surface 1A or the second main surface 1B was set to 3.0 ⁇ m.
  • the total thickness dimension of the first plating electrode layer 21 and the second plating electrode layer 22 on the first main surface 1A or the second main surface 1B of the first end surface electrode 4 and the second end surface electrode 5 is , approximately 2.5 ⁇ m to 12.0 ⁇ m.
  • the total thickness of the first plating electrode layer 21 and the second plating electrode layer 22 on the first main surface 1A or the second main surface 1B of the first end surface electrode 4 and the second end surface electrode 5 is The dimension was 6.0 ⁇ m.
  • the first side electrode 6 and the second side electrode 7 have the same multilayer structure.
  • the first side electrode 6 and the second side electrode 7 include a second base electrode layer 12 and a second base electrode layer formed on the outer surface of the laminate 1, respectively. 12, a fourth plating electrode layer 24 formed on the outer surface of the third plating electrode layer 23, and a fourth plating electrode layer 24 formed on the outer surface of the fourth plating electrode layer 24. It has a fifth plating electrode layer 25 and a sixth plating electrode layer 26 formed on the outer surface of the fifth plating electrode layer 25.
  • FIG. 2 shows the second side electrode 7 and does not show the first side electrode 6, the first side electrode 6 also has the same structure as the second side electrode 7.
  • Ni was used.
  • other metals such as Cu, Ag, Pd, and Au may be used instead of Ni.
  • Ni, Cu, Ag, Pd, Au, etc. may be alloyed with other metals.
  • the thickness of the second base electrode layer 12 is arbitrary, but for example, in the portion formed on the first main surface 1A or the second main surface 1B, the thickness is about 3.0 ⁇ m to 150.0 ⁇ m. It can be done. In this embodiment, the thickness dimension of the first base electrode layer 11 on the first main surface 1A or the second main surface 1B was set to 9.0 ⁇ m.
  • the thickness dimension of the second base electrode layer 12 on the first main surface 1A or the second main surface 1B is determined by the following method.
  • a completed multilayer ceramic capacitor 100 is prepared.
  • the multilayer ceramic capacitor 100 is cut at 1/2 the length in the length direction L, and a cross section parallel to the first end surface 1C and the second end surface 1D is observed.
  • a first side electrode 6 and a second side electrode 7 are formed on both sides in a C-shape of an alphabetic character (which may also be referred to as a C-shape of a Japanese katakana character). That is, the first side electrode 6 is formed on the first main surface 1A, the first side surface 1E, and the second main surface 1B.
  • the second side electrode 7 is formed on the first main surface 1A, the second side surface 1F, and the second main surface 1B.
  • the maximum dimension of the second base electrode layer 12 formed on the first main surface 1A of the first side electrode 6 and the maximum dimension of the second base electrode layer 12 formed on the second main surface 1B of the first side electrode 6 are determined.
  • the maximum dimension of the second base electrode layer 12 is determined.
  • the average value of these four maximum dimensions is determined, and the average value is taken as the thickness dimension on the first main surface 1A or the second main surface 1B of the second base electrode layer 12.
  • the thickness dimension of the third plating electrode layer 23 at the first main surface 1A or the second main surface 1B, the thickness dimension of the fourth plating electrode layer 24 at the first main surface 1A or the second main surface 1B, the fifth The thickness dimension on the first principal surface 1A or second principal surface 1B of the plating electrode layer 25 and the thickness dimension on the first principal surface 1A or second principal surface 1B of the sixth plating electrode layer 26 are also determined in the same manner. .
  • the third plating electrode layer 23 mainly functions to improve bonding properties.
  • the thickness of the third plating electrode layer 23 is arbitrary, but for example, in the portion formed on the first main surface 1A or the second main surface 1B, the thickness is set to about 1.0 ⁇ m to 6.0 ⁇ m. It can be done. In this embodiment, the thickness dimension of the third plating electrode layer 23 on the first main surface 1A or the second main surface 1B was set to 3.0 ⁇ m.
  • the fourth plated electrode layer 24 is provided mainly to increase the thickness of the first side electrode 6 and the second side electrode 7. Note that when Sn is used as the main component material of the fourth plating electrode layer 24, since Sn is a soft material, when the multilayer ceramic capacitor 100 is mounted on the board, the multilayer body 1 of the multilayer ceramic capacitor 100 is removed from the board. The stress transmitted to the fourth plating electrode layer 24 can be effectively absorbed by the fourth plating electrode layer 24. Therefore, this contributes to suppressing the occurrence of cracks and chips in the laminate 1.
  • the thickness of the fourth plating electrode layer 24 is arbitrary, for example, the thickness may be set to about 30.0 ⁇ m to 50.0 ⁇ m in the portion formed on the first main surface 1A or the second main surface 1B. It can be done. In this embodiment, the thickness dimension of the first plating electrode layer 21 on the first main surface 1A or the second main surface 1B was set to 40.0 ⁇ m.
  • the fifth plating electrode layer 25 mainly functions to improve solder heat resistance and bondability.
  • the thickness of the fifth plating electrode layer 25 is arbitrary, but for example, in the portion formed on the first main surface 1A or the second main surface 1B, the thickness is about 1.0 ⁇ m to 6.0 ⁇ m. It can be done. In this embodiment, the thickness dimension of the first plating electrode layer 21 on the first main surface 1A or the second main surface 1B was set to 3.0 ⁇ m.
  • the sixth plating electrode layer 26 mainly functions to improve solderability.
  • the thickness of the sixth plating electrode layer 26 is arbitrary, but for example, in the portion formed on the first main surface 1A or the second main surface 1B, the thickness is about 1.5 ⁇ m to 6.0 ⁇ m. It can be done. In this embodiment, the thickness dimension of the first plating electrode layer 21 on the first main surface 1A or the second main surface 1B was set to 3.0 ⁇ m.
  • the total thickness dimension including the sixth plating electrode layer 26 is about 33.5 ⁇ m to 68.0 ⁇ m.
  • the third plating electrode layer 23, the fourth plating electrode layer 24, and the fifth plating electrode layer are formed on the first main surface 1A or the second main surface 1B of the first end electrode 4 and the second end electrode 5.
  • the total thickness dimension of 25 and the sixth plating electrode layer 26 was 49.0 ⁇ m.
  • the total thickness dimension of the first plating electrode layer 21 and the second plating electrode layer 22 on the first main surface 1A or the second main surface 1B of the first end surface electrode 4 and the second end surface electrode 5 is , about 2.5 ⁇ m to 12.0 ⁇ m.
  • the total thickness dimension including the sixth plating electrode layer 26 is about 33.5 ⁇ m to 68.0 ⁇ m.
  • the total thickness dimension of the third plating electrode layer, the fourth plating electrode layer, the fifth plating electrode layer, and the sixth plating electrode layer on the first main surface 1A or the second main surface 1B was set as 100%.
  • the total thickness dimension of the first plating electrode layer 21 and the second plating electrode layer 22 on the first main surface A is 3.68% or more and 35.8% or less, about 3.6%. In other words, it becomes about 36.0% or less.
  • the first plating electrode layer 21 and the second plating electrode layer 22 of the first end surface electrode 4 and the second end surface electrode 5 on the first main surface 1A or the second main surface 1B The total thickness dimension of the first side electrode 6, the second side electrode 7, the third plating electrode layer 23, the fourth plating electrode layer 24, the fifth plating electrode layer 25, and the sixth plating Since the total thickness dimension with the electrode layer 26 is 49.0 ⁇ m, the third plating electrode layer 23, the fourth plating electrode layer 24, and the fifth plating electrode layer on the first main surface 1A or the second main surface 1B 25 and the sixth plating electrode layer 26 as 100%, the total thickness of the first plating electrode layer 21 and the second plating electrode layer 22 on the first main surface A is , about 12.2%.
  • the thickness of the first base electrode layer 11 and the second base electrode layer 12 on the first main surface 1A or the second main surface 1B are the same, then The thickness of the first side electrode 6 and the second side electrode 7 on the second main surface 1B is 43.0 ⁇ m larger than the thickness of the first end electrode 4 and the second end electrode 5.
  • FIG. 4 shows a mounting structure 200 in which a multilayer ceramic capacitor 100 is mounted on a substrate 50.
  • FIG. 4 is an explanatory diagram (cross-sectional view) of the mounting structure 200.
  • a first land electrode 51, a second land electrode 52, a third land electrode 53, and a fourth land electrode 54 are formed on the main surface of the substrate 50.
  • the first end electrode 4 of the multilayer ceramic capacitor 100 is joined to the first land electrode 51 by solder 61
  • the second end electrode 5 is joined to the second land electrode 52 by solder 62
  • the first end electrode 5 is joined to the second land electrode 52 by solder 62.
  • the second side electrode 7 is joined to the fourth land electrode 54 by solder 64.
  • solders 61, 62, 63, and 64 are applied on the first land electrode 51, the second land electrode 52, the third land electrode 53, and the fourth land electrode 54 in advance, respectively, before creating the mounting structure 200.
  • the solder that was supplied as cream solder was melted by reflow, then cooled and solidified again.
  • the solders 61, 62, 63, and 64 each form a solder fillet at the joint portion.
  • solders 61, 62, 63, and 64 are examples of bonding materials.
  • the material of the bonding material is arbitrary and is not limited to solder, but may be other materials such as conductive resin.
  • the thickness dimensions of the first side electrode 6 and the second side electrode 7 on the first main surface 1A or the second main surface 1B are the same as those of the first end surface electrode 4 and the second end surface electrode. It is 43.0 ⁇ m larger than the thickness dimension of No. 5. Therefore, the thickness dimension of the solder 61 between the first land electrode 51 and the first end surface electrode 4 and the thickness dimension of the solder 62 between the second land electrode 52 and the second end surface electrode 5 are respectively , 43 than the thickness of the solder 63 between the third land electrode 53 and the first side electrode 6 and the thickness of the solder 64 between the fourth land electrode 54 and the second side electrode 7. .0 ⁇ m, large.
  • the thickness dimension of the solder 61 between the first land electrode 51 and the first end surface electrode 4, and the thickness dimension of the solder 61 between the second land electrode 52 and the second end surface electrode 5 are Since the thickness of the solder 62 is large, even if stress is applied to the substrate 50 and the substrate 50 is bent, the portion where the first end electrode 4 of the ceramic laminate 1 is formed, , the occurrence of cracks and chips are suppressed in the vicinity thereof, in the portion where the second end face electrode 5 is formed, and in the vicinity thereof. That is, the first end electrode 4 of the laminate 1 is formed so that the solders 61 and 62, which have a large thickness, absorb stress transmitted from the substrate 50 and reduce the stress transmitted to the laminate 1. Occurrence of cracks and chips is suppressed in the portion, the vicinity thereof, and the portion where the second end face electrode 5 is formed, and in the vicinity thereof.
  • the multilayer ceramic capacitor 100 is mainly supported on the substrate 50 by the first side electrode 6 and the second side electrode 7, and the first end electrode 4 and the second end electrode 5 are in a raised state. You can also think that it is.
  • Example 1 In order to confirm the effectiveness of the present invention, the following experiment was conducted. First, 10 multilayer ceramic capacitors according to Example 1, 10 multilayer ceramic capacitors according to Example 2, and 10 multilayer ceramic capacitors according to Comparative Example 1 were manufactured. Structures, dimensions, etc. of Example 1, Example 2, and Comparative Example 1 will be described below with reference to the cross-sectional view of multilayer ceramic capacitor 100 in FIG. 2.
  • the first plated electrode layer of the first end surface electrode 4 and the second end surface electrode 5 on the first main surface 1A or the second main surface 1B is The thickness of the electrode layer 21 was 3.0 ⁇ m, and the thickness of the second plating electrode layer 22 was 3.0 ⁇ m.
  • the thickness of the third plated electrode layer 23 of the first side electrode 6 and the second side electrode 7 on the first main surface 1A or the second main surface 1B is 3.0 ⁇ m
  • the thickness of the fourth plating electrode layer 24 was 30.0 ⁇ m
  • the thickness of the fifth plating electrode layer 25 was 3.0 ⁇ m
  • the thickness of the sixth plating electrode layer 26 was 3.0 ⁇ m.
  • the thickness of the third plated electrode layer 23 of the first side electrode 6 and the second side electrode 7 on the first main surface 1A or the second main surface 1B is 3.0 ⁇ m
  • the thickness of the fourth plating electrode layer 24 was 50.0 ⁇ m
  • the thickness of the fifth plating electrode layer 25 was 3.0 ⁇ m
  • the thickness of the sixth plating electrode layer 26 was 3.0 ⁇ m.
  • the thickness of the third plated electrode layer 23 of the first side electrode 6 and the second side electrode 7 on the first main surface 1A or the second main surface 1B is 0 ⁇ m
  • the thickness of the plating electrode layer 24 was 0 ⁇ m
  • the thickness of the fifth plating electrode layer 25 was 3.0 ⁇ m
  • the thickness of the sixth plating electrode layer 26 was 3.0 ⁇ m. That is, in the multilayer ceramic capacitor of Comparative Example 1, the third plating electrode layer 23 and the fourth plating electrode layer 24 were not formed.
  • a deflection resistance experiment was conducted on each of 30 boards on which multilayer ceramic capacitors were mounted. Specifically, a pressure rod is brought into contact with the central part of the back side of the substrate using a grip that fixes the two opposing sides (short sides) of the substrate, and the pressure rod is moved to the center of the back side of the substrate. .0 mm, 4.0 mm, 5.0 mm, 6.0 mm, and 7.0 mm were pressed against the substrate in this order to bend the substrate. Then, cracks and chips occurring in the laminate 1 of the multilayer ceramic capacitor were observed. Note that here, the amount of pushing of the pressure rod is the amount of deflection of the substrate.
  • Table 2 shows the results of the experiment. Note that the number in each column indicates the cumulative number of cracks or chips among the 10 pieces.
  • the multilayer ceramic capacitor 100 can be manufactured, for example, by a first manufacturing method shown in FIGS. 5(A) to 6(F). In the actual production line, a large number of multilayer ceramic capacitors 100 are produced and used, and the mother green laminate is cut into individual green laminates along the way. A common method is to manufacture them all at once. However, for convenience of explanation, a case where one multilayer ceramic capacitor 100 is manufactured will be described here.
  • a first internal electrode 2 and a second internal electrode 3 are formed inside, and a first base electrode layer 11 and a second base electrode layer 12 are formed at predetermined positions on the outer surface. Additionally, a laminate 1 is produced.
  • dielectric ceramic powder dielectric ceramic powder, binder resin, solvent, etc. are prepared, and these are wet mixed to produce a ceramic slurry.
  • a ceramic slurry is applied in the form of a sheet onto the carrier film using a die coater, gravure coater, microgravure coater, etc., and dried to produce a ceramic green sheet.
  • a conductive paste prepared in advance is applied (for example, printed) in a desired pattern shape.
  • no conductive paste is applied to the ceramic green sheet serving as the outer layer.
  • a mixture of a solvent, a binder resin, a metal powder (for example, Ni powder), etc. can be used as the conductive paste.
  • ceramic green sheets are laminated in a predetermined order and integrated by heat and pressure bonding to produce an unfired laminate.
  • a conductive paste prepared in advance is applied to the desired shape and thickness.
  • a mixture of a solvent, a binder resin, a metal powder, a ceramic powder, etc. can be used as the conductive paste.
  • the unfired laminate is fired in a predetermined profile to complete the laminate 1.
  • the ceramic green sheet is fired to become the ceramic layer 1a, and the conductive paste applied to the main surface of the ceramic green sheet is fired at the same time to become the first internal electrode 2, the second internal electrode 3, and the unfired
  • the conductive paste applied to the outer surface of the laminate is fired simultaneously to form the first base electrode layer 11 and the second base electrode layer 12.
  • the production of the laminate 1 and the formation of the first base electrode layer 11 and the second base electrode layer 12 are performed simultaneously by simultaneous firing, but first, the laminate 1 is produced by firing. However, after that, a conductive paste may be applied to the outer surface of the laminate 1 and baked to form the first base electrode layer 11 and the second base electrode layer 12.
  • the first base electrode layer 11 is covered with a mask 71, and the third plating electrode layer 23 is formed on the second base electrode layer 12.
  • the first base electrode layer 11 is covered with a mask 71, and the fourth plating electrode layer 24 is formed on the third plating electrode layer 23.
  • the mask 71 is removed from the first base electrode layer 11.
  • a first plating electrode layer 21 is formed on the first base electrode layer 11, and a fifth plating electrode layer 25 is formed on the fourth plating electrode layer 24 at the same time.
  • a second plating electrode layer 22 is formed on the first plating electrode layer 21, and a sixth plating electrode layer 26 is formed on the fifth plating electrode layer 25 at the same time.
  • the first end surface electrode 4, the second end surface electrode 5, the first side surface electrode 6, and the second side surface electrode 7 are formed at predetermined positions on the outer surface of the laminate 1, and the multilayer ceramic capacitor 100 is completed.
  • the multilayer ceramic capacitor 100 can also be manufactured by the second manufacturing method shown in FIGS. 7(A) to 9(G).
  • the first internal electrode 2 and the second internal electrode 3 are formed inside, as shown in FIG. 11. Fabricate the laminate 1 on which the second base electrode layer 12 is formed.
  • a portion 21a of the first plating electrode layer 21 is placed on the first base electrode layer 11
  • a third plating electrode layer 23 is placed on the second base electrode layer 12, form at the same time.
  • a seventh plating electrode layer 27 is placed on the portion 21a of the first plating electrode layer 21, a fourth plating electrode layer 24 is placed on the third plating electrode layer 23, form at the same time.
  • one end of the laminate 1 is immersed in a solvent 81, and the seventh plating electrode layer 27 on one end of the laminate 1 is peeled off and removed. , a portion 21a of the first plating electrode layer 21 is exposed at one end of the laminate 1.
  • the other end of the laminate 1 is immersed in a solvent 81, and the seventh plating electrode layer 27 on the other end of the laminate 1 is peeled off and removed. , a portion 21a of the first plating electrode layer 21 is exposed at the other end of the laminate 1.
  • a portion 21a of the first plating electrode layer 21 is grown by plating to complete the first plating electrode layer 21, and at the same time, a fifth plating electrode layer 21 is grown on the fourth plating electrode layer 24.
  • a plating electrode layer 25 is formed. Note that according to the second manufacturing method, the thickness dimension of the first plating electrode layer 21 is larger than that in the first manufacturing method.
  • a second plating electrode layer 22 is formed on the first plating electrode layer 21 and a sixth plating electrode layer 26 is formed on the fifth plating electrode layer 25 at the same time.
  • the first end surface electrode 4, the second end surface electrode 5, the first side surface electrode 6, and the second side surface electrode 7 are formed at predetermined positions on the outer surface of the laminate 1, and the multilayer ceramic capacitor 100 is completed.
  • the multilayer ceramic capacitor 100 and mounting structure 200 according to the embodiment have been described above.
  • the present invention is not limited to the content described above, and various changes can be made in accordance with the spirit of the invention.
  • the materials of the main components of the first plating electrode layer 21, the second plating electrode layer 22, the third plating electrode layer 23, the fourth plating electrode layer 24, the fifth plating electrode layer 25, and the sixth plating electrode layer 26 are all This is just an example, and any material can be changed to other materials.
  • first side electrode 6 and the second side electrode 7 were separate bodies, but the first side electrode 6 and the second side electrode 7 are It is also possible to connect and integrate at least one of the second main surface 1A and the second main surface 1B.
  • the multilayer ceramic capacitor according to one embodiment of the present invention is as described in the "Means for Solving the Problems" section.
  • the first plated electrode layer and the fifth plated electrode layer are made of the same material, and that the second plated electrode layer and the sixth plated electrode layer are made of the same material. In this case, it becomes possible to simultaneously form the first plated electrode layer and the fifth plated electrode layer, and the second plated electrode layer and the sixth plated electrode layer, thereby improving the productivity of the multilayer ceramic capacitor.
  • the third plating electrode layer is made of the same material as the first plating electrode layer and the fifth plating electrode layer
  • the fourth plating electrode layer is made of the same material as the second plating electrode layer and the sixth plating electrode layer. It is also preferable. In this case, since it is sufficient to prepare two types of plating electrode vessels, the productivity of the multilayer ceramic capacitor is improved.
  • the first plating electrode layer and the fifth plating electrode layer contain Ni as a main component
  • the second plating electrode layer and the sixth plating electrode layer contain Sn as a main component.
  • the first plating electrode layer and the fifth plating electrode layer function mainly to improve solder heat resistance and bonding properties
  • the second plating electrode layer and the sixth plating electrode layer function mainly to improve solder heat resistance and bondability. , which can primarily function to improve solderability.
  • the first plating electrode layer, the third plating electrode layer, and the fifth plating electrode layer mainly contain Ni
  • the second plating electrode layer, the fourth plating electrode layer, and the sixth plating electrode layer mainly contain Sn. It is also preferable to In this case, since it is sufficient to prepare two types of plating electrode vessels, the productivity of the multilayer ceramic capacitor is improved.
  • the total thickness dimension of the third plating electrode layer, the fourth plating electrode layer, the fifth plating electrode layer, and the sixth plating electrode layer on the first main surface or the second main surface is It is also preferable that the thickness is larger than the total thickness of the first plating electrode layer and the second plating electrode layer on the main surface.
  • solder having a sufficiently large thickness is formed directly under the first end electrode and directly under the second end electrode. Even if stress is applied to the substrate and the substrate is deflected (including twisting), the occurrence of cracks or chips in the laminate is effectively suppressed.
  • the total thickness dimension of the third plating electrode layer, the fourth plating electrode layer, the fifth plating electrode layer, and the sixth plating electrode layer on the first main surface or the second main surface is taken as 100%, the first It is also preferable that the total thickness dimension of the first plating electrode layer and the second plating electrode layer on the main surface or the second main surface is 3.6% or more and 36.0% or less. Within this range, when a multilayer ceramic capacitor is mounted on a board, even if stress is applied to the board and the board is bent, the occurrence of cracks or chips in the laminate will be well suppressed. Ru.
  • the total thickness dimension of the third plating electrode layer, the fourth plating electrode layer, the fifth plating electrode layer, and the sixth plating electrode layer on the first main surface or the second main surface is 33.5 ⁇ m or more, 68. It is also preferable that the total thickness of the first plating electrode layer and the second plating electrode layer on the first main surface or the second main surface is 2.5 ⁇ m or more and 12.0 ⁇ m or less. . Within this range, when a multilayer ceramic capacitor is mounted on a board, even if stress is applied to the board and the board is bent, the occurrence of cracks or chips in the laminate will be well suppressed. Ru.
  • the thickness dimension of the third plating electrode layer on the first main surface or the second main surface is 1.0 ⁇ m or more and 6.0 ⁇ m or less;
  • the thickness dimension of the fourth plating electrode layer on the first main surface or the second main surface is 30.0 ⁇ m or more and 50.0 ⁇ m or less, and the first plating electrode layer and the fifth plating electrode layer on the first main surface or the second main surface are
  • the thickness dimension of the plating electrode layer is 1.0 ⁇ m or more and 6.0 ⁇ m or less, respectively, and the thickness dimension of the second plating electrode layer and the sixth plating electrode layer on the first main surface or the second main surface is , respectively, are preferably 1.5 ⁇ m or more and 6.0 ⁇ m or less.
  • each plating electrode layer can fulfill its respective functions as necessary and sufficient.
  • the thickness dimensions of the first base electrode layer and the second base electrode layer on the first main surface or the second main surface are 3.0 ⁇ m or more and 150.0 ⁇ m or less, respectively. Within this range, each base electrode layer can fulfill its respective functions as necessary and sufficient.
  • the first side electrode and the second side electrode are connected to each other on at least one of the first main surface and the second main surface.
  • the multilayer ceramic capacitor functions as a three-terminal capacitor.
  • the multilayer ceramic capacitor of the present invention can be manufactured, for example, by the following manufacturing method.
  • the multilayer ceramic capacitor of the present invention can also be manufactured, for example, by the following manufacturing method.
  • These multilayer ceramic capacitor manufacturing methods include the step of producing the laminate, the first base electrode of the first end electrode, the first base electrode of the second end electrode, and the first side electrode. It is also preferable that the steps of forming the second base electrode and the second base electrode of the second side electrode are performed at the same time. In this case, productivity of the multilayer ceramic capacitor is improved.
  • the mounting structure of the multilayer ceramic capacitor according to one embodiment of the present invention is as described in the "Means for Solving the Problems" section.
  • solder can be used as the bonding material.
  • the third land electrode and the fourth land electrode are integrated into one land electrode. Since the third land electrode and the fourth land electrode are both at ground potential, they can be integrated.

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PCT/JP2023/009471 2022-04-01 2023-03-12 積層セラミックコンデンサ、積層セラミックコンデンサの製造方法および積層セラミックコンデンサの実装構造 Ceased WO2023189448A1 (ja)

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JP2024511676A JP7740521B2 (ja) 2022-04-01 2023-03-12 積層セラミックコンデンサ、積層セラミックコンデンサの製造方法および積層セラミックコンデンサの実装構造
US18/788,314 US20240387112A1 (en) 2022-04-01 2024-07-30 Multilayer ceramic capacitor, multilayer-ceramic-capacitor manufacturing method, and multilayer-ceramic-capacitor mounting structure

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WO2025204851A1 (ja) * 2024-03-27 2025-10-02 パナソニックＩｐマネジメント株式会社 セラミック部品

Citations (3)

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Publication number Priority date Publication date Assignee Title
JP2003077775A (ja) * 2001-09-05 2003-03-14 Murata Mfg Co Ltd チップ状電子部品の製造方法およびチップ状電子部品
JP2012156315A (ja) * 2011-01-26 2012-08-16 Murata Mfg Co Ltd 積層セラミック電子部品
JP2020167231A (ja) * 2019-03-28 2020-10-08 株式会社村田製作所 積層セラミックコンデンサおよび積層セラミックコンデンサの製造方法

Patent Citations (3)

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Publication number Priority date Publication date Assignee Title
JP2003077775A (ja) * 2001-09-05 2003-03-14 Murata Mfg Co Ltd チップ状電子部品の製造方法およびチップ状電子部品
JP2012156315A (ja) * 2011-01-26 2012-08-16 Murata Mfg Co Ltd 積層セラミック電子部品
JP2020167231A (ja) * 2019-03-28 2020-10-08 株式会社村田製作所 積層セラミックコンデンサおよび積層セラミックコンデンサの製造方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2025204851A1 (ja) * 2024-03-27 2025-10-02 パナソニックＩｐマネジメント株式会社 セラミック部品

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