Classifications

• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10B—ELECTRONIC MEMORY DEVICES
  • H10B12/00—Dynamic random access memory [DRAM] devices
  • H10B12/20—DRAM devices comprising floating-body transistors, e.g. floating-body cells
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
  • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
  • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
  • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
  • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
  • G11C11/403—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
  • G11C11/404—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with one charge-transfer gate, e.g. MOS transistor, per cell
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
  • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
  • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
  • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
  • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
  • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
  • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
  • G11C11/409—Read-write [R-W] circuits 
  • G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches 
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
  • G11C2211/401—Indexing scheme relating to cells needing refreshing or charge regeneration, i.e. dynamic cells
  • G11C2211/4016—Memory devices with silicon-on-insulator cells

Definitions

• the present invention relates to a semiconductor memory device.
• the channel In a normal planar MOS transistor, the channel extends in the horizontal direction along the upper surface of the semiconductor substrate. In contrast, the channel of the SGT extends in a direction perpendicular to the upper surface of the semiconductor substrate (see, for example, Non-Patent Document 1). Therefore, the SGT allows higher density semiconductor devices than planar MOS transistors.
• DRAM Dynamic Random Access Memory
• PCM Phase Change Memory
• Non-Patent Document 3 Phase Change Memory
• Non-Patent Document 4 RRAM (Resistive Random Access Memory, see, for example, Non-Patent Document 4), MRAM (Magneto-resistive Random Access Memory, for example, non-patent See Patent Document 5 ) etc.
• DRAM memory cells configured with one MOS transistor without a capacitor see, for example, Non-Patent Documents 6 and 9
• DRAM memory cells with two gate electrodes and a trench for storing carriers for example, non-patent documents 6 and 9
• Patent Document 8 a DRAM without a capacitor has a problem in that it is largely affected by the coupling of the gate electrode from the word line of the floating body and cannot provide a sufficient voltage margin.
• Twin-Transistor memory element in which one memory cell is formed using two MOS transistors in an SOI (Silicon on Insulator) layer (see, for example, Patent Documents 1 and 2).
• SOI Silicon on Insulator
• an n+ layer that separates the floating body channels of two MOS transistors and serves as a source or drain is formed in contact with an insulating layer. Since this n+ layer is in contact with the insulating layer, the floating body channels of the two MOS transistors are electrically isolated.
• a group of holes, which are signal charges, are accumulated in the floating body channel of one transistor.
• Non-Patent Document 10 The voltage of the floating body channel in which holes are accumulated changes greatly by applying a pulse voltage to the gate electrode of an adjacent MOS transistor. As a result, the operating margin between "1" and "0" during writing cannot be made sufficiently large (for example, Non-Patent Document 10).
• the present application relates to a memory device using a semiconductor element that does not have a variable resistance element or a capacitor and can be configured only with a MOS transistor.
• This application uses a single transistor-type DRAM that eliminates capacitors to solve the problems of noise caused by coupling capacitance between the word line and the body, as well as erroneous reading and erroneous rewriting of stored data due to memory instability.
• a semiconductor memory device that realizes a high-density and high-speed MOS circuit is provided.
• a memory device using a semiconductor element includes: a semiconductor body extending horizontally or standing vertically with respect to the substrate; a first impurity layer connected to one end of the semiconductor matrix; a second impurity layer connected to one end of the semiconductor base opposite to the first impurity layer; a first gate insulating layer covering a portion of the semiconductor matrix and the first impurity layer; a first gate conductor layer covering the first gate insulating layer; a second gate insulating layer covering a portion of the semiconductor matrix and the second impurity layer; a second gate conductor layer that covers the second gate insulating layer without contacting the first gate conductor layer,
• the capacitance of the MOS gate structure formed by the second gate conductor layer, the second gate insulating layer, and the semiconductor matrix is divided by the contact area of the second gate conductor layer and the second gate insulating layer.
• the value of the capacitance of the MOS gate structure formed by the first gate conductor layer, the first gate insulating layer, and the semiconductor matrix is the capacitance of the first gate conductor layer and the first gate insulating layer. Different from the value divided by the contact area, (first invention).
• voltages applied to the first impurity layer, the second impurity layer, the first gate conductor layer, and the second gate conductor layer are controlled to an operation of generating an electron group and a hole group in the semiconductor matrix by an impact ionization phenomenon or a gate-induced drain leak current by a current flowing between the first impurity layer and the second impurity layer; and the generated electron group. and out of the hole group, a part or all of either the electron group or the hole group, which are majority carriers in the semiconductor matrix, remain in the semiconductor matrix to perform a memory write operation.
• a source line is connected to the first impurity layer
• a bit line is connected to the second impurity layer
• a word line is connected to the first gate conductor layer.
• a plate line is connected to the second gate conductor layer, and a voltage is applied to each of the source line, bit line, plate line, and word line to write and/or erase the memory.
• the capacitance of the MOS gate structure formed by the second gate conductor layer, the second gate insulating layer, and the semiconductor matrix is determined by the capacitance of the MOS gate structure formed by the second gate conductor layer and the second gate insulating layer.
• the capacitance of the MOS gate structure formed by the first gate conductor layer, the first gate insulating layer, and the semiconductor matrix is divided by the contact area of the first gate conductor layer and the first gate conductor layer. It is characterized in that it is smaller than the value divided by the contact area of the gate insulating layer (fourth invention).
• the thickness of the second gate insulating layer is thicker than the thickness of the first gate insulating layer (fifth invention).
• the dependence of the threshold value of the MOS transistor region having the second gate insulating layer on the majority carrier concentration of the semiconductor matrix is the same as that of the MOS transistor region having the first gate insulating layer. It is characterized in that the dependence of the threshold value on the majority carrier concentration of the semiconductor matrix is greater than that of the majority carrier concentration (sixth invention).
• the first invention is characterized in that, when reading information, the voltage applied to the plate line connected to the second gate conductor layer is between a threshold value for writing and a threshold value for erasing. (Seventh invention).
• the variation in the threshold value of the MOS transistor region having the second gate insulating layer is greater than that of the MOS transistor region having the first gate insulating layer in the write state and the erase state. It is characterized by being large (eighth invention).
• the threshold value of the MOS transistor having the second gate insulating layer close to the bit line is always the threshold value of the MOS transistor having the first gate insulating layer close to the source line.
• FIGS. 1 to 4 The structure and operating mechanism of a memory cell using a semiconductor element according to a first embodiment of the present invention will be described with reference to FIGS. 1 to 4.
• a cell structure of a memory using a semiconductor element according to this embodiment will be described with reference to FIG.
• An additional example of the cell structure of a memory using the semiconductor element according to this embodiment will be described with reference to FIG.
• the write mechanism and carrier behavior of a memory using a semiconductor element will be described with reference to FIG. 3, and the data erase mechanism will be described with reference to FIG.
• Table 1 a change in the threshold value of the MOS transistor region in the memory cell of the semiconductor device according to the present embodiment will be explained.
• FIG. 1 shows the structure of a memory using a semiconductor element according to a first embodiment of the present invention.
• FIG. 1 shows a plan view
• (b) shows a cross-sectional view along (a) line XX'
• (c) shows a cross-sectional view along (a) line YY'.
• Above the substrate 20 (which is an example of a "substrate” in the claims), in the horizontal direction with respect to the substrate 20, a central axis having a p-type or i-type (intrinsic type) conductivity type containing acceptor impurities.
• n+ layer 1 which is an example of a "semiconductor base” in the claims
• p layer 2 which is a silicon semiconductor matrix whose vertical cross section is rectangular.
• n+ layer 2 (hereinafter, a semiconductor region containing donor impurities at a high concentration is referred to as an "n+ layer") on one side of the p layer 1 in the horizontal direction (an example of a "first impurity layer” in the claims) ).
• n+ layer 3 which is an example of a "second impurity layer” in the claims).
• a gate insulating layer 4 (which is an example of a "first gate insulating layer” in the claims) is located on a part of the surface of the p layer 1 and in contact with or near the n+ layer 2.
• a first gate conductor layer 5 (which is an example of a “first gate conductor layer” in the claims) surrounds a part of the gate insulating layer 4 and is close to the n+ layer 2.
• a gate insulating layer 6 (which is an example of a "second gate insulating layer” in the claims) formed on a part of the surface of the p layer 1 and in contact with or near the n+ layer 3 is be.
• the gate conductor layer 7 (which is an example of a "second gate conductor layer” in the claims) is in contact with the gate insulating layer 6 and is close to the n+ layer 3 without being in contact with the gate conductor layer 5.
• One dynamic flash memory cell is formed by the p layer 1, the n+ layer 2, the n+ layer 3, the gate insulating layer 4, the gate conductor layer 5, the gate insulating layer 6, and the gate conductor layer 7.
• the MOS gate capacitance with the gate conductor layer 7 as the gate electrode is the contact between the gate conductor layer 7 and the gate insulating layer 6.
• capacitor per unit area the value obtained by dividing the MOS gate capacitance by the contact area between the gate electrode and the gate insulating layer, which are its constituent elements, is referred to as "capacitance per unit area"). , is smaller than the capacitance per unit area of the MOS gate structure formed by the gate insulating layer 4 and the p-layer 1.
• the n+ layer 2 is connected to the source line SL (which is an example of the "source line” in the claims) which is a wiring conductor
• the gate conductor layer 5 is connected to the word line WL (which is an example of the "source line” in the claims) which is a wiring conductor.
• the gate conductor layer 7 is connected to a plate line PL (which is an example of a "plate line” in the claims) which is a wiring conductor.
• the n+ layer 3 is connected to a bit line BL (which is an example of a "bit line” in the claims) which is a wiring conductor.
• the memory operates by individually manipulating the potentials of the source line, bit line, plate line, and word line.
• the plurality of dynamic flash memory cells described above are arranged two-dimensionally or three-dimensionally. This memory device is hereinafter referred to as dynamic flash memory.
• the capacitance per unit area of the MOS gate structure of the gate conductor layer 7, gate insulating layer 6, and p-layer 1 is smaller than that of the gate structure formed of the gate conductor layer 5, gate insulating layer 4, and p-layer 1.
• the purpose of this is to make the dependence of the threshold value of the MOS transistor region having the gate conductor layer 7 on the majority carrier concentration of the semiconductor matrix higher than that of the MOS transistor region having the gate conductor layer 5.
• the equation that determines the threshold value includes the term Qn/Cox, and furthermore, Qn is the substrate concentration. Has square root dependence.
• Cox the greater the dependence of the threshold on the majority carrier concentration of the semiconductor matrix.
• Cox ⁇ SiO2/tox ( ⁇ SiO2 is the dielectric constant of the silicon oxide film). Therefore, in order to make the capacitance per unit area of the MOS gate structure having the gate conductor layer 7 smaller than that of the MOS gate structure having the gate conductor layer 5, it is necessary to The thickness may be made thicker than the film thickness of the gate insulating layer 4. An example of this is illustrated in FIG.
• the same effect can be achieved by using a material for the gate insulating layer 6 that has a lower dielectric constant than the gate insulating layer 4 even if the film thickness is the same. Furthermore, by combining the film thickness and dielectric constant, the capacitance per unit area can be adjusted freely.
• any insulating film used in a normal MOS process can be used for the gate insulating layers 4 and 6, such as a SiO2 film, a SiON film, a HfSiON film, or a laminated film of SiO2/SiN.
• the p layer 1 is a p-type semiconductor, but there may be a profile in the impurity concentration. Further, there may be a profile in the impurity concentration of the n+ layer 2 and the n+ layer 3.
• the p layer 1 is If it is an n-type semiconductor, the Dynac flash memory operates by using electrons as carriers for writing.
• the potential of a part of the memory cell can be changed between the gate conductor layer 5 through the gate insulating layer 4 and the gate conductor layer 7 through the gate insulating layer 6, for example, W, Pd, Ru, etc.
• It may be a metal such as Al, TiN, TaN, or WN, a metal nitride, or an alloy thereof (including silicide), for example, a laminated structure such as TiN/W/TaN, or a highly doped structure. It may also be formed from a semiconductor.
• FIG. 1 shows an example in which the p-layer 1 extends horizontally with respect to the substrate 20, a structure in which the p-layer 1 extends vertically with respect to the substrate 20 may also be used.
• gate conductor layers 4 and 6 in each memory cell are shown as being integrated in FIG. 1, they may be divided horizontally or vertically with respect to the semiconductor matrix. I don't mind.
• FIG. 2 shows the structure of a memory using the semiconductor element according to the first embodiment of the present invention.
• FIG. 2 shows a plan view
• (b) shows a cross-sectional view along line XX' in (a)
• (c) shows a cross-sectional view along line Y-Y' in (a).
• the memory cell shown in FIG. 1 has a structure in which the gate conductor layers 5 and 7 are provided on both sides of the semiconductor base body 1, it is also possible to cover the periphery of the semiconductor base body 1 with the gate conductor layers 5 and 7 as shown in FIG. .
• the gate capacitance per unit area is It is sufficient that the capacitance per unit area of the MOS gate structure formed by 1 is smaller than the capacitance per unit area.
• the cross section of the semiconductor matrix 1 is rectangular in the vertical direction. It does not matter as long as the capacitance per unit area of the structure is smaller than that of the gate conductor layer 5.
• the MOS transistor region having the gate conductor layer 5 is referred to as WL-FET
• the MOS transistor region having the gate conductor layer 7 is referred to as PL-FET.
• the majority carriers in the n+ layer 2 and the n+ layer 3 are electrons.
• n+ poly polySi containing a high concentration of is used
• p-type semiconductor is used for the p layer 1.
• 0V is input to the n+ layer 2 connected to the source line SL
• 2.5V is inputted to the n+ layer 3 connected to the bit line BL
• the gate conductor layer 7 connected to the plate line PL is inputted.
• the voltage is 4V, and 1.5V, for example, is input to the gate conductor layer 5 connected to the word line WL.
• FIG. 3(b) shows the hole group 17 in the p-layer 1 when all biases become 0V immediately after writing.
• the generated hole group 17 is the majority carrier in the p-layer 1, and is temporarily accumulated in the p-layer 1 surrounded by the depletion layer 16, and in a non-equilibrium state, it is substantially used in the WL-FET or PL-FET.
• the p-layer 1, which is the substrate, is charged to a positive bias.
• the threshold voltage of the WL-FET with the gate conductor layer 5 and the threshold voltage of the PL-FET with the gate conductor layer 7 are the same as those of the positive substrate due to the holes temporarily accumulated in the p-layer 1.
• the voltage conditions applied to the bit line BL, source line SL, word line WL, and plate line PL described above are an example for performing a write operation, and other operating voltage conditions that allow a write operation may be used.
• the voltage conditions applied to the bit line BL, source line SL, word line WL, and plate line PL are 2.5V (BL)/0V (SL)/2V (PL)/4V (WL) and 2.5V (BL)/0V (SL)/2V (PL)/4V (WL).
• Combinations such as 5V (BL)/0V (SL)/4V (PL)/1V (WL) and 0V (BL)/2.5V (SL)/V (PL)/0V (WL) are also possible.
• a gate induced drain leak (GIDL) current may be passed to generate a hole group (for example, see Non-Patent Document 8).
• the voltage applied to the bit line may be higher or lower than 0.6V, but as long as the voltage causes electron drift within the depletion layer 16, it can be adjusted.
• the voltage conditions applied to the bit line BL, source line SL, word line WL, and plate line PL are 0.6V (BL) / 0V (SL) / 0V (PL) / 3V (WL), 0V (BL) / 0.6V (SL) / 3V (PL) / 0V (WL), 0.6V (BL) / 0V (SL) / 3V (PL) / 0V (WL) Combinations such as 1.5V (BL)/0V (SL)/0V (PL)/3V (WL) are also possible, and the voltage is applied to the above bit line BL, source line SL, word line WL, and plate line PL.
• the voltage condition is an example for performing the erase operation, and may be another operating condition that allows the erase operation.
• Figure 5(a) shows the configuration of a dynamic flash memory.
• Two types are shown: WL-FET and PL-FET.
• WL is the gate voltage for the WL-FET
• PL is the gate voltage for the PL-FET.
• the gate length of the WL-FET (hereinafter referred to as Lpoly) was set to 50 nm
• the Lpoly of the PL-FET was set to 100 nm
• the concentration of the p layer was made uniform at 6x10 17 cm -3 .
• the gate length is defined as the length of the gate conductor layer in the XX' direction in FIGS. 1 and 2.
• a silicon oxide film with a thickness of 5 nm (hereinafter referred to as TOX) is used for the gate oxide film of WL-FET, and the same material is used for the gate oxide film of PL-FET, and the film thickness is 5 nm, 10 nm, and 15 nm.
• TOX silicon oxide film with a thickness of 5 nm
• Vth the thresholds for writing and erasing data
• the thickness of the gate insulating layer of the PL-FET is made thicker than that of the WL-FET to reduce the gate electrode capacitance per unit area, the dependence of the threshold value of the MOS transistor on the majority carrier concentration of the semiconductor substrate decreases. It can be seen that the fluctuation of the threshold value becomes more sensitive depending on the amount of surplus holes due to writing and erasing.
• FIG. 6(c) shows the voltage relationship in the writing state.
• the memory read conditions are exactly the same as in FIG. 6(b).
• the gate voltages of both the WL-FET and the PL-FET become equal to or higher than the threshold, both MOS transistors are turned on, current flows from BL to SL, and the memory information is recognized as "1".
• the voltage conditions applied to the bit line BL, source line SL, word line WL, and plate line PL described above are an example for performing the data read operation, and other operating voltage conditions that allow the read operation may be applied. good.
• data can be similarly read by applying 1V to the bit line BL, 0V to the source line SL, 3V to the word line WL, and 1V to the plate line PL.
• the voltage applied to the plate line PL must be between the threshold values of the PL-FET in the data erase and write states.
• the gate length of the WL-FET was 50 nm and the gate length of the PL-FET was 100 nm, but the gate length of the PL-FET is as long as there is a sufficient margin of ⁇ Vth during writing and erasing. It may be shorter, but it is necessary that the threshold of the PL-FET is always higher than the threshold of the WL-FET.
• the dynamic flash memory according to the first embodiment of the present invention includes a p-layer 1 which is a semiconductor matrix, a first impurity layer 2, a second impurity layer 3, a first gate insulating layer 4, and a second gate insulating layer. It is composed of a layer 6 , a first gate conductor layer 5 , and a second gate conductor layer 7 .
• the capacitance per unit area with the second gate conductor layer as the gate electrode is The capacitance per unit area of the MOS gate structure formed by the first gate conductor layer, the first gate insulating layer, and the p-layer 1 is set to be smaller than the capacitance per unit area.
• the dependence of the threshold value of the PL-FET, which is a MOS transistor that operates with the second gate conductor layer as the gate electrode, on carriers of the substrate can be increased, and the PL-FET can be used for data writing and erasing.
• the threshold voltage difference can be increased, and the operating voltage margin of the memory can be expanded.
• the dynamic flash memory according to the first embodiment of the present invention places emphasis on on/off for PL-FET, and cell current for WL-FET, and changes the majority carrier concentration of the semiconductor base of PL-FET and WL-FET. Since dependence can be set independently, the margin of memory operating voltage can be expanded.
• the PL-FET which is highly dependent on the majority carrier concentration of the semiconductor matrix, is located on the drain side of the WL-FET, so that the current flowing through the threshold of the WL-FET is It is possible to perform stable operation without any change. If the positional relationship is reversed, the threshold value of the WL-FET will depend on the resistance of the MOS transistor channel region of the PL-FET, and the source voltage of the WL-FET will float, resulting in a decrease in the effective gate voltage and a decrease in the substrate bias effect. For reasons such as an increase in the threshold value, the threshold value becomes unstable and stable memory operation cannot be achieved.
• the threshold value of the MOS transistor region of the WL-FET can be set lower than the threshold value of the switching MOS transistor region of a normal memory. ⁇ A large amount of current can be taken during writing, leading to high-speed operation of the memory.

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