JPWO2023181172A1 - - Google Patents
Info
- Publication number
- JPWO2023181172A1 JPWO2023181172A1 JP2024508894A JP2024508894A JPWO2023181172A1 JP WO2023181172 A1 JPWO2023181172 A1 JP WO2023181172A1 JP 2024508894 A JP2024508894 A JP 2024508894A JP 2024508894 A JP2024508894 A JP 2024508894A JP WO2023181172 A1 JPWO2023181172 A1 JP WO2023181172A1
- Authority
- JP
- Japan
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/403—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
- G11C11/404—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with one charge-transfer gate, e.g. MOS transistor, per cell
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/20—DRAM devices comprising floating-body transistors, e.g. floating-body cells
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C2211/401—Indexing scheme relating to cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C2211/4016—Memory devices with silicon-on-insulator cells
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Databases & Information Systems (AREA)
- Non-Volatile Memory (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| PCT/JP2022/013515 WO2023181172A1 (ja) | 2022-03-23 | 2022-03-23 | 半導体メモリ装置 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPWO2023181172A1 true JPWO2023181172A1 (https=) | 2023-09-28 |
Family
ID=88096889
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2024508894A Pending JPWO2023181172A1 (https=) | 2022-03-23 | 2022-03-23 |
Country Status (3)
| Country | Link |
|---|---|
| US (1) | US12317478B2 (https=) |
| JP (1) | JPWO2023181172A1 (https=) |
| WO (1) | WO2023181172A1 (https=) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2023181172A1 (ja) * | 2022-03-23 | 2023-09-28 | ユニサンティス エレクトロニクス シンガポール プライベート リミテッド | 半導体メモリ装置 |
| WO2023195047A1 (ja) * | 2022-04-04 | 2023-10-12 | ユニサンティス エレクトロニクス シンガポール プライベート リミテッド | 半導体メモリ装置 |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003188279A (ja) * | 2001-12-14 | 2003-07-04 | Toshiba Corp | 半導体メモリ装置およびその製造方法 |
| US20080054310A1 (en) * | 2006-09-01 | 2008-03-06 | Commissariat A L'energie Atomique | Capacitorless DRAM memory cell comprising a partially-depleted MOSFET device comprising a gate insulator in two parts |
| JP2008147514A (ja) * | 2006-12-12 | 2008-06-26 | Renesas Technology Corp | 半導体記憶装置 |
| JP2009252264A (ja) * | 2008-04-02 | 2009-10-29 | Toshiba Corp | 半導体記憶装置およびその駆動方法 |
| US20170330623A1 (en) * | 2016-05-12 | 2017-11-16 | Korea University Research And Business Foundation | Dual gate semiconductor memory device with vertical semiconductor column |
| US20200135863A1 (en) * | 2015-04-29 | 2020-04-30 | Zeno Semiconductor, Inc. | MOSFET and Memory Cell Having Improved Drain Current Through Back Bias Application |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2023135631A1 (ja) * | 2022-01-11 | 2023-07-20 | ユニサンティス エレクトロニクス シンガポール プライベート リミテッド | 半導体メモリ装置 |
| WO2023162036A1 (ja) * | 2022-02-22 | 2023-08-31 | ユニサンティス エレクトロニクス シンガポール プライベート リミテッド | 半導体メモリ装置 |
| WO2023181172A1 (ja) * | 2022-03-23 | 2023-09-28 | ユニサンティス エレクトロニクス シンガポール プライベート リミテッド | 半導体メモリ装置 |
| WO2023195047A1 (ja) * | 2022-04-04 | 2023-10-12 | ユニサンティス エレクトロニクス シンガポール プライベート リミテッド | 半導体メモリ装置 |
-
2022
- 2022-03-23 WO PCT/JP2022/013515 patent/WO2023181172A1/ja not_active Ceased
- 2022-03-23 JP JP2024508894A patent/JPWO2023181172A1/ja active Pending
-
2023
- 2023-03-22 US US18/187,764 patent/US12317478B2/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003188279A (ja) * | 2001-12-14 | 2003-07-04 | Toshiba Corp | 半導体メモリ装置およびその製造方法 |
| US20080054310A1 (en) * | 2006-09-01 | 2008-03-06 | Commissariat A L'energie Atomique | Capacitorless DRAM memory cell comprising a partially-depleted MOSFET device comprising a gate insulator in two parts |
| JP2008147514A (ja) * | 2006-12-12 | 2008-06-26 | Renesas Technology Corp | 半導体記憶装置 |
| JP2009252264A (ja) * | 2008-04-02 | 2009-10-29 | Toshiba Corp | 半導体記憶装置およびその駆動方法 |
| US20200135863A1 (en) * | 2015-04-29 | 2020-04-30 | Zeno Semiconductor, Inc. | MOSFET and Memory Cell Having Improved Drain Current Through Back Bias Application |
| US20170330623A1 (en) * | 2016-05-12 | 2017-11-16 | Korea University Research And Business Foundation | Dual gate semiconductor memory device with vertical semiconductor column |
Also Published As
| Publication number | Publication date |
|---|---|
| US12317478B2 (en) | 2025-05-27 |
| US20230309287A1 (en) | 2023-09-28 |
| WO2023181172A1 (ja) | 2023-09-28 |
Similar Documents
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20240924 |
|
| A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20250619 |
|
| A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 20251211 |