WO2023179507A1 - 一种高频大功率封装模组、模组的制作方法及混合基板 - Google Patents

一种高频大功率封装模组、模组的制作方法及混合基板 Download PDF

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Publication number
WO2023179507A1
WO2023179507A1 PCT/CN2023/082358 CN2023082358W WO2023179507A1 WO 2023179507 A1 WO2023179507 A1 WO 2023179507A1 CN 2023082358 W CN2023082358 W CN 2023082358W WO 2023179507 A1 WO2023179507 A1 WO 2023179507A1
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Prior art keywords
frequency
layer
insulating
power
package module
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PCT/CN2023/082358
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English (en)
French (fr)
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WO2023179507A9 (zh
Inventor
曾剑鸿
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上海沛塬电子有限公司
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Publication of WO2023179507A1 publication Critical patent/WO2023179507A1/zh
Publication of WO2023179507A9 publication Critical patent/WO2023179507A9/zh

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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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Definitions

  • the invention belongs to the field of semiconductor packaging technology, and in particular relates to a high-frequency and high-power packaging module, a manufacturing method of the module and a hybrid substrate.
  • the third-generation semiconductor GaN/SiC gradually matures, its applications are becoming more and more widespread. Compared with traditional silicon devices, its equivalent internal resistance is significantly reduced, which greatly increases the applicable power of a single semiconductor power device. At the same time, the third generation of semiconductors also has better switching characteristics, its switching losses are greatly reduced, and it is easier to operate at high frequencies. However, due to the shortcomings of existing packaging technology, it is difficult to obtain the above two advantages at the same time.
  • one of the purposes of the present invention is to provide a high-frequency and high-power package module that not only ensures heat dissipation capabilities, but also greatly reduces the loop inductance, enabling high-power and high-frequency implementation, and giving full play to the third-generation semiconductor advantages, and provides an application basis for the upgrading of its performance.
  • Another object of the present invention is to provide a manufacturing method that can realize the above-mentioned high-frequency and high-power packaging module.
  • the high-frequency and high-power in the high-frequency and high-power package module of the present invention refers to: the power of the converter using the module exceeds 10KW, and the operating frequency is higher than 100KHz; or the operation of the converter using the module The frequency is higher than 300KHz, and the power exceeds 1KW; among them, the converter using this module is preferably with a power exceeding 10KW and an operating frequency exceeding 300KHz.
  • the power of the converter using the module exceeds 10KW, and the operating frequency is higher than 100KHz; or the operation of the converter using the module
  • the frequency is higher than 300KHz, and the power exceeds 1KW; among them, the converter using this module is preferably with a power exceeding 10KW and an operating frequency exceeding 300KHz.
  • this is only a preferred application scenario and is not a limitation of the present invention.
  • the first aspect of the present invention provides a high-frequency and high-power packaging module, including: at least one power conversion bridge arm, at least one high-frequency capacitor, a circuit layer, an insulating heat-conducting plate and a plastic package;
  • the power conversion bridge arm includes at least two semiconductor power devices connected in series;
  • the high-frequency capacitor is connected in parallel with the power conversion bridge arm to form a high-frequency loop
  • the circuit layer includes a first surface, an inner electrical connection layer, a second surface and a vertical electrical connection path, and the inner electrical connection layer is electrically connected to the first surface through at least one vertical electrical connection path;
  • the insulating and heat-conducting plate includes an insulating and heat-conducting layer, and an upper metal layer and a lower metal layer respectively provided on the upper and lower surfaces of the insulating and heat-conducting layer;
  • the plastic encapsulated body fills the gap area between the second surface of the circuit layer and the upper surface of the insulating and thermally conductive plate.
  • An external electrode is provided on the second surface or side edge of the circuit layer. The external electrode is connected to the power conversion bridge arm. electrical connection;
  • the front side of the semiconductor power device is electrically connected to the first surface of the circuit layer, and the back side of the semiconductor power device is thermally or electrically connected to the lower surface of the insulating and thermally conductive plate;
  • the high-frequency capacitor is electrically connected to the first surface of the circuit layer or the second surface of the circuit layer or the lower surface of the insulating and thermally conductive plate. At least one electrode of the high-frequency capacitor is connected to at least one semiconductor power device through an inner electrical connection layer. At least one electrode is electrically connected.
  • the semiconductor power device is electrically connected to the first surface of the circuit layer through a thermal resistance electrical connection layer.
  • the thermal resistance value Rth_DietoPCB of the thermal resistance electrical connection layer satisfies the following formula: (Tcase+(TdieMAX-Tcase) ⁇ Rth_PCBtoCase/(Rth_PCBtoCase+Rth_DietoPCB)) ⁇ TpcbMax;
  • Tcase is the ambient temperature when the high-frequency high-power package module is working
  • TdieMAX is the maximum operating temperature of the semiconductor power device
  • Rth_PCBtoCase is the total equivalent thermal resistance value from the circuit layer to the upper surface of the insulating thermal conductive plate
  • TpcbMax is the circuit layer the maximum operating temperature.
  • the thermal resistance value of the thermal resistance electrical connection layer is at least 3K/W.
  • the upper surface of the insulating and heat-conducting plate is thermally connected to a radiator, and there is an air gap between the upper surface of the plastic package and the radiator.
  • the height Hc of the high-frequency capacitor satisfies the following conditions: H1 ⁇ Hc ⁇ H2;
  • H1 is the distance from the first surface of the circuit layer to the back surface of the semiconductor power device, and H2 is the distance from the first surface of the circuit layer to the lower surface of the insulating and thermally conductive layer;
  • the insulating and heat-conducting plate extends above the high-frequency capacitor; the lower metal layer located between the high-frequency capacitor and the insulating and heat-conducting layer is isolated from the high-frequency capacitor by thinning or removing it.
  • the height Hc of the high-frequency capacitor satisfies the following conditions: H2 ⁇ Hc ⁇ H3;
  • H2 is the distance from the first surface of the circuit layer to the lower surface of the insulating and thermally conductive layer
  • H3 is the distance from the first surface of the circuit layer to the upper surface of the insulating and thermally conductive layer
  • the insulating and heat-conducting plate is located above devices other than high-frequency capacitors on the second surface of the circuit layer.
  • the two electrodes of the high-frequency capacitor are electrically connected to the inner electrical connection layer and the first surface of the circuit layer through vertical electrical connection paths respectively.
  • the high-frequency capacitor when the high-frequency capacitor is electrically connected to the lower surface of the insulating heat-conducting plate, at least one electrode of the high-frequency capacitor is electrically connected to the inner electrical connection layer through an electrical connector, and the height Hc of the high-frequency capacitor satisfies The following conditions: H1 ⁇ Hc ⁇ H4;
  • H1 is the distance from the first surface of the circuit layer to the back surface of the semiconductor power device
  • H4 is the distance from the second surface of the circuit layer to the lower surface of the insulating and thermally conductive layer
  • the circuit layer located below the high-frequency capacitor is isolated from the high-frequency capacitor by thinning or removing it.
  • the power electrodes of the semiconductor power device are located on the front side thereof.
  • it also includes at least one electrical connection hole, which is used to realize electrical connection between the front electrode of the semiconductor power device and the circuit board.
  • the back electrode of the semiconductor power device is electrically connected to the first surface of the circuit layer through the lower metal layer of the insulating and thermally conductive plate and the conductive component.
  • the back electrode of the semiconductor power device is electrically connected to the front side thereof through a conductive via provided inside the device.
  • At least one power electrode of the semiconductor power device is a back power electrode, and the back power electrode is electrically connected to the first surface of the circuit layer through the lower metal layer of the insulating thermal conductive plate and the conductive component, and the lower metal layer is Thick copper layer.
  • a high heat capacity element is provided inside the circuit layer, and the high heat capacity element is thermally or electrically connected to the inner electrical connection layer.
  • the horizontal projection of the wiring in the circuit layer connected to both ends of the high-frequency capacitor partially coincides with the horizontal projection of the semiconductor power device.
  • the high-frequency and high-power packaging module further includes distributed vertical connectors, and each of the semiconductor power devices is arranged adjacent to the corresponding vertical connector.
  • the distributed vertical connectors include a first vertical connector and a second vertical connector, the diameter of the first vertical connector is larger than the diameter of the second vertical connector, and the first vertical connector is The component is arranged adjacent to the side of the high-frequency and high-power package module.
  • it also includes buffered external pins, which are used to electrically connect the high-frequency high-power package module to the customer's motherboard.
  • the buffered external pin is provided on the second surface of the circuit layer.
  • the buffered external pins are provided on side edges of the circuit layer.
  • the inner side of the buffered outer pin is welded to the side edge of the circuit layer, and the outer side of the buffered outer pin is provided with an insulating reinforcement frame.
  • an elastic insulating fixing frame is also included, and the elastic insulating fixing frame is used to make the high-frequency high-power packaging module closely contact the radiator provided on the upper surface of the insulating heat-conducting plate.
  • the elastic insulation fixed frame includes an elastic member and an insulation reinforcement frame.
  • One end of the elastic member is connected to the radiator, and the other end of the elastic member is plugged into the insulation reinforcement frame.
  • the insulation reinforcement frame passes through the edge. The limiting structure limits the position of high-frequency and high-power package modules.
  • the elastic insulating fixed frame includes an insulating reinforced frame made of elastic material.
  • the insulated reinforced frame limits the position of the high-frequency and high-power packaging module through an edge limiting structure.
  • the insulated reinforced frame uses a through-type fixing component. Connect to the customer's motherboard and radiator respectively.
  • a mounting area is formed between the second surface of the circuit layer and the customer's motherboard, and at least one circuit component is disposed in the mounting area.
  • the buffered external pins are led out through a rewiring structure.
  • a second surface protection member is also included, the second surface protection member includes a shell, a sealant and a filling body, the shell is fixed by the sealant and covers the second surface of the circuit layer, and the shell A filler is filled between the body and the second surface of the circuit layer, and the filler can be silica gel or plastic sealant;
  • the housing is provided with an outer pin through hole for buffering the outer pin to extend.
  • one end of the housing is fixedly connected to a radiator disposed on the upper surface of the insulating heat-conducting plate.
  • the high-frequency high-power package module has an extension area in the horizontal direction that is not covered by the second surface protection member, and the extension area is provided with fixing holes for fixation.
  • the buffered external pins are led out through a rewiring structure.
  • it also includes at least one copper pillar and at least one soldering pad, the copper pillar is embedded in the second surface protective component, the soldering pad is disposed on the surface of the second surface protective component and is connected with the second surface protective component. Copper posts for electrical connections.
  • the second surface protection member includes at least one multiplexing pad
  • the multiplexing pad includes at least one large deep countersunk hole, at least one small via hole and at least one soldering pad
  • the large deep countersunk hole is formed by the The outer surface of the second surface protection member is concavely formed on the second surface of the circuit board, the pad covers the surface of the large deep countersunk hole and extends outside the large deep countersunk hole, the small via hole is provided at the bottom of the large deep countersunk hole, and At least one soldering pad is electrically connected to the circuit board, and the multiplexed soldering pad is used for soldering power pins.
  • the buffered external pin is one of a through-insertion welding pin, an in-line crimping pin, a surface contact crimping pin, and a surface contact welding pin.
  • a copper pillar is provided under the front electrode of the semiconductor power device, and the height of the copper pillar is at least 30 ⁇ m.
  • the semiconductor power device has at least two different thicknesses, and corresponding copper pillars or metal balls of different heights are provided below the front electrode of the semiconductor power device.
  • the semiconductor power device has at least two different thicknesses, at least one thicker semiconductor power device is provided with copper pillars under its front electrode, and at least one thinner semiconductor power device is provided with copper pillars under its front electrode. There are metal balls.
  • the front electrode of the semiconductor power device is a thick copper electrode formed by packaging, and the height of the thick copper electrode is at least 30 ⁇ m.
  • a copper clad layer is provided above the back electrode of the semiconductor power device.
  • the semiconductor power device has at least two different thicknesses, and the copper-clad layer above the back electrode of the semiconductor power device has correspondingly different thicknesses.
  • the back electrode of the semiconductor power device is a copper-clad layered electrode formed by packaging.
  • a power electrode and a gate electrode are provided on the back side of at least one of the semiconductor chips, and the power electrode is connected to the electrostatic potential of the circuit.
  • the gate electrode of the semiconductor power device is bonded to the circuit layer through electrical connection wires, and the solder joints of the gate electrode are protected by glue dispensing.
  • the semiconductor power device is an LDMOS device with a settable substrate potential, and the substrate potential is set to the electrostatic potential of the high-frequency high-power packaging module.
  • the substrate material of the LDMOS device is sapphire.
  • At least one of the semiconductor power devices includes a normally open third-generation semiconductor power device and a low-voltage normally closed semiconductor power device, and the normally-open third-generation semiconductor power device and the low-voltage normally closed semiconductor power device Semiconductor sub-power devices are cascaded.
  • the normally-open third-generation semiconductor power devices and the low-voltage normally-closed semiconductor power devices form a semiconductor power device in the form of stacked packaging.
  • At least one of the semiconductor power devices is a normally-open power device, and the normally-open power device is provided with a low-voltage normally-closed semiconductor power device.
  • the normally-open power device and the low-voltage normally-closed semiconductor power device Devices are cascaded, and the low-voltage normally closed semiconductor power device is arranged on the second surface of the circuit layer, and the position of the low-voltage normally closed semiconductor power device is vertically corresponding to the position of the normally open power device.
  • a plurality of the power conversion bridge arms are arranged in parallel, and the DC end external electrodes and the AC end external electrodes of the power conversion bridge arms are respectively arranged on both sides of the high-frequency high-power packaging module.
  • the side edges of the plastic package are step-shaped.
  • a customer sub-board is also included.
  • the customer sub-board is used to electrically connect the external electrode to the customer main board.
  • the customer sub-board is arranged parallel to the circuit layer.
  • the customer sub-board and the circuit layer are respectively perpendicular to the customer main board. set up.
  • the DC end external electrode of the power conversion bridge arm is disposed on the side close to the customer's main board, and the AC end external electrode of the power conversion bridge arm is disposed on the side away from the customer's main board.
  • the external AC terminal electrode is electrically connected to the external AC device provided on the customer's main board through the customer's daughter board.
  • the back electrodes of the two semiconductor power devices in each of the power conversion bridge arms are electrodes with the same potential as the two DC terminals of the power conversion bridge arm.
  • the thermal conductive column is arranged on the upper surface of the insulating thermal conductive plate, and the thermal conductive column is used for liquid cooling heat dissipation.
  • the area on the upper surface of the insulating heat-conducting plate that vertically corresponds to the semiconductor power device is the first heat dissipation area, and the number density of the heat-conducting pillars in the first heat dissipation area is greater than that outside the first heat dissipation area. Set quantity density.
  • the thermal conductive column includes a metal shell and an ultra-high thermal conductivity filler, wherein the ultra-high thermal conductivity filler is provided inside the metal shell, and the ultra-high thermal conductivity filler is a carbon fiber tube, graphene sheet or phase change material. liquid.
  • the present invention discloses a high-frequency and high-power package module, which includes: at least one power conversion bridge arm, at least one high-frequency capacitor, an insulating heat-conducting plate, an electrical connection device, a plastic package, a cross-ceramic layer electrical connection component, and Common mode suppression capacitor;
  • the power conversion bridge arm includes at least two semiconductor power devices connected in series;
  • the high-frequency capacitor is connected in parallel with the power conversion bridge arm;
  • the insulating and heat-conducting plate includes an insulating and heat-conducting layer, and an upper metal layer and a lower metal layer respectively provided on the upper and lower surfaces of the insulating and heat-conducting layer;
  • At least one electrode on the front side of the semiconductor power device is led out to the outside of the high-frequency high-power packaging module through the electrical connection device, and is electrically connected to at least one electrode of the high-frequency capacitor;
  • the plastic encapsulation body fills the gap area between the front surface of the semiconductor power device and the upper surface of the insulating and thermally conductive plate;
  • One electrode of the common mode suppression capacitor is electrically connected to the upper metal layer through a cross-ceramic layer electrical connection component, and the other electrode of the common mode suppression capacitor is electrically connected to a DC end of the power conversion bridge arm;
  • the back side of the semiconductor power device is thermally or electrically connected to the lower surface of the insulating and thermally conductive plate.
  • it also includes a radiator
  • the high-frequency high-power package module is installed on a radiator, the upper surface of the insulating heat-conducting plate is thermally connected to the radiator, and the potential of the radiator is the earth;
  • the common mode suppression capacitor is used to suppress the current flowing through the heat sink to the ground due to the bridge arm AC voltage jump.
  • the common mode suppression capacitor is arranged in the gap area, at least one of the semiconductor power devices is a first power device, and the back electrode of the first power device is at the same potential as a DC end of the power conversion bridge arm.
  • one electrode of the common mode suppression capacitor is electrically connected to the upper metal layer through a cross-ceramic layer electrical connection component, and the other electrode of the common mode suppression capacitor is electrically connected to the back electrode of the first power device through the lower metal layer.
  • the cross-ceramic layer electrical connection component includes an edge electrical interconnection member, the side edge electrical interconnection member is disposed on a side edge of the insulating thermal conductive plate, and one end of the side edge electrical interconnection member is connected to the upper metal The other end of the side edge electrical interconnection is electrically connected to the common mode suppression capacitor through the lower metal layer.
  • the cross-ceramic layer electrical connection component includes a through-type electrical interconnection, the through-type electrical interconnection passes through the insulating and thermally conductive layer, and one end of the through-type electrical interconnection is electrically connected to the upper metal layer, The other end of the through-type electrical interconnection is electrically connected to the common mode suppression capacitor through the lower metal layer.
  • the cross-ceramic layer electrical connection component includes a conductive coating, the conductive coating is disposed on the side edge of the insulating thermal conductive layer and adjacent areas of its upper and lower surfaces, and one end of the conductive coating is electrically connected to the upper metal layer. , the other end of the conductive coating is electrically connected to the common mode suppression capacitor.
  • the electrical connection device is a circuit layer.
  • the circuit layer includes a first surface, an inner electrical connection layer, a second surface and a vertical electrical connection path.
  • the inner electrical connection layer passes through at least one vertical electrical connection path. electrically connected to the first surface;
  • the plastic encapsulated body fills the gap area between the second surface of the circuit layer and the upper surface of the insulating and thermally conductive plate.
  • An external electrode is provided on the second surface or side edge of the circuit layer. The external electrode is connected to the power conversion bridge arm. electrical connection;
  • the front side of the semiconductor power device is electrically connected to the first surface of the circuit layer, and the back side of the semiconductor power device is thermally or electrically connected to the lower surface of the insulating and thermally conductive plate;
  • the high-frequency capacitor is electrically connected to the first surface of the circuit layer or the second surface of the circuit layer or the lower surface of the insulating and thermally conductive plate. At least one electrode of the high-frequency capacitor is connected to at least one semiconductor power device through an inner electrical connection layer. At least one electrode is electrically connected.
  • the present invention discloses a high-frequency and high-power package module, which includes: at least one power conversion bridge arm, at least one high-frequency capacitor, an insulating heat-conducting plate, an electrical connection device, a plastic package and an external electrode;
  • the power conversion bridge arm includes at least two semiconductor power devices connected in series;
  • the high-frequency capacitor is connected in parallel with the power conversion bridge arm;
  • the insulating and heat-conducting plate includes an insulating and heat-conducting layer, and an upper metal layer and a lower metal layer respectively provided on the upper and lower surfaces of the insulating and heat-conducting layer;
  • At least one electrode on the front side of the semiconductor power device is led out to the outside of the high-frequency high-power packaging module through the electrical connection device, and is electrically connected to at least one electrode of the high-frequency capacitor;
  • the plastic encapsulation body fills the gap area between the front surface of the semiconductor power device and the upper surface of the insulating and thermally conductive plate;
  • the external electrodes include at least one pair of DC terminal external electrodes, at least one pair of AC terminal external electrodes, and at least one pair of signal terminal external electrodes;
  • the back side of the semiconductor power device is thermally or electrically connected to the lower surface of the insulating and thermally conductive plate;
  • a plurality of the power conversion bridge arms are arranged in parallel, and the DC end external electrodes and the AC end external electrodes of the power conversion bridge arms are respectively arranged on both sides of the high-frequency high-power packaging module;
  • the signal terminal external electrode is disposed between the DC terminal external electrode and the AC terminal external electrode.
  • the minimum distance between the signal terminal external electrode and the DC terminal external electrode is greater than 4 mm, and the minimum distance between the signal terminal external electrode and the AC terminal external electrode is greater than 4 mm.
  • the signal terminal external electrode is a prefabricated multi-pin strip.
  • the multi-pin strip is a flexible PCB flat line.
  • the electrical connection device is a circuit layer.
  • the circuit layer includes a first surface, an inner electrical connection layer, a second surface and a vertical electrical connection path.
  • the inner electrical connection layer passes through at least one vertical electrical connection path. electrically connected to the first surface;
  • the plastic encapsulated body fills the gap area between the second surface of the circuit layer and the upper surface of the insulating and thermally conductive plate.
  • An external electrode is provided on the second surface or side edge of the circuit layer. The external electrode is connected to the power conversion bridge arm. electrical connection;
  • the front side of the semiconductor power device is electrically connected to the first surface of the circuit layer, and the back side of the semiconductor power device is thermally or electrically connected to the lower surface of the insulating and thermally conductive plate;
  • the high-frequency capacitor is electrically connected to the first surface of the circuit layer or the second surface of the circuit layer or the lower surface of the insulating and thermally conductive plate. At least one electrode of the high-frequency capacitor is connected to at least one semiconductor power device through an inner electrical connection layer. At least one electrode is electrically connected.
  • the present invention discloses a method for manufacturing the above-mentioned high-frequency and high-power package module, which includes:
  • the high-frequency capacitor is arranged on the circuit layer or the insulating heat-conducting plate;
  • the insulating and thermally conductive plate is arranged above the semiconductor power device;
  • the gap area is molded to form the molded body, and the upper surface of the insulating and heat-conducting plate is exposed.
  • the present invention discloses a method for manufacturing the above-mentioned high-frequency and high-power package module, which includes:
  • the high-frequency capacitor is arranged on the circuit layer or the insulating heat-conducting plate;
  • the insulating and thermally conductive plate is arranged above the semiconductor power device;
  • the gap area is molded to form the molded body, and the upper surface of the insulating and heat-conducting plate is exposed.
  • the present invention discloses a method for manufacturing the above-mentioned high-frequency and high-power package module, which includes:
  • the high-frequency capacitor is arranged on the circuit layer
  • the insulating and thermally conductive plate is provided on the upper surface of the semiconductor power device;
  • the insulating and heat-conducting plate is plastic-sealed to form a second plastic package, and the upper surface of the insulating and heat-conducting plate is exposed.
  • the present invention discloses a method for manufacturing the above-mentioned high-frequency and high-power package module, which includes:
  • the buffer external pins are electrically fixed and arranged in the circuit board through holes, so that the external electrodes are electrically connected to the first surface and/or the inner electrical connection layer and/or the second surface of the circuit layer, and Extend the buffer outer pin outwardly of the second surface of the circuit layer;
  • the high-frequency capacitor is arranged on the circuit layer or the insulating heat-conducting plate;
  • the insulating and thermally conductive plate is arranged above the semiconductor power device;
  • the gap area is molded to form the molded body, and the upper surface of the insulating and heat-conducting plate is exposed.
  • the present invention discloses a method for manufacturing the above-mentioned high-frequency and high-power package module, which includes:
  • Solder and the insulating thermal conductive plate are arranged above the semiconductor power device;
  • a heating plate is placed on the upper surface of the insulating and heat-conducting plate for heating to complete welding.
  • Another aspect of the invention discloses a high-frequency and high-power packaging module, including at least three semiconductor power devices and a driver;
  • the semiconductor power devices are arranged on the same plane;
  • the driver provides a driving signal for each of the semiconductor power devices, and the projection on the plane partially coincides with the projection of each of the semiconductor power devices on the plane.
  • the circuit layer includes an opposite first surface and a second surface; the semiconductor power device is disposed on the first surface, and the driver is disposed on the second surface.
  • the wiring distance from each of the semiconductor power devices to the corresponding driving signal terminal of the driver is the same.
  • it also includes at least one high-frequency capacitor, an insulating heat-conducting plate and a plastic encapsulation body;
  • the insulating and heat-conducting plate includes an insulating and heat-conducting layer, and an upper metal layer and a lower metal layer respectively provided on the upper and lower surfaces of the insulating and heat-conducting layer;
  • the plastic encapsulated body fills the gap area between the second surface of the circuit layer and the upper surface of the insulating and thermally conductive plate.
  • An external electrode is provided on the second surface or side edge of the circuit layer. The external electrode is connected to the power conversion bridge arm. electrical connection;
  • the front side of the semiconductor power device is electrically connected to the first surface of the circuit layer, and the back side of the semiconductor power device is thermally or electrically connected to the lower surface of the insulating and thermally conductive plate;
  • the high-frequency capacitor is connected in parallel with the power conversion bridge arm to form a high-frequency loop.
  • the high-frequency capacitor is electrically connected to the first surface of the circuit layer or the second surface of the circuit layer or the lower surface of the insulating heat-conducting plate.
  • At least one electrode of the capacitor is electrically connected to at least one electrode of the at least one semiconductor power device through the inner electrical connection layer;
  • the wiring distance from each of the semiconductor power devices to the corresponding driving signal terminal of the driver is the same.
  • hybrid substrate which includes a high thermal conductivity region and a low thermal conductivity region; the hybrid substrate has opposite upper surfaces and lower surfaces;
  • the high thermal conductivity areas and low thermal conductivity areas are arranged in a horizontal direction;
  • the high thermal conductivity area is used to install a heating semiconductor device, and the heating semiconductor device is specifically arranged on the lower surface;
  • the thermal conductivity of the high thermal conductivity area is greater than the thermal conductivity of the low thermal conductivity area
  • the upper surface of the hybrid substrate is used to assemble a heat dissipation device.
  • the thermal conductivity of the high thermal conductivity region is greater than twice the thermal conductivity of the low thermal conductivity region.
  • the high thermal conductivity area is a high thermal conductivity particle array, or the high thermal conductivity area is a mixture of a high thermal conductivity particle array and a low thermal conductivity material.
  • it further includes an upper metal layer and a lower metal layer respectively provided on the upper surface and the lower surface, and the material of the high thermal conductivity area and the low thermal conductivity area is an insulating material.
  • Another aspect of the invention discloses a high-frequency and high-power packaging module, including the above-mentioned hybrid substrate, at least one power conversion bridge arm, at least one high-frequency capacitor, circuit layer and plastic package;
  • the power conversion bridge arm includes at least two semiconductor power devices connected in series;
  • the high-frequency capacitor is connected in parallel with the power conversion bridge arm to form a high-frequency loop
  • the circuit layer includes a first surface, an inner electrical connection layer, a second surface and a vertical electrical connection path, and the inner electrical connection layer is electrically connected to the first surface through at least one vertical electrical connection path;
  • the plastic encapsulation body fills the gap area between the second surface of the circuit layer and the upper surface of the hybrid substrate.
  • An external electrode is provided on the second surface or side edge of the circuit layer. The external electrode is electrically connected to the power conversion bridge arm. connect;
  • the front side of the semiconductor power device is electrically connected to the first surface of the circuit layer, and the back side of the semiconductor power device is thermally or electrically connected to the lower metal layer corresponding to the high thermal conductivity area;
  • the high-frequency capacitor is electrically connected to the first surface of the circuit layer or the second surface of the circuit layer or the lower surface of the hybrid substrate, and at least one electrode of the high-frequency capacitor is connected to at least one semiconductor power device through an inner electrical connection layer. At least one electrode is electrically connected.
  • a high-frequency and high-power packaging module including the above-mentioned hybrid substrate, at least one power conversion bridge arm and a thermal conductive column;
  • the at least one power conversion bridge arm includes at least two semiconductor power devices connected in series, and the semiconductor power devices are arranged on the lower metal layer corresponding to the high thermal conductivity area;
  • the thermal conductive pillar is provided on the upper metal layer of the hybrid substrate;
  • At least a part of the thermal conductive pillars is disposed on the upper metal layer corresponding to the high thermal conductive area.
  • At least another part of the thermal conductive pillars is disposed on the upper metal layer corresponding to the low thermal conductivity area, and the number density of the thermal conduction pillars in the high thermal conductivity area is greater than the number density of the thermal conduction pillars in the low thermal conductivity area.
  • it also includes at least one high-frequency capacitor, a circuit layer and a plastic encapsulation body;
  • the high-frequency capacitor is connected in parallel with the power conversion bridge arm to form a high-frequency loop
  • the circuit layer includes a first surface, an inner electrical connection layer, a second surface and a vertical electrical connection path, and the inner electrical connection layer is electrically connected to the first surface through at least one vertical electrical connection path;
  • the plastic encapsulation body fills the gap area between the second surface of the circuit layer and the upper surface of the hybrid substrate.
  • An external electrode is provided on the second surface or side edge of the circuit layer. The external electrode is electrically connected to the power conversion bridge arm. connect;
  • the front side of the semiconductor power device is electrically connected to the first surface of the circuit layer, and the back side of the semiconductor power device is thermally or electrically connected to the lower surface of the hybrid substrate;
  • the high-frequency capacitor is electrically connected to the first surface of the circuit layer or the second surface of the circuit layer or the lower surface of the hybrid substrate, and at least one electrode of the high-frequency capacitor is connected to at least one semiconductor power device through an inner electrical connection layer. At least one electrode is electrically connected.
  • the present invention discloses a high-frequency high-power packaging module, at least one power conversion bridge arm, a multi-layer circuit board, an insulating heat-conducting plate and a plastic package;
  • the power conversion bridge arm includes at least two semiconductor power devices connected in series;
  • the multi-layer circuit board includes opposing first and second surfaces, an inner electrical connection layer, at least two low-circuit pads and vertical electrical connection paths.
  • the inner electrical connection layer passes through at least one vertical electrical connection path. electrically connected to the first surface;
  • the insulating and heat-conducting plate includes an insulating and heat-conducting layer and opposite upper and lower surfaces;
  • the plastic encapsulated body fills the gap area between the second surface of the multi-layer circuit board and the upper surface of the insulating and heat-conducting plate.
  • An external electrode is provided on the second surface or side edge of the multi-layer circuit board. The external electrode is connected to the second surface of the multi-layer circuit board.
  • the power conversion bridge arm is electrically connected;
  • the front side of the semiconductor power device is electrically connected to the first surface of the multilayer circuit board, and the back side of the semiconductor power device is thermally or electrothermally connected to the lower surface of the insulating heat conductive plate;
  • the multi-layer circuit board couples the two DC electrodes of the power conversion bridge arm to the corresponding two low-loop pads through the first surface and the inner electrical connection layer.
  • the low-loop pads are used for Electrically connect a high-frequency capacitor to form a low loop.
  • the at least two low-circuit pads are provided on the second surface of the multilayer circuit board, and the second surface is also provided with power pins and signal pins.
  • the second surface of the circuit board is electrically connected to one surface of a customer motherboard, and a high-frequency capacitor is provided on the other surface of the customer motherboard.
  • the high-frequency capacitor is connected to the low-circuit pad through the customer motherboard. Electrical connection.
  • the upper surface of the insulating and heat-conducting plate is thermally connected to a heat dissipation device, and the heat dissipation device is assembled with the customer's motherboard through at least one fixing column.
  • the potential of at least 80% of the area on the back side of the semiconductor power device is the electrostatic potential of the high-frequency high-power package module.
  • the high-frequency and high-power package module disclosed in the first aspect of the present invention not only ensures the heat dissipation capability, but also greatly reduces the loop inductance, enabling high power and high frequency to be realized, giving full play to the advantages of third-generation semiconductors. And provides an application basis for the upgrading of its performance.
  • Figure 1 is a schematic diagram of a third-generation semiconductor packaging structure in the prior art
  • FIGS. 2A to 2I are schematic structural diagrams of high-frequency and high-power package modules disclosed in embodiments of the present invention.
  • 3A to 3C are schematic structural diagrams of a high-frequency and high-power package module disclosed in another embodiment of the present invention.
  • 4A to 4C are schematic structural diagrams of a high-frequency and high-power package module disclosed in another embodiment of the present invention.
  • 4D to 4E are schematic structural diagrams of a high-frequency high-power package module disclosed in another embodiment of the present invention.
  • Figure 5A is a schematic structural diagram of a high-frequency high-power package module disclosed in an embodiment of the present invention.
  • Figure 5B is an equivalent circuit diagram of the high-frequency high-power package module disclosed in the embodiment of the present invention.
  • 5C to 5E are schematic structural diagrams of packaging modules for semiconductor power devices of different thicknesses
  • Figure 5F is an equivalent circuit diagram of the high-frequency high-power package module disclosed in the embodiment of the present invention.
  • Figures 5G to 5J are schematic structural diagrams of high-frequency and high-power packaged modules with thermal conductive pillars
  • Figure 5K is a schematic structural diagram of a high-frequency and high-power package module with a driver
  • Figure 5L is a schematic structural diagram of a high-frequency high-power package module disclosed in another embodiment of the present invention.
  • Figure 6 is another structural schematic diagram of the high-frequency high-power package module disclosed in the embodiment of the present invention.
  • FIGS. 7A to 7E are schematic structural diagrams of the high-frequency capacitor, multi-layer circuit board, power conversion bridge arm and insulating heat-conducting plate of the high-frequency high-power package module disclosed in the embodiment of the present invention at different heights;
  • 8A to 8F are schematic flow diagrams of the manufacturing method of the high-frequency and high-power package module disclosed in the embodiment of the present invention.
  • Figure 9 is a schematic structural diagram of a high-frequency high-power package module disclosed in another embodiment of the present invention.
  • Figure 10 is a schematic structural diagram of the electrode arrangement method of the semiconductor power device of the high-frequency high-power package module disclosed in the embodiment of the present invention.
  • Figure 11 is a schematic structural diagram of a high-frequency high-power package module equipped with high heat capacity components disclosed in an embodiment of the present invention
  • 12A to 12D are schematic structural diagrams of the buffered external pins of the high-frequency high-power package module disclosed in the embodiment of the present invention when they are arranged on the second surface of the multi-layer circuit board;
  • 13A to 13D are schematic structural diagrams of the buffered external pins of the high-frequency high-power package module disclosed in the embodiment of the present invention when they are arranged on the side edges of the multi-layer circuit board;
  • 13E to 13F are schematic structural diagrams of other arrangements of buffered external pins of the high-frequency high-power package module disclosed in the embodiment of the present invention.
  • 14A to 14E are schematic flow diagrams of a method for manufacturing buffered external pins of a high-frequency high-power package module disclosed in an embodiment of the present invention
  • 15A to 15D are structural schematic diagrams of the buffered external pins of the high-frequency high-power package module disclosed in the embodiment of the present invention, which are led out through the rewiring structure;
  • Figure 16A is a schematic structural diagram of the high-frequency and high-power packaging module disclosed in the embodiment of the present invention using packaged components directly SMD to the second surface of the multi-layer circuit board;
  • Figure 16B is a schematic structural diagram of the multi-layer circuit board of the high-frequency high-power package module disclosed in the embodiment of the present invention. After the components are placed and interconnected on the second surface, the entire surface is then plastic-sealed;
  • Figure 16C is a schematic structural diagram of the multi-layer circuit board of the high-frequency high-power package module disclosed in the embodiment of the present invention. The components are placed on the second surface and interconnected, and then fixed and protected using the COB process;
  • 16D to 16F are schematic structural diagrams of the high-frequency high-power package module disclosed in the embodiment of the present invention when it is provided with a second surface protection member;
  • 17A to 17E are schematic structural diagrams of the double-sided plastic packaging of the high-frequency and high-power packaging module disclosed in the embodiment of the present invention.
  • Figure 18 is a schematic structural diagram of the electrode arrangement method of the semiconductor power device of the high-frequency high-power package module disclosed in the embodiment of the present invention.
  • 19A is an equivalent circuit diagram when the semiconductor power device of the high-frequency high-power package module disclosed by the embodiment of the present invention includes a normally open third-generation semiconductor power device and a low-voltage normally closed semiconductor power device;
  • 19B to 19D are schematic structural diagrams of the semiconductor power device of the high-frequency high-power package module disclosed in the embodiment of the present invention including a normally open third-generation semiconductor sub-power device and a low-voltage normally closed semiconductor sub-power device. ;
  • Figure 20A is an equivalent circuit diagram when the high-frequency high-power package module disclosed in the embodiment of the present invention is equipped with multiple power conversion bridge arms;
  • 20B to 20D are schematic structural diagrams of the PIN surface when the high-frequency high-power package module disclosed in the embodiment of the present invention is provided with multiple power conversion bridge arms;
  • 21A to 21B are schematic structural diagrams of the plastic package body of the high-frequency and high-power package module disclosed in the embodiment of the present invention with stepped side edges;
  • 22A to 22B are schematic structural views of the electrically insulating pin bracket of the high-frequency high-power package module disclosed in the embodiment of the present invention.
  • Figure 23 is a schematic structural diagram of the high-frequency high-power package module disclosed in the embodiment of the present invention when it is installed perpendicularly to the customer's motherboard;
  • 24A to 24D are schematic diagrams of the heat dissipation situation of the high-frequency high-power package module disclosed in the embodiment of the present invention.
  • 25A to 25E are schematic flow charts of the secondary packaging process of the high-frequency high-power packaging module disclosed in the embodiment of the present invention.
  • 26A to 26C are schematic diagrams of preventing electromagnetic interference of the high-frequency high-power package module disclosed in the embodiment of the present invention.
  • 27A to 27C are schematic diagrams of common mode noise suppression by the high-frequency high-power package module disclosed in the embodiment of the present invention.
  • 27D to 27G are schematic structural diagrams of the arrangement of common mode suppression capacitors of the high-frequency high-power package module disclosed in the embodiment of the present invention.
  • 28A to 28D are schematic flow diagrams of another manufacturing method of the high-frequency high-power package module disclosed in the embodiment of the present invention.
  • 29A to 29C are schematic structural diagrams of a high-frequency high-power package module disclosed in another embodiment of the present invention.
  • the embodiment of the present invention discloses a high-frequency and high-power package module, including: a multi-layer circuit board 2, an insulating heat-conducting plate, a plastic package 7, at least one power conversion bridge arm and at least one high-frequency capacitor. 1;
  • the multi-layer circuit board 2 here is the circuit layer, which is not limited to an independent multi-layer circuit board.
  • the wiring layer of a multi-layer circuit can also refer to the wiring layer of a multi-layer circuit, or it can also be the wiring layer with the same function formed in the module process, as follows They are all referred to as multi-layer circuit boards; the x-axis and y-axis here represent the length direction and width direction of the module, and the x-axis and y-axis constitute the horizontal plane of the module, and the z-axis represents the height of the module. The following are the same.
  • the power conversion bridge arm includes at least two series-connected semiconductor power devices Q1 and Q2.
  • the high-frequency capacitor 1 is connected in parallel with the power conversion bridge arm to form a high-frequency loop.
  • At least one power conversion bridge arm is provided on the insulating and heat-conducting plate, and the plastic package 7 fills the gap area between the multi-layer circuit board and the insulating and heat-conducting plate.
  • the front surfaces of the semiconductor power devices Q1 and Q2 are electrically connected to the multilayer circuit board, and the back surfaces of the semiconductor power devices Q1 and Q2 are thermally or electrically connected to the lower surface of the insulating heat conductive plate.
  • the multilayer circuit board in its projection direction, at least partially overlaps the semiconductor power devices Q1 and Q2 of the high-frequency circuit to which it belongs.
  • the semiconductor power device is bonded to the insulating and heat-conducting plate DBC through the bonding material 101, and its front electrode is electrically connected to the wiring layer of the insulating and heat-conducting plate through the bonding wire 102.
  • the multilayer circuit board is stacked 2 On the insulating and heat-conducting plate, the multilayer circuit board 2 is equipped with a high-frequency capacitor 1 .
  • the insulating heat-conducting board can be a directly bonded copper-clad laminate (DBC for short, DBC is also used to refer to the insulating heat-conducting board below), including an insulating heat-conducting layer 3 and an upper metal layer 4 and a lower metal layer 5, wherein the upper metal layer 4 is disposed on the insulating layer.
  • the upper surface of the thermal conductive layer 3 and the lower metal layer 5 are disposed on the lower surface of the insulating thermal conductive layer 3.
  • the insulating thermal conductive plate can be a ceramic insulating plate or a printed circuit board, but is not limited thereto.
  • the multilayer circuit board 2 and the insulating and thermally conductive plate are electrically connected through vertical connectors 103 .
  • the multi-layer circuit board 2 and the insulating heat-conducting plate are mechanically connected and electrically insulated through the plastic sealant 7, and the environmental protection capability is effectively improved.
  • the bonding material 101 in the embodiment of the present invention includes but is not limited to solder, sintered materials such as silver or copper.
  • the material of the upper metal layer 4 and the lower metal layer 5 in the embodiment of the present invention is copper.
  • the electrical connection between the insulating and thermally conductive plate and the multilayer circuit board 2 can also be realized through electrochemical metal holes 104 .
  • the front electrode of the semiconductor power device is interconnected with the multilayer circuit board 2 through the metal conductive bridge 105 .
  • the metal conductive bridge 105 can have a smaller connection impedance.
  • the connection materials between the metal conductive bridge 105 and the semiconductor power device include but are not limited to solder, sintered materials such as silver or copper.
  • the front electrode of the semiconductor power device can be directly connected to the multilayer circuit board 2 through the vertical connector 103, or can be directly interconnected with the multilayer circuit board through the protruding structure 106 provided on the metal conductive bridge.
  • the multilayer circuit board 2 can be electroplated and etched on the surface of the plastic package 7, which reduces material matching requirements and improves reliability.
  • the multilayer circuit board 2 can place components on both sides to integrate more functions.
  • a shielding layer 107 is provided within the envelope area of the high-frequency loop composed of the high-frequency capacitor 1 and the semiconductor power device, and the shielding layer 107 can be connected to a fixed potential. . As shown in FIG. 2I , the shielding layer 107 may not be connected to other potentials. For example, the shielding layer 107 may be disposed inside a multilayer circuit board. This embodiment can further reduce the loop parasitic inductance by providing the shielding layer 107 .
  • a half-bridge circuit formed by two switching elements 200 connected in series is provided on the insulating and heat-conducting plate.
  • the two switching elements 200 are respectively composed of three semiconductor power devices (such as Q1-1, Q1-2 and Q1-3 or Q2-1, Q2-2 and Q2-3) connected in parallel. In actual use, each switching element is composed of The number of semiconductor power devices is not limited to this and can be adjusted freely as needed.
  • the gates of parallel-connected chips independently increase gate-level resistance (not shown in the figure) to improve dynamic and static current sharing between parallel-connected chips.
  • Vertical connectors 103 are provided on the insulating and heat-conducting plate as needed to achieve electrical connection with the multilayer circuit board 2 .
  • Figure 3B is a schematic diagram of a stacked multi-layer circuit board.
  • the wiring Vbus+ or Vbus- connected to both ends of the high-frequency capacitor 1 on the multi-layer circuit board has a projection in the horizontal direction that is at least as large as the horizontal projection of the semiconductor power device. The projections overlap to obtain minimum loop inductance.
  • FIG 3A It can be further seen from Figure 3A that between parallel chips, such as between Q1-1, Q1-2 and Q1-3, vertical distribution can be arranged on the outside of peripheral chips Q1 and Q3 and on the wiring layer of the insulating and thermally conductive layer.
  • Connectors 103 such as D1-D4, V1-V4, to construct multiple high-frequency loops.
  • the circuit topology C1/Q1/Q2/Q3 forms a high-frequency loop
  • C2/Q3/Q2/Q4 forms another high-frequency loop
  • Figure 4B is a wiring diagram of the insulating thermal conductive plate
  • Figure 4C is a schematic diagram of a stacked multi-layer circuit board. The wiring connected to both ends of the high-frequency capacitor 1 on the multi-layer circuit board at least partially overlaps with the semiconductor power device related to the high-frequency circuit to which it belongs in the horizontal projection direction. Obtain minimum loop inductance.
  • some of the vertical conductors used to connect the insulating heat conductive plate DBC and the multi-layer circuit board 2 can adopt different diameters.
  • large-diameter vertical conductors 108 are provided at the angles of the four sides of the DBC. (i.e., the first vertical connector), thus ensuring the parallelism of the assembly of the insulating and heat-conducting plate DBC and the multilayer circuit board 2 and reducing the difficulty of subsequent assembly.
  • the parallelism difference between the insulating and heat-conducting plate DBC and the multilayer circuit board 2 may cause glue to overflow.
  • the use of large-diameter vertical conductors 108 can solve similar problems.
  • At least one large-diameter vertical conductor 108 and at least one power terminal have the same electrical properties, and the projection of the large-diameter vertical conductor 108 on the vertical plane partially overlaps with the power terminal, so that the large-diameter vertical conductor 108 The parasitic impedance in the circuit where 108 is located is reduced, improving the electrical performance of the product.
  • each semiconductor chip can be tested individually. When a failed chip is found, the failed chip can be isolated from multiple semiconductor chips in parallel by removing the corresponding vertical conductive pillars between the insulating heat conduction plate DBC and the multi-layer circuit board 2. Similarly, the power electrode of each semiconductor chip can also be individually isolated on the insulating and heat-conducting plate DBC, and connected to the multilayer circuit board 2 through the corresponding vertical conductive member 103.
  • the electrodes on the side of the semiconductor chip (ie, semiconductor power device Q1 or Q2) facing the multilayer circuit board 2 can be drilled in the multilayer circuit board 2 and the plastic packaging material 7, and metal is deposited through a metallization process. , such as copper, etc., to form electrical connection holes 121 to realize the electrical connection between the semiconductor chip and the multilayer circuit board 2 .
  • the drilling process of the electrical connection hole 121 can be realized by mechanical and laser processing.
  • the semiconductor chip can be drilled on the side facing the multi-layer circuit board 2.
  • a metal layer (such as a copper layer) is bonded to the surface through solder, sintered silver, etc., and the thickness of the bonded metal layer is greater than 50um, preferably greater than 200um.
  • a thicker metal layer can also be directly metallized on the surface of the semiconductor chip.
  • the failed chip can be isolated by not setting the corresponding electrical connection hole; or after the electrical connection hole is set, the failure found when testing the module For samples, the corresponding electrical connection holes can also be removed through mechanical, laser and chemical methods to isolate failed samples.
  • the electrodes on the side of the semiconductor chip facing the multilayer circuit board are all drilled in the multilayer circuit board 2 and the plastic packaging material 7, and metal is deposited through a metallization process to realize the electrodes and multilayer circuits. Interconnects between boards, which allows for more complete isolation of failed chips.
  • FIG. 5A and Figure 5B another embodiment of the present invention also discloses a high-frequency and high-power package module, including at least one power conversion bridge arm and at least one high-frequency capacitor 1.
  • the power conversion bridge arm includes at least two Two semiconductor power devices are connected in series, and the high-frequency capacitor 1 is connected in parallel with the power conversion bridge arm.
  • the two poles of high-frequency capacitor 1 are the Vbus+ and Vbus- poles of the DC bus.
  • the semiconductor power devices Q1 and Q2 described in the present invention include but are not limited to third-generation semiconductor power devices, such as GaN devices, SiC devices, etc.
  • the present invention directly electrically interconnects the Chip Size GaN Top surface PAD to the first surface 201 of a high-precision multi-layer circuit board 2 (PCB), in which Vbus+ or Vbus- is at least one pole , interconnecting the first surface 201 and the second surface 202 through the inner electrical connection layer (Via), so that the loop inductance becomes extremely small through the coupling of the two layers.
  • PCB high-precision multi-layer circuit board 2
  • Vbus+ or Vbus- is at least one pole
  • the present invention has the opportunity to achieve a loop inductance below 1nH, which is enough to support MHz level applications.
  • the effect can be imagined.
  • the loop inductance is guaranteed and provides a foundation for high-frequency high-speed switching.
  • at least one of the two semiconductor power devices Q1 and Q2 has at least two electrodes, such as the source electrode and the gate electrode Gate, welded to the multi-layer circuit board.
  • the back side of the GaN device is thermally interconnected to an insulating thermal conductive plate (DBC) through a material with high thermal conductivity, such as a ceramic substrate.
  • the DBC includes an insulating and thermally conductive layer 3, and an upper metal layer 4 and a lower metal layer 5 respectively disposed on the upper and lower surfaces of the insulating and thermally conductive layer 3.
  • the insulating and heat-conducting layer 3 can not only conduct heat to the module surface, but also act as electrical insulation, making it convenient to install the radiator 6 (refer to the radiator 6 shown in Figure 6).
  • the thickness of the material with high thermal conductivity needs to be relatively thick, such as 50um or even more than 200um. Therefore, when the top surfaces of the two semiconductor power devices Q1 and Q2 are connected to the DBC, try to have only one large-area PAD, such as the drain Drain or the source, to reduce the requirements for connection accuracy.
  • the height of the protrusion structure 131 or 132 on the surface of the semiconductor chip is usually between 50um and 300um, and the thickness of the metal layer of the DCB is between 100um and 500um, the range of thickness tolerances of the protrusion structure and the metal layer is limited.
  • metal balls 134 are implanted on the surface of the semiconductor chip to solve the problem of thickness tolerance.
  • the diameter of the metal ball 134 is between 100um and 1mm, and the diameter can be adjusted according to actual needs, further enhancing the ability to absorb thickness tolerances.
  • the metal ball 134 may be made of metal, such as copper, iron, nickel, iron-nickel alloy, or solder ball.
  • metal balls 134 not only have different resistivities, but also have different magnetic permeability properties, and can be used to achieve different resistances and inductances. Furthermore, the same semiconductor chip can be equipped with different alloy balls at different positions to match the needs of different parasitic parameters (i.e. resistance or inductance) in local areas of the same semiconductor chip to improve the different internal properties of the same semiconductor chip. Consistency of dynamic and static characteristics of position. Furthermore, metal balls 134 of different materials can be used to differentially arrange multiple parallel-connected semiconductor chips, which can improve the consistency of dynamic and static characteristics between multiple parallel-connected chips.
  • the electrodes on one side of all semiconductor chips in the module can be realized and connected externally using metal balls, which can further reduce the cost and development cycle of directly forming copper pillars by metallizing the chip surface. Therefore, this embodiment can further shorten the product development cycle and reduce costs.
  • the electrostatic potential electrode Source of the semiconductor chip is connected to the wiring layer of the DBC.
  • the connection area between the semiconductor chip and the DBC it is necessary to increase the connection area between the semiconductor chip and the DBC as much as possible.
  • the copper area corresponding to the source and DBC of Q2 needs to be as large as possible.
  • the gate and source of Q2 are both located on the top surface of the semiconductor device Q2.
  • the gate When the semiconductor chip is assembled with the DBC, the gate The gate is easily short-circuited with the source, so glue is applied to the solder joint between the gate lead 139 and the gate to protect the solder joint between the gate lead and the gate from being affected by the assembly of the source.
  • the high-frequency capacitor 1 is disposed on the first surface 201 of the circuit board 2 , but it is not limited thereto.
  • the high-frequency capacitor 1 can also be disposed on the second surface 202 of the circuit board 2 .
  • the gate can also be set on the DBC by welding, as shown in Figure 5G.
  • the thickness of the lower metal layer 5 and the upper metal layer 4 of the DBC cannot be too thick, for example, less than 0.1mm. This will reduce the horizontal thermal diffusion in the plane direction formed by the x-axis and y-axis of the two metal layers of the DBC. ability, it is necessary to increase the heat dissipation capacity of the vertical heat dissipation channel of the semiconductor chip in the z-axis direction.
  • a thermal conductive pillar 135 is provided on the outer surface of the insulating heat dissipation layer 3 (ie, the upper metal layer 4) corresponding to the semiconductor chip in the vertical direction, which can be used for liquid cooling. Heat dissipation or use for liquid cooling devices, as shown in Figure 5H.
  • the number of thermal conductive columns 135 can be reduced at the position of the semiconductor chip outside the horizontal plane projection, just for adjusting the direction of the liquid flow; it is even not necessary to set the thermal conductive columns 135; that is, the thermal conductive columns
  • the number density of 135 installations within the horizontal plane projection of the semiconductor chip is greater than the installation number density outside the horizontal plane projection of the semiconductor chip. Because the copper layers of the upper metal layer 4 and the lower metal layer 5 are very thin, the insulating and thermally conductive layer 3 can only be electroplated with copper on the surface of the insulating and thermally conductive material.
  • the hybrid substrate 3a is composed of two types of thermally conductive materials.
  • the projected portion of the semiconductor chip on the hybrid substrate 3a ie, the high thermal conductivity area 137
  • the remaining portion ie, the low thermal conductivity area 138
  • the thermal conductivity of the high thermal conductivity material is greater than twice the thermal conductivity of the low thermal conductivity material.
  • the highly thermally conductive material may be highly thermally conductive particles, such as an array of high-purity diamond particles, especially an array of neatly arranged diamond particles mixed with ceramic materials.
  • the structure of the hybrid substrate 3a disclosed in this embodiment is applicable to all embodiments disclosed in the present invention, and is also applicable to thick copper DBC solutions and other traditional packaging solutions.
  • this embodiment has a three-dimensional structure, that is, one side of the insulating and heat-conducting plate is used for heat dissipation, and the other side is used for electrical connection. Therefore, the heat dissipation capacity cannot be upgraded through double-sided heat dissipation, and further processing is required on the heat dissipation surface.
  • the Die Bond of the semiconductor chip shown in Figure 5I can also use the sintered silver process to improve the high junction temperature operation capability and further improve the heat dissipation capability.
  • the hybrid substrate 3a may also include an upper metal layer 4 and a lower metal layer 5.
  • the bottom surface of the lower metal layer 5 is connected to the high thermal density power semiconductor chip Q10 through a high thermal conductivity interconnection 144.
  • the high thermal conductivity interconnect 144 can be sintered silver, and the high thermal density power semiconductor chip Q10 is fixed to the hybrid substrate 3a through sintering; the top surface of the hybrid substrate 3a is connected to the thermal conductive pillar 135 through the high thermal conductive interconnect 144, and the thermal conductive pillar 135 is generally used Copper material has a thermal conductivity of 400W/(m ⁇ K).
  • the thermal conductive column 135 is made of a carbon fiber tube or a composite body.
  • the composite body here can be a metal shell 143 with high thermal conductivity wrapped with an ultra-high thermal conductivity filler 145 .
  • the metal shell 143 can be made of copper material, and the ultra-high thermal conductivity filler 145 can be carbon fiber tubes, graphene sheets or phase change liquids (heat pipes).
  • the structure shown in Figure 5J conducts the heat generated by the high thermal density power semiconductor chip to the outer surface of the module, and then conducts it to the surface of the thermal conductive columns 135 by multiple high thermal conductivity coefficients.
  • the surface of the thermal conductive columns follows the cooling liquid flow (Cooling Liquid). Perform heat exchange to achieve efficient heat dissipation.
  • the hybrid substrate disclosed in the present invention can be applied to all the embodiments disclosed in the present invention, and can also be applied to other embodiments, as long as it meets the above technical characteristics.
  • the present invention also discloses an embodiment of parallel connection of multiple chips under high-power applications, as shown in Figure 5K.
  • Traditional multi-chip parallel connection often adopts a package structure in which the multi-chip and its driver are arranged on the same plane, which makes the distance between the driver and each chip unequal, resulting in inconsistent driving signals received by each chip, making multi-chip parallel connection Then uneven flow occurs.
  • the invention discloses a three-dimensional package in which multiple chips are connected in parallel, which can solve the consistency problem of parallel driving of multiple chips.
  • the multi-layer circuit board 2 is removed, and the driver is placed in the center of four wafers arranged in a 2x2 arrangement, that is, the projection of the driver on the first surface is the same as the projection of each semiconductor chip on the first surface.
  • the projections are partially overlapped, so that the wiring distance between each driver output pin and the gate of the corresponding chip is equal and the shortest distance; it can also be evenly routed through the wiring layer of the multi-layer circuit board 2 to improve each driver
  • the consistency of the circuit can achieve current sharing between each chip and achieve high-speed driving.
  • One high-current driver can be used to drive multiple semiconductor chips, or each semiconductor chip can be driven by its own driver.
  • the current of each semiconductor chip can also be sampled simultaneously, and the sampled current information can be fed back to the driver to make real-time differential adjustments to the drive of each semiconductor chip to achieve active current sharing control.
  • the number of semiconductor wafers here is not limited to four, but can also be three or other, as long as the projection of the driver on the first surface 201 of the multilayer circuit board is consistent with the projection of each semiconductor chip on the first surface of the multilayer circuit board.
  • the projections on 201 can all partially overlap.
  • the semiconductor wafer uses LD MOS whose substrate potential can be flexibly set, such as low-voltage GaN MOS, or GaN MOS using electrically insulating materials such as ceramics (sapphire) as the substrate.
  • the substrate of this type of semiconductor chip is thermally connected to the lower metal layer of the DBC, and the pins thermally connected to the lower metal layer are set to electrostatic potential, such as Vbus+ or Vbus- or power GND.
  • the high-frequency high-power package module disclosed in the embodiment of the present invention also includes a plastic package 7.
  • the thinnest plastic package 7 can be controlled between the upper surface of the insulating heat conductive plate DBC and the first surface 201 of the multi-layer circuit board 2, and realizes Safety insulation capability.
  • the plastic encapsulation body 7 fills the gap area between the first surface 201 of the multi-layer circuit board and the upper surface of the insulating and heat-conducting plate.
  • the upper surface of the insulating and heat-conducting plate is exposed, and the second surface 202 of the multi-layer circuit board and The side edges are exposed, and an external electrode 11 is provided on the second surface 202 or the side edge of the multilayer circuit board.
  • the external electrode 11 is electrically connected to the power conversion bridge arm.
  • This embodiment greatly improves the mechanical strength and can support thinner DBCs, such as 0.4mm or less insulation thickness. Compared with the silicone package in Figure 1, a thickness of at least 0.6mm can achieve lower thermal resistance, which is reduced by 30%. Above, support greater power.
  • the front side (i.e., the Bottom side) of the semiconductor power device of the high-frequency high-power package module disclosed in the embodiment of the present invention is electrically connected to the first surface 201 of the multilayer circuit board, and the back side (i.e., the Top side) of the semiconductor power device is insulated and thermally conductive.
  • the lower surface 302 of the board is thermally connected or electrically thermally connected.
  • the thermal interconnection between the semiconductor power device and the DBC is preferably welded. Therefore, the backside of the semiconductor power device is preferably metallized.
  • the high-frequency capacitor 1 is electrically connected to the first surface 201 of the multi-layer circuit board or the second surface 202 of the multi-layer circuit board or the lower surface of the insulating and thermally conductive plate. At least one electrode of the high-frequency capacitor 1 is connected to at least one through an inner electrical connection layer. At least one electrode of a semiconductor power device is electrically connected. It should be noted that the Bottom surface and Top surface of the semiconductor power device referred to in the present invention are only relative concepts, and do not specifically refer to a certain surface as the front or the back.
  • the second surface 201 of the multi-layer circuit board is used as a surface mount pad (SMD PAD), which is electrically interconnected to the customer's motherboard 8 to realize the customer's overall system.
  • SMD PAD surface mount pad
  • the module thickness L1 is thinner than a certain level, such as 5mm, and its thickness is thinner than the creepage distance required for safety insulation (usually greater than 6mm), the radiator 6 can only be in contact with the insulating heat sink DBC to ensure heat dissipation.
  • an electrical insulation sheet 9 may be provided between the upper surface of the plastic package 7 and the heat sink 6 to increase the insulation effect, as shown in FIG. 6 .
  • the high-frequency capacitor 1 is preferably integrated on the module, and the high-frequency capacitor 1 should be as close as possible to the semiconductor power devices Q1 and Q2.
  • high power often means high-voltage applications above 200V, such as 400V Vbus, which requires 630V ceramic capacitors. Capacitors for such high-voltage applications often require a higher height to achieve the required capacity, such as 1mm and above.
  • the thickness of the semiconductor power devices Q1 and Q2 must be as thin as possible, which causes the high-frequency capacitor 1 to be blocked by the DBC.
  • high-frequency capacitor 1 is used as an example. In fact, it is also applicable to other higher components.
  • the taller components are welded on the multi-layer circuit board 2.
  • the DBC is thickly covered on both sides. Copper, that is, the upper metal layer 4 and the lower metal layer 5 of the insulating and thermally conductive layer 3.
  • the lower metal layer 5 above the high-frequency capacitor 1 can be thinned or removed to make space so that the high-frequency capacitor 1 can be placed between the insulating and thermally conductive layer 3 and the multilayer circuit board 2 . That is, the high-frequency capacitor 1 is electrically connected to the first surface 201 of the multilayer circuit board, and the height Hc of the high-frequency capacitor 1 satisfies the following conditions: H1 ⁇ Hc ⁇ H2;
  • H1 is the distance from the first surface 201 of the multilayer circuit board to the Top surfaces of the semiconductor power devices Q1 and Q2, and H2 is the distance from the first surface 201 of the multilayer circuit board to the lower surface 302 of the insulating and thermally conductive layer; insulation and thermal conductivity
  • the plate extends above the high-frequency capacitor 1, and the lower metal layer 5 located between the high-frequency capacitor 1 and the insulating and thermally conductive plate is isolated from the high-frequency capacitor 1 by thinning or removing it.
  • the taller components are welded on the multilayer circuit board 2 , and when the height Hc of the high-frequency capacitor 1 is higher than the height between the lower surface 302 of the insulating and thermally conductive layer and the first surface 201 of the multilayer circuit board , then the entire insulating and heat-conducting plate can be retracted, so that there is only plastic packaging material between the top of the high-frequency capacitor 1 and the upper surface of the module.
  • the thickness of the plastic sealing material is preferably 0.4mm or more to ensure the electrical insulation strength. That is, the high-frequency capacitor 1 is electrically connected to the first surface 201 of the multilayer circuit board, and the height Hc of the high-frequency capacitor 1 satisfies the following conditions: H2 ⁇ Hc ⁇ H3;
  • H2 is the distance from the first surface 201 of the multilayer circuit board to the lower surface 302 of the insulating and thermally conductive layer 3
  • H3 is the distance from the first surface 201 of the multilayer circuit board to the upper surface 301 of the insulating and thermally conductive layer.
  • the insulating and heat-conducting plate 3 is located only above the semiconductor power devices Q1 and Q2.
  • the thickness of the insulating heat-conducting plate DBC is made as thin as possible. Therefore, even if the solution in Figure 7B is adopted, the thickness of the plastic sealing material on the high-frequency capacitor 1 may not meet the safety requirements, or may even be exposed. Therefore, the solution of FIG. 7C can be adopted, that is, the high-frequency capacitor 1 is placed on the second surface 202 of the multilayer circuit board. Not only can the circuit be similarly reduced, but the size of the module can also be reduced.
  • the high-frequency capacitor 1 is electrically connected to the second surface 202 of the multi-layer circuit board, and the two electrodes of the high-frequency capacitor 1 are electrically connected to the inner electrical connection layer and the first surface 201 of the multi-layer circuit board through the vertical electrical connection paths 130 respectively. connect.
  • these taller components are welded on the lower surface 302 of the insulating and thermally conductive layer, and the corresponding parts where there is insufficient space are thinned or removed in local areas of the multilayer circuit board 2 .
  • the lower metal layer 5 of the insulating and thermally conductive layer 3 can also be thinned. That is, the high-frequency capacitor 1 is electrically connected to the lower surface 302 of the insulating and thermally conductive layer, and at least one electrode of the high-frequency capacitor 1 is electrically connected to the inner electrical connection layer through an electrical connector (not shown in the figure), and the high-frequency capacitor 1
  • the height Hc satisfies the following conditions: H1 ⁇ Hc ⁇ H4;
  • H1 is the distance from the first surface 201 of the multilayer circuit board to the Top surface of the semiconductor power device
  • H4 is the distance from the second surface 202 of the multilayer circuit board to the lower surface 302 of the insulating and thermally conductive layer; located at the high-frequency capacitor 1
  • the lower multilayer circuit board 2 is isolated from the high-frequency capacitor 1 by thinning or removing it.
  • Step 1 Sa1 SMD the semiconductor power devices Q1, Q2 and other necessary components of multiple modules to the corresponding partitions of the PCB Panel; if necessary, the PCB can have double-sided SMD components, as shown in Figure 8A.
  • Second step Sa2 Optionally, the area between the pre-molded semiconductor power devices Q1 and Q2 and the first surface 201 of the multilayer circuit board is formed to form a thermal resistance electrical connection layer 12 to improve the strength and safety of the semiconductor power devices Q1 and Q2. Eliminate the bubbles at the bottom, as shown in Figure 8B.
  • the third step Sa3 Bond/solder the DBC of each module to the corresponding semiconductor power device Q1, Q2Top surface; if the scheme of Figure 8D, Figure 8E and Figure 29C is used, then the DBC is thermally connected to the semiconductor power device Q1, Q2 Before, weld the necessary components such as high-frequency capacitor 1 and common-mode suppression capacitor 24, as shown in Figure 8C.
  • the fourth step Sa4 Use the periphery of the PCB Panel as the plastic sealing area to prevent the plastic from overflowing, and effectively plastic seal the top of the PCB to form a plastic body 7, as shown in Figure 8D.
  • Step 5 Sa5 Optional, polish the upper metal layer 4 side of the DBC to remove overflow glue, improve the flatness of the insulating heat conductive plate DBC, reduce the thickness of the heat dissipation glue for subsequent installation, and improve the thickness consistency of each module to reduce the subsequent installation.
  • the thickness of heat dissipation glue for multi-module installation is shown in Figure 8E.
  • Step 6 Sa6 Cut and separate each module from the Panel, as shown in Figure 8F.
  • the module produced by this embodiment or in the module manufacturing process has a characteristic that the cutting and separation can make a circle around the side of the module and the side of the plastic package 7 flush with the side of the multilayer circuit board. Since a large Panel is cut into multiple modules, as long as the internal size of the large Panel meets the size of multiple module combinations, the same mold can be used, that is, one mold can produce multiple types of modules.
  • the semiconductor power device can be embedded in a multi-layer circuit board 2, and its electrodes 400 are led out through via holes and electroplating, and then electrically interconnected with the insulating heat-conducting plate and pins respectively. even. This eliminates the need for welding and wiring processes, resulting in higher reliability.
  • the top electrode of the semiconductor power device often needs to be connected to a certain appropriate potential, such as its source electrode or gate electrode. Since its Top surface is connected to the DBC, the Top surface electrode of the semiconductor power device needs to be electrically connected to the first surface 201 of the multilayer circuit board through the lower metal layer 5 and the conductive component 10, and then connected from the DBC to the multilayer circuit board 2.
  • this electrical connection is only for the semiconductor power device to obtain the necessary potential and does not require large current, so there is no need to lay thick copper on the DBC.
  • the power electrodes are placed on the upper and lower surfaces of the device, and the top surface electrodes are often electrostatic potential electrodes. Therefore, the drain electrode Drain needs to be electrically connected to the first surface 201 of the multilayer circuit board through the lower metal layer 5 and the conductive component 10, and the lower metal layer 5 is a thick copper layer.
  • the height of the conductive component 10 between the above-mentioned multi-layer circuit board 2 and the DBC and the height accuracy of the semiconductor power devices Q1 and Q2 are very demanding, which will result in high costs and complicated processes.
  • the present invention chooses to bury low thermal resistance and large heat capacity objects, such as thick copper, in the inner electrical connection layer of the circuit board directly below the TOP surfaces of the semiconductor power devices Q1 and Q2.
  • low thermal resistance and large heat capacity objects such as thick copper
  • the first surface 201, the second surface 202 of the multilayer circuit board 2 and the inner electrical connection layer are interconnected, and low thermal resistance interconnection is achieved. This not only achieves high-precision electrical interconnection on the surface, but also enables the semiconductor power devices Q1 and Q2 to obtain additional low thermal resistance and large heat capacity, which provides support for the module's transient high-power impact.
  • FIGS. 12A to 12D are shown.
  • the buffer external pin 14 (Pin).
  • Figure 12A shows the direct insertion soldering pin, which is soldered to the customer's motherboard 8 and is electrically connected by solder;
  • Figure 12B shows the direct insertion crimping pin, which presses the outer pin 14 into the through hole of the customer's motherboard 8 and relies on the Pin
  • the buffer elasticity forms a contact force for electrical connection;
  • Figure 12C shows the surface contact crimping pin, and the elastic Pin is crimped to the SMD Pad of the customer's motherboard 8;
  • Figure 12D shows the surface contact welding pin, and the elastic Pin is welded to SMD Pad for customer motherboard 8.
  • the thickness tolerance is buffered by the elasticity of the Pin or the difference in insertion depth, so that the thinnest thermal grease can be used to obtain the lowest thermal resistance and ensure maximum power.
  • the required electrodes are guided inside the multilayer circuit board 2 to the side edges of the multilayer circuit board, that is, the outer Pins of the multilayer circuit board that form the side of the module, and then implanted Enter buffered external pin 14.
  • Figure 13A shows the direct insertion soldering pin, which is welded to the customer's motherboard 8, and is electrically connected by solder;
  • Figure 13B shows the direct insertion crimping pin, which is pressed to the PCB through hole, and relies on the cushioning elasticity of the Pin to form a contact force to make the connection.
  • Figure 13C shows the surface contact crimping pin, and the elastic Pin is crimped to the SMD Pad of the customer's motherboard 8
  • Figure 13D shows the surface contact welding pin, and the elastic Pin is welded to the SMD Pad of the customer's motherboard 8.
  • the mounting holes 601 for fixing the module to the heat sink 6 may not be provided in the plastic package 7 .
  • the insulating fixing frame 15 can be added to the plastic body 7 .
  • the insulating fixing frame 15 is L-shaped in cross-section, and one side of the L-shaped frame is glued to the side of the plastic enclosure 7 for mechanical reinforcement and electrical insulation reinforcement.
  • a Z-shaped elastic insulating fixing frame 15 is used.
  • One end of the elastic insulating fixing frame 15 is a partial fixing frame 151 of insulating material, which is pressed against the outer edge of the module multi-layer circuit board 2;
  • the other end of the elastic insulating fixed frame 15 is a metal elastic piece 16 (ie, an elastic member), which is pressed on the radiator 6 through screws; the metal elastic piece 16 is compression-molded in part of the fixed frame 151 .
  • the pressure of the metal spring 16 is transmitted to the module through part of the fixed frame 151 to form an installation force.
  • the plastic part ensures the insulation requirements.
  • an L-shaped insulating fixed frame 15 is used.
  • the insulating fixed frame 15 has a certain elasticity to balance the thickness tolerance balance force.
  • One end of the insulating fixing frame 15 is pressed against the outer edge of the module circuit board, and screws lock the insulating fixing frame 15, the module, and the radiator 6 together to form a balanced pressure.
  • Figure 13E and Figure 13F also show the pin out method of the technical solution shown in Figure 7C, that is, making full use of the gap between the insulating fixing frame 15 and the second surface 202 of the multilayer circuit board, on the second surface of the multilayer circuit board.
  • SMD components are provided on the surface 202, such as Cbus, Driver and other necessary components. It not only makes full use of space, but also significantly reduces module size, reduces costs and improves yield.
  • the buffered external pins 14 of the solution shown in Figure 13E and Figure 13F are electrically connected to the external electrodes provided on the second surface 202 of the multilayer circuit board. It should be noted that the buffered external pins 14 can also be directly Electrically connected to the circuit structure inside the circuit board.
  • the module is implanted with buffer external pins 14. Regardless of the side or bottom, the simplest method is to reflow for soldering. However, since the plastic body 7 is hard-cured, all different materials need to be hard-connected together. The internal stress of the plastic package 7 caused by Reflow can easily destroy the structural stability and cause reliability problems. This embodiment proposes a technical solution of implanting pins before plastic sealing, which effectively solves this problem. The detailed technical solution is shown in Figures 14A to 14E.
  • Step 1 Sb1 PCB Panel reserves soldering space at the pin placement. As shown in Figure 14A.
  • Second step Sb2 Mechanically implant the Pin into the through hole 17 of the circuit board.
  • the top of the Pin should not exceed the first surface 201 of the multilayer circuit board. As shown in Figure 14B.
  • the third step Sb3 Before reflowing the SMD components on the multilayer circuit board 2, set enough solder paste on the top of the Pin. After such reflow, the solder not only reliably electrically connects the Pin to the PCB, but also fully fills the gap between the Pin and the multi-layer circuit board to prevent glue from overflowing during plastic sealing. As shown in Figure 14C.
  • the fourth step Sb4 Reflow SMD welding other components on the multi-layer circuit board 2. As shown in Figure 14D.
  • the fifth step Sb5 Plastic sealing and forming the plastic sealing body 7, as shown in Figure 14E, the subsequent process is similar to Figures 8A to 8F.
  • each buffered external pin 14 implanted can refer to the direct welding method shown in Figure 12A, the direct insertion crimping method shown in Figure 12B, the surface crimping method shown in Figure 12C, and the surface pressure welding method shown in Figure 12D.
  • the welding method makes a fixed electrical connection with the customer's motherboard 8. There is no need for the plastic body 7 to withstand high temperature reflow, making the module more reliable.
  • the Pin can be designed according to actual needs, thereby reducing the lateral diffusion resistance of the internal circuit of the multilayer circuit board 2 and greatly improving the utilization rate of the multilayer circuit board and the electrical performance of the module.
  • each Pin is unified to the required position to facilitate customer use.
  • the pin output flexibility of the internal circuit board of the module is taken into account to ensure the internal performance of the circuit board.
  • Figures 16A to 16F they are derivatives of the solutions in Figures 13F and 13F.
  • Cbus, driver or control IC and its peripheral circuits nearby. If they are placed on the same side of the multi-layer circuit board 2 as the semiconductor power devices Q1 and Q2, it will cause damage to the circuit board. The area increases, thereby increasing the module volume; second, it will cause the parasitic parameters in the high-frequency circuit to increase, affecting the high-frequency performance of the module; third, the IC and capacitor temperatures are high, affecting the performance and performance of other components in the module. reliability.
  • some components such as Cbus, driver IC or control IC and their peripheral circuits, are placed on the second surface 202 of the multi-layer circuit board, away from the heat source, thereby solving the above three problems and simplifying the customer's use of the module.
  • Convenience As shown in Figure 16A, packaged IC and other components are directly SMD to the second surface 202 of the multilayer circuit board; as shown in Figure 16C, semiconductor semiconductor power devices Q1 and Q2 are die bonded on the second surface 202 of the multilayer circuit board.
  • Figure 16D is an advancement of Figure 16C, that is, filling components (i.e. second surface protectors) are installed on both sides of the outer edges of the module PCB.
  • the filling components include a shell 19, a sealant 20 and a filler 21.
  • the shell 19 The sealant 20 is fixed and covered on the second surface 202 of the multilayer circuit board, and a filler 21 is filled between the housing 19 and the second surface 202 of the multilayer circuit board.
  • the components on the second surface 202 of the multilayer circuit board are within the range defined by the filling component, so the electronic components are protected by the filling body.
  • the filling body here can be silicone or plastic encapsulation material.
  • Figures 16E and 16F show two different implementations of Figure 16D.
  • Figure 16E is a schematic structural diagram of a silicone process flow for an independently formed plastic sealing module.
  • the so-called independently formed plastic module refers to a single module that is separated into boards after plastic packaging, and the second surface 202 of the multi-layer circuit board in the module has been installed with corresponding electronic components, such as resistors and capacitors driving IC pins, etc.
  • the independently formed package module set sealant 20 at the boundary of the range to be filled with silicone; install the shell 19, which is fixed to the module through the sealant 20; then fill in silicone, and place the relevant electronic components in the module shell
  • the inside of the body 19 is protected by silicone gel to form a silicone filling body 21 . Since it is an independently formed plastic module for installation, the filling component can be provided with screw holes to take into account the installation function of the module to the radiator 6 .
  • FIG 16F is a schematic structural diagram of a multi-module plastic-sealed Panel after plastic packaging is completed but has not yet been divided into panels.
  • the corresponding electronic components of each module such as resistors and capacitors driving IC pins, etc., have been installed on the second surface 202 of the multi-layer circuit board of the multi-module plastic panel.
  • the advantage of this is that it can greatly improve the efficiency of silicone filling.
  • the size of the filling component is smaller than that of the module, so it is difficult to independently undertake the fixed installation function of the finished module to the radiator 6 .
  • the solution in Figure 16F is suitable for the screw holes for fixing the module to the radiator 6 to be provided on the plastic body 7, that is, a screw hole is provided on both sides of the plastic body 7, which can be a full hole, or a half hole to save space. .
  • Figure 16B shows the pins coming out through the side of the multilayer circuit board.
  • the current is collected laterally through the multilayer circuit board 2, and the current loss is large.
  • FIG. 17A when welding pins on a flat surface, the welding strength is a big challenge, or copper pillars 602 are embedded in the plastic package 7 or the silicone filler, and then the surface of the plastic package 7 near the copper pillars 602 is electroplated to form a soldering pad. 603, it will only increase the cost and the process is relatively complicated.
  • Figures 17B and 17C use a large deep counterbore 611 plus a plurality of small vias 612. The large deep countersunk hole is formed by a silicone filler or a plastic encapsulation body that is concave toward the second surface of the circuit board.
  • the surface of the large deep countersunk hole and the adjacent The surface of the plastic package 7 or the silicone filler is electroplated to form a soldering pad.
  • Multiple small vias 612 are provided at the bottom of the large deep counterbore 611 and are electrically connected to the soldering pad and the circuit board to form a multiplexed soldering pad for power routing of large currents.
  • Pin 621 is used for welding. Due to the large number of small via holes 612 and short stroke, the resistance is small; the large deep countersunk hole 611 has a large surface area, a large diameter, high pin welding strength and low resistance.
  • FIG 17D it is a new pin design for the module. Because there are many signal pins 622 , in the previous embodiments, customers are often required to use through holes for the signal pins 622 . So if the spacing is large, it will occupy a large area, and if the spacing is small, it will be difficult to align during installation.
  • the signal pin 622 is designed as a pressure contact and is in contact with the flat pad on the surface of the customer's motherboard, while the power pin 621 still uses a through-hole design to ensure high current capability. In this way, very convenient installation can be achieved in a very small size.
  • Another feasible solution is to first package the semiconductor power devices Q1 and Q2, such as the embedded process or the fanout process.
  • the thick copper electrode formed through the package is used to raise the air gap using the thick copper on the surface of the package.
  • the thick copper is thicker than 30um is better.
  • the top surfaces of the semiconductor power devices Q1 and Q2 are directly covered with a large area of copper to form a copper-clad layer or a copper-clad layered electrode 632 formed through packaging to ensure that the thermal resistance of the top surfaces of the semiconductor power devices Q1 and Q2 is not significantly affected.
  • a preferred embodiment is to cascade a normally open third-generation semiconductor power device Normal On GaN/SiC and a low-voltage normally closed semiconductor power device Normal off SiMOS.
  • the normally open third-generation semiconductor power device Semiconductor power devices Q1 and Q2 are formed through stacked packaging with low-voltage normally closed semiconductor sub-power devices. That is, the drain Drain of the low-voltage normally closed semiconductor sub-power device is directly welded to the source of the high-voltage device and then packaged.
  • the top surface of the package transfers the heat generated by the high-voltage device to the top surface of the package through low thermal resistance, and leads out or internally interconnects each electrode and low-loop inductance. This can take into account the implementation of high power and high frequency on Normal On devices.
  • At least one semiconductor power device is a normally-on power device Normal On GaN/SiC.
  • the normally-on power device is provided with a low-voltage normally-off semiconductor power device Normal off SiMOS.
  • the normally-open power device is connected to the low-voltage Normally closed semiconductor power devices are cascaded, and low-voltage normally closed semiconductor power devices are arranged on the second surface 202 of the multilayer circuit board.
  • the position of the low-voltage normally closed semiconductor power device corresponds to the position of the normally open power device. That is, the low-voltage normally closed semiconductor power device and the normally open power device are respectively SMD on the second surface 202 and the first surface 201 of the module multi-layer circuit board, and are interconnected through the circuit board.
  • the low-voltage normally closed semiconductor power device is a Vertical MOS, it can be interconnected directly on the circuit board using Die Bond and Wirebond processes. If the low-voltage normally closed semiconductor power device is Lateral MOS, SMD can be performed directly on the circuit board to interconnect the low-voltage semiconductor power devices.
  • high-power converters often require a plurality of power conversion bridge arms, that is, a plurality of high-current, high-frequency voltage output pins, such as Pin A and Pin in Figure 20A B and Pin C.
  • Vbus+ and Vbus- can be designed into multiple pairs to facilitate customers to place corresponding capacitors on the motherboard to minimize the need for customer motherboards 8
  • the loop inductance between the capacitor and the high-frequency capacitor 1 inside the module can be designed into multiple pairs to facilitate customers to place corresponding capacitors on the motherboard to minimize the need for customer motherboards 8
  • the loop inductance between the capacitor and the high-frequency capacitor 1 inside the module can be designed into multiple pairs to facilitate customers to place corresponding capacitors on the motherboard to minimize the need for customer motherboards 8
  • the loop inductance between the capacitor and the high-frequency capacitor 1 inside the module can be designed into multiple pairs to facilitate customers to place corresponding capacitors on the motherboard to minimize the need for customer motherboards 8
  • the loop inductance between the capacitor and the high-frequency capacitor 1 inside the module can be designed into multiple
  • Vbus+ and Vbus- are placed as DC Pins on one side, and AC Pins A/B/C are placed on the other side, making it convenient for customers to set high-power Bulk capacitors, and AC magnetic or capacitive components.
  • the present invention can make the module size very small, in some high-voltage situations, the spacing between high-voltage power Pins (DC Pin, AC Pin) is tight, and there is no space to place signal Pins, such as drive signals, etc. Due to the use of the multi-layer circuit board 2 of the present invention, the pin positions can be flexibly set. Therefore, the embodiment of FIG. 20C is proposed, which can take into account the voltage resistance treatment between the module pins, and can also facilitate the layout when used by customers.
  • the power pins (DC terminal pins Vbus+ and Vbus- and AC terminal pins Pin A/B/C) are placed on the upper and lower sides respectively, and the signal pin 622 is placed in the middle of the two rows of power pins. .
  • the signal pins 622 will not occupy the spacing position of the power pins, so that the spacing can be reduced to make the module smaller, or the spacing can be enlarged to make the module suitable for higher operating voltage scenarios.
  • the circuit board resources of the customer's motherboard above and below the module can be used for DC power pins and AC power pins respectively, making the high current path unobstructed.
  • the signal pin 622 can be led out from the left or right side of the module, as shown in Figure 20D. The signal pin 622 and the power pin do not interfere with each other.
  • the minimum distance between the drive pin and the power pin needs to exceed 4mm to achieve a withstand voltage greater than 2KV. That is, the module integrates a driver IC that isolates the signal and driver output. Allows customers to achieve the function of isolating drive power semiconductors without the need for external isolation components. This is because traditional modules cannot achieve high power and isolation driving at the same time in such a small size scene, such as an area of 6cm ⁇ 4cm.
  • multiple drive pins pass through a pre-integrated power strip to reduce the floor space, and are compatible with customers drawing out the signal pins 622 through welding or connectors. This is because the driving pin current is small, but if each signal pin 622 is planted separately, a larger area is required for welding, resulting in a wider spacing between the driving signal pins.
  • the signal pin 622 can be led out from a flexible circuit board flat wire. Achieve smaller size and better anti-interference ability.
  • the plastic encapsulated body 7 can be ground into steps as shown in area 641 in Figure 21A, or a portion of the multilayer circuit board 2 and the plastic encapsulated body 7 can be ground away simultaneously in area 642 as shown in Figure 21B to form a step shape to increase the climb. electrical distance.
  • the creepage distance d between the module power pin 621 and the heat sink 6 is required to be as large as possible, often reaching 6mm or even 12mm. above. It is obviously uneconomical and impractical to rely solely on the thickness of the module.
  • the present invention can retract the power pins 621 and make full use of the surface distance of the circuit board 2 and even the surface distance of the electrically insulating pin bracket 643 to expand the creepage distance.
  • the air distance from the surface of the insulating material to the other surface must be a certain degree within the retracted space.
  • the d1 spacing should be more than 0.5mm so that customers can insert insulating sheets, or more than 1mm can be directly used. Air filling.
  • the outside of the electrically insulating pin bracket 643 is set in a step shape, and the air distance d2 between the top of the step and the circuit board and the air distance d1 between the bottom of the step and the customer's motherboard 8 are both set at more than 0.5mm to facilitate customer insertion. Insulation sheet; or both d1 and d2 are set above 1mm and can be filled directly with air. The number of steps can be adjusted and increased as needed.
  • the modules are placed in parallel and installed on the customer's motherboard 8 .
  • the module needs to be installed perpendicularly to the customer's motherboard 8. This facilitates the installation of the module and the radiator 6 separately to obtain the best heat dissipation performance. It’s just that the module output pin needs to be adjusted from perpendicular to the module heat dissipation surface to parallel.
  • the customer daughter board 22 can be provided with high-frequency decoupling capacitors 23, as well as system control components such as high-voltage isolation drivers or controllers.
  • One side of the customer daughter board 22 is connected to the high-frequency pins of the power magnetic components, that is, one or all of Pin A, Pin B, and Pin C.
  • the other side of the customer daughter board 22 is connected to the customer motherboard 8. And connect the Bulk capacitor through the motherboard. In this way, the respective paths are short to achieve connection without interference with each other, which can achieve higher efficiency and power density.
  • the maximum operating temperature of the capacitor and driver IC is often lower than the operating temperature of SiC/GaN.
  • the maximum operating temperature of SiC is 175°C
  • the maximum operating temperature of high-frequency capacitor 1 is only 125°C. Therefore, without special treatment, the performance and reliability of high-frequency capacitors will be affected due to excessive temperature.
  • thermally conductive electrical insulating material 644 can be added between these components and the customer's motherboard 8 to help these components reduce heat.
  • thermal resistance Rth_DietoPCB With the semiconductor power devices Q1 and Q2, then these thermal resistance relationships, plus the power consumption of Die Pdie and the thermal resistance Rth_DietoCase from Die to the outer surface of the DBC, that is, the module Case
  • the relationship must satisfy a certain relationship, so that the heat conducted by the semiconductor power devices Q1 and Q2 through the multilayer circuit board 2 and the temperature difference formed on the thermal resistance Rth_DietoPCB is close to or even greater than the maximum withstand temperature difference between Die and the multilayer circuit board. That is, when the semiconductor power devices Q1 and Q2 reach the maximum temperature TdieMAX, the temperature of the multilayer circuit board must be less than or equal to the maximum temperature resistance value TpcbMAX.
  • plastic sealing is performed twice.
  • the first step Sc1 As needed, weld the corresponding components on one or both sides of the multilayer circuit board 2, such as semiconductor power devices Q1, Q2, high-frequency capacitor 1, copper pillars connecting DBC/circuit board, etc., as shown in Figure 25A .
  • the second step Sc2 Plastic seal the first surface 201 of the circuit board 2 and one side of the semiconductor power devices Q1 and Q2 to form a plastic package 7. After plastic sealing, keep the top surfaces of the semiconductor power devices Q1 and Q2 exposed, and if necessary, the exposed semiconductor power Devices Q1 and Q2 remain solderable. For example, when plastic sealing, add a protective film to the exposed welding surface; or after plastic sealing, grind it down and plate it with metal. Since the molding cavity is smaller, the mold flow is easier to control on demand, as shown in Figure 25B.
  • the third step Sc3 Weld or bond the DBC so that there is good thermal conductivity between the DBC and the semiconductor power devices Q1 and Q2, and electrical conductivity when necessary, as shown in Figure 25C.
  • the fourth step Sc4 Based on the primary molding, the DBC and the primary molding body 7 are molded for a second time to form the molding body 70 . Similarly, decide whether to polish after the plastic sealing is completed as needed, as shown in Figure 25D.
  • the fifth step Sc5 divide the boards to form corresponding modules, as shown in Figure 25E.
  • the present invention since the present invention is suitable for high-frequency and high-voltage situations, it means that the problem of high-voltage and high-frequency jumps is prone to occur.
  • a plastic packaging structure is used to reduce the thickness of the insulating and thermally conductive layer 3, such as below 0.4mm, or even below 0.3mm, so that the parasitic capacitance between the upper metal layer 4 and the lower metal layer 5 on both sides of the insulating and thermally conductive layer 3 is very small. big.
  • the upper metal layer 4 is connected to the heat sink 6 and thus grounded. If the potential of the lower metal layer 5 jumps at high frequency and high voltage, the common mode current will be very large, resulting in an increase in electromagnetic interference in the system.
  • both ends of each power conversion bridge arm are DC voltages.
  • the potentials of Vbus+ and Vbus- are relatively calm and are not likely to cause large electromagnetic interference.
  • the midpoints of the power conversion bridge arms, such as points A, B, and C, are high-frequency and high-voltage jump potentials. Most of the electromagnetic interference in the system comes from this type of potential.
  • Figure 26B shows the conventional processing method, that is, the upper and lower power switches.
  • the heat dissipation surfaces of Q1 and Q2 are both drain electrodes.
  • they are Vbus+ and A potential respectively. Therefore, the Drain of Q2, that is, the A potential, will cause the pole Large electromagnetic interference.
  • this embodiment uses bridge arm switches with different heat dissipation surfaces. If it is a device such as SiC/MOS/IGBT with power current vertically penetrating the upper and lower surfaces of semiconductor power devices Q1 and Q2, the heat dissipation surface of the upper tube Q1 is the Drain electrode, and the heat dissipation surface of the lower tube Q2 is the Source electrode. That is, the potentials connected to DBC are electrostatic potentials, such as Vbus+ and Vbus-, which greatly reduces common-mode electromagnetic interference.
  • the heat dissipation surface of the upper tube Q1 is the Drain electrode
  • the heat dissipation surface of the lower tube Q2 is the Source or Gate electrode.
  • the potentials connected to DBC are electrostatic potentials, such as Vbus+ and Vbus- or Vbus+ and Vgs, which greatly reduces common-mode electromagnetic interference. Because the jump voltage and the electrostatic potential are relative, the electrostatic potential can be defined as less than one-tenth of the Vds voltage of the bridge arm power device, that is, the A voltage. For situations where the A voltage amplitude is generally greater than 400V, the driving voltage lower than 20V can be regarded as an electrostatic potential.
  • the common mode suppression capacitor 24 used to suppress common mode noise is integrated into the module nearby, so that the common mode noise, especially the high frequency common mode noise, is Suppressed inside the module.
  • the midpoint of the power conversion bridge arm is often the high-frequency and high-voltage jump VA.
  • At least one pole of the two interconnected electrodes of the semiconductor power device Q1 or Q2 involved is often the drain pole of Q2 in SiC applications.
  • This capacitance is short-circuited to the heat sink 6, thus Connect to ground GND. That is, the voltage source VA forms a large common mode current Icom through Cc and the impedance between the earth and the power ground GND_pw.
  • the heat sink 6 itself is a combination of multiple parasitic inductors and multiple pairs of ground parasitic capacitances. Even if the system adds Y capacitor Cy1 and common mode inductor Lcom between the ground and the power ground, the complexity of the parasitic circuit greatly reduces the suppression effect, or requires larger common mode inductors and capacitors to suppress.
  • the present invention proposes to integrate the Y capacitor Cy2 and the integrated damping Rin nearby inside the module, that is, to suppress the common mode energy inside the module before the complex parasitic circuit, so that the entire radiator 6 has almost no voltage drop.
  • Line_G here is the wiring ground connected to the earth, Ccer is the ceramic equivalent capacitance, Rth is the contact resistance between the outer copper and the radiator, Lth is the radiator distributed inductance, and Cth is the radiator distributed capacitance.
  • damping components such as resistors or high-impedance magnetic beads
  • Figure 27C shows the implementation plan of the specific structure, that is, a Y capacitor is set inside the module.
  • One electrode of the Y capacitor is electrically connected to the upper metal layer 4 through the cross-ceramic layer electrical connection component 25, and the other electrode of the Y capacitor passes through the lower metal layer 5.
  • the equivalent effect of Figure 29B can be achieved.
  • the cross-ceramic layer electrical connection component 25 interconnecting the Y capacitor to the upper metal layer 4 cannot extend beyond the upper metal layer 4 .
  • the cross-ceramic layer electrical connection component 25 is a side edge electrical interconnection component 26, which is arranged on the side edge of the insulating heat conductive plate. One end of the side edge electrical interconnection component 26 is electrically connected to the upper metal layer 4, and the side edge electrical interconnection component 26 is electrically connected to the upper metal layer 4.
  • the other end of the electrical interconnection member 26 is electrically connected to the Y capacitor through the lower metal layer 5; in Figure 27E, the cross-ceramic layer electrical connection component 25 is a through-type electrical interconnection member 27, and the through-type electrical interconnection member 27 penetrates the insulation and conducts heat.
  • the cross-ceramic layer electrical connection component 25 is a through-type electrical interconnection member 27, and the through-type electrical interconnection member 27 penetrates the insulation and conducts heat.
  • one end of the through-type electrical interconnection member 27 is electrically connected to the upper metal layer 4, and the other end of the through-type electrical interconnection member 27 is electrically connected to the common mode suppression capacitor 24 through the lower metal layer 5.
  • the solution shown in Figure 27F can use the conductive coating 28 to conduct the upper metal layer 4 and the lower metal layer 5 of the DBC.
  • Interconnects such as coating with silver paste.
  • the conductive coating 28 is further used to achieve the thinning effect. That is, the interconnection between the Y capacitor and the conductive coating 28 shown in Figure 27G can be directly achieved by using the viscosity of the conductive coating 28. It can also be bonded with conductive glue.
  • the first step Sd1 Place the semiconductor power devices Q1 and Q2 on the first surface 201 of the multi-layer circuit board. There is welding material between the front surfaces of the semiconductor power devices Q1 and Q2 and the multi-layer circuit board. After that, the semiconductor power devices Q1 and Q2 will be placed on the first surface 201 of the multi-layer circuit board.
  • the multilayer circuit board 2 of the devices Q1 and Q2 is placed on a support platform 29 .
  • the soldering material can be printed on the multi-layer circuit board 2 or pre-disposed on the front surfaces of the semiconductor power devices Q1 and Q2.
  • the support platform 29 under the multilayer circuit board 2 can also be a heating plate, as shown in Figure 28A.
  • the second step Sd2 Place the DBC on the top surfaces of the semiconductor power devices Q1 and Q2. There is welding material between the top surfaces of the semiconductor power devices Q1 and Q2 and the DCB. The welding material can be printed on the DBC or preset on the semiconductor.
  • the Top surfaces of power devices Q1 and Q2 are shown in Figure 28B and Figure 28C.
  • the third step Sd3 press a heating plate 30 on the DBC and then heat it. Since the DBC and the semiconductor power devices Q1 and Q2 are both good thermal conductors, the heat can be quickly transferred to each solder joint. In order to reduce energy consumption and heating speed, electric induction heating can be used to heat the copper layer of DBC, as shown in Figure 28D.
  • the vertical electrical connection paths 130 in the multilayer circuit board 2 are as close as possible to the edge of the module.
  • some applications that do not require safety insulation such as 48V low-voltage electrode drive or rectifier inverter applications, or converter applications where the radiator 6 is connected to the power ground instead of the earth, due to the relatively low withstand voltage requirements, no large voltage is required. safety distance requirements, so the thickness of the module can be further reduced.
  • the low-circuit pad 31 is disposed on the second surface 202 of the multi-layer circuit board.
  • the high-frequency capacitor 1 can be soldered to the second surface 202 of the circuit board 2 through the low-circuit pad 31.
  • the vertical electrical connection path 130 Set as close as possible to the low loop pad 31, the two electrodes of the high-frequency capacitor 1 form a low loop with the semiconductor power device via the vertical electrical connection path 130, the internal wiring layer of the multilayer circuit board, and the first surface 201 of the multilayer circuit board. loop.
  • the transmission path of the high-frequency signal is short and the area enveloped by the loop is small. Therefore, the parasitic inductance and other parasitic parameters in the loop are small, thereby reducing the peak voltage and loss.
  • the electrodes disposed on the back of the semiconductor power device are connected to the insulating and thermally conductive plate through the thermally conductive and electrically insulating material 644, and more than 80% of the total area of the back of the semiconductor power device is set to an electrostatic potential to reduce the common mode interference.
  • the module is disposed on one surface of the customer's motherboard 8 through surface mount welding, and the high-frequency capacitor 1 is disposed on the other surface of the customer's motherboard 8 corresponding to the module.
  • the high-frequency capacitor is placed adjacent to the low-loop pad 31 of the module, so that the wiring between the two poles of the high-frequency capacitor and the low-loop pad through the customer's motherboard is as short as possible, thereby forming a low loop.
  • Such a structure can achieve the same high-frequency effect, while reducing the number of internal components of the module, improving the yield of the module, reducing the height of the module, and saving costs.
  • a heat sink 6 is assembled on the upper surface of the module.
  • the heat generated by the semiconductor chip is directed to the heat dissipation device 6 through the insulating heat conduction plate, and the heat dissipation device 6 is connected to the heat dissipation device 6 through the fixing column 32.
  • Customer motherboard 8 connection assembly While increasing the heat dissipation capacity of the module, it also enhances the stability of the module.
  • the present invention strives to achieve both ultimate loop reduction and excellent thermal conductivity, thereby achieving the production of high-frequency and high-power packaged modules, and is electrically insulated from the heat dissipation surface and has good thermal conductivity effects. Therefore, the selection of insulating and thermal conductive materials for DBC in this case is particularly important. Materials with high thermal conductivity, such as aluminum oxide, aluminum nitride, and silicon nitride materials, are preferred; and the DBC in this case essentially refers to an electrically insulating good conductor substrate. , not limited to DBC ontology.
  • the circuit board in this case essentially refers to a multi-layer circuit wiring layer, which is not limited to an independent multi-layer circuit board.
  • the semiconductor power device in this case can also be a semiconductor wafer or a semiconductor chip, both of which are adapted to the technical solution disclosed in the present invention.
  • the present invention proposes a high-frequency and high-power module solution that can cope with future demand trends, and proposes various refined solutions to unleash the potential of the present invention. Some refined solutions are also applicable to other application scenarios and are not necessarily limited to those disclosed in the present invention.

Abstract

本发明公开了一种高频大功率封装模组、模组的制作方法及混合基板，包括至少一个功率变换桥臂、至少一个高频电容、电路层、绝缘导热板以及塑封体，半导体功率器件的正面与电路层的第一表面电连接，半导体功率器件的背面与绝缘导热板的下表面热连接或电热连接，高频电容与电路层的第一表面或电路层的第二表面或绝缘导热板的下表面电连接，高频电容的至少一个电极通过内层电连接层与至少一个半导体功率器件的至少一个电极电连接。本发明保障散热能力的同时，大幅减小了回路电感，使得大功率高频得以实现，充分发挥了第三代半导体的优势，并为其性能的更新换代提供了应用基础。

Description

一种高频大功率封装模组、模组的制作方法及混合基板 技术领域
本发明属于半导体封装技术领域，尤其涉及一种高频大功率封装模组、模组的制作方法及混合基板。
 背景技术
随着第三代半导体GaN/SiC的逐步成熟，其应用也越来越广泛。相对传统硅器件，其等效内阻大幅度下降，使得单一半导体功率器件的适用功率大幅度增加。同时，第三代半导体，也具备更优秀的开关特性，其开关损耗大为下降，更易工作在高频之下。但由于现有封装技术的不足，上述两个优势，较难同时得到。
如图1所示，由于其半导体功率器件Q1、Q2的面积小，热密度很高，需要厚铜陶瓷基板实现绝缘导热，而厚铜导致陶瓷基板的布线精度较差，不能实现小间距SMD作业。因此，通常是将半导体功率器件背面(即Top面)焊接到陶瓷板上进行散热，半导体功率器件正面通过wirebond打线，将半导体功率器件上的高精度电性排布引出。由于wirebond的存在，回路电感大幅度增加，限制了开关速度的提升，也就限制了频率的提升。
因此，如何在保障散热能力的同时，大幅减小回路电感，使得大功率高频得以实现，以充分发挥第三代半导体的优势是一个亟待解决的问题。
发明内容
有鉴于此，本发明的目的之一在于提供一种高频大功率封装模组，保障散热能力的同时，大幅减小了回路电感，使得大功率高频得以实现，充分发挥了第三代半导体的优势，并为其性能的更新换代提供了应用基础。
本发明的另一目的还在于提供一种能够实现上述高频大功率封装模组的制作方法。
本发明所述的高频大功率封装模组中的高频大功率是指：应用该模组的变换器的功率超过10KW，且工作频率高于100KHz；或应用该模组的变换器的工作频率高于300KHz，且功率超过1KW；其中，应用该模组的变换器以功率超过10KW，工作频率超过300KHz为佳。当然，这只是优选应用场景，并非本发明之限制。
为实现上述目的，本发明第一方面提供了一种高频大功率封装模组，包括：至少一个功率变换桥臂、至少一个高频电容、电路层、绝缘导热板和塑封体；
所述功率变换桥臂包括至少两个串联连接的半导体功率器件；
所述高频电容与功率变换桥臂并联，形成高频回路；
所述电路层包括第一表面、内层电连接层、第二表面及垂直电连接通路，所述内层电连接层通过至少一个垂直电连接通路与第一表面电连接；
所述绝缘导热板包括绝缘导热层，以及分别设置在绝缘导热层上下表面的上金属层和下金属层；
所述塑封体填充电路层的第二表面与绝缘导热板的上表面之间的间隙区域，所述电路层的第二表面或侧缘上设置有外部电极，所述外部电极与功率变换桥臂电连接；
所述半导体功率器件的正面与电路层的第一表面电连接，所述半导体功率器件的背面与绝缘导热板的下表面热连接或电热连接；
所述高频电容与电路层的第一表面或电路层的第二表面或绝缘导热板的下表面电连接，所述高频电容的至少一个电极通过内层电连接层与至少一个半导体功率器件的至少一个电极电连接。
优选的，所述半导体功率器件通过一热阻电连接层与电路层的第一表面电连接。
优选的，所述热阻电连接层的热阻值Rth_DietoPCB满足以下公式：(Tcase+(TdieMAX-Tcase)×Rth_PCBtoCase/(Rth_PCBtoCase+Rth_DietoPCB))≤TpcbMax；
其中，Tcase为高频大功率封装模组工作时的周围环境温度，TdieMAX为半导体功率器件的最高工作温度，Rth_PCBtoCase为电路层到绝缘导热板上表面的总等效热阻值，TpcbMax为电路层的最高工作温度。
优选的，所述热阻电连接层的热阻值至少为3K/W。
优选的，所述绝缘导热板的上表面与一散热器热连接，所述塑封体的上表面与散热器之间具有气隙。
优选的，所述高频电容与电路层的第一表面电连接时，所述高频电容与电路层的第一表面电连接时，所述高频电容的高度Hc满足以下条件：H1≤Hc＜H2；
其中，H1为电路层的第一表面至半导体功率器件的背面的距离，H2为电路层的第一表面至绝缘导热层的下表面的距离；
所述绝缘导热板延伸至高频电容的上方；位于所述高频电容与绝缘导热层之间的下金属层通过减薄或去除的方式与高频电容隔离。
优选的，所述高频电容与电路层的第一表面电连接时，所述高频电容的高度Hc满足以下条件：H2≤Hc＜H3；
其中，H2为电路层的第一表面至绝缘导热层的下表面的距离，H3为电路层的第一表面至绝缘导热层的上表面的距离；
所述绝缘导热板位于电路层的第二表面上除高频电容以外的器件的上方。
优选的，所述高频电容与电路层的第二表面电连接时，所述高频电容的两个电极分别通过垂直电连接通路与内层电连接层及电路层的第一表面电连接。
优选地，所述高频电容与绝缘导热板的下表面电连接时，所述高频电容的至少一个电极通过一电连接件与内层电连接层电连接，且高频电容的高度Hc满足以下条件：H1≤Hc＜H4；
其中，H1为电路层的第一表面至半导体功率器件的背面的距离，H4为电路层的第二表面至绝缘导热层的下表面的距离；
位于所述高频电容下方的电路层通过减薄或去除的方式与高频电容隔离。
优选地，所述半导体功率器件的功率电极均位于其正面。
优选地，还包括至少一个电连接孔，所述电连接孔用于实现半导体功率器件的正面电极与线路板之间的电连接。
优选地，所述半导体功率器件的背面电极依次通过绝缘导热板的下金属层及导电组件电连接至电路层的第一表面。
优选地，所述半导体功率器件的背面电极通过设置在其内部的导电通孔电连接至其正面。
优选地，所述半导体功率器件的至少一个功率电极为背面功率电极，所述背面功率电极通过绝缘导热板的下金属层及导电组件电连接至电路层的第一表面，所述下金属层为厚铜层。
优选地，所述电路层的内部设置有高热容元件，所述高热容元件与内层电连接层热连接或电热连接。
优选地，所述电路层中和所述高频电容两端相连的布线在水平方向的投影与半导体功率器件在水平方向的投影部分重合。
优选地，多个所述半导体功率器件并联电连接，所述高频大功率封装模组还包括分布式的垂直连接件，每一所述半导体功率器件与对应的垂直连接件邻近设置。
优选地，所述分布式的垂直连接件包括第一垂直连接件和第二垂直连接件，所述第一垂直连接件的直径大于所述第二垂直连接件的直径，所述第一垂直连接件邻近所述高频大功率封装模组的侧面设置。
优选地，还包括缓冲外引脚，所述缓冲外引脚用于将高频大功率封装模组与客户主板电连接。
优选地，所述缓冲外引脚设置在电路层的第二表面上。
优选地，所述缓冲外引脚设置在电路层的侧缘。
优选地，所述缓冲外引脚的内侧焊接在电路层的侧缘，所述缓冲外引脚的外侧设置有绝缘加固框架。
优选地，还包括弹性绝缘固定框架，所述弹性绝缘固定框架用于使高频大功率封装模组与设置在绝缘导热板上表面的散热器紧贴。
优选地，所述弹性绝缘固定框架包括弹性件及绝缘加固框架，所述弹性件的一端与散热器连接，所述弹性件的另一端插接在绝缘加固框架中，所述绝缘加固框架通过边缘限位结构对高频大功率封装模组进行限位。
优选地，所述弹性绝缘固定框架包括具有弹性材质的绝缘加固框架，所述绝缘加固框架通过边缘限位结构对高频大功率封装模组进行限位，所述绝缘加固框架通过贯穿式固定组件分别与客户主板、散热器连接。
优选地，所述电路层的第二表面与客户主板之间形成有安装区域，所述安装区域设置有至少一个电路元件。
优选地，所述缓冲外引脚通过重布线结构引出。
优选地，还包括第二表面保护件，所述第二表面保护件包括壳体、密封胶以及填充体，所述壳体通过密封胶固定并覆盖在电路层的第二表面上，所述壳体与电路层的第二表面之间填充有填充体，所述填充体可以为硅胶或者塑封料；
所述壳体上设置有供缓冲外引脚伸出的外引脚通孔。
优选地，所述壳体的一端与设置在绝缘导热板上表面的散热器固定连接。
优选地，所述高频大功率封装模组在水平方向上具有未被第二表面保护件覆盖的延伸区域，所述延伸区域上设置有供固定用的固定孔。
优选地，所述缓冲外引脚通过重布线结构引出。
优选地，还包括至少一个铜柱和至少一个焊盘，所述铜柱内埋于所述第二表面保护件内，所述焊盘设置于所述第二表面保护件表面，且与所述铜柱电连接。
优选地，所述第二表面保护件包括至少一个复用焊盘，所述复用焊盘包括至少一个大深沉孔、至少一个小过孔和至少一个焊盘，所述大深沉孔由所述第二表面保护件的外表面向所述线路板的第二表面内凹形成，所述焊盘覆盖大深沉孔表面并且延伸至大深沉孔以外和，所述小过孔设置于大深沉孔底部且电连接至少一个焊盘和线路板，所述复用焊盘用于焊接功率引脚。
优选地，所述缓冲外引脚为直插焊接引脚、直插压接引脚、表面触点压接引脚、表面触点焊接引脚中的一种。
优选地，所述半导体功率器件的正面电极下方设置有铜柱，所述铜柱的高度至少为30μm。
优选地，所述半导体功率器件具有至少两种不同的厚度，所述半导体功率器件的正面电极下方设置有对应的不同高度的铜柱或金属球。
优选地，所述半导体功率器件具有至少两种不同的厚度，至少一个较厚的所述半导体功率器件的正面电极下方设置有铜柱，至少一个较薄的所述半导体功率器件的正面电极下方设置有金属球。
优选地，所述半导体功率器件的正面电极为通过封装形成的厚铜电极，所述厚铜电极的高度至少为30μm。
优选地，所述半导体功率器件的背面电极上方设置有覆铜层。
优选地，所述半导体功率器件具有至少两种不同的厚度，所述半导体功率器件的背面电极上方的覆铜层具有对应的不同厚度。
优选地，所述半导体功率器件的背面电极为通过封装形成的覆铜层状电极。
优选地，至少一个所述半导体芯片的背面设置一个功率电极和一个门极电极，所述功率电极连接至电路的静电位。
优选地，所述半导体功率器件的门极电极通过电连接线键合至所述电路层，所述门极电极的焊点通过点胶处理保护。
优选地，所述半导体功率器件为衬底电位可设置的LDMOS器件，所述衬底电位设置为所述高频大功率封装模组的静电位。
优选地，所述LDMOS器件的衬底材质为蓝宝石。
优选地，至少一个所述半导体功率器件包括一常开式第三代半导体子功率器件及一低压常闭式半导体子功率器件，所述常开式第三代半导体子功率器件与低压常闭式半导体子功率器件级联，所述常开式第三代半导体子功率器件与低压常闭式半导体子功率器件通过叠层封装的形式形成半导体功率器件。
优选地，至少一个所述半导体功率器件为一常开式功率器件，所述常开式功率器件配合设置有一低压常闭式半导体功率器件，所述常开式功率器件与低压常闭式半导体功率器件级联，所述低压常闭式半导体功率器件设置在电路层的第二表面上，所述低压常闭式半导体功率器件的设置位置与常开式功率器件的位置垂直对应。
优选地，所述功率变换桥臂并联设置有多个，所述功率变换桥臂的直流端外部电极与交流端外部电极分别设置在高频大功率封装模组的两侧。
优选地，所述塑封体的侧缘为台阶形。
优选地，还包括一客户子板，所述客户子板用于将外部电极与客户主板电连接，所述客户子板与电路层平行设置，所述客户子板和电路层分别与客户主板垂直设置。
优选地，所述功率变换桥臂的直流端外部电极设置在靠近客户主板的一侧，所述功率变换桥臂的交流端外部电极设置在远离客户主板的一侧，所述功率变换桥臂的交流端外部电极通过客户子板与设置在客户主板上的外部交流器件电连接。
优选地，每个所述功率变换桥臂中的两个半导体功率器件的背面电极分别为与功率变换桥臂的两个直流端等电位的电极。
优选地，还包括导热柱，所述导热柱设置于绝缘导热板的上表面，所述导热柱用于液冷散热。
优选地，所述绝缘导热板的上表面的与半导体功率器件垂直对应的区域为第一散热区域，所述导热柱在第一散热区域内的设置数量密度，大于其在第一散热区域外的设置数量密度。
优选地，所述导热柱包括金属壳体和超高导热填充料，其中所述超高导热填充料设置于金属壳体内部，所述超高导热填充料为碳纤维管、石墨烯片或者相变液体。
本发明另一方面公开了一种高频大功率封装模组，包括：至少一个功率变换桥臂、至少一个高频电容、绝缘导热板、电连接装置、塑封体、跨陶瓷层电连接组件和共模抑制电容；
所述功率变换桥臂包括至少两个串联连接的半导体功率器件；
所述高频电容与功率变换桥臂并联；
所述绝缘导热板包括绝缘导热层，以及分别设置在绝缘导热层上下表面的上金属层和下金属层；
所述半导体功率器件的正面的至少一个电极通过所述电连接装置引出至高频大功率封装模组外部，并与高频电容的至少一个电极电连接；
所述塑封体填充半导体功率器件的正面与绝缘导热板的上表面之间的间隙区域；
所述共模抑制电容的一个电极通过跨陶瓷层电连接组件与上金属层电连接，所述共模抑制电容的另一个电极与功率变换桥臂的一个直流端电连接；
所述半导体功率器件的背面与绝缘导热板的下表面热连接或电热连接。
优选地，还包括一散热器；
所述高频大功率封装模组安装在散热器上，所述绝缘导热板的上表面与散热器热连接，所述散热器的电位为大地；
所述共模抑制电容用于抑制由于桥臂交流电压跳变而产生的流经散热器至大地的电流。
优选地，所述共模抑制电容设置在所述间隙区域内，至少一个所述半导体功率器件为第一功率器件，所述第一功率器件的背面电极与功率变换桥臂的一个直流端等电位，所述共模抑制电容的一个电极通过跨陶瓷层电连接组件与上金属层电连接，所述共模抑制电容的另一个电极通过下金属层与第一功率器件的背面电极电连接。
优选地，所述跨陶瓷层电连接组件包括一侧缘电互连件，所述侧缘电互连件设置在绝缘导热板的侧缘，所述侧缘电互连件的一端与上金属层电连接，所述侧缘电互连件的另一端通过下金属层与共模抑制电容电连接。
优选地，所述跨陶瓷层电连接组件包括一贯穿式电互连件，所述贯穿式电互连件贯穿绝缘导热层，所述贯穿式电互连件的一端与上金属层电连接，所述贯穿式电互连件的另一端通过下金属层与共模抑制电容电连接。
优选地，所述跨陶瓷层电连接组件包括一导电涂层，所述导电涂层设置在绝缘导热层侧缘及其上下表面的临近区域，所述导电涂层的一端与上金属层电连接，所述导电涂层的另一端与共模抑制电容电连接。
优选地，所述电连接装置为电路层，所述电路层包括第一表面、内层电连接层、第二表面及垂直电连接通路，所述内层电连接层通过至少一个垂直电连接通路与第一表面电连接；
所述塑封体填充电路层的第二表面与绝缘导热板的上表面之间的间隙区域，所述电路层的第二表面或侧缘上设置有外部电极，所述外部电极与功率变换桥臂电连接；
所述半导体功率器件的正面与电路层的第一表面电连接，所述半导体功率器件的背面与绝缘导热板的下表面热连接或电热连接；
所述高频电容与电路层的第一表面或电路层的第二表面或绝缘导热板的下表面电连接，所述高频电容的至少一个电极通过内层电连接层与至少一个半导体功率器件的至少一个电极电连接。
本发明另一方面公开了一种高频大功率封装模组，包括：至少一个功率变换桥臂、至少一个高频电容、绝缘导热板、电连接装置、塑封体和外部电极；
所述功率变换桥臂包括至少两个串联连接的半导体功率器件；
所述高频电容与功率变换桥臂并联；
所述绝缘导热板包括绝缘导热层，以及分别设置在绝缘导热层上下表面的上金属层和下金属层；
所述半导体功率器件的正面的至少一个电极通过所述电连接装置引出至高频大功率封装模组外部，并与高频电容的至少一个电极电连接；
所述塑封体填充半导体功率器件的正面与绝缘导热板的上表面之间的间隙区域；
所述外部电极包括至少一对直流端外部电极、至少一对交流端外部电极及至少一对信号端外部电极；
所述半导体功率器件的背面与绝缘导热板的下表面热连接或电热连接；
所述功率变换桥臂并联设置有多个，所述功率变换桥臂的直流端外部电极与交流端外部电极分别设置在高频大功率封装模组的两侧；
所述信号端外部电极设置在所述直流端外部电极与交流端外部电极之间。
优选地，所述信号端外部电极与直流端外部电极之间的最小间距大于4mm，所述信号端外部电极与交流端外部电极之间的最小间距大于4mm。
优选地，所述信号端外部电极为预制成型的多引脚排插。
优选地，所述多引脚排插为柔性PCB扁平线。
优选地，所述电连接装置为电路层，所述电路层包括第一表面、内层电连接层、第二表面及垂直电连接通路，所述内层电连接层通过至少一个垂直电连接通路与第一表面电连接；
所述塑封体填充电路层的第二表面与绝缘导热板的上表面之间的间隙区域，所述电路层的第二表面或侧缘上设置有外部电极，所述外部电极与功率变换桥臂电连接；
所述半导体功率器件的正面与电路层的第一表面电连接，所述半导体功率器件的背面与绝缘导热板的下表面热连接或电热连接；
所述高频电容与电路层的第一表面或电路层的第二表面或绝缘导热板的下表面电连接，所述高频电容的至少一个电极通过内层电连接层与至少一个半导体功率器件的至少一个电极电连接。
本发明另一方面公开了一种制作上述高频大功率封装模组的制作方法，包括：
提供一所述电路层及所述绝缘导热板；
将所述高频电容设置在电路层或绝缘导热板上；
在所述电路层上焊接所述半导体功率器件；
在所述半导体功率器件的上方设置所述绝缘导热板；
塑封所述间隙区域，形成所述塑封体，所述绝缘导热板的上表面外露。
本发明另一方面公开了一种制作上述高频大功率封装模组的制作方法，包括：
提供一所述电路层及所述绝缘导热板；
将所述高频电容设置在电路层或绝缘导热板上；
在所述电路层上焊接所述半导体功率器件；
预塑封所述半导体功率器件与电路层的第一表面之间的区域，形成所述热阻电连接层；
在所述半导体功率器件的上方设置所述绝缘导热板；
塑封所述间隙区域，形成所述塑封体，所述绝缘导热板的上表面外露。
本发明另一方面公开了一种制作上述高频大功率封装模组的制作方法，包括：
提供一所述电路层及所述绝缘导热板；
将所述高频电容设置在电路层上；
在所述电路层上焊接所述半导体功率器件；
塑封所述电路层和半导体功率器件，形成第一塑封体，所述半导体功率器件的上表面外露；
在所述半导体功率器件的上表面设置所述绝缘导热板；
塑封所述绝缘导热板，形成第二塑封体，所述绝缘导热板的上表面外露。
本发明另一方面公开了一种制作上述高频大功率封装模组的制作方法，包括：
提供一所述绝缘导热板及预设有线路板通孔的所述电路层；
将与所述缓冲外引脚固定电性设置在所述线路板通孔内，使外部电极分别与电路层的第一表面和/或内层电连接层和/或第二表面电连接，且使所述缓冲外引脚向电路层的第二表面外延伸；
将所述高频电容设置在电路层或绝缘导热板上；
在所述电路层上焊接所述半导体功率器件；
在所述半导体功率器件的上方设置所述绝缘导热板；
塑封所述间隙区域，形成所述塑封体，所述绝缘导热板的上表面外露。
本发明另一方面公开了一种制作上述高频大功率封装模组的制作方法，包括：
提供一所述电路层及所述绝缘导热板；
提供一支撑平台；
在所述电路层的第一表面上设置焊料和所述半导体功率器件；
将所述电路层的第二表面放置于支撑平台上；
在所述半导体功率器件的上方设置焊料和所述绝缘导热板；
将一加热平板放置于所述绝缘导热板的上表面进行加热完成焊接。
本发明另一方面公开了一种高频大功率封装模组，包括至少三个半导体功率器件、一个驱动器；
所述半导体功率器件设置于同一平面上；
所述驱动器为每个所述半导体功率器件提供驱动信号，且在所述平面的投影与每个所述半导体功率器件在所述平面上的投影都部分重合。
优选地，还包括一个电路层，所述电路层包括相对的第一表面和第二表面；所述半导体功率器件设置于第一表面，所述驱动器设置于第二表面。
优选地，每个所述半导体功率器件到所述驱动器的对应的驱动信号端的走线距离相同。
优选地，还包括至少一个高频电容、一个绝缘导热板和塑封体；
所述绝缘导热板包括绝缘导热层，以及分别设置在绝缘导热层上下表面的上金属层和下金属层；
所述塑封体填充电路层的第二表面与绝缘导热板的上表面之间的间隙区域，所述电路层的第二表面或侧缘上设置有外部电极，所述外部电极与功率变换桥臂电连接；
所述半导体功率器件的正面与电路层的第一表面电连接，所述半导体功率器件的背面与绝缘导热板的下表面热连接或电热连接；
所述高频电容与功率变换桥臂并联，形成高频回路，所述高频电容与电路层的第一表面或电路层的第二表面或绝缘导热板的下表面电连接，所述高频电容的至少一个电极通过内层电连接层与至少一个半导体功率器件的至少一个电极电连接；
每个所述半导体功率器件到所述驱动器的对应的驱动信号端的走线距离相同。
本发明另一方面公开了一种混合基板，包括包括高导热区域和低导热区域；所述混合基板具有相对的上表面和下表面；
所述高导热区域和低导热区域沿水平方向排布；
所述高导热区域用于设置发热半导体器件，所述发热半导体器件具体设置于所述下表面；
所述高导热区域的导热系数大于低导热区域的导热系数；
所述混合基板的上表面用于装配散热装置。
优选地，所述高导热区域的导热系数大于低导热区域的导热系数的两倍。
优选地，所述高导热区域为高导热颗粒阵列，或者，所述高导热区域为高导热颗粒阵列和低导热材料的混合物。
优选地，还包括分别设置在上表面和下表面的上金属层和下金属层，所述高导热区域和所述低导热区域的材质均为绝缘材质。
本发明另一方面公开了一种高频大功率封装模组，包括如上述的混合基板、至少一个功率变换桥臂、至少一个高频电容、电路层和塑封体；
所述功率变换桥臂包括至少两个串联连接的半导体功率器件；
所述高频电容与功率变换桥臂并联，形成高频回路；
所述电路层包括第一表面、内层电连接层、第二表面及垂直电连接通路，所述内层电连接层通过至少一个垂直电连接通路与第一表面电连接；
所述塑封体填充电路层的第二表面与混合基板的上表面之间的间隙区域，所述电路层的第二表面或侧缘上设置有外部电极，所述外部电极与功率变换桥臂电连接；
所述半导体功率器件的正面与电路层的第一表面电连接，所述半导体功率器件的背面与所述高导热区域对应的下金属层热连接或电热连接；
所述高频电容与电路层的第一表面或电路层的第二表面或混合基板的下表面电连接，所述高频电容的至少一个电极通过内层电连接层与至少一个半导体功率器件的至少一个电极电连接。
本发明另一方面公开了一种高频大功率封装模组，包括如上述的混合基板、至少一个功率变换桥臂和导热柱；
所述至少一个功率变换桥臂包括至少两个串联连接的半导体功率器件，且所述半导体功率器件设置于所述高导热区域对应的下金属层；
所述导热柱设置于所述混合基板的上金属层；
至少一部分所述导热柱设置于高导热区域对应的上金属层。
优选地，至少另一部分所述导热柱设置于低导热区域对应的上金属层，所述导热柱在高导热区域内的设置数量密度，大于其在低导热区域内的设置数量密度。
优选地，还包括至少一个高频电容、电路层和塑封体；
所述高频电容与功率变换桥臂并联，形成高频回路；
所述电路层包括第一表面、内层电连接层、第二表面及垂直电连接通路，所述内层电连接层通过至少一个垂直电连接通路与第一表面电连接；
所述塑封体填充电路层的第二表面与混合基板的上表面之间的间隙区域，所述电路层的第二表面或侧缘上设置有外部电极，所述外部电极与功率变换桥臂电连接；
所述半导体功率器件的正面与电路层的第一表面电连接，所述半导体功率器件的背面与混合基板的下表面热连接或电热连接；
所述高频电容与电路层的第一表面或电路层的第二表面或混合基板的下表面电连接，所述高频电容的至少一个电极通过内层电连接层与至少一个半导体功率器件的至少一个电极电连接。
本发明另一方面公开了一种高频大功率封装模组，至少一个功率变换桥臂、多层线路板、绝缘导热板和塑封体；
所述功率变换桥臂包括至少两个串联连接的半导体功率器件；
所述多层线路板包括相对的第一表面和第二表面、内层电连接层、至少两个低回路焊盘及垂直电连接通路，所述内层电连接层通过至少一个垂直电连接通路与第一表面电连接；
所述绝缘导热板包括绝缘导热层以及相对的上表面和下表面；
所述塑封体填充多层线路板的第二表面与绝缘导热板的上表面之间的间隙区域，所述多层线路板的第二表面或侧缘上设置有外部电极，所述外部电极与功率变换桥臂电连接；
所述半导体功率器件的正面与多层线路板的第一表面电连接，所述半导体功率器件的背面与绝缘导热板的下表面热连接或电热连接；
所述多层线路板，将所述功率变换桥臂的两个直流电极，通过第一表面及内层电连接层，耦合到对应的两个低回路焊盘，所述低回路焊盘用于电性连接一高频电容形成低回路。
优选地，所述至少两个低回路焊盘设置于多层线路板的第二表面，所述第二表面还设置有功率引脚和信号引脚。
优选地，所述线路板的第二表面电性连接一个客户主板的一个表面，所述客户主板的另一个表面设置一个高频电容，所述高频电容通过客户主板与所述低回路焊盘电性连接。
优选地，所述绝缘导热板的上表面与一个散热装置热连接，所述散热装置通过至少一固定柱与客户主板装配。
优选地，所述半导体功率器件的背面的至少80％面积的电位为所述高频大功率封装模组的静电位。
本发明第一方面中所公开的一种高频大功率封装模组，保障散热能力的同时，大幅减小了回路电感，使得大功率高频得以实现，充分发挥了第三代半导体的优势，并为其性能的更新换代提供了应用基础。
 附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为现有技术中的第三代半导体封装结构的示意图；
图2A至图2I为本发明实施例所公开的高频大功率封装模组的结构示意图；
图3A至图3C为本发明另一实施例所公开的高频大功率封装模组的结构示意图；
图4A至图4C为本发明另一实施例所公开的高频大功率封装模组的结构示意图；
图4D至图4E为本发明另一实施例所公开的高频大功率封装模组的结构示意图；
图5A为本发明实施例所公开的高频大功率封装模组的结构示意图；
图5B为本发明实施例所公开的高频大功率封装模组的等效电路图；
图5C至图5E为不同厚度半导体功率器件的封装模组的结构示意图；
图5F为本发明实施例所公开的高频大功率封装模组的等效电路图；
图5G至图5J为带导热柱的高频大功率封装模组的结构示意图；
图5K为带驱动器的高频大功率封装模组的结构示意图；
图5L为本发明另一实施例所公开的高频大功率封装模组的结构示意图；
图6为本发明实施例所公开的高频大功率封装模组的另一结构示意图；
图7A至图7E为本发明实施例所公开的高频大功率封装模组的高频电容、多层线路板、功率变换桥臂与绝缘导热板在不同高度下的结构示意图；
图8A至图8F为本发明实施例所公开的高频大功率封装模组的制作方法的流程示意图；
图9为本发明另一实施例所公开的高频大功率封装模组的结构示意图；
图10为本发明实施例所公开的高频大功率封装模组的半导体功率器件的电极设置方式的结构示意图；
图11为本发明实施例所公开的高频大功率封装模组设置有高热容元件的结构示意图；
图12A至图12D为本发明实施例所公开的高频大功率封装模组的缓冲外引脚设置在多层线路板的第二表面时的结构示意图；
图13A至图13D为本发明实施例所公开的高频大功率封装模组的缓冲外引脚设置在多层线路板的侧缘时的结构示意图；
图13E至图13F为本发明实施例所公开的高频大功率封装模组的缓冲外引脚的其他设置方式的结构示意图；
图14A至图14E为本发明实施例所公开的高频大功率封装模组的缓冲外引脚的制作方法的流程示意图；
图15A至图15D为本发明实施例所公开的高频大功率封装模组的缓冲外引脚通过重布线结构引出的结构示意图；
图16A为本发明实施例所公开的高频大功率封装模组用封装好元器件直接SMD到多层线路板第二表面的结构示意图；
图16B为本发明实施例所公开的高频大功率封装模组的多层线路板第二表面放置好元件并互联后，再进行整面塑封的结构示意图；
图16C为本发明实施例所公开的高频大功率封装模组的多层线路板第二表面放置好元件并互联后再用COB工艺加以固定和保护的结构示意图；
图16D至图16F为本发明实施例所公开的高频大功率封装模组设置有第二表面保护件时的结构示意图；
图17A至图17E为本发明实施例所公开的高频大功率封装模组的采用双面塑封的结构示意图；
图18为本发明实施例所公开的高频大功率封装模组的半导体功率器件的电极设置方式的结构示意图；
图19A为本发明实施例所公开的高频大功率封装模组的半导体功率器件包括一常开式第三代半导体子功率器件及一低压常闭式半导体子功率器件时的等效电路图；
[根据细则26改正 27.03.2023]
图19B至图19D为本发明实施例所公开的高频大功率封装模组的半导体功率器件包括一常开式第三代半导体子功率器件及一低压常闭式半导体子功率器件时的结构示意图；
图20A为本发明实施例所公开的高频大功率封装模组设置有多个功率变换桥臂时的等效电路图；
图20B至图20D为本发明实施例所公开的高频大功率封装模组设置有多个功率变换桥臂时的出PIN面的结构示意图；
图21A至图21B为本发明实施例所公开的高频大功率封装模组的塑封体的侧缘为台阶状的结构示意图；
图22A至图22B为本发明实施例所公开的高频大功率封装模组的电绝缘引脚支架的结构示意图；
图23为本发明实施例所公开的高频大功率封装模组的垂直于客户主板安装时的结构示意图；
图24A至图24D为本发明实施例所公开的高频大功率封装模组的散热情况的示意图；
图25A至图25E为本发明实施例所公开的高频大功率封装模组的二次封装过程的流程示意图；
图26A至图26C为本发明实施例所公开的高频大功率封装模组的防止电磁干扰的示意图；
图27A至图27C为本发明实施例所公开的高频大功率封装模组抑制共模噪音的示意图；
图27D至图27G为本发明实施例所公开的高频大功率封装模组的共模抑制电容的设置方式的结构示意图；
图28A至图28D为本发明实施例所公开的高频大功率封装模组的另一种制作方法的流程示意图。
图29A至图29C为本发明另一种实施例所公开的高频大功率封装模组的结构示意图；
其中：
1高频电容；2多层线路板；3绝缘导热层；3a混合基板；4上金属层；5下金属层；6散热器；7/70塑封体；8客户主板；9电绝缘片；10导电组件；11外部电极；12热阻电连接层；13高热容元件；14缓冲外引脚；15绝缘固定框架；16金属弹片；17线路板通孔；18重布线结构；19壳体；20密封胶；21硅胶填充体；22客户子板；23高频退耦电容；24共模抑制电容；25跨陶瓷层电连接组件；26侧缘电互连件；27贯穿式电互连件；28导电涂层；29支撑平台；30加热平板；31低回路焊盘；32固定柱；101键合材料；102键合引线；103垂直连接件；104电化学金属孔；105金属导接桥；106突起结构；107屏蔽层；108大直径垂直导接件；110门极键合线；111源极键合线；112功率键合线；121电连接孔；130垂直电连接通路；131/132突起结构；133导热/导电互连材料；134金属球；135导热柱；135a导热柱顶端；135b导热柱底端；136导流装置；137高导热区域；138低导热区域；139门极引线；141陶瓷材料；142高导热电绝缘颗粒；143壳体；144高导热互联；145超高导热填充料；151固定框架；200开关元件；201多层线路板的第一表面；202多层线路板的第二表面；301绝缘导热层的上表面；302绝缘导热层的下表面；400电极；601安装孔；602铜柱；603焊盘；611大深沉孔；612小过孔；621功率引脚；622信号引脚；631铜柱；632覆铜层状电极；641/642区域；643电绝缘引脚支架；644导热电绝缘材料；A/B/C pin脚位；Bottom半导体功率器件正面；C1/C2电容；Cbus母线电容；Ccer陶瓷等效电容；Cth分布电容；Cy1外加Y电容；Cy2集成Y电容；D1-D4垂直连接件；DBC绝缘导热板；Drain漏极；Driver驱动器；Gate/G1-G4门极；H1第一表面到Top面的距离；H2第一表面到下表面的距离；H3第一表面到上表面的距离；H4第二表面到下表面的距离；HC高频电容的高度；Icom共模电流；L1模组厚度；L2绝缘距离；L3气隙；Line_G布线地；Lloop回路寄生电感；Lth分布电感；Q1/Q2/Q3/Q4/Q1-1/Q1-2/Q1-3/Q2-1/Q2-2/Q2-3半导体功率器件；Q10高热密度的功率半导体晶片；Rin阻尼；Rth接触电阻；Source/S1-S4源极；Top半导体功率器件背面；V1-V4垂直连接件；x模组长度所在轴；y模组宽度所在轴；z模组高度所在轴。
 具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
如图2A所示，本发明实施例公开了一种高频大功率封装模组，包括：多层线路板2、绝缘导热板、塑封体7、至少一个功率变换桥臂及至少一个高频电容1；这里的多层线路板2即电路层，并非限制为独立的多层线路板，也可以指多层电路的布线层，亦可以为模组工艺中形成的具有相同功能的布线层，以下皆以多层线路板指代；这里的x轴和y轴代表模组的长度方向和宽度方向，且x轴和y轴构成模组的水平面，z轴代表模组的高度，以下皆同。
功率变换桥臂包括至少两个串联连接的半导体功率器件Q1、Q2，高频电容1与功率变换桥臂并联，形成高频回路。绝缘导热板上设置至少一个功率变换桥臂，塑封体7填充多层线路板与绝缘导热板之间的间隙区域。
半导体功率器件Q1、Q2的正面与多层线路板电连接，半导体功率器件Q1、Q2的背面与绝缘导热板的下表面热连接或电热连接。
多层线路板在其投影方向上，至少与其所属的高频回路的半导体功率器件Q1、Q2部分重叠。
如图2A所示，半导体功率器件通过键合材料101键合至绝缘导热板DBC上，其正面电极通过键合引线102的方式和绝缘导热板的布线层实现电连接，多层线路板2叠于绝缘导热板之上，多层线路板2上搭载有高频电容1。绝缘导热板可以为直接键合覆铜板(简称DBC，以下也用DBC指代绝缘导热板)，包括绝缘导热层3和上金属层4以及下金属层5，其中，上金属层4设置于绝缘导热层3的上表面，下金属层5设置于绝缘导热层3的下表面，绝缘导热板可以为陶瓷绝缘板，也可以是印刷电路板，并不以此为限。多层线路板2和绝缘导热板之间通过垂直连接件103实现电连接。多层线路板2和绝缘导热板之间通过塑封料7实现机械连接和电气绝缘，并有效提高环境保护能力。本发明实施例的键合材料101包括但不限于钎料、银或铜等烧结材料，本发明实施例的上金属层4和下金属层5的材料为铜。
如图2B所示，在高频电容1的电流环路上，相邻垂直连接件103内通过的电流被反向设置，因此该回路电感可以被控制在较低水平。
在其他实施例中，如图2C所示，绝缘导热板与多层线路板2之间的电连接还可以通过电化学金属孔104实现。
如图2D所示，半导体功率器件的正面电极通过金属导接桥105实现和多层线路板2的互联，相对键合引线102而言，金属导接桥105可以有更小的连接阻抗。金属导接桥105和半导体功率器件之间的连接材料包括但不限于钎料、银或铜等烧结材料。
如图2E所示，半导体功率器件的正面电极可以通过垂直连接件103直接与多层线路板2相连，也可以通过金属导接桥上设置的突起结构106实现和多层线路板的直接互联。
如图2F所示，多层线路板2可以在塑封体7表面电镀、蚀刻实现，减小材料匹配需求，提升可靠性。
如图2G所示，多层线路板2可以双面放置元器件，以集成更多功能。
在其他的一些实施例中，如图2H所示，在高频电容1和半导体功率器件组成的高频回路的包络区域内设置一屏蔽层107，屏蔽层107可以被连接到一固定电位上。如图2I所示，屏蔽层107也可以不和其余电位连接，例如屏蔽层107设置在多层线路板的内部。该实施例通过设置屏蔽层107可以进一步降低回路寄生电感。
如图3A所示，绝缘导热板上设置有两个开关元件200串连形成的半桥电路。两个开关元件200分别由三颗半导体功率器件(譬如Q1-1、Q1-2和Q1-3或者Q2-1、Q2-2和Q2-3)并联组成，实际使用时组成每个开关元件的半导体功率器件的数量并不以此为限，可根据需要自由调整。并联芯片的门极均独立增加门级电阻(图中未示出)，以改善并联芯片之间的动、静态均流。在绝缘导热板上根据需要设置垂直连接件103，实现与多层线路板2的电连接。图3B为叠层设置多层线路板后的示意图，多层线路板上和高频电容1两端相连的布线Vbus+或者Vbus-，在水平方向上的投影至少和半导体功率器件在水平方向上的投影部分重叠，以获得最小的回路电感。从图3A中可以进一步看出，在并联芯片之间，如Q1-1、Q1-2和Q1-3之间，外围芯片Q1和Q3的外侧以及绝缘导热层的布线层上可以分布式设置垂直连接件103，如D1-D4，V1-V4，以构造多个高频回路。使得(Q1-1、Q2-1组)(Q1-2、Q2-2组)(Q1-3、Q2-3组)的高频回路阻抗近似相当。这相对传统的平面型布置具备更低、且更均匀的高频回路阻抗，这不仅可以降低开关器件的电压应力也可以进一步改善模组高频均流特性。参考图3C，经过高频电容1的高频电流实际经过的为一3D回路，在水平面的投影方向上的电流环路参考图中的回路所示，由于高频电容1可以被分布设置在(Q1-1、Q2-1组)的中间，因此其两侧的两个高频电流形成的磁场是相反的，可以有效降低对外部元件的干扰提高系统的可靠性。
在其他的实施例中，如图4A至图4C所示，电路拓扑C1/Q1/Q2/Q3形成一高频回路，C2/Q3/Q2/Q4形成另一高频回路。图4B为绝缘导热板的布线图。图4C叠层设置多层线路板后的示意图，多层线路板上和高频电容1两端相连的布线，在水平投影方向上至少和与其所属高频回路相关的半导体功率器件部分重叠，以获得最小的回路电感。在本实施例中，部分用于连接绝缘导热板DBC和多层线路板2的垂直导接件可以采用不同的直径，譬如在DBC的四个侧面夹角的位置设置大直径垂直导接件108(即第一垂直连接件)，如此可以确保绝缘导热板DBC和多层线路板2组装的平行度，降低后续组装的难度。譬如在塑封过程中，绝缘导热板DBC和多层线路板2之间的平行度差会导致溢胶，采用大直径垂直导接件108，可以解决类似的问题。更进一步的，至少一个大直径垂直导接件108和至少一个功率端子的电性相同，该大直径垂直导接件108在垂直面的投影和该功率端子部分重叠，使得大直径垂直导接件108所在的回路中的寄生阻抗降低，提升产品的电性能。
更进一步，同时参照图3A和图4B，多个并联的半导体芯片的门极均为独立控制，门极键合线110、源极键合线111和功率键合线112键合完成后，每个半导体芯片都可以单独测试，当发现失效芯片时，可以通过去掉绝缘导热板DBC和多层线路板2之间相应的垂直导接柱，将这个失效芯片从多个半导体芯片并联中单独隔离出来；同样的，每个半导体芯片的功率电极也可以在绝缘导热板DBC上单独隔离出来，并通过相应的垂直导接件103连接到多层线路板2上。因此，在安装多层线路板2之前，首先完成绝缘导热板DBC的Die Bond和Wire Bond，接着完成每个Die的完整特性，进一步筛选后，再进行多层线路板2的安装。相比于测试在模组完成后进行的制程，可以避免各种物料的浪费。
如图4D所示，半导体芯片(即半导体功率器件Q1或者Q2)朝向多层线路板2一侧的电极可以通过在多层线路板2以及塑封料7内钻孔，并通过金属化工艺沉积金属，如铜等，形成电连接孔121实现半导体芯片和多层线路板2之间的电连接。电连接孔121的钻孔工艺可以通过机械及激光加工的方式实现，为了避免钻孔过程中对半导体芯片正面电极的损伤，可以如图4D所示，在半导体芯片朝向多层线路板2的一侧通过焊料、烧结银等方式在表面键合金属层(如铜层)，键合金属层的厚度大于50um，优选的可以大于200um。另一方面，也可以在半导体芯片表面直接金属化较厚的金属层。在本实施例中，在绝缘导热板DBC装配阶段测试时，可以对失效芯片通过不设置相应的电连接孔来实现隔离；或者在设置了电连接孔后，对模组进行测试时发现的失效样品，也可以通过机械、激光和化学等方法去除对应的电连接孔，用来隔离失效样品。
更进一步的，如图4E所示，半导体芯片朝向多层线路板的一侧电极全都通过在多层线路板2以及塑封料7内钻孔，并通过金属化工艺沉积金属实现电极和多层线路板之间的互联，这可以对失效芯片进行更完整的隔离。
如图5A和图5B所示，本发明另一实施例还公开了一种高频大功率封装模组，包括至少一个功率变换桥臂和至少一个高频电容1，功率变换桥臂包括至少两个串联连接的半导体功率器件，高频电容1与功率变换桥臂并联。为了降低变换的开关损耗，追求开关元件的极致高速，就需要降低上述三个元件形成的回路电感，其中高频电容1的两极分别为直流母线的Vbus+和Vbus-两极。本发明所述的半导体功率器件Q1、Q2包括但不限于第三代半导体功率器件，如GaN器件、SiC器件等。
以GaN器件为例，常用的是平面型器件，即其Pure Die的三个电极在同一面(Top面)。因此，其Top面的PAD非常密集。为了减少互联电阻和电感，本发明将Chip Size的GaN Top表面PAD，直接电性互联到一高精度的多层线路板2(PCB)的第一表面201上，其中Vbus+或者Vbus-至少一极，通过内层电连接层(Via)，互联第一表面201和第二表面202，使得回路电感通过两层的耦合，变得极小。
相较于图1的传统封装的近10nH级别，支持100KHz以下的应用为宜，本发明有机会实现1nH以下的回路电感，足以支撑MHz级别的应用，效果可想而知。如此，保障了回路电感，为高频化的高速开关提供了基础。显然，为了实现低回路，两个半导体功率器件Q1、Q2的至少其中一颗，至少有两个电极，比如源极Source和门极Gate焊接到多层线路板上。
同时，GaN器件的反面，通过高导热系数的材料，热互联到一绝缘导热板(DBC)上，如陶瓷基板。DBC包括绝缘导热层3，以及分别设置在绝缘导热层3上下表面的上金属层4和下金属层5。绝缘导热层3既可以将热传导到模组表面，又起到电性绝缘的作用，方便安装散热器6(可参照图6所示的散热器6)。由于两个半导体功率器件Q1、Q2优先焊接到高密度线路板上，半导体功率器件Q1、Q2的背面高度不易平齐，因此，高导热系数的材料厚度需要比较厚，比如50um甚至200um以上。因此，两半导体功率器件Q1、Q2的Top面连接到DBC的，尽量只有一个大面积PAD，比如漏极Drain或者源极Source，以减小对连接精度的要求。
如图5C所示，在电子电路中，通常需要搭载不同类型的半导体芯片，尤其是垂直结构的半导体芯片，其厚度和半导体芯片的性能息息相关。为了可以装配不同厚度的半导体芯片，在本实施例中，通过不同厚度的突起结构131和132(譬如铜柱)来实现。在其他的实施例中，如图5D所示，将绝缘导热板DBC的下金属层5的部分减薄，用来适配不同厚度的半导体芯片。另外，因为半导体芯片表面的突起结构131或者132的高度通常在50um至300um之间，DCB的金属层的厚度在100um至500um之间，突起结构和金属层吸收厚度公差的范围有限。而在图5E所示的实施例中，采用在半导体芯片的表面植入金属球134的方式，来解决厚度公差的问题。金属球134的直径在100um至1mm之间，而且直径可以根据实际需求进行调整，使得吸收厚度公差的能力进一步加强。在该实施例中，金属球134的材质可以是金属，如铜、铁、镍、铁镍合金或者焊料球等。这些金属球134不仅具备了不同的电阻率，更具备了不同的导磁特性，可以用来实现不同的电阻及电感。更进一步的，同一颗半导体芯片在不同的位置可以搭载不同的合金球，用来匹配同一颗半导体芯片的局部区域的不同寄生参数(即电阻或者电感)的需求，以提高同一颗半导体芯片内部不同位置的动静态特性的一致性。更进一步，可以在多个并联的半导体芯片之间通过使用不同材料的金属球134进行差异化排列，可以提升多个并联芯片之间的动静态特性的一致性。此外，模组内的所有半导体芯片的一面的电极均可以采用金属球的方式实现和对外连接，这样可以进一步降低芯片表面金属化直接形成铜柱的成本及开发周期。因此，本实施例可以进一步缩短产品开发周期、降低成本。
如图5F，为了进一步降低模组和散热器之间的寄生电容，寄生电容在跳变电压下引起共模噪音，因此将半导体芯片的静电位电极源极Source和DBC的布线层相连。同时为了降低半导体芯片至DBC的Top面的热阻，需要尽量增加半导体芯片和DBC之间的连接面积。以Q2为例，Q2的源极Source与DBC对应的铺铜区域需要尽可能大，Q2的门极Gate与源极Source同位于半导体器件Q2的Top面，在将半导体芯片与DBC组装时，门极Gate容易与源极Source短路，因此在门极引线139与门极的连接焊点上进行点胶处理，保护门极引线与门极的焊点不受源极Source的装配影响。
在本实施例中，高频电容1设置于线路板2的第一表面201，但并不限于此，高频电容1也可以设置于线路板2的第二表面202。而门极Gate也可以通过焊接设置于DBC上，如图5G所示。但此时DBC的下金属层5和上金属层4的厚度不能过厚，比如薄于0.1mm，这样就会降低DBC两个金属层表面的x轴及y轴构成的平面方向的水平热扩散能力，需要增加半导体芯片在z轴方向的垂直散热通道的散热能力。为了更好地解决垂直方向的散热问题，如图5G所示，在半导体芯片在垂直方向所对应的绝缘散热层3的外表面(即上金属层4)上设置导热柱135，可用于液冷散热或供液冷散热装置使用，如图5H所示。因为水平方向的导热可以忽略，因此在半导体芯片在水平面投影之外的位置，可以减少导热柱135的数量，仅用于调整液流方向即可；甚至可以不需设置导热柱135；即导热柱135在半导体芯片水平面投影内的设置数量密度，大于在半导体芯片水平面投影之外的设置数量密度。因为上金属层4和下金属层5的铜层很薄，绝缘导热层3可以只采用在绝缘导热材料表面电镀铜即可。
在另一实施例中，如图5I所示，混合基板3a包括两种导热材料构成，半导体芯片在混合基板3a上的投影部分(即高导热区域137)可采用高导热材料，混合基板3a的其余部分(即低导热区域138)可采用相对导热系数较低的低导热材料，更进一步，高导热材料的导热系数大于低导热材料的导热系数的两倍。具体的，高导热材料可以是高导热颗粒，比如高纯度金刚石颗粒阵列，尤其是整齐排列的金刚石颗粒与陶瓷材料混烧而成的阵列。因为金刚石的导热系数十倍于陶瓷材料的导热系数，所以只要金刚石在该区域的占比大于10％或者大于20％，即可大幅度提升等效导热系数。本实施例所揭露的混合基板3a的结构可适用于本发明所揭露的所有实施例，并且也适用于厚铜DBC方案和其它传统封装方案。另一方面，因为本实施例为立体结构，即绝缘导热板的一面用于散热，另一面用于电性能连接，因此无法通过双面散热来升级散热能力，需要在散热面进行更一步处理来提升散热能力，如图5I所示的半导体芯片的Die Bond，还可以使用烧结银工艺，用来提升高结温运行能力，进一步提升散热能力。
混合基板3a的一种应用实施例如图5J所示，混合基板3a还可以包括上金属层4和下金属层5，其下金属层5的底面通过高导热互联144与高热密度的功率半导体晶片Q10连接，高导热互联144可以为烧结银，通过烧结将高热密度的功率半导体晶片Q10固定到混合基板3a上；混合基板3a的顶面通过高导热互联144与导热柱135连接，导热柱135一般采用铜材料，其导热率为400W/(m·K)，当使用高导热的混合基板后(金刚石的导热率高于2000W/(m·K))，又因为导热柱的高度大于混合基板的厚度，使得铜导热柱成为散热瓶颈。因此在图5J所示的实施例中，导热柱135采用碳纤维管或者一种复合体，这里的复合体可以是具有高导热特性的金属壳体143包覆超高导热填充料145，金属壳体143可以采用铜材料，超高导热填充料145可以是碳纤维管、石墨烯片或者相变液体(热管)。图5J所示的结构将高热密度的功率半导体晶片产生的热量导到模组外表面，再由多个高导热系数的导热柱135传导到导热柱表面，导热柱表面跟液流(Cooling Liquid)进行热交换，实现高效散热。本发明所揭示的混合基板，可适用于本发明所揭示的所有实施例，也可适用于其它实施例中，只要满足以上技术特征即可。
另外，本发明还揭露了大功率应用下，多晶片并联的实施例，如图5K所示。传统的多晶片并联，多采用多晶片和其驱动器设置于同一平面的封装的结构，使得驱动器到各芯片之间的距离不相等，从而使得每个晶片接收到的驱动信号不一致，使得多晶片并联后产生不均流现象。本发明揭示了一种多晶片并联的立体封装，可以解决多晶片并联驱动的一致性问题。如图5K所示的底视图和侧视图，4颗晶片以2x2的排布设置于多层线路板的第一表面201上，且每颗半导体晶片的门极就近排布；驱动器设置于多层线路板的第二表面202上，DBC的下金属层5贴合4颗晶片的顶面。参照图5K所示的底视示意图，去掉了多层线路板2，驱动器Driver设置于2x2排布的4颗晶片的中心，即驱动器在第一表面的投影与每颗半导体晶片在第一表面的投影都部分重合，使得每个驱动输出脚位与对应的晶片的门极Gate之间的走线距离相等，而且距离最短；还可以通过多层线路板2的布线层均匀布线，提升每个驱动回路的一致性；即可实现每个晶片之间的均流，还可以实现高速驱动。
综合上述散热的优化结构，可以实现高频大功率应用。可以采用一颗大电流驱动器Driver驱动多颗半导体晶片，也可以每颗半导体晶片都由各自驱动器驱动。针对多颗驱动器的方案，还可以同时采样每颗半导体晶片的电流，将采样的电流信息反馈给驱动器，对每颗半导体晶片的驱动进行实时差异化调整，实现主动均流控制。这里的多颗半导体晶片并不仅限于四颗，也可以为三颗或其它，只要使得驱动器在多层线路板的第一表面201上的投影与每一个半导体晶片在多层线路板的第一表面201上的投影都部分重合即可。
如上图5F所示，通过将两个半导体晶片的脚位交错焊接，譬如一个半导体晶片的源极和另一个半导体晶片的漏极同设置在线路板上，一个半导体晶片的漏极Drain(静电位)和另一个半导体晶片的源极Source(静电位)同设置在下金属层5上，实现了低共模干扰，大大降低了系统应用时，对共模电感的需求，减少了成本，降低了体积。图5L所示的实施例，揭示了实现相同效果的另一个技术方案。在本实施例中，半导体晶片采用衬底电位可灵活设置的LD MOS，譬如低压GaN MOS，或者以陶瓷(蓝宝石)这样的电绝缘材料作为衬底的GaN MOS。这一类半导体晶片的衬底热连接到DBC的下金属层，并将与下金属层热连接的脚位设置为静电位，比如Vbus+或Vbus-或者功率GND等。
本发明实施例公开的高频大功率封装模组还包括塑封体7，塑封体7最薄可以控制在绝缘导热板DBC的上表面和多层线路板2的第一表面201之间，并且实现安规绝缘能力。如图6所示，塑封体7填充多层线路板的第一表面201与绝缘导热板的上表面之间的间隙区域，绝缘导热板的上表面外露，多层线路板的第二表面202及侧缘外露，多层线路板的第二表面202或侧缘上设置有外部电极11，外部电极11与功率变换桥臂电连接。该实施例大大提高了机械强度，可以支持更薄的DBC，比如0.4mm甚至以下绝缘厚度，相对于图1的硅胶封装，至少0.6mm以上的厚度，可以实现更低的热阻，下降30％以上，支持更大功率。
本发明实施例公开的高频大功率封装模组的半导体功率器件的正面(即Bottom面)与多层线路板的第一表面201电连接，半导体功率器件的背面(即Top面)与绝缘导热板的下表面302热连接或电热连接，半导体功率器件与DBC热互联以焊接为佳，因此，半导体功率器件的背面以金属化处理为佳。
高频电容1与多层线路板的第一表面201或多层线路板的第二表面202或绝缘导热板的下表面电连接，高频电容1的至少一个电极通过内层电连接层与至少一个半导体功率器件的至少一个电极电连接。需要注意的是，本发明中所指的半导体功率器件的Bottom面和Top面只是一个相对的概念，并不是特指某一个面是正面或背面。
作为实施例，如图6所示，由于本发明追求超薄，并用多层线路板的第二表面201做表贴焊盘(SMD PAD)，电性互联到客户主板8上，实现客户整体系统的最薄化，或者使得本发明模组占客户系统的空间尽可能小。当模组厚度L1薄于一定程度时，比如5mm时，其厚度薄于安规绝缘所需的爬电距离时(通常大于6mm)，可以将散热器6只与绝缘散热板DBC接触，保障散热效果，而与模组边沿的塑封料之间有不小于1mm的气隙，来增加绝缘距离L2，即塑封体7的上表面与散热器6之间具有气隙L3，气隙L3大于1mm。在其他实施例中，塑封体7的上表面与散热器6之间可以设置电绝缘片9，用于增加提升绝缘效果，如图6所示。
为了实现更小回路电感，高频电容1以集成在模组上为宜，且高频电容1应尽可能靠近半导体功率器件Q1、Q2。在实际应用中，存在两个原因，会导致高频电容与半导体功率器件不容易靠近。一则，大功率往往意味着高于200V以上的高压场合，比如400V Vbus，需要630V的陶瓷电容，这种高压应用的电容，往往需要较高高度才能实现所需的容量，比如1mm及以上。再则，为了实现更小的热阻，半导体功率器件Q1、Q2的厚度要尽可能薄，这就导致高频电容1会被DBC阻挡。这里是以高频电容1为例，事实上也适用于其他的较高元件。
如图7A所示，较高元件焊接在多层线路板2上，为了帮助半导体功率器件Q1、Q2热扩散和提升热容，同时增强瞬态和稳态的热管理能力，DBC双面覆厚铜，即绝缘导热层3的上金属层4和下金属层5。那么可以通过将高频电容1上方的下金属层5减薄或者去除，让出空间，使得高频电容1可以置于绝缘导热层3和多层线路板2之间。也就是高频电容1与多层线路板的第一表面201电连接，且高频电容1的高度Hc满足以下条件：H1≤Hc＜H2；
其中，H1为多层线路板的第一表面201至半导体功率器件Q1、Q2的Top面的距离，H2为多层线路板的第一表面201至绝缘导热层的下表面302的距离；绝缘导热板延伸至高频电容1的上方，位于高频电容1与绝缘导热板之间的下金属层5通过减薄或去除的方式与高频电容1隔离。
如图7B所示，较高元件焊接在多层线路板2上，在高频电容1的高度Hc高于绝缘导热层的下表面302和多层线路板的第一表面201之间的高度时，那么可以将整个绝缘导热板内缩，使得高频电容1上方与模组上表面之间只有塑封材料。塑封材料的厚度以0.4mm以上为宜以保证电绝缘强度。即高频电容1与多层线路板的第一表面201电连接，且高频电容1的高度Hc满足以下条件：H2≤Hc＜H3；
其中，H2为多层线路板的第一表面201至绝缘导热层3的下表面302的距离，H3为多层线路板的第一表面201至绝缘导热层的上表面301的距离。绝缘导热板3仅位于半导体功率器件Q1、Q2上方。
如图7C所示，由于高频电容1高度受限，为了追求极致热性能，又将绝缘导热板DBC的厚度尽可能薄。所以，即便采用图7B的方案，高频电容1上的塑封料厚度可能不能满足安规要求，甚至裸露在外。因此，可以采用图7C的方案，即将高频电容1放置到多层线路板的第二表面202上。不仅可以同样减小回路，还可以减小模组的尺寸。即高频电容1与多层线路板的第二表面202电连接，高频电容1的两个电极分别通过垂直电连接通路130与内层电连接层及多层线路板的第一表面201电连接。
图7D和图7E的方案，这些较高元件焊接在绝缘导热层的下表面302上，其空间不足之对应部分，将多层线路板2的局部区域减薄或者去除。绝缘导热层3的下金属层5也可以减薄。即高频电容1与绝缘导热层的下表面302电连接，高频电容1的至少一个电极通过一电连接件(图中未示出)与内层电连接层电连接，且高频电容1的高度Hc满足以下条件：H1≤Hc＜H4；
其中，H1为多层线路板的第一表面201至半导体功率器件的Top面的距离，H4为多层线路板的第二表面202至绝缘导热层的下表面302的距离；位于高频电容1下方的多层线路板2通过减薄或去除的方式与高频电容1隔离。
作为实施例，如图8A至8F所示，在高频场合，模组内部回路要小，但由于空间有限，内部电容量有限，所以，需要客户主板8的上电容与模组内部的高频电容1就近放置。所以，不同应用场景的模组，包括不同功率、不同内部电路，需要最优化的封装形式和出Pin排布，这样就意味着会有非常多种的封装。而塑封封装跟硅胶封装不同，模具的成本非常高昂。本实施例公开了一种高频大功率封装模组的制作方法，来有效规避模具的成本非常高昂的问题，既可以保留本发明模组成品的性能，又可以通过多类模组共用一个模具的方式来降低成本，更可以实现自动化大批量生产，进一步降低成本，步骤如下：
第一步Sa1：将多个模组的半导体功率器件Q1、Q2和其他必要元件SMD到PCB Panel的相应分区上；若有需要，PCB可以双面SMD元件，如图8A所示。
第二步Sa2：可选的，预塑封半导体功率器件Q1、Q2与多层线路板的第一表面201之间的区域，形成热阻电连接层12，来提升半导体功率器件Q1、Q2强度和排除底部气泡，如图8B所示。
第三步Sa3：粘结/焊接各模组的DBC到相应的半导体功率器件Q1、Q2Top面上；若是图8D和图8E和图29C的方案，那么DBC在与半导体功率器件Q1、Q2热连接前，先焊接高频电容1和共模抑制电容24等必要元件，如图8C所示。
第四步Sa4：以PCB Panel的周边为塑封密封区，防止塑封溢出，对PCB的上方进行有效塑封，形成塑封体7，如图8D所示。
第五步Sa5：可选的，对DBC的上金属层4一侧进行打磨，去除溢胶，提升绝缘导热板DBC平整度降低后续安装的散热胶厚度，提升各模组的厚度一致性降低后续多模组安装的散热胶厚度，如图8E所示。
第六步Sa6：进行切割，将各模组从Panel分离，如图8F所示。
通过本实施例做出来的模组或者在模组制作过程，有一个特征，因为切割分离可使得模组侧面周边一圈以及塑封体7侧面与多层线路板的侧面是平齐的。由于是一个大Panel切割成多个模组，所以只要是这个大Panel内部的尺寸满足多个模组组合的尺寸，就可以使用同一个模具，也就是一个模具可以制作多个类型的模组。
在其他实施例中，如图9所示，半导体功率器件可以内埋在一个多层线路板2中，并通过过孔和电镀将其电极400引出后，分别与绝缘导热板及引脚电互连。这样可以省去焊接和打线工艺，可靠性更高。
作为实施例，如图10所示，平面型器件如GaN，其半导体功率器件的Top面电极往往需要接到某一合适电位，如其源极Source极或者门极Gate电极。由于其Top面接到DBC，所以半导体功率器件的Top面电极需要依次通过下金属层5及导电组件10电连接至多层线路板的第一表面201，将其从DBC连到多层线路板2。只是，该电性连接只是为了半导体功率器件获得必要电位，无需大电流，因此DBC上不需要铺设厚铜。
而使用垂直型器件如SiC时，其功率电极分置于器件的上下表面，其Top面电极往往是静电位电极。因此，其漏极Drain需要通过下金属层5及导电组件10电连接至多层线路板的第一表面201，且下金属层5为厚铜层。
作为实施例，可参照图5A所示，上述多层线路板2和DBC的之间的导电组件10的高度，以及半导体功率器件Q1、Q2的高度精度要求很高，会造成成本高和工艺复杂的问题。由于只是为了稳固半导体功率器件base的电性，更优的做法是在半导体功率器件内部，通过其内部的导电通孔，将base连到所需电极，如源极Source，这样就可以省去封装级别的挑战和成本。
作为实施例，如图11所示，由于电动汽车的趋势，SiC/GaN在车规场合的应用越来越普及，尤其是电动马达的驱动。根据汽车的特殊性，常有秒级的加速，即秒级的高功率输出。那么，在模组中，为半导体功率器件Q1、Q2设置秒级的热容，则是最为有效和经济的。半导体功率器件Q1、Q2由于很薄，其横向热阻很大，难有文章可为。半导体功率器件Q1、Q2Top面已经接DBC，在封装应力允许的前提下，自会尽可能使用尽可能厚的DBC覆铜，获得秒级低热阻高热容。所以，只能从半导体功率器件Q1、Q2的TOP层找机会。但TOP层因为电性走线的需求，表面覆铜厚度受到限制，难以得到足够大的秒级热容。所以，本发明选择在半导体功率器件Q1、Q2的TOP面正下方的线路板的内层电连接层处埋低热阻大热容物体，比如厚铜。通过高密度排布的高热容元件13，实现了多层线路板2的第一表面201、第二表面202与内层电连接层的互联，并实现了低热阻互联。这样既实现了表层的高精度电互联，又使得半导体功率器件Q1、Q2额外获得的低热阻大热容，为模组瞬态大功率冲击提供了支持。
如图6所示，模组通过SMD工艺安装到客户主板8。但这样在某些应用也有不足。比如多个模组同时安装在同一散热器6时，由于模组厚度公差，SMD工艺公差，常导致多个模组的散热面高度不一，需要更厚的导热硅脂来缓冲公差。厚的导热硅脂增加模组热阻，限制了功率。因此，需要实施例缓冲公差。
作为实施例，如图12A至12D所示。在模组SMD PAD上，植入缓冲外引脚14(Pin)。图12A为直插焊接引脚，焊接到客户主板8，靠焊料进行电性连接；图12B为直插压接引脚，将外引脚14压接到客户主板8的通孔内，靠Pin的缓冲弹性，形成接触力，进行电性连接；图12C为表面触点压接引脚，弹性Pin压接到客户主板8的SMD Pad；图12D为表面触点焊接引脚，弹性Pin焊接到客户主板8的SMD Pad。多模组安装时，厚度公差靠Pin的弹性或者插入深度差异来缓冲，使得可以使用最薄的导热硅脂，获得最低热阻，保障最大功率。
作为实施例，如图13A至图13E所示，在多层线路板2的内部将所需电极引导到多层线路板的侧缘，即形成模组侧面的多层线路板外侧Pin，再植入缓冲外引脚14。图13A为直插焊接引脚，焊接到客户主板8，靠焊料进行电性连接；图13B为直插压接引脚，压接到PCB通孔，靠Pin的缓冲弹性，形成接触力，进行电性连接；图13C为表面触点压接引脚，弹性Pin压接到客户主板8的SMD Pad；图13D为表面触点焊接引脚，弹性Pin焊接到客户主板8的SMD Pad。多模组安装时，厚度公差靠Pin的弹性或者插入深度差异来缓冲，使得可以使用最薄的导热硅脂，获得最低热阻，保障最大功率。
作为实施例，如图13A至13D所示，为了尽可能减小模组的塑封体7尺寸，提升产能，模组固定到散热器6的安装孔601可以不设置在塑封体7中。那么，可以加绝缘固定框架15在塑封体7上。绝缘固定框架15的切面图为L型，L型的一边，通过胶水粘在塑封体7侧面，进行机械加固和电绝缘加固。L型的另一边有螺丝安装孔601，用于安装固定框架15到散热器6。
作为实施例，如图13E所示，采用Z型的弹性绝缘固定框架15，弹性绝缘固定框架15的一端为绝缘材料的部分固定框架151，其压在模组多层线路板2的外侧边沿；弹性绝缘固定框架15的另一端为金属弹片16(即弹性件)，通过螺丝压在散热器6上；金属弹片16压塑在部分固定框架151之中。金属弹片16的压力通过部分固定框架151传递到模组之上，形成安装力。而塑料部分保障了绝缘所需。
作为实施例，如图13F所示，采用L型的绝缘固定框架15。该绝缘固定框架15具备一定的弹性来平衡厚度公差平衡力。绝缘固定框架15的一端压在模组线路板外侧边缘，螺丝将绝缘固定框架15、模组、散热器6锁在一起，形成均衡压力。
图13E和图13F同时也示出了图7C所示技术方案的出Pin方式，即充分利用绝缘固定框架15与多层线路板第二表面202之间的间隙，在多层线路板的第二表面202上设置SMD元件，比如Cbus、Driver等等必要元件。既充分利用空间，还大幅度下降模组尺寸，降低成本并提升成品率。图13E和图13F所示的方案的缓冲外引脚14是与设置在多层线路板的第二表面202上的外部电极电性连接的，需要注意的是，缓冲外引脚14也可以直接与线路板内部的电路结构电连接。
前面各实施例，模组植入缓冲外引脚14，无论侧面还是底部，最简单的做法都是reflow进行焊接。但是，塑封体7由于是硬固化，因此需要将所有不同材料硬连接在一起。而Reflow导致的塑封体7内部应力，容易破坏结构稳定性，导致可靠性问题。本实施例提出在塑封前进行植Pin的技术方案，有效地解决了这个问题。详细的技术方案如图图14A至图14E所示。
第一步Sb1：PCB Panel在植Pin处预留焊接用的。如图14A所示。
第二步Sb2：将Pin机械植入线路板通孔17中，Pin的顶部以不超过多层线路板的第一表面201为宜。如图14B所示。
第三步Sb3：在多层线路板2上的SMD元件reflow之前，先于Pin的顶部设置足够多的焊膏。这样reflow后，焊锡不仅将Pin与PCB进行可靠的电性连接，还将Pin与多层线路板之间的间隙充分填充，防止塑封时溢胶。如图14C所示。
第四步Sb4：Reflow SMD焊接多层线路板2上的其他元件。如图14D所示。
第五步Sb5：塑封并形成塑封体7，如图14E所示，后续过程与图8A至图8F类似。
至此，植入的每个缓冲外引脚14都可以参照如图12A的直接焊接方式、图12B所示的直插压接方式、图12C所示的表面压接方式以及图12D所示的表面焊接方式与客户主板8进行固定电连接。而无需塑封体7经受高温reflow，使得模组可靠性更佳。并且，Pin可以根据实际需要进行设计，从而降低多层线路板2内部电路横向扩散电阻，大大提升的多层线路板的利用率和模组电性能。
如图15A至图15D所示，通过重布线结构18，将各Pin统一出至所需位置，方便客户使用。且同时兼顾模组内部线路板的出Pin灵活性，保障线路板的内部性能。
作为实施例，如图16A至图16F所示，为图13F和图13F的方案的衍生。为了更好的提升模组性能，往往需要就近放置Cbus、驱动或者控制IC及其外围电路，如果都与半导体功率器件Q1、Q2放置于多层线路板2的同一面，一则导致线路板的面积增大，从而模组体积增大；二则会导致高频回路中的寄生参数增大，影响模组的高频性能；三则IC、电容温度高，影响模组中其它元件的性能和可靠性。本实施例将部分元件，比如Cbus、驱动IC或者控制IC及其外围电路，放置于多层线路板的第二表面202，远离热源，从而解决上述三方面问题，更可简化客户使用模组的便利性。如图16A，用封装好的IC等元器件，直接SMD到多层线路板的第二表面202；如图16C，半导体半导体功率器件Q1、Q2，Die Bond在多层线路板的第二表面202上，然后通过wirebond打线到多层线路板的第二表面202的PAD上，再用COB等工艺，加以固定和保护；或者如图16B，多层线路板的第二表面202放置好元件并互联后，再进行整面塑封、填硅胶、COB或者喷涂三防漆加以加强保护。这是因为若无防护，无论是防水防尘，和电性耐压绝缘间距，都会有较大牺牲，影响模组尺寸和可靠性。
图16D为图16C的进阶，即在模组PCB的两侧外缘加装填充组件(即第二表面保护件)，填充组件包括壳体19、密封胶20以及填充体21，壳体19通过密封胶20固定并覆盖在多层线路板的第二表面202上，壳体19与多层线路板的第二表面202之间填充有填充体21。多层线路板的第二表面202上的元件在填充组件圈定的范围内，因此实现填充体对电子元件的防护，这里的填充体可以为硅胶或者塑封料。
图16E和16F为图16D的两种不同实现方式。图16E是针对已经独立成型的塑封模组进行硅胶工艺流程而形成的结构示意图。所谓独立成型的塑封模组，指塑封后分板而得的单一模组，且模组中多层线路板的第二表面202已经安装完成相应电子元件，比如电阻电容驱动IC引脚等等。
先完成独立成型的封装模组；在欲硅胶填充范围的边界设置密封胶20；安装壳体19，壳体19通过密封胶20与模组固定；之后灌硅胶，将相关电子元件在模组壳体19内部进行硅胶保护，形成硅胶填充体21。由于是独立成型的塑封模组进行安装，所以该填充组件可以设置螺丝孔，兼顾模组对散热器6的安装功能。
图16F是针对塑封完成后但尚未分板的多模组塑封Panel的结构示意图。多模组塑封panel的多层线路板的第二表面202上已经安装完成各模组相应电子元件，比如电阻电容驱动IC引脚等等。先完成多模组塑封panel；在各模组内硅胶填充范围的边界设置密封胶20；安装各模组对应壳体19，壳体19通过密封胶20与模组固定；各模组区域灌硅胶，将相关电子元件在模组壳体19内部进行硅胶保护，形成硅胶填充体21；再进行分板。这样的好处是，可以大大提升硅胶填充的效率。但填充组件尺寸小于模组，因此不易独立承担成品模组对散热器6的固定安装功能。图16F的方案适合模组固定到散热器6的螺丝孔设置在塑封体7上，即在塑封体7的两侧，各自设置一螺丝孔，可以是全孔，或者为了节省空间设置成半孔。
图16B是通过多层线路板侧面出引脚的，电流通过多层线路板2横向汇集，电流损耗较大。作为双面塑封的实施例，垂直于塑封体7，预埋铜柱并在预埋铜柱形成过孔，并以铜柱顶端作为焊盘；或者电镀形成过孔和焊盘；或者预埋铜柱后，再在顶端电镀大面积焊盘。
如图17A，在平面上焊接引脚，焊接强度是很大挑战，或者在塑封体7或硅胶填充体中内埋铜柱602，再在铜柱602附近的塑封体7的表面电镀形成焊盘603，只是会增加成本，工序相对复杂。图17B和图17C使用一个大深沉孔611加多个小过孔612，大深沉孔由硅胶填充体或塑封体向所述线路板的第二表面内凹形成，大深沉孔表面以及相邻的塑封体7或硅胶填充体的表面电镀形成一个焊盘，多个小过孔612设置于大深沉孔611底部，且电连接焊盘和线路板，形成一个复用焊盘供大电流的功率引脚621焊接使用。由于小过孔612数量多，行程短，因此电阻小；大深沉孔611表面积大，直径大，引脚焊接强度大，电阻小。
如图17D，作为模组新型引脚设计。因为信号引脚622比较多，前面各实施例中，信号引脚622常有要求客户使用通孔。那么若间距大，则占地面积大，若间距小，则不容易在安装时对准。本实施例将信号引脚622设计为压力接触，且是跟客户主板表面的平面焊盘接触，而功率引脚621依旧使用通孔设计，保障大电流能力。这样，就可以在极小的尺寸下，实现非常便利的安装。
如图17E，将功率引脚621设置成螺纹，使用螺丝通过电缆引导到远处。将信号引脚622通过排线引导到远处。这是因为大功率场合，磁性元件和电容元件都很大，其与功率模组的电连接位置很难与他们的尺寸匹配，给系统设计带来了很大的挑战。本实施例，可以确保模组本体高频大功率的同时，也允许通过电缆进行功率引脚之间和信号引脚之间的互联。
作为实施例，如图18所示，由于塑封时，模流需要一定的间隙更能可靠排除气泡。如果半导体功率器件Q1、Q2直接焊接到模组多层线路板上，因为半导体功率器件Q1、Q2表面金属层很薄，通常薄于10um，意味着半导体功率器件Q1、Q2与PCB间的间隙最薄只有10um以下，不能可靠排气，会造成耐压不足等可靠性问题。一可行的方案为半导体功率器件Q1、Q2的Bottom面电极表面植铜柱631，抬高上述间隙至30um以上，以助模流可靠排气。另一可行的方案为先将半导体功率器件Q1、Q2进行封装，比如内埋工艺或者fanout工艺，通过封装形成的厚铜电极，使用封装的表面厚铜将气隙抬高，厚铜以厚于30um为佳。半导体功率器件Q1、Q2的Top面则直接大面积覆铜形成覆铜层或者通过封装形成的覆铜层状电极632，保障半导体功率器件Q1、Q2Top面的热阻不受明显影响。
[根据细则26改正 27.03.2023]
作为实施例，如图19A至19D所示，由于GaN/SiC这类功率器件有部分是常开式(Normal on)的，比如GaN的D Mode和SiC的JFET。这类器件具备更好的性能、成本和可靠性优势。但由于是Normal On的，通常需要用一个低压常闭式(Normal off)器件比如低压Si MOS或者E-Mode GaN FET来进行级联形成本发明实施例的半导体功率器件Q1、Q2。由于级联结构，既有功率回路，又有驱动回路，为获得最佳性能，两者都要尽可能小。
一个较佳地实施例是将一常开式第三代半导体子功率器件Normal On GaN/SiC与一低压常闭式半导体子功率器件Normal off SiMOS级联，常开式第三代半导体子功率器件与低压常闭式半导体子功率器件通过叠层封装的形式形成半导体功率器件Q1、Q2。即将低压常闭式半导体子功率器件的漏极Drain直接焊接在高压器件的源极Source上后进行封装。封装体的Top面将高压器件产生的热通过低热阻传出至封装体的Top面，将各电极、低回路电感引出或者内部互联。这样可以兼顾大功率和高频在Normal On器件上的实现。
作为进一步的实施例，至少一个半导体功率器件为一常开式功率器件Normal On GaN/SiC，常开式功率器件配合设置有一低压常闭式半导体功率器件Normal off SiMOS，常开式功率器件与低压常闭式半导体功率器件级联，低压常闭式半导体功率器件设置在多层线路板的第二表面202上，低压常闭式半导体功率器件的设置位置与常开式功率器件的位置相对应。即低压常闭式半导体功率器件和常开式功率器件分别SMD在模组多层线路板的第二表面202和第一表面201，并通过线路板互联。相当于未增加任何工艺环节的前提下，实现了大功率和高频互联。若低压常闭式半导体功率器件是Vertical MOS，可以直接在线路板上进行Die Bond和Wirebond工艺进行互联。若低压常闭式半导体功率器件是Lateral MOS，可以直接在线路板上进行SMD，将低压半导体功率器件进行互联。
作为实施例，如图20A至图20D所示，大功率变换器往往有复数个功率变换桥臂的需求，也就是复数个大电流高频电压输出引脚，如图20A中的Pin A、Pin B和Pin C。而作为Vbus的两个引脚Vbus+和Vbus-，为了减小模组内部电容的需求，Vbus+和Vbus-可以设计成复数对，方便客户应用主板上放置相应电容，以尽可能减小客户主板8电容与模组内部高频电容1之间的回路电感。
如图20B所示，Vbus+和Vbus-作为直流Pin放置于一侧，交流PinA/B/C放置于另一侧，方便客户设置大功率Bulk电容，和交流磁性或者电容元件。
由于本发明可以将模组尺寸做的很小，那么在某些高压场合，高压功率Pin(直流Pin、交流Pin)脚的间距紧张，没有空间放置信号Pin，比如驱动信号等。本发明由于多层线路板2的使用，可以灵活设置引脚位置，因此提出图20C的实施例，可以兼顾模组引脚间的耐压处理，更可以方便客户使用时的layout。
图20C中将功率引脚(直流端引脚Vbus+和Vbus-以及交流端引脚Pin A/B/C)分别置于上下两侧，将信号引脚622放置于两排功率引脚的中间位置。这样，信号引脚622就不会占用功率引脚的间距位置，使得缩小间距让模组尺寸更小，或者扩大间距让模组适用于更高的工作电压场景。
客户应用时，模组上下方的客户主板的线路板资源可以各自给直流功率引脚和交流功率引脚使用，使得大电流路径通畅。而信号引脚622可以从模组左侧或者右侧引出，如图20D所示，信号引脚622与功率引脚互相不干扰。
作为优选的，驱动引脚与功率引脚的最小间距需超过4mm，才能实现大于2KV的耐压。即模组内部集成信号与驱动输出隔离的驱动IC。允许客户在无需外部隔离元件的情况下，实现隔离驱动功率半导体的功能。这是传统模组无法在如此小尺寸场景，如6cm×4cm面积下，同时实现大功率和隔离驱动的。
作为优选的，多个驱动引脚通过预先集成的排插，以减小占地面积，并且兼容客户通过焊接，或者接插件引出信号引脚622。这是由于驱动引脚电流小，但若每个信号引脚622单独种植，焊接所需面积较大，导致驱动信号引脚间距拉大。
作为优选的，信号引脚622的引出，可以是柔性线路板扁平线。实现更小尺寸和更好的抗干扰能力。
作为实施例，如图21A和图21B所示，当模组SMD出Pin时，由于模组很薄，导致爬电距离不够。可以如图21A所示的区域641，将塑封体7磨出台阶来，或者如图21B所示的区域642，同时磨去部分多层线路板2和塑封体7，形成台阶形，来增加爬电距离。
作为实施例，如图22A和图22B所示，随着客户对安全系数要求的提高，要求模组功率引脚621与散热器6之间的爬电距离d越大越好，常常达到6mm甚至12mm以上。如果一味靠模组厚度来实现，显然是不经济、不实用的。本发明可以将功率引脚621内缩，充分利用线路板2的表面距离，甚至电绝缘引脚支架643的表面距离来扩充爬电距离。要实现等效爬电距离d，内缩避让的空间，绝缘材料表面至另一表面的空气距离要有一定的程度，比如d1间距在0.5mm以上以便客户插入绝缘片，或者1mm以上可以直接以空气填充。
如图22B所述，一味的内缩引脚，会导致引脚尺寸变小。因此，将电绝缘引脚支架643的外侧设置成台阶状，台阶上面与线路板之间的空气距离d2、台阶下面与客户主板8之间的空气距离d1都设置在0.5mm以上，以便客户插入绝缘片；或者d1和d2都设置在1mm以上，可以直接以空气填充。台阶的数量可以根据需要调整增加。
作为实施例，如图25所示，先前的实施例都以模组平行放置于客户主板8之上安装。也有多种场合需要模组垂直于客户主板8安装，这样有利于模组与散热器6单独先安装，获得最佳散热性能。只是模组出Pin需要从原先的垂直于模组散热表面，调整为平行。
如图23所示，使用垂直于模组表面的引脚，就近连接到客户子板22上。客户子板22可以设置高频退耦电容23，以及高压隔离驱动或者控制器等系统控制元件。客户子板22的一边如上侧边，连接功率磁性元件的高频引脚，即Pin A、Pin B、Pin C之一或者全部；客户子板22的另一边如下侧边，连接客户主板8，并通过主板连接Bulk电容。这样各自路径就短实现连接，且相互无干涉，可以实现更高的效率和功率密度。
作为实施例，如图24A至图24D所示，由于电容、驱动IC的最高工作温度往往低于SiC/GaN的工作温度。比如SiC的最高工作温度为175℃，而高频电容1的最高工作温度才125℃。所以，若不特别处理，会因为温度过高而影响高频电容的性能和可靠性。
如图24A，当这些元件设置在模组的多层线路板2的外侧时，可以在这些元件和客户主板8之间加导热电绝缘材料644，帮助这些元件降热。
如图24B以及图24C和图24D所示，不光电容等元件，高密度多层线路板的热极限温度往往也较低，比如145℃。那么，当半导体功率器件Q1、Q2温度达到175℃时，需要控制多层线路板的温度在145℃的话，多层线路板2就需要有自己的散热通道(即thermal path)Rth_PCBtoCase，即多层线路板2到周围环境的总等效热阻值。并且与半导体功率器件Q1、Q2之间需要有一定的热阻Rth_DietoPCB，那么这几个热阻关系，加上Die的功耗Pdie和Die到DBC外表面即模组Case的热阻Rth_DietoCase之间的关系要满足一定关系，使得半导体功率器件Q1、Q2通过多层线路板2导走的热量，在热阻Rth_DietoPCB上形成的温差，接近甚至大于Die和多层线路板的最高耐受温度差。也就是当半导体功率器件Q1、Q2达到最高温TdieMAX时，多层线路板温度要小于等于最高耐温值TpcbMAX。即(Tcase+(TdieMAX-Tcase)×Rth_PCBtoCase/(Rth_PCBtoCase+Rth_DietoPCB))≤TpcbMax。可以看出，Rth_DietoPCB适当增加有利于控制线路板的温度。由于1mOhm电阻的铜大概有等效于150K/W热阻。若希望10W的热形成30℃以上Die to PCB温差，那么热阻就是Rth_DietoPCB≥3K/W，即所有从Die连接到多层线路板的铜的并联电阻要大于0.02mOhm。
作为实施例，如图25A至图25E所示，为了解决前面实施例中，只用一次塑封，模流较难控制的问题。本实施例根据本案结构的特殊性，进行两次塑封。
第一步Sc1：根据需要，多层线路板2单面或者双面焊接相应元件，比如半导体功率器件Q1、Q2、高频电容1、连接DBC/线路板的铜柱等，如图25A所示。
第二步Sc2：将线路板2的第一表面201及半导体功率器件Q1、Q2一侧塑封形成塑封体7，塑封后保持半导体功率器件Q1、Q2Top面裸露，且在必要时，裸露的半导体功率器件Q1、Q2保持可焊性。比如在塑封时，对需裸露焊接面加保护膜；或者塑封后，磨平，镀金属层。由于塑封腔体较小，所以模流更易按需控制，如图25B所示。
第三步Sc3：焊接或者粘结DBC，使DBC跟半导体功率器件Q1、Q2之间有良好导热能力，必要时有导电能力，如图25C所示。
第四步Sc4：在一次塑封基础上，将DBC与一次塑封体7进行第二次塑封形成塑封体70。同样的，根据需要决定是否在塑封完成后打磨，如图25D所示。
第五步Sc5：分板形成相应的模组，如图25E所示。
作为实施例，如图26A至图26C所示，由于本发明适合于高频高压场合，意味着容易出现高压高频跳变的问题。为了更好散热，使用了塑封结构将绝缘导热层3的厚度降低，如0.4mm以下，甚至0.3mm以下，使得绝缘导热层3两面的上金属层4和下金属层5之间的寄生电容很大。而上金属层4是接散热器6从而接地的。如果下金属层5的电位是高频高压跳变，那么共模电流就会很大，导致系统电磁干扰的增加。
如图26A所示，各功率变换桥臂两端为直流电压，Vbus+和Vbus-的电位相对平静，不易造成大的电磁干扰。而功率变换桥臂的中点，如A、B、C点，则为高频高压跳变电位，系统的大部分电磁干扰都来自于这类电位。图26B所示为常规处理方法，即上下功率开关，如Q1、Q2的散热面均为漏极Drain电极，对应图26A，分别为Vbus+和A电位，所以，Q2的Drain即A电位会导致极大的电磁干扰。
如图26C所示，本实施例选用散热面相异的桥臂开关。如果是SiC/MOS/IGBT等功率电流垂直穿透半导体功率器件Q1、Q2上下表面的器件，上管Q1的散热面为Drain电极，下管Q2的散热面为Source电极。即接到DBC的电位分别为静电位，比如Vbus+和Vbus-，大大降低共模电磁干扰。
如果是GaN等功率电流在半导体功率器件Q1、Q2同一面流动的器件，上管Q1的散热面为Drain电极，下管Q2的散热面为Source或者Gate电极。即接到DBC的电位分别为静电位，比如Vbus+和Vbus-或者Vbus+和Vgs，大大降低共模电磁干扰。因为跳变电压和静电位是相对的，可以定义静电位为桥臂功率器件Vds电压即A电压的十分之一以下。对于通常A电压幅度大于400V的场合来讲，低于20V的驱动电压可以视为静电位。
作为实施例，如图27A至图27C所示，将用于抑制共模噪音的共模抑制电容24(Y电容)，就近集成在模组之中，使得共模噪音特别是高频共模噪音被压制在模组内部。
如图27A所示，往往功率变换桥臂中点即高频高压跳变VA，所涉及的半导体功率器件Q1或者Q2的两个互连电极的至少一极，往往是SiC场合Q2的Drain极，是GaN场合Q1的Source极，电连接到DBC的下金属层5，从而通过绝缘导热层3，与DBC上金属层4形成较大寄生共模电容Cc，该电容短路到散热器6上，从而与大地GND相连接。即电压源VA通过Cc及大地与功率地GND_pw间的阻抗形成较大共模电流Icom。
而实际上的系统远比图27A复杂，如图27B，散热器6本身就是一个多寄生电感和多对大地寄生电容的组合体。即便是系统通过在大地和功率地之间加Y电容Cy1和共模电感Lcom，其寄生电路之复杂性，也大大降低了抑制效果，或者需要更大尺寸的共模电感和电容才能抑制。本发明提出，在模组内部就近集成Y电容Cy2及集成阻尼Rin，即在复杂寄生电路之前，将共模能量抑制在模组内部，使得整个散热器6都近乎无电压降。这里的Line_G为与大地连接的布线地，Ccer为陶瓷等效电容，Rth为外铜与散热器接触电阻，Lth为散热器分布电感，Cth为散热器分布电容。
为了得到更好的效果，可以在内置Y电容上加阻尼元件，比如电阻或者高阻抗磁珠。
图27C为具体结构的实现方案，即在模组内部设置Y电容，Y电容的一个电极通过跨陶瓷层电连接组件25与上金属层4电连接，Y电容的另一个电极通过下金属层5与第一功率器件的Top面电极电连接，即可实现图29B的等效效果。
如图27D至27G所示，由于DBC的上金属层4要安装到散热器6，所以对其平整度的要求很高。互连Y电容到上金属层4的跨陶瓷层电连接组件25不能超出上金属层4。图27D中，跨陶瓷层电连接组件25为一侧缘电互连件26，其设置在绝缘导热板的侧缘，侧缘电互连件26的一端与上金属层4电连接，侧缘电互连件26的另一端通过下金属层5与Y电容电连接；图27E中，跨陶瓷层电连接组件25为一贯穿式电互连件27，贯穿式电互连件27贯穿绝缘导热层3，贯穿式电互连件27的一端与上金属层4电连接，贯穿式电互连件27的另一端通过下金属层5与共模抑制电容24电连接。图27F和图27G中，由于铜线焊接工艺操作复杂，而Y电容的电流较小，所以图27F所示的方案可以用导电涂层28来将DBC的上金属层4和下金属层5进行互联，比如用银浆涂层。如图27C所示，而由于Y电容高度较大，不仅仅将线路板第一表面挖槽让出空间，还将DBC下金属层5局部减薄，但铜层局部减薄需要额外工艺，可以在图27F所示方案的基础上，进阶使用导电涂层28来实现减薄效果，即图27G所示的Y电容与导电涂层28的互联，可以直接用导电涂层28的粘性实现，也可以通过导电胶粘结。
由于前述实施例都是通过多次焊接完成模组的制作，工艺流程较多，且导致了需要在半导体功率器件Q1、Q2的底部做热阻电连接层12，制作过程时间长，成本高。故提出简化的制作方法，如图28A至28D所示，具体如下：
第一步Sd1：将半导体功率器件Q1、Q2放置在多层线路板的第一表面201上，半导体功率器件Q1、Q2的正面与多层线路板之间有焊接材料，之后将放置好半导体功率器件Q1、Q2的多层线路板2置于一支撑平台29上。其中，焊接材料可以印刷在多层线路板2上，也可以预置在半导体功率器件Q1、Q2的正面上。为了减少焊接温差，多层线路板2下方的支撑平台29也可以是加热板，如图28A所示。
第二步Sd2：将DBC放置在半导体功率器件Q1、Q2的Top面，半导体功率器件Q1、Q2的Top面与DCB之间有焊接材料，焊接材料可以印刷在DBC上，也可以预置在半导体功率器件Q1、Q2的Top面上，如图28B和图28C所示。
第三步Sd3：将一加热平板30压在DBC上后进行加热，由于DBC和半导体功率器件Q1、Q2都是热良导体，热可快速传递至各焊点。为了减少能耗及加热速度，可以用电感应加热的方式给DBC的铜层加热，如图28D所示。
以上所示的实施例中，为了满足安规绝缘要求，多层线路板2中的垂直电连接通路130尽可能靠近模组的边缘。在一些不需要安规绝缘的应用中，比如48V低压电极驱动或者整流逆变应用中，或者散热器6连接功率地而非大地的变换器的应用场合，由于耐压要求比较低，不需要大的安规距离要求，因此模组的厚度可以进一步减小。
如图29A所示，低回路焊盘31设置于多层线路板的第二表面202，高频电容1可以通过低回路焊盘31焊接到线路板2的第二表面202，垂直电连接通路130尽可能靠近低回路焊盘31设置，高频电容1的两个电极经由垂直电连接通路130、多层线路板内部走线层、多层线路板的第一表面201与半导体功率器件形成一个低回路。在低回路中，高频信号的传输路径短，回路所包络的面积小，因此回路中的寄生电感以及其它寄生参数小，从而减小尖峰电压，降低损耗。与之前实施例相同的是，设置于半导体功率器件的背面的电极通过导热电绝缘材料644与绝缘导热板连接，半导体功率器件的背面面积总和超过80％的面积设置为静电位，以降低共模干扰。
在另一实施例中，如图29B所示，将模组通过表贴焊接设置在客户主板8的一个表面，高频电容1与模组相对应的设置在客户主板8的另一个表面上，高频电容邻近模组的低回路焊盘31设置，使得高频电容两极经由客户主板与低回路焊盘电连接的布线尽可能短，从而形成一个低回路。这样的结构可以获得相同的高频效果，同时又降低了模组的内部元件数量，提升了模组的成品率，降低了模组的高度，节约了成本。
参照图29C，在图29B所示的应用基础上，在模组的上表面装配一个散热器6，半导体晶片产生的热量经由绝缘导热板导至散热装置6，而散热装置6通过固定柱32与客户主板8连接装配。增加了模组的散热能力的同时，也增强了模组的稳固度。
本发明力求极致回路减小和极佳导热性能的兼顾，从而实现高频大功率封装模组的制作，且与散热面进行电绝缘且热良导效果。因此，此案DBC的绝缘导热材料的选择尤其的重要，以高热导系数的材料，如氧化铝、氮化铝、氮化硅材料为佳；而且此案的DBC实质是指电绝缘良导体基板，并非限制为DBC本体。此案的线路板实质是指多层电路布线层，并非限制在独立的多层线路板，也可以为在模组工艺中形成的具有相同功能的布线层。此案的半导体功率器件也可以半导体晶片或半导体芯片，都适应本发明所揭示的技术方案。本发明提出了可应对未来需求趋势的高频大功率模组方案，并提出了各种精进方案以发挥本发明的潜质，部分精进方案也适用于其它应用场景，未必限于本发明所揭露。
本说明书中各个实施例采用递进的方式描述，每个实施例重点说明的都是与其他实施例的不同之处，各个实施例之间相同相似部分互相参见即可。
对所公开的实施例的上述说明，使本领域专业技术人员能够实现或使用本发明。对这些实施例的多种修改对本领域的专业技术人员来说将是显而易见的，本文中所定义的一般原理可以在不脱离本发明的精神或范围的情况下，在其它实施例中实现。因此，本发明将不会被限制于本文所示的这些实施例，而是要符合与本文所公开的原理和新颖特点相一致的最宽的范围。

Claims (89)

  1. 一种高频大功率封装模组，其特征在于，包括：至少一个功率变换桥臂、至少一个高频电容、电路层、绝缘导热板和塑封体；
    所述功率变换桥臂包括至少两个串联连接的半导体功率器件；
    所述高频电容与功率变换桥臂并联，形成高频回路；
    所述电路层包括第一表面、内层电连接层、第二表面及垂直电连接通路，所述内层电连接层通过至少一个垂直电连接通路与第一表面电连接；
    所述绝缘导热板包括绝缘导热层，以及分别设置在绝缘导热层上下表面的上金属层和下金属层；
    所述塑封体填充电路层的第二表面与绝缘导热板的上表面之间的间隙区域，所述电路层的第二表面或侧缘上设置有外部电极，所述外部电极与功率变换桥臂电连接；
    所述半导体功率器件的正面与电路层的第一表面电连接，所述半导体功率器件的背面与绝缘导热板的下表面热连接或电热连接；
    所述高频电容与电路层的第一表面或电路层的第二表面或绝缘导热板的下表面电连接，所述高频电容的至少一个电极通过内层电连接层与至少一个半导体功率器件的至少一个电极电连接。
  2. 根据权利要求1所述的高频大功率封装模组，其特征在于，所述半导体功率器件通过一热阻电连接层与电路层的第一表面电连接。
  3. 根据权利要求2所述的高频大功率封装模组，其特征在于，所述热阻电连接层的热阻值Rth_DietoPCB满足以下公式：
    (Tcase+(TdieMAX-Tcase)×Rth_PCBtoCase/(Rth_PCBtoCase+Rth_DietoPCB))≤TpcbMax
    ；
    其中，Tcase为高频大功率封装模组工作时的周围环境温度，TdieMAX为半导体功率器件的最高工作温度，Rth_PCBtoCase为电路层到绝缘导热板上表面的总等效热阻值，TpcbMax为电路层的最高工作温度。
  4. 根据权利要求2所述的高频大功率封装模组，其特征在于，所述热阻电连接层的热 阻值至少为3K/W。
  5. 根据权利要求1所述的高频大功率封装模组，其特征在于，所述绝缘导热板的上表面与一散热器热连接，所述塑封体的上表面与散热器之间具有气隙。
  6. 根据权利要求1所述的高频大功率封装模组，其特征在于，所述高频电容与电路层的第一表面电连接时，所述高频电容的高度Hc满足以下条件：
    H1≤Hc＜H2；
    其中，H1为电路层的第一表面至半导体功率器件的背面的距离，H2为电路层的第一表面至绝缘导热层的下表面的距离；
    所述绝缘导热板延伸至高频电容的上方；位于所述高频电容与绝缘导热层之间的下金属层通过减薄或去除的方式与高频电容隔离。
  7. 根据权利要求1所述的高频大功率封装模组，其特征在于，所述高频电容与电路层的第一表面电连接时，所述高频电容的高度Hc满足以下条件：
    H2≤Hc＜H3；
    其中，H2为电路层的第一表面至绝缘导热层的下表面的距离，H3为电路层的第一表面至绝缘导热层的上表面的距离；
    所述绝缘导热板位于电路层的第二表面上除高频电容以外的器件的上方。
  8. 根据权利要求1所述的高频大功率封装模组，其特征在于，所述高频电容与电路层的第二表面电连接时，所述高频电容的两个电极分别通过垂直电连接通路与内层电连接层及电路层的第一表面电连接。
  9. 根据权利要求1所述的高频大功率封装模组，其特征在于，所述高频电容与绝缘导热板的下表面电连接时，所述高频电容的至少一个电极通过一电连接件与内层电连接层电连接，且高频电容的高度Hc满足以下条件：
    H1≤Hc＜H4；
    其中，H1为电路层的第一表面至半导体功率器件的背面的距离，H4为电路层的第二表面至绝缘导热层的下表面的距离；
    位于所述高频电容下方的电路层通过减薄或去除的方式与高频电容隔离。
  10. 根据权利要求1所述的高频大功率封装模组，其特征在于，所述半导体功率器件的功率电极均位于其正面。
  11. 根据权利要求10所述的高频大功率封装模组，其特征在于，还包括至少一个电连接孔，所述电连接孔用于实现半导体功率器件的正面电极与线路板之间的电连接。
  12. 根据权利要求10所述的高频大功率封装模组，其特征在于，所述半导体功率器件的背面电极依次通过绝缘导热板的下金属层及导电组件电连接至电路层的第一表面。
  13. 根据权利要求10所述的高频大功率封装模组，其特征在于，所述半导体功率器件的背面电极通过设置在其内部的导电通孔电连接至其正面。
  14. 根据权利要求1所述的高频大功率封装模组，其特征在于，所述半导体功率器件的至少一个功率电极为背面功率电极，所述背面功率电极通过绝缘导热板的下金属层及导电组件电连接至电路层的第一表面，所述下金属层为厚铜层。
  15. 根据权利要求1所述的高频大功率封装模组，其特征在于，所述电路层的内部设置有高热容元件，所述高热容元件与内层电连接层热连接或电热连接。
  16. 根据权利要求1所述的高频大功率封装模组，其特征在于，所述电路层中和所述高频电容两端相连的布线在水平方向的投影与半导体功率器件在水平方向的投影部分重合。
  17. 根据权利要求16所述的高频大功率封装模组，其特征在于，多个所述半导体功率器件并联电连接，所述高频大功率封装模组还包括分布式的垂直连接件，每一所述半导体功率器件与对应的垂直连接件邻近设置。
  18. 根据权利要求17所述的高频大功率封装模组，其特征在于，所述分布式的垂直连接件包括第一垂直连接件和第二垂直连接件，所述第一垂直连接件的直径大于所述第二垂直连接件的直径，所述第一垂直连接件邻近所述高频大功率封装模组的侧面设置。
  19. 根据权利要求1所述的高频大功率封装模组，其特征在于，还包括缓冲外引脚，所述缓冲外引脚用于将高频大功率封装模组与客户主板电连接。
  20. 根据权利要求19所述的高频大功率封装模组，其特征在于，所述缓冲外引脚设置在电路层的第二表面上。
  21. 根据权利要求19所述的高频大功率封装模组，其特征在于，所述缓冲外引脚设置在电路层的侧缘。
  22. 根据权利要求21所述的高频大功率封装模组，其特征在于，所述缓冲外引脚的内侧焊接在电路层的侧缘，所述缓冲外引脚的外侧设置有绝缘加固框架。
  23. 根据权利要求19所述的高频大功率封装模组，其特征在于，还包括弹性绝缘固定框架，所述弹性绝缘固定框架用于使高频大功率封装模组与设置在绝缘导热板上表面的散热器紧贴。
  24. 根据权利要求23所述的高频大功率封装模组，其特征在于，所述弹性绝缘固定框架包括弹性件及绝缘加固框架，所述弹性件的一端与散热器连接，所述弹性件的另一端插接在绝缘加固框架中，所述绝缘加固框架通过边缘限位结构对高频大功率封装模组进行限位。
  25. 根据权利要求23所述的高频大功率封装模组，其特征在于，所述弹性绝缘固定框架包括具有弹性材质的绝缘加固框架，所述绝缘加固框架通过边缘限位结构对高频大功率封装模组进行限位，所述绝缘加固框架通过贯穿式固定组件分别与客户主板、散热器连接。
  26. 根据权利要求19所述的高频大功率封装模组，其特征在于，所述电路层的第二表面与客户主板之间形成有安装区域，所述安装区域设置有至少一个电路元件。
  27. 根据权利要求19所述的高频大功率封装模组，其特征在于，所述缓冲外引脚通过重布线结构引出。
  28. 根据权利要求19所述的高频大功率封装模组，其特征在于，还包括第二表面保护件，所述第二表面保护件包括壳体、密封胶以及填充体，所述壳体通过密封胶固定并覆盖在电路层的第二表面上，所述壳体与电路层的第二表面之间填充有填充体，所述填充体可以为硅胶或者塑封料；
    所述壳体上设置有供缓冲外引脚伸出的外引脚通孔。
  29. 根据权利要求28所述的高频大功率封装模组，其特征在于，所述壳体的一端与设置在绝缘导热板上表面的散热器固定连接。
  30. 根据权利要求28所述的高频大功率封装模组，其特征在于，所述高频大功率封装模组在水平方向上具有未被第二表面保护件覆盖的延伸区域，所述延伸区域上设置有供固定用的固定孔。
  31. 根据权利要求28所述的高频大功率封装模组，其特征在于，所述缓冲外引脚通过重布线结构引出。
  32. 根据权利要求28所述的高频大功率封装模组，其特征在于，还包括至少一个铜柱和至少一个焊盘，所述铜柱内埋于所述第二表面保护件内，所述焊盘设置于所述第二表面保护件表面，且与所述铜柱电连接。
  33. 根据权利要求28所述的高频大功率封装模组，其特征在于，所述第二表面保护件包括至少一个复用焊盘，所述复用焊盘包括至少一个大深沉孔、至少一个小过孔和至少一个焊盘，所述大深沉孔由所述第二表面保护件的外表面向所述线路板的第二表面内凹形成，所述焊盘覆盖大深沉孔表面并且延伸至大深沉孔以外和，所述小过孔设置于大深沉孔底部且电连接至少一个焊盘和线路板，所述复用焊盘用于焊接功率引脚。
  34. 根据权利要求19至33任一项所述的高频大功率封装模组，其特征在于，所述缓冲外引脚为直插焊接引脚、直插压接引脚、表面触点压接引脚、表面触点焊接引脚中的一种。
  35. 根据权利要求1所述的高频大功率封装模组，其特征在于，所述半导体功率器件的正面电极下方设置有铜柱，所述铜柱的高度至少为30μm。
  36. 根据权利要求1所述的高频大功率封装模组，其特征在于，所述半导体功率器件具有至少两种不同的厚度，所述半导体功率器件的正面电极下方设置有对应的不同高度的铜柱或金属球。
  37. 根据权利要求1所述的高频大功率封装模组，其特征在于，所述半导体功率器件具有至少两种不同的厚度，至少一个较厚的所述半导体功率器件的正面电极下方设置有铜柱，至少一个较薄的所述半导体功率器件的正面电极下方设置有金属球。
  38. 根据权利要求1所述的高频大功率封装模组，其特征在于，所述半导体功率器件的正面电极为通过封装形成的厚铜电极，所述厚铜电极的高度至少为30μm。
  39. 根据权利要求1所述的高频大功率封装模组，其特征在于，所述半导体功率器件的背面电极上方设置有覆铜层。
  40. 根据权利要求39所述的高频大功率封装模组，其特征在于，所述半导体功率器件具有至少两种不同的厚度，所述半导体功率器件的背面电极上方的覆铜层具有对应的不同厚度。
  41. 根据权利要求1所述的高频大功率封装模组，其特征在于，所述半导体功率器件的背面电极为通过封装形成的覆铜层状电极。
  42. 根据权利要求1所述的高频大功率封装模组，其特征在于，至少一个所述半导体芯片的背面设置一个功率电极和一个门极电极，所述功率电极连接至电路的静电位。
  43. 根据权利要求42所述的高频大功率封装模组，其特征在于，所述半导体功率器件的门极电极通过电连接线键合至所述电路层，所述门极电极的焊点通过点胶处理保护。
  44. 根据权利要求1所述的高频大功率封装模组，其特征在于，所述半导体功率器件为衬底电位可设置的LDMOS器件，所述衬底电位设置为所述高频大功率封装模组的静电位。
  45. 根据权利要求44所述的高频大功率封装模组，其特征在于，所述LDMOS器件的衬底材质为蓝宝石。
  46. 根据权利要求1所述的高频大功率封装模组，其特征在于，至少一个所述半导体功率器件包括一常开式第三代半导体子功率器件及一低压常闭式半导体子功率器件，所述常开式第三代半导体子功率器件与低压常闭式半导体子功率器件级联，所述常开式第三代半导体子功率器件与低压常闭式半导体子功率器件通过叠层封装的形式形成半导体功率器件。
  47. 根据权利要求1所述的高频大功率封装模组，其特征在于，至少一个所述半导体功率器件为一常开式功率器件，所述常开式功率器件配合设置有一低压常闭式半导体功率 器件，所述常开式功率器件与低压常闭式半导体功率器件级联，所述低压常闭式半导体功率器件设置在电路层的第二表面上，所述低压常闭式半导体功率器件的设置位置与常开式功率器件的位置垂直对应。
  48. 根据权利要求1所述的高频大功率封装模组，其特征在于，所述功率变换桥臂并联设置有多个，所述功率变换桥臂的直流端外部电极与交流端外部电极分别设置在高频大功率封装模组的两侧。
  49. 根据权利要求1所述的高频大功率封装模组，其特征在于，所述塑封体的侧缘为台阶形。
  50. 根据权利要求1所述的高频大功率封装模组，其特征在于，还包括一客户子板，所述客户子板用于将外部电极与客户主板电连接，所述客户子板与电路层平行设置，所述客户子板和电路层分别与客户主板垂直设置。
  51. 根据权利要求50所述的高频大功率封装模组，其特征在于，所述功率变换桥臂的直流端外部电极设置在靠近客户主板的一侧，所述功率变换桥臂的交流端外部电极设置在远离客户主板的一侧，所述功率变换桥臂的交流端外部电极通过客户子板与设置在客户主板上的外部交流器件电连接。
  52. 根据权利要求1所述的高频大功率封装模组，其特征在于，每个所述功率变换桥臂中的两个半导体功率器件的背面电极分别为与功率变换桥臂的两个直流端等电位的电极。
  53. 根据权利要求1所述的高频大功率封装模组，其特征在于，还包括导热柱，所述导热柱设置于绝缘导热板的上表面，所述导热柱用于液冷散热。
  54. 根据权利要求53所述的高频大功率封装模组，其特征在于，所述绝缘导热板的上表面的与半导体功率器件垂直对应的区域为第一散热区域，所述导热柱在第一散热区域内的设置数量密度，大于其在第一散热区域外的设置数量密度。
  55. 根据权利要求53所述的高频大功率封装模组，其特征在于，所述导热柱包括金属壳体和超高导热填充料，其中所述超高导热填充料设置于金属壳体内部，所述超高导热填 充料为碳纤维管、石墨烯片或者相变液体。
  56. 一种高频大功率封装模组，其特征在于，包括：至少一个功率变换桥臂、至少一个高频电容、绝缘导热板、电连接装置、塑封体、跨陶瓷层电连接组件和共模抑制电容；
    所述功率变换桥臂包括至少两个串联连接的半导体功率器件；
    所述高频电容与功率变换桥臂并联；
    所述绝缘导热板包括绝缘导热层，以及分别设置在绝缘导热层上下表面的上金属层和下金属层；
    所述半导体功率器件的正面的至少一个电极通过所述电连接装置引出至高频大功率封装模组外部，并与高频电容的至少一个电极电连接；
    所述塑封体填充半导体功率器件的正面与绝缘导热板的上表面之间的间隙区域；
    所述共模抑制电容的一个电极通过跨陶瓷层电连接组件与上金属层电连接，所述共模抑制电容的另一个电极与功率变换桥臂的一个直流端电连接；
    所述半导体功率器件的背面与绝缘导热板的下表面热连接或电热连接。
  57. 根据权利要求56所述的高频大功率封装模组，其特征在于，还包括一散热器；
    所述高频大功率封装模组安装在散热器上，所述绝缘导热板的上表面与散热器热连接，所述散热器的电位为大地；
    所述共模抑制电容用于抑制由于桥臂交流电压跳变而产生的流经散热器至大地的电流。
  58. 根据权利要求56所述的高频大功率封装模组，其特征在于，所述共模抑制电容设置在所述间隙区域内，至少一个所述半导体功率器件为第一功率器件，所述第一功率器件的背面电极与功率变换桥臂的一个直流端等电位，所述共模抑制电容的一个电极通过跨陶瓷层电连接组件与上金属层电连接，所述共模抑制电容的另一个电极通过下金属层与第一功率器件的背面电极电连接。
  59. 根据权利要求58所述的高频大功率封装模组，其特征在于，所述跨陶瓷层电连接组件包括一侧缘电互连件，所述侧缘电互连件设置在绝缘导热板的侧缘，所述侧缘电互连 件的一端与上金属层电连接，所述侧缘电互连件的另一端通过下金属层与共模抑制电容电连接。
  60. 根据权利要求58所述的高频大功率封装模组，其特征在于，所述跨陶瓷层电连接组件包括一贯穿式电互连件，所述贯穿式电互连件贯穿绝缘导热层，所述贯穿式电互连件的一端与上金属层电连接，所述贯穿式电互连件的另一端通过下金属层与共模抑制电容电连接。
  61. 根据权利要求58所述的高频大功率封装模组，其特征在于，所述跨陶瓷层电连接组件包括一导电涂层，所述导电涂层设置在绝缘导热层侧缘及其上下表面的临近区域，所述导电涂层的一端与上金属层电连接，所述导电涂层的另一端与共模抑制电容电连接。
  62. 根据权利要求56至61任一项所述的高频大功率封装模组，其特征在于，所述电连接装置为电路层，所述电路层包括第一表面、内层电连接层、第二表面及垂直电连接通路，所述内层电连接层通过至少一个垂直电连接通路与第一表面电连接；
    所述塑封体填充电路层的第二表面与绝缘导热板的上表面之间的间隙区域，所述电路层的第二表面或侧缘上设置有外部电极，所述外部电极与功率变换桥臂电连接；
    所述半导体功率器件的正面与电路层的第一表面电连接，所述半导体功率器件的背面与绝缘导热板的下表面热连接或电热连接；
    所述高频电容与电路层的第一表面或电路层的第二表面或绝缘导热板的下表面电连接，所述高频电容的至少一个电极通过内层电连接层与至少一个半导体功率器件的至少一个电极电连接。
  63. 一种高频大功率封装模组，其特征在于，包括：至少一个功率变换桥臂、至少一个高频电容、绝缘导热板、电连接装置、塑封体和外部电极；
    所述功率变换桥臂包括至少两个串联连接的半导体功率器件；
    所述高频电容与功率变换桥臂并联；
    所述绝缘导热板包括绝缘导热层，以及分别设置在绝缘导热层上下表面的上金属层和下金属层；
    所述半导体功率器件的正面的至少一个电极通过所述电连接装置引出至高频大功率封装模组外部，并与高频电容的至少一个电极电连接；
    所述塑封体填充半导体功率器件的正面与绝缘导热板的上表面之间的间隙区域；
    所述外部电极包括至少一对直流端外部电极、至少一对交流端外部电极及至少一对信号端外部电极；
    所述半导体功率器件的背面与绝缘导热板的下表面热连接或电热连接；
    所述功率变换桥臂并联设置有多个，所述功率变换桥臂的直流端外部电极与交流端外部电极分别设置在高频大功率封装模组的两侧；
    所述信号端外部电极设置在所述直流端外部电极与交流端外部电极之间。
  64. 根据权利要求63所述的高频大功率封装模组，其特征在于，所述信号端外部电极与直流端外部电极之间的最小间距大于4mm，所述信号端外部电极与交流端外部电极之间的最小间距大于4mm。
  65. 根据权利要求63所述的高频大功率封装模组，其特征在于，所述信号端外部电极为预制成型的多引脚排插。
  66. 根据权利要求65所述的高频大功率封装模组，其特征在于，所述多引脚排插为柔性PCB扁平线。
  67. 根据权利要求63至66任一项所述的高频大功率封装模组，其特征在于，所述电连接装置为电路层，所述电路层包括第一表面、内层电连接层、第二表面及垂直电连接通路，所述内层电连接层通过至少一个垂直电连接通路与第一表面电连接；
    所述塑封体填充电路层的第二表面与绝缘导热板的上表面之间的间隙区域，所述电路层的第二表面或侧缘上设置有外部电极，所述外部电极与功率变换桥臂电连接；
    所述半导体功率器件的正面与电路层的第一表面电连接，所述半导体功率器件的背面与绝缘导热板的下表面热连接或电热连接；
    所述高频电容与电路层的第一表面或电路层的第二表面或绝缘导热板的下表面电连接，所述高频电容的至少一个电极通过内层电连接层与至少一个半导体功率器件的至少一 个电极电连接。
  68. 一种如权利要求1至55任一项所述的高频大功率封装模组的制作方法，其特征在于，包括：
    提供一所述电路层及所述绝缘导热板；
    将所述高频电容设置在电路层或绝缘导热板上；
    在所述电路层上焊接所述半导体功率器件；
    在所述半导体功率器件的上方设置所述绝缘导热板；
    塑封所述间隙区域，形成所述塑封体，所述绝缘导热板的上表面外露。
  69. 一种如权利要求2至4任一项所述的高频大功率封装模组的制作方法，其特征在于，包括：
    提供一所述电路层及所述绝缘导热板；
    将所述高频电容设置在电路层或绝缘导热板上；
    在所述电路层上焊接所述半导体功率器件；
    预塑封所述半导体功率器件与电路层的第一表面之间的区域，形成所述热阻电连接层；
    在所述半导体功率器件的上方设置所述绝缘导热板；
    塑封所述间隙区域，形成所述塑封体，所述绝缘导热板的上表面外露。
  70. 一种如权利要求1至55任一项所述的高频大功率封装模组的制作方法，其特征在于，包括：
    提供一所述电路层及所述绝缘导热板；
    将所述高频电容设置在电路层上；
    在所述电路层上焊接所述半导体功率器件；
    塑封所述电路层和半导体功率器件，形成第一塑封体，所述半导体功率器件的上表面外露；
    在所述半导体功率器件的上表面设置所述绝缘导热板；
    塑封所述绝缘导热板，形成第二塑封体，所述绝缘导热板的上表面外露。
  71. 一种如权利要求19至34任一项所述的高频大功率封装模组的制作方法，其特征在于，包括：
    提供一所述绝缘导热板及预设有线路板通孔的所述电路层；
    将与所述缓冲外引脚固定电性设置在所述线路板通孔内，使外部电极分别与电路层的第一表面和/或内层电连接层和/或第二表面电连接，且使所述缓冲外引脚向电路层的第二表面外延伸；
    将所述高频电容设置在电路层或绝缘导热板上；
    在所述电路层上焊接所述半导体功率器件；
    在所述半导体功率器件的上方设置所述绝缘导热板；
    塑封所述间隙区域，形成所述塑封体，所述绝缘导热板的上表面外露。
  72. 一种如权利要求1至52任一项所述的高频大功率封装模组的制作方法，其特征在于，包括：
    提供一所述电路层及所述绝缘导热板；
    提供一支撑平台；
    在所述电路层的第一表面上设置焊料和所述半导体功率器件；
    将所述电路层的第二表面放置于支撑平台上；
    在所述半导体功率器件的上方设置焊料和所述绝缘导热板；
    将一加热平板放置于所述绝缘导热板的上表面进行加热完成焊接。
  73. 一种高频大功率封装模组，其特征在于，包括至少三个半导体功率器件、一个驱动器；
    所述半导体功率器件设置于同一平面上；
    所述驱动器为每个所述半导体功率器件提供驱动信号，且在所述平面的投影与每个所述半导体功率器件在所述平面上的投影都部分重合。
  74. 根据权利要求73所述的高频大功率封装模组，其特征在于，还包括一个电路层， 所述电路层包括相对的第一表面和第二表面；所述半导体功率器件设置于第一表面，所述驱动器设置于第二表面。
  75. 根据权利要求73所述的高频大功率封装模组，其特征在于，每个所述半导体功率器件到所述驱动器的对应的驱动信号端的走线距离相同。
  76. 根据权利要求74所述的高频大功率封装模组，其特征在于，还包括至少一个高频电容、一个绝缘导热板和塑封体；
    所述绝缘导热板包括绝缘导热层，以及分别设置在绝缘导热层上下表面的上金属层和下金属层；
    所述塑封体填充电路层的第二表面与绝缘导热板的上表面之间的间隙区域，所述电路层的第二表面或侧缘上设置有外部电极，所述外部电极与功率变换桥臂电连接；
    所述半导体功率器件的正面与电路层的第一表面电连接，所述半导体功率器件的背面与绝缘导热板的下表面热连接或电热连接；
    所述高频电容与功率变换桥臂并联，形成高频回路，所述高频电容与电路层的第一表面或电路层的第二表面或绝缘导热板的下表面电连接，所述高频电容的至少一个电极通过内层电连接层与至少一个半导体功率器件的至少一个电极电连接；
    每个所述半导体功率器件到所述驱动器的对应的驱动信号端的走线距离相同。
  77. 一种混合基板，其特征在于，包括高导热区域和低导热区域；所述混合基板具有相对的上表面和下表面；
    所述高导热区域和低导热区域沿水平方向排布；
    所述高导热区域用于设置发热半导体器件，所述发热半导体器件具体设置于所述下表面；
    所述高导热区域的导热系数大于低导热区域的导热系数；
    所述混合基板的上表面用于装配散热装置。
  78. 根据权利要求77所述的混合基板，其特征在于，所述高导热区域的导热系数大于低导热区域的导热系数的两倍。
  79. 根据权利要求77所述的混合基板，其特征在于，所述高导热区域为高导热颗粒阵列，或者，所述高导热区域为高导热颗粒阵列和低导热材料的混合物。
  80. 根据权利要求77所述的混合基板，其特征在于，还包括分别设置在上表面和下表面的上金属层和下金属层，所述高导热区域和所述低导热区域的材质均为绝缘材质。
  81. 一种高频大功率封装模组，其特征在于，包括如权利要求80所述的混合基板、至少一个功率变换桥臂、至少一个高频电容、电路层和塑封体；
    所述功率变换桥臂包括至少两个串联连接的半导体功率器件；
    所述高频电容与功率变换桥臂并联，形成高频回路；
    所述电路层包括第一表面、内层电连接层、第二表面及垂直电连接通路，所述内层电连接层通过至少一个垂直电连接通路与第一表面电连接；
    所述塑封体填充电路层的第二表面与混合基板的上表面之间的间隙区域，所述电路层的第二表面或侧缘上设置有外部电极，所述外部电极与功率变换桥臂电连接；
    所述半导体功率器件的正面与电路层的第一表面电连接，所述半导体功率器件的背面与所述高导热区域对应的下金属层热连接或电热连接；
    所述高频电容与电路层的第一表面或电路层的第二表面或混合基板的下表面电连接，所述高频电容的至少一个电极通过内层电连接层与至少一个半导体功率器件的至少一个电极电连接。
  82. 一种高频大功率封装模组，其特征在于，包括如权利要求80所述的混合基板、至少一个功率变换桥臂和导热柱；
    所述至少一个功率变换桥臂包括至少两个串联连接的半导体功率器件，且所述半导体功率器件设置于所述高导热区域对应的下金属层；
    所述导热柱设置于所述混合基板的上金属层；
    至少一部分所述导热柱设置于高导热区域对应的上金属层。
  83. 根据权利要求82所述的高频大功率封装模组，其特征在于，至少另一部分所述导热柱设置于低导热区域对应的上金属层，所述导热柱在高导热区域内的设置数量密度，大 于其在低导热区域内的设置数量密度。
  84. 根据权利要求82所述的高频大功率封装模组，其特征在于，还包括至少一个高频电容、电路层和塑封体；
    所述高频电容与功率变换桥臂并联，形成高频回路；
    所述电路层包括第一表面、内层电连接层、第二表面及垂直电连接通路，所述内层电连接层通过至少一个垂直电连接通路与第一表面电连接；
    所述塑封体填充电路层的第二表面与混合基板的上表面之间的间隙区域，所述电路层的第二表面或侧缘上设置有外部电极，所述外部电极与功率变换桥臂电连接；
    所述半导体功率器件的正面与电路层的第一表面电连接，所述半导体功率器件的背面与混合基板的下表面热连接或电热连接；
    所述高频电容与电路层的第一表面或电路层的第二表面或混合基板的下表面电连接，所述高频电容的至少一个电极通过内层电连接层与至少一个半导体功率器件的至少一个电极电连接。
  85. 一种高频大功率封装模组，其特征在于，包括：至少一个功率变换桥臂、多层线路板、绝缘导热板和塑封体；
    所述功率变换桥臂包括至少两个串联连接的半导体功率器件；
    所述多层线路板包括相对的第一表面和第二表面、内层电连接层、至少两个低回路焊盘及垂直电连接通路，所述内层电连接层通过至少一个垂直电连接通路与第一表面电连接；
    所述绝缘导热板包括绝缘导热层以及相对的上表面和下表面；
    所述塑封体填充多层线路板的第二表面与绝缘导热板的上表面之间的间隙区域，所述多层线路板的第二表面或侧缘上设置有外部电极，所述外部电极与功率变换桥臂电连接；
    所述半导体功率器件的正面与多层线路板的第一表面电连接，所述半导体功率器件的背面与绝缘导热板的下表面热连接或电热连接；
    所述多层线路板，将所述功率变换桥臂的两个直流电极，通过第一表面及内层电连接 层，耦合到对应的两个低回路焊盘，所述低回路焊盘用于电性连接一高频电容形成低回路。
  86. 根据权利要求85所述的高频大功率封装模组，其特征在于，所述至少两个低回路焊盘设置于多层线路板的第二表面，所述第二表面还设置有功率引脚和信号引脚。
  87. 根据权利要求86所述的高频大功率封装模组，其特征在于，所述线路板的第二表面电性连接一个客户主板的一个表面，所述客户主板的另一个表面设置一个高频电容，所述高频电容通过客户主板与所述低回路焊盘电性连接。
  88. 根据权利要求87所述的高频大功率封装模组，其特征在于，所述绝缘导热板的上表面与一个散热装置热连接，所述散热装置通过至少一固定柱与客户主板装配。
  89. 根据权利要求85所述的高频大功率封装模组，其特征在于，所述半导体功率器件的背面的至少80％面积的电位为所述高频大功率封装模组的静电位。
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