WO2023178897A1 - 碳化硅器件终端结构及其制造方法 - Google Patents

碳化硅器件终端结构及其制造方法 Download PDF

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WO2023178897A1
WO2023178897A1 PCT/CN2022/107347 CN2022107347W WO2023178897A1 WO 2023178897 A1 WO2023178897 A1 WO 2023178897A1 CN 2022107347 W CN2022107347 W CN 2022107347W WO 2023178897 A1 WO2023178897 A1 WO 2023178897A1
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trench
silicon carbide
layer
hard mask
type silicon
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PCT/CN2022/107347
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English (en)
French (fr)
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范让萱
缪进征
王鹏飞
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苏州东微半导体股份有限公司
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide

Definitions

  • the present application belongs to the technical field of silicon carbide devices, and relates, for example, to a silicon carbide device terminal structure and a manufacturing method thereof.
  • Silicon carbide devices in related technologies usually use structures such as field-limited rings and junction termination extension (JTE) as the terminal structures of the device.
  • JTE junction termination extension
  • Using a field-limited ring structure as the terminal structure will make the terminal area of the silicon carbide device larger and cannot effectively reduce the chip size of the silicon carbide device; using a junction terminal extension structure as the terminal structure of the silicon carbide device has a complicated manufacturing process, especially It is difficult to control the doping dose in the junction terminal extension region and the manufacturing cost is high.
  • the present application provides a silicon carbide device terminal structure and a manufacturing method thereof, which can improve the voltage resistance and stability of the silicon carbide device without increasing the chip area of the silicon carbide device.
  • first trench located in the n-type silicon carbide layer and at least one second trench located on one side of the first trench;
  • the side walls of the first groove and the at least one second groove are divided into at least two sections in the vertical direction and are in the form of stepped steps, and the lateral sides of the first groove and the at least one second groove are The width gradually decreases from top to bottom in the vertical direction;
  • first p-type region located in the n-type silicon carbide layer close to the sidewalls and bottom of the first trench and a second p-type region close to the sidewalls and bottom of the at least one second trench;
  • An insulating layer covering the surface of the n-type silicon carbide layer and filling the first trench and the at least one second trench;
  • a metal layer located on the insulating layer and covering part of the first trench.
  • a method for manufacturing a silicon carbide device terminal structure of this application includes:
  • Step 1 Form a hard mask layer on the provided n-type silicon carbide layer, deposit photoresist and define the positions of the first trench and the second trench through a photolithography process, and etch the hard mask layer. Etching exposes the n-type silicon carbide layer;
  • Step 2 Remove the photoresist, use the remaining hard mask layer as a mask to etch the n-type silicon carbide layer, and form a first shallow trench in the n-type silicon carbide layer. second shallow trench;
  • Step 3 Isotropically etch the hard mask layer, reduce the thickness and width of the remaining hard mask layer, and use the remaining hard mask layer as a mask to cover the first shallow trench and
  • the n-type silicon carbide layer is etched in the second shallow trench, respectively, to form a first trench and a second trench with two-section sidewalls and stepped steps;
  • Step 4 Isotropically etch the hard mask layer, reduce the thickness and width of the remaining hard mask layer, perform p-type ion implantation, and form a layer located in the n-type silicon carbide layer. a first p-type region on the sidewalls and bottom of the trench, and a second p-type region located on the sidewalls and bottom of the second trench;
  • Step 5 Remove the hard mask layer, deposit an insulating layer, deposit a metal layer and etch the metal layer. After etching, the remaining metal layer covers part of the first layer. trench.
  • Figure 1 is a schematic cross-sectional structural diagram of an embodiment of the terminal structure of a silicon carbide device provided by this application;
  • FIGS. 2 to 7 are schematic cross-sectional structural diagrams of main process nodes of an embodiment of the method for manufacturing a silicon carbide device terminal structure of the present application.
  • Figure 1 is a schematic cross-sectional structural diagram of an embodiment of a silicon carbide device terminal structure provided by the present application.
  • the silicon carbide device terminal structure of the present application includes an n-type silicon carbide layer 20 located on the n-type silicon carbide layer.
  • three second trenches 62 are shown as an example.
  • the side walls of the first trench 61 and the second trench 62 are divided into at least two sections in the vertical direction and are in the form of stepped steps, and the lateral widths of the first trench 61 and the second trench 62 are both from It gradually becomes smaller from top to bottom.
  • the side walls of the first trench 61 and the second trench 62 are exemplarily divided into two sections, that is, they have only one step. It should be noted that the lateral width of the first groove 61 and the second groove 62 gradually decreases from top to bottom in the vertical direction, which can be understood as the different segments of the first groove 61 and the second groove 62 .
  • the grooves correspond to different lateral widths, that is, the grooves in the upper section correspond to larger lateral widths, the grooves in the lower section correspond to smaller lateral widths, and any one of the first trench 61 and the second trench 62 is segmented.
  • the corresponding lateral width of the groove is the same from top to bottom.
  • the first p-type region 21 is located in the n-type silicon carbide layer 20 close to the sidewall and bottom of the first trench 61, and the second p-type region 21 is located in the n-type silicon carbide layer 20 close to the sidewall and bottom of the second trench 62.
  • Type area 22 the opening width A1 of the first trench 61 is greater than the opening width A2 of the second trench 62, and the first p-type body region 21 serves as the main junction region. It should be noted that the opening width A1 of the first trench 61 is greater than the opening width A2 of the second trench 62, which can be understood to mean that the opening width A1 of the first trench 61 in the corresponding segment is greater than the opening width of the second trench 62.
  • the opening width of the upper section of the first trench 61 is greater than the opening width of the upper section of the second trench 62
  • the opening width of the lower section of the first trench 61 is greater than the opening width of the lower section of the second trench 62.
  • the insulating layer 23 covers the surface of the n-type silicon carbide layer 20 and fills the first trench 61 and the second trench 62 .
  • the metal layer 24 is located on the insulating layer 23 and covers part of the first trench 61 .
  • This application uses a composite structure of multiple trenches and field limiting rings as the terminal structure of the silicon carbide device.
  • the sidewalls of the first trench and the second trench both adopt a stepped structure, and the first p-type region is close to the first The side walls and bottom of the trench, and the second p-type region is close to the side walls and bottom of the second trench, which can effectively increase the doping area of the first p-type region and the second p-type region, and increase the doping area of the first p-type region and the second p-type region.
  • the effect of the p-type region can reduce the area of the terminal structure under the same withstand voltage conditions, making the silicon carbide device have a small chip size, and improving the voltage withstand capability and stability of the silicon carbide device.
  • FIGS. 2 to 7 are schematic cross-sectional structural diagrams of main process nodes of an embodiment of the method for manufacturing a silicon carbide device terminal structure of the present application.
  • a method for manufacturing a silicon carbide device terminal structure of the present application includes:
  • Step 1 As shown in Figure 2, form a hard mask layer 31 on the provided n-type silicon carbide layer 20, deposit a layer of photoresist 32 and define the first trench and the second trench through a photolithography process. position, and then etching the hard mask layer 31 to expose the n-type silicon carbide layer 20.
  • the opening width of the subsequently formed first trench and the opening width of the second trench can be controlled. Opening width.
  • Step 2 As shown in Figure 3, remove the photoresist 32, use the remaining hard mask layer 31 as a mask to etch the n-type silicon carbide layer 20, and form a first shallow trench in the n-type silicon carbide layer 20.
  • the depth of the first shallow trench and the second shallow trench is not limited in the embodiment of the present application. It is only necessary that the bottoms of the first shallow trench and the second shallow trench end at n-type carbonization. Just within the silicon layer 20 .
  • Step 3 As shown in Figure 4, perform isotropic etching on the hard mask layer 31 to reduce the thickness and width of the remaining hard mask layer 31, and then, as shown in Figure 5, use the remaining hard mask layer 31 to The n-type silicon carbide layer 20 is etched as a mask to form a first trench 61 and a second trench 62 with two-stage sidewalls and stepped steps. Since the isotropic etching process is used to etch the hard mask layer 31, there is no need to add a photolithography process, and the etching process of the hard mask layer can be streamlined and the manufacturing cost can be reduced.
  • the number of the first groove 61 is one, and the number of the second groove 62 is at least one.
  • the opening width of the first groove 61 is greater than the opening width of the second groove 62 .
  • step three can be repeated and the number of steps on the sidewalls of the first trench 61 and the second trench 62 formed can be controlled by controlling the number of step three.
  • the side walls of the first trench 61 and the second trench 62 are divided into two sections, that is, there is only one step.
  • the first trench 61 can be and the side wall of the second groove 62 are in the shape of at least two steps.
  • Step 4 Etch the hard mask layer 31 isotropically as shown in Figure 6, further reduce the thickness and width of the remaining hard mask layer 31, and then perform p-type ion implantation to form a layer located in the n-type silicon carbide layer 20.
  • the first p-type region 21 is located on the side wall and bottom of the first trench 62
  • the second p-type region 22 is located on the side wall and bottom of the second trench 62. Since the isotropic etching process is used to etch the hard mask layer 31, there is no need to add a photolithography process, and the etching process of the hard mask layer can be streamlined and the manufacturing cost can be reduced.
  • Step 5 As shown in Figure 7, remove the remaining hard mask layer, then deposit an insulating layer 23, and then deposit a metal layer and etch the metal layer.
  • the metal layer 24 covers part of the first trench 61 .
  • the insulating layer 23 is located on the n-type silicon carbide layer 20 and fills the first trench 61 and the second trench 62 .
  • the first trench 61 and the second trench 62 with stepped side walls can be formed by only one photolithography process.
  • the manufacturing process is simple and easy to control.

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Abstract

本申请实施例提供的一种碳化硅器件终端结构，包括：n型碳化硅层；位于所述n型碳化硅层内的一个第一沟槽以及位于所述第一沟槽一侧的至少一个第二沟槽；所述第一沟槽和所述第二沟槽的侧壁在垂直方向上均至少分成两段且呈阶梯状台阶，所述第一沟槽和所述第二沟槽的横向宽度在垂直方向上均自上而下逐步变小；位于所述n型碳化硅层内的靠近所述第一沟槽侧壁及底部的第一p型区和靠近所述第二沟槽侧壁及底部的第二p型区；覆盖所述n型碳化硅层表面并填充所述第一沟槽和所述第二沟槽的绝缘层；位于所述绝缘层上且覆盖部分所述第一沟槽的金属层。

Description

碳化硅器件终端结构及其制造方法
本申请要求在2022年3月21日提交中国专利局、申请号为202210281170.6的中国专利申请的优先权，该申请的全部内容通过引用结合在本申请中。
技术领域
本申请属于碳化硅器件技术领域，例如涉及一种碳化硅器件终端结构及其制造方法。
背景技术
相关技术的碳化硅器件通常以场限环和结终端扩展(Junction Termination Extension，JTE)等结构来作为器件的终端结构。采用场限环结构作为终端结构会使得碳化硅器件的终端面积较大，不能有效降低碳化硅器件的芯片尺寸；采用结终端扩展结构来作为碳化硅器件的终端结构，其制造工艺复杂，特别是对结终端扩展区域掺杂剂量的控制难度大，制造成本高。
发明内容
本申请提供一种碳化硅器件终端结构及其制造方法，在不提高碳化硅器件芯片面积的基础上，提高碳化硅器件的耐压能力和稳定性。
本申请实施例提供的一种碳化硅器件终端结构，包括：
n型碳化硅层；
位于所述n型碳化硅层内的一个第一沟槽以及位于所述第一沟槽一侧的至少一个第二沟槽；
所述第一沟槽和所述至少一个第二沟槽的侧壁在垂直方向上均至少分成两段且呈阶梯状台阶，所述第一沟槽和所述至少一个第二沟槽的横向宽度在垂直方向上均自上而下逐步变小；
位于所述n型碳化硅层内的靠近所述第一沟槽侧壁及底部的第一p型区和靠 近所述至少一个第二沟槽侧壁及底部的第二p型区；
覆盖所述n型碳化硅层表面并填充所述第一沟槽和所述至少一个第二沟槽的绝缘层；
位于所述绝缘层上且覆盖部分所述第一沟槽的金属层。
本申请的一种碳化硅器件终端结构的制造方法，包括：
步骤一：在提供的n型碳化硅层上形成硬掩膜层，淀积光刻胶并通过光刻工艺定义第一沟槽和第二沟槽的位置，对所述硬掩膜层进行刻蚀将所述n型碳化硅层暴露出来；
步骤二：去除所述光刻胶，以剩余的所述硬掩膜层为掩膜对所述n型碳化硅层进行刻蚀，在所述n型碳化硅层内形成第一浅沟槽和第二浅沟槽；
步骤三：各向同性刻蚀所述硬掩膜层，减小剩余的所述硬掩膜层的厚度和宽度，以剩余的所述硬掩膜为掩膜在所述第一浅沟槽和所述第二浅沟槽内分别对所述n型碳化硅层进行刻蚀，形成侧壁为两段且呈阶梯状台阶的第一沟槽和第二沟槽；
步骤四：各向同性刻蚀所述硬掩膜层，减小剩余的所述硬掩膜层的厚度和宽度，进行p型离子注入，在所述n型碳化硅层内形成位于所述第一沟槽侧壁和底部的第一p型区、以及位于所述第二沟槽侧壁和底部的第二p型区；
步骤五：去除所述硬掩膜层，淀积形成一层绝缘层，淀积一层金属层并对所述金属层进行刻蚀，刻蚀后剩余的所述金属层覆盖部分所述第一沟槽。
附图说明
图1是本申请提供的碳化硅器件终端结构的一个实施例的剖面结构示意图；
图2至图7是本申请的碳化硅器件终端结构的制造方法的一个实施例的主要工艺节点的剖面结构示意图。
具体实施方式
以下将结合本申请实施例中的附图，通过具体方式，完整地描述本申请的技术方案。
图1是本申请提供的一种碳化硅器件终端结构的一个实施例的剖面结构示意图，如图1所示，本申请的碳化硅器件终端结构包括n型碳化硅层20，位于n型碳化硅层20内的一个第一沟槽61以及位于第一沟槽61一侧的至少一个第二沟槽62，本申请实施例中示例性的示出了3个第二沟槽62。
第一沟槽61和第二沟槽62的侧壁在垂直方向上均至少分成两段且呈阶梯状台阶，且第一沟槽61和第二沟槽62的横向宽度在垂直方向上均自上而下逐步变小。在本申请实施列中，第一沟槽61和第二沟槽62的侧壁均示例性的分为两段，即仅具有一个台阶。需要说明的是，第一沟槽61和第二沟槽62的横向宽度在垂直方向上均自上而下逐步变小可以理解为第一沟槽61和第二沟槽62中不同分段的沟槽对应不同的横向宽度，即上段的沟槽对应较大的横向宽度，下段的沟槽对应较小的横向宽度，且第一沟槽61和第二沟槽62中任意一个分段的沟槽对应的横向宽度，从上到下相同。
位于n型碳化硅层20内的靠近第一沟槽61侧壁及底部的第一p型区21，位于n型碳化硅层20内的靠近第二沟槽62侧壁及底部的第二p型区22。可选的，第一沟槽61的开口宽度A1大于第二沟槽62的开口宽度A2，第一p型体区21作为主结区。需要说明的是，第一沟槽61的开口宽度A1大于第二沟槽62的开口宽度A2可以理解为对应分段中的第一沟槽61的开口宽度A1大于第二沟槽62的开口宽度A2，即第一沟槽61上段的开口宽度大于第二沟槽62上段的开口宽度，第一沟槽61下段的开口宽度大于第二沟槽62下段的开口宽度。
覆盖n型碳化硅层20表面并填充第一沟槽61和第二沟槽62的绝缘层23，位于绝缘层23上且覆盖部分第一沟槽61的金属层24。
本申请采用多重沟槽和场限环的复合结构来作为碳化硅器件的终端结构，第一沟槽和第二沟槽的侧壁均采用阶梯状台阶结构，同时第一p型区靠近第一沟槽侧壁及底部，第二p型区靠近第二沟槽侧壁及底部，可以有效增加第一p 型区和第二p型区的掺杂面积，增加第一p型区和第二p型区的效果，从而在相同的耐压条件下可以减小终端结构的面积，使得碳化硅器件具有小的芯片尺寸，并提高碳化硅器件的耐压能力和稳定性。
图2至图7是本申请的碳化硅器件终端结构的制造方法的一个实施例的主要工艺节点的剖面结构示意图。如图2至图7所示，本申请的一种碳化硅器件终端结构的制造方法，包括：
步骤一：如图2所示，在提供的n型碳化硅层20上形成硬掩膜层31，淀积一层光刻胶32并通过光刻工艺定义第一沟槽和第二沟槽的位置，然后对硬掩膜层31进行刻蚀将n型碳化硅层20暴露出来。通过控制第一沟槽位置处的光刻胶图形宽度a和第二沟槽位置处的光刻胶图形宽度b的尺寸，可以控制后续形成的第一沟槽的开口宽度和第二沟槽的开口宽度。
步骤二：如图3所示，去除光刻胶32，以剩余的硬掩膜层31为掩膜对n型碳化硅层20进行刻蚀，在n型碳化硅层20内形成第一浅沟槽和第二浅沟槽，本申请实施例对第一浅沟槽和第二浅沟槽的深度不进行限定，只需第一浅沟槽和第二浅沟槽的底部截止于n型碳化硅层20内即可。
步骤三：如图4所示，对硬掩膜层31进行各向同性刻蚀，减小剩余的硬掩膜层31的厚度和宽度，然后如图5所示，以剩余的硬掩膜31为掩膜对n型碳化硅层20进行刻蚀，形成侧壁为两段且呈阶梯状台阶的第一沟槽61和第二沟槽62。由于采用各向同性刻蚀工艺刻蚀硬掩膜层31，无需增加光刻工艺，可以精简硬掩膜层的刻蚀工艺，降低制造成本。
本申请中，第一沟槽61的数量为一个，第二沟槽62的数量为至少一个，可选的，第一沟槽61的开口宽度大于第二沟槽62的开口宽度。
本申请的碳化硅器件终端结构的制造方法，步骤三完成后，可以重复进行步骤三并通过控制步骤三的次数来控制形成的第一沟槽61和第二沟槽62的侧壁的台阶数量，本申请实施例中，第一个沟槽61和第二沟槽62的侧壁均分为两段，即仅具有一个台阶，通过控制步骤三的重复次数，可以使得第一个沟槽 61和第二沟槽62的侧壁成至少两个台阶状。
步骤四：如图6各向同性刻蚀硬掩膜层31，进一步减小剩余的硬掩膜层31的厚度和宽度，然后进行p型离子注入，在n型碳化硅层20内形成位于所述第一沟槽侧壁和底部的第一p型区21、以及位于第二沟槽62侧壁和底部的第二p型区22。由于采用各向同性刻蚀工艺刻蚀硬掩膜层31，无需增加光刻工艺，可以精简硬掩膜层的刻蚀工艺，降低制造成本。
步骤五：如图7所示，去除剩余的硬掩膜层，然后淀积形成一层绝缘层23，之后淀积一层金属层并对所述金属层进行刻蚀，刻蚀后剩余的所述金属层24覆盖部分第一沟槽61。可选的，绝缘层23位于n型碳化硅层20上并填充第一沟槽61和第二沟槽62。
本申请的碳化硅器件终端结构的制造方法，侧壁呈阶梯状台阶的第一沟槽61和第二沟槽62，仅需要进行一次光刻工艺即可形成，制造工艺简单，容易控制。

Claims (7)

  1. 一种碳化硅器件终端结构，包括：
    n型碳化硅层；
    位于所述n型碳化硅层内的一个第一沟槽以及位于所述第一沟槽一侧的至少一个第二沟槽；
    所述第一沟槽和所述至少一个第二沟槽的侧壁在垂直方向上均至少分成两段且呈阶梯状台阶，所述第一沟槽和所述至少一个第二沟槽的横向宽度在垂直方向上均自上而下逐步变小；
    位于所述n型碳化硅层内的靠近所述第一沟槽侧壁及底部的第一p型区和靠近所述至少一个第二沟槽侧壁及底部的第二p型区；
    覆盖所述n型碳化硅层表面并填充所述第一沟槽和所述至少一个第二沟槽的绝缘层；
    位于所述绝缘层上且覆盖部分所述第一沟槽的金属层。
  2. 如权利要求1所述的碳化硅器件终端结构，其中，所述第一沟槽的开口宽度大于所述第二沟槽的开口宽度。
  3. 一种碳化硅器件终端结构的制造方法，包括：
    步骤一：在提供的n型碳化硅层上形成硬掩膜层，淀积光刻胶并通过光刻工艺定义第一沟槽和第二沟槽的位置，对所述硬掩膜层进行刻蚀将所述n型碳化硅层暴露出来；
    步骤二：去除所述光刻胶，以剩余的所述硬掩膜层为掩膜对所述n型碳化硅层进行刻蚀，在所述n型碳化硅层内形成第一浅沟槽和第二浅沟槽；
    步骤三：各向同性刻蚀所述硬掩膜层，减小剩余的所述硬掩膜层的厚度和宽度，以剩余的所述硬掩膜为掩膜在所述第一浅沟槽和所述第二浅沟槽内分别对所述n型碳化硅层进行刻蚀，形成侧壁为两段且呈阶梯状台阶的第一沟槽和第二沟槽；
    步骤四：各向同性刻蚀所述硬掩膜层，减小剩余的所述硬掩膜层的厚度和宽度，进行p型离子注入，在所述n型碳化硅层内形成位于所述第一沟槽侧壁 和底部的第一p型区、以及位于所述第二沟槽侧壁和底部的第二p型区；
    步骤五：去除所述硬掩膜层，淀积形成一层绝缘层，淀积一层金属层并对所述金属层进行刻蚀，刻蚀后剩余的所述金属层覆盖部分所述第一沟槽。
  4. 如权利要求3所述的碳化硅器件终端结构的制造方法，其中，所述第一沟槽的数量为一个，所述第二沟槽的数量为至少一个。
  5. 如权利要求3所述的碳化硅器件终端结构的制造方法，其中，所述第一沟槽的开口宽度大于所述第二沟槽的开口宽度。
  6. 如权利要求3所述的碳化硅器件终端结构的制造方法，其中，步骤三完成后，重复进行步骤三并通过控制步骤三的次数来控制形成的所述第一沟槽和所述第二沟槽的侧壁的台阶数量。
  7. 如权利要求3所述的碳化硅器件终端结构的制造方法，其中，所述绝缘层位于所述n型碳化硅层上并填充所述第一沟槽和所述第二沟槽。
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