WO2023178874A1 - 封装壳体的制备方法及封装芯片的制备方法 - Google Patents

封装壳体的制备方法及封装芯片的制备方法 Download PDF

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Publication number
WO2023178874A1
WO2023178874A1 PCT/CN2022/102669 CN2022102669W WO2023178874A1 WO 2023178874 A1 WO2023178874 A1 WO 2023178874A1 CN 2022102669 W CN2022102669 W CN 2022102669W WO 2023178874 A1 WO2023178874 A1 WO 2023178874A1
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Prior art keywords
substrate
opening
carrier
layer
groove
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PCT/CN2022/102669
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English (en)
French (fr)
Inventor
王逸群
汪松
孙远
刘天建
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湖北江城芯片中试服务有限公司
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Priority to JP2023519343A priority Critical patent/JP7510654B2/ja
Publication of WO2023178874A1 publication Critical patent/WO2023178874A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4803—Insulating or insulated parts, e.g. mountings, containers, diamond heatsinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/52—Mounting semiconductor bodies in containers

Definitions

  • Embodiments of the present disclosure relate to the field of semiconductor packaging technology, and in particular to a method of preparing a packaging shell and a method of preparing a packaged chip.
  • the packaging process of semiconductor chips refers to the process steps of encapsulating and fixing one or more semiconductor chips cut from the wafer into a packaging shell to prevent physical damage, corrosion, etc., in order to carry and support the semiconductor chips. Avoid direct contact between the semiconductor chip and the external environment to prevent damage and failure of the semiconductor chip.
  • embodiments of the present disclosure provide a method of manufacturing a packaging case and a method of manufacturing a packaging chip.
  • a method for preparing a packaging housing including:
  • a substrate is provided; wherein the substrate has opposing first and second surfaces;
  • An opening is formed on the first surface of the substrate; wherein the bottom of the opening is located in the substrate;
  • a groove is formed on the second surface of the substrate; wherein, in a direction perpendicular to the substrate, the groove and the opening are connected;
  • the carrier layer is removed.
  • the method before forming the opening, the method further includes:
  • the opening includes a connected first sub-hole and a second sub-hole; forming the opening on the first surface of the substrate includes:
  • a second etching is performed on the bottom of the first sub-hole to penetrate part of the thickness of the substrate to form the second sub-hole; wherein the bottom of the second sub-hole is located in the substrate.
  • the method before forming the second sub-hole, the method further includes:
  • Performing the second etching includes:
  • the second etching is performed on the barrier layer at the bottom of the first sub-hole and the substrate to penetrate the barrier layer at the bottom of the first sub-hole and part of the thickness of the substrate to form the third Er Zi Kong.
  • bonding the first surface of the substrate on which the opening is formed to a carrier includes:
  • an adhesive layer is formed on the surface of the dielectric layer and/or the carrier, and the dielectric layer and the carrier are bonded through the adhesive layer.
  • the method before forming the adhesive layer, the method further includes:
  • a filler is formed in the opening; wherein the filler at least closes the opening of the opening.
  • the filler is made of the same material as the adhesive layer.
  • the method further includes:
  • fixing the second surface of the substrate with the groove on the carrier layer includes: pasting the second surface of the substrate with the groove on the carrier layer. on the bearing layer to fix the second surface and the bearing layer;
  • the step of removing the bearing layer after removing the bearing body includes: removing the bearing layer after removing the adhesive layer and the filler in the opening.
  • the method before forming the groove, the method further includes:
  • the second surface of the substrate is thinned; wherein the thickness of the thinned substrate is greater than the depth of the opening.
  • a method for manufacturing a chip package including:
  • the semiconductor chip is fixed to the package housing, and the semiconductor chip is disposed in the groove; wherein the opening exposes at least a partial area of the semiconductor chip.
  • one side of the semiconductor chip is provided with a bonding pad, and the bonding pad is exposed from the opening, and the method further includes:
  • the opening is filled with conductive material to form a conductive plug coupled to the pad.
  • Figure 1a is a schematic diagram 1 of a method for preparing a packaging housing according to an exemplary embodiment
  • Figure 1b is a schematic diagram 2 of a method for preparing a packaging case according to an exemplary embodiment
  • Figure 1c is a schematic diagram 3 of a method for preparing a packaging case according to an exemplary embodiment
  • Figure 1d is a schematic diagram 4 of a method for preparing a packaging case according to an exemplary embodiment
  • Figure 2 is a schematic flow chart of a method for preparing a packaging housing according to an embodiment of the present disclosure
  • Figure 3a is a schematic diagram 1 of a method for preparing a packaging shell according to an embodiment of the present disclosure
  • Figure 3b is a schematic diagram 2 of a method for preparing a packaging shell according to an embodiment of the present disclosure
  • Figure 3c is a schematic diagram 3 of a method for preparing a packaging shell according to an embodiment of the present disclosure
  • Figure 3d is a schematic diagram 4 of a method for preparing a packaging shell according to an embodiment of the present disclosure
  • Figure 3e is a schematic diagram 5 of a method for preparing a packaging shell according to an embodiment of the present disclosure
  • Figure 3f is a schematic diagram 6 of a method for preparing a packaging shell according to an embodiment of the present disclosure
  • Figure 3g is a schematic diagram 7 of a method for preparing a packaging shell according to an embodiment of the present disclosure
  • Figure 3h is a schematic diagram 8 of a method for preparing a packaging shell according to an embodiment of the present disclosure
  • Figure 4a is a schematic diagram 9 of a method for preparing a packaging shell according to an embodiment of the present disclosure
  • Figure 4b is a schematic diagram 10 of a method for preparing a packaging shell according to an embodiment of the present disclosure
  • Figure 4c is a schematic diagram 11 of a method for preparing a packaging shell according to an embodiment of the present disclosure
  • Figure 4d is a schematic diagram 12 of a method for preparing a packaging shell according to an embodiment of the present disclosure
  • Figure 4e is a schematic diagram 13 of a method for preparing a packaging shell according to an embodiment of the present disclosure
  • Figure 4f is a schematic diagram of a method for preparing a packaging shell according to an embodiment of the present disclosure
  • Figure 4g is a schematic diagram 15 of a method for preparing a packaging shell according to an embodiment of the present disclosure
  • Figure 4h is a schematic diagram 16 of a method for preparing a packaging shell according to an embodiment of the present disclosure
  • Figure 4i is a schematic view of a method for preparing a packaging shell according to an embodiment of the present disclosure
  • Figure 5a is a schematic diagram 1 of a method for preparing a packaged chip according to an embodiment of the present disclosure
  • Figure 5b is a schematic diagram 2 of a method for preparing a packaged chip according to an embodiment of the present disclosure
  • Figure 5c is a schematic diagram 3 of a method for preparing a packaged chip according to an embodiment of the present disclosure
  • Figure 5d is a schematic diagram 4 of a method for preparing a packaged chip according to an embodiment of the present disclosure.
  • the term "A and B are in contact” includes the situation where A and B are in direct contact, or the situation where A and B are interposed with other components and A is in indirect contact with B.
  • the term "layer" refers to a portion of material that includes a region having a thickness.
  • a layer may extend over the entirety of the underlying or overlying structure, or may have an extent that is less than the extent of the underlying or overlying structure.
  • a layer may be a region of a homogeneous or non-homogeneous continuous structure having a thickness less than the thickness of the continuous structure.
  • the layer may be located between the top and bottom surfaces of the continuous structure, or the layer may be between any horizontal plane at the top and bottom surfaces of the continuous structure. Layers may extend horizontally, vertically and/or along inclined surfaces.
  • a layer may include multiple sub-layers.
  • FIGS. 1a to 1d are schematic diagrams of a method for preparing a packaging housing according to an exemplary embodiment. Referring to Figures 1a to 1d, the method includes:
  • Step 1 Referring to Figure 1a, provide a first substrate 110a.
  • the first substrate 110a has an opposite first surface and a second surface; bond the second surface of the first substrate 110a to the first carrier 120a; in the A groove 111 is formed on the first surface of a substrate 110a through the first substrate 110a until the first carrier 120a is exposed;
  • Step 2 Referring to FIG. 1b, provide a second substrate 110b.
  • the second substrate 110b has an opposite third surface and a fourth surface; bond the fourth surface of the second substrate 110b to the second carrier 120b; in the The third surface of the two substrates 110b forms an opening 112 that penetrates the second substrate 110b until the second carrier 120b is exposed; wherein, the diameter of the opening 112 is smaller than the diameter of the groove 111;
  • Step 3 Referring to Figure 1c, bond the first surface of the first substrate 110a and the third surface of the second substrate 110b; wherein, in the direction perpendicular to the first substrate 110a and the second substrate 110b, the groove 111 Connected to opening 112;
  • Step 4 Referring to Figure 1d, after bonding the first substrate 110a and the second substrate 110b, remove the first carrier 120a and the second carrier 120b.
  • three grooves 111 are formed in the first substrate 110a and three openings 112 are formed in the second substrate 110b, which are only used as an example to illustrate this embodiment.
  • This embodiment does not limit the number of grooves 111 and the number of openings 112 .
  • the groove 111 in the first substrate 110a and the opening 112 in the second substrate 110b are connected through bonding.
  • the diameter of the groove 111 is larger than the diameter of the opening 112 and can be a groove.
  • 111 is in communication with one opening 112, or one groove 111 is in communication with multiple openings 112.
  • the process of forming the groove 111 and the opening 112 includes but is not limited to: dry etching process, wet etching process or any combination thereof.
  • the structure after removing the first carrier 120a and the second carrier 120b can be used as a semiconductor chip packaging case for semiconductor chip packaging.
  • the semiconductor chip is fixed in the groove 111 in the first substrate 110a, and a conductive plug is formed in the opening 112 of the second substrate 110b to couple with the semiconductor chip to connect the electrical signal of the semiconductor chip. Lead out for electrical signal interconnection with external integrated circuits.
  • the first carrier 120 a may not be etched.
  • the first carrier 120a can be used to protect the carrier platform used to carry the wafer in the dry etching machine (for example, electrostatic chuck ESC or vacuum suction cup, etc.), so that the first substrate 110a is penetrated by the cavity to prevent the etchant from passing through.
  • the cavity contacts the bearing platform, reducing damage to the bearing platform.
  • a vacuum adsorption device eg, a vacuum suction cup
  • the vacuum adsorption device directly contacts the first substrate 110a formed with the groove 111.
  • the groove 111 will destroy the vacuum environment between the first substrate 110a and the vacuum adsorption device, and the adsorption action cannot be completed, and thus The first substrate 110a cannot be transferred, and the first substrate 110a cannot be fixed for subsequent chemical mechanical grinding and wheel grinding processes.
  • the first substrate 110a may even be fragmented due to failure of adsorption, jeopardizing the equipment.
  • the first carrier 120a is bonded to the first substrate 110a, and by adsorbing or grabbing the first carrier 120a, the adsorption or grabbing of the first substrate 110a can be completed, thereby reducing the risk of fragments of the first substrate 110a, thereby reducing the risk of fragments of the first substrate 110a. Reduce damage to equipment caused by fragments.
  • the function of the second carrier 120b is similar to that of the first carrier 120a, and will not be described again here.
  • the groove 111 and the opening 112 need to be aligned to ensure that the groove 111 and the opening 112 are connected.
  • the difficulty of alignment during bonding increases, resulting in the failure of the grooves 111 and the openings 112 to communicate, thereby reducing the production yield of the package housing.
  • the bonding between the first substrate 110 a and the second substrate 110 b may fail. , causing the first substrate 110a and the second substrate 110b to be separated.
  • the package case 100 shown in FIG. 1d has the risk of debonding of the first substrate 110a and the second substrate 110b during high temperature or external force extrusion, which increases the risk of semiconductor chip failure.
  • FIG. 2 is a schematic flowchart of a method for preparing a packaging case according to an embodiment of the present disclosure.
  • FIGS. 3a to 3h are schematic diagrams of a method of preparing a packaging case according to an embodiment of the present disclosure. Referring to Figure 2, Figure 3a to Figure 3h, the preparation method includes the following steps:
  • S100 Referring to FIG. 3a, provide a substrate 210; wherein the substrate 210 has an opposite first surface and a second surface;
  • S200 Referring to Figure 3b, form an opening 211 on the first surface of the substrate 210; wherein the bottom of the opening 211 is located in the substrate 210;
  • S300 Referring to Figure 3c and Figure 3d, bond the first surface of the substrate 210 with the opening 211 to the carrier 220; wherein the carrier 220 covers the opening 211;
  • S700 Referring to FIG. 3h, after removing the carrier 220, remove the carrier layer 231.
  • the constituent materials of the substrate 210 may include: elemental semiconductor materials (such as silicon, germanium), group III-V compound semiconductor materials, group II-VI compound semiconductor materials, organic semiconductor materials, or other semiconductor materials known in the art. .
  • the constituent materials of the substrate 210 may also include silicon oxide materials, aluminum oxide (sapphire) or ceramic materials.
  • the first surface may be the upper surface of the substrate 210
  • the second surface may be the lower surface of the substrate 210 opposite the first surface, which will not be described again below.
  • the formation process of the opening 211 and the groove 212 includes but is not limited to: dry etching process, wet etching process or any combination thereof.
  • the carrier 220 may include a semiconductor wafer, and the component material of the carrier 220 may be the same as or different from the substrate 210 .
  • the opening 211 when an etching process is performed on the first surface of the substrate 210 to form the opening 211 , the opening 211 only penetrates part of the thickness of the substrate 210 , that is, the depth of the opening 211 is smaller than the depth of the substrate 210
  • the thickness of the opening 211 is a blind hole located in the substrate 210 .
  • the bonding process in which the first surface of the substrate 210 formed with the opening 211 is bonded to the carrier 220 may include direct bonding or bonding through other bonding media.
  • direct bonding may include thermocompression bonding. Specifically, at a relatively high temperature, pressure is applied between the bonding surfaces of the substrate 210 and the carrier 220 so that the molten bonding surfaces come into contact, and the bonding can be completed after cooling.
  • the substrate 210 and the carrier 220 are made of the same material (for example, the substrate 210 and the carrier 220 are both silicon materials, or the substrate 210 and the carrier 220 are metal materials), or the materials of the substrate 210 and the carrier 220 are compatible ( For example, if the substrate 210 is made of silicon material and the carrier 220 is made of silicon oxide material), a direct bonding process can be applied.
  • the substrate 210 and the carrier 220 are not in direct contact during the bonding process, and other bonding media are formed between the substrate 210 and the carrier 220 for bonding.
  • a bonding glue is applied on the surface of the substrate 210 and/or the surface of the carrier 220 to form an adhesive layer 251, and the substrate 210 and the carrier 220 are bonded together through the bonding glue.
  • the coated bonding glue is located on the surface of the substrate 210 facing the carrier 220; and/or, during bonding, the coated bonding glue is located on the surface of the carrier 220 facing the substrate 210.
  • the bonding glue can be used to fill the opening 211 and support the opening 211, thereby reducing the probability of the opening 211 deforming during the bonding process and improving packaging. Housing preparation yield.
  • the carrier 220 covers the first surface of the substrate 210 on which the opening 211 is formed, and the carrier 220 completely covers the opening of the opening 211 to seal the opening of the opening 211 .
  • This further facilitates the formation of the groove 212 communicating with the opening 211 on the second surface of the substrate 210, reducing the probability of fragments of the substrate 210 caused by failure of vacuum adsorption, and improving the production yield of the packaging substrate.
  • the carrier 220 is located on the substrate 210 in the z direction.
  • the bonded carrier 220 and the substrate 210 need to be flipped over so that the substrate 210 is located above the carrier 220.
  • the second surface of the substrate 210 can be exposed to the etchant to form the groove 212 .
  • an etching process may be performed to form the groove 212.
  • the carrier 220 is in contact with the bearing platform of the etching equipment to prevent the first surface of the substrate 210 with the opening 211 from being damaged by contact with the bearing platform.
  • the second surface of the substrate 210 is protected by the carrier 220, and will not directly contact the transfer equipment during the transfer process of the substrate 210, thereby reducing damage to the second surface of the substrate 210.
  • the etchant will reach the surface of the carrier 220 along the opening 211 .
  • the presence of the carrier 220 can reduce or even avoid damage to the carrier platform by the etchant.
  • the groove 212 and the opening 211 together form a through cavity that penetrates the substrate 210, and the carrier 220 can convert the through cavity with the opening 211.
  • One side that is, the first surface of the substrate 210 on which the opening 211 is formed
  • the vacuum adsorption method can be used.
  • the chip is grasped and the risk of fragments due to grasping failure is reduced, thereby increasing the production yield of the package housing.
  • the vacuum suction cup can adsorb and grasp the carrier 220, and together with the substrate 210, the substrate 210 can be transferred or turned over.
  • one groove 212 and one opening 211 shown in this embodiment are only examples, and more grooves 212 and more openings 211 can be formed.
  • one groove 212 may be formed to communicate with at least one opening 211, and the number of connected openings 211 is not specifically limited. It can be understood that in some embodiments, one groove 212 formed may be connected with two openings 211 , three openings 211 or more openings 211 . The number of openings 211 connected to the same groove 212 can be directly related to the number of conductive plugs that need to be provided for subsequent chips embedded in the groove.
  • one groove 212 in the z direction, can communicate with at least two openings 211 to form a through-cavity with holes.
  • the size of the groove 212 is larger than the size of the opening 211 in a plane perpendicular to the z-direction. Specifically, in some examples, as shown in FIGS. 3e to 3h , on the projection plane perpendicular to the z direction, the projection of the opening 211 falls within the projection range of the groove 212 .
  • the shapes of the groove 212 and the opening 211 may include a cylinder, and the diameter of the groove 212 is larger than the diameter of the opening 211 . In this way, when the groove 212 is formed, the difficulty of aligning the groove 212 and the opening 211 can be reduced, the phenomenon that the groove 212 and the opening 211 cannot be connected can be reduced, and the production yield of the package housing can be improved.
  • the projected area of the carrier 220 is greater than or equal to the projected area of the substrate 210 , that is, in the z-direction, the carrier 220 can
  • the opening 211 is formed on the first surface of the substrate 210 to completely cover it. In this way, the carrier 220 can better protect and seal the first surface of the substrate 210 on which the opening 211 is formed, which is more conducive to vacuum adsorption of the substrate 210 and improves the production yield of the packaging case.
  • the fixing method between the second surface of the substrate 210 and the carrier layer 231 may include: adhesion, vacuum adsorption or electrostatic adsorption.
  • the carrier layer 231 may include an adhesive film, and another surface of the film may be adhered to other devices.
  • the film can be peeled off from the substrate 210 to form the package housing 200 as shown in Figure 3h.
  • the carrier layer 231 may also include a vacuum adsorption element or an electrostatic adsorption element.
  • the carrier layer 231 and the substrate 210 can be desorbed to separate the carrier layer 231 and the substrate 210.
  • the carrier layer 231 is used to fix the substrate 210, which can reduce the number of wafer bonding processes required and reduce the manufacturing cost. Furthermore, compared with the fixing process of wafer bonding, the carrier layer 231 in the embodiment of the present disclosure is easier to remove, which facilitates the execution of S700 and improves packaging while reaching the second surface of the substrate 210 formed with the groove 212 . Housing preparation yield.
  • the bearing layer 231 is located on the bearing body 220.
  • one side of the carrier layer 231 can be fixed manually or by other equipment, and then the substrate 210 fixed on the other side of the carrier layer can be flipped over so that the carrier 220 is located on the carrier layer 231. , to facilitate removal of the carrier 220.
  • a heating debonding method can be used to separate the carrier 220 from the substrate 210 .
  • the carrier 220 can continue to be recycled after being cleaned and polished.
  • the packaging shell 200 in FIG. 3h can be used for packaging semiconductor chips, and the dimensions of the grooves 212 and the openings 211 are relatively small and can include micrometers or even nanometers.
  • the semiconductor chip is disposed in the groove 212 and fixed with the package housing 200 , and the semiconductor chip is exposed from the opening 211 .
  • the semiconductor chip may include an optoelectronic chip or a photosensitive device, and the opening 211 may be used as a light path for transmission of optical signals.
  • conductive plugs may also be formed in the openings 211 to be coupled with the semiconductor chip to extract electrical signals from the semiconductor chip for electrical signal interconnection with external integrated circuits.
  • the first surface of the substrate is bonded to the carrier, and the carrier covers the opening. Because the carrier covers the opening, the substrate can be vacuum-adsorbed through the carrier, which facilitates the formation of a groove on the second surface of the substrate that communicates with the opening, reduces the probability of substrate fragments caused by vacuum adsorption failure, and improves the packaging shell. preparation yield. Moreover, after the carrier is bonded to the first surface with the opening formed on the substrate, during the transfer process of the substrate and the preparation process such as forming the groove, the carrier is in direct contact with the device to reduce damage to the first surface of the substrate.
  • grooves and openings that communicate with each other are prepared on a substrate.
  • the embodiments of the present disclosure reduce the number of bonding times of the substrates and omit the use of grooves and openings during bonding.
  • the alignment process at the same time reduces the risk of the package case cracking due to substrate debonding during use, and improves the package case yield rate.
  • the method before performing S200, the method further includes:
  • a dielectric layer 241 covering the first surface is formed; wherein, an electrical connection structure 242 is embedded in the dielectric layer 241;
  • the opening 211 includes a connected first sub-hole 211a and a second sub-hole 211b; the opening 211 is formed on the first surface of the substrate 210, including:
  • the dielectric layer 241 is first etched until the substrate 210 is exposed to form the first sub-hole 211a;
  • a second etching is performed on the bottom of the first sub-hole 211a to penetrate part of the thickness of the substrate 210 to form a second sub-hole 211b; wherein the bottom of the second sub-hole 211b is located in the substrate 210.
  • the dotted line between the first sub-hole 211a and the second sub-hole 211b shown in FIG. 4c is only used to more intuitively distinguish the first sub-hole 211a and the second sub-hole in this embodiment. 211b area. In the actual preparation process of the packaging housing, this dotted line does not exist.
  • the constituent materials of the dielectric layer 241 include, but are not limited to, insulating materials such as silicon oxide, silicon nitride, or silicon oxynitride.
  • the formation process of the dielectric layer 241 may include any process known in the art, such as a low-temperature chemical vapor deposition process, a low-pressure chemical vapor deposition process, a rapid thermal chemical vapor deposition process, an atomic layer deposition process, or plasma enhanced chemistry. Vapor deposition, etc.
  • the first etching and the second etching include but are not limited to: dry etching, wet etching or any combination thereof.
  • the electrical connection structure 242 may include, but is not limited to: conductive pads, conductive lines, wiring layers, or any combination thereof.
  • the constituent materials of the electrical connection structure 242 include but are not limited to: copper, tungsten, aluminum, gold, titanium or nickel.
  • the present disclosure does not limit the number of electrical connection structures 242, such as one or more conductive pads, one wiring layer or multiple stacked wiring layers.
  • the electrical connection structure 242 is formed in the dielectric layer 241.
  • the dielectric layer 241 surrounds the electrical connection structure 242, supports the electrical connection structure 242, and reduces damage to the electrical connection structure 242. It can also be placed between the electrical connection structure 242. Form electrical insulation between them to reduce short circuits.
  • the size of the electrical connection structure 242 is tiny, may include micrometer level, or even nanometer level, and may be used for coupling with a semiconductor chip or for coupling with other semiconductor structures (or semiconductor devices).
  • the electrical connection structure 242 can be used as a lead structure of the packaging shell, to form a coupling with the semiconductor chip during the packaging process of the semiconductor chip, to extract the electrical signals of the semiconductor chip, and to interconnect the electrical signals with the external integrated circuit. .
  • the electrical connection structure 242 can also be coupled with other electronic components to integrate more functions on the package shell.
  • the substrate 210 in S100 may be a wafer, and the electrical connection structure 242 may be formed on the wafer in advance.
  • the electrical connection structure 242 may include multiple bonding pads, multiple conductive lines, etc. that are coupled to each other. structure. It should be emphasized that when performing S200, the opening 211 will not penetrate or destroy these conductive structures. For example, openings 211 are formed in gaps between conductive structures.
  • the substrate 210 may also be a wafer including a semiconductor structure (the semiconductor structure is not shown in the drawings of this embodiment).
  • the semiconductor structure may include a CMOS circuit, a memory device, an optoelectronic device or a communication device, etc.
  • the electrical connection structure 242 is formed on the wafer and coupled with the semiconductor structure, so that more functions can be integrated into the prepared package shell.
  • the thickness of the dielectric layer 241 and the substrate 210 is relatively large, and it is difficult to form the opening 211 through the dielectric layer 241 and through part of the thickness of the substrate 210 through one etching, which is not conducive to The overall shape of the opening 211 is maintained in good condition.
  • the opening 211 is formed through two etchings, which can reduce the difficulty of the etching process and help expand the etching process window.
  • the dielectric layer 241 and the substrate 210 are made of different materials. It is difficult to etch holes in different materials at one time, and it is difficult to control the shape of the opening 211 to be good.
  • the dielectric layer 241 is silicon oxide
  • the substrate 210 is silicon.
  • the etching rate of silicon oxide is greater than the etching rate of silicon, or the first etching does not substantially etch silicon.
  • the etching rate of silicon is greater than the etching rate of silicon oxide, or the second etching does not substantially etch silicon oxide.
  • the first sub-hole 211a and the second sub-hole 211b are formed step by step by etching different material layers step by step, which facilitates the morphology control of the sub-holes, thereby improving the quality of the final opening 211 and improving the quality of the final opening 211.
  • the preparation yield of the packaging casing is conducive to the expansion of the etching process window.
  • the method before forming the second sub-hole 211b, the method further includes:
  • Performing the second etch involves:
  • a second etching is performed on the barrier layer 243 at the bottom of the first sub-hole 211a and the substrate 210 to penetrate the barrier layer 243 at the bottom of the first sub-hole 211a and part of the thickness of the substrate 210 to form a second sub-hole 211b.
  • composition material of the barrier layer 243 includes but is not limited to: silicon oxide, silicon nitride, silicon oxynitride, or aluminum oxide.
  • the etching rate of the barrier layer 243 is less than the etching rate of the substrate 210 , or the second etching does not substantially etch the barrier layer 243 .
  • the barrier layer 243 can reduce the etching of the sidewall of the first sub-hole 211a by the second etching, and is beneficial to maintaining the good shape of the first sub-hole 211a, thereby improving the quality of the final opening 211 and improving the manufacturing yield of the packaging case.
  • S300 includes:
  • an adhesive layer 251 is formed on the surface of the dielectric layer 241 and/or the carrier 220 , and the dielectric layer 241 and the carrier 220 are bonded through the adhesive layer 251 .
  • the constituent materials of the adhesive layer 251 include but are not limited to: bonding glue, photosensitive glue (also called UV glue or ultraviolet curing glue) or viscous resin.
  • the dielectric layer 241 and the carrier 220 on the substrate 210 are bonded through the adhesive layer 251.
  • bonding glue is coated on the surface of the dielectric layer 241 and/or the carrier 220, and they are bonded through the bonding glue.
  • substrate 210 and carrier 220 are bonded through the bonding glue.
  • the adhesive layer 251 may not fill the opening 211 .
  • the bonding glue is applied to the surface of the carrier 220, and then the surface of the carrier 220 coated with the bonding glue is bonded to the surface of the substrate 210 with the dielectric layer 241. The bonding glue will not damage the opening 211. To fill.
  • the adhesive layer 251 when the adhesive layer 251 is formed, the adhesive layer 251 can fill the opening 211 .
  • the bonding glue is applied to the surface of the dielectric layer 241 where the openings 211 are formed, and the bonding glue can fill the openings 211 at the same time.
  • the bonding layer 251 can be bonded in a relatively low-temperature environment, reducing damage to the substrate 210 caused by high temperatures and conducive to reducing the production cost. cost. Moreover, during the execution of S600, by heating the adhesive layer 251, the adhesive layer 251 can be reduced or lose its viscosity, thereby separating the substrate 210 from the carrier 220 and reducing damage to the substrate 210 when the carrier 220 is removed. Reduce the preparation difficulty and improve the preparation yield of the packaging shell.
  • the method before forming the adhesive layer 251, the method further includes:
  • a filler 252 is formed in the opening 211; wherein the filler 252 at least closes the opening of the opening 211.
  • the constituent materials of the filler 252 include but are not limited to: bonding glue, photosensitive glue, bottom anti-reflective coating, silicon oxide, silicon nitride, silicon oxynitride or metal materials.
  • the formation process of the filler 252 may include any process known in the art, such as a low-temperature chemical vapor deposition process, a low-pressure chemical vapor deposition process, a rapid thermal chemical vapor deposition process, an atomic layer deposition process, and plasma enhanced chemistry. Vapor deposition or spin coating process, etc.
  • this embodiment does not limit the number of openings 211. It can be understood that when the number of openings 211 formed on the first surface of the substrate 210 is greater, the remaining area on the first surface of the substrate 210 will be smaller, and the area on the first surface of the substrate 210 that can be bonded to the carrier 220 will be smaller. The less, the lower the bonding strength.
  • a filler 252 is formed in the opening 211 .
  • the filler 252 may only close the opening of the opening 211 , or may fill all the openings 211 . Alternatively, the filler 252 closes the opening of the opening 211, and there may be an air gap in the filler 252 in the middle or bottom of the opening 211.
  • the filler 252 closes the opening of the opening 211, which can increase the bonding area between the first surface of the substrate 210 and the carrier 220, improve the bonding strength, and also support and protect the opening 211, reducing the occurrence of deformation defects of the opening 211.
  • the filler 252 is made of the same material as the adhesive layer 251 .
  • the constituent materials of the filler 252 and the adhesive layer 251 may include bonding glue, photosensitive glue (also called UV glue or ultraviolet curing glue), or viscous resin.
  • bonding glue is applied to the first surface of the substrate 210 to fill the opening 211 , and the bonding glue at least closes the opening of the opening 211 .
  • the bonding glue is continued to be coated on the first surface of the substrate 210 to form an adhesive layer 251 covering the first surface of the substrate 210, and then the first surface of the substrate 210 and the carrier 220 are bonded. In this way, the steps of depositing other materials to form the filler 252 can be reduced and the manufacturing cost can be reduced.
  • the opening 211 is filled with the bonding glue, so that the opening 211 can be
  • the support is provided to reduce the probability of deformation of the opening 211 during the bonding process and improve the production yield of the packaging shell.
  • metal can be filled in the opening 211 to form a filler 252.
  • the metal filler 252 has higher mechanical strength, improves the support of the opening 211, and reduces the number of openings. 211 reduces the probability of deformation and improves the production yield of the packaging shell.
  • the metal filler 252 reacts with the etchant to generate metal ions, which are dissolved in the etchant, so that the metal filler 252 is removed more effectively and the metal filler 252 is reduced. 252 residue to improve yield.
  • the method further includes:
  • the adhesive layer 251 and the filler 252 in the opening 211 are removed.
  • Methods for removing the filler 252 in the adhesive layer 251 and the opening 211 include, but are not limited to: dry etching, wet etching, cleaning or any combination thereof.
  • the adhesive layer 251 and/or the filler 252 includes bonding glue or photosensitive adhesive
  • the adhesive layer 251 and openings can be removed by heating or ultraviolet irradiation, followed by wet etching and cleaning. Filler 252 in 211.
  • S500 includes: pasting the second surface of the substrate 210 with the groove 212 formed on the carrier layer 231 to fix the second surface and the carrier layer 231;
  • S700 includes: removing the carrier layer 231 after removing the adhesive layer 251 and the filler 252 in the opening 211.
  • the carrier layer 231 may be an adhesive carrier film or carrier plate. One side of the carrier film or carrier plate is adhered to the second surface of the substrate 210 to fix the second surface to achieve flipping of the substrate 210 . It can be understood that the carrier film or carrier plate may be provided with a bandage ring 232, through which the base plate 210 can be turned over and the carrier film or carrier plate can be removed.
  • the process of pasting and fixing in this embodiment is simpler, reduces damage to the second surface of the substrate 210 where the groove 212 is formed, and improves the yield of the package case.
  • both sides of the carrier film or carrier plate are adhesive, one side is adhered to the second surface of the substrate 210, and the other side can be adhered to the process equipment.
  • the method before forming groove 212, the method further includes:
  • the second surface of the substrate 210 is thinned; the thickness of the thinned substrate 210 is greater than the depth of the opening 211 .
  • the thinning process includes but is not limited to: dry etching, wet etching, chemical mechanical grinding, wheel grinding, or any combination thereof.
  • the thickness of the substrate 210 of the package shell includes: 150 microns to 300 microns. While having a certain thickness to maintain good mechanical properties, the substrate 210 is not thick enough to Too thick, reducing the integration density of integrated circuits.
  • the thickness of the substrate 210 is relatively thick, for example, when the substrate 210 is a silicon wafer, the thickness is approximately 775 microns, and the substrate 210 needs to be thinned.
  • the second surface of the substrate 210 can be thinned so that the thickness of the substrate 210 reaches 150 microns to 300 microns.
  • the amount of etching required to form the groove 212 can be reduced and the difficulty of etching can be reduced. It should be emphasized that after the second surface of the substrate 210 is thinned, the opening 211 is not exposed on the second surface of the remaining substrate 210 .
  • FIGS. 5a to 5d are schematic diagrams of a method for preparing a packaged chip according to an embodiment of the present disclosure. Referring to Figure 5a, the method includes:
  • the semiconductor chip 260 is fixed to the packaging case 200, and the semiconductor chip 260 is disposed in the groove 212; wherein the opening 211 exposes at least a partial area of the semiconductor chip 260.
  • the semiconductor chip 260 includes, but is not limited to: digital circuit chip, analog circuit chip, radio frequency/microwave circuit chip, microelectromechanical system (MEMS) chip, photonic chip, passive circuit chip, etc.
  • digital circuit chip analog circuit chip
  • radio frequency/microwave circuit chip radio frequency/microwave circuit chip
  • MEMS microelectromechanical system
  • MEMS microelectromechanical systems
  • the semiconductor chip 260 can be fixed in the groove 212 of the packaging case 200, and the fixing method can include bonding, lamination, welding and other processes.
  • Microelectromechanical system chips can include microcircuits and micromachines.
  • Micromachines can include microelectronic devices with mechanical movable structures that can convert electrical signals into physical signals such as displacement, speed, vibration, and sound waves. They can also convert electrical signals into physical signals such as displacement, speed, vibration, and sound waves. These physical signals are converted into electrical signals. Therefore, when packaging MEMS chips, it is necessary to minimize external pressure on the MEMS chips and provide a sealed movable space for the micromachines in the MEMS chips.
  • the semiconductor chip 260 is packaged using the packaging case 200 as shown in FIG. 3h.
  • the semiconductor chip 260 is fixed in the groove 212 , and the thickness of the semiconductor chip 260 may be smaller than the depth of the groove 212 .
  • the packaging cover 280 and the packaging case 200 can also be fixed.
  • the groove 212 in this embodiment can provide a sealed cavity for the semiconductor chip 260 after the packaging is completed, and can provide a movable space for the movable components of the MEMS chip. It can be understood that for other semiconductor chips 260 that do not require movable space, after the semiconductor chip 260 is fixed to the packaging substrate 210 , the groove 212 can be filled with insulating material to form an insulating layer covering the semiconductor chip 260 .
  • the semiconductor chip 260 may include an optoelectronic chip or a photosensitive device.
  • the opening 211 can be used as an optical path for the transmission of optical signals, allowing the semiconductor chip to interconnect with the optical signals.
  • the openings 211 may include multiple slit structures extending perpendicular to the xoz plane.
  • the multiple openings 211 may divide the first surface of the substrate 210 into multiple gratings.
  • the openings 211 transmit light.
  • the optical signal can also be debugged through transmitted light diffraction or reflected light diffraction to meet the requirements of different semiconductor chips 260 for optical signals of different intensities and different modes.
  • one side of the semiconductor chip 260 is provided with a bonding pad 261, and the bonding pad 261 is exposed from the opening 211; the method further includes:
  • the opening 211 is filled with conductive material to form a conductive plug 271 coupled to the pad 261 .
  • the formation process of the conductive plug 271 and the pad 261 includes but is not limited to: physical deposition, chemical deposition, or electroplating.
  • the constituent materials of the conductive plug 271 and the pad 261 include, but are not limited to, conductive materials such as copper, tungsten, aluminum, gold, titanium, or nickel.
  • the conductive plug 271 is coupled to the pad 261 to lead out the electrical signal of the semiconductor chip 260 for electrical signal interconnection with an external integrated circuit.
  • a package cover 280 with a recess may be used to form a cavity.
  • the semiconductor chip 260 can be packaged using the packaging case 200 as shown in FIG. 4i .
  • the conductive plug 271 can be coupled to the electrical connection structure 242 through the conductive structure 272 , and the electrical connection is
  • the structure 242 leads out the electrical signals from the semiconductor chip 260 for electrical signal interconnection with external integrated circuits.
  • the conductive structure 272 may include a cylindrical or elongated contact plug.
  • the dimensions of the groove 212, the opening 211, the pad 261, the conductive plug 271, the electrical connection structure 242 and the conductive structure 272 in the embodiment of the present disclosure may include micron level or even nano level to meet the requirements of highly integrated semiconductors. Chip packaging, thereby improving the integration of external integrated circuits.
  • the packaging case of this embodiment can provide a cavity for the semiconductor chip. While supporting and protecting the semiconductor chip, it can also be a semiconductor chip with movable parts (for example, a micro-electromechanical system chip). It provides movable space and can also provide interconnection of optical signals or electrical signals for different semiconductor chips, which is beneficial to the packaging of various semiconductor chips and to maintaining good functions of the semiconductor chips.
  • the first surface of the substrate is bonded to the carrier, and the carrier covers the opening. Because the carrier covers the opening, the substrate can be vacuum-adsorbed through the carrier, which facilitates the formation of a groove on the second surface of the substrate that communicates with the opening, reduces the probability of substrate fragments caused by vacuum adsorption failure, and improves the packaging shell. preparation yield. Moreover, after the carrier is bonded to the first surface with the opening formed on the substrate, during the transfer process of the substrate and the preparation process such as forming the groove, the carrier is in direct contact with the device to reduce damage to the first surface of the substrate.

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Abstract

一种封装壳体的制备方法及封装芯片的制备方法，封装壳体的制备方法包括：提供基板（210）；其中，基板（210）具有相对的第一表面和第二表面；在基板（210）的第一表面形成开孔（211）；其中，开孔（211）的底部位于基板（210）中；将基板（210）形成有开孔（211）的第一表面与承载体（220）键合；其中，承载体（220）覆盖开孔（211）；在第一表面与承载体（220）键合之后，在基板（210）的第二表面形成凹槽（212）；其中，在垂直于基板（210）的方向上，凹槽（212）与开孔（211）连通；将基板（210）形成有凹槽（212）的第二表面固定于承载层（231）上；在第二表面与承载层（231）固定之后，去除承载体（220）；在去除承载体（220）后，去除承载层（231）。

Description

封装壳体的制备方法及封装芯片的制备方法
相关申请的交叉引用
本公开基于申请号为202210283093.8、申请日为2022年03月22日、申请名称为“封装壳体的制备方法及封装芯片的制备方法”的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此以全文引入的方式引入本公开。
技术领域
本公开实施例涉及半导体封装技术领域，特别涉及一种封装壳体的制备方法及封装芯片的制备方法。
背景技术
半导体芯片的封装工艺，是指将由晶圆切割下来的一个或者多个半导体芯片包封、固定到用于防止物理损伤、腐蚀等的封装壳体中的工艺步骤，以此承载和支撑半导体芯片，避免半导体芯片与外部环境直接接触，防止半导体芯片损伤失效。
在集成电路中，可将多种半导体芯片以及其他电子元件集成在一起构成电子系统。对电子系统功能多元化、复杂化需求逐步提高的同时，要求电子系统的体积、功耗、重量进一步减小，促进了电子集成技术的飞速发展。不同半导体芯片之间功能各异，工艺节点、晶圆尺寸和半导体芯片尺寸相差巨大。如何实现这些不同尺寸、不同材料、不同工艺以及不同功能的半导体芯片的封装与集成，如何提高封装壳体制备过程的良率成为亟待解决的问题。
发明内容
有鉴于此，本公开实施例提供一种封装壳体的制备方法及封装芯片的制备方法。
根据本公开实施例的第一方面，提供一种封装壳体的制备方法，包括：
提供基板；其中，所述基板具有相对的第一表面和第二表面；
在所述基板的所述第一表面形成开孔；其中，所述开孔的底部位于所述基板中；
将所述基板形成有所述开孔的所述第一表面与承载体键合；其中，所述承载体覆盖所述开孔；
在所述第一表面与所述承载体键合之后，在所述基板的所述第二表面形成凹槽；其中，在垂直于所述基板的方向上，所述凹槽与所述开孔连通；
将所述基板形成有所述凹槽的所述第二表面固定于承载层上；
在所述第二表面与所述承载层固定之后，去除所述承载体；
在去除所述承载体后，去除所述承载层。
在一些实施例中，在形成所述开孔前，所述方法还包括：
形成覆盖所述第一表面的介质层；其中，所述介质层中嵌设有电连接结构；
所述开孔包括连通的第一子孔和第二子孔；所述在所述基板的所述第一表面形成开孔，包括：
在所述开孔的预设形成位置，对所述介质层进行第一蚀刻，直至显露所述基板，以形成所述第一子孔；
对所述第一子孔底部进行第二蚀刻，以贯穿部分厚度的所述基板，形成所述第二子孔；其中，所述第二子孔的底部位于所述基板中。
在一些实施例中，在形成所述第二子孔前，所述方法还包括：
形成覆盖所述第一子孔内壁的阻挡层；
进行所述第二蚀刻包括：
对所述第一子孔底部的所述阻挡层和所述基板进行所述第二蚀刻，以贯穿所述第一子孔底部的所述阻挡层以及部分厚度的所述基板，形成所述第二子孔。
在一些实施例中，所述将所述基板形成有所述开孔的所述第一表面与承载体键合，包括：
形成所述开孔后，在所述介质层和/或所述承载体表面形成黏接层，通过所述黏接层键合所述介质层和所述承载体。
在一些实施例中，在形成所述黏接层之前，所述方法还包括：
在所述开孔中形成填充物；其中，所述填充物至少闭合所述开孔的开口。
在一些实施例中，所述填充物的组成材料与所述黏接层的组成材料相同。
在一些实施例中，在去除所述承载体之后，所述方法还包括：
去除所述黏接层和所述开孔中的所述填充物。
在一些实施例中，所述将所述基板形成有所述凹槽的所述第二表面固定于承载层上，包括：将所述基板形成有所述凹槽的所述第二表面粘贴于所述承载层上，以固定所述第二表面和所述承载层；
所述在去除所述承载体后，去除所述承载层，包括：在去除所述黏接层和所述开孔中的所述填充物之后，去除所述承载层。
在一些实施例中，在形成所述凹槽之前，所述方法还包括：
对所述基板的所述第二表面进行减薄；其中，减薄后的所述基板的厚度大于所述开孔的深度。
根据本公开实施例的第二方面，提供一种芯片封装的制备方法，包括：
提供所述的方法制备的封装壳体；
提供半导体芯片；
将所述半导体芯片与所述封装壳体固定，所述半导体芯片设置在所述凹槽中；其中，所述开孔显露所述半导体芯片的至少部分区域。
在一些实施例中，所述半导体芯片的一面设置有焊盘，所述焊盘从所述开孔中显露，所述方法还包括：
以导电材料填充所述开孔，以形成与所述焊盘耦接的导电插塞。
附图说明
图1a是根据一示例性实施例示出的一种封装壳体的制备方法的示意图一；
图1b是根据一示例性实施例示出的一种封装壳体的制备方法的示意图二；
图1c是根据一示例性实施例示出的一种封装壳体的制备方法的示意图三；
图1d是根据一示例性实施例示出的一种封装壳体的制备方法的示意图四；
图2是根据本公开实施例示出的一种封装壳体的制备方法的流程示意图；
图3a是根据本公开实施例示出的一种封装壳体的制备方法的示意图一；
图3b是根据本公开实施例示出的一种封装壳体的制备方法的示意图二；
图3c是根据本公开实施例示出的一种封装壳体的制备方法的示意图三；
图3d是根据本公开实施例示出的一种封装壳体的制备方法的示意图四；
图3e是根据本公开实施例示出的一种封装壳体的制备方法的示意图五；
图3f是根据本公开实施例示出的一种封装壳体的制备方法的示意图六；
图3g是根据本公开实施例示出的一种封装壳体的制备方法的示意图七；
图3h是根据本公开实施例示出的一种封装壳体的制备方法的示意图八；
图4a是根据本公开实施例示出的一种封装壳体的制备方法的示意图九；
图4b是根据本公开实施例示出的一种封装壳体的制备方法的示意图十；
图4c是根据本公开实施例示出的一种封装壳体的制备方法的示意图十一；
图4d是根据本公开实施例示出的一种封装壳体的制备方法的示意图十二；
图4e是根据本公开实施例示出的一种封装壳体的制备方法的示意图十三；
图4f是根据本公开实施例示出的一种封装壳体的制备方法的示意图十四；
图4g是根据本公开实施例示出的一种封装壳体的制备方法的示意图十五；
图4h是根据本公开实施例示出的一种封装壳体的制备方法的示意图十六；
图4i是根据本公开实施例示出的一种封装壳体的制备方法的示意图十七；
图5a是根据本公开实施例示出的一种封装芯片的制备方法的示意图一；
图5b是根据本公开实施例示出的一种封装芯片的制备方法的示意图二；
图5c是根据本公开实施例示出的一种封装芯片的制备方法的示意图三；
图5d是根据本公开实施例示出的一种封装芯片的制备方法的示意图四。
具体实施方式
以下结合说明书附图及具体实施例对本公开的技术方案做进一步的详细阐述。
在本公开实施例中，术语“第一”、“第二”等是用于区别类似的对象，而不用于描述特定的顺序或先后次序。
在本公开实施例中，术语“A与B接触”包含A与B直接接触的情形，或者A、B两者之间还间插有其它部件而A间接地与B接触的情形。
在本公开实施例中，术语“层”是指包括具有厚度的区域的材料部分。层可以在下方或上方结构的整体之上延伸，或者可以具有小于下方或上方结构范围的范围。此外，层可以是厚度小于连续结构厚度的均质或非均质连续结构的区域。例如，层可位于连续结构的顶表面和底表面之间，或者层可在连续结构顶表面和底表面处的任何水平面对之间。层可以水平、垂直和/或沿倾斜表面延伸。并且，层可以包括多个子层。
可以理解的是，本公开中的“在……上”、“在……之上”和“在……上方”的含义应当以最宽方式被解读，以使得“在……上”不仅表示其“在”某物“上”且其间没有居间特征或层(即直接在某物上)的含义，而且还包括“在”某物“上”且其间有居间特征或层的含义。
需要说明的是，虽然本说明书按照实施方式加以描述，但并非每个实施方式仅包含一个独立的技术方案，说明书的这种叙述方式仅仅是为清楚起见，本领域技术人员应当将说明书作为一个整体，各实施方式中的技术方案也可以经适当组合，形成本领域技术人员可以理解的其它实施方式。
图1a至图1d是根据一示例性实施例示出的一种封装壳体的制备方法的示意图。参照图1a至图1d所示，该方法包括：
步骤一：参照图1a所示，提供第一基板110a，第一基板110a具有相对的第一面和第二面；将第一基板110a的第二面与第一承载体120a键合；在第一基板110a的第一面形成贯穿第一基板110a的凹槽111，直至显露第一承载体120a；
步骤二：参照图1b所示，提供第二基板110b，第二基板110b具有相对的第三面和第四面；将第二基板110b的第四面与第二承载体120b键合；在第二基板110b的第三面形成贯穿第二基板110b的开孔112，直至显露第二承载体120b；其中，开孔112的直径小于凹槽111的直径；
步骤三：参照图1c所示，键合第一基板110a的第一面和第二基板110b的第三面；其中，在垂直于第一基板110a和第二基板110b的方向上，凹槽111与开孔112连通；
步骤四：参照图1d所示，键合第一基板110a和第二基板110b之后，去除第一承载体120a和第二承载体120b。
结合图1a和图1b所示，在第一基板110a中形成三个凹槽111，在第二基板110b中形成三个开孔112，仅作为对该实施例的示例说明。该实施例对于凹槽111的数量以及开孔112的数量不作限制。
参照图1c和图1d所示，第一基板110a中的凹槽111与第二基板110b中的开孔112通过键合连通，凹槽111的直径大于开孔112的直径，可以是一个凹槽111与一个开孔112对应连通，也可以是一个凹槽111与多个开孔112对应连通。
示例性的，形成凹槽111和开孔112的工艺包括但不限于：干法蚀刻工艺、湿法蚀刻工艺或者其任意组合。
参照图1d所示，去除第一承载体120a和第二承载体120b后的结构可作为半导体芯片的封装壳体用于半导体芯片封装。在一些实施例中，将半导体芯片固定于第一基板110a中的凹槽111内，在第二基板110b的开孔112中形成导电插塞，与半导体芯片耦接，以将半导体芯片的电信号引出，用于与外部集成电路进行电信号互联。
继续参照图1a所示，在蚀刻形成凹槽111的过程中，可不对第一承载体120a进行蚀刻。第一承载体120a，可用于保护干法蚀刻机台中用于承载晶圆的承载台(例如，静电卡盘ESC或者真空吸盘等)，使得第一基板110a被空腔贯穿后，避免蚀刻剂通过空腔接触到承载台，减少承载台的损伤。
在封装壳体的制备过程中，第一基板110a在不同设备之间流转时，需要使用真空吸附设备(例如，真空吸盘)对第一基板110a进行传递。在进行化学机械研磨和轮磨工艺时，也需要使用真空吸附设备对第一基板110a进行吸附固定。如果没有第一承载体120a，真空吸附设备直接与形成有凹槽111的第一基板110a接触，凹槽111会破坏第一基板110a与真空吸附设备之间的真空环境，无法完成吸附动作，进而无法对第一基板110a进行传递，无法固定第一基板110a以进行后续的化学机械研磨和轮磨工艺，甚至会因为吸附失败而使得第一基板110a碎片，危害设备。
可以理解的是，由于多个凹槽111的存在，第一基板110a的机械强度会下降，直接吸附或者抓取第一基板110a会加大第一基板110a碎片的风险。因此，将第一承载体120a与第一基板110a键合，通过吸附或者抓取第一承载体120a，可完成对第一基板110a的吸附或者抓取，减少第一基板110a的碎片风险，进而减少破片对设备的损伤。第二承载体120b的作用于第一承载体120a作用类似，在此不作赘述。
参照图1c所示，在第一基板110a与第二基板110b的键合过程中，凹槽111与开孔112需要进行对准，以保证凹槽111与开孔112连通，当凹槽111与开孔112的个数增多时，键合时的对准难度增加，导致凹槽111与开孔112无法连通的现象，降低封装壳体的制备良率。
结合图1c和图1d所示，当以解键合的方式去除第一承载体120a以及第二承载体120b以形成封装壳体100时，可能会使第一基板110a和第二基板110b的键合失效，导致第一基板110a和第二基板110b分离。并且，在半导体芯片的使用过程中，图1d所示的封装壳体100，在高温或者外力挤压过程中存在第一基板110a和第二基板110b解键合的风险，增加半导体芯片失效的风险。
图2是根据本公开实施例示出的一种封装壳体的制备方法的流程示意图，图3a至图3h是根据本公开实施例示出的一种封装壳体的制备方法的示意图。参照图2、图3a至图3h所示，该制备方法包括以下步骤：
S100：参照图3a所示，提供基板210；其中，基板210具有相对的第一表面和第二表面；
S200：参照图3b所示，在基板210的第一表面形成开孔211；其中，开孔211的底部位于基板210中；
S300：参照图3c和图3d所示，将基板210形成有开孔211的第一表面与承载体220键合；其中，承载体220覆盖开孔211；
S400：参照图3e所示，在第一表面与承载体220键合之后，在基板210的第二表面形成凹槽212；其中，在垂直于基板210的方向上，凹槽212与开孔211连通；
S500：参照图3f所示，将基板210形成有凹槽212的第二表面固定于承载层231上；
S600：参照图3g所示，在第二表面与承载层231固定之后，去除承载体220；
S700：参照图3h所示，在去除承载体220后，去除承载层231。
示例性的，基板210的组成材料可包括：单质半导体材料(例如硅、锗)、Ⅲ-Ⅴ族化合物半导体材料、Ⅱ-Ⅵ族化合物半导体材料、有机半导体材料或者本领域已知的其它半导体材料。基板210的组成材料还可包括：氧化硅材料、氧化铝(蓝宝石)或者陶瓷材料。
示例性的，在垂直于基板210的z方向上，第一表面可以为基板210的上表面，第二表面可以为与第一表面相对的基板210的下表面，下文不再赘述。
示例性的，开孔211和凹槽212的形成工艺包括但不限于：干法蚀刻工艺、湿法蚀刻工艺或者其任意组合。
示例性的，承载体220可包括半导体晶圆，承载体220的组成材料可与基板210相同或不同。
具体的，参照图3b所示，在z方向上，对基板210的第一表面执行蚀刻工艺形成开孔211时，开孔211仅贯穿部分厚度的基板210，即开孔211的深度小于基板210的厚度，开孔211为位于基板210内的盲孔。
参照图3c所示，基板210形成有开孔211的第一表面与承载体220键合的 键合工艺可包括直接键合或者通过其他键合介质进行键合。
在一些实施例中，直接键合可包括热压键合。具体的，在较高的温度下，在基板210和承载体220的键合表面之间施加压力，使得熔融的键合表面接触，冷却后即可完成键合。基板210和承载体220的组成材料相同(例如，基板210和承载体220都为硅材料，或者，基板210和承载体220为金属材料)，或者基板210和承载体220的组成材料相亲和(例如，基板210为硅材料，承载体220为氧化硅材料)，可应用直接键合工艺。
在一些实施例中，参照图3d所示，基板210和承载体220在键合过程中不直接接触，在基板210和承载体220之间形成其他的键合介质进行键合。例如，在基板210表面和/或承载体220表面涂布键合胶以形成黏接层251，通过键合胶将基板210和承载体220键合在一起。可以理解的是，在键合时，涂布的键合胶位于基板210朝向承载体220的表面；和/或，在键合时，涂布的键合胶位于承载体220朝向基板210的表面。在涂布键合胶以形成黏接层251时，可利用键合胶对开孔211进行填充，可对开孔211进行支撑，减少开孔211在键合过程中发生变形的几率，提高封装壳体的制备良率。
需要强调的是，参照图3c所示，承载体220将基板210形成有开孔211的第一表面进行覆盖，承载体220完全覆盖开孔211的开口，以对开孔211的开口进行密封，进而便于在基板210的第二表面形成与开孔211连通凹槽212，减少真空吸附失败导致基板210碎片的几率，提高封装基板的制备良率。
参照图3c和图3d所示，执行S300后，在z方向上，承载体220位于基板210之上。参照图3e所示，执行S400前，需要将键合之后的承载体220和基板210进行翻转倒装，使基板210位于承载体220之上。由此，可使基板210的第二表面暴露在蚀刻剂中，以形成凹槽212。在执行S400时，可执行蚀刻工艺以形成凹槽212。承载体220与蚀刻设备的承载台接触，避免基板210具有开孔211的第一表面与承载台接触产生损伤。并且，基板210的第二表面有承载体220的保护，在基板210的传递过程中不会直接接触传递设备，减少基板210的第二表面的损伤。
继续参照图3e所示，凹槽212与开孔211连通之后，蚀刻剂会沿着开孔211到达承载体220表面，承载体220的存在可减少甚至避免蚀刻剂对承载台的损伤。
进一步地，凹槽212与开孔211连通后，在z方向上，凹槽212与开孔211一起组成一个贯穿基板210的贯穿空腔，承载体220可将该贯穿空腔具有开孔211的一侧(即，基板210的形成有开孔211的第一表面)进行密封，在对基板210进行真空吸附抓片动作时，贯穿空腔不会破坏真空吸附，如此，可采用真空吸附方式进行抓片，且降低了由于抓取失败而出现碎片的风险，由此增加封装壳体的制备良率。例如，在对基板210进行真空吸附时，真空吸盘可吸附 抓取承载体220，连带基板210进行传递或者翻转动作。
需要强调的是，本实施例中示出的一个凹槽212与一个开孔211仅作为示例，可形成更多的凹槽212以及更多的开孔211。
另外，形成的一个凹槽212可与至少一个开孔211连通，对于连通的开孔211的数量不作具体限制。可以理解的是，在一些实施例中，形成的一个凹槽212可以与两个开孔211、三个开孔211或者更多的开孔211连通。与同一个凹槽212连通的开孔211的数量，可根据后续嵌入在该凹槽中的芯片需要设置的导电插塞数量正相关。
在一些实施例中，结合图3e至图3h所示，在z方向上，一个凹槽212可与至少两个开孔211连通，以形成套孔的贯穿空腔。
在一些实施例中，在垂直于z方向的平面内，凹槽212的尺寸大于开孔211的尺寸。具体地，在一些示例中，结合图3e至图3h所示，在垂直于z方向的投影面上，开孔211的投影落在凹槽212的投影范围之内。在另一些示例中凹槽212和开孔211的形状可包括圆柱，凹槽212的直径大于开孔211的直径。如此，在形成凹槽212时，可降低凹槽212与开孔211的对准难度，减少出现凹槽212与开孔211无法连通的现象，提高封装壳体的制备良率。
在一些实施例中，结合图3c至图3e所示，在垂直于z方向的投影面上，承载体220的投影面积大于或者等于基板210的投影面积，即在z方向上，承载体220可完全覆盖基板210形成有开孔211的第一表面。以此，承载体220可以更好对基板210形成有开孔211的第一表面进行保护以及密封，更有利于基板210的真空吸附，提高封装壳体的制备良率。
参照图3f所示，基板210的第二表面与承载层231的固定方式可以包括：粘贴、真空吸附或者静电吸附。
在一些示例中，承载层231可包括具有粘性的薄膜，该薄膜的另外一个表面还可与其他设备粘贴。执行S700时，可将该薄膜从基板210上撕下，以形成如图3h所示的封装壳体200。
在一些示例中，承载层231还可包括真空吸附元件或者静电吸附元件。在执行S700时，可使承载层231与基板210脱吸附，以分离承载层231与基板210。
本公开实施例，采用承载层231固定基板210，可减少需要进行晶圆键合工艺的次数，降低制备成本。进一步地，相较于晶圆键合的固定工艺，本公开实施例中的承载层231更容易去除，在达到保护基板210形成有凹槽212的第二表面的同时，利于执行S700，提高封装壳体的制备良率。
参照图3f所示，执行S500后，承载层231位于承载体220之上。参照图3g所示，执行S600时，可用人工或者利用其他设备吸附固定承载层231的一侧的方式，进而翻转固定在承载层另一侧的基板210，使承载体220位于承载 层231之上，便于去除承载体220。可采用加热解键合的方法，使承载体220与基板210分离。
在一些实施例中，承载体220与基板210解键合后，承载体220经过清洗和抛光后还可继续循环使用。
在一些实施例中，图3h中封装壳体200可用于半导体芯片的封装，凹槽212和开孔211的尺寸较微小，可包括微米级，甚至是纳米级。
在一些实施例中，半导体芯片设置与凹槽212中，与封装壳体200进行固定，半导体芯片从开孔211中显露。半导体芯片可以包括光电芯片，或者包括感光器件，开孔211可作为光通路，用于光信号的传输。在另外一些实施例中，还可在开孔211中形成导电插塞，与半导体芯片耦接，将半导体芯片的电信号引出，用于与外部集成电路进行电信号互联。
本公开实施例，在基板的第一表面形成开孔后，将基板的第一表面与承载体键合，承载体覆盖开孔。因为承载体对开孔的覆盖，所以可以通过承载体对基板进行真空吸附，进而便于在基板的第二表面形成与开孔连通凹槽，减少真空吸附失败导致基板碎片的几率，提高封装壳体的制备良率。并且，在承载体与基板形成有开孔的第一表面键合之后，在基板的传递过程以及形成凹槽等制备过程中，承载体与直接设备接触，减少基板第一表面的损伤。
本公开实施例，在一个基板上制备出相互连通(在垂直于基板的方向上连通)的凹槽和开孔。相较于在不同基板上分别形成凹槽和开孔，再通过键合工艺将两块基板键合在一起的制备方法，本公开实施例减少基板的键合次数，省略凹槽和开孔在键合时的对准工艺，减少封装壳体在使用过程中因为基板解键合而导致封装壳体裂片失效的风险，提高封装壳体良率。
在一些实施例中，在执行S200之前，所述方法还包括：
参照图4a所示，形成覆盖第一表面的介质层241；其中，介质层241中嵌设有电连接结构242；
结合图4b和图4c所示，开孔211包括连通的第一子孔211a和第二子孔211b；在基板210的第一表面形成开孔211，包括：
参照图4b所示，在开孔211的预设形成位置，对介质层241进行第一蚀刻，直至显露基板210，以形成第一子孔211a；
参照图4c所示，对第一子孔211a底部进行第二蚀刻，以贯穿部分厚度的基板210，形成第二子孔211b；其中，第二子孔211b的底部位于基板210中。
需要强调的是，图4c中示出的位于第一子孔211a与第二子孔211b之间的虚线，仅是用于更加直观的区分本实施例的第一子孔211a与第二子孔211b的区域。在封装壳体的实际制备过程中，并不存在该虚线。
示例性的，介质层241的组成材料包括但不限于：氧化硅、氮化硅或者氮氧化硅等绝缘材料。
示例性的，介质层241的形成工艺可以包括本技术领域所知的任何工艺，例如低温化学气相沉积工艺、低压化学气相沉积工艺、快速热化学气相沉积工艺、原子层沉积工艺或者等离子体增强化学气相沉积等。
示例性的，第一蚀刻和第二蚀刻包括但不限于：干法蚀刻、湿法蚀刻或者其任意组合。
示例性的，电连接结构242可以包括但不限于：导电的焊盘、导电线、布线层或者其任意组合。电连接结构242的组成材料包括但不限于：铜、钨、铝、金、钛或者镍等。本公开对于电连接结构242的数量不作限制，例如1个或者多个导电焊盘、一个布线层或者多个堆叠的布线层。
参照图4a所示，电连接结构242形成于介质层241内，介质层241包围电连接结构242，对电连接结构242进行支撑，减少电连接结构242的损伤，也可在电连接结构242之间形成电绝缘，减少短路现象。
电连接结构242的尺寸微小，可包括微米级，甚至是纳米级，可用于与半导体芯片耦接，或用于与其他半导体结构(或者半导体器件)耦接。
在一些实施例中，电连接结构242可用作封装壳体的引线结构，在半导体芯片封装的过程中与半导体芯片形成耦接，将半导体芯片的电信号引出，与外部集成电路进行电信号互联。在另外一些实施例中，电连接结构242还可与其他电子元件耦接，在封装壳体上集成更多的功能。
在一些实施例中，S100中的基板210可为晶圆，电连接结构242可在该晶圆上提前形成，电连接结构242可以包括多个焊盘、多个导电线等相互耦接的导电结构。需要强调的是，在执行S200时，开孔211并不会贯穿、破坏这些导电结构。例如，在导电结构之间的缝隙中形成开孔211。
在另外一些实施例中，基板210还可以为包括半导体结构的晶圆(半导体结构未在本实施例附图中示出)，半导体结构可包括CMOS电路、存储器器件、光电器件或者通讯器件等。电连接结构242在晶圆上形成，与半导体结构耦接，可在制备完成的封装壳体上集成更多的功能。
结合图4b和图4c所示，在z方向上，介质层241与基板210的厚度较大，一次蚀刻形成贯穿介质层241、贯穿部分厚度基板210的开孔211的工艺难度较大，不利于保持开孔211的整体形貌良好。本公开实施例中，通过两次蚀刻形成开孔211，可降低蚀刻工艺难度，有利于蚀刻工艺窗口的扩大。
在一些实施例中，介质层241和基板210的组成材料不相同，在不同材料中一次蚀刻成孔，蚀刻的难度较大，难以控制开孔211的形貌良好。
例如，介质层241为氧化硅，基板210为硅。在执行第一蚀刻的过程中，氧化硅的蚀刻速率大于硅的蚀刻速率，或者第一蚀刻基本不蚀刻硅。在执行第二蚀刻的过程中，硅的蚀刻速率大于氧化硅的蚀刻速率，或者第二蚀刻基本不蚀刻氧化硅。
本公开实施例中，通过分步蚀刻不同的材料层，先后分步形成第一子孔211a和第二子孔211b，利于对子孔的形貌控制，以提高最终开孔211的质量，提高封装壳体的制备良率，利于蚀刻工艺窗口的扩大。
在一些实施例中，参照图4d所示，在形成第二子孔211b前，所述方法还包括：
形成覆盖第一子孔211a内壁的阻挡层243；
进行第二蚀刻包括：
对第一子孔211a底部的阻挡层243和基板210进行第二蚀刻，以贯穿第一子孔211a底部的阻挡层243以及部分厚度的基板210，形成第二子孔211b。
示例性的，阻挡层243的组成材料包括但不限于：氧化硅、氮化硅、氮氧化硅或者氧化铝等。
在执行第二蚀刻的过程中，阻挡层243的蚀刻速率小于基板210的蚀刻速率，或者第二蚀刻基本不蚀刻阻挡层243。阻挡层243可以减少第二蚀刻对第一子孔211a侧壁的蚀刻，有利于保持第一子孔211a的形貌良好，以提高最终开孔211的质量，提高封装壳体的制备良率。
在一些实施例中，参照图4e所示，S300包括：
形成开孔211后，在介质层241和/或承载体220表面形成黏接层251，通过黏接层251键合介质层241和承载体220。
黏接层251的组成材料包括但不限于：键合胶、光敏胶(又叫UV胶或者紫外线固化胶)或者具有粘性的树脂等。
本实施例的基板210上的介质层241与承载体220之间通过黏接层251进行键合，例如在介质层241和/或承载体220表面涂布键合胶，通过键合胶键合基板210和承载体220。
在一些实施例中，黏接层251可不对开孔211进行填充。例如，将键合胶涂布到承载体220的表面，再将承载体220涂布有键合胶的表面与基板210具有介质层241的表面进行键合，键合胶不会对开孔211进行填充。
在另外一些实施例中，黏接层251形成时，黏接层251可以对开孔211进行填充。例如，将键合胶涂布到介质层241形成有开孔211的表面，键合胶可同时对开孔211进行填充。
相较于直接将基板210的介质层241与承载体220直接进行热压键合的工艺，黏接层251可以在相对低温环境中实现键合，减少高温对基板210的损伤，有利于降低制备成本。并且，在执行S600过程中，通过对黏接层251进行加热即可使得黏接层251减少或者失去粘性，从而使得基板210和承载体220分离，减少去除承载体220时对基板210的损伤，降低制备难度，提高封装壳体的制备良率。
在一些实施例中，参照图4f所示，在形成黏接层251之前，所述方法还包 括：
在开孔211中形成填充物252；其中，填充物252至少闭合开孔211的开口。
填充物252的组成材料包括但不限于：键合胶、光敏胶、底部抗反射涂层、氧化硅、氮化硅、氮氧化硅或者金属材料等。
示例性的，填充物252的形成工艺可以包括本技术领域所知的任何工艺，例如低温化学气相沉积工艺、低压化学气相沉积工艺、快速热化学气相沉积工艺、原子层沉积工艺、等离子体增强化学气相沉积或者旋涂工艺等。
参照图4c所示，本实施例对于开孔211的数量不作限制。可以理解的是，当在基板210的第一表面形成开孔211的数量越多，基板210第一表面剩余的面积就越少，基板210第一表面可与承载体220进行键合的面积就越少，降低键合强度。本实施例在开孔211中形成填充物252，填充物252可仅闭合开孔211的开口，也可将开孔211全部填实。或者，填充物252将开孔211的开口闭合，开孔211中部或者底部的填充物252可存在气隙。填充物252闭合开孔211的开口，可增加基板210第一表面与承载体220的键合面积，提高键合强度，还可对开孔211进行支撑保护，减少开孔211变形缺陷的发生。
在一些实施例中，填充物252的组成材料与黏接层251的组成材料相同。
具体的，填充物252和黏接层251的组成材料可包括键合胶、光敏胶(又叫UV胶或者紫外线固化胶)或者具有粘性的树脂等。例如，在形成开孔211之后，在基板210的第一表面涂布键合胶以填充开孔211，键合胶至少闭合开孔211的开口。之后，继续在基板210的第一表面继续涂布键合胶，以形成覆盖基板210的第一表面的黏接层251，再键合基板210的第一表面和承载体220。如此，可减少沉积其他材料形成填充物252的步骤，降低制备成本。
可以理解的是，相较于仅在介质层241和/或承载体220表面涂布键合胶以形成黏接层251，本实施例在开孔211中填充键合胶，可对开孔211进行支撑，减少开孔211在键合过程中发生变形的几率，提高封装壳体的制备良率。
在一些实施例中，可在开孔211中填充金属以形成填充物252，相较于其他填充物252，金属填充物252具有更高的机械强度，提高对开孔211的支撑，减少开孔211发生变形的几率，提高封装壳体的制备良率。并且，在执行湿蚀刻以及清洗工艺去除金属填充物252时，金属填充物252与蚀刻剂反应生成金属离子，溶解在蚀刻剂中，使得金属填充物252被去除的效果更好，减少金属填充物252的残留，提高良率。
在一些实施例中，结合图4g和图4h所示，在去除承载体220之后，所述方法还包括：
去除黏接层251和开孔211中的填充物252。
去除黏接层251和开孔211中的填充物252的方法包括但不限于：干法蚀 刻、湿法蚀刻、清洗或者其任意组合。
在一些实施例中，黏接层251和/或填充物252中包括有键合胶、光敏胶时，可通过加热或者紫外照射后，再用湿法蚀刻、清洗去除黏接层251和开孔211中的填充物252。
在一些实施例中，参照图4g所示，S500包括：将基板210形成有凹槽212的第二表面粘贴于承载层231上，以固定第二表面和承载层231；
参照图4h和图4i所示，S700包括：在去除黏接层251和开孔211中的填充物252之后，去除承载层231。
承载层231可以是一个具有粘性的承载膜或者承载板，承载膜或者承载板的一面与基板210的第二表面粘贴以固定第二表面，实现对基板210的翻转。可以理解的是，承载膜或者承载板可设置绷膜环232，通过绷膜环232可实现基板210的翻转以及去除承载膜或者承载板。
相较于键合或者焊接等固定方式，本实施例中的粘贴固定方式工序更加简单，减少对基板210形成有凹槽212的第二表面的损伤，提高封装壳体良率。
在一些实施例中，承载膜或者承载板的两面都具有粘性，一面粘贴基板210的第二表面，另一面可粘贴于工艺设备上。
在一些实施例中，在形成凹槽212之前，所述方法还包括：
对基板210的第二表面进行减薄；其中，减薄后的基板210的厚度大于开孔211的深度。
示例性的，减薄工艺包括但不限于：干法蚀刻、湿法蚀刻、化学机械研磨、轮磨或者其任意组合。
参照图3h和图4i所示，在z方向上，封装壳体的基板210厚度包括：150微米至300微米，在具有一定的厚度以维持较好的机械性能的同时，还不至于使基板210过厚，降低集成电路的集成密度。
当基板210的厚度较厚时，例如基板210为硅晶圆时，厚度大致在775微米，需要对基板210进行减薄。本实施例可在执行S400之前，对基板210的第二表面进行减薄，使基板210的厚度达到150微米至300微米。
参照图3e所示，对基板210的第二表面减薄后，可以降低形成凹槽212的蚀刻量，降低蚀刻难度。需要强调的是，对基板210的第二表面进行减薄后，剩余基板210的第二表面不显露开孔211。
图5a至图5d是根据本公开实施例示出的一种封装芯片的制备方法的示意图。参照图5a所示，该方法包括：
提供封装壳体200；
提供半导体芯片260；
将半导体芯片260与封装壳体200固定，半导体芯片260设置在凹槽212中；其中，开孔211显露半导体芯片260的至少部分区域。
示例性的，半导体芯片260包括但不限于：数字电路芯片、模拟电路芯片、射频/微波电路芯片、微机电系统(MEMS)芯片、光子芯片以及无源电路芯片等。
示例性的，微机电系统(MEMS)芯片，包括MEMS加速度计、MEMS麦克风、微马达、微泵、微振子、MEMS压力传感器、MEMS陀螺仪、MEMS湿度传感器等芯片以及它们的集成产品。
半导体芯片260可固定于封装壳体200的凹槽212内，固定的方式可包括键合、贴合或者焊接等工艺。
微机电系统芯片中可包括微电路和微机械，其中微机械可包括一种具有机械可动结构的微电子器件，可将电信号转换为位移、速度、振动、声波等物理信号，也可将这些物理信号转换为电信号。因此，在对微机电系统芯片进行封装时，需要尽量减少外界压力对微机电系统芯片的施压，并且要为微机电系统芯片中的微机械提供密封的可动空间。
参照图5a所示，采用如图3h所示的封装壳体200对半导体芯片260进行封装。将半导体芯片260固定于凹槽212中，半导体芯片260的厚度可小于凹槽212的深度。完成半导体芯片260与封装壳体200的固定后，还可将封装盖板280与封装壳体200固定。
本实施例中的凹槽212，在封装完成后可为半导体芯片260提供一个密闭的空腔，可以为微机电系统芯片的可动部件提供可动空间。可以理解的是，对于无需可动空间的其他半导体芯片260，待半导体芯片260与封装基板210固定后，可用绝缘材料填充凹槽212，形成包覆半导体芯片260的绝缘层。
在一些实施例中，继续参照图5a所示，半导体芯片260可以包括光电芯片，或者包括感光器件。开孔211可作为光通路，用于光信号的传输，使得半导体芯片与光信号进行互联。在另外一些实施例中，开孔211可包括沿着垂直于xoz平面延伸的多个缝隙结构，多个开孔211可将基板210的第一表面分割成多条光栅，开孔211在传输光信号的同时，还可通过透射光衍射或者反射光衍射对光信号进行调试，以满足不同的半导体芯片260对于不同强度以及不同模式的光信号的需求。
在一些实施例中，参照图5b至图5d所示，半导体芯片260的一面设置有焊盘261，焊盘261从开孔211中显露；该方法还包括：
以导电材料填充开孔211，以形成与焊盘261耦接的导电插塞271。
示例性的，导电插塞271和焊盘261的形成工艺包括但不限于：物理沉积、化学沉积或者电镀等。导电插塞271和焊盘261的组成材料包括但不限于：铜、钨、铝、金、钛或者镍等导电材料。导电插塞271与焊盘261耦接，将半导体芯片260的电信号引出，用于与外部集成电路进行电信号互联。
在一些实施例中，参照图5c所示，当半导体芯片260高度较大时，可使用带有凹陷的封装盖板280以形成空腔。
在一些实施例中，参照图5d所示，可采用如图4i所示的封装壳体200对半导体芯片260进行封装，导电插塞271可通过导电结构272与电连接结构242耦接，电连接结构242将半导体芯片260的电信号引出，用以与外部集成电路进行电信号互联。导电结构272可包括柱状的或者长条状的接触插塞。
本公开实施例中的凹槽212、开孔211、焊盘261、导电插塞271、电连接结构242以及导电结构272的尺寸可包括微米级，甚至是纳米级，以满足对高集成度半导体芯片的封装，进而提高外部集成电路的集成度。
本实施例的封装壳体在封装半导体芯片时，可为半导体芯片提供空腔，在对半导体芯片进行支撑以及保护的同时，还可为具有可动部件的半导体芯片(例如，微机电系统芯片)提供可动空间，还可为不同的半导体芯片提供光信号或者电信号的互联，利于多种半导体芯片的封装，利于维持半导体芯片的功能良好。
本公开实施例，在基板的第一表面形成开孔后，将基板的第一表面与承载体键合，承载体覆盖开孔。因为承载体对开孔的覆盖，所以可以通过承载体对基板进行真空吸附，进而便于在基板的第二表面形成与开孔连通凹槽，减少真空吸附失败导致基板碎片的几率，提高封装壳体的制备良率。并且，在承载体与基板形成有开孔的第一表面键合之后，在基板的传递过程以及形成凹槽等制备过程中，承载体与直接设备接触，减少基板第一表面的损伤。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (11)

  1. 一种封装壳体的制备方法，其中，包括：
    提供基板；其中，所述基板具有相对的第一表面和第二表面；
    在所述基板的所述第一表面形成开孔；其中，所述开孔的底部位于所述基板中；
    将所述基板形成有所述开孔的所述第一表面与承载体键合；其中，所述承载体覆盖所述开孔；
    在所述第一表面与所述承载体键合之后，在所述基板的所述第二表面形成凹槽；其中，在垂直于所述基板的方向上，所述凹槽与所述开孔连通；
    将所述基板形成有所述凹槽的所述第二表面固定于承载层上；
    在所述第二表面与所述承载层固定之后，去除所述承载体；
    在去除所述承载体后，去除所述承载层。
  2. 根据权利要求1所述的方法，其中，在形成所述开孔前，所述方法还包括：
    形成覆盖所述第一表面的介质层；其中，所述介质层中嵌设有电连接结构；
    所述开孔包括连通的第一子孔和第二子孔；所述在所述基板的所述第一表面形成开孔，包括：
    在所述开孔的预设形成位置，对所述介质层进行第一蚀刻，直至显露所述基板，以形成所述第一子孔；
    对所述第一子孔底部进行第二蚀刻，以贯穿部分厚度的所述基板，形成所述第二子孔；其中，所述第二子孔的底部位于所述基板中。
  3. 根据权利要求2所述的方法，其中，在形成所述第二子孔前，所述方法还包括：
    形成覆盖所述第一子孔内壁的阻挡层；
    进行所述第二蚀刻包括：
    对所述第一子孔底部的所述阻挡层和所述基板进行所述第二蚀刻，以贯穿所述第一子孔底部的所述阻挡层以及部分厚度的所述基板，形成所述第二子孔。
  4. 根据权利要求2所述的方法，其中，所述将所述基板形成有所述开孔的所述第一表面与承载体键合，包括：
    形成所述开孔后，在所述介质层和/或所述承载体表面形成黏接层，通过所述黏接层键合所述介质层和所述承载体。
  5. 根据权利要求4所述的方法，其中，在形成所述黏接层之前，所述方法还包括：
    在所述开孔中形成填充物；其中，所述填充物至少闭合所述开孔的开口。
  6. 根据权利要求5所述的方法，其中，所述填充物的组成材料与所述黏接层的组成材料相同。
  7. 根据权利要求5所述的方法，其中，在去除所述承载体之后，所述方法还包括：
    去除所述黏接层和所述开孔中的所述填充物。
  8. 根据权利要求7所述的方法，其中，
    所述将所述基板形成有所述凹槽的所述第二表面固定于承载层上，包括：将所述基板形成有所述凹槽的所述第二表面粘贴于所述承载层上，以固定所述第二表面和所述承载层；
    所述在去除所述承载体后，去除所述承载层，包括：在去除所述黏接层和所述开孔中的所述填充物之后，去除所述承载层。
  9. 根据权利要求1所述的方法，其中，在形成所述凹槽之前，所述方法还包括：
    对所述基板的所述第二表面进行减薄；其中，减薄后的所述基板的厚度大于所述开孔的深度。
  10. 一种封装芯片的制备方法，其中，包括：
    提供如权利要求1至9任意一项所述的方法制备的封装壳体；
    提供半导体芯片；
    将所述半导体芯片与所述封装壳体固定，所述半导体芯片设置在所述凹槽中；其中，所述开孔显露所述半导体芯片的至少部分区域。
  11. 根据权利要求10所述的方法，其中，所述半导体芯片的一面设置有焊盘，所述焊盘从所述开孔中显露；所述方法还包括：
    以导电材料填充所述开孔，以形成与所述焊盘耦接的导电插塞。
PCT/CN2022/102669 2022-03-22 2022-06-30 封装壳体的制备方法及封装芯片的制备方法 WO2023178874A1 (zh)

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