WO2023173930A1

WO2023173930A1 - Topcon cell and preparation method therefor

Info

Publication number: WO2023173930A1
Application number: PCT/CN2023/072532
Authority: WO
Inventors: 张东威; 袁陨来; 叶枫; 王建波; 吕俊
Original assignee: 西安隆基乐叶光伏科技有限公司
Priority date: 2022-03-15
Filing date: 2023-01-17
Publication date: 2023-09-21
Also published as: CN114744054A

Abstract

Disclosed in the embodiments of the present application are a TOPCon cell and a preparation method therefor. The TOPCon cell comprises a silicon substrate, and a diffusion layer and a first electrode which are located on the front surface of the silicon substrate, the first electrode comprising a plurality of fingers. A plurality of finger reserving areas distributed corresponding to the fingers are arranged on the diffusion layer. First passivation contact structures are provided in the finger reserving areas, each first passivation contact structure comprising a first tunneling oxide layer and a first doped silicon layer which are sequentially arranged in the direction away from the silicon substrate. The cell of the present application can reduce carrier recombination of a metal contact area while reducing parasitic light absorption of the doped silicon layers and reducing current loss, thus increasing the open-circuit voltage and conversion efficiency of the cell.

Description

A TOPCon battery and its preparation method

This application claims priority to the Chinese patent application filed with the China Patent Office on March 15, 2022, with the application number 202210255501.9 and the invention title "A TOPCon battery and its preparation method", the entire content of which is incorporated into this application by reference. middle.

Technical field

This application relates to the technical field of solar cells, and specifically to a TOPCon cell and its preparation method.

Background technique

Among the many factors that affect the photoelectric conversion efficiency of solar cells, the recombination at the contact between metal electrodes and crystalline silicon has become a key factor affecting the efficiency of solar cells. Tunnel Oxide Passivated Contact solar cell (TOPCon) solar cell is one of the most promising solar cells at present. Its tunnel oxide passivated contact structure consists of an ultra-thin tunnel oxide layer It is composed of a doped silicon layer, which can significantly reduce the recombination in the metal contact area while maintaining good contact performance.

However, most of the current TOPCon structures are used on the backside of solar cells.

Contents of the invention

The front surface of the TOPCon battery adopts a traditional battery structure, which results in great limitations in reducing carrier recombination and limits the further improvement of conversion efficiency.

One purpose of this application is to provide a TOPCon cell with a TOPCon structure in a local area on the front side of a silicon substrate, in order to achieve excellent photoelectric conversion efficiency while reducing front-side parasitic absorption.

Another purpose of this application is to provide a method for preparing a TOPCon battery, which can conveniently form a TOPCon structure in a target area, thereby improving battery efficiency.

The purpose of the present application is not limited to the above-mentioned purpose. Other purposes and advantages of the present application not mentioned above can be understood from the following description and more clearly understood through the implementation of the present application. Furthermore, it is easily understood that the present invention can be implemented by the features disclosed in the claims and their combinations. please the purpose and advantages.

In the first aspect, according to the embodiment of the present application, the present application proposes a TOPCon battery, including:

A silicon substrate, a diffusion layer and a first electrode located on the front side of the silicon substrate, the first electrode including a plurality of thin gate lines;

The diffusion layer is provided with a plurality of gate line preset areas distributed correspondingly to the fine gate lines. A first passivation contact structure is provided in the gate line preset area. The first passivation contact structure includes an edge along the A first tunnel oxide layer and a first doped silicon layer are arranged sequentially in a direction away from the silicon substrate.

In some embodiments, the cross-sectional shape of the gate line preset area perpendicular to its extension direction is an inverted pyramid shape, and the cross-sectional shape of the first passivation contact structure is consistent with the gate line preset area. to match the cross-sectional shape.

In some embodiments, the gate line preset area includes a groove formed on the diffusion layer, the first passivation contact structure is formed along with the groove, and the thin gate lines overlap in said groove and in ohmic contact with said first passivation contact structure;

Optionally, the cross-sectional shape of the groove is an inverted pyramid, a concave arc, a triangle or a quadrilateral.

In some embodiments, the first tunnel oxide layer is a silicon oxide film with a thickness of 1.3 to 1.7 nm;

And/or, the thickness of the first doped silicon layer is 110-130 nm.

In some embodiments, the TOPCon battery further includes:

A second passivation contact structure is formed on the back side of the silicon substrate. The second passivation contact structure includes a second tunnel oxide layer and a second doped silicon layer sequentially arranged in a direction away from the silicon substrate. .

In some embodiments, the TOPCon battery further includes:

A front-side passivation layer formed on the surface of the diffusion layer facing away from the silicon substrate and covering the first passivation contact structure;

A back passivation layer formed on the surface of the second doped silicon layer facing away from the silicon substrate;

The first electrode penetrates the front passivation layer and forms ohmic contact with the diffusion layer;

Optionally, the front-side passivation layer is one or more stack combinations of SiO _x layer, AlO _x layer, SiN _x layer, SiON _x layer;

Optionally, the back passivation layer is one or two stacked layers of SiN _x layer and SiON _x layer. combine.

In some embodiments, the front side of the silicon substrate is a pyramid-shaped textured surface;

And/or, the back side of the silicon substrate is a polished surface.

In the second aspect, according to the embodiments of the present application, the present application proposes a method for preparing a TOPCon battery as described above, including:

Form a diffusion layer and a borosilicate glass layer on the front side of the silicon substrate in sequence;

Make grooves on the silicon substrate at preset positions corresponding to the thin gate lines to form preset gate line areas that penetrate the borosilicate glass layer;

A first passivation contact structure is formed in the gate line preset area, and the first passivation contact structure includes a first tunnel oxide layer and a first doped silicon layer sequentially arranged in a direction away from the silicon substrate. .

In some embodiments, forming a groove on the silicon substrate at a predetermined position corresponding to the thin gate line to form a preset gate line area penetrating the borosilicate glass layer includes:

The preset gate line area is formed by using a laser to make grooves on the silicon substrate at preset positions corresponding to the fine gate lines.

In some embodiments, the gate line preset area extends downward to form a groove on the diffusion layer while penetrating the borosilicate glass layer, and the first passivation contact structure follows the A groove is formed, and the surface of the first passivation contact structure is closer to the center of the silicon substrate than the surface of the borosilicate glass layer;

Optionally, in some embodiments, after forming the gate line preset area, the method further includes: modifying the front surface of the silicon substrate after the trenching to remove damage on the front surface of the silicon substrate. layer and modify the surface of the gate line preset area;

Optionally, the modification includes soaking the front side of the silicon substrate with 0.8-1.2wt% alkali solution at 70-90°C;

Optionally, in some embodiments, after forming the first passivation contact structure in the gate line preset area, the method further includes: forming a second passivation contact structure on the back side of the silicon substrate, and the third passivation contact structure is formed on the back side of the silicon substrate. The second passivation contact structure includes a second tunnel oxide layer and a second doped silicon layer sequentially arranged in a direction away from the silicon substrate;

Optionally, in some embodiments, after forming the second passivation contact structure on the back side of the silicon substrate, the method further includes: preparing a front passivation layer on the surface of the diffusion layer; A back passivation layer is prepared on the surface of the silicon layer.

The technical solutions provided by the embodiments of this application may include the following beneficial effects:

The TOPCon cell provided by the embodiment of the present application has a passivation contact structure including a first tunnel oxide layer and a first doped silicon layer between the silicon substrate and the front fine gate line, thereby reducing the impact of the doped silicon layer on light. Parasitic absorption can reduce current loss while reducing carrier recombination in the metal contact area, improving the open circuit voltage and conversion efficiency of the battery.

The preparation method disclosed in this application realizes the preparation of the target area passivation contact structure by preforming the gate line preset area, simplifies the process steps, reduces the production cost, and is suitable for industrial production.

Description of the drawings

In order to more clearly explain the embodiments of the present application or the technical solutions in the prior art, the following will briefly introduce the drawings that need to be used in the description of the embodiments or the prior art. Obviously, the drawings in the following description These are some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without exerting creative efforts.

Figure 1 is a schematic structural diagram of a TOPCon battery according to an embodiment of the present application.

Specific embodiments

The present application will be further described in detail below in conjunction with examples. It can be understood that the specific embodiments described here are only used to explain the relevant invention, but not to limit the invention.

It should be noted that, as long as there is no conflict, the embodiments and features in the embodiments of this application can be combined with each other.

It should be noted that the endpoints of ranges and any values disclosed herein are not limited to such precise ranges or values, and these ranges or values should be understood to include values approaching these ranges or values. For numerical ranges, the endpoint values of each range, the endpoint values of each range and individual point values, and the individual point values can be combined with each other to obtain one or more new numerical ranges. These values The scope shall be deemed to be specifically disclosed herein.

If specific techniques or conditions are not specified in the examples, the techniques or conditions described in literature in the field or product instructions will be followed. If the manufacturer of the reagents or instruments used is not indicated, they are all conventional products that can be purchased commercially.

In the description of this specification, reference to the description of the terms "one embodiment,""someembodiments,""examples,""specificexamples," or "some examples" or the like is intended to mean that the specific embodiment or examples are described in connection with the description. Features, structures, materials or characteristics are included in at least one embodiment or example of the present application. In this specification, the schematic expressions of the above terms are not necessarily directed to the same embodiment or example. Furthermore, the specific features, structures, materials or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, those skilled in the art may combine and combine different embodiments or examples and features of different embodiments or examples described in this specification unless they are inconsistent with each other.

Tunnel Oxide Passivated Contact (TOPCon) cells can effectively reduce recombination losses and improve cell photoelectric conversion efficiency. Its excellent passivation performance mainly comes from two aspects. One is the chemical passivation provided by the ultra-thin SiOx layer. The other is the field passivation effect provided by the doped poly-Si layer. Specifically, the ultra-thin SiOx layer has selective transmission to carriers. Many carriers can penetrate this passivation layer, while minority carriers is blocked. Based on this, by forming a metal electrode on the passivation contact structure, a passivation contact without opening a hole can be obtained. At this time, the metal electrode can collect the majority carriers that penetrate the ultra-thin silicon oxide layer and the doped silicon layer, and the minority carriers blocked in the passivation contact structure cannot recombine with the majority carriers in the metal contact area, so that the majority carriers can be collected. Reduce recombination rate.

Compared with the crystalline silicon emitter, the doped silicon layer has a larger absorption coefficient in the visible light band. If it is used in the front window layer of the battery, it will produce parasitic absorption and reduce the short-circuit current. Therefore, the existing TOPCon structure is mostly used as a non-conductor. The back surface field of the battery on the light-receiving surface is rarely used on the front (i.e., the light-receiving surface). At this stage, the continuous increase in market demand has put forward higher requirements for solar cells, and the compounding of the metal contact area on the front of the battery has seriously restricted the further improvement of solar cell efficiency. How to appropriately apply the TOPCon structure to the front of the battery is expected to gain Solar cells with further improved efficiency.

In view of this, please refer to Figure 1. This application proposes a TOPCon battery, including a silicon substrate 10, a diffusion layer 20 located on the front side of the silicon substrate, and a first electrode. The first electrode includes a plurality of fine gate lines. 301;

The diffusion layer 20 is provided with a plurality of gate line preset areas 40 distributed corresponding to the thin gate lines 301. A first passivation contact structure 50 is provided in the gate line preset area 40. The first passivation contact structure 50 is provided in the gate line preset area 40. The contact structure 50 includes a first tunnel oxide layer and a first doped silicon layer sequentially arranged in a direction away from the silicon substrate 10 .

The TOPCon cell of this embodiment improves the front side of the silicon substrate 10 by arranging gate line preset areas 40 on the diffusion layer 20 and forming the first passivation contact structure 50 on these gates corresponding to the thin gate lines 301 Within the line preset area 40, the direct contact between metal and silicon can be eliminated, thereby reducing metal contact. Regional carrier recombination improves the photoelectric conversion efficiency and open circuit voltage of the battery. Among them, since the first passivation contact structure 50 only exists in a local area corresponding to the thin gate line 301, this reduces the area ratio of the passivation contact structure on the front of the battery, thereby significantly reducing the parasitic effect of the doped silicon layer on light. Absorb and reduce current loss, thereby increasing the short-circuit current of the battery.

In addition, the TOPCon battery of this embodiment preforms the gate line preset area 40, which on the one hand improves the accuracy of forming the first passivation contact structure 50 in the target area, and on the other hand reduces the cost of forming the first passivation structure in the target area. The process complexity and cost of the contact structure 50 are eliminated. For example, there is no need to grow the first passivation contact structure on the entire surface of the diffusion layer 20 and then remove the non-target area passivation contact structure through a mask to obtain a passivation contact structure only in the target area. of battery.

Wherein, preferably, the gate line preset area 40 extends along the printed circuit of the fine gate lines 301, that is, extends along the length direction of the fine gate lines, wherein the number of the thin gate lines 301 is different from the gate line preset area 40. Correspondingly, the number of fine gate lines 301 is 20-500. More preferably, the number of fine gate lines 301 is 80-200. The fine grid lines 301 can be straight lines, curves, arcs, waves, polygonal lines, etc. The shape of the grid line preset area 40 preferably corresponds to the thin grid lines, and its implementation is not limited to that described in this application. Give examples.

Among them, the type of silicon substrate 10 is not specifically limited in this application and can be selected by oneself. For example, the silicon substrate 10 may be a P-type silicon substrate or an N-type silicon substrate. In order to make TOPCon cells have higher efficiency, N-type silicon substrate is preferred. In the embodiments of this application, an N-type silicon substrate is taken as an example for explanation.

Among them, the diffusion layer 20 is made by diffusing boron on the silicon substrate 10 to obtain a P+ emitter layer with a sheet resistance of 190-210Ω/sq. During the process of diffusion to form the diffusion layer 20, a layer of borosilicate glass layer (BSG layer) with a certain thickness will spontaneously grow on the surface of the diffusion layer 20. This layer is mainly a boron-rich silicon dioxide layer with an impurity content of More will affect battery efficiency. In conventional solar cell preparation processes, the borosilicate glass layer needs to be removed to avoid affecting cell quality. In the embodiment of the present application, it is preferred that the gate line preset area 40 penetrates the borosilicate glass layer on the surface of the diffusion layer 20 so that the fine gate line 301 can form good ohmic contact with the diffusion layer 20 . In the non-target areas that do not correspond to the fine gate lines 301, the borosilicate glass layer on the surface of the diffusion layer 20 is removed by appropriate methods commonly used in this field.

The materials and thicknesses of the first tunnel oxide layer and the first doped silicon layer can be set according to actual application scenarios. For example, the first tunnel oxide layer may be a silicon oxide film, such as a silicon monoxide film, a silicon dioxide film, or a stack of both. The above-mentioned first doped silicon layer can be a doped amorphous silicon layer or a doped polysilicon layer, preferably a doped polysilicon layer, the doping element is preferably boron, and the sheet resistance is between 70 and 90Ω/sq, preferably 80Ω/sq. sq.

Further, in some embodiments, please refer to FIG. 1 , the cross-sectional shape of the gate line preset area 40 perpendicular to its extension direction is an inverted pyramid shape, and the lateral shape of the first passivation contact structure 50 is The cross-sectional shape is adapted to the cross-sectional shape of the gate line preset area 40 .

When other factors are equal, the first passivation contact structure 50 having an inverted pyramid cross-sectional shape has a larger side area, thereby increasing the area of the electrode formed above it, thereby increasing the distance between the electrode and the silicon substrate. The contact area is reduced, thereby reducing the contact resistance between the electrode and the silicon substrate, which helps the electrode collect more majority carriers and reduces the series resistance. It can be understood that the cross-sectional shape of the grid line preset area 40 is not limited to an inverted pyramid shape, and may be a concave arc shape, a triangle or a quadrilateral (such as a rectangle or a trapezoid), etc., which is not limited in this application.

Further, in some embodiments, the gate line preset area includes a groove formed on the diffusion layer, the first passivation contact structure is formed along with the groove, and the fine gate wires are stacked in the grooves and in ohmic contact with the first passivation contact structure;

In this embodiment, when the thin gate line 301 is stacked in the groove, the bottom surface and the side surface of the first passivation contact structure 10 facing the thin gate line 301 can be in contact with the thin gate line 301 at the same time, thereby increasing the The contact area between the electrode and the first passivation contact structure 50 improves the passivation effect.

Further, in some embodiments, the first tunnel oxide layer is a silicon oxide film, preferably a silicon dioxide film, and has a thickness of 1.3 to 1.7 nm, preferably 1.5 nm;

And/or, the thickness of the first doped silicon layer is 110-130 nm, preferably 120 nm.

The passivation effect is closely related to the thickness of the first tunnel oxide layer and the first doped silicon layer. For example, when the first tunnel oxide layer is very thin, it is not enough to hinder the transmission of minority carriers, and the interface passivation effect is poor. When the first tunnel oxide layer exceeds the critical thickness of 1.7nm, tunneling of majority carriers This will not be possible because a large number of photogenerated carriers will recombine at the interface, resulting in a sharp decline in the photoelectric conversion efficiency of the battery. The larger the thickness of the doped silicon layer, the more serious the absorption of light. However, if the thickness is too thin, the doped elements (such as boron and phosphorus) will be injected into the silicon substrate, resulting in increased defects and increased recombination.

Further, in some embodiments, please refer to FIG. 1 , the TOPCon battery further includes: a second passivation contact structure 60 formed on the back side of the silicon substrate 20 , the second passivation contact structure 60 . The contact structure 60 includes a second tunnel oxide layer and a second doped silicon layer sequentially arranged in a direction away from the silicon substrate.

In this embodiment, the second passivation contact structure 60 covers the battery back surface field, which can significantly reduce battery back surface recombination. The composition and thickness of the second tunnel oxide layer are the same as those of the first tunnel oxide layer. The second doped silicon layer can be a doped amorphous silicon layer or a doped polysilicon layer, preferably a doped polysilicon layer. The element is preferably phosphorus, and the square resistance is between 70 and 90Ω/sq, preferably 80Ω/sq.

Further, in some embodiments, please refer to Figure 1, the TOPCon battery further includes:

A front passivation layer 70 is formed on the surface of the diffusion layer 20 facing away from the silicon substrate 10 and covers the first passivation contact structure 50;

A back passivation layer 80 is formed on the surface of the second doped silicon layer facing away from the silicon substrate 10;

The first electrode penetrates the front passivation layer 70 and forms ohmic contact with the diffusion layer 20;

Optionally, the front passivation layer 70 is one or a combination of several stacked layers selected from the group consisting of SiOx layer, AlOx layer, SiNx layer, and SiONx layer;

Optionally, the backside passivation layer 80 is one or a stack combination of SiNx layer and SiONx layer.

Among them, in the preferred embodiment of the present application, the front passivation film 70 is composed of an AlOx layer and a SiNx layer stacked from the inside out, and the thickness can be 50-200 nm. The back passivation layer 80 is a SiNx layer, and the thickness can be 50 nm. -200nm.

Further, in some embodiments, please refer to FIG. 1 , the front side of the silicon substrate 10 is a pyramid-shaped textured surface, and the back side of the silicon substrate 10 is a polished surface.

Alkaline texturing or reactive ion etching technology can be used to form a pyramid-shaped texturing surface on the front side of the silicon substrate 10. This textured surface structure can play a role in trapping light and reduce the reflection of light by solar cells, making more The light can be refracted into the solar cell, improving the utilization rate of light energy by the solar cell.

According to the embodiments of the present application, the present application also proposes a method for preparing the TOPCon battery as described above, including:

A diffusion layer 20 and a borosilicate glass layer are sequentially formed on the front side of the silicon substrate 10;

Make grooves on the silicon substrate at the preset positions of the thin gate lines 301 to form preset gate line areas 40 that penetrate the borosilicate glass layer;

A first passivation contact structure 50 is formed in the gate line preset area 40 . The first passivation contact structure 50 includes a first tunnel oxide layer and a first tunnel oxide layer sequentially arranged in a direction away from the silicon substrate 10 . Doped silicon layer.

Among them, this application does not specifically limit the method of preparing the diffusion layer 20. For example, it can be carried out by boron diffusion. The boron diffusion can be promoted by ion implantation, thermal diffusion or doping source coating. The user can proceed according to actual needs. The choice of method and the selection of corresponding preparation conditions. Further, the square resistance range of the diffusion layer is controlled to be 190-210Ω/sq, including the endpoint value. The borosilicate glass layer will spontaneously grow on the surface of the diffusion layer 20 away from the silicon substrate 10 during the diffusion process to form the diffusion layer 20, and its thickness is related to the boron diffusion process.

In this embodiment, grooves are made in advance at the preset positions for stacking the fine grid lines 301 to remove the BSG layer corresponding to the preset positions to form a preset gate line area. The groove pattern matches the fine grid line screen printing image. consistent. In this case, since there is no BSG layer at the electrode contact position, the preparation of the first passivation contact structure 50 is facilitated.

Among them, this application does not specifically limit the method of grooving, and it can be laser etching, physical etching, chemical etching, etc.

Among them, this application does not specifically limit the method of preparing the first passivation contact structure 50, and you can choose it yourself. For example, prepare a first tunnel oxide layer in the gate line preset area 40, and then prepare the first tunnel oxide layer away from the silicon. A first silicon layer is prepared on the surface of the substrate, and the first silicon layer is doped to form the first doped silicon layer (N-Poly).

Optionally, preparing the first tunnel oxide layer in the gate line preset area 40 includes:

The first tunnel oxide layer is prepared in the gate line preset area using any one of high-temperature thermal oxidation methods, nitric acid oxidation methods, ozone oxidation methods, and chemical vapor deposition methods.

The first tunnel oxide layer is a silicon dioxide layer with a thickness of 1.3 to 1.7 nm.

Optionally, a low pressure chemical vapor deposition method, a plasma enhanced chemical vapor deposition method, or the like may be used to prepare the first silicon layer on the surface of the first tunnel oxide layer facing away from the silicon substrate.

Optionally, doping the first silicon layer, and forming the first doped silicon layer includes: doping the first silicon layer using a diffusion method, an ion implantation method, or a laser doping method, The first doped silicon layer is formed. The doping element may be boron, and the square resistance of the first doped silicon layer is between 70 and 90Ω/sq.

It should be pointed out that during diffusion, a diffusion layer and a surrounding borosilicate glass layer will be formed on the back side of the silicon substrate 10. Therefore, after diffusion, a chain cleaning equipment is required and an acidic cleaning solution is used to remove the back diffusion. layer and surrounding borosilicate glass layer. Specifically, the above-mentioned acidic cleaning solution can be any acidic solution capable of removing the back diffusion layer and the surrounding borosilicate glass layer. For example, the acidic cleaning solution can be hydrofluoric acid, or a mixture of hydrofluoric acid and inorganic acid (such as nitric acid, sulfuric acid). The concentration and liquid level of the above-mentioned acidic cleaning solution, as well as the process conditions when using the acidic cleaning solution to remove the back diffusion layer and the borosilicate glass layer, can be set according to actual needs, as long as it can be applied to the solar energy provided by the embodiment of the present invention. Any method of manufacturing the battery can be used. For example: when removing the back diffusion layer, when the acidic cleaning solution is a mixture of hydrofluoric acid, nitric acid and sulfuric acid, HF: _HNO3 : _H2SO4 =54: ₁₆₅ :38 (volume ratio), temperature 25±2 ℃, etching amount 0.4±0.05g, back reflectivity 35±2%.

Further, in some embodiments, forming a groove on the silicon substrate at a preset position corresponding to the thin gate line 301 to form a preset gate line area 40 penetrating the borosilicate glass layer includes:

The gate line preset area 40 is formed on the silicon substrate at a preset position corresponding to the thin gate line 301 by using a laser.

Optionally, set the laser power to 10~50W and the frequency to 20000~60000Hz. The groove pattern is consistent with the fine grid line pattern. After removing the surface BSG corresponding to the pattern area, the laser simultaneously burns the underlying silicon to form Inverted pyramid grid line preset area 40.

Compared with existing methods, such as the photolithography method, the method of forming the gate line preset area 40 in this embodiment avoids the process steps of printing acid and alkali-resistant slurry, masking, photolithography, etc. This method has a simple implementation process and short preparation time. It is short, only needs to add a laser step, does not introduce additional chemical pollution, has low cost, high alignment accuracy, and is easy to achieve mass production.

Further, in some embodiments, the gate line preset area 40 extends downward to form a groove on the diffusion layer 20 while penetrating the borosilicate glass layer. , the first passivation contact structure 50 is formed along with the groove, and the surface of the first passivation contact structure 50 is closer to the center of the silicon substrate 10 than the surface of the borosilicate glass layer.

In this embodiment, the gate line preset area 40 includes a groove on the diffusion layer 20 , and a first passivation contact structure 50 is formed along with the groove, where the first passivation contact structure 50 faces away from the silicon. The surface of the substrate 10 is lower than the surface of the borosilicate glass layer facing away from the silicon substrate 10. At this time, when the fine gate lines 301 are stacked in the groove, the first passivation contact structure 10 faces the fine gate. The bottom and sides of line 301 can be When in contact with the thin gate line, the contact area between the electrode and the first passivation contact structure 50 can be increased, and the contact area between the electrode and the silicon substrate 10 mediated by the first passivation contact structure 50 can be increased, thereby improving the Passivating effect.

Further, in some embodiments, after forming the gate line preset area 40, it also includes:

Modify the front surface of the grooved silicon substrate 10 to remove the damage layer on the front surface of the silicon substrate 10 and modify the surface of the gate line preset area 40;

Optionally, the modification includes soaking the front side of the silicon substrate 10 with 0.8-1.2 wt% alkali solution at 70-90°C.

For example, during the process of laser burning to remove the BSG layer to form the gate line preset area 40, since the BSG layer is thin, the silicon under the BSG layer will inevitably be burned, causing damage. The above-mentioned alkali solution can be Any alkaline solution that can remove the damaged layer and round the edges and corners of the gate line preset area 40, such as an inverted pyramid shape, is beneficial to improving battery quality. For example: the alkali solution can be potassium hydroxide, sodium hydroxide or a mixture thereof. In one embodiment, the alkaline solution is a mixture of water, potassium hydroxide and texturing additives. Among them, the above-mentioned texturing additive can be any texturing additive that can adjust the transverse and longitudinal corrosion rates of potassium hydroxide. For example: the texturing additive can be the texturing additive model TS55 provided by Changzhou Shichuang Energy Technology Co., Ltd. Under the above circumstances, during the etching and cleaning process of the gate line preset area 40 with potassium hydroxide in an alkali solution, the texturing additive can adjust the longitudinal and transverse corrosion rates of the potassium hydroxide, so that the gate line preset area 40 is modified after modification. The inverted pyramid structure of the area 40 is more regular and uniform, which is conducive to obtaining a more regular and uniform first passivation contact structure in the gate line preset area 40, thereby allowing all electrodes located above the gate line preset area 40 to be in contact with the silicon There is a large contact area between the substrates, which facilitates the collection of majority carriers by each of the above electrodes, further improving the photoelectric conversion efficiency of the solar cell.

The volume ratio of water, potassium hydroxide and texturing additive in the alkali solution can be: 354:5.5:2. At this time, the corrosion intensity of potassium hydroxide in the alkali solution for corrosion cleaning is moderate. In addition, the above-mentioned processing conditions when using an alkali solution to modify the front side of the silicon substrate can also be set according to actual needs. For example: the above treatment conditions can be that the temperature of the alkali solution is 70°C to 90°C, and the process time is 100 to 150s. Under the above circumstances, the damaged layer can be completely removed and a regular and uniform inverted pyramid-shaped gate line preset area 40 can be obtained, ensuring a good repair effect.

Further, in some embodiments, after forming the first passivation contact structure 50 in the gate line preset area 40, the following steps are also included:

A second passivation contact structure 60 is formed on the back side of the silicon substrate 10 . The second passivation contact structure 60 includes a second tunnel oxide layer and a second doped silicon sequentially arranged in a direction away from the silicon substrate 10 . layer.

Among them, this application does not specifically limit the method of preparing the second passivation contact structure 60, and you can choose it yourself. For example, prepare a second tunnel oxide layer on the back side of the silicon substrate 10, and then form a second tunnel oxide layer on the back side of the second tunnel oxide layer. A second silicon layer is prepared on the surface of the silicon substrate, and the second silicon layer is doped to form the second doped silicon layer (P-Poly).

Optionally, preparing the second tunnel oxide layer on the back side of the silicon substrate 10 includes:

The second tunneling oxide layer is prepared on the silicon substrate using any one of high-temperature thermal oxidation, nitric acid oxidation, ozone oxidation, and chemical vapor deposition.

The second tunnel oxide layer is a silicon dioxide layer with a thickness of 1.3 to 1.7 nm.

Optionally, a low pressure chemical vapor deposition method, a plasma enhanced chemical vapor deposition method, or the like may be used to prepare the second silicon layer on the surface of the second tunnel oxide layer facing away from the silicon substrate 10 .

Optionally, doping the second silicon layer, and forming the second doped silicon layer includes: doping the second silicon layer using a diffusion method, an ion implantation method, or a laser doping method, The second doped silicon layer is formed. The doping element may be phosphorus, and the square resistance of the second doped silicon layer is between 70 and 90Ω/sq.

It should be noted that when the second passivation contact structure 60 is prepared, a P-Poly layer will be formed on the front side of the silicon substrate 10 , so after the second passivation contact structure 60 is formed, it is necessary to use, for example, tank cleaning. equipment, and use an alkaline cleaning solution to remove the P-Poly layer around the plating. Specifically, the above-mentioned alkaline cleaning solution can be any alkaline solution capable of removing the circumferentially plated P-Poly layer. For example: the alkaline cleaning solution can be potassium hydroxide, sodium hydroxide, or a mixture thereof. The concentration and liquid level of the above-mentioned alkaline cleaning solution, as well as the process conditions when removing the circumferentially plated P-Poly layer through the alkaline cleaning solution, can be set according to actual needs, as long as they can be applied to the solar cells provided by the embodiments of the present invention. Any manufacturing method is applicable. In one embodiment, the alkaline cleaning solution is a mixture of water, potassium hydroxide and texturing additives. Among them, the above-mentioned texturing additive can be any texturing additive that can adjust the transverse and longitudinal corrosion rates of potassium hydroxide. For example: the texturing additive can be the texturing additive model BP63 provided by Shaoxing Topband Electronic Technology Co., Ltd., in the above alkaline cleaning solution The volume ratio of water, potassium hydroxide and texturing additives can be 340:16:4, and the treatment conditions can be that the temperature of the alkaline cleaning solution is 58°C to 62°C, and the process time is 200 to 250s.

Further, in the embodiment of the present application, after removing the surrounding P-Poly layer, the step of removing the BSG layer in the area outside the gate line preset area 40 on the front side of the silicon substrate 10 is also included. For example: in tank cleaning equipment, an acidic cleaning solution is used to remove the front BSG layer. The acidic cleaning solution can be a hydrofluoric acid solution. The concentration and liquid level of the above-mentioned acidic cleaning solution, as well as the process conditions when removing the front BSG layer through the acidic cleaning solution, can be set according to actual needs, as long as they can be applied to the manufacturing method of solar cells provided by the embodiments of the present invention. . For example: when removing the front BSG layer, when the acidic cleaning solution is a hydrofluoric acid solution, it is composed of HF and water in a volume ratio of 50:300. The processing conditions can be that the temperature of the acidic cleaning solution is 25±2°C. The process time is 200~250s.

Further, in some embodiments, after forming the second passivation contact structure 60 on the back side of the silicon substrate 10, the method further includes:

Prepare a front passivation layer 70 on the surface of the diffusion layer 20;

A back passivation layer 80 is prepared on the surface of the second doped silicon layer.

For example, the front passivation layer 70 can be formed through a process such as chemical vapor deposition or atomic layer deposition, and the material and thickness of the front passivation layer 70 can be set according to actual requirements. Optionally, the front passivation layer 70 includes an aluminum oxide layer and a silicon nitride layer stacked from the inside to the outside. Since the doping type of the diffusion layer is P+ type, the negative fixed charge carried by the aluminum oxide has a shielding effect on the electron carriers (minority carriers) on the silicon surface, which can reduce the concentration of surface electron carriers, thereby enabling Reducing the surface recombination rate allows the first electrode to collect more hole carriers and improves the photoelectric conversion efficiency of the solar cell. The silicon nitride layer has an anti-reflective effect. The formation of silicon nitride on the aluminum oxide layer can increase the absorption of light by solar cells and improve the utilization rate of light energy by solar cells. For example, an atomic layer deposition method can be used to prepare the aluminum oxide layer, and plasma enhanced chemical vapor deposition equipment can be used to pass silane, ammonia, nitrogen and other gases to deposit the silicon nitride layer using a plasma enhanced chemical vapor deposition method.

For example, the back passivation layer 80 can be formed on the second doped silicon layer through a process such as chemical vapor deposition or atomic layer deposition. The material and thickness of the back passivation layer 80 can be set according to actual requirements. Optionally, the back passivation layer 80 includes a silicon nitride layer. Plasma-enhanced chemical vapor deposition equipment can be used to pass silane, ammonia, nitrogen and other gases to deposit the silicon nitride layer using a plasma-enhanced chemical vapor deposition method. .

Further, in some embodiments, the front passivation layer 70 is prepared on the surface of the diffusion layer 20 , and after the back passivation layer 80 is prepared on the surface of the second doped silicon layer, the front passivation layer A metallization process is performed on the second electrode 70 and the back passivation layer 80 respectively to form the second electrode 90 and the first electrode including the above-mentioned thin gate line 301.

For example, the above electrodes can be formed through processes such as printing and sintering. The first electrode located above the front side of the silicon substrate is the positive electrode of the solar cell, and the second electrode 90 located above the back side of the silicon substrate is the back electrode of the solar cell. The material of the electrode can be metal materials such as silver, copper or nickel. . Wherein, the first electrode and the second electrode 90 both include thin gate lines and main gate lines, and the main gate lines are perpendicular to the thin gate lines, wherein the thin gate lines 301 of the first electrode are located above the preset gate line area 40 .

Further, in some embodiments, the silicon substrate 10 is textured before preparing the diffusion layer 20 to form a silicon substrate with a pyramid-shaped textured surface on the front.

For example, an alkaline solution may be used to process the front surface of the silicon substrate 10 to form a pyramid-shaped texture structure on the front surface of the silicon substrate 10 . The alkaline solution can be any alkaline solution that can achieve texturing treatment. For example: the alkaline solution can be potassium hydroxide solution or sodium hydroxide solution. The textured structure located on the front side of the silicon substrate can trap light to reduce the reflection of light by the solar cell, allowing more light to be refracted into the solar cell and improving the utilization rate of light energy by the solar cell. In one embodiment, the alkaline solution is a mixture of water, potassium hydroxide and texturing additives. Among them, the above-mentioned texturing additive can be any texturing additive that can adjust the transverse and longitudinal corrosion rates of potassium hydroxide. For example: the texturing additive can be the texturing additive model TS55 provided by Changzhou Shichuang Energy Technology Company. The volume ratio of water, potassium hydroxide and texturing additive in the above alkali solution can be 354:5.5:2. At this time , the corrosion intensity of potassium hydroxide in alkali solution for corrosion cleaning is moderate. In addition, the above-mentioned processing conditions when using an alkali solution to texturize the front side of the silicon substrate can also be set according to actual needs. For example: the above processing conditions can be that the temperature of the alkali solution is 77°C to 83°C, the process time is 495 to 505s, the etching amount is 0.6±0.05g, and the reflectivity is 9±0.3%. In the above case, a regular and uniform pyramid-shaped texturing surface can be obtained.

Example 1

TOPCon batteries are prepared according to the following process:

1) Put the N-type bare silicon wafer into a tank-type texturing cleaning machine for alkali texturing. The alkali solution for texturing is composed of H ₂ O, KOH and texturing additives in a volume ratio of 354:5.5:2, in which the KOH concentration is 1%, system The velvet additive is Shichuang TS55. Texturing process conditions: alkali solution temperature 80°C, processing time 500s, etching amount 0.6g, reflectivity 9%.

2) The textured silicon wafer is subjected to a boron diffusion process in a boron diffusion furnace tube with a square resistance of 200Ω/sq and a temperature of 1000°C.

3) Use an ultraviolet laser to laser groove the BSG layer on the front side of the silicon wafer. The laser power is 20W and the frequency is 40000Hz. The groove pattern is consistent with the front metal fine grid line pattern. After removing the surface BSG layer in this pattern area, the laser At the same time, the lower silicon is burned to form a groove to form an inverted pyramid-shaped gate line preset area 40; Mark points are marked on the four corners of the silicon wafer for alignment during subsequent screen printing.

4) Modification is carried out in a tank cleaning machine. The alkali solution for modification is composed of H ₂ O, KOH and texturing additives in a volume ratio of 354:5.5:2, in which the KOH concentration is 1% and the texturing additive is Shichuang TS55. Modification process conditions: alkali solution temperature 80°C, treatment time 120s.

5) Deposit the first tunnel oxide layer (SiO ₂ ) and the polysilicon layer in the front gate line preset area 40 in a low-pressure chemical vapor deposition furnace (LPCVD). The thickness of the first tunnel oxide layer is 1.5nm, and the polysilicon layer The thickness is 120nm.

6) The silicon wafer after the LPCVD process is doped into the polysilicon layer in a boron diffusion furnace tube with a square resistance of 80Ω/sq and a process temperature of 1000°C to form the first doped silicon layer (P-Poly).

7) Remove the backside boron diffusion layer in chain acid etching equipment. The liquid consists of HF, HNO ₃ and H ₂ SO ₄ in a volume ratio of 54:165:38. The liquid temperature is 25°C and the etching amount is 0.4g. , backside reflectivity 35%.

8) Deposit the second tunnel oxide layer (SiO ₂ ) and the polysilicon layer on the back in a low-pressure chemical vapor deposition furnace (LPCVD). The thickness of the second tunnel oxide layer is 1.5nm, and the thickness of the polysilicon layer is 120nm.

9) Use a phosphorus diffusion furnace to inject phosphorus into the back polysilicon layer to form a second doped silicon layer (N-Poly).

10) In the first tank of the tank cleaning machine, remove the front-side wrapped N-Poly layer. The alkali solution used to remove the wrapped N-Poly layer is composed of H ₂ O, KOH and texturing additives in a volume ratio of 340:16:4. , where the KOH concentration is 4%, the texturing additive is Topband BP63, the alkali solution temperature is 60°C, and the processing time is 220s; in the second tank of the tank cleaning machine, remove other parts other than the front grid line preset area 40 For the BSG layer in the area, the acid solution used to remove the BSG layer is composed of HF and H ₂ O with a volume ratio of 50:300. The acid solution temperature is 25°C and the treatment time is 200s.

11) Deposit an AlOx layer + SiNx layer on the front side of the silicon wafer, and prepare a SiNx layer on the back side.

12) Screen printing, sintering and testing and sorting.

Comparative example 1

A TOPCon battery was prepared according to the process of Example 1, except that the above steps 3) to 6) were not performed.

The batteries prepared in Example 1 and Comparative Example 1 were tested, and the results are as shown in the following table:

It can be seen that compared with the battery provided by the embodiment of the present application without the TOPCon passivation structure on the front, the open circuit voltage (Voc) can be increased by 15mV, the fill factor (FF) can be increased by 0.5% abs, and the series resistance (Rs ) can be reduced by 0.12mΩ, the battery conversion efficiency (Eta) can be increased by 0.6% abs, and the short circuit circuit (Isc) has no significant reduction.

To sum up, the TOPCon battery and its preparation method in the embodiments of the present application have a simple process, good passivation effect, and high battery efficiency.

The above description is only a preferred embodiment of the present application and an explanation of the technical principles used. Those skilled in the art should understand that the disclosure scope involved in this application is not limited to technical solutions composed of specific combinations of the above technical features, but should also cover solutions consisting of the above technical features or without departing from the foregoing disclosed concept. Other technical solutions formed by any combination of equivalent features. For example, a technical solution is formed by replacing the above features with technical features with similar functions disclosed in this application (but not limited to).

Claims

A TOPCon battery is characterized by including:

A silicon substrate, a diffusion layer and a first electrode located on the front side of the silicon substrate, the first electrode including a plurality of thin gate lines;

The diffusion layer is provided with a plurality of gate line preset areas distributed correspondingly to the fine gate lines. A first passivation contact structure is provided in the gate line preset area. The first passivation contact structure includes an edge along the A first tunnel oxide layer and a first doped silicon layer are arranged sequentially in a direction away from the silicon substrate.
The TOPCon battery according to claim 1, wherein the cross-sectional shape of the gate line preset area perpendicular to its extension direction is an inverted pyramid, and the cross-sectional shape of the first passivation contact structure is consistent with the cross-sectional shape of the first passivation contact structure. The cross-sectional shape of the grid line preset area is adapted to the cross-sectional shape.
The TOPCon battery according to claim 1, wherein the gate line preset area includes a groove formed on the diffusion layer, and the first passivation contact structure is formed along with the groove, so The thin gate lines are stacked in the grooves and are in ohmic contact with the first passivation contact structure.
The TOPCon battery according to claim 3, wherein the cross-sectional shape of the groove is an inverted pyramid, a concave arc, a triangle or a quadrilateral.
The TOPCon battery according to claim 1, wherein the first tunnel oxide layer is a silicon oxide film with a thickness of 1.3 to 1.7 nm;

And/or, the thickness of the first doped silicon layer is 110-130 nm.
The TOPCon battery according to claim 1, further comprising:

A second passivation contact structure is formed on the back side of the silicon substrate. The second passivation contact structure includes a second tunnel oxide layer and a second doped silicon layer sequentially arranged in a direction away from the silicon substrate. .
The TOPCon battery according to claim 6, further comprising:

A front-side passivation layer formed on the surface of the diffusion layer facing away from the silicon substrate and covering the first passivation contact structure;

A back passivation layer formed on the surface of the second doped silicon layer facing away from the silicon substrate;

The first electrode penetrates the front passivation layer and forms ohmic contact with the diffusion layer.
The TOPCon battery according to claim 7, wherein the front passivation layer is one or a combination of several stacked layers selected from the group consisting of SiO x layer, AlO x layer, SiN x layer, and SiON x layer.
The TOPCon battery according to claim 7, wherein the backside passivation layer is one or a stacked combination of SiN x layer and SiON x layer.
The TOPCon battery according to any one of claims 1 to 9, characterized in that:

The front side of the silicon substrate is a pyramid-shaped textured surface;

And/or, the back side of the silicon substrate is a polished surface.
A method for preparing the TOPCon battery according to any one of claims 1 to 10, characterized in that it includes:

Form a diffusion layer and a borosilicate glass layer on the front side of the silicon substrate in sequence;

Make grooves on the silicon substrate at preset positions corresponding to the thin gate lines to form preset gate line areas that penetrate the borosilicate glass layer;

A first passivation contact structure is formed in the gate line preset area, and the first passivation contact structure includes a first tunnel oxide layer and a first doped silicon layer sequentially arranged in a direction away from the silicon substrate. .
The method according to claim 11, characterized in that, forming a groove on the silicon substrate at a preset position of the fine gate line to form a preset gate line area penetrating the borosilicate glass layer includes:

The preset gate line area is formed by using a laser to make grooves on the silicon substrate at preset positions corresponding to the fine gate lines.
The method of claim 11, wherein the gate line preset area extends downward to form a groove on the diffusion layer while penetrating the borosilicate glass layer, and the first passivation contact A structure is formed along with the groove, and the surface of the first passivation contact structure is closer to the center of the silicon substrate than the surface of the borosilicate glass layer.
The method according to claim 11, characterized in that, after forming the gate line preset area, further comprising: modifying the front surface of the silicon substrate after the groove is formed to remove the surface of the front surface of the silicon substrate. Damage the layer and modify the surface of the gate line preset area.
The method of claim 14, wherein the modification includes soaking the front side of the silicon substrate with an alkali solution of 0.8 to 1.2 wt% at 70 to 90°C.
The method according to claim 11, characterized in that after forming the first passivation contact structure in the gate line preset area, it further includes: forming a second passivation contact structure on the back side of the silicon substrate, said The second passivation contact structure includes a second tunnel oxide layer and a second doped silicon layer sequentially arranged in a direction away from the silicon substrate.
The method according to claim 16, characterized in that, after forming the second passivation contact structure on the back side of the silicon substrate, it further includes: preparing a front passivation layer on the surface of the diffusion layer; A back passivation layer is prepared on the surface of the hybrid silicon layer.