WO2023173608A1 - 一种反熔丝存储阵列电路及其操作方法以及存储器 - Google Patents

一种反熔丝存储阵列电路及其操作方法以及存储器 Download PDF

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Publication number
WO2023173608A1
WO2023173608A1 PCT/CN2022/098713 CN2022098713W WO2023173608A1 WO 2023173608 A1 WO2023173608 A1 WO 2023173608A1 CN 2022098713 W CN2022098713 W CN 2022098713W WO 2023173608 A1 WO2023173608 A1 WO 2023173608A1
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Prior art keywords
transistor
memory array
antifuse memory
fuse
programming
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PCT/CN2022/098713
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English (en)
French (fr)
Inventor
季汝敏
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长鑫存储技术有限公司
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Publication of WO2023173608A1 publication Critical patent/WO2023173608A1/zh

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/4067—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the bipolar type

Definitions

  • the present disclosure relates to the field of integrated circuit technology, and in particular, to an antifuse memory array circuit, an operating method thereof, and a memory.
  • anti-fuse programmable memory in DRAM chips can store defective memory cell address information, thereby achieving redundant replacement. (Including row replacement and column replacement); you can also program the antifuse programmable memory to achieve precise modification of various internal parameters of the chip (such as voltage, current, frequency).
  • the information stored in the antifuse programmable memory will be sent through the built-in transmission circuit and latched where it is needed.
  • the current antifuse programmable memory requires a sensitive amplifier with a fast response speed and consumes a lot of power.
  • embodiments of the present disclosure provide an antifuse memory array circuit, an operating method thereof, and a memory.
  • an antifuse memory array circuit including:
  • At least one antifuse memory array the antifuse memory array including a plurality of antifuse memory cells
  • a programming control module is connected to the at least one antifuse memory array and configured to provide a fixed programming current when programming the antifuse memory cells.
  • it also includes:
  • the anti-fuse memory array includes a plurality of bit lines extending along a first direction and arranged along a second direction, each of the bit lines is connected to a plurality of the anti-fuse memory cells, and the same anti-fuse memory unit
  • Each bit line in the fuse memory array is connected to the first node through a different first switch, the control terminal of the first switch receives the column address signal, and the programming control module is connected to the first node, Configured to provide the programming current to the first node when programming the antifuse memory cell.
  • the programming current ranges from 0.2mA to 1mA.
  • the programming control module includes a first current mirror circuit and at least one first transistor; a first electrode of the first transistor is connected to a first node of the antifuse memory array, and the first The second pole of a transistor is connected to the output end of the first current mirror circuit, and the control end of the first transistor receives a programming control signal.
  • it also includes:
  • a logical read module connected to the first node and configured to provide a fixed read current when reading the anti-fuse memory cell
  • a readout module is connected to the first node and configured to read out the data stored in the antifuse memory unit.
  • the read current ranges from 1 ⁇ A to 20 ⁇ A.
  • the logic reading module includes a second current mirror circuit and a second transistor; a first pole of the second transistor is connected to the first node, and a second pole of the second transistor is connected to the The output terminal of the second current mirror circuit and the control terminal of the second transistor receive the logic read signal.
  • the readout module includes an amplifier, a first input terminal of the amplifier is connected to the first node, and a second input terminal of the amplifier is connected to a standard voltage; wherein the voltage of the first node
  • the comparison result between the value and the standard voltage is the data stored in the anti-fuse memory cell.
  • it also includes:
  • a resistance reading module is connected to the first node and configured to read the resistance value of the anti-fuse memory cell in a resistance reading mode.
  • the resistance reading module includes a third transistor, a first electrode of the third transistor is connected to the first node, a second electrode of the third transistor is grounded, and a The control terminal receives the resistance reading signal.
  • each bit line is connected to a precharge unit configured to precharge protection for unprogrammed antifuse memory cells on the bit line.
  • the precharge unit includes a second switch, a first pole of the second switch is connected to the bit line, a second pole of the second switch receives the precharge voltage, and the second switch The control end receives the column address signal.
  • the first switch includes an N-type transistor and the second switch includes a P-type transistor.
  • the antifuse memory cell includes a first antifuse memory transistor, a fourth transistor, a fifth transistor, and a second antifuse memory transistor;
  • the fourth transistor and the fifth transistor are respectively controlled by two adjacent word lines;
  • the first anti-fuse storage transistor and the second anti-fuse storage transistor are respectively controlled by two programming wires;
  • the first pole of the first antifuse memory transistor is connected to the first pole of the fourth transistor
  • the first pole of the second antifuse memory transistor is connected to the first pole of the fifth transistor
  • the second electrode of the fourth transistor is connected to the second electrode of the fifth transistor, and the second electrode of the fourth transistor and the second electrode of the fifth transistor are connected to the bit line.
  • a memory including the antifuse memory array circuit as described in any one of the above embodiments.
  • an operating method of an antifuse memory array circuit including:
  • the programming control module is controlled to provide a fixed programming current to the antifuse memory array.
  • the method further includes:
  • the control logic read module provides a fixed read current to the antifuse memory array.
  • the programming control module provides the programming current for the anti-fuse memory cell, and the programming control module can perform current-limiting control on the programming current, so that the resistance distribution of the programmed anti-fuse memory cell is more concentrated. In this way, there is It is beneficial for the subsequent readout module to read the data stored in the anti-fuse memory unit, and the response speed requirement of the readout module, that is, the amplifier is reduced, which can save current and reduce power consumption.
  • Figure 1 is a circuit diagram of an antifuse memory array circuit provided in some embodiments.
  • Figure 2 is a schematic structural diagram of an antifuse memory array circuit provided by an embodiment of the present disclosure
  • Figure 3 is a circuit diagram of an antifuse memory array provided by an embodiment of the present disclosure.
  • Figure 4 is a circuit diagram of an antifuse memory array circuit provided by an embodiment of the present disclosure.
  • Figure 5 is a circuit diagram of an antifuse memory array circuit provided by another embodiment of the present disclosure.
  • FIG. 6 is a schematic flowchart of an operating method of an antifuse memory array circuit provided by an embodiment of the present disclosure.
  • 10-antifuse memory array 101-antifuse memory cell; 101-1-first antifuse memory transistor; 101-2-fourth transistor; 101-3-fifth transistor; 101-4-second Antifuse memory transistor; 102-first switch; 103-second switch;
  • 50-resistance reading module 501-third transistor.
  • the row address (XADD_n) in the antifuse memory array is in the same phase as the programming line (PGM_n); in programming mode, the row address of the target cell is selected to be set high, and the target The bit line (BLn) is set to a low potential; PGM_n is set to a high voltage to establish a strong electric field between the gate and drain of the target fuse unit, thereby breaking down the gate oxide layer to form a resistor with a smaller resistance.
  • the precharge-discharge method when reading the status of the fuse unit in the anti-fuse memory array, the precharge-discharge method is usually used to determine the data latch time and sense amplifier. ) has higher response speed requirements, and a sensitive amplifier with a faster response speed is required to accurately read the data stored in the fuse.
  • an embodiment of the present disclosure provides an anti-fuse memory array circuit.
  • Figure 2 is a schematic structural diagram of an anti-fuse memory array circuit provided by an embodiment of the present disclosure
  • Figure 3 is a schematic diagram of an anti-fuse memory array circuit provided by an embodiment of the present disclosure. Circuit diagram of the array
  • Figure 4 is a circuit diagram of an antifuse memory array circuit provided by an embodiment of the present disclosure.
  • the anti-fuse memory array circuit includes: at least one anti-fuse memory array 10, the anti-fuse memory array 10 includes a plurality of anti-fuse memory cells 101; a programming control module 20, The at least one antifuse memory array 10 is connected and configured to provide a fixed programming current IPGM when programming the antifuse memory cell 101 .
  • the programming control module provides the programming current for the anti-fuse memory cell.
  • the programming control module can perform current-limiting control on the programming current, so that the resistance distribution of the programmed anti-fuse memory cell is more concentrated. In this way, there is It is beneficial for the subsequent readout module to read the data stored in the anti-fuse memory unit, and the response speed requirement of the readout module, that is, the amplifier is reduced, which can save current and reduce power consumption.
  • the antifuse memory array 10 includes a plurality of bit lines BLn extending along the first direction and arranged along the second direction (n is the serial number of the corresponding bit line).
  • Each of the bit lines A plurality of the anti-fuse memory cells 101 are connected thereto, and each of the bit lines located in the same anti-fuse memory array 10 is connected to the first node N1 through a different first switch 102.
  • the bit lines in the wire memory array 10 are connected to different first nodes, and the control terminal of the first switch 102 receives the column address signal Yn (Yn is the column address received by the control terminal of the first switch corresponding to different bit lines. signal), the programming control module 20 is connected to the first node N1, and is configured to provide the programming current IPGM to the first node N1 when programming the anti-fuse memory cell 101.
  • the first switch 102 includes an N-type transistor.
  • the programming current IPGM ranges from 0.2mA to 1mA. More specifically, the programming current IPGM may be 0.6mA.
  • the anti-fuse memory cell When the programming current IPGM is within this range, the anti-fuse memory cell has the best programming effect. Otherwise, if the programming current is less than 0.2mA, it may result in incomplete programming of the anti-fuse memory cell. If the programming current is greater than 1mA, the anti-fuse memory cell will be programmed incompletely. This can cause overheating, which can damage other nearby antifuse memory cells that need to be programmed.
  • the programming control module 20 includes a first current mirror circuit 201 and at least one first transistor 202 ; the first electrode of the first transistor 202 is connected to a first terminal of the antifuse memory array 10 . Node N1, the second pole of the first transistor 202 is connected to the output terminal of the first current mirror circuit 201, and the control terminal of the first transistor 202 receives the programming control signal V1.
  • the first transistor 202 is an N-type transistor.
  • the programming control signal V1 received by the control terminal of the first transistor 202 is set to a high level, so that the path of the programming control module 20 is opened, and the control terminal of the anti-fuse memory cell to be programmed is opened.
  • the first current mirror circuit 201 provides the programming current IPGM to the anti-fuse memory cell to implement the programming operation of the anti-fuse memory cell.
  • the first current mirror circuit in the programming control module can limit the current of the programming current, so that the resistance distribution of the programmed anti-fuse is more concentrated. In this way, the accuracy of reading the data stored in the anti-fuse memory cell can be improved.
  • the typical value of the programming current IPGM can be controlled by a test mode signal (not shown in the figure).
  • the anti-fuse memory cell is programmed in the chip test mode.
  • the test mode can control the size of the programming current, so that the programming current can be flexibly controlled, and finally the most appropriate current is selected for programming, and then the During final programming, the signal corresponding to the appropriate current in the corresponding test mode controls the size of the programming current.
  • the first current mirror circuit 201 includes a set of N-type transistors, and the input terminal of the first current mirror circuit 201 is connected to the programming current IPGM.
  • an antifuse memory array 10 is connected to a programming control module 20 .
  • multiple antifuse memory arrays 10 are connected to a programming control module 20; wherein the programming control module 20 includes a first current mirror circuit 201 and at least one A first transistor 202. Each antifuse memory array 10 is connected to the first current mirror circuit 201 through a first transistor 202.
  • each antifuse memory array 10 is distinguished by a first transistor 202 , but shares the same first current mirror circuit, thereby saving chip area.
  • the anti-fuse memory array circuit also includes: a logic read module 30, connected to the first node N1, configured to provide a fixed read current IREAD when reading the anti-fuse memory unit 101; read The output module 40 is connected to the first node N1 and is configured to read the data stored in the anti-fuse memory unit 101 .
  • the read current IREAD ranges from 1 ⁇ A to 20 ⁇ A. More specifically, the read current IREAD may be 10 ⁇ A.
  • the read current IREAD When the read current IREAD is within this range, the accuracy of reading data stored in the antifuse memory cell can be improved. Otherwise, if the read current is less than 1 ⁇ A, it will easily be interfered when reading the data stored in the anti-fuse memory unit, resulting in low read accuracy; if the read current is greater than 20 ⁇ A, the read power consumption will increase. .
  • the actual read current needs to be set according to the resistance distribution of the antifuse memory cell after programming.
  • the logic reading module 30 includes a second current mirror circuit 301 and a second transistor 302; the first pole of the second transistor 302 is connected to the first node N1, and the second transistor 302 The second pole is connected to the output terminal of the second current mirror circuit 301, and the control terminal of the second transistor 302 receives the logic read signal V2.
  • the second transistor 302 is an N-type transistor.
  • the second current mirror circuit 301 includes a set of N-type transistors, and the input terminal of the second current mirror circuit 301 is connected to the read current IREAD.
  • the logic read signal received by the control terminal of the second transistor is set to a high level, so that the path of the logic read module is opened, and the control terminal of the anti-fuse memory cell to be programmed is applied.
  • the first voltage, the read current IREAD flows through the antifuse memory cell and generates a voltage drop (Drop Voltage).
  • the readout module 40 includes an amplifier 401, the first input terminal of the amplifier 401 is connected to the first node N1, and the second input terminal of the amplifier 401 is connected to the standard voltage V_REF; wherein, the The comparison result between the voltage value of the first node N1 and the standard voltage V_REF is the data stored in the anti-fuse memory unit 101 .
  • the voltage at the first node N1 is the common voltage V_Com;
  • the comparison result between the voltage value of the first node N1 and the standard voltage V_REF is the data stored in the anti-fuse memory unit 101, including: the common voltage V_Com
  • the comparison result with the standard voltage V_REF is the data stored in the anti-fuse memory unit 101 .
  • the first input terminal of the amplifier is a positive input terminal, and the second input terminal is a negative input terminal;
  • the comparison result of the common voltage V_Com and the standard voltage V_REF is the anti-fuse memory unit 101
  • Stored data includes:
  • the fuse resistance of the anti-fuse memory unit is low, so the voltage drop of the anti-fuse memory unit is small, and the common voltage V_Com is greater than the standard voltage V_REF, so The output of the amplifier is "1", and the logic state of the anti-fuse memory unit is high level;
  • the fuse resistance of the anti-fuse memory cell is high, so the voltage drop of the anti-fuse memory cell is large, and the common voltage V_Com is smaller than the standard voltage V_REF.
  • the output of the amplifier is "0", and the logic state of the anti-fuse memory cell is low level.
  • the precharge-discharge method is not used to read the data stored in the anti-fuse memory unit, the response speed requirement for the amplifier is low, which can save current and reduce power consumption.
  • the anti-fuse memory array circuit further includes: a resistance reading module 50 connected to the first node N1 and configured to read the anti-fuse memory unit 101 in the resistance reading mode. resistance.
  • the resistance reading module 50 includes a third transistor 501.
  • the first electrode of the third transistor 501 is connected to the first node N1.
  • the second electrode of the third transistor 501 is grounded.
  • the control terminal of the three transistors 501 receives the resistance reading signal V3.
  • the resistance reading signal V3 is set to a high level, so that the path of the resistance reading module 50 is opened, and a second voltage is applied to the control end of the anti-fuse memory cell to be programmed.
  • the current of the anti-fuse memory cell determines the resistance value of the anti-fuse memory cell.
  • the fuse resistance of the programmed anti-fuse memory cell is low, and the current flowing through the anti-fuse memory cell is relatively large, for example, it can be tens to hundreds of microamps;
  • the fuse resistance of the programmed anti-fuse memory cell is large, and the current flowing through the anti-fuse memory cell is small, for example, a few nanoamps.
  • each bit line is connected to a precharge unit configured to precharge protection for unprogrammed antifuse memory cells 101 on the bit line.
  • the precharge unit includes a second switch 103.
  • the first pole of the second switch 103 is connected to the bit line.
  • the second pole of the second switch 103 receives the precharge voltage VPRE.
  • the first pole of the second switch 103 receives the precharge voltage VPRE.
  • the control terminals of the two switches receive the column address signal Pn (Pn is the column address signal received by the control terminal of the second switch corresponding to a different bit line, Pn and the control terminal of the first switch 102 receive the column address signal Yn can be same signal).
  • the VPRE voltage received by the second switch is used to protect the unprogrammed antifuse memory cells.
  • the bit line where the unprogrammed antifuse memory cells are located will be precharged to the VPRE voltage; this can avoid unprogrammed antifuses.
  • the wire storage unit is damaged.
  • the second switch includes a P-type transistor
  • the antifuse memory array 10 includes a plurality of antifuse memory cells 101.
  • the antifuse memory unit 101 includes a first antifuse memory transistor 101-1, a fourth transistor 101-2, Five transistors 101-3 and the second anti-fuse storage transistor 101-4; the fourth transistor 101-2 and the fifth transistor 101-3 respectively pass through two adjacent word lines XADD_m (m is the serial number of the corresponding word line) Control; the first anti-fuse storage transistor 101-1 and the second anti-fuse storage transistor 101-4 are respectively controlled by two programming wires PGM_m; the first pole of the first anti-fuse storage transistor 101-1 The first electrode of the fourth transistor 101-2 is connected; the first electrode of the second anti-fuse memory transistor 101-4 is connected to the first electrode of the fifth transistor 101-3; the fourth transistor 101 The second pole of -2 is connected to the second pole of the fifth transistor 101-3, and the second pole of the fourth transistor 101-2 and the second pole of the fifth transistor 101-3 are connected to the bit Wire.
  • the antifuse memory array is a 16*16 antifuse memory array, that is, the antifuse memory array includes 16 bit lines BL and 16 word lines PGM. Therefore, In the embodiment shown in FIG. 3 and FIG. 4 , a total of eight anti-fuse memory cells 101 are connected to each bit line, namely out1 to out8 shown in the figure.
  • An embodiment of the present disclosure also provides a memory, which includes an antifuse memory array circuit as described in any of the above embodiments.
  • An embodiment of the present disclosure also provides an operating method of an antifuse memory array circuit. Please refer to Figure 6 for details. As shown in Figure 6, the operating method includes the following steps:
  • Step 601 Program the antifuse memory array
  • Step 602 Control the programming control module to provide a fixed programming current to the antifuse memory array.
  • steps 601 and 602 are executed to program the anti-fuse memory array 10 ; the programming control module 20 is controlled to provide a fixed programming current to the anti-fuse memory array 10 .
  • the antifuse memory array includes a plurality of antifuse memory cells 101; a programming control module 20 is connected to the at least one antifuse memory array 10.
  • the antifuse memory array 10 includes a plurality of bit lines BLn extending along a first direction and arranged along a second direction (n is the serial number of the corresponding bit line). Each of the bit lines is connected to a plurality of the bit lines BLn. Antifuse memory unit 101, and each bit line located in the same antifuse memory array 10 is connected to the first node N1 through a different first switch 102.
  • the control end of the first switch 102 receives the column The address signal Yn (Yn is the column address signal received by the control end of the first switch corresponding to the different bit line), the programming control module 20 is connected to the first node N1, and is configured to store the anti-fuse When the unit 101 performs programming, the programming current IPGM is provided to the first node N1.
  • the programming current IPGM ranges from 0.2mA to 1mA. More specifically, the programming current IPGM may be 0.6mA.
  • the anti-fuse memory cell When the programming current IPGM is within this range, the anti-fuse memory cell has the best programming effect. Otherwise, if the programming current is less than 0.2mA, it may result in incomplete programming of the anti-fuse memory cell. If the programming current is greater than 1mA, the anti-fuse memory cell will be programmed incompletely. This can cause overheating, which can damage other nearby antifuse memory cells that need to be programmed.
  • the programming control module 20 includes a first current mirror circuit 201 and at least one first transistor 202 ; the first electrode of the first transistor 202 is connected to a first terminal of the antifuse memory array 10 . Node N1, the second pole of the first transistor 202 is connected to the output terminal of the first current mirror circuit 201, and the control terminal of the first transistor 202 receives the programming control signal V1.
  • the programming control signal V1 received by the control terminal of the first transistor 202 is set to a high level, so that the path of the programming control module 20 is opened, and the control terminal of the anti-fuse memory cell to be programmed is opened.
  • the first current mirror circuit 201 provides the programming current IPGM to the anti-fuse memory cell to implement the programming operation of the anti-fuse memory cell.
  • the first current mirror circuit in the programming control module can limit the current of the programming current, so that the resistance distribution of the programmed anti-fuse is more concentrated. In this way, the accuracy of reading the data stored in the anti-fuse memory cell can be improved.
  • an antifuse memory array 10 is connected to a programming control module 20 .
  • multiple antifuse memory arrays 10 are connected to a programming control module 20; wherein the programming control module 20 includes a first current mirror circuit 201 and a plurality of A first transistor 202. Each antifuse memory array 10 is connected to the first current mirror circuit 201 through a first transistor 202.
  • each antifuse memory array 10 is distinguished by a first transistor 202 , but shares the same first current mirror circuit, thereby saving chip area.
  • the method further includes: reading the anti-fuse memory array 10 ; controlling the logic read module 30 to provide a fixed read current to the anti-fuse memory array 10 .
  • the read current IREAD ranges from 1 ⁇ A to 20 ⁇ A. More specifically, the read current IREAD may be 10 ⁇ A.
  • the read current IREAD When the read current IREAD is within this range, the accuracy of reading data stored in the antifuse memory cell can be improved. Otherwise, if the read current is less than 1 ⁇ A, it will easily be interfered when reading the data stored in the anti-fuse memory unit, resulting in low read accuracy; if the read current is greater than 20 ⁇ A, the read power consumption will increase. .
  • the actual read current needs to be set according to the resistance distribution of the antifuse memory cell after programming.
  • the logic reading module 30 includes a second current mirror circuit 301 and a second transistor 302; the first pole of the second transistor 302 is connected to the first node N1, and the second transistor 302 The second pole is connected to the output terminal of the second current mirror circuit 301, and the control terminal of the second transistor 302 receives the logic read signal V2.
  • the logic read signal received by the control terminal of the second transistor is set to a high level, so that the path of the logic read module is opened, and the control terminal of the anti-fuse memory cell to be programmed is applied.
  • the first voltage, the read current IREAD flows through the antifuse memory cell and generates a voltage drop (Drop Voltage).
  • the method further includes: controlling the readout module 40 to obtain the data stored in the anti-fuse memory unit 101 based on the comparison result between the voltage value of the first node N1 and the standard voltage V_REF.
  • the voltage at the first node N1 is the common voltage V_Com; the data stored in the anti-fuse memory unit 101 is obtained based on the comparison result between the voltage value of the first node N1 and the standard voltage V_REF, including: The data stored in the anti-fuse memory unit 101 is obtained from the comparison result of the common voltage V_Com and the standard voltage V_REF.
  • the first input terminal of the amplifier is a positive input terminal, and the second input terminal is a negative input terminal; according to the comparison result of the common voltage V_Com and the standard voltage V_REF, the anti-fuse storage
  • the data stored in unit 101 includes:
  • the fuse resistance of the anti-fuse memory unit is low, so the voltage drop of the anti-fuse memory unit is small, and the common voltage V_Com is greater than the standard voltage V_REF, so The output of the amplifier is "1", and the logic state of the anti-fuse memory unit is high level;
  • the fuse resistance of the anti-fuse memory cell is high, so the voltage drop of the anti-fuse memory cell is large, and the common voltage V_Com is smaller than the standard voltage V_REF.
  • the output of the amplifier is "0", and the logic state of the anti-fuse memory cell is low level.
  • the precharge-discharge method is not used to read the data stored in the anti-fuse memory unit, the response speed requirement for the amplifier is low, which can save current and reduce power consumption.
  • the method further includes: controlling the resistance reading module 50 to read the resistance value of the anti-fuse memory unit 101 in the resistance reading mode.
  • the resistance reading module 50 includes a third transistor 501.
  • the first electrode of the third transistor 501 is connected to the first node N1.
  • the second electrode of the third transistor 501 is grounded.
  • the control terminal of the three transistors 501 receives the resistance reading signal V3.
  • the resistance reading signal V3 is set to a high level, so that the path of the resistance reading module 50 is opened, and a second voltage is applied to the control end of the anti-fuse memory cell to be programmed.
  • the current of the anti-fuse memory cell determines the resistance value of the anti-fuse memory cell.
  • the fuse resistance of the programmed anti-fuse memory cell is low, and the current flowing through the anti-fuse memory cell is relatively large, for example, it can be tens to hundreds of microamps;
  • the fuse resistance of the programmed anti-fuse memory cell is large, and the current flowing through the anti-fuse memory cell is small, for example, a few nanoamps.
  • the method further includes: controlling a precharge unit to perform precharge protection on the unprogrammed antifuse memory unit 101 on the bit line.
  • the precharge unit includes a second switch 103, a first pole of the second switch 103 is connected to the bit line, a second pole of the second switch 103 receives the precharge voltage VPRE, and the control of the second switch 103
  • the terminal receives the column address signal Pn (Pn is the column address signal received by the control terminal of the second switch corresponding to the different bit line).
  • Pn is the column address signal received by the control terminal of the second switch corresponding to the different bit line).
  • the VPRE voltage received by the second switch is used to protect the unprogrammed antifuse memory cells.
  • the bit line where the unprogrammed antifuse memory cells are located will be precharged to the VPRE voltage; this can avoid unprogrammed antifuses.
  • the wire storage unit is damaged.
  • the programming control module provides the programming current for the anti-fuse memory cell, and the programming control module can perform current-limiting control on the programming current, so that the resistance distribution of the programmed anti-fuse memory cell is more concentrated. In this way, there is It is beneficial for the subsequent readout module to read the data stored in the anti-fuse memory unit, and the response speed requirement of the readout module, that is, the amplifier is reduced, which can save current and reduce power consumption.

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Abstract

一种反熔丝存储阵列电路及其操作方法以及存储器，其中，所述反熔丝存储阵列电路，包括：至少一个反熔丝存储阵列（10），所述反熔丝存储阵列包括多个反熔丝存储单元；编程控制模块（20），连接所述至少一个反熔丝存储阵列（10），配置为在对所述反熔丝存储单元进行编程时提供固定的编程电流。

Description

一种反熔丝存储阵列电路及其操作方法以及存储器
相关的交叉引用
本公开基于申请号为202210255882.0、申请日为2022年03月15日、发明名称为“一种反熔丝存储阵列电路及其操作方法以及存储器”的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本公开作为参考。
技术领域
本公开涉及集成电路技术领域，尤其涉及一种反熔丝存储阵列电路及其操作方法以及存储器。
背景技术
基于反熔丝(Anti-fuse)技术的一次可编程器件被广泛应用于各类芯片中，例如DRAM芯片中利用反熔丝可编程存储器可以存储具有缺陷的存储单元地址信息，进而实现冗余替换(包括行替换和列替换)；也可以通过对反熔丝可编程存储器进行编程，进而实现对芯片内部各种参数(例如电压、电流、频率…)的精确修调。在芯片上电启动时，反熔丝可编程存储器中存储的信息会通过内置的传输电路进行发送并锁存在需要用到的地方。
但是，目前的反熔丝可编程存储器在读取数据时，需要响应速度较快的灵敏放大器，功耗消耗大。
发明内容
有鉴于此，本公开实施例提供一种反熔丝存储阵列电路及其操作方法以及存储器。
根据本公开实施例的第一方面，提供了一种反熔丝存储阵列电路，包括：
至少一个反熔丝存储阵列，所述反熔丝存储阵列包括多个反熔丝存储单元；
编程控制模块，连接所述至少一个反熔丝存储阵列，配置为在对所述反熔丝存储单元进行编程时提供固定的编程电流。
在一些实施例中，还包括：
所述反熔丝存储阵列包括多条沿第一方向延伸且沿第二方向排布的位线，每条所述位线上连接有多个所述反熔丝存储单元，且同一所述反熔丝存储阵列中的每条所述位线分别通过不同的第一开关连接至第一节点，所述第一开关的控制端接收列地址信号，所述编程控制模块连接所述第一节点，配置为在对所述反熔丝存储单元进行编程时向所述第一节点提供所述编程电流。
在一些实施例中，所述编程电流的范围为0.2mA-1mA。
在一些实施例中，所述编程控制模块包括第一电流镜电路和至少一个第一晶体管；所述第一晶体管的第一极连接一个所述反熔丝存储阵列的第一节点，所述第一晶体管的第二极连接所述第一电流镜电路的输出端，所述第一晶体管的控制端接收编程控制信号。
在一些实施例中，还包括：
逻辑读取模块，连接所述第一节点，配置为在对所述反熔丝存储单元进行读取时提供固定的读取电流；
读出模块，连接所述第一节点，配置为读出所述反熔丝存储单元存储的数据。
在一些实施例中，所述读取电流的范围为1μA-20μA。
在一些实施例中，所述逻辑读取模块包括第二电流镜电路和第二晶体 管；所述第二晶体管的第一极连接所述第一节点，所述第二晶体管的第二极连接所述第二电流镜电路的输出端，所述第二晶体管的控制端接收逻辑读取信号。
在一些实施例中，所述读出模块包括放大器，所述放大器的第一输入端连接所述第一节点，所述放大器的第二输入端连接标准电压；其中，所述第一节点的电压值和标准电压的比较结果为所述反熔丝存储单元存储的数据。
在一些实施例中，还包括：
电阻读取模块，连接所述第一节点，配置为在电阻读取模式下读取所述反熔丝存储单元的电阻值。
在一些实施例中，所述电阻读取模块包括第三晶体管，所述第三晶体管的第一极连接所述第一节点，所述第三晶体管的第二极接地，所述第三晶体管的控制端接收电阻读取信号。
在一些实施例中，每条所述位线连接有预充电单元，配置为对所述位线上未编程的反熔丝存储单元进行预充电保护。
在一些实施例中，所述预充电单元包括第二开关，所述第二开关的第一极连接所述位线，所述第二开关的第二极接收预充电电压，所述第二开关的控制端接收所述列地址信号。
在一些实施例中，所述第一开关包括N型晶体管，所述第二开关包括P型晶体管。
在一些实施例中，所述反熔丝存储单元包括第一反熔丝存储晶体管、第四晶体管、第五晶体管和第二反熔丝存储晶体管；
所述第四晶体管和第五晶体管分别通过相邻两根字线控制；
所述第一反熔丝存储晶体管和第二反熔丝存储晶体管分别通过两根编程导线控制；
所述第一反熔丝存储晶体管的第一极连接所述第四晶体管的第一极；
所述第二反熔丝存储晶体管的第一极连接所述第五晶体管的第一极；
所述第四晶体管的第二极连接所述第五晶体管的第二极，且所述第四晶体管的第二极和所述第五晶体管的第二极连接所述位线。
根据本公开实施例的第二方面，提供了一种存储器，包括如上述实施例中任一项所述的反熔丝存储阵列电路。
根据本公开实施例的第三方面，提供一种反熔丝存储阵列电路的操作方法，包括：
对所述反熔丝存储阵列进行编程；
控制编程控制模块向所述反熔丝存储阵列提供固定的编程电流。
在一些实施例中，所述方法还包括：
对所述反熔丝存储阵列进行读取；
控制逻辑读取模块向所述反熔丝存储阵列提供固定的读取电流。
本公开实施例中，通过编程控制模块为反熔丝存储单元提供编程电流，编程控制模块可以对编程电流进行限流控制，使得编程后的反熔丝存储单元的电阻分布更集中，如此，有利于后续读出模块对反熔丝存储单元存储的数据的读取，对读出模块，也即放大器的响应速度要求降低，可以节省电流，降低功耗。
附图说明
为了更清楚地说明本公开实施例或传统技术中的技术方案，下面将对实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为一些实施例中提供的反熔丝存储阵列电路的电路图；
图2为本公开实施例提供的反熔丝存储阵列电路的结构示意图；
图3为本公开实施例提供的反熔丝存储阵列的电路图；
图4为本公开实施例提供的反熔丝存储阵列电路的电路图；
图5为本公开另一实施例提供的反熔丝存储阵列电路的电路图；
图6为本公开实施例提供的反熔丝存储阵列电路的操作方法的流程示意图。
附图标记说明：
10-反熔丝存储阵列；101-反熔丝存储单元；101-1-第一反熔丝存储晶体管；101-2-第四晶体管；101-3-第五晶体管；101-4-第二反熔丝存储晶体管；102-第一开关；103-第二开关；
20-编程控制模块；201-第一电流镜电路；202-第一晶体管；
30-逻辑读取模块；301-第二电流镜电路；302-第二晶体管；
40-读出模块；401-放大器；
50-电阻读取模块；501-第三晶体管。
具体实施方式
下面将参照附图更详细地描述本公开公开的示例性实施方式。虽然附图中显示了本公开的示例性实施方式，然而应当理解，可以以各种形式实现本公开，而不应被这里阐述的具体实施方式所限制。相反，提供这些实施方式是为了能够更透彻地理解本公开，并且能够将本公开公开的范围完整的传达给本领域的技术人员。
在下文的描述中，给出了大量具体的细节以便提供对本公开更为彻底的理解。然而，对于本领域技术人员而言显而易见的是，本公开可以无需一个或多个这些细节而得以实施。在其他的例子中，为了避免与本公开发生混淆，对于本领域公知的一些技术特征未进行描述；即，这里不描述实际实施例的全部特征，不详细描述公知的功能和结构。
在附图中，为了清楚，层、区、元件的尺寸以及其相对尺寸可能被夸 大。自始至终相同附图标记表示相同的元件。
应当明白，当元件或层被称为“在……上”、“与……相邻”、“连接到”或“耦合到”其它元件或层时，其可以直接地在其它元件或层上、与之相邻、连接或耦合到其它元件或层，或者可以存在居间的元件或层。相反，当元件被称为“直接在……上”、“与……直接相邻”、“直接连接到”或“直接耦合到”其它元件或层时，则不存在居间的元件或层。应当明白，尽管可使用术语第一、第二、第三等描述各种元件、部件、区、层和/或部分，这些元件、部件、区、层和/或部分不应当被这些术语限制。这些术语仅仅用来区分一个元件、部件、区、层或部分与另一个元件、部件、区、层或部分。因此，在不脱离本公开教导之下，下面讨论的第一元件、部件、区、层或部分可表示为第二元件、部件、区、层或部分。而当讨论第二元件、部件、区、层或部分时，并不表明本公开必然存在第一元件、部件、区、层或部分。
空间关系术语例如“在……下”、“在……下面”、“下面的”、“在……之下”、“在……之上”、“上面的”等，在这里可为了方便描述而被使用从而描述图中所示的一个元件或特征与其它元件或特征的关系。应当明白，除了图中所示的取向以外，空间关系术语意图还包括使用和操作中的器件的不同取向。例如，如果附图中的器件翻转，然后，描述为“在其它元件下面”或“在其之下”或“在其下”元件或特征将取向为在其它元件或特征“上”。因此，示例性术语“在……下面”和“在……下”可包括上和下两个取向。器件可以另外地取向(旋转90度或其它取向)并且在此使用的空间描述语相应地被解释。
在此使用的术语的目的仅在于描述具体实施例并且不作为本公开的限制。在此使用时，单数形式的“一”、“一个”和“所述/该”也意图包括复数形式，除非上下文清楚指出另外的方式。还应明白术语“组成”和/或“包 括”，当在该说明书中使用时，确定所述特征、整数、步骤、操作、元件和/或部件的存在，但不排除一个或更多其它的特征、整数、步骤、操作、元件、部件和/或组的存在或添加。在此使用时，术语“和/或”包括相关所列项目的任何及所有组合。
为了彻底理解本公开，将在下列的描述中提出详细的步骤以及详细的结构，以便阐释本公开的技术方案。本公开的较佳实施例详细描述如下，然而除了这些详细描述外，本公开还可以具有其他实施方式。
在一些实施例中，如图1所示，反熔丝存储阵列中的行地址(XADD_n)与编程线(PGM_n)同相位；在编程模式下，目标单元的行地址被选中置高电位，目标位线(BLn)被置低电位；PGM_n置高电压从而在目标熔丝单元的栅极与漏极之间建立强电场，从而将栅氧化层击穿形成阻值较小的电阻。
如图1所示，在对反熔丝存储阵列中的熔丝单元进行状态读取时，通常采用预充电-放电(Precharge-discharge)的方式，对数据的锁存时间以及灵敏放大器(sense amplifier)的响应速度要求较高，需要响应速度较快的灵敏放大器才能准确读取熔丝存储的数据。
基于此，本公开实施例提供了一种反熔丝存储阵列电路，图2为本公开实施例提供的反熔丝存储阵列电路的结构示意图；图3为本公开实施例提供的反熔丝存储阵列的电路图；图4为本公开实施例提供的反熔丝存储阵列电路的电路图。
参见图2至图4，所述反熔丝存储阵列电路，包括：至少一个反熔丝存储阵列10，所述反熔丝存储阵列10包括多个反熔丝存储单元101；编程控制模块20，连接所述至少一个反熔丝存储阵列10，配置为在对所述反熔丝存储单元101进行编程时提供固定的编程电流IPGM。
本公开实施例中，通过编程控制模块为反熔丝存储单元提供编程电流， 编程控制模块可以对编程电流进行限流控制，使得编程后的反熔丝存储单元的电阻分布更集中，如此，有利于后续读出模块对反熔丝存储单元存储的数据的读取，对读出模块，也即放大器的响应速度要求降低，可以节省电流，降低功耗。
参见图3和图4，所述反熔丝存储阵列10包括多条沿第一方向延伸且沿第二方向排布的位线BLn(n为对应位线的序号)，每条所述位线上连接有多个所述反熔丝存储单元101，且位于同一反熔丝存储阵列10中的每条所述位线分别通过不同的第一开关102连接至第一节点N1，不同的反熔丝存储阵列10中的位线连接至不同的第一节点，所述第一开关102的控制端接收列地址信号Yn(Yn为对应不同位线上的第一开关的控制端接收到的列地址信号)，所述编程控制模块20连接所述第一节点N1，配置为在对所述反熔丝存储单元101进行编程时向所述第一节点N1提供所述编程电流IPGM。
所述第一开关102包括N型晶体管。
在一实施例中，所述编程电流IPGM的范围为0.2mA-1mA。更具体的，所述编程电流IPGM可以为0.6mA。
编程电流IPGM在此范围内，反熔丝存储单元的编程效果最好，否则，若编程电流小于0.2mA，则可能会导致对反熔丝存储单元的编程不彻底，若编程电流大于1mA，又会导致过热，从而对邻近的其他需要编程的反熔丝存储单元产生破坏。
如图4所示，所述编程控制模块20包括第一电流镜电路201和至少一个第一晶体管202；所述第一晶体管202的第一极连接一个所述反熔丝存储阵列10的第一节点N1，所述第一晶体管202的第二极连接所述第一电流镜电路201的输出端，所述第一晶体管202的控制端接收编程控制信号V1。
所述第一晶体管202为N型晶体管。
在实际操作中，所述第一晶体管202的控制端接收到的编程控制信号V1置高电平，使所述编程控制模块20的通路打开，对要进行编程的反熔丝存储单元的控制端施加高电压，所述第一电流镜电路201对所述反熔丝存储单元提供编程电流IPGM，以实现对反熔丝存储单元的编程操作。
编程控制模块中的第一电流镜电路能够对编程电流进行限流控制，使得编程后的反熔丝的电阻分布更加集中，如此，可以提高读取反熔丝存储单元存储的数据的准确性。
在一些实施例中，所述编程电流IPGM的典型值可以通过测试模式(test mode)信号(图中未示出)控制。
具体地，对反熔丝存储单元的编程是在芯片测试模式下进行，通过测试模式可以控制编程电流的大小，这样可以实现对编程电流的灵活控制，最终选取最合适的电流进行编程，然后在最终编程的时候，对应测试模式下，合适的电流所对应的信号来控制编程电流的大小。
所述第一电流镜电路201包括一组N型晶体管，所述第一电流镜电路201的输入端连接编程电流IPGM。
在一些实施例中，如图4所示，一个反熔丝存储阵列10与一个编程控制模块20连接。
在其他一些实施例中，如图5所示，多个所述反熔丝存储阵列10连接至一个编程控制模块20；其中，所述编程控制模块20包括一个第一电流镜电路201和至少一个第一晶体管202，每个反熔丝存储阵列10分别通过一个第一晶体管202与所述第一电流镜电路201连接。
由于反熔丝存储单元熔断时所需电流较大，因此作为限流电路的第一电流镜电路的尺寸较大，当反熔丝存储阵列的数目较多时，可以将第一电流镜电路共享；如图5所示，每个反熔丝存储阵列10分别通过一个第一晶体管202进行区分，但是共享同一个第一电流镜电路，节省芯片面积。
所述反熔丝存储阵列电路还包括：逻辑读取模块30，连接所述第一节点N1，配置为在对所述反熔丝存储单元101进行读取时提供固定的读取电流IREAD；读出模块40，连接所述第一节点N1，配置为读出所述反熔丝存储单元101存储的数据。
在一实施例中，所述读取电流IREAD的范围为1μA-20μA。更具体的，所述读取电流IREAD可以为10μA。
读取电流IREAD在此范围内时，能提高读取反熔丝存储单元存储的数据时的准确率。否则，如果读取电流小于1μA时，会使得读取反熔丝存储单元存储的数据时，容易受到干扰，导致读出准确率低；如果读取电流大于20μA，又会使得读出功耗增加。实际的读取电流需要根据反熔丝存储单元编程后的电阻分布进行设置。
如图4所示，所述逻辑读取模块30包括第二电流镜电路301和第二晶体管302；所述第二晶体管302的第一极连接所述第一节点N1，所述第二晶体管302的第二极连接所述第二电流镜电路301的输出端，所述第二晶体管302的控制端接收逻辑读取信号V2。
所述第二晶体管302为N型晶体管。
所述第二电流镜电路301包括一组N型晶体管，所述第二电流镜电路301的输入端连接读取电流IREAD。
在实际操作中，所述第二晶体管的控制端接收到的逻辑读取信号置高电平，使所述逻辑读取模块的通路打开，对要进行编程的反熔丝存储单元的控制端施加第一电压，读取电流IREAD流经反熔丝存储单元，并产生压降(Drop Voltage)。
继续参见图4，所述读出模块40包括放大器401，所述放大器401的第一输入端连接所述第一节点N1，所述放大器401的第二输入端连接标准电压V_REF；其中，所述第一节点N1的电压值和标准电压V_REF的比较 结果为所述反熔丝存储单元101存储的数据。
其中，所述第一节点N1处的电压为公共电压V_Com；所述第一节点N1的电压值和标准电压V_REF的比较结果为所述反熔丝存储单元101存储的数据，包括：公共电压V_Com与标准电压V_REF的比较结果为所述反熔丝存储单元101存储的数据。
在实际操作中，所述放大器的第一输入端为正输入端，所述第二输入端为负输入端；所述公共电压V_Com与标准电压V_REF的比较结果为所述反熔丝存储单元101存储的数据，包括：
当所述反熔丝存储单元发生编程操作时，反熔丝存储单元的熔丝电阻较低，因此该反熔丝存储单元的压降小，所述公共电压V_Com大于所述标准电压V_REF，所述放大器的输出为“1”，得到所述反熔丝存储单元的逻辑状态为高电平；
当所述反熔丝存储单元未发生编程操作时，反熔丝存储单元的熔丝电阻较高，因此该反熔丝存储单元的压降大，所述公共电压V_Com小于所述标准电压V_REF，所述放大器的输出为“0”，得到所述反熔丝存储单元的逻辑状态为低电平。
在本公开实施例中，因为并不使用预充电-放电的方式对反熔丝存储单元存储的数据进行读取，因此，对放大器的响应速度要求较低，可以节省电流，降低功耗。
在一实施例中，所述反熔丝存储阵列电路还包括：电阻读取模块50，连接所述第一节点N1，配置为在电阻读取模式下读取所述反熔丝存储单元101的电阻值。
参见图4，所述电阻读取模块50包括第三晶体管501，所述第三晶体管501的第一极连接所述第一节点N1，所述第三晶体管501的第二极接地，所述第三晶体管501的控制端接收电阻读取信号V3。
在实际操作中，所述电阻读取信号V3置高电平，使所述电阻读取模块50的通路打开，对要进行编程的反熔丝存储单元的控制端施加第二电压，根据流过所述反熔丝存储单元的电流确定该反熔丝存储单元的电阻值。
在一些实施例中，经过编程的反熔丝存储单元的熔丝电阻较低，此时流经该反熔丝存储单元的电流较大，例如可以为几十到几百微安；而未经过编程的反熔丝存储单元的熔丝电阻较大，此时流经该反熔丝存储单元的电流较小，例如为几纳安。
在一实施例中，每条所述位线连接有预充电单元，配置为对所述位线上未编程的反熔丝存储单元101进行预充电保护。
参见图4，所述预充电单元包括第二开关103，所述第二开关103的第一极连接所述位线，所述第二开关103的第二极接收预充电电压VPRE，所述第二开关的控制端接收所述列地址信号Pn(Pn为对应不同位线上的第二开关的控制端接收到的列地址信号，Pn与第一开关102的控制端接收列地址信号Yn可以为同一个信号)。第二开关接收到的VPRE电压用于对未编程的反熔丝存储单元进行保护，未编程的反熔丝存储单元所在的位线将被预充电至VPRE电压；这样可以避免未编程的反熔丝存储单元被损伤。
在一实施例中，所述第二开关包括P型晶体管
参见图3，所述反熔丝存储阵列10包括多个反熔丝存储单元101，所述反熔丝存储单元101包括第一反熔丝存储晶体管101-1、第四晶体管101-2、第五晶体管101-3和第二反熔丝存储晶体管101-4；所述第四晶体管101-2和第五晶体管101-3分别通过相邻两根字线XADD_m(m为对应字线的序号)控制；所述第一反熔丝存储晶体管101-1和第二反熔丝存储晶体管101-4分别通过两根编程导线PGM_m控制；所述第一反熔丝存储晶体管101-1的第一极连接所述第四晶体管101-2的第一极；所述第二反熔丝存储晶体管101-4的第一极连接所述第五晶体管101-3的第一极；所述第四晶体 管101-2的第二极连接所述第五晶体管101-3的第二极，且所述第四晶体管101-2的第二极和所述第五晶体管101-3的第二极连接所述位线。
具体地，结合图3和图4，所述反熔丝存储阵列为16*16的反熔丝存储阵列，即该反熔丝存储阵列包括16根位线BL和16根字线PGM，因此，在图3和图4所示的实施例中，每根位线上一共连接有8个反熔丝存储单元101，即图中显示的out1至out8。
本公开实施例还提供了一种存储器，所述存储器包括如上述任一实施例中所述的反熔丝存储阵列电路。
本公开实施例还提供了一种反熔丝存储阵列电路的操作方法，具体请参见图6，如图6所示，所述操作方法包括以下步骤：
步骤601：对所述反熔丝存储阵列进行编程；
步骤602：控制编程控制模块向所述反熔丝存储阵列提供固定的编程电流。
下面结合具体实施例对本公开实施例提供的反熔丝存储阵列电路的操作方法再作进一步详细的说明。
首先，参见图4，执行步骤601和步骤602，对所述反熔丝存储阵列10进行编程；控制编程控制模块20向所述反熔丝存储阵列10提供固定的编程电流。
在一实施例中，所述反熔丝存储阵列包括多个反熔丝存储单元101；编程控制模块20，连接所述至少一个反熔丝存储阵列10。
所述反熔丝存储阵列10包括多条沿第一方向延伸且沿第二方向排布的位线BLn(n为对应位线的序号)，每条所述位线上连接有多个所述反熔丝存储单元101，且位于同一反熔丝存储阵列10中的每条所述位线分别通过不同的第一开关102连接至第一节点N1，所述第一开关102的控制端接收列地址信号Yn(Yn为对应不同位线上的第一开关的控制端接收到的列地 址信号)，所述编程控制模块20连接所述第一节点N1，配置为在对所述反熔丝存储单元101进行编程时向所述第一节点N1提供所述编程电流IPGM。
在一实施例中，所述编程电流IPGM的范围为0.2mA-1mA。更具体的，所述编程电流IPGM可以为0.6mA。
编程电流IPGM在此范围内，反熔丝存储单元的编程效果最好，否则，若编程电流小于0.2mA，则可能会导致对反熔丝存储单元的编程不彻底，若编程电流大于1mA，又会导致过热，从而对邻近的其他需要编程的反熔丝存储单元产生破坏。
如图4所示，所述编程控制模块20包括第一电流镜电路201和至少一个第一晶体管202；所述第一晶体管202的第一极连接一个所述反熔丝存储阵列10的第一节点N1，所述第一晶体管202的第二极连接所述第一电流镜电路201的输出端，所述第一晶体管202的控制端接收编程控制信号V1。
在实际操作中，所述第一晶体管202的控制端接收到的编程控制信号V1置高电平，使所述编程控制模块20的通路打开，对要进行编程的反熔丝存储单元的控制端施加高电压，所述第一电流镜电路201对所述反熔丝存储单元提供编程电流IPGM，以实现对反熔丝存储单元的编程操作。
编程控制模块中的第一电流镜电路能够对编程电流进行限流控制，使得编程后的反熔丝的电阻分布更加集中，如此，可以提高读取反熔丝存储单元存储的数据的准确性。
在一些实施例中，如图4所示，一个反熔丝存储阵列10与一个编程控制模块20连接。
在其他一些实施例中，如图5所示，多个所述反熔丝存储阵列10连接至一个编程控制模块20；其中，所述编程控制模块20包括一个第一电流镜电路201和多个第一晶体管202，每个反熔丝存储阵列10分别通过一个第一晶体管202与所述第一电流镜电路201连接。
由于反熔丝存储单元熔断时所需电流较大，因此作为限流电路的第一电流镜电路的尺寸较大，当反熔丝存储阵列的数目较多时，可以将第一电流镜电路共享；如图5所示，每个反熔丝存储阵列10分别通过一个第一晶体管202进行区分，但是共享同一个第一电流镜电路，节省芯片面积。
接着，继续参见图4，所述方法还包括：对所述反熔丝存储阵列10进行读取；控制逻辑读取模块30向所述反熔丝存储阵列10提供固定的读取电流。
在一实施例中，所述读取电流IREAD的范围为1μA-20μA。更具体的，所述读取电流IREAD可以为10μA。
读取电流IREAD在此范围内时，能提高读取反熔丝存储单元存储的数据时的准确率。否则，如果读取电流小于1μA时，会使得读取反熔丝存储单元存储的数据时，容易受到干扰，导致读出准确率低；如果读取电流大于20μA，又会使得读出功耗增加。实际的读取电流需要根据反熔丝存储单元编程后的电阻分布进行设置。
如图4所示，所述逻辑读取模块30包括第二电流镜电路301和第二晶体管302；所述第二晶体管302的第一极连接所述第一节点N1，所述第二晶体管302的第二极连接所述第二电流镜电路301的输出端，所述第二晶体管302的控制端接收逻辑读取信号V2。
在实际操作中，所述第二晶体管的控制端接收到的逻辑读取信号置高电平，使所述逻辑读取模块的通路打开，对要进行编程的反熔丝存储单元的控制端施加第一电压，读取电流IREAD流经反熔丝存储单元，并产生压降(Drop Voltage)。
接着，继续参见图4，所述方法还包括：控制读出模块40根据第一节点N1的电压值和标准电压V_REF的比较结果，得到所述反熔丝存储单元101存储的数据。
其中，所述第一节点N1处的电压为公共电压V_Com；所述根据第一节点N1的电压值和标准电压V_REF的比较结果，得到所述反熔丝存储单元101存储的数据，包括：根据公共电压V_Com与标准电压V_REF的比较结果，得到所述反熔丝存储单元101存储的数据。
在实际操作中，所述放大器的第一输入端为正输入端，所述第二输入端为负输入端；所述根据公共电压V_Com与标准电压V_REF的比较结果，得到所述反熔丝存储单元101存储的数据，包括：
当所述反熔丝存储单元发生编程操作时，反熔丝存储单元的熔丝电阻较低，因此该反熔丝存储单元的压降小，所述公共电压V_Com大于所述标准电压V_REF，所述放大器的输出为“1”，得到所述反熔丝存储单元的逻辑状态为高电平；
当所述反熔丝存储单元未发生编程操作时，反熔丝存储单元的熔丝电阻较高，因此该反熔丝存储单元的压降大，所述公共电压V_Com小于所述标准电压V_REF，所述放大器的输出为“0”，得到所述反熔丝存储单元的逻辑状态为低电平。
在本公开实施例中，因为并不使用预充电-放电的方式对反熔丝存储单元存储的数据进行读取，因此，对放大器的响应速度要求较低，可以节省电流，降低功耗。
接着，继续参见图4，所述方法还包括：控制电阻读取模块50在电阻读取模式下读取所述反熔丝存储单元101的电阻值。
参见图4，所述电阻读取模块50包括第三晶体管501，所述第三晶体管501的第一极连接所述第一节点N1，所述第三晶体管501的第二极接地，所述第三晶体管501的控制端接收电阻读取信号V3。
在实际操作中，所述电阻读取信号V3置高电平，使所述电阻读取模块50的通路打开，对要进行编程的反熔丝存储单元的控制端施加第二电压， 根据流过所述反熔丝存储单元的电流确定该反熔丝存储单元的电阻值。
在一些实施例中，经过编程的反熔丝存储单元的熔丝电阻较低，此时流经该反熔丝存储单元的电流较大，例如可以为几十到几百微安；而未经过编程的反熔丝存储单元的熔丝电阻较大，此时流经该反熔丝存储单元的电流较小，例如为几纳安。
参见图4，所述方法还包括：控制预充电单元对所述位线上未编程的反熔丝存储单元101进行预充电保护
所述预充电单元包括第二开关103，所述第二开关103的第一极连接所述位线，所述第二开关103的第二极接收预充电电压VPRE，所述第二开关的控制端接收所述列地址信号Pn(Pn为对应不同位线上的第二开关的控制端接收到的列地址信号)。第二开关接收到的VPRE电压用于对未编程的反熔丝存储单元进行保护，未编程的反熔丝存储单元所在的位线将被预充电至VPRE电压；这样可以避免未编程的反熔丝存储单元被损伤。
以上所述，仅为本公开的较佳实施例而已，并非用于限定本公开的保护范围，凡在本公开的精神和原则之内所作的任何修改、等同替换和改进等，均应包含在本公开的保护范围之内。
工业实用性
本公开实施例中，通过编程控制模块为反熔丝存储单元提供编程电流，编程控制模块可以对编程电流进行限流控制，使得编程后的反熔丝存储单元的电阻分布更集中，如此，有利于后续读出模块对反熔丝存储单元存储的数据的读取，对读出模块，也即放大器的响应速度要求降低，可以节省电流，降低功耗。

Claims (17)

  1. 一种反熔丝存储阵列电路，包括：
    至少一个反熔丝存储阵列，所述反熔丝存储阵列包括多个反熔丝存储单元；
    编程控制模块，连接所述至少一个反熔丝存储阵列，配置为在对所述反熔丝存储单元进行编程时提供固定的编程电流。
  2. 根据权利要求1所述的反熔丝存储阵列电路，其中，还包括：
    所述反熔丝存储阵列包括多条沿第一方向延伸且沿第二方向排布的位线，每条所述位线上连接有多个所述反熔丝存储单元，且同一所述反熔丝存储阵列中的每条所述位线分别通过不同的第一开关连接至第一节点，所述第一开关的控制端接收列地址信号，所述编程控制模块连接所述第一节点，配置为在对所述反熔丝存储单元进行编程时向所述第一节点提供所述编程电流。
  3. 根据权利要求2所述的反熔丝存储阵列电路，其中，
    所述编程电流的范围为0.2mA-1mA。
  4. 根据权利要求2所述的反熔丝存储阵列电路，其中，所述编程控制模块包括第一电流镜电路和至少一个第一晶体管；所述第一晶体管的第一极连接一个所述反熔丝存储阵列的第一节点，所述第一晶体管的第二极连接所述第一电流镜电路的输出端，所述第一晶体管的控制端接收编程控制信号。
  5. 根据权利要求2所述的反熔丝存储阵列电路，其中，还包括：
    逻辑读取模块，连接所述第一节点，配置为在对所述反熔丝存储单元进行读取时提供固定的读取电流；
    读出模块，连接所述第一节点，配置为读出所述反熔丝存储单元存储的数据。
  6. 根据权利要求5所述的反熔丝存储阵列电路，其中，所述读取电流的范围为1μA-20μA。
  7. 根据权利要求5所述的反熔丝存储阵列电路，其中，
    所述逻辑读取模块包括第二电流镜电路和第二晶体管；所述第二晶体管的第一极连接所述第一节点，所述第二晶体管的第二极连接所述第二电流镜电路的输出端，所述第二晶体管的控制端接收逻辑读取信号。
  8. 根据权利要求5所述的反熔丝存储阵列电路，其中，
    所述读出模块包括放大器，所述放大器的第一输入端连接所述第一节点，所述放大器的第二输入端连接标准电压；其中，所述第一节点的电压值和标准电压的比较结果为所述反熔丝存储单元存储的数据。
  9. 根据权利要求2所述的反熔丝存储阵列电路，其中，还包括：
    电阻读取模块，连接所述第一节点，配置为在电阻读取模式下读取所述反熔丝存储单元的电阻值。
  10. 根据权利要求9所述的反熔丝存储阵列电路，其中，所述电阻读取模块包括第三晶体管，所述第三晶体管的第一极连接所述第一节点，所述第三晶体管的第二极接地，所述第三晶体管的控制端接收电阻读取信号。
  11. 根据权利要求2所述的反熔丝存储阵列电路，其中，
    每条所述位线连接有预充电单元，配置为对所述位线上未编程的反熔丝存储单元进行预充电保护。
  12. 根据权利要求11所述的反熔丝存储阵列电路，其中，所述预充电单元包括第二开关，所述第二开关的第一极连接所述位线，所述第二开关的第二极接收预充电电压，所述第二开关的控制端接收所述列地址信号。
  13. 根据权利要求12所述的反熔丝存储阵列电路，其中，所述第一开关包括N型晶体管，所述第二开关包括P型晶体管。
  14. 根据权利要求2所述的反熔丝存储阵列电路，其中，
    所述反熔丝存储单元包括第一反熔丝存储晶体管、第四晶体管、第五晶体管和第二反熔丝存储晶体管；
    所述第四晶体管和第五晶体管分别通过相邻两根字线控制；
    所述第一反熔丝存储晶体管和第二反熔丝存储晶体管分别通过两根编程导线控制；
    所述第一反熔丝存储晶体管的第一极连接所述第四晶体管的第一极；
    所述第二反熔丝存储晶体管的第一极连接所述第五晶体管的第一极；
    所述第四晶体管的第二极连接所述第五晶体管的第二极，且所述第四晶体管的第二极和所述第五晶体管的第二极连接所述位线。
  15. 一种存储器，包括如权利要求1-14中任一项所述的反熔丝存储阵列电路。
  16. 一种反熔丝存储阵列电路的操作方法，包括：
    对所述反熔丝存储阵列进行编程；
    控制编程控制模块向所述反熔丝存储阵列提供固定的编程电流。
  17. 根据权利要求16所述的方法，其中，所述方法还包括：
    对所述反熔丝存储阵列进行读取；
    控制逻辑读取模块向所述反熔丝存储阵列提供固定的读取电流。
PCT/CN2022/098713 2022-03-15 2022-06-14 一种反熔丝存储阵列电路及其操作方法以及存储器 WO2023173608A1 (zh)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5353028A (en) * 1992-05-14 1994-10-04 Texas Instruments Incorporated Differential fuse circuit and method utilized in an analog to digital converter
CN107293328A (zh) * 2017-05-05 2017-10-24 上海华力微电子有限公司 一种采用电流编程的电子可编程熔丝电路结构
CN112582013A (zh) * 2019-09-29 2021-03-30 长鑫存储技术有限公司 反熔丝存储单元电路、阵列电路及其读写方法
CN113948141A (zh) * 2020-07-16 2022-01-18 长鑫存储技术有限公司 反熔丝存储单元状态检测电路及存储器

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5353028A (en) * 1992-05-14 1994-10-04 Texas Instruments Incorporated Differential fuse circuit and method utilized in an analog to digital converter
CN107293328A (zh) * 2017-05-05 2017-10-24 上海华力微电子有限公司 一种采用电流编程的电子可编程熔丝电路结构
CN112582013A (zh) * 2019-09-29 2021-03-30 长鑫存储技术有限公司 反熔丝存储单元电路、阵列电路及其读写方法
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