WO2023173505A1 - 一种半导体器件的制备方法及半导体器件 - Google Patents

一种半导体器件的制备方法及半导体器件 Download PDF

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WO2023173505A1
WO2023173505A1 PCT/CN2022/084584 CN2022084584W WO2023173505A1 WO 2023173505 A1 WO2023173505 A1 WO 2023173505A1 CN 2022084584 W CN2022084584 W CN 2022084584W WO 2023173505 A1 WO2023173505 A1 WO 2023173505A1
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layer
conductive layer
region
gate
resistive
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PCT/CN2022/084584
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English (en)
French (fr)
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王剑屏
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长鑫存储技术有限公司
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Priority to US17/846,131 priority Critical patent/US20230299074A1/en
Publication of WO2023173505A1 publication Critical patent/WO2023173505A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
    • H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
    • H01L27/0629—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with diodes, or resistors, or capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/20—Resistors
    • H01L28/24—Resistors with an active material comprising a refractory, transition or noble metal, metal compound or metal alloy, e.g. silicides, oxides, nitrides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4966—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2

Definitions

  • the present disclosure relates to the field of semiconductor manufacturing, and in particular, to a method of manufacturing a semiconductor device and a semiconductor device.
  • gate structures and resistor structures are very important components.
  • the traditional process multiple different processes are required to form the gate structure and the resistor structure respectively, and the process is relatively complex. Therefore, how to optimize the preparation process of the gate structure and resistor structure has become an urgent problem that needs to be solved.
  • Embodiments of the present disclosure provide a method for manufacturing a semiconductor device, including:
  • the substrate including a first region and a second region
  • the stacked material layer including a first dielectric layer, a first conductive layer and a second conductive layer from bottom to top;
  • the first conductive layer remaining under the second gate layer constitutes the first gate layer
  • the first conductive layer remaining in the middle part of the second area and the first conductive layer remaining under the resistive contact part constitute the resistor layer
  • the resistive layer and the resistive contact portion form a resistor structure.
  • the method before performing the second etching process on the stacked material layer, the method further includes:
  • An etching process is performed on the mask layer, the mask layer located in the middle part of the second region is retained, and the mask layer on the first region and the mask layer on other regions of the second region except the middle part are removed.
  • the method further includes: removing the mask layer located in the second region.
  • the method further includes: forming a first contact and a second contact above both ends of the resistor structure.
  • the method before forming the first contact and the second contact, the method further includes:
  • An etching process is performed on the second dielectric layer to form first insulating spacers on both sides of the first gate layer and the second gate layer, and to form first insulating spacers on both sides of the resistor structure. Second insulating spacer.
  • the method before forming the stacked material layer on the substrate, the method further includes: forming a shallow trench isolation structure on the second area of the substrate, and the resistor structure is located in the shallow trench. Isolation structure.
  • the material of the first conductive layer includes transition metal nitride; the material of the second conductive layer includes polysilicon.
  • the thickness of the first conductive layer ranges from 1 nm to 10 nm.
  • the stacked material layer further includes a third conductive layer, and the third conductive layer is located on the second conductive layer; performing the first etching process on the stacked material layer further includes: removing the layer located on the second conductive layer. The two ends of the first region and the third conductive layer located in the middle part of the second region.
  • the stacked material layer further includes a buffer conductive layer, the buffer conductive layer is located between the second conductive layer and the third conductive layer; a first etching process is performed on the stacked material layer It also includes: removing the buffer conductive layer located at both ends of the first region and at a middle portion of the second region.
  • An embodiment of the present disclosure also provides a semiconductor device, including:
  • the substrate including a first region and a second region
  • a first dielectric layer, the first dielectric layer is located on the substrate;
  • a first gate layer and a second gate layer the first gate layer is located on the first dielectric layer in the first region, the second gate layer is located on the first gate layer ;
  • a resistor structure is located on the first dielectric layer in the second region.
  • the resistor structure includes a resistive layer and a resistive contact portion.
  • the resistive contact portion is located above the resistive layer and disposed on the resistor. Both ends of the layer, and the lower part of the resistive contact part is in contact with the upper surface of the two ends of the resistive layer;
  • first gate layer and the resistance layer are made of the same material
  • second gate layer and the resistance contact part are made of the same material
  • the material of the first dielectric layer includes a high-K dielectric material.
  • the material of the first gate layer and the resistance layer includes transition metal nitride; the material of the second gate layer and the resistance contact portion includes polysilicon.
  • the semiconductor device further includes a first contact and a second contact located above both ends of the resistor structure.
  • the thickness of the first gate layer and the resistance layer ranges from 1 nm to 10 nm.
  • the semiconductor device further includes a third conductive layer, and the third conductive layer is located on the second gate layer and the resistive contact portion.
  • the semiconductor device further includes a first insulating spacer and a second insulating spacer; wherein the first insulating spacer is located on both sides of the first gate layer and the second gate layer. , the second insulating spacers are located on both sides of the resistor structure.
  • the semiconductor device further includes a buffer conductive layer located between the third conductive layer and the second gate layer, and between the third conductive layer and the resistive contact layer. between departments.
  • Embodiments of the present disclosure provide a method for preparing a semiconductor device and a semiconductor device, wherein the method includes: providing a substrate, the substrate including a first region and a second region; forming a stacked material layer on the substrate, The stacked material layer includes a first dielectric layer, a first conductive layer and a second conductive layer from bottom to top; perform a first etching process on the stacked material layer to remove the The second conductive layer is located in the middle part of the second region, so that the first conductive layer is exposed from both ends of the first region and from the middle part of the second region; wherein, the first conductive layer remains in the middle part of the second region.
  • the second conductive layer in the middle part of the first region constitutes the second gate layer, and the second conductive layer remaining at both ends of the second region constitutes the resistive contact part; perform a second etching on the stacked material layer process, retaining the first conductive layer located under the second gate layer, the resistive contact portion and the first conductive layer located in the middle part of the second region; wherein, retaining the first conductive layer located under the second gate layer A conductive layer constitutes the first gate layer, the first conductive layer remaining in the middle part of the second region and the first conductive layer remaining below the resistive contact portion form a resistance layer, the resistance layer is connected to the resistance contact portion form a resistor structure.
  • the second gate layer and the resistor contact are formed through the first etching process, and the first gate layer and the resistor are formed through the second etching process.
  • layer wherein, the first gate layer and the second gate layer can serve as the gate electrode of the semiconductor device, and the resistance contact portion and the resistance layer together form a resistor structure.
  • the gate structure and the resistor structure can be formed simultaneously through two etching processes, making the process of forming the gate structure and the process of forming the resistor structure compatible, and simplifying the process of forming the gate structure and the resistor structure. Process flow. Therefore, in the embodiments of the present disclosure, the process of forming the gate structure is compatible with the process of forming the resistor structure, which can effectively simplify the production process and significantly improve production efficiency.
  • Figure 1 is a flow chart of a method for manufacturing a semiconductor device provided by an embodiment of the present disclosure
  • gate structures and resistor structures are very important structures.
  • part of the structure includes a polysilicon layer, but this polysilicon layer has a low resistivity and is not suitable as the bulk of the resistor.
  • the resistor body part can be obtained by reforming a polysilicon layer and performing a doping process on it.
  • the gate structure and the resistor structure are usually formed in different processes, which increases the complexity of the process and is not conducive to the improvement of production efficiency.
  • An embodiment of the present disclosure provides a method for manufacturing a semiconductor device. Please see Figure 1 for details. As shown in the figure, the method includes the following steps:
  • Step 101 Provide a substrate, the substrate including a first region and a second region;
  • Step 102 Form a stacked material layer on the substrate, the stacked material layer includes a first dielectric layer, a first conductive layer and a second conductive layer from bottom to top;
  • Step 103 Perform a first etching process on the stacked material layer to remove the second conductive layer located at both ends of the first region and the middle portion of the second region, so that the first conductive layer The layer is exposed from both ends of the first region and from the middle part of the second region; wherein the second conductive layer remaining in the middle part of the first region constitutes a second gate layer, and the second conductive layer remaining in the middle part of the first region constitutes a second gate layer.
  • the second conductive layer at both ends of the second region constitutes a resistive contact portion;
  • Step 104 Perform a second etching process on the stacked material layer, retaining the first conductive layer located under the second gate layer, the resistive contact portion and the first conductive layer located in the middle part of the second region.
  • Conductive layer wherein, the first conductive layer remaining under the second gate layer constitutes the first gate layer, the first conductive layer remaining in the middle part of the second region and the first conductive layer remaining under the resistive contact portion
  • the resistive layer forms a resistive layer, which together with the resistive contact forms a resistor structure.
  • an etching process is performed on the stacked material layer: the second gate layer and the resistive contact portion are formed through the first etching process, and the third gate layer and the resistive contact portion are formed through the second etching process.
  • the gate structure and the resistor structure can be formed simultaneously through two etching processes, making the process of forming the gate structure and the process of forming the resistor structure compatible, and simplifying the process of forming the gate structure and the resistor structure. Process flow. Therefore, in the embodiments of the present disclosure, the process of forming the gate structure is compatible with the process of forming the resistor structure, which can effectively simplify the production process and significantly improve production efficiency.
  • step 101 is performed.
  • a substrate 10 is provided.
  • the substrate 10 includes a first region and a second region.
  • the substrate may be a semiconductor substrate; specifically, it includes at least one elemental semiconductor material (for example, silicon (Si) substrate, germanium (Ge) substrate, etc.), at least one III-V compound semiconductor material (for example, gallium nitride) (GaN) substrate, gallium arsenide (GaAs) substrate, indium phosphide (InP) substrate, etc.), at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art .
  • the substrate is a silicon substrate.
  • step 102 is performed.
  • a stacked material layer 12 is formed on the substrate 10 .
  • the stacked material layer 12 includes a first dielectric layer 12a, a first conductive layer 12b and a second layer from bottom to top. Conductive layer 12c.
  • the material of the first dielectric layer 12a includes but is not limited to oxide, nitride, metal oxide, oxynitride, etc.; optionally, in some embodiments, the material of the first dielectric layer 12a includes High-K dielectric material, the high-K dielectric material may contain hafnium element.
  • the high-K dielectric material may include but is not limited to aluminum oxide (Al 2 O 3 ), tantalum oxide (Ta 2 O 3 ), titanium oxide (TiO 2 ), yttrium oxide (Y 2 O 3 ), zirconium oxide (ZrO 2 ), zirconium silicon oxide ( ZrSix O y ), hafnium oxide (HfO 2 ), hafnium silicon oxide (HfSi x O y ), hafnium silicon oxynitride (HfSiON), hafnium Zirconate (HfZrO 4 ), lanthanum oxide (La 2 O 3 ), lanthanum aluminum oxide (LaAl x O y ), lanthanum hafnium oxide (LaHf x O y ), hafnium aluminum oxide (HfAl x O y ) and/or praseodymium oxide (Pr 2 O 3 ), etc.
  • Al 2 O 3 aluminum oxide
  • Ta 2 O 3 tanta
  • the thickness of the first conductive layer 12b ranges from 1 nm to 10 nm, such as 2 nm, 2.5 nm, 4 nm, 6 nm or 8 nm.
  • the material of the first conductive layer 12b includes transition metal nitride, such as titanium nitride. But it is not limited thereto.
  • the first conductive layer 12b may also include but is not limited to titanium (Ti), tantalum (Ta), titanium aluminide (TiAl), tantalum carbide (TaC), tantalum nitride (TaN), etc.;
  • the material of the second conductive layer 12c includes but is not limited to polysilicon.
  • the stacked material layer 12 also includes a third conductive layer 12e, and the third conductive layer 12e is located on the second conductive layer 12c; perform the first step on the stacked material layer 12.
  • the sub-etching process further includes: removing the third conductive layer 12e located at both ends of the first region and at the middle portion of the second region.
  • the material of the third conductive layer includes but is not limited to tungsten.
  • the stacked material layer 12 further includes a buffer conductive layer 12d located between the second conductive layer 12c and the third conductive layer 12e; for the stacked material layer Performing the first etching process further includes: removing the buffer conductive layer located at both ends of the first region and at a middle portion of the second region.
  • the buffer conductive layer 12d can serve as an anti-diffusion barrier layer to prevent the material of the third conductive layer 12e from diffusing to the area where the second conductive layer 12c is located.
  • the material of the buffer conductive layer 12d includes but is not limited to titanium silicon nitride (TiSiN) and the like.
  • the stacked material layer 12 also includes a capping layer 12f.
  • the material of the capping layer 12f includes but is not limited to silicon nitride.
  • the first dielectric layer 12a, the first conductive layer 12b, the second conductive layer 12c, the buffer conductive layer 12d, the third conductive layer 12e and the capping layer 12f The formation can be formed using one or more thin film deposition processes; specifically, the thin film deposition processes include but are not limited to chemical vapor deposition (CVD) process, plasma enhanced chemical vapor deposition (PECVD) process, atomic layer deposition (ALD) process or combination thereof.
  • CVD chemical vapor deposition
  • PECVD plasma enhanced chemical vapor deposition
  • ALD atomic layer deposition
  • the method before forming the stacked material layer 12 on the substrate 10 , the method further includes: forming on the second region of the substrate 10 Shallow trench isolation structure 101, the resistor structure 14 is located on the shallow trench isolation structure 101.
  • Materials forming the shallow trench isolation structure 101 include, but are not limited to, oxides, nitrides, oxynitrides, and the like.
  • step 103 is performed.
  • a first etching process is performed on the stacked material layer 12 to remove the two ends of the first region and the middle part of the second region.
  • the second conductive layer 12c is such that the first conductive layer 12b is exposed from both ends of the first region and from the middle part of the second region; wherein, the second conductive layer 12b remains in the middle part of the first region.
  • the conductive layer 12c constitutes the second gate layer 132, and the second conductive layer 12c remaining at both ends of the second region constitutes the resistive contact portion 142.
  • the etching process may be at least one of a dry etching process or a wet etching process or a combination thereof.
  • step 104 is performed.
  • a second etching process is performed on the stacked material layer 12 to retain the first conductive layer located under the second gate layer 132 and the resistive contact portion 142 12b and the first conductive layer 12b located in the middle part of the second region; wherein, the first conductive layer 12b remaining under the second gate layer 132 constitutes the first gate layer 131, and the first conductive layer 12b remaining in the middle part of the second region.
  • the first conductive layer 12b and the first conductive layer 12b remaining under the resistive contact portion 142 form the resistive layer 141, and the resistive layer 141 and the resistive contact portion 142 form the resistor structure 14.
  • the etching process may be at least one of a dry etching process or a wet etching process or a combination thereof.
  • the first gate layer and the second gate layer may serve as gate structures of the semiconductor device.
  • the gate structure can be used as a gate of an NMOS structure or a PMOS structure; in different MOS structures, the thickness of the first conductive layer included in the gate structure can be different. Therefore, it can be understood that in embodiments of the present disclosure, the resistor structure formed simultaneously with the gate structure can provide a variety of resistance values for practical selection.
  • the thickness of the resistance layer formed simultaneously with the gate structure in the NMOS structure is 6 nm; the thickness of the resistance layer formed simultaneously with the gate structure in the PMOS structure The thickness of the resistive layer is 2.5nm. Both thicknesses of material provide resistor structures that provide higher resistance values.
  • the preparation method provided by the embodiments of the present disclosure greatly simplifies the process of forming the gate structure and forming the resistor structure, which is beneficial to improving production efficiency.
  • the etching precision when forming the resistor structure can be the same as the etching precision when forming the gate structure, thereby effectively preventing Risk of defective products due to abnormal etching accuracy.
  • the active area can be doped to form a resistor, but the resistance of this type of resistor is greatly affected by process fluctuations, and the settings of critical dimensions, injection energy, and annealing temperature will all affect the resistance of the resistor. has an impact on the resistance value.
  • the resistor structure is prone to generate coupling capacitance with the doped well region of the substrate. Since there is a large PN junction capacitance between the resistor structure and the substrate, it is necessary to ensure that the PN junction is in a forward-biased state when voltage is applied to the resistor structure, which limits the application of the resistor structure.
  • the resistor structure has the advantages of relatively stable resistance, low temperature coefficient, and the resistance does not easily fluctuate with temperature changes.
  • the voltage applied to the resistor structure can be freely modulated.
  • the method before performing a second etching process on the stacked material layer 12 , the method further includes:
  • An etching process is performed on the mask layer 17 to retain the mask layer 17 located in the middle part of the second area, and remove the mask layer 17 on the first area and other areas of the second area except the middle part.
  • the material of the mask layer may include but is not limited to silicon nitride, etc.
  • the formation process of the mask layer may be the same as the formation process of the first dielectric layer, which will not be described again here.
  • the method further includes: removing the mask layer 17 located in the second region.
  • the method further includes: forming a first contact 181 and a second contact 182 above both ends of the resistor structure 14 .
  • the bottoms of the first contact 181 and the second contact 182 may be in contact with the upper surface of the third conductive layer 12e.
  • first contact 181 and second contact 182 includes:
  • An etching process is performed on the insulating material layer 19 to form a first contact hole (not labeled in the figure) and a second contact hole (not labeled in the figure).
  • the first contact hole (not labeled in the figure) and the second contact Holes (not labeled) are located above both ends of the resistor structure 14 and stop on the upper surface of the third conductive layer 12e;
  • the first contact 181 and the second contact 182 are respectively formed in the first contact hole (not labeled in the figure) and the second contact hole (not labeled in the figure).
  • the materials forming the insulating material layer 19 may include, but are not limited to, oxides, nitrides, oxynitrides, etc.
  • the material forming the first contact 181 and the second contact 182 may be a conductive material.
  • the conductive material may include but is not limited to tungsten.
  • the method before forming the first contact 181 and the second contact 182, the method further includes:
  • first insulating spacers 15 on both sides of the first gate layer 131 and the second gate layer 132, and on Second insulating spacers 16 are formed on both sides of the resistor structure.
  • the first insulating spacer 15 and the second insulating spacer 16 may form an electrical isolation effect between the first gate layer 131 , the second gate layer 132 and the resistor structure 14 .
  • the materials of the first insulating spacer 15 and the second insulating spacer 16 may include but are not limited to oxide, nitride, oxynitride, etc.
  • the process of forming the gate structure is compatible with the process of forming the resistor structure.
  • the process of forming the gate structure and the resistor structure is greatly simplified, which is beneficial to improving production efficiency.
  • the resistor structure has the advantages of high resistance, stable resistance, and low temperature coefficient, and its resistance will not easily fluctuate with changes in temperature.
  • the voltage applied to the resistor structure can be freely modulated.
  • An embodiment of the present disclosure also provides a semiconductor device, as shown in Figure 11, including:
  • Substrate 10 said substrate 10 including a first region and a second region;
  • a first dielectric layer 12a, the first dielectric layer 12a is located on the substrate 10;
  • a first gate layer 131 and a second gate layer 132 are located on the first dielectric layer 12a in the first region, and the second gate layer 132 is located on the first dielectric layer 12a in the first region. on a gate layer 131;
  • the resistor structure 14 is located on the first dielectric layer 12a in the second area.
  • the resistor structure 14 includes a resistance layer 141 and a resistance contact portion 142.
  • the resistance contact portion 142 is located on the resistance layer 141. Above and disposed at both ends of the resistive layer 141, and the lower part of the resistive contact portion 142 is in contact with the upper surfaces of both ends of the resistive layer 141;
  • the first gate layer 131 and the resistance layer 141 are made of the same material, and the second gate layer 132 and the resistance contact portion 142 are made of the same material.
  • the substrate 10 may be a silicon substrate.
  • a shallow trench isolation structure 101 is provided in the second region of the substrate 10 and the resistor structure 14 is located on the shallow trench isolation structure 101 .
  • Materials forming the shallow trench isolation structure 101 include, but are not limited to, oxides, nitrides, oxynitrides, and the like.
  • the material of the first dielectric layer 12a includes but is not limited to oxide, nitride, metal oxide, oxynitride, etc.; optionally, the material of the first dielectric layer 12a includes High-K dielectric material, the high-K dielectric material may contain hafnium element.
  • the high-K dielectric material may include but is not limited to aluminum oxide (Al 2 O 3 ), tantalum oxide (Ta 2 O 3 ), titanium oxide (TiO 2 ), yttrium oxide (Y 2 O 3 ), zirconium oxide (ZrO 2 ), zirconium silicon oxide ( ZrSix O y ), hafnium oxide (HfO 2 ), hafnium silicon oxide (HfSi x O y ), hafnium silicon oxynitride (HfSiON), hafnium Zirconate (HfZrO 4 ), lanthanum oxide (La 2 O 3 ), lanthanum aluminum oxide (LaAl x O y ), lanthanum hafnium oxide (LaHf x O y ), hafnium aluminum oxide (HfAl x O y ) and/or praseodymium oxide (Pr 2 O 3 ), etc.
  • Al 2 O 3 aluminum oxide
  • Ta 2 O 3 tanta
  • the first gate layer 131 and the resistive layer 141 are made of the same material, and the second gate layer 132 and the resistive contact portion 142 are made of the same material.
  • the materials of the first gate layer 131 and the resistance layer 141 include transition metal nitride, such as titanium nitride. But it is not limited thereto.
  • the first conductive layer 12b may also include but is not limited to titanium (Ti), tantalum (Ta), titanium aluminide (TiAl), tantalum carbide (TaC), tantalum nitride (TaN), etc.;
  • the materials of the second gate layer 132 and the resistive contact portion 142 include but are not limited to polysilicon.
  • the thickness of the first gate layer and the resistive layer ranges from 1 nm to 10 nm, such as 2 nm, 2.5 nm, 4 nm, 6 nm or 8 nm.
  • the first gate layer and the second gate layer may serve as gate structures of a semiconductor device.
  • the gate structure can be used as a gate of an NMOS structure or a PMOS structure; when the material of the resistance layer is the same as the material of the first gate layer in the gate structure included in the NMOS structure, and the material is nitrogen
  • the thickness of the first gate layer and the resistance layer may be 6 nm; when the material of the resistance layer is the same as the material of the first gate layer in the gate structure included in the PMOS structure, and When the material is titanium nitride, the thickness of the first gate layer and the resistance layer may be 2.5 nm. Both thicknesses of material provide resistor structures that provide higher resistance values.
  • the process of forming the gate structure and the process of forming the resistor structure can be compatible, thereby effectively simplifying the production process and improving production efficiency.
  • the semiconductor device further includes a third conductive layer 12 e located on the second gate layer 132 and the resistive contact 142 .
  • the material of the third conductive layer includes but is not limited to tungsten.
  • the semiconductor device further includes a buffer conductive layer 12d located between the third conductive layer 12e and the second gate layer 132, and located between the third conductive layer 12e and the second gate layer 132. between the three conductive layers 12e and the resistive contact portion 142.
  • the buffer conductive layer 12d can serve as an anti-diffusion barrier layer to prevent the material of the third conductive layer 12e from diffusing to the area where the second conductive layer 12c is located.
  • the material of the buffer conductive layer 12d includes but is not limited to titanium silicon nitride (TiSiN) and the like.
  • the semiconductor device further includes a cap layer 12f located above the third conductive layer 12e on the second gate layer 132, and a third conductive layer 12e on the resistive contact portion 142. above the conductive layer 12e.
  • the material forming the cap layer 12f includes but is not limited to silicon nitride and the like.
  • the semiconductor device further includes a first insulating spacer 15 and a second insulating spacer 16 ; wherein the first insulating spacer 15 is located between the first gate layer 131 and the second insulating spacer 16 .
  • the second insulating spacers 16 are located on both sides of the resistor structure 14 .
  • first insulating spacer 15 and the second insulating spacer 16 may be formed between the first gate layer 131 , the second gate layer 132 and the resistor structure 14 The effect of electrical isolation.
  • the materials of the first insulating spacer 15 and the second insulating spacer 16 may include but are not limited to oxide, nitride, oxynitride, etc.
  • the semiconductor device further includes a first contact 181 and a second contact 182 located above both ends of the resistor structure 14 .
  • the bottoms of the first contact 181 and the second contact 182 may be in contact with the upper surface of the third conductive layer 12e.
  • the material of the first contact 181 and the second contact 182 may be a conductive material.
  • the conductive material may include but is not limited to tungsten.
  • the semiconductor device further includes an insulating material layer 19 located on the substrate 10 , and a top surface of the insulating material layer 19 is in contact with the first contact 181 and the The top surface of the second contact 182 is flush.
  • the materials forming the insulating material layer 19 may include, but are not limited to, oxides, nitrides, oxynitrides, etc.
  • the gate structure and the resistor structure can be obtained simultaneously through only two etching processes, that is, the process of forming the gate structure and The process for forming the resistor structure is compatible. In this way, the process of forming the gate structure and the resistor structure is greatly simplified, which is beneficial to improving production efficiency.
  • the etching precision when forming the resistor structure is the same as the etching precision when forming the gate structure, thereby effectively preventing etching errors.
  • Abnormal corrosion accuracy may cause product defects.
  • the resistor structure has the advantages of high resistance, good resistance stability, and the resistance does not easily fluctuate with temperature changes. At the same time, since there is basically no coupling capacitance between the resistor structure and the doped well region of the substrate, the voltage applied to the resistor structure can be freely modulated.
  • the method for manufacturing a semiconductor device provided by the embodiments of the present disclosure can be applied to a DRAM structure or other semiconductor devices, and is not subject to excessive limitations here.
  • the embodiments of the semiconductor device preparation method provided by the present disclosure and the embodiments of the semiconductor device belong to the same concept; the technical features in the technical solutions recorded in each embodiment can be combined arbitrarily as long as there is no conflict.
  • the process of forming the gate structure is compatible with the process of forming the resistor structure, which can effectively simplify the production process and significantly improve production efficiency.

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Abstract

本公开实施例提供了一种半导体器件的制备方法及半导体器件，其中，所述方法包括：提供衬底，衬底包括第一区域和第二区域；在衬底上形成堆叠材料层，堆叠材料层包括第一介质层、第一导电层及第二导电层；对堆叠材料层执行第一次刻蚀工艺，去除位于第一区域两端部和位于第二区域中间部分的第二导电层形成第二栅极层和电阻接触部；对堆叠材料层执行第二次刻蚀工艺，保留位于第二栅极层、电阻接触部下方的第一导电层和位于第二区域中间部分的第一导电层；其中，保留在第二栅极层下方的第一导电层构成第一栅极层，保留在第二区域中间部分的第一导电层和保留在电阻接触部下方的第一导电层构成电阻层，电阻层与电阻接触部构成电阻器结构。

Description

一种半导体器件的制备方法及半导体器件
相关申请的交叉引用
本公开基于申请号为202210254166.0、申请日为2022年03月15日、发明名称为“一种半导体器件的制备方法及半导体器件”的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本公开作为参考。
技术领域
本公开涉及半导体制造领域，尤其涉及一种半导体器件的制备方法及半导体器件。
背景技术
半导体器件中，栅极结构和电阻器结构是非常重要的组成部分。在传统工艺过程中，需要采用多次不同的工艺过程来分别形成栅极结构和电阻器结构，工艺过程较复杂。因此，如何优化栅极结构与电阻器结构的制备工艺，成为亟需解决的问题。
发明内容
本公开实施例提供了一种半导体器件的制备方法，包括：
提供衬底，所述衬底包括第一区域和第二区域；
在所述衬底上形成堆叠材料层，所述堆叠材料层包括从下至上的第一介质层、第一导电层及第二导电层；
对所述堆叠材料层执行第一次刻蚀工艺，去除位于所述第一区域两端部和位于所述第二区域中间部分的所述第二导电层，使得所述第一导电层从所述第一区域的两端部以及从所述第二区域的中间部分暴露；其中，保留在所述第一区域中间部分的第二导电层构成第二栅极层，保留在所述第二区域两端部分的第二导电层构成电阻接触部；
对所述堆叠材料层执行第二次刻蚀工艺，保留位于所述第二栅极层、 所述电阻接触部下方的第一导电层和位于所述第二区域中间部分的第一导电层；其中，保留在第二栅极层下方的第一导电层构成第一栅极层，保留在第二区域中间部分的第一导电层和保留在所述电阻接触部下方的第一导电层构成电阻层，所述电阻层与所述电阻接触部构成电阻器结构。
上述方案中，对所述堆叠材料层执行第二次刻蚀工艺之前，所述方法还包括：
在所述第一导电层上形成掩膜层；
对所述掩膜层执行刻蚀工艺，保留位于第二区域中间部分的掩膜层，去除第一区域上的掩膜层以及第二区域上除中间部分以外的其他区域上的掩膜层。
上述方案中，对所述堆叠材料层执行第二次刻蚀工艺后，所述方法还包括：去除位于所述第二区域的所述掩膜层。
上述方案中，在形成所述电阻器结构之后，所述方法还包括：在所述电阻器结构的两端上方形成第一接触和第二接触。
上述方案中，在形成所述第一接触和所述第二接触之前，所述方法还包括：
在所述衬底上形成第二介质层；
对所述第二介质层执行刻蚀工艺，以在所述第一栅极层和所述第二栅极层的两侧形成第一绝缘间隔物，及在所述电阻器结构的两侧形成第二绝缘间隔物。
上述方案中，在所述衬底上形成堆叠材料层之前，所述方法还包括：在所述衬底的所述第二区域上形成浅槽隔离结构，所述电阻器结构位于所述浅槽隔离结构上。
上述方案中，所述第一导电层的材料包括过渡金属氮化物；所述第二导电层的材料包括多晶硅。
上述方案中，所述第一导电层的厚度范围在1nm至10nm之间。
上述方案中，所述堆叠材料层还包括第三导电层，所述第三导电层位于所述第二导电层上；对所述堆叠材料层执行第一次刻蚀工艺还包括：去除位于所述第一区域两端部和位于所述第二区域中间部分的所述第三导电层。
上述方案中，所述堆叠材料层还包括缓冲导电层，所述缓冲导电层位于所述第二导电层和所述第三导电层之间；对所述堆叠材料层执行第一次刻蚀工艺还包括：去除位于所述第一区域两端部和位于所述第二区域中间部分的所述缓冲导电层。
本公开实施例还提供了一种半导体器件，包括：
衬底，所述衬底包括第一区域和第二区域；
第一介质层，所述第一介质层位于所述衬底上；
第一栅极层和第二栅极层，所述第一栅极层位于所述第一区域的所述第一介质层上，所述第二栅极层位于所述第一栅极层上；
电阻器结构，位于所述第二区域的所述第一介质层上，所述电阻器结构包括电阻层和电阻接触部，所述电阻接触部位于所述电阻层的上方并设置于所述电阻层的两端，且所述电阻接触部的下方与所述电阻层的两端部的上表面接触；
其中，所述第一栅极层与所述电阻层的材料相同，所述第二栅极层与所述电阻接触部的材料相同。
上述方案中，所述第一介质层的材料包括高K介质材料。
上述方案中，所述第一栅极层和所述电阻层的材料包括过渡金属氮化物；所述第二栅极层与所述电阻接触部的材料包括多晶硅。
上述方案中，所述半导体器件还包括位于所述电阻器结构两端上方的第一接触和第二接触。
上述方案中，所述第一栅极层与所述电阻层的厚度范围在1nm至10nm之间。
上述方案中，所述半导体器件还包括第三导电层，所述第三导电层位于所述第二栅极层和所述电阻接触部上。
上述方案中，所述半导体器件还包括第一绝缘间隔物和第二绝缘间隔物；其中，所述第一绝缘间隔物位于所述第一栅极层和所述第二栅极层的两侧，所述第二绝缘间隔物位于所述电阻器结构的两侧。
上述方案中，所述半导体器件还包括缓冲导电层，所述缓冲导电层位于所述第三导电层和所述第二栅极层之间，及位于所述第三导电层和所述电阻接触部之间。
本公开实施例提供的半导体器件的制备方法及半导体器件，其中，所述方法包括：提供衬底，所述衬底包括第一区域和第二区域；在所述衬底上形成堆叠材料层，所述堆叠材料层包括从下至上的第一介质层、第一导电层及第二导电层；对所述堆叠材料层执行第一次刻蚀工艺，去除位于所述第一区域两端部和位于所述第二区域中间部分的所述第二导电层，使得所述第一导电层从所述第一区域的两端部以及从所述第二区域的中间部分暴露；其中，保留在所述第一区域中间部分的第二导电层构成第二栅极层，保留在所述第二区域两端部分的第二导电层构成电阻接触部；对所述堆叠材料层执行第二次刻蚀工艺，保留位于所述第二栅极层、所述电阻接触部下方的第一导电层和位于所述第二区域中间部分的第一导电层；其中，保留在第二栅极层下方的第一导电层构成第一栅极层，保留在第二区域中间部分的第一导电层和保留在所述电阻接触部下方的第一导电层构成电阻层，所述电阻层与所述电阻接触部构成电阻器结构。形成堆叠材料层后，对堆叠材料层执行刻蚀工艺：通过第一次刻蚀工艺形成了第二栅极层和电阻接触部，通过第二次刻蚀工艺形成了第一栅极层和电阻层；其中，第一栅极层和第二栅极层可作为半导体器件的栅极，电阻接触部和电阻层共同构成电阻器结构。如此，通过两次刻蚀工艺便可同时形成栅极结构和电阻器结构，使得形成栅极结构的工艺过程和形成电阻器结构的工艺过程相兼容，简化了形成栅极结构和电阻器结构的工艺流程。因此，本公开实施例中，形成栅极结构的工艺过程和形成电阻器结构的工艺过程相兼容，可有效简化生产工艺流程，显著提高生产效率。
本公开的一个或多个实施例的细节在下面的附图和描述中提出。本公开的其它特征和优点将从说明书、附图以及权利要求书变得明显。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本公开实施例提供的半导体器件的制备方法的流程框图；
图2至图11为本公开实施例提供的半导体器件在制备过程中的工艺流程图。
具体实施方式
下面将参照附图更详细地描述本公开公开的示例性实施方式。虽然附图中显示了本公开的示例性实施方式，然而应当理解，可以以各种形式实现本公开，而不应被这里阐述的具体实施方式所限制。相反，提供这些实施方式是为了能够更透彻地理解本公开，并且能够将本公开公开的范围完整的传达给本领域的技术人员。
在下文的描述中，给出了大量具体的细节以便提供对本公开更为彻底的理解。然而，对于本领域技术人员而言显而易见的是，本公开可以无需一个或多个这些细节而得以实施。在其他的例子中，为了避免与本公开发生混淆，对于本领域公知的一些技术特征未进行描述；即，这里不描述实际实施例的全部特征，不详细描述公知的功能和结构。
在附图中，为了清楚，层、区、元件的尺寸以及其相对尺寸可能被夸大。自始至终相同附图标记表示相同的元件。
应当明白，当元件或层被称为“在……上”、“与……相邻”、“连接到”或“耦合到”其它元件或层时，其可以直接地在其它元件或层上、与之相邻、连接或耦合到其它元件或层，或者可以存在居间的元件或层。相反，当元件被称为“直接在……上”、“与……直接相邻”、“直接连接到”或“直接耦合到”其它元件或层时，则不存在居间的元件或层。应当明白，尽管可使用术语第一、第二、第三等描述各种元件、部件、区、层和/或部分，这些元件、部件、区、层和/或部分不应当被这些术语限制。这些术语仅仅用来区分一个元件、部件、区、层或部分与另一个元件、部件、区、层或部分。因此，在不脱离本公开教导之下，下面讨论的第一元件、部件、区、层或部分可表示为第二元件、部件、区、层或部分。而当讨论的第二元件、部件、区、层或部分时，并不表明本公开必然存在第一元件、部件、区、层或部分。
空间关系术语例如“在……下”、“在……下面”、“下面的”、“在……之下”、“在……之上”、“上面的”等，在这里可为了方便描述而被使用从 而描述图中所示的一个元件或特征与其它元件或特征的关系。应当明白，除了图中所示的取向以外，空间关系术语意图还包括使用和操作中的器件的不同取向。例如，如果附图中的器件翻转，然后，描述为“在其它元件下面”或“在其之下”或“在其下”元件或特征将取向为在其它元件或特征“上”。因此，示例性术语“在……下面”和“在……下”可包括上和下两个取向。器件可以另外地取向(旋转90度或其它取向)并且在此使用的空间描述语相应地被解释。
在此使用的术语的目的仅在于描述具体实施例并且不作为本公开的限制。在此使用时，单数形式的“一”、“一个”和“所述/该”也意图包括复数形式，除非上下文清楚指出另外的方式。还应明白术语“组成”和/或“包括”，当在该说明书中使用时，确定所述特征、整数、步骤、操作、元件和/或部件的存在，但不排除一个或更多其它的特征、整数、步骤、操作、元件、部件和/或组的存在或添加。在此使用时，术语“和/或”包括相关所列项目的任何及所有组合。
半导体器件中，栅极结构和电阻器结构是非常重要的结构。在大多数栅极结构中，其组成部分包括多晶硅层，但该多晶硅层具有较低的电阻率，不适合作为电阻器的主体部分。通常，为了获得具有较高电阻值的电阻器结构，电阻器主体部分可通过重新形成多晶硅层并对其执行掺杂工艺来获得。
因此，在传统工艺过程中，栅极结构和电阻器结构通常在不同的工艺过程中形成，使得工艺复杂性增加，不利于生产效率的提高。
基于此，提出了本公开实施例的以下技术方案：
本公开实施例提供了一种半导体器件的制备方法，具体请参见图1。如图所示，所述方法包括了如下步骤：
步骤101：提供衬底，所述衬底包括第一区域和第二区域；
步骤102：在所述衬底上形成堆叠材料层，所述堆叠材料层包括从下至上的第一介质层、第一导电层及第二导电层；
步骤103：对所述堆叠材料层执行第一次刻蚀工艺，去除位于所述第一区域两端部和位于所述第二区域中间部分的所述第二导电层，使得所述第一导电层从所述第一区域的两端部以及从所述第二区域的中间部分暴露； 其中，保留在所述第一区域中间部分的第二导电层构成第二栅极层，保留在所述第二区域两端部分的第二导电层构成电阻接触部；
步骤104：对所述堆叠材料层执行第二次刻蚀工艺，保留位于所述第二栅极层、所述电阻接触部下方的第一导电层和位于所述第二区域中间部分的第一导电层；其中，保留在第二栅极层下方的第一导电层构成第一栅极层，保留在第二区域中间部分的第一导电层和保留在所述电阻接触部下方的第一导电层构成电阻层，所述电阻层与所述电阻接触部构成电阻器结构。
本公开实施例中，形成堆叠材料层后，对堆叠材料层执行刻蚀工艺：通过第一次刻蚀工艺形成了第二栅极层和电阻接触部，通过第二次刻蚀工艺形成了第一栅极层和电阻层；其中，第一栅极层和第二栅极层可作为半导体器件的栅极，电阻接触部和电阻层共同构成电阻器结构。如此，通过两次刻蚀工艺便可同时形成栅极结构和电阻器结构，使得形成栅极结构的工艺过程和形成电阻器结构的工艺过程相兼容，简化了形成栅极结构和电阻器结构的工艺流程。因此，本公开实施例中，形成栅极结构的工艺过程和形成电阻器结构的工艺过程相兼容，可有效简化生产工艺流程，显著提高生产效率。
为使本公开的上述目的、特征和优点能够更加明显易懂，下面结合附图对本公开的具体实施方式做详细的说明。在详述本公开实施例时，为便于说明，示意图会不依一般比例作局部放大，而且所述示意图只是示例，其在此不应限制本公开的保护范围。
图2至图11为本公开实施例提供的半导体器件在制备过程中的工艺流程图。
首先，执行步骤101，如图2所示，提供衬底10，所述衬底10包括第一区域和第二区域。
所述衬底可以为半导体衬底；具体包括至少一个单质半导体材料(例如为硅(Si)衬底、锗(Ge)衬底等)、至少一个III-V化合物半导体材料(例如为氮化镓(GaN)衬底、砷化镓(GaAs)衬底、磷化铟(InP)衬底等)、至少一个II-VI化合物半导体材料、至少一个有机半导体材料或者在本领域已知的其他半导体材料。在一具体实施例中，所述衬底为硅衬底。
接着，执行步骤102，如图4所示，在所述衬底10上形成堆叠材料层 12，所述堆叠材料层12包括从下至上的第一介质层12a、第一导电层12b及第二导电层12c。
这里，所述第一介质层12a的材料包括但不限于氧化物、氮化物、金属氧化物及氮氧化物等；可选的，在一些实施例中，所述第一介质层12a的材料包括高K介质材料，所述高K介质材料可以包含铪元素。具体的，所述高K介质材料可以包括但不限于铝氧化物(Al 2O 3)、钽氧化物(Ta 2O 3)、钛氧化物(TiO 2)、钇氧化物(Y 2O 3)、锆氧化物(ZrO 2)、锆硅氧化物(ZrSi xO y)、铪氧化物(HfO 2)、铪硅氧化物(HfSi xO y)、铪硅氮氧化物(HfSiON)、铪锆酸盐(HfZrO 4)、镧氧化物(La 2O 3)、镧铝氧化物(LaAl xO y)、镧铪氧化物(LaHf xO y)、铪铝氧化物(HfAl xO y)和/或镨氧化物(Pr 2O 3)等。
在一些实施例中，所述第一导电层12b的厚度范围在1nm至10nm之间，比如2nm、2.5nm、4nm、6nm或者8nm等。
在一些具体的实施例中，所述第一导电层12b的材料包括过渡金属氮化物，比如氮化钛等。但不限于此，所述第一导电层12b还可以包括但不限于钛(Ti)、钽(Ta)、铝化钛(TiAl)、碳化钽(TaC)和氮化钽(TaN)等；所述第二导电层12c的材料包括但不限于多晶硅等。
继续参考图4，可以看出，所述堆叠材料层12还包括第三导电层12e，所述第三导电层12e位于所述第二导电层12c上；对所述堆叠材料层12执行第一次刻蚀工艺还包括：去除位于所述第一区域两端部和位于所述第二区域中间部分的所述第三导电层12e。这里，所述第三导电层的材料包括但不限于钨等。
在一些实施例中，所述堆叠材料层12还包括缓冲导电层12d，所述缓冲导电层12d位于所述第二导电层12c和所述第三导电层12e之间；对所述堆叠材料层执行第一次刻蚀工艺还包括：去除位于所述第一区域两端部和位于所述第二区域中间部分的所述缓冲导电层。
这里，所述缓冲导电层12d可作为防扩散阻挡层，防止所述第三导电层12e的材料向所述第二导电层12c所在的区域进行扩散。在一些实施例中，所述缓冲导电层12d的材料包括但不限于钛硅氮(TiSiN)等。
可选的，所述堆叠材料层12还包括盖帽层12f，所述盖帽层12f的材料包括但不限于氮化硅等。
在实际工艺中，所述第一介质层12a、所述第一导电层12b、所述第二导电层12c、所述缓冲导电层12d、所述第三导电层12e及所述盖帽层12f的形成可以采用一种或多种薄膜沉积工艺形成；具体地，所述薄膜沉积工艺包括但不限于化学气相沉积(CVD)工艺、等离子体增强化学气相沉积(PECVD)工艺、原子层沉积(ALD)工艺或其组合。
可以理解的，如图3所示，在一些实施例中，在所述衬底10上形成堆叠材料层12之前，所述方法还包括：在所述衬底10的所述第二区域上形成浅槽隔离结构101，所述电阻器结构14位于所述浅槽隔离结构101上。
形成所述浅槽隔离结构101的材料包括但不限于氧化物、氮化物、氮氧化物等。
接下来，执行步骤103，如图5所示，对所述堆叠材料层12执行第一次刻蚀工艺，去除位于所述第一区域两端部和位于所述第二区域中间部分的所述第二导电层12c，使得所述第一导电层12b从所述第一区域的两端部以及从所述第二区域的中间部分暴露；其中，保留在所述第一区域中间部分的第二导电层12c构成第二栅极层132，保留在所述第二区域两端部分的第二导电层12c构成电阻接触部142。
在实际工艺中，所述刻蚀工艺可以为干法刻蚀工艺或者湿法刻蚀工艺中的至少一种或其组合。
最后，执行步骤104，如图8所示，对所述堆叠材料层12执行第二次刻蚀工艺，保留位于所述第二栅极层132、所述电阻接触部142下方的第一导电层12b和位于所述第二区域中间部分的第一导电层12b；其中，保留在第二栅极层132下方的第一导电层12b构成第一栅极层131，保留在第二区域中间部分的第一导电层12b和保留在所述电阻接触部142下方的第一导电层12b构成电阻层141，所述电阻层141与所述电阻接触部142构成电阻器结构14。
这里，所述刻蚀工艺可以为干法刻蚀工艺或者湿法刻蚀工艺中的至少一种或其组合。
在实际工艺中，所述第一栅极层和所述第二栅极层可以作为半导体器件的栅极结构。所述栅极结构可作为NMOS结构或者PMOS结构的栅极使用；其中，在不同的MOS结构中，所述栅极结构包含的所述第一导电层的 厚度可以不同。因此，可以理解的，在本公开实施例中，与栅极结构同时形成的电阻器结构可以提供多种阻值供实际选择。
在一些具体的实施例中，当所述电阻层的材料为氮化钛时，与NMOS结构中的栅极结构同时形成的电阻层的厚度为6nm；与PMOS结构中的栅极结构同时形成的电阻层的厚度为2.5nm。两种厚度的材料所形成的电阻器结构均可以提供较高的电阻值。
在本公开实施例中，无需重新形成作为电阻层的材料层，仅通过两次刻蚀工艺即可同时获得栅极结构和电阻器结构，即形成栅极结构的工艺过程和形成电阻器结构的工艺过程相兼容。因此，本公开实施例提供的制备方法，极大的简化了形成栅极结构和形成电阻器结构的工艺过程，有利于生产效率的提高。
同时，由于形成栅极结构的工艺过程和形成电阻器结构的工艺过程相兼容，使得形成所述电阻器结构时的刻蚀精度与形成栅极结构时的刻蚀精度可以相同，从而可有效防止因刻蚀精度异常引发产品不良的风险。
传统技术中，可对有源区进行掺杂来形成电阻器，但该类型电阻器的阻值受工艺波动的影响较大，且关键尺寸、注入能量及退火温度等的设置均会对电阻器的阻值产生影响。此外，该电阻器结构还容易与衬底的掺杂阱区之间产生耦合电容。由于在电阻器结构和衬底之间存在较大的PN结电容，在对电阻器结构施加电压时需要保证PN结处于正偏状态，限制了电阻器结构的应用。
与之相比，本公开实施例中，电阻器结构具有阻值较稳定、温度系数较低，阻值不轻易随温度变化引起波动等优点。同时，由于电阻器结构与衬底的掺杂阱区之间基本没有耦合电容产生，使得施加在电阻器结构上的电压可以进行自由调制。
在一些实施例中，如图6和图7所示，对所述堆叠材料层12执行第二次刻蚀工艺之前，所述方法还包括：
在所述第一导电层12b上形成掩膜层17；
对所述掩膜层17执行刻蚀工艺，保留位于第二区域中间部分的掩膜层17，去除第一区域上的掩膜层17以及第二区域上除中间部分以外的其他区域上的掩膜层17。
所述掩膜层的材料可以包括但不限于氮化硅等，所述掩膜层的形成工艺可以与所述第一介质层的形成工艺相同，在此不做赘述。
如图9所示，对所述堆叠材料层12执行第二次刻蚀工艺后，所述方法还包括：去除位于所述第二区域的所述掩膜层17。
在实际工艺中，如图11所示，在形成所述电阻器结构14之后，所述方法还包括：在所述电阻器结构14的两端上方形成第一接触181和第二接触182。所述第一接触181和所述第二接触182的底部可以与所述第三导电层12e的上表面接触。
在一些实施例中，形成第一接触181和第二接触182，包括：
在所述衬底10上方形成绝缘材料层19；
对所述绝缘材料层19执行刻蚀工艺，形成第一接触孔(图未标识)和第二接触孔(图未标识)，所述第一接触孔(图未标识)和所述第二接触孔(图未标识)位于所述电阻器结构14的两端上方，且停止于所述第三导电层12e的上表面；
在所述第一接触孔(图未标识)和所述第二接触孔(图未标识)中分别形成所述第一接触181和所述第二接触182。
在实际工艺中，形成所述绝缘材料层19的材料可以包括但不限于氧化物、氮化物、氮氧化物等。
形成所述第一接触181和所述第二接触182的材料可以为导电材料。具体的，所述导电材料可以包括但不限于钨等。
可选的，如图10所示，在形成所述第一接触181和所述第二接触182之前，所述方法还包括：
在所述衬底10上形成第二介质层(图未示出)；
对所述第二介质层(图未示出)执行刻蚀工艺，以在所述第一栅极层131和所述第二栅极层132的两侧形成第一绝缘间隔物15，及在所述电阻器结构的两侧形成第二绝缘间隔物16。
所述第一绝缘间隔物15和所述第二绝缘间隔物16可以在所述第一栅极层131、所述第二栅极层132与所述电阻器结构14之间形成电隔离的效果。
这里，所述第一绝缘间隔物15和所述第二绝缘间隔物16的材料可以 包括但不限于氧化物、氮化物、氮氧化物等。
在本公开实施例中，形成栅极结构的工艺过程和形成电阻器结构的工艺过程相兼容。极大的简化了形成栅极结构和形成电阻器结构的工艺过程，有利于生产效率的提高。
同时，本公开实施例中，电阻器结构具有阻值较高、阻值稳定且温度系数较低的优点，其电阻值不会轻易随温度的变化产生波动。同时，由于电阻器结构与衬底的掺杂阱区之间基本没有耦合电容产生，使得施加在电阻器结构上的电压可以进行自由调制。
本公开实施例还提供了一种半导体器件，如图11所示，包括：
衬底10，所述衬底10包括第一区域和第二区域；
第一介质层12a，所述第一介质层12a位于所述衬底10上；
第一栅极层131和第二栅极层132，所述第一栅极层131位于所述第一区域的所述第一介质层12a上，所述第二栅极层132位于所述第一栅极层131上；
电阻器结构14，位于所述第二区域的所述第一介质层12a上，所述电阻器结构14包括电阻层141和电阻接触部142，所述电阻接触部142位于所述电阻层141的上方并设置于所述电阻层141的两端，且所述电阻接触部142的下方与所述电阻层141的两端部的上表面接触；
其中，所述第一栅极层131与所述电阻层141的材料相同，所述第二栅极层132与所述电阻接触部142的材料相同。
这里，所述衬底10可以为硅衬底。
在一些实施例中，在所述衬底10的所述第二区域中设置有浅槽隔离结构101，所述电阻器结构14位于所述浅槽隔离结构101上。形成所述浅槽隔离结构101的材料包括但不限于氧化物、氮化物、氮氧化物等。
在一些具体的实施例中，所述第一介质层12a的材料包括但不限于氧化物、氮化物、金属氧化物及氮氧化物等；可选的，所述第一介质层12a的材料包括高K介质材料，所述高K介质材料可以包含铪元素。具体的，所述高K介质材料可以包括但不限于铝氧化物(Al 2O 3)、钽氧化物(Ta 2O 3)、钛氧化物(TiO 2)、钇氧化物(Y 2O 3)、锆氧化物(ZrO 2)、锆硅氧化物(ZrSi xO y)、铪氧化物(HfO 2)、铪硅氧化物(HfSi xO y)、铪硅氮氧化物(HfSiON)、铪锆酸盐 (HfZrO 4)、镧氧化物(La 2O 3)、镧铝氧化物(LaAl xO y)、镧铪氧化物(LaHf xO y)、铪铝氧化物(HfAl xO y)和/或镨氧化物(Pr 2O 3)等。
在一些实施例中，所述第一栅极层131与所述电阻层141的材料相同，所述第二栅极层132与所述电阻接触部142的材料相同。具体的，所述第一栅极层131和所述电阻层141的材料包括过渡金属氮化物，比如氮化钛等。但不限于此，所述第一导电层12b还可以包括但不限于钛(Ti)、钽(Ta)、铝化钛(TiAl)、碳化钽(TaC)和氮化钽(TaN)等；所述第二栅极层132与所述电阻接触部142的材料包括但不限于多晶硅等。
在一些具体的实施例中，所述第一栅极层与所述电阻层的厚度范围在1nm至10nm之间，比如2nm、2.5nm、4nm、6nm或者8nm等。
可以理解的，所述第一栅极层和所述第二栅极层可作为半导体器件的栅极结构。所述栅极结构可作为NMOS结构或者PMOS结构的栅极使用；当所述电阻层的材料与NMOS结构所包含的栅极结构中的第一栅极层的材料相同，且所述材料为氮化钛时，所述第一栅极层与所述电阻层的厚度可以为6nm；当所述电阻层的材料与PMOS结构所包含的栅极结构中的第一栅极层的材料相同，且所述材料为氮化钛时，所述第一栅极层与所述电阻层的厚度可以为2.5nm。两种厚度的材料所形成的电阻器结构均可以提供较高的电阻值。
在一些实施例中，形成所述栅极结构的工艺过程和形成所述电阻器结构的工艺过程可以兼容，从而有效简化生产工艺流程，提高生产效率。
在一些实施例中，所述半导体器件还包括第三导电层12e，所述第三导电层12e位于所述第二栅极层132和所述电阻接触部142上。这里，所述第三导电层的材料包括但不限于钨等。
在一些具体的实施例中，所述半导体器件还包括缓冲导电层12d，所述缓冲导电层12d位于所述第三导电层12e和所述第二栅极层132之间，及位于所述第三导电层12e和所述电阻接触部142之间。
可以理解的，所述缓冲导电层12d可作为防扩散阻挡层，防止所述第三导电层12e的材料向所述第二导电层12c所在的区域进行扩散。这里，所述缓冲导电层12d的材料包括但不限于钛硅氮(TiSiN)等。
可选的，所述半导体器件还包括盖帽层12f，所述盖帽层12f位于所述 第二栅极层132上的第三导电层12e的上方，及位于所述电阻接触部142上的第三导电层12e的上方。形成所述盖帽层12f的材料包括但不限于氮化硅等。
继续参考图11，可以看出，所述半导体器件还包括第一绝缘间隔物15和第二绝缘间隔物16；其中，所述第一绝缘间隔物15位于所述第一栅极层131和所述第二栅极层132的两侧，所述第二绝缘间隔物16位于所述电阻器结构14的两侧。
可以理解的，所述第一绝缘间隔物15和所述第二绝缘间隔物16可以在所述第一栅极层131、所述第二栅极层132与所述电阻器结构14之间形成电隔离的效果。
这里，所述第一绝缘间隔物15和所述第二绝缘间隔物16的材料可以包括但不限于氧化物、氮化物、氮氧化物等。
在实际工艺中，所述半导体器件还包括位于所述电阻器结构14两端上方的第一接触181和第二接触182。所述第一接触181和所述第二接触182的底部可以与所述第三导电层12e的上表面接触。所述第一接触181和所述第二接触182的材料可以为导电材料。具体的，所述导电材料可以包括但不限于钨等。
在一些实施例中，所述半导体器件还包括绝缘材料层19，所述绝缘材料层19位于所述衬底10上，且所述绝缘材料层19的顶表面与所述第一接触181和所述第二接触182的顶表面平齐。在实际工艺中，形成所述绝缘材料层19的材料可以包括但不限于氧化物、氮化物、氮氧化物等。
综上所述，在本公开实施例中，无需重新形成作为电阻层的材料层，仅通过两次刻蚀工艺即可同时获得栅极结构和电阻器结构，即形成栅极结构的工艺过程和形成电阻器结构的工艺过程相兼容。如此，极大程度上简化了形成栅极结构和形成电阻器结构的工艺过程，有利于生产效率的提高。
同时，由于形成栅极结构的工艺过程和形成电阻器结构的工艺过程相兼容，使得形成所述电阻器结构时的刻蚀精度与形成栅极结构时的刻蚀精度相同，从而有效防止因刻蚀精度异常引发产品不良的风险。
另外，本公开实施例中，电阻器结构具有阻值高、阻值稳定性好、阻值不轻易随温度变化产生波动等优点。同时，由于电阻器结构与衬底的掺 杂阱区之间基本没有耦合电容产生，使得施加在电阻器结构上的电压可以进行自由调制。
需要说明的是，本公开实施例提供的半导体器件的制备方法可应用于DRAM结构或其他半导体器件中，在此不做过多限定。本公开提供的半导体器件制备方法的实施例与半导体器件的实施例属于同一构思；各实施例所记载的技术方案中各技术特征之间，在不冲突的情况下，可以任意组合。
以上所述，仅为本公开的较佳实施例而已，并非用于限定本公开的保护范围，凡在本公开的精神和原则之内所作的任何修改、等同替换和改进等，均应包含在本公开的保护范围之内。
工业实用性
本公开实施例中，形成栅极结构的工艺过程和形成电阻器结构的工艺过程相兼容，可有效简化生产工艺流程，显著提高生产效率。

Claims (18)

  1. 一种半导体器件的制备方法，所述方法包括：
    提供衬底，所述衬底包括第一区域和第二区域；
    在所述衬底上形成堆叠材料层，所述堆叠材料层包括从下至上的第一介质层、第一导电层及第二导电层；
    对所述堆叠材料层执行第一次刻蚀工艺，去除位于所述第一区域两端部和位于所述第二区域中间部分的所述第二导电层，使得所述第一导电层从所述第一区域的两端部以及从所述第二区域的中间部分暴露；其中，保留在所述第一区域中间部分的第二导电层构成第二栅极层，保留在所述第二区域两端部分的第二导电层构成电阻接触部；
    对所述堆叠材料层执行第二次刻蚀工艺，保留位于所述第二栅极层、所述电阻接触部下方的第一导电层和位于所述第二区域中间部分的第一导电层；其中，保留在第二栅极层下方的第一导电层构成第一栅极层，保留在第二区域中间部分的第一导电层和保留在所述电阻接触部下方的第一导电层构成电阻层，所述电阻层与所述电阻接触部构成电阻器结构。
  2. 根据权利要求1所述的方法，其中，对所述堆叠材料层执行第二次刻蚀工艺之前，所述方法还包括：
    在所述第一导电层上形成掩膜层；
    对所述掩膜层执行刻蚀工艺，保留位于第二区域中间部分的掩膜层，去除第一区域上的掩膜层以及第二区域上除中间部分以外的其他区域上的掩膜层。
  3. 根据权利要求2所述的方法，其中，对所述堆叠材料层执行第二次刻蚀工艺后，所述方法还包括：去除位于所述第二区域的所述掩膜层。
  4. 根据权利要求1所述的方法，其中，在形成所述电阻器结构之后，所述方法还包括：在所述电阻器结构的两端上方形成第一接触和第二接触。
  5. 根据权利要求4所述的方法，其中，在形成所述第一接触和所述第二接触之前，所述方法还包括：
    在所述衬底上形成第二介质层；
    对所述第二介质层执行刻蚀工艺，以在所述第一栅极层和所述第二栅 极层的两侧形成第一绝缘间隔物，及在所述电阻器结构的两侧形成第二绝缘间隔物。
  6. 根据权利要求1所述的方法，其中，在所述衬底上形成堆叠材料层之前，所述方法还包括：在所述衬底的所述第二区域上形成浅槽隔离结构，所述电阻器结构位于所述浅槽隔离结构上。
  7. 根据权利要求1所述的方法，其中，所述第一导电层的材料包括过渡金属氮化物；所述第二导电层的材料包括多晶硅。
  8. 根据权利要求1或7所述的方法，其中，所述第一导电层的厚度范围在1nm至10nm之间。
  9. 根据权利要求1所述的方法，其中，所述堆叠材料层还包括第三导电层，所述第三导电层位于所述第二导电层上；对所述堆叠材料层执行第一次刻蚀工艺还包括：去除位于所述第一区域两端部和位于所述第二区域中间部分的所述第三导电层。
  10. 根据权利要求9所述的方法，其中，所述堆叠材料层还包括缓冲导电层，所述缓冲导电层位于所述第二导电层和所述第三导电层之间；对所述堆叠材料层执行第一次刻蚀工艺还包括：去除位于所述第一区域两端部和位于所述第二区域中间部分的所述缓冲导电层。
  11. 一种半导体器件，包括：
    衬底，所述衬底包括第一区域和第二区域；
    第一介质层，所述第一介质层位于所述衬底上；
    第一栅极层和第二栅极层，所述第一栅极层位于所述第一区域的所述第一介质层上，所述第二栅极层位于所述第一栅极层上；
    电阻器结构，位于所述第二区域的所述第一介质层上，所述电阻器结构包括电阻层和电阻接触部，所述电阻接触部位于所述电阻层的上方并设置于所述电阻层的两端，且所述电阻接触部的下方与所述电阻层的两端部的上表面接触；
    其中，所述第一栅极层与所述电阻层的材料相同，所述第二栅极层与所述电阻接触部的材料相同。
  12. 根据权利要求11所述的器件，其中，所述第一介质层的材料包括高K介质材料。
  13. 根据权利要求11所述的器件，其中，所述第一栅极层和所述电阻层的材料包括过渡金属氮化物；所述第二栅极层与所述电阻接触部的材料包括多晶硅。
  14. 根据权利要求11所述的器件，其中，所述半导体器件还包括位于所述电阻器结构两端上方的第一接触和第二接触。
  15. 根据权利要求11所述的器件，其中，所述第一栅极层与所述电阻层的厚度范围在1nm至10nm之间。
  16. 根据权利要求11所述的器件，其中，所述半导体器件还包括第三导电层，所述第三导电层位于所述第二栅极层和所述电阻接触部上。
  17. 根据权利要求14所述的器件，其中，所述半导体器件还包括第一绝缘间隔物和第二绝缘间隔物；其中，所述第一绝缘间隔物位于所述第一栅极层和所述第二栅极层的两侧，所述第二绝缘间隔物位于所述电阻器结构的两侧。
  18. 根据权利要求16所述的器件，其中，所述半导体器件还包括缓冲导电层，所述缓冲导电层位于所述第三导电层和所述第二栅极层之间，及位于所述第三导电层和所述电阻接触部之间。
PCT/CN2022/084584 2022-03-15 2022-03-31 一种半导体器件的制备方法及半导体器件 WO2023173505A1 (zh)

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