WO2023173453A1 - 像素电路、像素驱动方法及显示装置 - Google Patents

像素电路、像素驱动方法及显示装置 Download PDF

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Publication number
WO2023173453A1
WO2023173453A1 PCT/CN2022/082246 CN2022082246W WO2023173453A1 WO 2023173453 A1 WO2023173453 A1 WO 2023173453A1 CN 2022082246 W CN2022082246 W CN 2022082246W WO 2023173453 A1 WO2023173453 A1 WO 2023173453A1
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WO
WIPO (PCT)
Prior art keywords
light
electrically connected
node
transistor
control
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Application number
PCT/CN2022/082246
Other languages
English (en)
French (fr)
Inventor
李佳龙
Original Assignee
惠州华星光电显示有限公司
Tcl华星光电技术有限公司
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Application filed by 惠州华星光电显示有限公司, Tcl华星光电技术有限公司 filed Critical 惠州华星光电显示有限公司
Priority to US17/756,045 priority Critical patent/US20240153438A1/en
Publication of WO2023173453A1 publication Critical patent/WO2023173453A1/zh

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0439—Pixel structures
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/027—Details of drivers for data electrodes, the drivers handling digital grey scale data, e.g. use of D/A converters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0271—Adjustment of the gradation levels within the range of the gradation scale, e.g. by redistribution or clipping

Definitions

  • the present application relates to the field of display, and specifically to a pixel circuit, a pixel driving method and a display device.
  • Micro-LED micro light-emitting diode
  • Mini-LED mini light-emitting diode
  • the traditional current control drive circuit cannot realize separate driving of high and low gray scales, and cannot meet the requirements of both high gray scale and high gray scale. It can drive light for a long time and meet the requirements of low gray scale and high current driving.
  • the present application provides a pixel circuit, a pixel driving method and a display device, which can solve the problem that the existing current control driving circuit cannot realize separate driving of high and low gray levels, and cannot satisfy both the long-duration light-emitting driving of high gray levels and the low gray levels. High current drive problem.
  • this application provides a pixel circuit, including: a driving module and a light-emitting module; wherein,
  • the driving module is electrically connected to the first power line, the first node and the second node respectively.
  • the driving module is used to control the conduction or disconnection of the first power supply under the control of the potential of the first node.
  • the light-emitting module includes a first light-emitting unit, a first light-emitting element, a second light-emitting unit and a second light-emitting element;
  • the first light-emitting unit is electrically connected to the data line, the scan line, the first node, the second node and the first light-emitting element respectively.
  • the first light-emitting unit is used to adjust the potential of the scan line. Under control, control the potential of the first node according to the potential of the data line to control the connection between the first power line and the first light-emitting element;
  • the second light-emitting unit is electrically connected to the data line, the scan line, the second node and the second light-emitting element respectively.
  • the second light-emitting unit is used to control the potential of the scan line.
  • the connection between the second node and the second light-emitting element is controlled to be turned on or off according to the potential of the data line.
  • the driving module includes a first transistor, a first end of the first transistor is electrically connected to the first node, and a second end of the first transistor is electrically connected to the first node.
  • the power line is electrically connected, and the third terminal of the first transistor is electrically connected to the second node.
  • the first light-emitting unit includes a second transistor, a third transistor, a fourth transistor, a first voltage stabilizing diode and a first capacitor;
  • the first end of the second transistor is electrically connected to the scan line, the first end of the second transistor is electrically connected to the data line, and the third end of the second transistor is electrically connected to the first node. connect;
  • the first end of the third transistor is electrically connected to the scan line, the first end of the third transistor is electrically connected to the first node, and the third end of the third transistor is electrically connected to the third node. ;
  • the first end of the fourth transistor is electrically connected to the control line
  • the second end of the fourth transistor is electrically connected to the second node
  • the third end of the fourth transistor is electrically connected to the first light-emitting element.
  • the anode terminal is electrically connected
  • the cathode terminal of the first light-emitting element is electrically connected to the second power line;
  • the anode terminal of the first Zener diode is electrically connected to the first node, and the cathode terminal of the first Zener diode is electrically connected to the third node;
  • the first end of the first capacitor is electrically connected to the third node, and the second end of the first capacitor is electrically connected to the second node.
  • the first light-emitting unit further includes a fifth transistor, a first end of the fifth transistor is electrically connected to the reset control line, and a second end of the fifth transistor is electrically connected to the reset line. connection, the third terminal of the fifth transistor is electrically connected to the third node.
  • the second light-emitting unit includes a sixth transistor and a seventh transistor;
  • the first end of the sixth transistor is electrically connected to the scan line, the second end of the sixth transistor is electrically connected to the data line, and the third end of the sixth transistor is electrically connected to the fourth node;
  • the first terminal of the seventh transistor is electrically connected to the fourth node, the second terminal of the seventh transistor is electrically connected to the second node, and the third terminal of the seventh transistor is electrically connected to the second node.
  • the anode terminal of the light-emitting element is electrically connected;
  • the cathode terminal of the second light-emitting element is electrically connected to the second power line.
  • the second light-emitting unit further includes an eighth transistor, a second voltage stabilizing diode and a second capacitor;
  • the first end of the eighth transistor is electrically connected to the scan line, the second end of the eighth transistor is electrically connected to the fourth node, and the third end of the eighth transistor is electrically connected to the fifth node. ;
  • the anode terminal of the second Zener diode is electrically connected to the fourth node, and the cathode terminal of the second Zener diode is electrically connected to the fifth node;
  • the first end of the second capacitor is electrically connected to the fifth node, the second end of the second capacitor is electrically connected to the anode end of the second light-emitting element; the cathode end of the second light-emitting element is electrically connected to The second power source is electrically connected.
  • the second light-emitting unit further includes a ninth transistor, a first end of the ninth transistor is electrically connected to the reset control line, and a second end of the ninth transistor is electrically connected to the reset line. connection, the third terminal of the ninth transistor is electrically connected to the fifth node.
  • the first light-emitting element is a micro light-emitting diode or a mini light-emitting diode
  • the second light-emitting element is a micro light-emitting diode or a mini light-emitting diode.
  • this application also provides a pixel driving method, which is applied to the above-mentioned pixel circuit.
  • the pixel driving method includes:
  • the driving module controls to turn on or off the connection between the first power line and the second node under the control of the potential of the first node
  • the first light-emitting unit controls the potential of the first node according to the potential of the data line under the control of the potential of the scan line to control the conduction or disconnection of the first power line and the third power line.
  • the second light-emitting unit is controlled to turn on or off the connection between the second node and the second light-emitting unit according to the potential of the data line under the control of the potential of the scan line.
  • the display cycle includes a first control stage and a second control stage set in sequence
  • the pixel driving method includes: in high grayscale display mode:
  • the first light-emitting unit stores the potential of the data line under the control of the potential of the scan line, and outputs the potential of the data line to the first node, controlling Turn on the connection between the first power line and the second node, thereby controlling the connection between the first power line and the first light-emitting element;
  • the potential of the first node is equal to the potential of the data line stored in the first light-emitting unit in the first control stage, and the first power line and the third power line are controlled to be connected.
  • the connection between the two nodes thereby controls the connection between the first power line and the first light-emitting element; in the second control stage, the second light-emitting unit controls the scanning line Next, the connection between the second node and the second light-emitting element is controlled and turned on according to the potential of the data line;
  • the pixel driving method also includes: in low grayscale display mode:
  • the second node is disconnected from the first light-emitting member
  • the first light-emitting unit stores the potential of the data line under the control of the potential of the scan line, and outputs the potential of the data line to the first node, controlling Connect the connection between the first power line and the second node;
  • the potential of the first node is equal to the potential of the data line stored in the first light-emitting unit in the first control stage, and the first power line and the third power line are controlled to be connected. connection between two nodes; in the second control stage, the second light-emitting unit is controlled to conduct the second node and the second node according to the potential of the data line under the control of the scan line. connection between light-emitting elements.
  • the display period further includes setting a third control stage after the second control stage;
  • the second light-emitting unit also stores the potential of the data line under the control of the scan line;
  • the second light-emitting unit controls the connection between the second node and the second light-emitting element based on the potential stored in the second control stage.
  • the time that the second light-emitting element lasts for emitting light in the low gray-scale display mode is shorter than the time that the first light-emitting element lasts for emitting light in the high gray-scale display mode.
  • the present application also provides a display device, which includes a pixel circuit, where the pixel circuit includes: a driving module and a light-emitting module; wherein,
  • the driving module is electrically connected to the first power line, the first node and the second node respectively.
  • the driving module is used to control the conduction or disconnection of the first power supply under the control of the potential of the first node.
  • the light-emitting module includes a first light-emitting unit, a first light-emitting element, a second light-emitting unit and a second light-emitting element;
  • the first light-emitting unit is electrically connected to the data line, the scan line, the first node, the second node and the first light-emitting element respectively.
  • the first light-emitting unit is used to adjust the potential of the scan line. Under control, control the potential of the first node according to the potential of the data line to control the connection between the first power line and the first light-emitting element;
  • the second light-emitting unit is electrically connected to the data line, the scan line, the second node and the second light-emitting element respectively.
  • the second light-emitting unit is used to control the potential of the scan line.
  • the connection between the second node and the second light-emitting element is controlled to be turned on or off according to the potential of the data line.
  • the driving module includes a first transistor, a first end of the first transistor is electrically connected to the first node, and a second end of the first transistor is electrically connected to the first node.
  • the power line is electrically connected, and the third terminal of the first transistor is electrically connected to the second node.
  • the first light-emitting unit includes a second transistor, a third transistor, a fourth transistor, a first voltage stabilizing diode and a first capacitor;
  • the first end of the second transistor is electrically connected to the scan line, the first end of the second transistor is electrically connected to the data line, and the third end of the second transistor is electrically connected to the first node. connect;
  • the first end of the third transistor is electrically connected to the scan line, the first end of the third transistor is electrically connected to the first node, and the third end of the third transistor is electrically connected to the third node. ;
  • the first end of the fourth transistor is electrically connected to the control line
  • the second end of the fourth transistor is electrically connected to the second node
  • the third end of the fourth transistor is electrically connected to the first light-emitting element.
  • the anode terminal is electrically connected; the cathode terminal of the first light-emitting element is electrically connected to the second power line.
  • the anode terminal of the first Zener diode is electrically connected to the first node, and the cathode terminal of the first Zener diode is electrically connected to the third node;
  • the first end of the first capacitor is electrically connected to the third node, and the second end of the first capacitor is electrically connected to the second node.
  • the first light-emitting unit further includes a fifth transistor, a first end of the fifth transistor is electrically connected to the reset control line, and a second end of the fifth transistor is electrically connected to the reset line. connection, the third terminal of the fifth transistor is electrically connected to the third node.
  • the second light-emitting unit includes a sixth transistor and a seventh transistor;
  • the first end of the sixth transistor is electrically connected to the scan line, the second end of the sixth transistor is electrically connected to the data line, and the third end of the sixth transistor is electrically connected to the fourth node;
  • the first terminal of the seventh transistor is electrically connected to the fourth node, the second terminal of the seventh transistor is electrically connected to the second node, and the third terminal of the seventh transistor is electrically connected to the second node.
  • the anode terminal of the light-emitting element is electrically connected;
  • the cathode terminal of the second light-emitting element is electrically connected to the second power line.
  • the second light-emitting unit further includes an eighth transistor, a second voltage stabilizing diode, and a second capacitor;
  • the first end of the eighth transistor is electrically connected to the scan line, the second end of the eighth transistor is electrically connected to the fourth node, and the third end of the eighth transistor is electrically connected to the fifth node. ;
  • the anode terminal of the second Zener diode is electrically connected to the fourth node, and the cathode terminal of the second Zener diode is electrically connected to the fifth node;
  • the first end of the second capacitor is electrically connected to the fifth node, the second end of the second capacitor is electrically connected to the anode end of the second light-emitting element; the cathode end of the second light-emitting element is electrically connected to The second power source is electrically connected.
  • the second light-emitting unit further includes a ninth transistor, a first end of the ninth transistor is electrically connected to the reset control line, and a second end of the ninth transistor is electrically connected to the reset line. connection, the third terminal of the ninth transistor is electrically connected to the fifth node.
  • the first light-emitting element is a micro-light-emitting diode or a mini-light-emitting diode
  • the second light-emitting element is a micro-light-emitting diode or a mini-light-emitting diode.
  • the pixel circuit, pixel driving method and display device provided by this application can realize independent driving of high and low gray scale voltages through current control and duration control, which not only satisfies long-duration driving of high gray scales, but also satisfies high current driving of low gray scales.
  • Figure 1 is a schematic structural diagram of a pixel circuit provided by an embodiment of the present application.
  • Figure 2 is a first circuit schematic diagram of the pixel circuit shown in Figure 1;
  • Figure 3 is a timing diagram of the specific embodiment of the pixel circuit shown in Figure 2 of the present application in high grayscale display mode during operation;
  • Figure 4 is a timing diagram of the specific embodiment of the pixel circuit shown in Figure 2 of the present application in low grayscale display mode during operation;
  • Figure 5 is a second circuit schematic diagram of the pixel circuit shown in Figure 1;
  • Figure 6 is a timing diagram of the specific embodiment of the pixel circuit shown in Figure 5 of the present application in low grayscale display mode when working;
  • FIG. 7 is a third circuit schematic diagram of the pixel circuit shown in FIG. 1 .
  • the transistors used in all embodiments of this application may be transistors, thin film transistors, field effect transistors, or other devices with the same characteristics.
  • one terminal is called the second terminal and the other terminal is called the third terminal.
  • the first terminal when the transistor is a triode, can be the base, the second terminal can be the collector, and the third terminal can be the emitter; or, the first terminal can be the base, and the second terminal can be the emitter. pole, the third terminal can be the collector.
  • the first terminal when the transistor is a thin film transistor or a field effect transistor, the first terminal can be a gate, the second terminal can be a drain, and the third terminal can be a source; or, the first terminal can be a gate, The second terminal can be the source, and the third terminal can be the drain.
  • FIG. 1 is a schematic structural diagram of a pixel circuit provided by an embodiment of the present application.
  • the pixel circuit provided by the embodiment of the present application includes a driving module 11 and a light-emitting module 12 .
  • the driving module 11 is electrically connected to the first power line VDD, the first node a1 and the second node a2 respectively.
  • the light-emitting module 12 includes a first light-emitting unit 121, a first light-emitting element 123, a second light-emitting unit 122 and a second light-emitting element 124.
  • the first light-emitting unit 121 is electrically connected to the data line D, the scan line S, the first node a1, the second node a2 and the first light-emitting element 123 respectively.
  • the second light-emitting unit 122 is electrically connected to the data line D, the scan line S, the second node a2 and the second light-emitting element 124 respectively.
  • the driving module 11 is used to control the connection between the first power line VDD and the second node a2 to be on or off under the control of the potential of the first node a1.
  • the first light-emitting unit 121 is used to control the potential of the first node a1 according to the potential of the data line D under the control of the potential of the scan line S, so as to control the conduction or disconnection between the first power line VDD and the first light-emitting element 123. connection between.
  • the second light-emitting unit 122 is used to control the connection between the second node a2 and the second light-emitting element 124 according to the potential of the data line D under the control of the potential of the scan line S.
  • the first light-emitting element 123 may be a Micro-LED (micro-light-emitting diode) or a Mini-LED (mini-light-emitting diode).
  • the second light-emitting element 124 may be a Micro-LED (micro-light-emitting diode) or a Mini-LED (mini-light-emitting diode), but is not limited thereto.
  • the pixel circuit of the embodiment of the present application can realize separate driving of high and low gray scale voltages through current control and duration control, which not only satisfies the long-duration driving of high gray scales, but also satisfies the high current driving of low gray scales; and, the embodiments of the present application also It can achieve high and low gray levels to work simultaneously through one data line.
  • the pixel circuit of the embodiment of the present application can adopt the current + light-emitting duration control mode.
  • different light-emitting units drive the corresponding light-emitting elements to emit light.
  • the light-emitting duration does not affect each other.
  • the high gray-scale light-emitting duration reaches Maximum, conducive to low power consumption.
  • the display cycle includes a first control stage and a second control stage set in sequence.
  • high grayscale display mode In high grayscale display mode:
  • the first light-emitting unit 121 stores the potential of the data line D under the control of the potential of the scan line S, outputs the potential of the data line D to the first node a1, and controls the conduction of the first power line VDD.
  • the potential of the first node a1 is equal to the potential of the data line D stored in the first light-emitting unit 121 in the first control stage, controlling the connection between the first power line VDD and the second node a2, thereby controlling The connection between the first power line VDD and the first light-emitting element 123 is turned on; in the second control stage, the second light-emitting unit 122 is controlled to turn on the second node a2 according to the potential of the data line D under the control of the scan line S. and the second light-emitting element 124 .
  • the first light-emitting unit 121 When the pixel circuit of the embodiment of the present application is working, in the high grayscale display mode, in the first control stage, the first light-emitting unit 121 directly connects the first power line VDD and the first light-emitting element through the potential on the data line D. 123, the driving module 11 drives the first light-emitting element 123 to emit light; in the second control stage, the first light-emitting unit 121 conducts the connection between the first power line VDD and the first light-emitting element 123 through the stored potential of the data line D. The driving module 11 drives the first light-emitting element 123 to emit light. In the high-grayscale display mode, the embodiment of the present application combines high driving current and high luminescence duration to achieve high-grayscale display and reduce backplane power consumption.
  • the display cycle includes a first control stage and a second control stage set in sequence.
  • low grayscale display mode In low grayscale display mode:
  • the second node a2 is disconnected from the first light-emitting element 123;
  • the first light-emitting unit 121 stores the potential of the data line D under the control of the potential of the scan line S, outputs the potential of the data line D to the first node a1, and controls the conduction of the first power line VDD.
  • the potential of the first node a1 is equal to the potential of the data line D stored in the first light-emitting unit 121 in the first control stage, and the connection between the first power line VDD and the second node a2 is controlled to be turned on;
  • the second light-emitting unit 122 controls the connection between the second node a2 and the second light-emitting element 124 according to the potential of the data line D under the control of the scan line S.
  • the duration of the second light-emitting element 124 emitting light in the low gray-scale display mode is shorter than the duration of the first light-emitting element 123 emitting light in the high gray-scale display mode.
  • Embodiments of the present application realize low gray-scale display by combining high driving current with low light emission duration, so as to realize low gray-scale display under the premise of high driving current.
  • the display cycle includes a first control stage, a second control stage and a third control stage set in sequence.
  • the display cycle includes a first control stage, a second control stage and a third control stage set in sequence.
  • the second node a2 is disconnected from the first light-emitting element 123;
  • the first light-emitting unit 121 stores the potential of the data line D under the control of the potential of the scan line S, outputs the potential of the data line D to the first node a1, and controls the conduction of the first power line VDD.
  • the potential of the first node a1 is equal to the potential of the data line D stored in the first light-emitting unit 121 in the first control stage, and the connection between the first power line VDD and the second node a2 is controlled to be turned on;
  • the second light-emitting unit 122 controls and conducts the connection between the second node a2 and the second light-emitting element 124 according to the potential of the data line D under the control of the scan line S; in the second control stage, the second light-emitting unit 122 The unit 122 also stores the potential of the data line D under the control of the scan line S;
  • the second light-emitting unit 122 controls the connection between the second node a2 and the second light-emitting element 124 based on the potential stored in the second control stage.
  • the time that the second light-emitting element 124 continues to emit light in the low gray-scale display mode is equal to the time that the first light-emitting element 123 continues to emit light in the high gray-scale display mode.
  • the duration of the first light-emitting element 123 emitting light is equal to the duration of the second light-emitting element 124 by design, so that when one light-emitting element emits abnormal light, the other light-emitting element can still emit light normally. This reduces dark spot defects and improves backplane yield.
  • the driving module 11 includes a first transistor T1.
  • the first terminal of the first transistor T1 is electrically connected to the first node a1.
  • the second terminal of the first transistor T1 is electrically connected to the first power supply line VDD.
  • the third terminal of the first transistor T1 is electrically connected to the second node a2.
  • the first light-emitting unit 121 includes a second transistor T2, a third transistor T3, a fourth transistor T4, a first zener diode VD1 and a first capacitor C1.
  • the first terminal of the second transistor T2 is electrically connected to the scan line S.
  • the first terminal of the second transistor T2 is electrically connected to the data line D.
  • the third terminal of the second transistor T2 is electrically connected to the first node a1.
  • the first terminal of the third transistor T3 is electrically connected to the scan line S.
  • the first terminal of the third transistor T3 is electrically connected to the first node a1.
  • the third terminal of the third transistor T3 is electrically connected to the third node a3.
  • the first end of the fourth transistor T4 is electrically connected to the control line K.
  • the second terminal of the fourth transistor T4 is electrically connected to the second node a2.
  • the third terminal of the fourth transistor T4 is electrically connected to the anode terminal of the first light-emitting element 123 .
  • the cathode terminal of the first light emitting element 123 is electrically connected to the second power supply line VSS.
  • the anode terminal of the first Zener diode VD1 is electrically connected to the first node a1.
  • the cathode terminal of the first Zener diode VD1 is electrically connected to the third node a3.
  • the first end of the first capacitor C1 is electrically connected to the third node a3.
  • the second end of the first capacitor C1 is electrically connected to the second node a2.
  • the second light-emitting unit 122 includes a sixth transistor T6 and a seventh transistor T7.
  • the first end of the sixth transistor T6 is electrically connected to the scan line S.
  • the second terminal of the sixth transistor T6 is electrically connected to the data line D.
  • the third terminal of the sixth transistor T6 is electrically connected to the fourth node.
  • the first terminal of the seventh transistor T7 is electrically connected to the fourth node a4.
  • the second terminal of the seventh transistor T7 is electrically connected to the second node a2.
  • the third terminal of the seventh transistor T7 is electrically connected to the anode terminal of the second light-emitting element 124 .
  • the cathode of the second light emitting element 124 is electrically connected to the second power supply line VSS.
  • the first transistor T1 and the seventh transistor T7 are both N-type transistors
  • the second transistor T2 , the third transistor T3 , the fourth transistor T4 and the sixth transistor T6 are all P-type transistors. transistor, but not limited to this.
  • the display cycle may include a first control phase t1 and a second control phase t2 set in sequence. .
  • the first light-emitting unit 121 stores the potential of the data line D under the control of the potential of the scan line S, and outputs the potential of the data line D to the first node a1.
  • the first transistor T1 , the second transistor T2 and the fourth transistor T4 are turned on, and the third transistor T3, the sixth transistor T6 and the seventh transistor T7 are turned off. Control the connection between the first power line VDD and the second node a2, thereby controlling the connection between the first power line VDD and the first light-emitting element 123;
  • the potential of the first node a1 is equal to the potential of the data line D stored in the first light-emitting unit 121 in the first control stage t1.
  • the first transistor T1, the third transistor T3, the fourth transistor T4, The sixth transistor T6 and the seventh transistor T7 are turned on, and the second transistor T2 is turned off.
  • the first light-emitting time of the first light-emitting element is the time between the first control phase t1 and the second control phase t2 .
  • the first light-emitting element emits light during operation, using a long first light-emitting time, and the signal provided by the data line D takes a value in a high current density range, and the two cooperate to Able to achieve 50-255 gray scale brightness.
  • the display cycle may include a first control phase t1 and a second control phase t2 set in sequence. .
  • the fourth transistor T4 is turned off, and under the control of the first light-emitting unit 121, the second node a2 is disconnected from the first light-emitting element 123;
  • the first light-emitting unit 121 is controlled by the potential of the scan line S.
  • the first transistor T1 and the second transistor T2 are turned on, storing the potential of the data line D, and converting the potential of the data line D.
  • the potential is output to the first node a1 to control the connection between the first power line VDD and the second node a2;
  • the potential of the first node a1 is equal to the potential of the data line D stored in the first light-emitting unit 121 in the first control stage t1.
  • the first transistor T1, the third transistor T3, the sixth transistor T6 and The seventh transistor T7 is turned on, and the second transistor T2 is turned off.
  • the second light-emitting unit 122 controls the connection between the second node a2 and the second light-emitting element 124 according to the potential of the data line D.
  • the second light-emitting time of the second light-emitting element is the time of the second control phase t2.
  • the second light-emitting element 124 emits light during operation, using an hour-long second light-emitting time, and the signal provided by the data line D takes a value in a high current density range. The two cooperate To be able to achieve 0-50 gray scale brightness.
  • FIG. 5 is a second circuit schematic diagram of the pixel circuit shown in FIG. 1 .
  • the difference between the pixel circuit shown in Figure 5 and the pixel circuit shown in Figure 2 is that the second light-emitting unit 122 in the pixel circuit shown in Figure 5 also includes an eighth transistor T8, a second zener diode VD2 and a third Two capacitors C2.
  • the first end of the eighth transistor T8 is electrically connected to the scan line S.
  • the second terminal of the eighth transistor T8 is electrically connected to the fourth node a4.
  • the third terminal of the eighth transistor T8 is electrically connected to the fifth node a5.
  • the anode terminal of the second Zener diode VD2 is electrically connected to the fourth node a4.
  • the cathode terminal of the second Zener diode VD2 is electrically connected to the fifth node a5.
  • the first end of the second capacitor C2 is electrically connected to the fifth node a5.
  • the second terminal of the second capacitor C2 is electrically connected to the anode terminal of the second light-emitting element 124 .
  • the cathode terminal of the second light emitting element 124 is electrically connected to the second power supply line VSS.
  • the display period may include a first control phase t1 and a second control phase t2 set in sequence. and the third control stage t3.
  • the fourth transistor T4 is turned off, and under the control of the first light-emitting unit 121, the second node a2 is disconnected from the first light-emitting element 123;
  • the first light-emitting unit 121 is controlled by the potential of the scan line S.
  • the first transistor T1 and the second transistor T2 are turned on, storing the potential of the data line D, and converting the potential of the data line D.
  • the potential is output to the first node a1 to control the connection between the first power line VDD and the second node a2;
  • the potential of the first node a1 is equal to the potential of the data line D stored in the first light-emitting unit 121 in the first control stage t1.
  • the first transistor T1, the third transistor T3, the sixth transistor T6 and The seventh transistor T7 is turned on, and the second transistor T2 is turned off.
  • the second light-emitting unit 122 controls the connection between the second node a2 and the second light-emitting element 124 according to the potential of the data line D.
  • the eighth transistor T8 is turned on, and the second light-emitting unit 122 also stores the potential of the data line D under the control of the scan line S.
  • the second light-emitting unit 122 controls the connection between the second node a2 and the second light-emitting element 124 based on the potential stored in the second control stage t2.
  • the third light-emitting time of the second light-emitting element is the time between the second control phase t2 and the third control phase t3 .
  • the second light-emitting element 124 emits light during operation, and the use time is the third light-emitting time, in which the first light-emitting time and the third light-emitting time are set to equal lengths.
  • the duration of the first light-emitting element 123 emitting light is equal to the duration of the second light-emitting element 124 through design, so that when one light-emitting element emits abnormal light, the other light-emitting element can still emit light normally, thereby reducing dark spots. defective, improving backplane yield.
  • FIG. 7 is a third circuit schematic diagram of the pixel circuit shown in FIG. 2 .
  • the difference between the pixel circuit shown in Figure 7 and the pixel circuit shown in Figure 5 is that: the first light-emitting unit in the pixel circuit shown in Figure 7 also includes a fifth transistor T5, and the second light-emitting unit also includes a ninth transistor. T9.
  • the first terminal of the fifth transistor T5 is electrically connected to the reset control line A, the second terminal of the fifth transistor T5 is electrically connected to the reset line B, and the third terminal of the fifth transistor T5 is electrically connected to the third node a3.
  • the first terminal of the ninth transistor T9 is electrically connected to the reset control line A, the second terminal of the ninth transistor T9 is electrically connected to the reset line B, and the third terminal of the ninth transistor T9 is electrically connected to the fifth node a5.
  • the pixel circuit can be reset and controlled.
  • the pixel driving method described in the embodiment of the present application is applied to the above-mentioned pixel circuit.
  • the pixel driving method includes:
  • the driving module controls the connection between the first power line and the second node under the control of the potential of the first node
  • the first light-emitting unit controls the potential of the first node according to the potential of the data line to control the connection between the first power line and the first light-emitting element;
  • the second light-emitting unit controls to turn on or off the connection between the second node and the second light-emitting unit according to the potential of the data line.
  • the pixel driving method of the embodiment of the present application can achieve separate driving of high and low gray scale voltages through current control and duration control, which not only satisfies the long-duration driving of high gray scales, but also satisfies the high current driving of low gray scales; and, the implementation of this application Examples can also enable high and low gray levels to work simultaneously through one data line.
  • the display cycle includes a first control stage and a second control stage set in sequence
  • Pixel driving methods include: In high grayscale display mode:
  • the first light-emitting unit stores the potential of the data line under the control of the potential of the scan line, outputs the potential of the data line to the first node, and controls the conduction between the first power line and the second node. connection, thereby controlling the connection between the first power line and the first light-emitting element;
  • the potential of the first node is equal to the potential of the data line stored in the first light-emitting unit in the first control stage, and the connection between the first power line and the second node is controlled to be turned on, thereby controlling the turn on of the first power supply.
  • the connection between the line and the first light-emitting element; in the second control stage, the second light-emitting unit controls the connection between the second node and the second light-emitting element according to the potential of the data line under the control of the scan line.
  • Pixel driving methods also include: In low grayscale display mode:
  • the second node is disconnected from the first light-emitting member
  • the first light-emitting unit stores the potential of the data line under the control of the potential of the scan line, outputs the potential of the data line to the first node, and controls the conduction between the first power line and the second node. Connection;
  • the potential of the first node is equal to the potential of the data line stored in the first light-emitting unit in the first control phase, controlling the connection between the first power line and the second node; in the second control phase, the Under the control of the scan line, the two light-emitting units control the connection between the second node and the second light-emitting element according to the potential of the data line.
  • the display cycle also includes a third control stage after setting and the second control stage;
  • the second light-emitting unit also stores the potential of the data line under the control of the scan line;
  • the second light-emitting unit controls the connection between the second node and the second light-emitting element based on the potential stored in the second control stage.
  • the display device described in the embodiment of the present application includes the above-mentioned pixel circuit.
  • the display device provided in the embodiment of the present application can be a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, or any other product or component with a display function.

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Abstract

一种像素电路、像素驱动方法及显示装置。像素电路包括驱动模块(11)以及发光模块(12)；发光模块(12)包括第一发光单元(121)、第一发光元件(123)、第二发光单元(122)以及第二发光元件(124)。

Description

像素电路、像素驱动方法及显示装置 技术领域
本申请涉及显示领域，具体涉及一种像素电路、像素驱动方法及显示装置。
 背景技术
Micro-LED(微型发光二极管)/Mini-LED(迷你发光二极管)因为其高亮度高信赖性在未来显示领域中有广泛应用。Micro-LED/Mini-LED作为一种自发光器件，其发光效率、亮度、色坐标会在低电流密度下随着电流密度变化而变化。故Micro‑LED/Mini‑LED要实现灰阶显示需在高电流密度下，即高电流下实现灰阶显示，传统的电流控制驱动电路无法实现高低灰阶单独驱动，不能既满足高灰阶的长时长发光驱动，又满足低灰阶的高电流驱动。
 技术问题
本申请提供一种像素电路、像素驱动方法及显示装置，可以解决现有的电流控制驱动电路无法实现高低灰阶单独驱动，不能既满足高灰阶的长时长发光驱动，又满足低灰阶的高电流驱动的问题。
 技术解决方案
第一方面，本申请提供一种像素电路，包括：驱动模块以及发光模块；其中，
所述驱动模块分别与第一电源线、第一节点以及第二节点电连接，所述驱动模块用于在所述第一节点的电位的控制下，控制导通或者断开所述第一电源线与所述第二节点之间的连通；
所述发光模块包括第一发光单元、第一发光元件、第二发光单元以及第二发光元件；
所述第一发光单元分别与数据线、扫描线、所述第一节点、所述第二节点以及所述第一发光元件电连接，所述第一发光单元用于在所述扫描线的电位的控制下，根据所述数据线的电位控制所述第一节点的电位，以控制导通或者断开所述第一电源线与所述第一发光元件之间的连通；
所述第二发光单元分别与所述数据线、所述扫描线、所述第二节点以及所述第二发光元件电连接，所述第二发光单元用于在所述扫描线的电位的控制下，根据所述数据线的电位控制导通或者断开所述第二节点与所述第二发光元件之间的连通。
在本申请提供的像素电路中，所述驱动模块包括第一晶体管，所述第一晶体管的第一端与所述第一节点电连接，所述第一晶体管的第二端与所述第一电源线电连接，所述第一晶体管的第三端与所述第二节点电连接。
在本申请提供的像素电路中，所述第一发光单元包括第二晶体管、第三晶体管、第四晶体管、第一稳压二极管以及第一电容；
所述第二晶体管的第一端与所述扫描线电连接，所述第二晶体管的第一端与所述数据线电连接，所述第二晶体管的第三端与所述第一节点电连接；
所述第三晶体管的第一端与所述扫描线电连接，所述第三晶体管的第一端与所述第一节点电连接，所述第三晶体管的第三端与第三节点电连接；
所述第四晶体管的第一端与控制线电连接，所述第四晶体管的第二端与所述第二节点电连接，所述第四晶体管的第三端与所述第一发光元件的阳极端电连接；所述第一发光元件的阴极端与第二电源线电连接；
所述第一稳压二极管的阳极端与所述第一节点电连接，所述第一稳压二极管的阴极端与所述第三节点电连接；
所述第一电容的第一端与所述第三节点电连接，所述第一电容的第二端与所述第二节点电连接接。
在本申请提供的像素电路中，所述第一发光单元还包括第五晶体管，所述第五晶体管的第一端与复位控制线电连接，所述第五晶体管的第二端与复位线电连接，所述第五晶体管的第三端与所述第三节点电连接。
在本申请提供的像素电路中，所述第二发光单元包括第六晶体管以及第七晶体管；
所述第六晶体管的第一端与所述扫描线电连接，所述第六晶体管的第二端与所述数据线电连接，所述第六晶体管的第三端与第四节点电连接；
所述第七晶体管的第一端与所述第四节点电连接，所述第七晶体管的第二端与所述第二节点电连接，所述第七晶体管的第三端与所述第二发光元件的阳极端电连接；
所述第二发光元件的阴极端与第二电源线电连接。
在本申请提供的像素电路中，所述第二发光单元还包括第八晶体管、第二稳压二极管以及第二电容；
所述第八晶体管的第一端与所述扫描线电连接，所述第八晶体管的第二端与所述第四节点电连接，所述第八晶体管的第三端与第五节点电连接；
所述第二稳压二极管的阳极端与所述第四节点电连接，所述第二稳压二极管的阴极端与所述第五节点电连接；
所述第二电容的第一端与所述第五节点电连接，所述第二电容的第二端与所述第二发光元件的阳极端电连接；所述第二发光元件的阴极端与第二电源电连接。
在本申请提供的像素电路中，所述第二发光单元还包括第九晶体管，所述第九晶体管的第一端与复位控制线电连接，所述第九晶体管的第二端与复位线电连接，所述第九晶体管的第三端与所述第五节点电连接。
在本申请提供的像素电路中，所述第一发光元件为微型发光二极管或者迷你发光二极管，所述第二发光元件为微型发光二极管或者迷你发光二极管。
第二方面，本申请还提供一种像素驱动方法，应用于以上所述的像素电路，所述像素驱动方法包括：
所述驱动模块在所述第一节点的电位的控制下，控制导通或者断开所述第一电源线与所述第二节点之间的连通；
所述第一发光单元在所述扫描线的电位的控制下，根据所述数据线的电位控制所述第一节点的电位，以控制导通或者断开所述第一电源线与所述第一发光元件之间的连通；
所述第二发光单元在所述扫描线的电位的控制下，根据所述数据线的电位控制导通或者断开所述第二节点与所述第二发光单元之间的连通。
在本申请提供的像素驱动方法中，显示周期包括依次设置的第一控制阶段以及第二控制阶段；
所述像素驱动方法包括：在高灰阶显示模式下：
在所述第一控制阶段，所述第一发光单元在所述扫描线的电位的控制下，存储所述数据线的电位，并将所述数据线的电位输出至所述第一节点，控制导通所述第一电源线与所述第二节点之间的连接，从而控制导通所述第一电源线与所述第一发光元件之间的连通；
在所述第二控制阶段，所述第一节点的电位等于所述第一控制阶段所述第一发光单元存储的所述数据线的电位，控制导通所述第一电源线与所述第二节点之间的连接，从而控制导通所述第一电源线与所述第一发光元件之间的连通；在所述第二控制阶段，所述第二发光单元在所述扫描线的控制下，根据所述数据线的电位控制导通所述第二节点与所述第二发光元件之间的连通；
所述像素驱动方法还包括：在低灰阶显示模式下：
在所述第一控制阶段以及所述第二控制阶段，在所述第一发光单元的控制下，所述第二节点与所述第一发光件断开；
在所述第一控制阶段，所述第一发光单元在所述扫描线的电位的控制下，存储所述数据线的电位，并将所述数据线的电位输出至所述第一节点，控制导通所述第一电源线与所述第二节点之间的连接；
在所述第二控制阶段，所述第一节点的电位等于所述第一控制阶段所述第一发光单元存储的所述数据线的电位，控制导通所述第一电源线与所述第二节点之间的连接；在所述第二控制阶段，所述第二发光单元在所述扫描线的控制下，根据所述数据线的电位控制导通所述第二节点与所述第二发光元件之间的连通。
在本申请提供的像素驱动方法中，所述显示周期还包括设置与所述第二控制阶段后的第三控制阶段；
在所述第二控制阶段，所述第二发光单元还在所述扫描线的控制下，存储所述数据线的电位；
在所述第三控制阶段，所述第二发光单元基于在所述第二控制阶段存储的电位，控制导通所述第二节点与所述第二发光元件之间的连通。
在本申请提供的像素驱动方法中，在所述低灰阶显示模式下所述第二发光元件发光持续的时间小于在所述高灰阶显示模式下所述第一发光元件发光持续的时间。
第三方面，本申请还提供一种显示装置，其包括包括像素电路，所述像素电路包括：驱动模块以及发光模块；其中，
所述驱动模块分别与第一电源线、第一节点以及第二节点电连接，所述驱动模块用于在所述第一节点的电位的控制下，控制导通或者断开所述第一电源线与所述第二节点之间的连通；
所述发光模块包括第一发光单元、第一发光元件、第二发光单元以及第二发光元件；
所述第一发光单元分别与数据线、扫描线、所述第一节点、所述第二节点以及所述第一发光元件电连接，所述第一发光单元用于在所述扫描线的电位的控制下，根据所述数据线的电位控制所述第一节点的电位，以控制导通或者断开所述第一电源线与所述第一发光元件之间的连通；
所述第二发光单元分别与所述数据线、所述扫描线、所述第二节点以及所述第二发光元件电连接，所述第二发光单元用于在所述扫描线的电位的控制下，根据所述数据线的电位控制导通或者断开所述第二节点与所述第二发光元件之间的连通。
在本申请提供的显示装置中，所述驱动模块包括第一晶体管，所述第一晶体管的第一端与所述第一节点电连接，所述第一晶体管的第二端与所述第一电源线电连接，所述第一晶体管的第三端与所述第二节点电连接。
在本申请提供的显示装置中，所述第一发光单元包括第二晶体管、第三晶体管、第四晶体管、第一稳压二极管以及第一电容；
所述第二晶体管的第一端与所述扫描线电连接，所述第二晶体管的第一端与所述数据线电连接，所述第二晶体管的第三端与所述第一节点电连接；
所述第三晶体管的第一端与所述扫描线电连接，所述第三晶体管的第一端与所述第一节点电连接，所述第三晶体管的第三端与第三节点电连接；
所述第四晶体管的第一端与控制线电连接，所述第四晶体管的第二端与所述第二节点电连接，所述第四晶体管的第三端与所述第一发光元件的阳极端电连接；所述第一发光元件的阴极端与第二电源线电连接。
所述第一稳压二极管的阳极端与所述第一节点电连接，所述第一稳压二极管的阴极端与所述第三节点电连接；
所述第一电容的第一端与所述第三节点电连接，所述第一电容的第二端与所述第二节点电连接接。
在本申请提供的显示装置中，所述第一发光单元还包括第五晶体管，所述第五晶体管的第一端与复位控制线电连接，所述第五晶体管的第二端与复位线电连接，所述第五晶体管的第三端与所述第三节点电连接。
在本申请提供的显示装置中中，所述第二发光单元包括第六晶体管以及第七晶体管；
所述第六晶体管的第一端与所述扫描线电连接，所述第六晶体管的第二端与所述数据线电连接，所述第六晶体管的第三端与第四节点电连接；
所述第七晶体管的第一端与所述第四节点电连接，所述第七晶体管的第二端与所述第二节点电连接，所述第七晶体管的第三端与所述第二发光元件的阳极端电连接；
所述第二发光元件的阴极端与第二电源线电连接。
在本申请提供的显示装置中，所述第二发光单元还包括第八晶体管、第二稳压二极管以及第二电容；
所述第八晶体管的第一端与所述扫描线电连接，所述第八晶体管的第二端与所述第四节点电连接，所述第八晶体管的第三端与第五节点电连接；
所述第二稳压二极管的阳极端与所述第四节点电连接，所述第二稳压二极管的阴极端与所述第五节点电连接；
所述第二电容的第一端与所述第五节点电连接，所述第二电容的第二端与所述第二发光元件的阳极端电连接；所述第二发光元件的阴极端与第二电源电连接。
在本申请提供的显示装置中，所述第二发光单元还包括第九晶体管，所述第九晶体管的第一端与复位控制线电连接，所述第九晶体管的第二端与复位线电连接，所述第九晶体管的第三端与所述第五节点电连接。
在本申请提供的显示装置中，所述第一发光元件为微型发光二极管或者迷你发光二极管，所述第二发光元件为微型发光二极管或者迷你发光二极管。
 有益效果
本申请提供的像素电路、像素驱动方法及显示装置，可以通过电流控制与时长控制来实现高低灰阶电压单独驱动，既满足高灰阶的长时长驱动，又满足低灰阶的高电流驱动。
 附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本申请实施例提供的像素电路的结构示意图；
图2为图1所示的像素电路的第一种电路示意图；
图3是本申请如图2所示的像素电路的具体实施例在工作时，在高灰阶显示模式下的时序图；
图4是本申请如图2所示的像素电路的具体实施例在工作时，在低灰阶显示模式下的时序图；
图5为为图1所示的像素电路的第二种电路示意图；
图6是本申请如图5所示的像素电路的具体实施例在工作时，在低灰阶显示模式下的时序图；
图7为为图1所示的像素电路的第三种电路示意图。
 本发明的实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本申请的一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
本申请所有实施例中采用的晶体管均可以为三极管、薄膜晶体管或场效应管或其他特性相同的器件。在本申请实施例中，为区分晶体管除第一端（控制端）之外的两端，将其中一端称为第二端，另一端称为第三端。
在实际操作时，当晶体管为三极管时，第一端可以为基极，第二端可以为集电极，第三端可以发射极；或者，第一端可以为基极，第二端可以为发射极，第三端可以集电极。
在实际操作时，当晶体管为薄膜晶体管或场效应管时，第一端可以为栅极，第二端可以为漏极，第三端可以为源极；或者，第一端可以为栅极，第二端可以为源极，第三端可以为漏极。
请参阅图1，图1为本申请实施例提供的像素电路的结构示意图。如图1所示，本申请实施例提供的像素电路包括驱动模块11以及发光模块12。驱动模块11分别与第一电源线VDD、第一节点a1以及第二节点a2电连接。发光模块12包括第一发光单元121、第一发光元件123、第二发光单元122以及第二发光元件124。第一发光单元121分别与数据线D、扫描线S、第一节点a1、第二节点a2以及第一发光元件123电连接。第二发光单元122分别与数据线D、扫描线S、第二节点a2以及第二发光元件124电连接。
其中，驱动模块11用于在第一节点a1的电位的控制下，控制导通或者断开第一电源线VDD与第二节点a2之间的连通。第一发光单元121用于在扫描线S的电位的控制下，根据数据线D的电位控制第一节点a1的电位，以控制导通或者断开第一电源线VDD与第一发光元件123之间的连通。第二发光单元122用于在扫描线S的电位的控制下，根据数据线D的电位控制导通或者断开第二节点a2与第二发光元件124之间的连通。
在本申请实施例中，第一发光元件123可以为Micro-LED(微型发光二极管)或Mini-LED(迷你发光二极管)。第二发光元件124可以为Micro-LED(微型发光二极管)或Mini-LED(迷你发光二极管)，但不以此为限。
本申请实施例的像素电路可以通过电流控制与时长控制来实现高低灰阶电压单独驱动，既满足高灰阶的长时长驱动，又满足低灰阶的高电流驱动；并且，本申请实施例还可以实现高低灰阶通过一条数据线同时工作。
本申请实施例的像素电路可以采用电流+发光时长控制模式，在高灰阶、低灰阶下，通过不同的发光单元驱动相应的发光元件发光，发光时长互不影响，高灰阶发光时长达到最大，利于低功耗。
本申请实施例的像素电路在工作时，显示周期包括依次设置的第一控制阶段和第二控制阶段。在高灰阶显示模式下：
在第一控制阶段，第一发光单元121在扫描线S的电位的控制下，存储数据线D的电位，并将数据线D的电位输出至第一节点a1，控制导通第一电源线VDD与第二节点a2之间的连接，从而控制导通第一电源线VDD与第一发光元件123之间的连通；
在第二控制阶段，第一节点a1的电位等于第一控制阶段第一发光单元121存储的数据线D的电位，控制导通第一电源线VDD与第二节点a2之间的连接，从而控制导通第一电源线VDD与第一发光元件123之间的连通；在第二控制阶段，第二发光单元122在扫描线S的控制下，根据数据线D的电位控制导通第二节点a2与第二发光元件124之间的连通。
本申请实施例的像素电路在工作时，在高灰阶显示模式下，在第一控制阶段，第一发光单元121通过数据线D上的电位直接导通第一电源线VDD与第一发光元件123之间的连接，驱动模块11驱动第一发光元件123发光；在第二控制阶段，第一发光单元121通过存储的数据线D的电位导通第一电源线VDD与第一发光元件123之间的连接，驱动模块11驱动第一发光元件123发光。在高灰阶显示模式下，本申请实施例通过高驱动电流和高发光时长相结合，以实现高灰阶显示，能够降低背板功耗。
本申请实施例的像素电路在工作时，显示周期包括依次设置的第一控制阶段和第二控制阶段。在低灰阶显示模式下：
在第一控制阶段以及第二控制阶段，在第一发光单元121的控制下，第二节点a2与第一发光元件123断开；
在第一控制阶段，第一发光单元121在扫描线S的电位的控制下，存储数据线D的电位，并将数据线D的电位输出至第一节点a1，控制导通第一电源线VDD与第二节点a2之间的连接；
在第二控制阶段，第一节点a1的电位等于第一控制阶段第一发光单元121存储的数据线D的电位，控制导通第一电源线VDD与第二节点a2之间的连接；在第二控制阶段，第二发光单元122在扫描线S的控制下，根据数据线D的电位控制导通第二节点a2与第二发光元件124之间的连通。
在低灰阶显示模式下第二发光元件124发光持续的时间小于在高灰阶显示模式下第一发光元件123发光持续的时间。本申请实施例通过高驱动电流与低发光时长相结合以实现低灰阶显示，以能够在高驱动电流的前提下实现低灰阶显示。
本申请实施例的像素电路在工作时，显示周期包括依次设置的第一控制阶段、第二控制阶段和第三控制阶段。在低灰阶显示模式下：
在第一控制阶段以及第二控制阶段，在第一发光单元121的控制下，第二节点a2与第一发光元件123断开；
在第一控制阶段，第一发光单元121在扫描线S的电位的控制下，存储数据线D的电位，并将数据线D的电位输出至第一节点a1，控制导通第一电源线VDD与第二节点a2之间的连接；
在第二控制阶段，第一节点a1的电位等于第一控制阶段第一发光单元121存储的数据线D的电位，控制导通第一电源线VDD与第二节点a2之间的连接；在第二控制阶段，第二发光单元122在扫描线S的控制下，根据数据线D的电位控制导通第二节点a2与第二发光元件124之间的连通；在第二控制阶段，第二发光单元122还在扫描线S的控制下，存储数据线D的电位；
在第三控制阶段，第二发光单元122基于在第二控制阶段存储的电位，控制导通第二节点a2与第二发光元件124之间的连通。
在低灰阶显示模式下第二发光元件124发光持续的时间等于在高灰阶显示模式下第一发光元件123发光持续的时间。在本申请实施例的像素电路中，通过设计使得第一发光元件123发光的持续时间等于第二发光元件124的持续时间，使得在一个发光元件发光异常时，另一个发光元件仍可正常发光，进而降低暗点不良，提升背板良率。
具体的，请参阅图2，图2为图1所示的像素电路的第一种电路示意图。结合图1、图2所示，驱动模块11包括第一晶体管T1。第一晶体管T1的第一端与第一节点a1电连接。第一晶体管T1的第二端与第一电源线VDD电连接。第一晶体管T1的第三端与第二节点a2电连接。
结合图1、图2所示，第一发光单元121包括第二晶体管T2、第三晶体管T3、第四晶体管T4、第一稳压二极管VD1以及第一电容C1。
第二晶体管T2的第一端与所述扫描线S电连接。第二晶体管T2的第一端与数据线D电连接。第二晶体管T2的第三端与第一节点a1电连接。
第三晶体管T3的第一端与扫描线S电连接。第三晶体管T3的第一端与第一节点a1电连接。第三晶体管T3的第三端与第三节点a3电连接。
第四晶体管T4的第一端与控制线K电连接。第四晶体管T4的第二端与第二节点a2电连接。第四晶体管T4的第三端与第一发光元件123的阳极端电连接。第一发光元件123的阴极端与第二电源线VSS电连接。
第一稳压二极管VD1的阳极端与第一节点a1电连接。第一稳压二极管VD1的阴极端与第三节点a3电连接。
第一电容C1的第一端与第三节点a3电连接。第一电容C1的第二端与第二节点a2电连接接。
结合图1、图2所示，第二发光单元122包括第六晶体管T6以及第七晶体管T7。
第六晶体管T6的第一端与扫描线S电连接。第六晶体管T6的第二端与数据线D电连接。第六晶体管T6的第三端与第四节点电连接。
第七晶体管T7的第一端与第四节点a4电连接。第七晶体管T7的第二端与第二节点a2电连接。第七晶体管T7的第三端与第二发光元件124的阳极端电连接。第二发光元件124的阴极与第二电源线VSS电连接。
其中，在图2所示的像素电路中，第一晶体管T1以及第七晶体管T7均为N型晶体管，第二晶体管T2、第三晶体管T3、第四晶体管T4以及第六晶体管T6均为P型晶体管，但不以此为限。
本申请如图2所示的像素电路的具体实施例在工作时，在高灰阶显示模式下，如图3所示，显示周期可以包括依次设置的第一控制阶段t1和第二控制阶段t2。
在第一控制阶段t1，第一发光单元121在扫描线S的电位的控制下，存储数据线D的电位，并将数据线D的电位输出至第一节点a1，此时，第一晶体管T1、第二晶体管T2以及第四晶体管T4导通，第三晶体管T3、第六晶体管T6以及第七晶体管T7关闭。控制导通第一电源线VDD与第二节点a2之间的连接，从而控制导通第一电源线VDD与第一发光元件123之间的连通；
在第二控制阶段t2，第一节点a1的电位等于第一控制阶段t1第一发光单元121存储的数据线D的电位，此时，第一晶体管T1、第三晶体管T3、第四晶体管T4、第六晶体管T6以及第七晶体管T7导通，第二晶体管T2关闭。控制导通第一电源线VDD与第二节点a2之间的连接，从而控制导通第一电源线VDD与第一发光元件123之间的连通；在第二控制阶段t2，第二发光单元122在扫描线S的控制下，根据数据线D的电位控制导通第二节点a2与第二发光元件124之间的连通。
如图3所示，第一发光元件的第一发光时间为第一控制阶段t1与第二控制阶段t2的时间。本申请如图3所述的像素电路的具体实施例在工作时第一发光元件发光，使用大时长的第一发光时间，数据线D提供的信号在高电流密度区间取值，二者配合以能够实现50-255灰阶亮度。
本申请如图2所示的像素电路的具体实施例在工作时，在低灰阶显示模式下，如图4所示，显示周期可以包括依次设置的第一控制阶段t1和第二控制阶段t2。
在第一控制阶段t1以及第二控制阶段t2，此时，第四晶体管T4关闭，在第一发光单元121的控制下，第二节点a2与第一发光元件123断开；
在第一控制阶段t1，第一发光单元121在扫描线S的电位的控制下，此时，第一晶体管T1、第二晶体管T2导通，存储数据线D的电位，并将数据线D的电位输出至第一节点a1，控制导通第一电源线VDD与第二节点a2之间的连接；
在第二控制阶段t2，第一节点a1的电位等于第一控制阶段t1第一发光单元121存储的数据线D的电位，此时，第一晶体管T1、第三晶体管T3、第六晶体管T6以及第七晶体管T7导通，第二晶体管T2关闭。第二发光单元122在扫描线S的控制下，根据数据线D的电位控制导通第二节点a2与第二发光元件124之间的连通。
如图4所示第二发光元件的第二发光时间为第二控制阶段t2的时间。本申请如图4所述的像素电路的具体实施例在工作时第二发光元件124发光，使用小时长的第二发光时间，数据线D提供的信号在高电流密度区间取值，二者配合以能够实现0-50灰阶亮度。
请参阅图5，图5为为图1所示的像素电路的第二种电路示意图。其中，图5所示的像素电路与图2所示的像素电路的区别在于：图5所示的像素电路中的第二发光单元122还包括第八晶体管T8、第二稳压二极管VD2以及第二电容C2。
第八晶体管T8的第一端与扫描线S电连接。第八晶体管T8的第二端与第四节点a4电连接。第八晶体管T8的第三端与第五节点a5电连接。
第二稳压二极管VD2的阳极端与第四节点a4电连接。第二稳压二极管VD2的阴极端与第五节点a5电连接。
第二电容C2的第一端与第五节点a5电连接。第二电容C2的第二端与第二发光元件124的阳极端电连接。第二发光元件124的阴极端与第二电源线VSS电连接。
本申请如图5所示的像素电路的具体实施例在工作时，在低灰阶显示模式下，如图6所示，显示周期可以包括依次设置的第一控制阶段t1、第二控制阶段t2以及第三控制阶段t3。
在第一控制阶段t1以及第二控制阶段t2，此时，第四晶体管T4关闭，在第一发光单元121的控制下，第二节点a2与第一发光元件123断开；
在第一控制阶段t1，第一发光单元121在扫描线S的电位的控制下，此时，第一晶体管T1、第二晶体管T2导通，存储数据线D的电位，并将数据线D的电位输出至第一节点a1，控制导通第一电源线VDD与第二节点a2之间的连接；
在第二控制阶段t2，第一节点a1的电位等于第一控制阶段t1第一发光单元121存储的数据线D的电位，此时，第一晶体管T1、第三晶体管T3、第六晶体管T6以及第七晶体管T7导通，第二晶体管T2关闭。第二发光单元122在扫描线S的控制下，根据数据线D的电位控制导通第二节点a2与第二发光元件124之间的连通。在第二控制阶段t2，此时，第八晶体管T8导通，第二发光单元122还在扫描线S的控制下，存储数据线D的电位。
在第三控制阶段t3，第二发光单元122基于在第二控制阶段t2存储的电位，控制导通第二节点a2与第二发光元件124之间的连通。
如图6所示，第二发光元件的第三发光时间为第二控制阶段t2与第三控制阶段t3的时间。本申请如图5所述的像素电路的具体实施例在工作时第二发光元件124发光，使用时长为第三发光时间，其中第一发光时间与第三发光时间等时长设置，在本申请实施例的像素电路中，通过设计使得第一发光元件123发光的持续时间等于第二发光元件124的持续时间，使得在一个发光元件发光异常时，另一个发光元件仍可正常发光，进而降低暗点不良，提升背板良率。
请参阅图7，图7为图2所示的像素电路的第三中电路示意图。其中，图7所示的像素电路与图5所示的像素电路的区别在于：图7所示的像素电路中的第一发光单元还包括第五晶体管T5，第二发光单元还包括第九晶体管T9。
第五晶体管T5的第一端与复位控制线A电连接，第五晶体管T5的第二端与复位线B电连接，第五晶体管T5的第三端与第三节点a3电连接。
第九晶体管T9的第一端与复位控制线A电连接，第九晶体管T9的第二端与复位线B电连接，第九晶体管T9的第三端与第五节点a5电连接。
本申请实施例通过设置第五晶体管T5和第九晶体管T9，可以对该像素电路进行复位控制。
本申请实施例所述的像素驱动方法，应用于上述的像素电路，所述像素驱动方法包括：
驱动模块在第一节点的电位的控制下，控制导通或者断开第一电源线与第二节点之间的连通；
第一发光单元在扫描线的电位的控制下，根据数据线的电位控制第一节点的电位，以控制导通或者断开第一电源线与第一发光元件之间的连通；
第二发光单元在扫描线的电位的控制下，根据数据线的电位控制导通或者断开第二节点与第二发光单元之间的连通。
本申请实施例的像素驱动方法，可以通过电流控制与时长控制来实现高低灰阶电压单独驱动，既满足高灰阶的长时长驱动，又满足低灰阶的高电流驱动；并且，本申请实施例还可以实现高低灰阶通过一条数据线同时工作。
在本申请实施例的像素驱动方法中，显示周期包括依次设置的第一控制阶段以及第二控制阶段；
像素驱动方法包括：在高灰阶显示模式下：
在第一控制阶段，第一发光单元在扫描线的电位的控制下，存储数据线的电位，并将数据线的电位输出至第一节点，控制导通第一电源线与第二节点之间的连接，从而控制导通第一电源线与第一发光元件之间的连通；
在第二控制阶段，第一节点的电位等于第一控制阶段第一发光单元存储的数据线的电位，控制导通第一电源线与第二节点之间的连接，从而控制导通第一电源线与第一发光元件之间的连通；在第二控制阶段，第二发光单元在扫描线的控制下，根据数据线的电位控制导通第二节点与第二发光元件之间的连通。
像素驱动方法还包括：在低灰阶显示模式下：
在第一控制阶段以及第二控制阶段，在第一发光单元的控制下，第二节点与所述第一发光件断开；
在第一控制阶段，第一发光单元在扫描线的电位的控制下，存储数据线的电位，并将数据线的电位输出至第一节点，控制导通第一电源线与第二节点之间的连接；
在第二控制阶段，第一节点的电位等于第一控制阶段第一发光单元存储的数据线的电位，控制导通第一电源线与第二节点之间的连接；在第二控制阶段，第二发光单元在扫描线的控制下，根据数据线的电位控制导通第二节点与第二发光元件之间的连通。
在本申请实施例的像素驱动方法中，显示周期还包括设置与第二控制阶段后的第三控制阶段；
在第二控制阶段，第二发光单元还在扫描线的控制下，存储数据线的电位；
在第三控制阶段，第二发光单元基于在第二控制阶段存储的电位，控制导通第二节点与第二发光元件之间的连通。
本申请实施例所述的显示装置包括上述的像素电路。
本申请实施例所提供的显示装置可以为手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
以上所述是本申请的优选实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本申请所述原理的前提下，还可以作出若干改进和润饰，这些改进和润饰也应视为本发明的保护范围。

Claims (20)

  1. 一种像素电路，其包括：驱动模块以及发光模块；其中，
    所述驱动模块分别与第一电源线、第一节点以及第二节点电连接，所述驱动模块用于在所述第一节点的电位的控制下，控制导通或者断开所述第一电源线与所述第二节点之间的连通；
    所述发光模块包括第一发光单元、第一发光元件、第二发光单元以及第二发光元件；
    所述第一发光单元分别与数据线、扫描线、所述第一节点、所述第二节点以及所述第一发光元件电连接，所述第一发光单元用于在所述扫描线的电位的控制下，根据所述数据线的电位控制所述第一节点的电位，以控制导通或者断开所述第一电源线与所述第一发光元件之间的连通；
    所述第二发光单元分别与所述数据线、所述扫描线、所述第二节点以及所述第二发光元件电连接，所述第二发光单元用于在所述扫描线的电位的控制下，根据所述数据线的电位控制导通或者断开所述第二节点与所述第二发光元件之间的连通。
  2. 根据权利要求1所述的像素电路，其中，所述驱动模块包括第一晶体管，所述第一晶体管的第一端与所述第一节点电连接，所述第一晶体管的第二端与所述第一电源线电连接，所述第一晶体管的第三端与所述第二节点电连接。
  3. 根据权利要求1所述的像素电路，其中，所述第一发光单元包括第二晶体管、第三晶体管、第四晶体管、第一稳压二极管以及第一电容；
    所述第二晶体管的第一端与所述扫描线电连接，所述第二晶体管的第一端与所述数据线电连接，所述第二晶体管的第三端与所述第一节点电连接；
    所述第三晶体管的第一端与所述扫描线电连接，所述第三晶体管的第一端与所述第一节点电连接，所述第三晶体管的第三端与第三节点电连接；
    所述第四晶体管的第一端与控制线电连接，所述第四晶体管的第二端与所述第二节点电连接，所述第四晶体管的第三端与所述第一发光元件的阳极端电连接；所述第一发光元件的阴极端与第二电源线电连接；
    所述第一稳压二极管的阳极端与所述第一节点电连接，所述第一稳压二极管的阴极端与所述第三节点电连接；
    所述第一电容的第一端与所述第三节点电连接，所述第一电容的第二端与所述第二节点电连接接。
  4. 根据权利要求3所述的像素电路，其中，所述第一发光单元还包括第五晶体管，所述第五晶体管的第一端与复位控制线电连接，所述第五晶体管的第二端与复位线电连接，所述第五晶体管的第三端与所述第三节点电连接。
  5. 根据权利要求1所述的像素电路，其中，所述第二发光单元包括第六晶体管以及第七晶体管；
    所述第六晶体管的第一端与所述扫描线电连接，所述第六晶体管的第二端与所述数据线电连接，所述第六晶体管的第三端与第四节点电连接；
    所述第七晶体管的第一端与所述第四节点电连接，所述第七晶体管的第二端与所述第二节点电连接，所述第七晶体管的第三端与所述第二发光元件的阳极端电连接；
    所述第二发光元件的阴极端与第二电源线电连接。
  6. 根据权利要求5所述的像素电路，其中，所述第二发光单元还包括第八晶体管、第二稳压二极管以及第二电容；
    所述第八晶体管的第一端与所述扫描线电连接，所述第八晶体管的第二端与所述第四节点电连接，所述第八晶体管的第三端与第五节点电连接；
    所述第二稳压二极管的阳极端与所述第四节点电连接，所述第二稳压二极管的阴极端与所述第五节点电连接；
    所述第二电容的第一端与所述第五节点电连接，所述第二电容的第二端与所述第二发光元件的阳极端电连接；所述第二发光元件的阴极端与第二电源电连接。
  7. 根据权利要求6所述的像素电路，其中，所述第二发光单元还包括第九晶体管，所述第九晶体管的第一端与复位控制线电连接，所述第九晶体管的第二端与复位线电连接，所述第九晶体管的第三端与所述第五节点电连接。
  8. 根据权利要求1所述的像素电路，其中，所述第一发光元件为微型发光二极管或者迷你发光二极管，所述第二发光元件为微型发光二极管或者迷你发光二极管。
  9. 一种像素驱动方法，应用于像素电路，所述像素电路包括：驱动模块以及发光模块；
    所述驱动模块分别与第一电源线、第一节点以及第二节点电连接，所述驱动模块用于在所述第一节点的电位的控制下，控制导通或者断开所述第一电源线与所述第二节点之间的连通；
    所述发光模块包括第一发光单元、第一发光元件、第二发光单元以及第二发光元件；
    所述第一发光单元分别与数据线、扫描线、所述第一节点、所述第二节点以及所述第一发光元件电连接，所述第一发光单元用于在所述扫描线的电位的控制下，根据所述数据线的电位控制所述第一节点的电位，以控制导通或者断开所述第一电源线与所述第一发光元件之间的连通；
    所述第二发光单元分别与所述数据线、所述扫描线、所述第二节点以及所述第二发光元件电连接，所述第二发光单元用于在所述扫描线的电位的控制下，根据所述数据线的电位控制导通或者断开所述第二节点与所述第二发光元件之间的连通，所述像素驱动方法包括：
    所述驱动模块在所述第一节点的电位的控制下，控制导通或者断开所述第一电源线与所述第二节点之间的连通；
    所述第一发光单元在所述扫描线的电位的控制下，根据所述数据线的电位控制所述第一节点的电位，以控制导通或者断开所述第一电源线与所述第一发光元件之间的连通；
    所述第二发光单元在所述扫描线的电位的控制下，根据所述数据线的电位控制导通或者断开所述第二节点与所述第二发光单元之间的连通。
  10. 根据权利要求9所述的像素驱动方法，其中，显示周期包括依次设置的第一控制阶段以及第二控制阶段；
    所述像素驱动方法包括：在高灰阶显示模式下：
    在所述第一控制阶段，所述第一发光单元在所述扫描线的电位的控制下，存储所述数据线的电位，并将所述数据线的电位输出至所述第一节点，控制导通所述第一电源线与所述第二节点之间的连接，从而控制导通所述第一电源线与所述第一发光元件之间的连通；
    在所述第二控制阶段，所述第一节点的电位等于所述第一控制阶段所述第一发光单元存储的所述数据线的电位，控制导通所述第一电源线与所述第二节点之间的连接，从而控制导通所述第一电源线与所述第一发光元件之间的连通；在所述第二控制阶段，所述第二发光单元在所述扫描线的控制下，根据所述数据线的电位控制导通所述第二节点与所述第二发光元件之间的连通；
    所述像素驱动方法还包括：在低灰阶显示模式下：
    在所述第一控制阶段以及所述第二控制阶段，在所述第一发光单元的控制下，所述第二节点与所述第一发光件断开；
    在所述第一控制阶段，所述第一发光单元在所述扫描线的电位的控制下，存储所述数据线的电位，并将所述数据线的电位输出至所述第一节点，控制导通所述第一电源线与所述第二节点之间的连接；
    在所述第二控制阶段，所述第一节点的电位等于所述第一控制阶段所述第一发光单元存储的所述数据线的电位，控制导通所述第一电源线与所述第二节点之间的连接；在所述第二控制阶段，所述第二发光单元在所述扫描线的控制下，根据所述数据线的电位控制导通所述第二节点与所述第二发光元件之间的连通。
  11. 根据权利要求10所述的像素驱动方法，其中，所述显示周期还包括设置与所述第二控制阶段后的第三控制阶段；
    在所述第二控制阶段，所述第二发光单元还在所述扫描线的控制下，存储所述数据线的电位；
    在所述第三控制阶段，所述第二发光单元基于在所述第二控制阶段存储的电位，控制导通所述第二节点与所述第二发光元件之间的连通。
  12. 根据权利要求10所述的像素驱动方法，其中，在所述低灰阶显示模式下所述第二发光元件发光持续的时间小于在所述高灰阶显示模式下所述第一发光元件发光持续的时间。
  13. 一种显示装置，其包括像素电路，所述像素电路包括：驱动模块以及发光模块；其中，
    所述驱动模块分别与第一电源线、第一节点以及第二节点电连接，所述驱动模块用于在所述第一节点的电位的控制下，控制导通或者断开所述第一电源线与所述第二节点之间的连通；
    所述发光模块包括第一发光单元、第一发光元件、第二发光单元以及第二发光元件；
    所述第一发光单元分别与数据线、扫描线、所述第一节点、所述第二节点以及所述第一发光元件电连接，所述第一发光单元用于在所述扫描线的电位的控制下，根据所述数据线的电位控制所述第一节点的电位，以控制导通或者断开所述第一电源线与所述第一发光元件之间的连通；
    所述第二发光单元分别与所述数据线、所述扫描线、所述第二节点以及所述第二发光元件电连接，所述第二发光单元用于在所述扫描线的电位的控制下，根据所述数据线的电位控制导通或者断开所述第二节点与所述第二发光元件之间的连通。
  14. 根据权利要求13所述的显示装置，其中，所述驱动模块包括第一晶体管，所述第一晶体管的第一端与所述第一节点电连接，所述第一晶体管的第二端与所述第一电源线电连接，所述第一晶体管的第三端与所述第二节点电连接。
  15. 根据权利要求13所述的显示装置，其中，所述第一发光单元包括第二晶体管、第三晶体管、第四晶体管、第一稳压二极管以及第一电容；
    所述第二晶体管的第一端与所述扫描线电连接，所述第二晶体管的第一端与所述数据线电连接，所述第二晶体管的第三端与所述第一节点电连接；
    所述第三晶体管的第一端与所述扫描线电连接，所述第三晶体管的第一端与所述第一节点电连接，所述第三晶体管的第三端与第三节点电连接；
    所述第四晶体管的第一端与控制线电连接，所述第四晶体管的第二端与所述第二节点电连接，所述第四晶体管的第三端与所述第一发光元件的阳极端电连接；所述第一发光元件的阴极端与第二电源线电连接；
    所述第一稳压二极管的阳极端与所述第一节点电连接，所述第一稳压二极管的阴极端与所述第三节点电连接；
    所述第一电容的第一端与所述第三节点电连接，所述第一电容的第二端与所述第二节点电连接接。
  16. 根据权利要求15所述的显示装置，其中，所述第一发光单元还包括第五晶体管，所述第五晶体管的第一端与复位控制线电连接，所述第五晶体管的第二端与复位线电连接，所述第五晶体管的第三端与所述第三节点电连接。
  17. 根据权利要求13所述的显示装置，其中，所述第二发光单元包括第六晶体管以及第七晶体管；
    所述第六晶体管的第一端与所述扫描线电连接，所述第六晶体管的第二端与所述数据线电连接，所述第六晶体管的第三端与第四节点电连接；
    所述第七晶体管的第一端与所述第四节点电连接，所述第七晶体管的第二端与所述第二节点电连接，所述第七晶体管的第三端与所述第二发光元件的阳极端电连接；
    所述第二发光元件的阴极端与第二电源线电连接。
  18. 根据权利要求17所述的显示装置，其中，所述第二发光单元还包括第八晶体管、第二稳压二极管以及第二电容；
    所述第八晶体管的第一端与所述扫描线电连接，所述第八晶体管的第二端与所述第四节点电连接，所述第八晶体管的第三端与第五节点电连接；
    所述第二稳压二极管的阳极端与所述第四节点电连接，所述第二稳压二极管的阴极端与所述第五节点电连接；
    所述第二电容的第一端与所述第五节点电连接，所述第二电容的第二端与所述第二发光元件的阳极端电连接；所述第二发光元件的阴极端与第二电源电连接。
  19. 根据权利要求18所述的显示装置，其中，所述第二发光单元还包括第九晶体管，所述第九晶体管的第一端与复位控制线电连接，所述第九晶体管的第二端与复位线电连接，所述第九晶体管的第三端与所述第五节点电连接。
  20. 根据权利要求13所述的显示装置，其中，所述第一发光元件为微型发光二极管或者迷你发光二极管，所述第二发光元件为微型发光二极管或者迷你发光二极管。
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