WO2019041592A1 - Oled像素驱动电路及像素驱动方法 - Google Patents

Oled像素驱动电路及像素驱动方法 Download PDF

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Publication number
WO2019041592A1
WO2019041592A1 PCT/CN2017/113036 CN2017113036W WO2019041592A1 WO 2019041592 A1 WO2019041592 A1 WO 2019041592A1 CN 2017113036 W CN2017113036 W CN 2017113036W WO 2019041592 A1 WO2019041592 A1 WO 2019041592A1
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Prior art keywords
thin film
film transistor
scan signal
nth
low
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PCT/CN2017/113036
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English (en)
French (fr)
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邝继木
温亦谦
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深圳市华星光电半导体显示技术有限公司
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Priority to US15/735,200 priority Critical patent/US10223967B1/en
Publication of WO2019041592A1 publication Critical patent/WO2019041592A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]

Definitions

  • the present invention relates to the field of OLED driving technologies, and in particular, to an OLED pixel driving circuit and a pixel driving method.
  • OLED Organic Light Emitting Display
  • OLED panel has self-luminous, low driving voltage, high luminous efficiency, short response time, high definition and contrast, nearly 180° viewing angle, and wide temperature range. It can realize many advantages such as flexible display and large-area full-color display, and is recognized by the industry as the most promising display device.
  • the OLED panel has a plurality of pixels arranged in an array, each of which is driven by an OLED pixel driving circuit.
  • the OLED is a current driving device. When a current flows through the organic light emitting diode, the organic light emitting diode emits light, and the luminance of the light is determined by the current flowing through the organic light emitting diode itself.
  • Most existing integrated circuits (ICs) only transmit voltage signals, so the pixel driving circuit of the OLED needs to complete the task of converting the voltage signal into a current signal.
  • the conventional OLED pixel driving circuit is usually 2T1C, that is, a structure in which two thin film transistors are added with a capacitor to convert a voltage into a current.
  • a conventional 2T1C pixel driving circuit for an OLED includes: a first thin film transistor T10, a second thin film transistor T20, and a capacitor C10, the first thin film transistor T10 is a switching thin film transistor, and the second The thin film transistor T20 is a driving thin film transistor, and the capacitor C10 is a storage capacitor.
  • the gate of the first thin film transistor T10 is connected to the scan signal Scan(n) corresponding to the row of the pixel driving circuit, the source is connected to the data signal Data, the drain and the gate of the second thin film transistor T20, and the capacitor One end of the C10 is electrically connected; the drain of the second thin film transistor T20 is electrically connected to the positive voltage VDD of the power source, the source is electrically connected to the anode of the organic light emitting diode D10; and the cathode of the organic light emitting diode D10 is electrically connected.
  • the power supply has a negative voltage VSS; one end of the capacitor C10 is electrically connected to the drain of the first thin film transistor T10, and the other end is electrically connected to the source of the second thin film transistor T20.
  • VSS negative voltage
  • the scan signal Scan(n) controls the first thin film transistor T10 to be turned on, and the data signal Data passes through the first thin film transistor T10 to enter the gate of the second thin film transistor T20 and the capacitor C10, and then the first thin film transistor T10 is turned off.
  • the gate voltage of the second thin film transistor T20 can continue to maintain the data signal voltage, so that the second thin film transistor T20 is in an on state, and the driving current enters the organic light emitting diode through the second thin film transistor T20. D10, driving the organic light-emitting diode D10 to emit light.
  • I OLED K ⁇ (Vgs - V th ) 2
  • Vgs represents the voltage between the gate and the source of the driving thin film transistor
  • Vth represents the threshold voltage of the driving thin film transistor
  • the current I OLED flowing through the organic light emitting diode is related to the threshold voltage V th of the driving thin film transistor.
  • the threshold voltage Vth of the driving thin film transistor of each pixel in the panel is different, and the long-term operation causes the material of the thin film transistor to age, resulting in the threshold voltage Vth of the driving thin film transistor.
  • the drift occurs to affect the luminance of the light-emitting diode, and the pixel driving circuit of the conventional 2T1C structure does not have the function of compensating for the threshold voltage Vth of the driving thin film transistor, thereby causing uneven brightness of the display of the OLED panel.
  • An object of the present invention is to provide an OLED pixel driving circuit capable of compensating for a threshold voltage of a driving thin film transistor, eliminating the influence of a threshold voltage of a driving thin film transistor on an LED, and making the display brightness of the OLED panel uniform, thereby improving the display quality of the OLED panel.
  • Another object of the present invention is to provide an OLED pixel driving method capable of compensating for a threshold voltage of a driving thin film transistor, eliminating the influence of a threshold voltage of a driving thin film transistor on a light emitting diode, and making the display brightness of the OLED panel uniform, and improving the OLED.
  • the display quality of the panel is to provide an OLED pixel driving method capable of compensating for a threshold voltage of a driving thin film transistor, eliminating the influence of a threshold voltage of a driving thin film transistor on a light emitting diode, and making the display brightness of the OLED panel uniform, and improving the OLED.
  • the present invention first provides an OLED pixel driving circuit including a first thin film transistor, a second thin film transistor, a third thin film transistor, a fourth thin film transistor, a fifth thin film transistor, a sixth thin film transistor, and a first capacitor. , a second capacitor, and an organic light emitting diode;
  • the gate of the first thin film transistor is electrically connected to the first node, the drain is connected to the positive voltage of the power source, and the source is electrically connected to the drain of the third thin film transistor;
  • the first thin film transistor is a driving thin film transistor;
  • n be a positive integer greater than 1, the gate of the second thin film transistor is connected to the nth third scan signal corresponding to the row of the OLED pixel driving circuit, the source is connected to the data signal, and the drain is electrically connected.
  • the gate of the third thin film transistor is connected to the nth second scan signal corresponding to the row of the OLED pixel driving circuit, the drain is electrically connected to the source of the first thin film transistor, and the source is electrically connected to the third node;
  • the gate of the fourth thin film transistor is connected to the n-1th first scan signal corresponding to the previous row of the row of the OLED pixel driving circuit, and the source is electrically connected to one end of the second node and the second capacitor, and the drain Electrically connecting the third node and the other end of the second capacitor;
  • the gate of the fifth thin film transistor is connected to the nth first scan signal corresponding to the row of the OLED pixel driving circuit, the source is electrically connected to the second node, and the drain is connected to the negative voltage of the power supply;
  • the gate of the sixth thin film transistor is connected to the nth fourth scan signal corresponding to the row of the OLED pixel driving circuit, the source is electrically connected to the third node, and the drain is connected to the negative voltage of the power supply;
  • One end of the first capacitor is electrically connected to the first node, and the other end is electrically connected to the second node;
  • One end of the second capacitor is electrically connected to the second node, and the other end is electrically connected to the third node;
  • the anode of the organic light emitting diode is electrically connected to the third node, and the cathode is connected to a negative voltage of the power source.
  • the first thin film transistor, the second thin film transistor, the third thin film transistor, the fourth thin film transistor, the fifth thin film transistor, and the sixth thin film transistor are both low temperature polysilicon thin film transistors, oxide semiconductor thin film transistors, or amorphous silicon thin films Transistor.
  • the n-1th first scan signal, the nth first scan signal, the nth second scan signal, the nth third scan signal, the nth fourth scan signal, and the data signal are all externally Timing controller available.
  • the n-1th first scan signal, the nth first scan signal, the nth second scan signal, the nth third scan signal, the nth fourth scan signal, and the data signal are combined, Corresponding to a reset phase, a threshold voltage storage phase, a data write phase, a capacitor cascade phase, and a display illumination phase.
  • the n-1th first scan signal is high, the nth first scan signal is low, the nth second scan signal is low, and the nth third scan signal is For the low potential, the nth fourth scan signal is at a high potential, and the data signal is at a low potential;
  • the n-1th first scan signal is low, the nth first scan signal is high, the nth second scan signal is high, the nth third The scan signal is high, the nth fourth scan signal is low, and the data signal is the first high potential;
  • the n-1th first scan signal is low, the nth first scan signal is high, the nth second scan signal is low, the nth third The scan signal is high, the nth fourth scan signal is low, and the data signal is second high potential higher than the first high potential;
  • the n-1th first scan signal is low, the nth first scan signal is low, the nth second scan signal is low, the nth third The scan signal is low, the nth fourth scan signal is high, and the data signal is low;
  • the n-1th first scan signal is low
  • the nth A scan signal is low
  • the nth second scan signal is high
  • the nth third scan signal is low
  • the nth fourth scan signal is low
  • the data signal is low.
  • the invention also provides an OLED pixel driving method, comprising the following steps:
  • Step S1 providing an OLED pixel driving circuit
  • the OLED pixel driving circuit includes a first thin film transistor, a second thin film transistor, a third thin film transistor, a fourth thin film transistor, a fifth thin film transistor, a sixth thin film transistor, a first capacitor, a second capacitor, and an organic light emitting diode;
  • the gate of the first thin film transistor is electrically connected to the first node, the drain is connected to the positive voltage of the power source, and the source is electrically connected to the drain of the third thin film transistor;
  • the first thin film transistor is a driving thin film transistor;
  • n be a positive integer greater than 1, the gate of the second thin film transistor is connected to the nth third scan signal corresponding to the row of the OLED pixel driving circuit, the source is connected to the data signal, and the drain is electrically connected.
  • the gate of the third thin film transistor is connected to the nth second scan signal corresponding to the row of the OLED pixel driving circuit, the drain is electrically connected to the source of the first thin film transistor, and the source is electrically connected to the third node;
  • the gate of the fourth thin film transistor is connected to the n-1th first scan signal corresponding to the previous row of the row of the OLED pixel driving circuit, and the source is electrically connected to one end of the second node and the second capacitor, and the drain Electrically connecting the third node and the other end of the second capacitor;
  • the gate of the fifth thin film transistor is connected to the nth first scan signal corresponding to the row of the OLED pixel driving circuit, the source is electrically connected to the second node, and the drain is connected to the negative voltage of the power supply;
  • the gate of the sixth thin film transistor is connected to the nth fourth scan signal corresponding to the row of the OLED pixel driving circuit, the source is electrically connected to the third node, and the drain is connected to the negative voltage of the power supply;
  • One end of the first capacitor is electrically connected to the first node, and the other end is electrically connected to the second node;
  • One end of the second capacitor is electrically connected to the second node, and the other end is electrically connected to the third node;
  • the anode of the organic light emitting diode is electrically connected to the third node, and the cathode is connected to the negative voltage of the power source;
  • Step S2 entering a reset phase
  • the n-1th first scan signal provides a high potential
  • the nth first scan signal provides a low potential
  • the nth second scan signal provides a low potential
  • the nth third scan signal provides a low potential
  • the nth The fourth scan signal provides a high potential
  • the data signal provides a low potential
  • the second thin film transistor, the third thin film transistor, and the fifth thin film transistor are both turned off;
  • the fourth thin film transistor is turned on to reset the second capacitor;
  • the sixth thin film The transistor is turned on to reset the organic light emitting diode;
  • Step S3 entering a threshold voltage storage phase
  • the n-1th first scan signal transitions to a low potential, the nth first scan signal transitions to a high potential, the nth second scan signal transitions to a high potential, and the nth third scan signal transitions to a high level a potential, the nth fourth scan signal is converted to a low potential; the fourth thin film transistor and the sixth thin film transistor are both turned off; the second thin film transistor, the first thin film transistor, the third thin film transistor, and the fifth thin film transistor are both guided
  • Step S4 entering a data writing phase
  • Step S5 entering a capacitor serial connection phase
  • the n-1th first scan signal remains at a low potential
  • the nth first scan signal transitions to a low potential
  • the nth second scan signal remains at a low potential
  • the nth third scan signal transitions to a low potential
  • the nth fourth scan signal transitions to a high potential
  • the data signal transitions to a low potential
  • the second thin film transistor, the third thin film transistor, the fourth thin film transistor, and the fifth thin film transistor are both turned off, and the sixth thin film transistor is turned on
  • Step S6 entering a display illumination phase
  • the n-1th first scan signal remains at a low potential
  • the nth first scan signal remains at a low potential
  • the nth second scan signal transitions to a high potential
  • the nth third scan signal remains at a low potential
  • the n fourth scan signals are converted to a low potential
  • the data signal provides a low potential
  • the second thin film transistor, the fourth thin film transistor, the fifth thin film transistor, and the sixth thin film transistor are all turned off, the first thin film transistor, and the third thin film
  • the transistors are all turned on, the organic light emitting diode emits light, and the current flowing through the organic light emitting diode is independent of the threshold voltage of the driving thin film transistor.
  • the first thin film transistor, the second thin film transistor, the third thin film transistor, the fourth thin film transistor, the fifth thin film transistor, and the sixth thin film transistor are both low temperature polysilicon thin film transistors, oxide semiconductor thin film transistors, or amorphous silicon thin films Transistor.
  • the n-1th first scan signal, the nth first scan signal, the nth second scan signal, the nth third scan signal, the nth fourth scan signal, and the data signal are all externally Timing controller available.
  • the present invention also provides an OLED pixel driving circuit, including a first thin film transistor, a second thin film transistor, a third thin film transistor, a fourth thin film transistor, a fifth thin film transistor, a sixth thin film transistor, a first capacitor, a second capacitor, And organic light emitting diodes;
  • the gate of the first thin film transistor is electrically connected to the first node, the drain is connected to the positive voltage of the power source, and the source is electrically connected to the drain of the third thin film transistor;
  • the first thin film transistor is a driving thin film transistor;
  • n be a positive integer greater than 1, the gate of the second thin film transistor is connected to the nth third scan signal corresponding to the row of the OLED pixel driving circuit, the source is connected to the data signal, and the drain is electrically connected.
  • the gate of the third thin film transistor is connected to the nth second scan signal corresponding to the row of the OLED pixel driving circuit, the drain is electrically connected to the source of the first thin film transistor, and the source is electrically connected to the third node;
  • the gate of the fourth thin film transistor is connected to the n-1th first scan signal corresponding to the previous row of the row of the OLED pixel driving circuit, and the source is electrically connected to one end of the second node and the second capacitor, and the drain Electrically connecting the third node and the other end of the second capacitor;
  • the gate of the fifth thin film transistor is connected to the nth first scan signal corresponding to the row of the OLED pixel driving circuit, the source is electrically connected to the second node, and the drain is connected to the negative voltage of the power supply;
  • the gate of the sixth thin film transistor is connected to the nth fourth scan signal corresponding to the row of the OLED pixel driving circuit, the source is electrically connected to the third node, and the drain is connected to the negative voltage of the power supply;
  • One end of the first capacitor is electrically connected to the first node, and the other end is electrically connected to the second node;
  • One end of the second capacitor is electrically connected to the second node, and the other end is electrically connected to the third node;
  • the anode of the organic light emitting diode is electrically connected to the third node, and the cathode is connected to the negative voltage of the power source;
  • first thin film transistor, the second thin film transistor, the third thin film transistor, the fourth thin film transistor, the fifth thin film transistor, and the sixth thin film transistor are both low temperature polysilicon thin film transistors, oxide semiconductor thin film transistors, or amorphous Silicon thin film transistor;
  • the n-1th first scan signal, the nth first scan signal, the nth second scan signal, the nth third scan signal, the nth fourth scan signal, and the data signal are both Provided by an external timing controller;
  • the n-1th first scan signal, the nth first scan signal, the nth second scan signal, the nth third scan signal, the nth fourth scan signal, and the data signal phase Combining, corresponding to a reset phase, a threshold voltage storage phase, a data writing phase, a capacitor series phase, and a display lighting phase;
  • the n-1th first scan signal is high, nth The first scan signal of the strip is low, the nth second scan signal is low, the nth third scan signal is low, the nth fourth scan signal is high, and the data signal is low;
  • the n-1th first scan signal is low, the nth first scan signal is high, the nth second scan signal is high, the nth third The scan signal is high, the nth fourth scan signal is low, and the data signal is the first high potential;
  • the n-1th first scan signal is low, the nth first scan signal is high, the nth second scan signal is low, the nth third The scan signal is high, the nth fourth scan signal is low, and the data signal is second high potential higher than the first high potential;
  • the n-1th first scan signal is low, the nth first scan signal is low, the nth second scan signal is low, the nth third The scan signal is low, the nth fourth scan signal is high, and the data signal is low;
  • the n-1th first scan signal is low, the nth first scan signal is low, the nth second scan signal is high, and the nth third scan The signal is low, the nth fourth scan signal is low, and the data signal is low.
  • the present invention provides an OLED pixel driving circuit and a pixel driving method, which employs a driving circuit of a 6T2C structure, an n-1th first scanning signal, an nth first scanning signal, and an nth
  • the second scan signal, the nth third scan signal, the nth fourth scan signal, and the data signal are combined to sequentially correspond to a reset phase, a threshold voltage storage phase, a data write phase, and a capacitor cascade phase.
  • a display illumination phase which ultimately causes the current flowing through the organic light emitting diode to be independent of the threshold voltage of the driving thin film transistor, that is, can compensate the threshold voltage of the driving thin film transistor, and eliminate the influence of the threshold voltage of the driving thin film transistor on the light emitting diode, thereby enabling
  • the display brightness of the OLED panel is relatively uniform, and the display quality of the OLED panel is improved.
  • 1 is a circuit diagram of a conventional 2T1C pixel driving circuit for an OLED
  • FIG. 2 is a circuit diagram of an OLED pixel driving circuit of the present invention
  • FIG. 3 is a signal timing diagram of an OLED pixel driving circuit of the present invention.
  • step S2 of the OLED pixel driving method of the present invention is a schematic diagram of step S2 of the OLED pixel driving method of the present invention.
  • FIG. 5 is a schematic diagram of step S3 of the OLED pixel driving method of the present invention.
  • step S4 of the OLED pixel driving method of the present invention is a schematic diagram of step S4 of the OLED pixel driving method of the present invention.
  • FIG. 7 is a schematic diagram of step S5 of the OLED pixel driving method of the present invention.
  • FIG. 8 is a schematic diagram of step S6 of the OLED pixel driving method of the present invention.
  • the invention firstly provides an OLED pixel driving circuit applied in an OLED panel.
  • the OLED panel has a plurality of pixels arranged in an array, and each pixel is driven by an OLED pixel driving circuit.
  • the OLED pixel driving circuit of the present invention is a 6T2C structure, including: a first thin film transistor T1, a second thin film transistor T2, a third thin film transistor T3, a fourth thin film transistor T4, and a fifth thin film transistor.
  • T5 a sixth thin film transistor T6, a first capacitor C1, a second capacitor C2, and an organic light emitting diode D, wherein the first thin film transistor T1 is used as a driving thin film transistor.
  • the gate of the first thin film transistor T1 is electrically connected to the first node G, the drain is connected to the power supply positive voltage VDD, and the source is electrically connected to the drain of the third thin film transistor T3; the first thin film transistor T1 is a driving film.
  • n be a positive integer greater than 1, the gate of the second thin film transistor T2 is connected to the nth third scan signal Scan3(n) corresponding to the row of the OLED pixel driving circuit, and the source is connected to the data signal Data.
  • the drain is electrically connected to the first node G;
  • the gate of the third thin film transistor T3 is connected to the nth second scan signal Scan2(n) corresponding to the row of the OLED pixel driving circuit, and the drain is electrically connected to the source of the first thin film transistor T1, and the source is electrically Sexually connected to the third node B;
  • the gate of the fourth thin film transistor T4 is connected to the n-1th first scan signal Scan1(n-1) corresponding to the previous row of the row of the OLED pixel driving circuit, and the source is electrically connected to the second node A and One end of the second capacitor C2, the drain is electrically connected to the other end of the third node B and the second capacitor C2;
  • the gate of the fifth thin film transistor T5 is connected to the nth first scan signal Scan1(n) corresponding to the row of the OLED pixel driving circuit, the source is electrically connected to the second node A, and the drain is connected to the negative voltage of the power supply. VSS;
  • the gate of the sixth thin film transistor T6 is connected to the nth fourth scan signal Scan4(n) corresponding to the row of the OLED pixel driving circuit, the source is electrically connected to the third node B, and the drain is connected to the negative voltage of the power supply. VSS;
  • One end of the first capacitor C1 is electrically connected to the first node G, and the other end is electrically connected to the second node.
  • One end of the second capacitor C2 is electrically connected to the second node A, and the other end is electrically connected to the third node B;
  • the anode of the organic light emitting diode D is electrically connected to the third node B, and the cathode is connected to the power supply negative voltage VSS.
  • the first thin film transistor T1, the second thin film transistor T2, the third thin film transistor T3, the fourth thin film transistor T4, the fifth thin film transistor T5, and the sixth thin film transistor T6 are both low temperature polysilicon thin film transistors and oxides.
  • the nth fourth scan signal Scan4(n) and the data signal Data are both supplied by an external timing controller. As shown in FIG.
  • the third scan signal Scan3(n) and the nth fourth scan signal Scan4(n) are combined with the data signal Data, and sequentially correspond to a reset phase t1, a threshold voltage storage phase t2, and a data writing phase t3. a capacitor series phase t4 and a display lighting phase t5.
  • the n-1th first scan signal Scan1(n-1) is at a high potential, and the nth first scan signal Scan1(n) is Low potential, the nth second scan signal Scan2(n) is low, the nth third scan signal Scan3(n) is low, and the nth fourth scan signal Scan4(n) is high, data signal Data is low;
  • the second thin film transistor T2, the third thin film transistor T3, and the fifth thin film transistor T5 are both turned off;
  • the fourth thin film transistor T4 is turned on to short the two ends of the second capacitor C2, so that the second capacitor C2
  • a reset of the organic light-emitting diode D is achieved. Since the n-1th first scan signal Scan1(n-1) is generated before the nth first scan signal Scan1(n), the nth fourth scan signal Scan4(n) and the n-1th The first scan signal Scan1(n-1) is synchronized during the reset phase t1, so the reset operation of the second capacitor C2 and the organic light-emitting diode D before the nth first scan signal Scan1(n) arrives Already done.
  • the n-1th first scan signal Scan1(n-1) is low, and the nth first scan signal Scan1(n) ) is high, the nth second scan signal Scan2(n) is high, the nth third scan signal Scan3(n) is high, and the nth fourth scan signal Scan4(n) is low.
  • the data signal Data is the first high potential V1 D ; the fourth thin film transistor T4 and the sixth thin film transistor T6 are both turned off; the second thin film transistor T2, the first thin film transistor T1, the third thin film transistor T3, and the fifth thin film transistor T5 is both turned on, the first high potential V1 D of the data signal Data reaches the first node G, and the second capacitor C2 is charged through the first thin film transistor T1 and the third thin film transistor T3 until both ends of the second capacitor C2
  • V BA V1 D - V th , where V th represents the threshold voltage of the first thin film transistor T1, that is, the driving thin film transistor.
  • the n-1th first scan signal Scan1(n-1) is low, and the nth first scan signal Scan1(n) ) is high, the nth second scan signal Scan2(n) is low, the nth third scan signal Scan3(n) is high, and the nth fourth scan signal Scan4(n) is low.
  • the n-1th first scan signal Scan1(n-1) is low, and the nth first scan signal Scan1(n) ) is low, the nth second scan signal Scan2(n) is low, the nth third scan signal Scan3(n) is low, and the nth fourth scan signal Scan4(n) is high.
  • the data signal Data is low; the second thin film transistor T2, the third thin film transistor T3, the fourth thin film transistor T4, and the fifth thin film transistor T5 are both turned off, the sixth thin film transistor T6 is turned on, and the first capacitor C1 and the second The capacitor C2 is connected in series such that the voltage difference V GB between the first node G and the third node B is:
  • the organic light emitting diode D does not emit light.
  • the n-1th first scan signal Scan1(n-1) is low, and the nth first scan signal Scan1(n)
  • the nth second scan signal Scan2(n) is high, the nth third scan signal Scan3(n) is low, and the nth fourth scan signal Scan4(n) is low
  • data The signal of the second thin film transistor T2, the fourth thin film transistor T4, the fifth thin film transistor T5, and the sixth thin film transistor T6 are turned off, and the first thin film transistor T1 and the third thin film transistor T3 are both turned on;
  • the voltage difference V GB of the first node G and the third node B that is, the voltage Vgs between the gate and the source of the first thin film transistor T1 is maintained as:
  • Organic light emitting diode D emits light
  • K is the intrinsic conduction factor of the driving thin film transistor, that is, the first thin film transistor T1. It can be seen that the current flowing through the organic light emitting diode D is independent of the threshold voltage Vth of the first thin film transistor T1, that is, the driving thin film transistor, eliminating the influence of the threshold voltage Vth of the driving thin film transistor on the light emitting diode D, thereby enabling the OLED panel to The display brightness is relatively uniform, which improves the display quality of the OLED panel.
  • the present invention further provides an OLED pixel driving method, including the following steps:
  • Step S1 providing an OLED pixel driving circuit using the 6T2C structure as shown in FIG. 2, where the OLED pixel driving circuit structure is not repeatedly described herein.
  • the first thin film transistor T1, the second thin film transistor T2, the third thin film transistor T3, the fourth thin film transistor T4, the fifth thin film transistor T5, and the sixth thin film transistor T6 are both low temperature polysilicon thin film transistors and oxides.
  • the nth fourth scan signal Scan4(n) and the data signal Data are both supplied by an external timing controller.
  • Step S2 please refer to FIG. 4, and in conjunction with FIG. 3, enter the reset phase t1.
  • the n-1th first scan signal Scan1(n-1) provides a high potential
  • the nth first scan signal Scan1(n) provides a low potential
  • the nth second scan signal Scan2(n) provides a low potential
  • the nth third scan signal Scan3(n) provides a low potential
  • the nth fourth scan signal Scan4(n) provides a high potential
  • the data signal Data provides a low potential.
  • the second thin film transistor T2, the third thin film transistor T3, and the fifth thin film transistor T5 are both turned off; the fourth thin film transistor T4 is turned on to short the two ends of the second capacitor C2, so that the voltage difference between the second capacitor C2 is 0, the reset of the second capacitor C2 is realized; the sixth thin film transistor T6 is turned on to short the anode and the cathode of the organic light emitting diode D, so that the voltage difference between the anode and the cathode of the organic light emitting diode D is 0, realizing the organic light emitting Reset of stage D.
  • Step S3 please refer to FIG. 5, in conjunction with FIG. 3, enter the threshold voltage storage phase t2.
  • the n-1th first scan signal Scan1(n-1) transitions to a low potential
  • the nth first scan signal Scan1(n) transitions to a high potential
  • the nth second scan signal Scan2(n) transitions
  • the nth third scan signal Scan3(n) transitions to a high potential
  • the nth fourth scan signal Scan4(n) transitions to a low potential.
  • the fourth thin film transistor T4 and the sixth thin film transistor T6 are both turned off; the second thin film transistor T2, the first thin film transistor T1, the third thin film transistor T3, and the fifth thin film transistor T5 are both turned on, and the data signal Data is first.
  • the node G provides the first high potential V1 D while charging the second capacitor C2 via the first thin film transistor T1 and the third thin film transistor T3 until the voltages of the third node B and the second node A are both ends of the second capacitor C2.
  • Step S4 please refer to FIG. 6, in conjunction with FIG. 3, enter data writing phase t3.
  • the n-1th first scan signal Scan1(n-1) is kept at a low potential
  • the nth first scan signal Scan1(n) is kept at a high potential
  • the nth second scan signal Scan2(n) is turned low
  • the nth third scan signal Scan3(n) remains at a high potential
  • the nth fourth scan signal Scan4(n) remains at a low potential.
  • the third thin film transistor T3, the fourth thin film transistor T4, and the sixth thin film transistor T6 are both turned off; the second thin film transistor T2, the first thin film transistor T1, and the fifth thin film transistor T5 are both turned on, and the data signal Data is first.
  • the node G provides a second high potential V2 D higher than the first high potential V1 D while charging the first capacitor C1 such that the voltage difference V GA between the first node G and the second node A is:
  • V GA V2 D .
  • Step S5 please refer to FIG. 7, and in conjunction with FIG. 3, enter the capacitor series connection stage t4.
  • the n-1th first scan signal Scan1(n-1) remains low, the nth first scan signal Scan1(n) transitions to a low potential, and the nth second scan signal Scan2(n) remains low At the potential, the nth third scan signal Scan3(n) transitions to a low potential, the nth fourth scan signal Scan4(n) transitions to a high potential, and the data signal Data transitions to a low potential.
  • the second thin film transistor T2, the third thin film transistor T3, the fourth thin film transistor T4, and the fifth thin film transistor T5 are both turned off, the sixth thin film transistor T6 is turned on, and the first capacitor C1 and the second capacitor C2 are connected in series, so that the first The voltage difference V GB between a node G and a third node B is:
  • the organic light emitting diode D does not emit light.
  • Step S6 please refer to FIG. 8, and in conjunction with FIG. 3, enter the display illumination phase t5.
  • the n-1th first scan signal Scan1(n-1) is kept low, the nth first scan signal Scan1(n) is kept low, and the nth second scan signal Scan2(n) is turned high Potential, the nth third scan signal Scan3(n) remains low, the nth fourth scan signal Scan4 (n) transitions to a low potential, and the data signal Data provides a low potential.
  • the second thin film transistor T2, the fourth thin film transistor T4, the fifth thin film transistor T5, and the sixth thin film transistor T6 are both turned off, and the first thin film transistor T1 and the third thin film transistor T3 are both turned on; in the first capacitor C1 and Under the storage of the second capacitor C2, the voltage difference V GB between the first node G and the third node B, that is, the voltage Vgs between the gate and the source of the first thin film transistor T1 is maintained as:
  • Organic light emitting diode D emits light
  • K is the intrinsic conduction factor of the driving thin film transistor, that is, the first thin film transistor T1. It can be seen that the current flowing through the organic light emitting diode D is independent of the threshold voltage Vth of the first thin film transistor T1, that is, the driving thin film transistor, eliminating the influence of the threshold voltage Vth of the driving thin film transistor on the light emitting diode D, thereby enabling the OLED panel to The display brightness is relatively uniform, which improves the display quality of the OLED panel.
  • the OLED pixel driving circuit and the pixel driving method of the present invention adopt a 6T2C structure driving circuit, the n-1th first scanning signal, the nth first scanning signal, the nth second scanning signal, The nth third scan signal, the nth fourth scan signal, and the data signal are combined, and corresponding to a reset phase, a threshold voltage storage phase, a data writing phase, a capacitor serial phase, and a display
  • the current flowing through the organic light emitting diode is finally independent of the threshold voltage of the driving thin film transistor, that is, the threshold voltage of the driving thin film transistor can be compensated, and the influence of the threshold voltage of the driving thin film transistor on the light emitting diode is eliminated, thereby enabling the OLED panel to
  • the display brightness is relatively uniform, which improves the display quality of the OLED panel.

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Abstract

一种OLED像素驱动电路及像素驱动方法。OLED像素驱动电路采用6T2C结构，包括：第一至第六薄膜晶体管（T1、T2、T3、T4、T5、T6）、第一电容（C1）、第二电容（C2）及有机发光二极管（D），第n-1条第一扫描信号（Scan1(n-1)）、第n条第一扫描信号（Scan1(n)）、第n条第二扫描信号（Scan2(n)）、第n条第三扫描信号（Scan3(n)）、第n条第四扫描信号（Scan4(n)）与数据信号（Data）相组合，先后对应于一复位阶段（t1）、一阈值电压存储阶段（t2）、一数据写入阶段（t3）、一电容串接阶段（t4）以及一显示发光阶段（t5），使得流过有机发光二极管（D）的电流（IOLED）与驱动薄膜晶体管（T1）的阈值电压（Vth）无关。

Description

OLED像素驱动电路及像素驱动方法 技术领域
本发明涉及OLED驱动技术领域，尤其涉及一种OLED像素驱动电路及像素驱动方法。
背景技术
有机发光二极管(Organic Light Emitting Display，OLED)显示面板，简称OLED面板，具有自发光、驱动电压低、发光效率高、响应时间短、清晰度与对比度高、近180°视角、使用温度范围宽，可实现柔性显示与大面积全色显示等诸多优点，被业界公认为是最有发展潜力的显示装置。
OLED面板内具有呈阵列式排布的多个像素，每一像素通过一OLED像素驱动电路来进行驱动。OLED是电流驱动器件，当有电流流经有机发光二极管时，有机发光二极管发光，且发光亮度由流经有机发光二极管自身的电流决定。大部分已有的集成电路(Integrated Circuit，IC)都只传输电压信号，故OLED的像素驱动电路需要完成将电压信号转变为电流信号的任务。传统的OLED像素驱动电路通常为2T1C，即两个薄膜晶体管加一个电容的结构，将电压变换为电流。
如图1所示，传统的用于OLED的2T1C像素驱动电路包括：第一薄膜晶体管T10、第二薄膜晶体管T20、及电容C10，所述第一薄膜晶体管T10为开关薄膜晶体管，所述第二薄膜晶体管T20为驱动薄膜晶体管，所述电容C10为存储电容。具体地，第一薄膜晶体管T10的栅极接入该像素驱动电路所在行对应的扫描信号Scan(n)，源极接入数据信号Data，漏极与第二薄膜晶体管T20的栅极、及电容C10的一端电性连接；所述第二薄膜晶体管T20的漏极电性连接电源正电压VDD，源极电性连接有机发光二级管D10的阳极；有机发光二级管D10的阴极电性连接电源负电压VSS；电容C10的一端电性连接第一薄膜晶体管T10的漏极，另一端电性连接第二薄膜晶体管T20的源极。OLED显示时，扫描信号Scan(n)控制第一薄膜晶体管T10导通，数据信号Data经过第一薄膜晶体管T10进入到第二薄膜晶体管T20的栅极及电容C10，然后第一薄膜晶体管T10关断，由于电容C10的存储作用，第二薄膜晶体管T20的栅极电压仍可继续保持数据信号电压，使得第二薄膜晶体管T20处于导通状态，驱动电流通过第二薄膜晶体管T20进入有机发光二级管D10，驱动有机发光二级管D10发光。
已知的计算流经有机发光二极管的电流IOLED的公式为：
IOLED＝K×(Vgs－Vth)2
其中，K为驱动薄膜晶体管的本征导电因子，Vgs表示驱动薄膜晶体管的栅极与源极之间的电压，Vth表示驱动薄膜晶体管的阈值电压。
可见流经有机发光二极管的电流IOLED与驱动薄膜晶体管的阈值电压Vth有关。
由于OLED面板制程技术不稳定的原因，面板内每个像素的驱动薄膜晶体管的阈值电压Vth会有差别，加上长时间工作会使薄膜晶体管的材料老化，导致驱动薄膜晶体管的阈值电压Vth发生漂移，对发光二极管的发光亮度造成影响，而上述传统的2T1C结构的像素驱动电路不具有补偿驱动薄膜晶体管的阈值电压Vth的功能，从而会产生OLED面板显示亮度不均匀的现象。
发明内容
本发明的目的在于提供一种OLED像素驱动电路，能够补偿驱动薄膜晶体管的阈值电压，消除驱动薄膜晶体管的阈值电压对发光二极管的影响，使OLED面板的显示亮度较均匀，提升OLED面板的显示品质。
本发明的另一目的在于提供一种OLED像素驱动方法，能够对驱动薄膜晶体管的阈值电压进行补偿，消除驱动薄膜晶体管的阈值电压对发光二极管的影响，使OLED面板的显示亮度较均匀，提升OLED面板的显示品质。
为实现上述目的，本发明首先提供一种OLED像素驱动电路，包括第一薄膜晶体管、第二薄膜晶体管、第三薄膜晶体管、第四薄膜晶体管、第五薄膜晶体管、第六薄膜晶体管、第一电容、第二电容、及有机发光二极管；
所述第一薄膜晶体管的栅极电性连第一节点，漏极接入电源正电压，源极电性连接第三薄膜晶体管的漏极；该第一薄膜晶体管为驱动薄膜晶体管；
设n为大于1的正整数，所述第二薄膜晶体管的栅极接入该OLED像素驱动电路所在行对应的第n条第三扫描信号，源极接入数据信号，漏极电性连第一节点；
所述第三薄膜晶体管的栅极接入该OLED像素驱动电路所在行对应的第n条第二扫描信号，漏极电性连接第一薄膜晶体管的源极，源极电性连第三节点；
所述第四薄膜晶体管的栅极接入该OLED像素驱动电路所在行的上一行对应的第n-1条第一扫描信号，源极电性连接第二节点与第二电容的一端，漏极电性连接第三节点与第二电容的另一端；
所述第五薄膜晶体管的栅极接入该OLED像素驱动电路所在行对应的第n条第一扫描信号，源极电性连接第二节点，漏极接入电源负电压；
所述第六薄膜晶体管的栅极接入该OLED像素驱动电路所在行对应的第n条第四扫描信号，源极电性连接第三节点，漏极接入电源负电压；
所述第一电容的一端电性连接第一节点，另一端电性连接第二节点；
所述第二电容的一端电性连接第二节点，另一端电性连接第三节点；
所述有机发光二极管的阳极电性连接第三节点，阴极接入电源负电压。
所述第一薄膜晶体管、第二薄膜晶体管、第三薄膜晶体管、第四薄膜晶体管、第五薄膜晶体管、与第六薄膜晶体管均为低温多晶硅薄膜晶体管、氧化物半导体薄膜晶体管、或非晶硅薄膜晶体管。
所述第n-1条第一扫描信号、第n条第一扫描信号、第n条第二扫描信号、第n条第三扫描信号、第n条第四扫描信号、与数据信号均通过外部时序控制器提供。
所述第n-1条第一扫描信号、第n条第一扫描信号、第n条第二扫描信号、第n条第三扫描信号、第n条第四扫描信号、与数据信号相组合，先后对应于一复位阶段、一阈值电压存储阶段、一数据写入阶段、一电容串接阶段、以及一显示发光阶段。
在所述复位阶段，所述第n-1条第一扫描信号为高电位，第n条第一扫描信号为低电位，第n条第二扫描信号为低电位，第n条第三扫描信号为低电位，第n条第四扫描信号为高电位，数据信号为低电位；
在所述阈值电压存储阶段，所述第n-1条第一扫描信号为低电位，第n条第一扫描信号为高电位，第n条第二扫描信号为高电位，第n条第三扫描信号为高电位，第n条第四扫描信号为低电位，数据信号为第一高电位；
在所述数据写入阶段，所述第n-1条第一扫描信号为低电位，第n条第一扫描信号为高电位，第n条第二扫描信号为低电位，第n条第三扫描信号为高电位，第n条第四扫描信号为低电位，数据信号为高于第一高电位的第二高电位；
在所述电容串接阶段，所述第n-1条第一扫描信号为低电位，第n条第一扫描信号为低电位，第n条第二扫描信号为低电位，第n条第三扫描信号为低电位，第n条第四扫描信号为高电位，数据信号为低电位；
在所述显示发光阶段，所述第n-1条第一扫描信号为低电位，第n条第 一扫描信号为低电位，第n条第二扫描信号为高电位，第n条第三扫描信号为低电位，第n条第四扫描信号为低电位，数据信号为低电位。
本发明还提供一种OLED像素驱动方法，包括如下步骤：
步骤S1、提供OLED像素驱动电路；
所述OLED像素驱动电路包括第一薄膜晶体管、第二薄膜晶体管、第三薄膜晶体管、第四薄膜晶体管、第五薄膜晶体管、第六薄膜晶体管、第一电容、第二电容、及有机发光二极管；
所述第一薄膜晶体管的栅极电性连第一节点，漏极接入电源正电压，源极电性连接第三薄膜晶体管的漏极；该第一薄膜晶体管为驱动薄膜晶体管；
设n为大于1的正整数，所述第二薄膜晶体管的栅极接入该OLED像素驱动电路所在行对应的第n条第三扫描信号，源极接入数据信号，漏极电性连第一节点；
所述第三薄膜晶体管的栅极接入该OLED像素驱动电路所在行对应的第n条第二扫描信号，漏极电性连接第一薄膜晶体管的源极，源极电性连第三节点；
所述第四薄膜晶体管的栅极接入该OLED像素驱动电路所在行的上一行对应的第n-1条第一扫描信号，源极电性连接第二节点与第二电容的一端，漏极电性连接第三节点与第二电容的另一端；
所述第五薄膜晶体管的栅极接入该OLED像素驱动电路所在行对应的第n条第一扫描信号，源极电性连接第二节点，漏极接入电源负电压；
所述第六薄膜晶体管的栅极接入该OLED像素驱动电路所在行对应的第n条第四扫描信号，源极电性连接第三节点，漏极接入电源负电压；
所述第一电容的一端电性连接第一节点，另一端电性连接第二节点；
所述第二电容的一端电性连接第二节点，另一端电性连接第三节点；
所述有机发光二极管的阳极电性连接第三节点，阴极接入电源负电压；
步骤S2、进入复位阶段；
所述第n-1条第一扫描信号提供高电位，第n条第一扫描信号提供低电位，第n条第二扫描信号提供低电位，第n条第三扫描信号提供低电位，第n条第四扫描信号提供高电位，数据信号提供低电位；第二薄膜晶体管、第三薄膜晶体管、与第五薄膜晶体管均关断；第四薄膜晶体管导通对第二电容进行复位；第六薄膜晶体管导通对有机发光二级管进行复位；
步骤S3、进入阈值电压存储阶段；
所述第n-1条第一扫描信号转变为低电位，第n条第一扫描信号转变为 高电位，第n条第二扫描信号转变为高电位，第n条第三扫描信号转变为高电位，第n条第四扫描信号转变为低电位；第四薄膜晶体管、与第六薄膜晶体管均关断；第二薄膜晶体管、第一薄膜晶体管、第三薄膜晶体管、与第五薄膜晶体管均导通，数据信号向第一节点提供第一高电位，同时对第二电容充电，直至第三节点与第二节点的电压差VBA达到：VBA＝V1D-Vth，其中V1D表示数据信号提供的第一高电位，Vth表示第一薄膜晶体管的阈值电压；
步骤S4、进入数据写入阶段；
所述第n-1条第一扫描信号保持低电位，第n条第一扫描信号保持高电位，第n条第二扫描信号转变为低电位，第n条第三扫描信号保持高电位，第n条第四扫描信号保持低电位；第三薄膜晶体管、第四薄膜晶体管、与第六薄膜晶体管均关断；第二薄膜晶体管、第一薄膜晶体管、与第五薄膜晶体管均导通，数据信号向第一节点提供高于第一高电位的第二高电位，同时对第一电容充电，使得第一节点与第二节点之间的电压差VGA为：VGA＝V2D，其中V2D表示数据信号提供的第二高电位；
步骤S5、进入电容串接阶段；
所述第n-1条第一扫描信号保持低电位，第n条第一扫描信号转变为低电位，第n条第二扫描信号保持低电位，第n条第三扫描信号转变为低电位，第n条第四扫描信号转变为高电位，数据信号转变为低电位；第二薄膜晶体管、第三薄膜晶体管、第四薄膜晶体管、与第五薄膜晶体管均关断，第六薄膜晶体管导通，第一电容与第二电容串接，使得第一节点与第三节点的电压差VGB为：VGB＝V2D-V1D+Vth；
步骤S6、进入显示发光阶段；
所述第n-1条第一扫描信号保持低电位，第n条第一扫描信号保持低电位，第n条第二扫描信号转变为高电位，第n条第三扫描信号保持低电位，第n条第四扫描信号转变为低电位，数据信号提供低电位；第二薄膜晶体管、第四薄膜晶体管、第五薄膜晶体管、与第六薄膜晶体管均关断，第一薄膜晶体管、与第三薄膜晶体管均导通，有机发光二极管发光，且流过有机发光二极管的电流与驱动薄膜晶体管的阈值电压无关。
所述第一薄膜晶体管、第二薄膜晶体管、第三薄膜晶体管、第四薄膜晶体管、第五薄膜晶体管、与第六薄膜晶体管均为低温多晶硅薄膜晶体管、氧化物半导体薄膜晶体管、或非晶硅薄膜晶体管。
所述第n-1条第一扫描信号、第n条第一扫描信号、第n条第二扫描信号、第n条第三扫描信号、第n条第四扫描信号、与数据信号均通过外部 时序控制器提供。
本发明还提供一种OLED像素驱动电路，包括第一薄膜晶体管、第二薄膜晶体管、第三薄膜晶体管、第四薄膜晶体管、第五薄膜晶体管、第六薄膜晶体管、第一电容、第二电容、及有机发光二极管；
所述第一薄膜晶体管的栅极电性连第一节点，漏极接入电源正电压，源极电性连接第三薄膜晶体管的漏极；该第一薄膜晶体管为驱动薄膜晶体管；
设n为大于1的正整数，所述第二薄膜晶体管的栅极接入该OLED像素驱动电路所在行对应的第n条第三扫描信号，源极接入数据信号，漏极电性连第一节点；
所述第三薄膜晶体管的栅极接入该OLED像素驱动电路所在行对应的第n条第二扫描信号，漏极电性连接第一薄膜晶体管的源极，源极电性连第三节点；
所述第四薄膜晶体管的栅极接入该OLED像素驱动电路所在行的上一行对应的第n-1条第一扫描信号，源极电性连接第二节点与第二电容的一端，漏极电性连接第三节点与第二电容的另一端；
所述第五薄膜晶体管的栅极接入该OLED像素驱动电路所在行对应的第n条第一扫描信号，源极电性连接第二节点，漏极接入电源负电压；
所述第六薄膜晶体管的栅极接入该OLED像素驱动电路所在行对应的第n条第四扫描信号，源极电性连接第三节点，漏极接入电源负电压；
所述第一电容的一端电性连接第一节点，另一端电性连接第二节点；
所述第二电容的一端电性连接第二节点，另一端电性连接第三节点；
所述有机发光二极管的阳极电性连接第三节点，阴极接入电源负电压；
其中，所述第一薄膜晶体管、第二薄膜晶体管、第三薄膜晶体管、第四薄膜晶体管、第五薄膜晶体管、与第六薄膜晶体管均为低温多晶硅薄膜晶体管、氧化物半导体薄膜晶体管、或非晶硅薄膜晶体管；
其中，所述第n-1条第一扫描信号、第n条第一扫描信号、第n条第二扫描信号、第n条第三扫描信号、第n条第四扫描信号、与数据信号均通过外部时序控制器提供；
其中，所述第n-1条第一扫描信号、第n条第一扫描信号、第n条第二扫描信号、第n条第三扫描信号、第n条第四扫描信号、与数据信号相组合，先后对应于一复位阶段、一阈值电压存储阶段、一数据写入阶段、一电容串接阶段、以及一显示发光阶段；
其中，在所述复位阶段，所述第n-1条第一扫描信号为高电位，第n 条第一扫描信号为低电位，第n条第二扫描信号为低电位，第n条第三扫描信号为低电位，第n条第四扫描信号为高电位，数据信号为低电位；
在所述阈值电压存储阶段，所述第n-1条第一扫描信号为低电位，第n条第一扫描信号为高电位，第n条第二扫描信号为高电位，第n条第三扫描信号为高电位，第n条第四扫描信号为低电位，数据信号为第一高电位；
在所述数据写入阶段，所述第n-1条第一扫描信号为低电位，第n条第一扫描信号为高电位，第n条第二扫描信号为低电位，第n条第三扫描信号为高电位，第n条第四扫描信号为低电位，数据信号为高于第一高电位的第二高电位；
在所述电容串接阶段，所述第n-1条第一扫描信号为低电位，第n条第一扫描信号为低电位，第n条第二扫描信号为低电位，第n条第三扫描信号为低电位，第n条第四扫描信号为高电位，数据信号为低电位；
在所述显示发光阶段，所述第n-1条第一扫描信号为低电位，第n条第一扫描信号为低电位，第n条第二扫描信号为高电位，第n条第三扫描信号为低电位，第n条第四扫描信号为低电位，数据信号为低电位。
本发明的有益效果：本发明提供的一种OLED像素驱动电路及像素驱动方法，采用6T2C结构的驱动电路，第n-1条第一扫描信号、第n条第一扫描信号、第n条第二扫描信号、第n条第三扫描信号、第n条第四扫描信号、与数据信号相组合，先后对应于一复位阶段、一阈值电压存储阶段、一数据写入阶段、一电容串接阶段、以及一显示发光阶段，最终使得流过有机发光二极管的电流与驱动薄膜晶体管的阈值电压无关，即能够补偿驱动薄膜晶体管的阈值电压，消除驱动薄膜晶体管的阈值电压对发光二极管的影响，从而能够使OLED面板的显示亮度较均匀，提升OLED面板的显示品质。
附图说明
为了能更进一步了解本发明的特征以及技术内容，请参阅以下有关本发明的详细说明与附图，然而附图仅提供参考与说明用，并非用来对本发明加以限制。
附图中，
图1为传统的用于OLED的2T1C像素驱动电路的电路图；
图2为本发明的OLED像素驱动电路的电路图；
图3为本发明的OLED像素驱动电路的信号时序图；
图4为本发明的OLED像素驱动方法的步骤S2的示意图；
图5为本发明的OLED像素驱动方法的步骤S3的示意图；
图6为本发明的OLED像素驱动方法的步骤S4的示意图；
图7为本发明的OLED像素驱动方法的步骤S5的示意图；
图8为本发明的OLED像素驱动方法的步骤S6的示意图。
具体实施方式
为更进一步阐述本发明所采取的技术手段及其效果，以下结合本发明的优选实施例及其附图进行详细描述。
本发明首先提供一种应用于OLED面板内的OLED像素驱动电路，OLED面板内具有呈阵列式排布的多个像素，每一像素通过一OLED像素驱动电路来进行驱动。请同时参阅图2与图3，本发明的OLED像素驱动电路为6T2C结构，包括：第一薄膜晶体管T1、第二薄膜晶体管T2、第三薄膜晶体管T3、第四薄膜晶体管T4、第五薄膜晶体管T5、第六薄膜晶体管T6、第一电容C1、第二电容C2、及有机发光二极管D，其中所述第一薄膜晶体管T1作驱动薄膜晶体管之用。
所述第一薄膜晶体管T1的栅极电性连第一节点G，漏极接入电源正电压VDD，源极电性连接第三薄膜晶体管T3的漏极；该第一薄膜晶体管T1为驱动薄膜晶体管；
设n为大于1的正整数，所述第二薄膜晶体管T2的栅极接入该OLED像素驱动电路所在行对应的第n条第三扫描信号Scan3(n)，源极接入数据信号Data，漏极电性连第一节点G；
所述第三薄膜晶体管T3的栅极接入该OLED像素驱动电路所在行对应的第n条第二扫描信号Scan2(n)，漏极电性连接第一薄膜晶体管T1的源极，源极电性连第三节点B；
所述第四薄膜晶体管T4的栅极接入该OLED像素驱动电路所在行的上一行对应的第n-1条第一扫描信号Scan1(n-1)，源极电性连接第二节点A与第二电容C2的一端，漏极电性连接第三节点B与第二电容C2的另一端；
所述第五薄膜晶体管T5的栅极接入该OLED像素驱动电路所在行对应的第n条第一扫描信号Scan1(n)，源极电性连接第二节点A，漏极接入电源负电压VSS；
所述第六薄膜晶体管T6的栅极接入该OLED像素驱动电路所在行对应的第n条第四扫描信号Scan4(n)，源极电性连接第三节点B，漏极接入电源负电压VSS；
所述第一电容C1的一端电性连接第一节点G，另一端电性连接第二节 点A；
所述第二电容C2的一端电性连接第二节点A，另一端电性连接第三节点B；
所述有机发光二极管D的阳极电性连接第三节点B，阴极接入电源负电压VSS。
具体地，所述第一薄膜晶体管T1、第二薄膜晶体管T2、第三薄膜晶体管T3、第四薄膜晶体管T4、第五薄膜晶体管T5、与第六薄膜晶体管T6均为低温多晶硅薄膜晶体管、氧化物半导体薄膜晶体管、或非晶硅薄膜晶体管。
所述第n-1条第一扫描信号Scan1(n-1)、第n条第一扫描信号Scan1(n)、第n条第二扫描信号Scan2(n)、第n条第三扫描信号Scan3(n)、第n条第四扫描信号Scan4(n)、与数据信号Data均通过外部时序控制器提供。如图3所示，所述第n-1条第一扫描信号Scan1(n-1)、第n条第一扫描信号Scan1(n)、第n条第二扫描信号Scan2(n)、第n条第三扫描信号Scan3(n)、第n条第四扫描信号Scan4(n)、与数据信号Data相组合，先后对应于一复位阶段t1、一阈值电压存储阶段t2、一数据写入阶段t3、一电容串接阶段t4、以及一显示发光阶段t5。
结合图2与图3，并参考图4，在复位阶段t1，所述第n-1条第一扫描信号Scan1(n-1)为高电位，第n条第一扫描信号Scan1(n)为低电位，第n条第二扫描信号Scan2(n)为低电位，第n条第三扫描信号Scan3(n)为低电位，第n条第四扫描信号Scan4(n)为高电位，数据信号Data为低电位；第二薄膜晶体管T2、第三薄膜晶体管T3、与第五薄膜晶体管T5均关断；第四薄膜晶体管T4导通使得第二电容C2的两端短接，从而第二电容C2两端的电压差为0，实现对第二电容C2的复位；第六薄膜晶体管T6导通使得有机发光二极管D的阳极与阴极短接，从而有机发光二极管D的阳极与阴极的电压差为0，实现对有机发光二级管D的复位。由于所述第n-1条第一扫描信号Scan1(n-1)先于第n条第一扫描信号Scan1(n)产生，第n条第四扫描信号Scan4(n)与第n-1条第一扫描信号Scan1(n-1)在该复位阶段t1内是同步的，所以在第n条第一扫描信号Scan1(n)到达之前，第二电容C2与有机发光二级管D的复位动作已经完成了。
结合图2与图3，并参考图5，在阈值电压存储阶段t2，所述第n-1条第一扫描信号Scan1(n-1)为低电位，第n条第一扫描信号Scan1(n)为高电位，第n条第二扫描信号Scan2(n)为高电位，第n条第三扫描信号Scan3(n)为高电位，第n条第四扫描信号Scan4(n)为低电位，数据信 号Data为第一高电位V1D；第四薄膜晶体管T4、与第六薄膜晶体管T6均关断；第二薄膜晶体管T2、第一薄膜晶体管T1、第三薄膜晶体管T3、与第五薄膜晶体管T5均导通，数据信号Data的第一高电位V1D到达第一节点G，同时经第一薄膜晶体管T1与第三薄膜晶体管T3对第二电容C2充电，直至第二电容C2的两端即第三节点B与第二节点A的电压差VBA达到：VBA＝V1D-Vth，其中Vth表示第一薄膜晶体管T1即驱动薄膜晶体管的阈值电压。
结合图2与图3，并参考图6，在数据写入阶段t3，所述第n-1条第一扫描信号Scan1(n-1)为低电位，第n条第一扫描信号Scan1(n)为高电位，第n条第二扫描信号Scan2(n)为低电位，第n条第三扫描信号Scan3(n)为高电位，第n条第四扫描信号Scan4(n)为低电位，数据信号Data为高于第一高电位V1D的第二高电位V2D；第三薄膜晶体管T3、第四薄膜晶体管T4、与第六薄膜晶体管T6均关断；第二薄膜晶体管T2、第一薄膜晶体管T1、与第五薄膜晶体管T5均导通，数据信号Data的第二高电位V2D到达第一节点G，同时对第一电容C1充电，使得第一节点G与第二节点A之间的电压差VGA为：VGA＝V2D。
结合图2与图3，并参考图7，在电容串接阶段t4，所述第n-1条第一扫描信号Scan1(n-1)为低电位，第n条第一扫描信号Scan1(n)为低电位，第n条第二扫描信号Scan2(n)为低电位，第n条第三扫描信号Scan3(n)为低电位，第n条第四扫描信号Scan4(n)为高电位，数据信号Data为低电位；第二薄膜晶体管T2、第三薄膜晶体管T3、第四薄膜晶体管T4、与第五薄膜晶体管T5均关断，第六薄膜晶体管T6导通，第一电容C1与第二电容C2串接，使得第一节点G与第三节点B的电压差VGB为：
VGB＝V2D-(V1D-Vth)＝V2D-V1D+Vth；
在该电容串接阶段t4，由于第六薄膜晶体管T6短接了有机发光二极管D的阳极与阴极，所以有机发光二极管D不会发光。
结合图2与图3，并参考图8，在显示发光阶段t5，所述第n-1条第一扫描信号Scan1(n-1)为低电位，第n条第一扫描信号Scan1(n)为低电位，第n条第二扫描信号Scan2(n)为高电位，第n条第三扫描信号Scan3(n)为低电位，第n条第四扫描信号Scan4(n)为低电位，数据信号Data为低电位；第二薄膜晶体管T2、第四薄膜晶体管T4、第五薄膜晶体管T5、与第六薄膜晶体管T6均关断，第一薄膜晶体管T1、与第三薄膜晶体管T3均导通；在第一电容C1与第二电容C2的存储作用下，第一节点G与第三节点B的电压差VGB也即第一薄膜晶体管T1的栅极与源极之间的电压Vgs 保持为：
VGB＝Vgs＝V2D-V1D+Vth；
有机发光二极管D发光；
根据计算流经有机发光二极管D的电流IOLED的公式：
IOLED＝K×(Vgs-Vth)2＝K×(V2D-V1D+Vth-Vth)2＝K×(V2D-V1D)2
其中，K为驱动薄膜晶体管即第一薄膜晶体管T1的本征导电因子。可见，流过有机发光二极管D的电流与第一薄膜晶体管T1即驱动薄膜晶体管的阈值电压Vth无关，消除了驱动薄膜晶体管的阈值电压Vth对发光二极管D的影响，从而能够使OLED面板的显示亮度较均匀，提升OLED面板的显示品质。
请同时参阅图4至图8，本发明还提供一种OLED像素驱动方法，包括如下步骤：
步骤S1、提供一上述如图2所示的采用6T2C结构的OLED像素驱动电路，此处不再对该OLED像素驱动电路结构进行重复描述，
具体地，所述第一薄膜晶体管T1、第二薄膜晶体管T2、第三薄膜晶体管T3、第四薄膜晶体管T4、第五薄膜晶体管T5、与第六薄膜晶体管T6均为低温多晶硅薄膜晶体管、氧化物半导体薄膜晶体管、或非晶硅薄膜晶体管。所述第n-1条第一扫描信号Scan1(n-1)、第n条第一扫描信号Scan1(n)、第n条第二扫描信号Scan2(n)、第n条第三扫描信号Scan3(n)、第n条第四扫描信号Scan4(n)、与数据信号Data均通过外部时序控制器提供。
步骤S2、请参阅图4，结合图3，进入复位阶段t1。
所述第n-1条第一扫描信号Scan1(n-1)提供高电位，第n条第一扫描信号Scan1(n)提供低电位，第n条第二扫描信号Scan2(n)提供低电位，第n条第三扫描信号Scan3(n)提供低电位，第n条第四扫描信号Scan4(n)提供高电位，数据信号Data提供低电位。
第二薄膜晶体管T2、第三薄膜晶体管T3、与第五薄膜晶体管T5均关断；第四薄膜晶体管T4导通使得第二电容C2的两端短接，从而第二电容C2两端的电压差为0，实现对第二电容C2的复位；第六薄膜晶体管T6导通使得有机发光二极管D的阳极与阴极短接，从而有机发光二极管D的阳极与阴极的电压差为0，实现对有机发光二级管D的复位。
步骤S3、请参阅图5，结合图3，进入阈值电压存储阶段t2。
所述第n-1条第一扫描信号Scan1(n-1)转变为低电位，第n条第一扫描信号Scan1(n)转变为高电位，第n条第二扫描信号Scan2(n)转变为 高电位，第n条第三扫描信号Scan3(n)转变为高电位，第n条第四扫描信号Scan4(n)转变为低电位。
第四薄膜晶体管T4、与第六薄膜晶体管T6均关断；第二薄膜晶体管T2、第一薄膜晶体管T1、第三薄膜晶体管T3、与第五薄膜晶体管T5均导通，数据信号Data向第一节点G提供第一高电位V1D，同时经第一薄膜晶体管T1与第三薄膜晶体管T3对第二电容C2充电，直至第二电容C2的两端即第三节点B与第二节点A的电压差VBA达到：VBA＝V1D-Vth，其中Vth表示第一薄膜晶体管T1即驱动薄膜晶体管的阈值电压。
步骤S4、请参阅图6，结合图3，进入数据写入阶段t3。
所述第n-1条第一扫描信号Scan1(n-1)保持低电位，第n条第一扫描信号Scan1(n)保持高电位，第n条第二扫描信号Scan2(n)转变为低电位，第n条第三扫描信号Scan3(n)保持高电位，第n条第四扫描信号Scan4(n)保持低电位。
第三薄膜晶体管T3、第四薄膜晶体管T4、与第六薄膜晶体管T6均关断；第二薄膜晶体管T2、第一薄膜晶体管T1、与第五薄膜晶体管T5均导通，数据信号Data向第一节点G提供高于第一高电位V1D的第二高电位V2D，同时对第一电容C1充电，使得第一节点G与第二节点A之间的电压差VGA为：
VGA＝V2D。
步骤S5、请参阅图7，结合图3，进入电容串接阶段t4。
所述第n-1条第一扫描信号Scan1(n-1)保持低电位，第n条第一扫描信号Scan1(n)转变为低电位，第n条第二扫描信号Scan2(n)保持低电位，第n条第三扫描信号Scan3(n)转变为低电位，第n条第四扫描信号Scan4(n)转变为高电位，数据信号Data转变为低电位。
第二薄膜晶体管T2、第三薄膜晶体管T3、第四薄膜晶体管T4、与第五薄膜晶体管T5均关断，第六薄膜晶体管T6导通，第一电容C1与第二电容C2串接，使得第一节点G与第三节点B的电压差VGB为：
VGB＝V2D-(V1D-Vth)＝V2D-V1D+Vth；
在该电容串接阶段t4，由于第六薄膜晶体管T6短接了有机发光二极管D的阳极与阴极，所以有机发光二极管D不会发光。
步骤S6、请参阅图8，结合图3，进入显示发光阶段t5。
所述第n-1条第一扫描信号Scan1(n-1)保持低电位，第n条第一扫描信号Scan1(n)保持低电位，第n条第二扫描信号Scan2(n)转变为高电位，第n条第三扫描信号Scan3(n)保持低电位，第n条第四扫描信号Scan4 (n)转变为低电位，数据信号Data提供低电位。
第二薄膜晶体管T2、第四薄膜晶体管T4、第五薄膜晶体管T5、与第六薄膜晶体管T6均关断，第一薄膜晶体管T1、与第三薄膜晶体管T3均导通；在第一电容C1与第二电容C2的存储作用下，第一节点G与第三节点B的电压差VGB也即第一薄膜晶体管T1的栅极与源极之间的电压Vgs保持为：
VGB＝Vgs＝V2D-V1D+Vth；
有机发光二极管D发光；
根据计算流经有机发光二极管D的电流IOLED的公式：
IOLED＝K×(Vgs-Vth)2＝K×(V2D-V1D+Vth-Vth)2＝K×(V2D-V1D)2；
其中，K为驱动薄膜晶体管即第一薄膜晶体管T1的本征导电因子。可见，流过有机发光二极管D的电流与第一薄膜晶体管T1即驱动薄膜晶体管的阈值电压Vth无关，消除了驱动薄膜晶体管的阈值电压Vth对发光二极管D的影响，从而能够使OLED面板的显示亮度较均匀，提升OLED面板的显示品质。
综上所述，本发明的OLED像素驱动电路及像素驱动方法，采用6T2C结构的驱动电路，第n-1条第一扫描信号、第n条第一扫描信号、第n条第二扫描信号、第n条第三扫描信号、第n条第四扫描信号、与数据信号相组合，先后对应于一复位阶段、一阈值电压存储阶段、一数据写入阶段、一电容串接阶段、以及一显示发光阶段，最终使得流过有机发光二极管的电流与驱动薄膜晶体管的阈值电压无关，即能够补偿驱动薄膜晶体管的阈值电压，消除驱动薄膜晶体管的阈值电压对发光二极管的影响，从而能够使OLED面板的显示亮度较均匀，提升OLED面板的显示品质。
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本发明的权利要求的保护范围。

Claims (9)

  1. 一种OLED像素驱动电路，包括第一薄膜晶体管、第二薄膜晶体管、第三薄膜晶体管、第四薄膜晶体管、第五薄膜晶体管、第六薄膜晶体管、第一电容、第二电容、及有机发光二极管；
    所述第一薄膜晶体管的栅极电性连第一节点，漏极接入电源正电压，源极电性连接第三薄膜晶体管的漏极；该第一薄膜晶体管为驱动薄膜晶体管；
    设n为大于1的正整数，所述第二薄膜晶体管的栅极接入该OLED像素驱动电路所在行对应的第n条第三扫描信号，源极接入数据信号，漏极电性连第一节点；
    所述第三薄膜晶体管的栅极接入该OLED像素驱动电路所在行对应的第n条第二扫描信号，漏极电性连接第一薄膜晶体管的源极，源极电性连第三节点；
    所述第四薄膜晶体管的栅极接入该OLED像素驱动电路所在行的上一行对应的第n-1条第一扫描信号，源极电性连接第二节点与第二电容的一端，漏极电性连接第三节点与第二电容的另一端；
    所述第五薄膜晶体管的栅极接入该OLED像素驱动电路所在行对应的第n条第一扫描信号，源极电性连接第二节点，漏极接入电源负电压；
    所述第六薄膜晶体管的栅极接入该OLED像素驱动电路所在行对应的第n条第四扫描信号，源极电性连接第三节点，漏极接入电源负电压；
    所述第一电容的一端电性连接第一节点，另一端电性连接第二节点；
    所述第二电容的一端电性连接第二节点，另一端电性连接第三节点；
    所述有机发光二极管的阳极电性连接第三节点，阴极接入电源负电压。
  2. 如权利要求1所述的OLED像素驱动电路，其中，所述第一薄膜晶体管、第二薄膜晶体管、第三薄膜晶体管、第四薄膜晶体管、第五薄膜晶体管、与第六薄膜晶体管均为低温多晶硅薄膜晶体管、氧化物半导体薄膜晶体管、或非晶硅薄膜晶体管。
  3. 如权利要求1所述的OLED像素驱动电路，其中，所述第n-1条第一扫描信号、第n条第一扫描信号、第n条第二扫描信号、第n条第三扫描信号、第n条第四扫描信号、与数据信号均通过外部时序控制器提供。
  4. 如权利要求1所述的OLED像素驱动电路，其中，所述第n-1条第一扫描信号、第n条第一扫描信号、第n条第二扫描信号、第n条第三扫 描信号、第n条第四扫描信号、与数据信号相组合，先后对应于一复位阶段、一阈值电压存储阶段、一数据写入阶段、一电容串接阶段、以及一显示发光阶段。
  5. 如权利要求4所述的OLED像素驱动电路，其中，在所述复位阶段，所述第n-1条第一扫描信号为高电位，第n条第一扫描信号为低电位，第n条第二扫描信号为低电位，第n条第三扫描信号为低电位，第n条第四扫描信号为高电位，数据信号为低电位；
    在所述阈值电压存储阶段，所述第n-1条第一扫描信号为低电位，第n条第一扫描信号为高电位，第n条第二扫描信号为高电位，第n条第三扫描信号为高电位，第n条第四扫描信号为低电位，数据信号为第一高电位；
    在所述数据写入阶段，所述第n-1条第一扫描信号为低电位，第n条第一扫描信号为高电位，第n条第二扫描信号为低电位，第n条第三扫描信号为高电位，第n条第四扫描信号为低电位，数据信号为高于第一高电位的第二高电位；
    在所述电容串接阶段，所述第n-1条第一扫描信号为低电位，第n条第一扫描信号为低电位，第n条第二扫描信号为低电位，第n条第三扫描信号为低电位，第n条第四扫描信号为高电位，数据信号为低电位；
    在所述显示发光阶段，所述第n-1条第一扫描信号为低电位，第n条第一扫描信号为低电位，第n条第二扫描信号为高电位，第n条第三扫描信号为低电位，第n条第四扫描信号为低电位，数据信号为低电位。
  6. 一种OLED像素驱动方法，包括如下步骤：
    步骤S1、提供OLED像素驱动电路；
    所述OLED像素驱动电路包括第一薄膜晶体管、第二薄膜晶体管、第三薄膜晶体管、第四薄膜晶体管、第五薄膜晶体管、第六薄膜晶体管、第一电容、第二电容、及有机发光二极管；
    所述第一薄膜晶体管的栅极电性连第一节点，漏极接入电源正电压，源极电性连接第三薄膜晶体管的漏极；该第一薄膜晶体管为驱动薄膜晶体管；
    设n为大于1的正整数，所述第二薄膜晶体管的栅极接入该OLED像素驱动电路所在行对应的第n条第三扫描信号，源极接入数据信号，漏极电性连第一节点；
    所述第三薄膜晶体管的栅极接入该OLED像素驱动电路所在行对应的第n条第二扫描信号，漏极电性连接第一薄膜晶体管的源极，源极电性连第三节点；
    所述第四薄膜晶体管的栅极接入该OLED像素驱动电路所在行的上一行对应的第n-1条第一扫描信号，源极电性连接第二节点与第二电容的一端，漏极电性连接第三节点与第二电容的另一端；
    所述第五薄膜晶体管的栅极接入该OLED像素驱动电路所在行对应的第n条第一扫描信号，源极电性连接第二节点，漏极接入电源负电压；
    所述第六薄膜晶体管的栅极接入该OLED像素驱动电路所在行对应的第n条第四扫描信号，源极电性连接第三节点，漏极接入电源负电压；
    所述第一电容的一端电性连接第一节点，另一端电性连接第二节点；
    所述第二电容的一端电性连接第二节点，另一端电性连接第三节点；
    所述有机发光二极管的阳极电性连接第三节点，阴极接入电源负电压；
    步骤S2、进入复位阶段；
    所述第n-1条第一扫描信号提供高电位，第n条第一扫描信号提供低电位，第n条第二扫描信号提供低电位，第n条第三扫描信号提供低电位，第n条第四扫描信号提供高电位，数据信号提供低电位；第二薄膜晶体管、第三薄膜晶体管、与第五薄膜晶体管均关断；第四薄膜晶体管导通对第二电容进行复位；第六薄膜晶体管导通对有机发光二级管进行复位；
    步骤S3、进入阈值电压存储阶段；
    所述第n-1条第一扫描信号转变为低电位，第n条第一扫描信号转变为高电位，第n条第二扫描信号转变为高电位，第n条第三扫描信号转变为高电位，第n条第四扫描信号转变为低电位；第四薄膜晶体管、与第六薄膜晶体管均关断；第二薄膜晶体管、第一薄膜晶体管、第三薄膜晶体管、与第五薄膜晶体管均导通，数据信号向第一节点提供第一高电位，同时对第二电容充电，直至第三节点与第二节点的电压差VBA达到：VBA＝V1D-Vth，其中V1D表示数据信号提供的第一高电位，Vth表示第一薄膜晶体管的阈值电压；
    步骤S4、进入数据写入阶段；
    所述第n-1条第一扫描信号保持低电位，第n条第一扫描信号保持高电位，第n条第二扫描信号转变为低电位，第n条第三扫描信号保持高电位，第n条第四扫描信号保持低电位；第三薄膜晶体管、第四薄膜晶体管、与第六薄膜晶体管均关断；第二薄膜晶体管、第一薄膜晶体管、与第五薄膜晶体管均导通，数据信号向第一节点提供高于第一高电位的第二高电位，同时对第一电容充电，使得第一节点与第二节点之间的电压差VGA为：VGA＝V2D，其中V2D表示数据信号提供的第二高电位；
    步骤S5、进入电容串接阶段；
    所述第n-1条第一扫描信号保持低电位，第n条第一扫描信号转变为低电位，第n条第二扫描信号保持低电位，第n条第三扫描信号转变为低电位，第n条第四扫描信号转变为高电位，数据信号转变为低电位；第二薄膜晶体管、第三薄膜晶体管、第四薄膜晶体管、与第五薄膜晶体管均关断，第六薄膜晶体管导通，第一电容与第二电容串接，使得第一节点与第三节点的电压差VGB为：VGB＝V2D-V1D+Vth；
    步骤S6、进入显示发光阶段；
    所述第n-1条第一扫描信号保持低电位，第n条第一扫描信号保持低电位，第n条第二扫描信号转变为高电位，第n条第三扫描信号保持低电位，第n条第四扫描信号转变为低电位，数据信号提供低电位；第二薄膜晶体管、第四薄膜晶体管、第五薄膜晶体管、与第六薄膜晶体管均关断，第一薄膜晶体管、与第三薄膜晶体管均导通，有机发光二极管发光，且流过有机发光二极管的电流与驱动薄膜晶体管的阈值电压无关。
  7. 如权利要求6所述的OLED像素驱动方法，其中，所述第一薄膜晶体管、第二薄膜晶体管、第三薄膜晶体管、第四薄膜晶体管、第五薄膜晶体管、与第六薄膜晶体管均为低温多晶硅薄膜晶体管、氧化物半导体薄膜晶体管、或非晶硅薄膜晶体管。
  8. 如权利要求6所述的OLED像素驱动方法，其中，所述第n-1条第一扫描信号、第n条第一扫描信号、第n条第二扫描信号、第n条第三扫描信号、第n条第四扫描信号、与数据信号均通过外部时序控制器提供。
  9. 一种OLED像素驱动电路，包括第一薄膜晶体管、第二薄膜晶体管、第三薄膜晶体管、第四薄膜晶体管、第五薄膜晶体管、第六薄膜晶体管、第一电容、第二电容、及有机发光二极管；
    所述第一薄膜晶体管的栅极电性连第一节点，漏极接入电源正电压，源极电性连接第三薄膜晶体管的漏极；该第一薄膜晶体管为驱动薄膜晶体管；
    设n为大于1的正整数，所述第二薄膜晶体管的栅极接入该OLED像素驱动电路所在行对应的第n条第三扫描信号，源极接入数据信号，漏极电性连第一节点；
    所述第三薄膜晶体管的栅极接入该OLED像素驱动电路所在行对应的第n条第二扫描信号，漏极电性连接第一薄膜晶体管的源极，源极电性连第三节点；
    所述第四薄膜晶体管的栅极接入该OLED像素驱动电路所在行的上一行对应的第n-1条第一扫描信号，源极电性连接第二节点与第二电容的一端， 漏极电性连接第三节点与第二电容的另一端；
    所述第五薄膜晶体管的栅极接入该OLED像素驱动电路所在行对应的第n条第一扫描信号，源极电性连接第二节点，漏极接入电源负电压；
    所述第六薄膜晶体管的栅极接入该OLED像素驱动电路所在行对应的第n条第四扫描信号，源极电性连接第三节点，漏极接入电源负电压；
    所述第一电容的一端电性连接第一节点，另一端电性连接第二节点；
    所述第二电容的一端电性连接第二节点，另一端电性连接第三节点；
    所述有机发光二极管的阳极电性连接第三节点，阴极接入电源负电压；
    其中，所述第一薄膜晶体管、第二薄膜晶体管、第三薄膜晶体管、第四薄膜晶体管、第五薄膜晶体管、与第六薄膜晶体管均为低温多晶硅薄膜晶体管、氧化物半导体薄膜晶体管、或非晶硅薄膜晶体管；
    其中，所述第n-1条第一扫描信号、第n条第一扫描信号、第n条第二扫描信号、第n条第三扫描信号、第n条第四扫描信号、与数据信号均通过外部时序控制器提供；
    其中，所述第n-1条第一扫描信号、第n条第一扫描信号、第n条第二扫描信号、第n条第三扫描信号、第n条第四扫描信号、与数据信号相组合，先后对应于一复位阶段、一阈值电压存储阶段、一数据写入阶段、一电容串接阶段、以及一显示发光阶段；
    其中，在所述复位阶段，所述第n-1条第一扫描信号为高电位，第n条第一扫描信号为低电位，第n条第二扫描信号为低电位，第n条第三扫描信号为低电位，第n条第四扫描信号为高电位，数据信号为低电位；
    在所述阈值电压存储阶段，所述第n-1条第一扫描信号为低电位，第n条第一扫描信号为高电位，第n条第二扫描信号为高电位，第n条第三扫描信号为高电位，第n条第四扫描信号为低电位，数据信号为第一高电位；
    在所述数据写入阶段，所述第n-1条第一扫描信号为低电位，第n条第一扫描信号为高电位，第n条第二扫描信号为低电位，第n条第三扫描信号为高电位，第n条第四扫描信号为低电位，数据信号为高于第一高电位的第二高电位；
    在所述电容串接阶段，所述第n-1条第一扫描信号为低电位，第n条第一扫描信号为低电位，第n条第二扫描信号为低电位，第n条第三扫描信号为低电位，第n条第四扫描信号为高电位，数据信号为低电位；
    在所述显示发光阶段，所述第n-1条第一扫描信号为低电位，第n条第一扫描信号为低电位，第n条第二扫描信号为高电位，第n条第三扫描信号为低电位，第n条第四扫描信号为低电位，数据信号为低电位。
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