WO2021092990A1 - 像素驱动电路和显示面板 - Google Patents

像素驱动电路和显示面板 Download PDF

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Publication number
WO2021092990A1
WO2021092990A1 PCT/CN2019/119871 CN2019119871W WO2021092990A1 WO 2021092990 A1 WO2021092990 A1 WO 2021092990A1 CN 2019119871 W CN2019119871 W CN 2019119871W WO 2021092990 A1 WO2021092990 A1 WO 2021092990A1
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WIPO (PCT)
Prior art keywords
transistor
point
light
control signal
reference voltage
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PCT/CN2019/119871
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English (en)
French (fr)
Inventor
杨波
梁鹏飞
Original Assignee
深圳市华星光电半导体显示技术有限公司
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Application filed by 深圳市华星光电半导体显示技术有限公司 filed Critical 深圳市华星光电半导体显示技术有限公司
Priority to US16/625,119 priority Critical patent/US20210343229A1/en
Publication of WO2021092990A1 publication Critical patent/WO2021092990A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2007—Display of intermediate tones
    • G09G3/2077—Display of intermediate tones by a combination of two or more gradation control methods
    • G09G3/2081—Display of intermediate tones by a combination of two or more gradation control methods with combination of amplitude modulation and time modulation
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0852—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor being a dynamic memory with more than one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/06—Adjustment of display parameters
    • G09G2320/066—Adjustment of display parameters for control of contrast

Definitions

  • This application relates to the field of display technology, and in particular to a pixel drive circuit and a display panel.
  • LED devices have the characteristics of high brightness and long life, and are widely used in the field of display technology. Due to the low contrast of LEDs at low gray scales, the existing LED driving method uses PWM dimming technology to shorten the LED light-emitting time, thereby achieving a more accurate gray scale distinction. However, this driving method cannot compensate for the threshold voltage of the driving transistor. Differences will cause uneven brightness of the screen when displayed.
  • the existing display panel has technical problems that high contrast and uniform brightness cannot be achieved at the same time, and it needs to be improved.
  • the present application provides a pixel driving circuit and a display panel to alleviate the technical problem that high contrast and uniform brightness cannot be achieved at the same time in the existing display panel.
  • the present application provides a pixel driving circuit, including:
  • the reference voltage input module is used to input the reference voltage to the first point under the control of the first control signal in the first working state
  • a light emitting module connected to the reference voltage input module through the first point, and configured to emit light under the control of a second control signal and the potential of the first point;
  • a sensing module connected to the light-emitting module through a second point, and configured to sense the threshold voltage of the light-emitting module under the control of a third control signal;
  • the storage capacitor module is connected to the light-emitting module through the first point, the second point, and the third point, and is used to store the threshold voltage of the light-emitting module;
  • the data signal input module is connected to the reference voltage input module and the light emitting module through the first point, and is used to input to the first point under the control of the fourth control signal in the second working state Data signal
  • the reference voltage input module is further configured to input the reference voltage to the first point under the control of the first control signal in the third working state after the light-emitting module emits light to control the The light-emitting module stops emitting light.
  • the reference voltage input module includes a first transistor, the gate of the first transistor is connected to the first control signal, and the first electrode of the first transistor is connected to the reference voltage input Terminal is connected, and the second electrode of the first transistor is connected to the first point.
  • the light-emitting module includes a second transistor, a third transistor, and a light-emitting diode, the gate of the second transistor is connected to the second control signal, and the first transistor of the second transistor is connected to the second control signal.
  • the electrode is connected to the third point and the first power signal, the second electrode of the second transistor is connected to the first electrode of the third transistor, and the gate of the third transistor is connected to the first point.
  • the second electrode of the third transistor is connected to the second point and the anode of the light emitting diode, and the cathode of the light emitting diode is connected to a second power signal.
  • the sensing module includes a fourth transistor, the gate of the fourth transistor is connected to the third control signal, and the first electrode of the fourth transistor is connected to the initial voltage input terminal. Connected, the second electrode of the fourth transistor is connected to the second point.
  • the storage capacitor module includes a first storage capacitor and a second storage capacitor, the first plate of the first storage capacitor is connected to the first point, and the first storage capacitor The second electrode plate and the first electrode plate of the second storage capacitor are connected through the second point, and the second electrode plate of the second storage capacitor is connected to the third point.
  • the data signal input module includes a fifth transistor, the gate of the fifth transistor is connected to the fourth control signal, and the first electrode of the fifth transistor is connected to the data line , The second electrode of the fifth transistor is connected to the first point.
  • the reference voltage input module is used to input a high-potential reference voltage in the first working state.
  • the reference voltage input module is used for inputting a high potential reference voltage in the third working state.
  • the first control signal, the second control signal, the third control signal, and the fourth control signal are all provided by an external timing device.
  • the present application also provides a display panel, including the pixel driving circuit described in any one of the above.
  • the present application provides a pixel drive circuit and a display panel.
  • the pixel drive circuit includes: a reference voltage input module for inputting a reference voltage to a first point under the control of a first control signal in a first working state; a light emitting module, It is connected to the reference voltage input module through the first point, and is used to emit light under the control of the second control signal and the potential of the first point; the sensing module is connected to the light emitting module through the second point, and Under the control of the third control signal, the threshold voltage of the light-emitting module is sensed; the storage capacitor module is connected to the light-emitting module through the first point, the second point, and the third point for storing The threshold voltage of the light-emitting module; a data signal input module, which is connected to the reference voltage input module and the light-emitting module through the first point, and is used in the second working state under the control of a fourth control signal , Input a data signal to the first point; wherein, the reference voltage input module is
  • the present application obtains and stores the threshold voltage of the light-emitting module in the first working state, can compensate for the threshold voltage difference after the data signal is written in the second working state, and can control the light-emitting module by inputting a reference voltage in the third working state The light emission is stopped and the light emission time is shortened. Therefore, the pixel driving circuit of the present application can simultaneously improve the uniformity of the picture and realize the high contrast ratio, thereby improving the display effect.
  • FIG. 1 is a schematic structural diagram of a pixel driving circuit provided by the implementation of this application;
  • FIG. 2 is a timing diagram of various signals in a pixel driving circuit provided by an embodiment of the application.
  • Figure 3 is a schematic diagram of contrast comparison when PWM dimming is used and when PWM dimming is not used;
  • FIG. 4 is a schematic diagram of the structure of a pixel driving circuit in the prior art
  • FIG. 5 is a schematic diagram showing the comparison between the dimming time zone and the light-emitting time zone of the prior art and this embodiment.
  • the present application provides a pixel driving circuit and a display panel to alleviate the technical problem that high contrast and uniform brightness cannot be achieved at the same time in the existing display panel.
  • LED devices have the characteristics of high brightness and long life, and are widely used in the field of display technology. Due to the low contrast of LEDs at low gray scales, the existing LED driving method uses PWM dimming technology to shorten the LED light-emitting time, thereby achieving a more accurate gray scale distinction. However, this driving method cannot compensate for the threshold voltage of the driving transistor. Differences will cause uneven brightness of the screen when displayed.
  • the existing display panel has technical problems that high contrast and uniform brightness cannot be achieved at the same time, and it needs to be improved.
  • the pixel driving circuit includes a reference voltage input module 101, a light emitting module 102, a sensing module 103, a storage capacitor module 104, and a data signal input module 105.
  • the reference voltage input module 101 is configured to input a reference voltage Vref to the first point g under the control of the first control signal PWM in the first working state;
  • the light emitting module 102 is connected to the reference voltage input module 101 through the first point g, and is configured to emit light under the control of the second control signal EM and the potential of the first point g;
  • the sensing module 103 is connected to the light emitting module 102 through the second point s, and is used for sensing the threshold voltage Vth of the light emitting module 102 under the control of the third control signal RD;
  • the storage capacitor module 104 is connected to the light-emitting module 102 through the first point g, the second point s, and the third point a, and is used to store the threshold voltage Vth of the light-emitting module 102;
  • the data signal input module 105 is connected to the reference voltage input module 101 and the light emitting module 102 through the first point g, and is used to input the data signal data to the first point g under the control of the fourth control signal WR in the second working state. ;
  • the reference voltage input module 101 is also used to input the reference voltage Vref to the first point g under the control of the first control signal PWM in the third working state after the light-emitting module 102 emits light to control the light-emitting module 102 not to emit light.
  • the reference voltage input module 101 includes a first transistor T1, the gate of the first transistor T1 is connected to the first control signal PWM, the first electrode of the first transistor T1 is connected to the reference voltage input terminal, and the first transistor T1 is connected to the reference voltage input terminal.
  • the two electrodes are connected to the first point g.
  • the light emitting module 102 includes a second transistor T2, a third transistor T3, and a light emitting diode D.
  • the gate of the second transistor T2 is connected to the second control signal EM.
  • the first electrode of the second transistor T2 is connected to the third point a and the first power source.
  • the signal OVDD is connected, the second electrode of the second transistor T2 is connected to the first electrode of the third transistor T3, the gate of the third transistor T3 is connected to the first point g, and the anode of the third transistor T3 is connected to the second point s and emits light.
  • the anode of the diode D is connected, and the cathode of the light emitting diode D is connected to the second power signal OVSS.
  • the sensing module 103 includes a fourth transistor T4, the gate of the fourth transistor T4 is connected to the third control signal RD, the first electrode of the fourth transistor T4 is connected to the initial voltage input terminal, and the second electrode of the fourth transistor T4 is connected to the Two-point s connection.
  • the storage capacitor module 104 includes a first storage capacitor Cst and a second storage capacitor C1.
  • the first plate of the first storage capacitor Cst is connected to the first point g, and the second plate of the first storage capacitor Cst and the second storage capacitor C1
  • the first electrode plate of is connected through the second point s, and the second electrode plate of the second storage capacitor C1 is connected to the third point a.
  • the data signal input module includes a fifth transistor T5, the gate of the fifth transistor T5 is connected to the fourth control signal WR, the first electrode of the fifth transistor T5 is connected to the data line, and the second electrode of the fifth transistor T5 is connected to the first point. gConnect.
  • one of the first electrode and the second electrode of each transistor is the source and the other is the drain.
  • the initial voltage input terminal is used to input the initial voltage Vpre
  • the data line is used to input the data signal Data
  • the reference voltage input terminal is used to input the reference voltage Vref.
  • the first power supply signal OVDD is the power supply high potential signal
  • the second power supply OVSS is the power supply low potential. Signal, the output voltage value of the first power signal OVDD is greater than the voltage value output of the second power signal OVSS.
  • the third transistor T3 is a driving transistor, and the threshold voltage of the light emitting module 102 is the threshold voltage Vth of the third transistor T3.
  • the first control signal PWM, the second control signal EM, the third control signal RD, and the fourth control signal WR are all provided by an external timing device.
  • FIG. 2 it is a timing diagram of each signal in the pixel driving circuit provided by the embodiment of this application.
  • the operation of the pixel driving circuit includes an initialization phase t0, a data writing phase t1, and a light-emitting phase t2.
  • the initialization phase t0 corresponds to the first working state
  • the data writing phase t1 corresponds to the second working state
  • the light-emitting phase t2 corresponds to the third working state.
  • the initialization phase t0 includes a threshold voltage extraction phase t01 and a threshold voltage storage phase t02, wherein the threshold voltage extraction phase t01 also includes a first phase and a second phase.
  • the first control signal PWM is at a high level
  • the first transistor T1 is turned on
  • a high-level reference voltage Vref is input to the first point g
  • the fourth control signal WR is a low-level signal.
  • the third control signal RD is at a high potential
  • the potential difference between the reference voltage Vref and the initial voltage Vpre is greater than the threshold voltage Vth of the third transistor T3, and the potential of the initial voltage Vpre is less than the threshold voltage Vth1 of the light emitting diode D, that is, Vref-Vpre>Vth, Vpre ⁇ Vth1.
  • the third transistor T3 is turned on, but no current flows through the light emitting diode D.
  • the first control signal PWM and the reference voltage Vref are still at a high level
  • the fourth control signal WR is still at a low level
  • the potential Vg at the first point g Vref
  • the third transistor T3 turn on.
  • the third control signal RD is at a low level
  • the fourth transistor T4 is turned off. Due to the effects of the first storage capacitor Cst and the second storage capacitor C1, the potential of the second node s will correspondingly change until the third transistor T3 is turned off.
  • Vs Vref-Vth ⁇ Vth1
  • the light-emitting diode D still does not emit light.
  • the sensing module 103 senses the Vpre value at the moment when the third transistor T3 is fully charged, and obtains the threshold voltage Vth of the third transistor T3 through calculation.
  • the first control signal PMW, the third control signal RD, and the fourth control signal WR are at a low level
  • the first transistor T1, the fourth transistor T4, and the fifth transistor T5 are turned off
  • the second control signal EM is At a high potential
  • the second transistor T2 is turned on, and Vth is stored to both sides of the first storage capacitor Cst.
  • the first control signal PMW and the third control signal RD are at a low potential
  • the first transistor T1 and the fourth transistor T4 are turned off
  • the second control signal EM is at a low potential
  • the second transistor T2 is turned off
  • the fourth transistor T2 is turned off.
  • the control signal WR is at a high potential
  • the data line inputs a high-level data signal data to the first point g.
  • the first control signal PMW, the third control signal RD, and the fourth control signal WR are at a low level
  • the first transistor T1, the fourth transistor T4, and the fifth transistor T5 are turned off
  • the second control signal EM is at a high level
  • the second transistor T2 is turned on
  • the potential Vg of the first point g is high
  • the third transistor T3 is also turned on
  • the light emitting diode D emits light under the control of the second control signal EM and the potential of the first point g.
  • the formula for the current I(D) flowing through the light-emitting diode D is:
  • Vg Vdata
  • Vs (Vref-Vth)+(Vdata-Vref)*Cst/(Cst+C1)
  • I(D) 1/2*K((Vdata-Vref)*Cst/(Cst+C1)-Vref)2.
  • K is the intrinsic conductivity factor of the driving thin film transistor, that is, the third transistor T3. It can be seen that the current flowing through the light-emitting diode D has nothing to do with the threshold voltage Vth of the third transistor T3, and the threshold voltage Vth drift of the driving transistor is eliminated. The influence of D can make the display brightness of the display panel more uniform and improve the display quality of the display panel.
  • the reference voltage input module 101 inputs the reference voltage Vref to the first point g under the control of the first control signal PWM to control the light-emitting module 102 to stop light-emitting.
  • the pixel driving circuit provided by the embodiment of the application is suitable for LED display panels.
  • the LED brightness is high.
  • the conventional LED driving method cannot achieve high-precision discrimination of low gray scales, that is, the contrast is low.
  • the first control signal PWM is used to control the input time of the reference voltage Vref, so that the light-emitting time of the LED can be shortened, and a more accurate gray scale distinction can be achieved.
  • the first control signal PWM is a rectangular wave and is connected to the gate of the first transistor T1, which can make the input reference voltage Vref a rectangular wave with the same duty cycle, that is, when the first control signal PWM is When the potential is high, the reference voltage Vref is also at a high potential, and when the first control signal PWM is at a low potential, the reference voltage Vref is also at a low potential.
  • the reference voltage Vref of the high potential interacts with other modules, so that the light-emitting diode D does not emit light.
  • the first control signal PWM is at a low potential
  • the reference voltage Vref interacts with other modules to make the light-emitting diode D emit light.
  • the input first control signal PWM is at a high potential
  • the reference voltage input module 101 works with other modules to complete the extraction of the threshold voltage Vth.
  • the low-level first control signal PWM is input to complete the storage of the threshold voltage Vth, the writing of the data signal Data, and the light emitting of the light emitting diode D.
  • the first control signal PWM can be changed from low to high at any time as needed.
  • the input reference voltage Vref is also at high, and the signal potentials in the other modules are The high and low are consistent with the threshold voltage extraction phase t01.
  • the light emitting diode D stops emitting light, and the first control signal PWM plays a role in adjusting the light emitting time.
  • the first control signal PWM at this stage is used to complete the initialization in the next frame The function of dimming and initialization is completed in the same time period.
  • the reference voltage input module 101 simultaneously plays the role of dimming and initialization.
  • FIG. 3 it is a schematic diagram of contrast comparison when PWM dimming is used and when PWM dimming is not used.
  • A is the contrast curve when PWM dimming is not used
  • B is the contrast curve after dimming by the pixel driving circuit of the embodiment of the application.
  • the abscissa T represents time
  • the ordinate Lum represents light intensity
  • T1 and T2 respectively represent two The moment when a dimming method is adjusted to a stable state.
  • FIG. 4 it is a schematic structural diagram of a pixel driving circuit in the prior art, which includes a driving transistor DT, a first switching transistor ST1, a second switching transistor ST2, and a third switching transistor ST3, a light emitting diode D and a storage capacitor C.
  • the first electrode of the transistor DT is connected to the power supply high potential EVDD
  • the second electrode is connected to the anode of the light emitting diode D
  • the cathode of the light emitting diode D is connected to the power supply low potential EVSS
  • the poles are all connected to the fifth control signal GP
  • the gate of the third switch transistor ST3 is connected to the dimming signal PWM.
  • the second electrode of the first switching transistor ST1, the gate of the driving transistor DT, the first electrode of the third switching transistor ST3, and the first plate of the storage capacitor C are commonly connected to the first node N1, and the second electrode of the storage capacitor C
  • the plate, the second electrode of the driving transistor DT, the second electrode of the second switching transistor ST2, and the anode of the light emitting diode D are connected to the second node N2.
  • the first electrode and the second electrode of the third transistor ST3 are respectively connected to the first node N1 and the power supply low potential EVSS, and the gate of the third transistor ST3 is connected to the dimming signal PWM for dimming.
  • This dimming method adopts the method of directly connecting the first node N1 and the power supply low potential EVSS to dimming the light-emitting diode D, so that it stops emitting light.
  • the dimming time can only be fixedly adjusted before and after the entire light-emitting period of the light-emitting diode D. .
  • FIG. 5 it is a schematic diagram of the comparison between the dimming time zone and the light emitting time zone of the prior art and this embodiment.
  • the first group from top to bottom represents the relationship between the dimming time zone 10 and the light-emitting time zone 20 in the prior art
  • the second group represents the relationship between the dimming time zone 10 and the light-emitting time zone 20 in this embodiment.
  • the PWM dimming method adopted in the prior art can only perform dimming before and after the light-emitting time zone 20, while the PWM dimming method in this embodiment can perform dimming at any time within the light-emitting time zone 20.
  • the present application can be adjusted in the entire light-emitting time zone, which expands the selection range of the dimming time, and flexibly setting the dimming time is more conducive to achieving high contrast under low gray levels.
  • the present application also provides a display panel, including the pixel driving circuit described in any of the above embodiments.
  • the display panel is an LED display panel.
  • the present application provides a pixel drive circuit and a display panel.
  • the pixel drive circuit includes: a reference voltage input module for inputting a reference voltage to a first point under the control of a first control signal in a first working state; a light emitting module, The first point is connected to the reference voltage input module, which is used to emit light under the control of the second control signal and the potential of the first point; the sensing module, which is connected to the light-emitting module through the second point, is used to control the third control signal
  • the threshold voltage of the light-emitting module is sensed; the storage capacitor module is connected to the light-emitting module through the first point, the second point and the third point for storing the threshold voltage of the light-emitting module; the data signal input module is connected to the light-emitting module through the first point
  • the reference voltage input module is connected to the light-emitting module, and is used to input a data signal to the first point under the control of the fourth control signal in the second working state; wherein,
  • the reference voltage is input to the first point under the control of the first control signal to control the light-emitting module to stop emitting light.
  • the present application obtains and stores the threshold voltage of the light-emitting module in the first working state, can compensate for the threshold voltage difference after the data signal is written in the second working state, and can control the light-emitting module by inputting a reference voltage in the third working state The light emission is stopped and the light emission time is shortened. Therefore, the pixel driving circuit of the present application can simultaneously improve the uniformity of the picture and realize the high contrast ratio, thereby improving the display effect.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Control Of El Displays (AREA)

Abstract

一种像素驱动电路和显示面板，像素驱动电路包括：参考电压输入模块（101），用于输入参考电压（Vref）和控制发光模块（102）停止发光；发光模块（102），用于发光；感测模块（103），用于感测发光模块（102）的阈值电压（Vth）；存储电容模块（104），用于存储发光模块（102）的阈值电压（Vth）；数据信号输入模块（105），用于输入数据信号（data）。像素驱动电路可以同时提升画面均匀性和实现高对比度。

Description

像素驱动电路和显示面板 技术领域
本申请涉及显示技术领域，尤其涉及一种像素驱动电路和显示面板。
 背景技术
LED器件具有亮度高、寿命长的特点，在显示技术领域广泛应用。由于LED在低灰阶下对比度较低，现有的LED驱动方法采用PWM调光技术来缩短LED发光时间，进而达到精度更大的灰阶区分，然而这种驱动方法无法补偿驱动晶体管的阈值电压差异，显示时会造成画面亮度不均。
因此，现有的显示面板存在不能同时实现高对比度和亮度均匀的技术问题，需要改进。
 技术问题
本申请提供一种像素驱动电路和显示面板，以缓解现有的显示面板中不能同时实现高对比度和亮度均匀的技术问题。
 技术解决方案
为解决上述问题，本申请提供的技术方案如下：
本申请提供一种像素驱动电路，包括：
参考电压输入模块，用于在第一工作状态时，在第一控制信号的控制下向第一点输入参考电压；
发光模块，通过所述第一点与所述参考电压输入模块连接，用于在第二控制信号和所述第一点的电位控制下发光；
感测模块，通过第二点与所述发光模块连接，用于在第三控制信号的控制下，感测所述发光模块的阈值电压；
存储电容模块，通过所述第一点、所述第二点和第三点与所述发光模块连接，用于存储所述发光模块的阈值电压；
数据信号输入模块，通过所述第一点与所述参考电压输入模块和所述发光模块连接，用于在第二工作状态时，在第四控制信号的控制下，向所述第一点输入数据信号；
其中，所述参考电压输入模块还用于在所述发光模块发光后的第三工作状态时，在所述第一控制信号的控制下向所述第一点输入所述参考电压，控制所述发光模块停止发光。
在本申请的像素驱动电路中，所述参考电压输入模块包括第一晶体管，所述第一晶体管的栅极与所述第一控制信号连接，所述第一晶体管的第一电极与参考电压输入端连接，所述第一晶体管的第二电极与所述第一点连接。
在本申请的像素驱动电路中，所述发光模块包括第二晶体管、第三晶体管和发光二极管，所述第二晶体管的栅极与所述第二控制信号连接，所述第二晶体管的第一电极与所述第三点和第一电源信号连接，所述第二晶体管的第二电极与所述第三晶体管的第一电极连接，所述第三晶体管的栅极与所述第一点连接，所述第三晶体管的第二电极与所述第二点和所述发光二极管的阳极连接，所述发光二极管的阴极与第二电源信号连接。
在本申请的像素驱动电路中，所述感测模块包括第四晶体管，所述第四晶体管的栅极与所述第三控制信号连接，所述第四晶体管的第一电极与初始电压输入端连接，所述第四晶体管的第二电极与所述第二点连接。
在本申请的像素驱动电路中，所述存储电容模块包括第一存储电容和第二存储电容，所述第一存储电容的第一极板与所述第一点连接，第一存储电容的第二极板和所述第二存储电容的第一极板通过所述第二点连接，所述第二存储电容的第二极板与所述第三点连接。
在本申请的像素驱动电路中，所述数据信号输入模块包括第五晶体管，所述第五晶体管的栅极与所述第四控制信号连接，所述第五晶体管的第一电极与数据线连接，所述第五晶体管的第二电极与所述第一点连接。
在本申请的像素驱动电路中，所述参考电压输入模块用于，在第一工作状态时输入高电位的参考电压。
在本申请的像素驱动电路中，所述参考电压输入模块用于，在第三工作状态时输入高电位的参考电压。
在本申请的像素驱动电路中，所述第一控制信号，所述第二控制信号、所述第三控制信号以及所述第四控制信号均由外部时序器提供。
本申请还提供一种显示面板，包括上述任一项所述的像素驱动电路。
 有益效果
本申请提供一种像素驱动电路和显示面板，像素驱动电路包括：参考电压输入模块，用于在第一工作状态时，在第一控制信号的控制下向第一点输入参考电压；发光模块，通过所述第一点与所述参考电压输入模块连接，用于在第二控制信号和所述第一点的电位控制下发光；感测模块，通过第二点与所述发光模块连接，用于在第三控制信号的控制下，感测所述发光模块的阈值电压；存储电容模块，通过所述第一点、所述第二点和第三点与所述发光模块连接，用于存储所述发光模块的阈值电压；数据信号输入模块，通过所述第一点与所述参考电压输入模块和所述发光模块连接，用于在第二工作状态时，在第四控制信号的控制下，向所述第一点输入数据信号；其中，所述参考电压输入模块还用于在所述发光模块发光后的第三工作状态时，在所述第一控制信号的控制下向所述第一点输入所述参考电压，控制所述发光模块停止发光。本申请通过在第一工作状态时获取和存储发光模块的阈值电压，在第二工作状态数据信号写入后可以补偿阈值电压差异，而在第三工作状态时可以通过输入参考电压，控制发光模块停止发光，缩短发光时间，因此，本申请的像素驱动电路可以同时起到提升画面均匀性和实现高对比度的作用，提高了显示效果。
 附图说明
为了更清楚地说明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单介绍，显而易见地，下面描述中的附图仅仅是发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本申请实施提供的像素驱动电路的结构示意图；
图2为本申请实施例提供的像素驱动电路中各信号的时序图；
图3为采用PWM调光和未采用PWM调光时的对比度比较示意图；
图4为现有技术中像素驱动电路的结构示意图；
图5为现有技术和本实施例的调光时间区和发光时间区对比示意图。
 本发明的实施方式
以下各实施例的说明是参考附加的图示，用以例示本申请可用以实施的特定实施例。本申请所提到的方向用语，例如[上]、[下]、[前]、[后]、[左]、[右]、[内]、[外]、[侧面]等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本申请，而非用以限制本申请。在图中，结构相似的单元是用以相同标号表示。
本申请提供一种像素驱动电路和显示面板，以缓解现有的显示面板中不能同时实现高对比度和亮度均匀的技术问题。
LED器件具有亮度高、寿命长的特点，在显示技术领域广泛应用。由于LED在低灰阶下对比度较低，现有的LED驱动方法采用PWM调光技术来缩短LED发光时间，进而达到精度更大的灰阶区分，然而这种驱动方法无法补偿驱动晶体管的阈值电压差异，显示时会造成画面亮度不均。
因此，现有的显示面板存在不能同时实现高对比度和亮度均匀的技术问题，需要改进。
如图1所述，为本申请实施提供的像素驱动电路的结构示意图。像素驱动电路包括参考电压输入模块101、发光模块102、感测模块103、存储电容模块104和数据信号输入模块105。
参考电压输入模块101用于在第一工作状态时，在第一控制信号PWM的控制下向第一点g输入参考电压Vref；
发光模块102通过第一点g与参考电压输入模块101连接，用于在第二控制信号EM和第一点g的电位控制下发光；
感测模块103通过第二点s与发光模块102连接，用于在第三控制信号RD的控制下，感测发光模块102的阈值电压Vth；
存储电容模块104通过第一点g、第二点s和第三点a与发光模块102连接，用于存储发光模块102的阈值电压Vth；
数据信号输入模块105通过第一点g与参考电压输入模块101和发光模块102连接，用于在第二工作状态时，在第四控制信号WR的控制下，向第一点g输入数据信号data；
其中，参考电压输入模块101还用于在发光模块102发光后的第三工作状态时，在第一控制信号PWM的控制下向第一点g输入参考电压Vref，控制发光模块102不发光。
具体地，参考电压输入模块101包括第一晶体管T1，第一晶体管T1的栅极与第一控制信号PWM连接，第一晶体管T1的第一电极与参考电压输入端连接，第一晶体管T1的第二电极与第一点g连接。
发光模块102包括第二晶体管T2、第三晶体管T3和发光二极管D，第二晶体管T2的栅极与第二控制信号EM连接，第二晶体管T2的第一电极与第三点a和第一电源信号OVDD连接，第二晶体管T2的第二电极与第三晶体管T3的第一电极连接，第三晶体管T3的栅极与第一点g连接，第三晶体管T3的阳极与第二点s和发光二极管D的阳极连接，发光二极管D的阴极与第二电源信号OVSS连接。
感测模块103包括第四晶体管T4，第四晶体管T4的栅极与第三控制信号RD连接，第四晶体管T4的第一电极与初始电压输入端连接，第四晶体管T4的第二电极与第二点s连接。
存储电容模块104包括第一存储电容Cst和第二存储电容C1，第一存储电容Cst的第一极板与第一点g连接，第一存储电容Cst的第二极板和第二存储电容C1的第一极板通过第二点s连接，第二存储电容C1的第二极板与第三点a连接。
数据信号输入模块包括第五晶体管T5，第五晶体管T5的栅极与第四控制信号WR连接，第五晶体管T5的第一电极与数据线连接，第五晶体管T5的第二电极与第一点g连接。
在本申请中，各晶体管的第一电极和第二电极，其中一个为源极，另一个为漏极。初始电压输入端用于输入初始电压Vpre，数据线用于输入数据信号Data，参考电压输入端用于输入参考电压Vref，第一电源信号OVDD为电源高电位信号，第二电源OVSS为电源低电位信号,第一电源信号OVDD的输出的电压值大于第二电源信号OVSS输出的电压值。
发光模块102中，第三晶体管T3为驱动晶体管，发光模块102的阈值电压即第三晶体管T3的阈值电压Vth。第一控制信号PWM、第二控制信号EM、第三控制信号RD以及第四控制信号WR均由外部时序器提供。
如图2所示，为本申请实施例提供的像素驱动电路中各信号的时序图。像素驱动电路的运行包括初始化阶段t0、数据写入阶段t1、发光阶段t2。其中，初始化阶段t0对应第一工作状态，数据写入阶段t1对应第二工作状态，发光阶段t2对应第三工作状态。
初始化阶段t0包括阈值电压提取阶段t01和阈值电压存储阶段t02，其中阈值电压提取阶段t01还包括第一阶段和第二阶段。
在阈值电压提取阶段t01的第一阶段，第一控制信号PWM为高电位，第一晶体管T1打开，向第一点g输入高电位的参考电压Vref，第四控制信号WR为低电位信号，第五晶体管T5关闭，此时第一点g的电位Vg=Vref。第三控制信号RD为高电位，第四晶体管T4打开，向第二点s输入高电位的初始电压Vpre，此时第二点s的电位Vs=Vpre。参考电压Vref与初始电压Vpre的电位差值大于第三晶体管T3的阈值电压Vth，且初始电压Vpre的电位小于发光二极管D的阈值电压Vth1，即Vref-Vpre＞Vth，Vpre＜Vth1。此时，第三晶体管T3打开，但无电流流过发光二极管D。
在阈值电压提取阶段t01的第二阶段，第一控制信号PWM和参考电压Vref仍为高电位，第四控制信号WR仍为低电位信号，第一点g的电位Vg=Vref，第三晶体管T3打开。第三控制信号RD为低电位，第四晶体管T4关闭。由于第一存储电容Cst以及第二存储电容C1的作用，第二节点s的电位会相应发生变化，直至第三晶体管T3关闭。
此时，第三晶体管T3的第二电极从上一阶段的Vpre值开始充电，第二点s的电位Vs逐渐升高，直至Vref-Vs=Vth时完成充电。此时，Vs=Vref-Vth＜Vth1，发光二极管D仍然不发光。感测模块103通过感测第三晶体管T3完成充电时刻的Vpre值，通过计算可得到第三晶体管T3的阈值电压Vth。
在阈值电压存储阶段t02，第一控制信号PMW、第三控制信号RD和第四控制信号WR为低电位，第一晶体管T1、第四晶体管T4和第五晶体管T5关闭，第二控制信号EM为高电位，第二晶体管T2打开，Vth被存储至第一存储电容Cst的两侧。
在数据写入阶段t1，第一控制信号PMW和第三控制信号RD为低电位，第一晶体管T1和第四晶体管T4关闭，第二控制信号EM为低电位，第二晶体管T2关闭，第四控制信号WR为高电位，数据线向第一点g输入高电位的数据信号data，此时第一点g的电位Vg=Vdata，相对于上一阶段，第一点g的电位变化为Vdata-Vref，由于第一存储电容Cst与第二存储电容C1的共同耦合作用，第二点s的电位Vs=（Vref-Vth）+（Vdata-Vref）*Cst/（Cst+C1），其中Cst为第一存储电容的电容值，C1为第二存储电容的电容值。
在发光阶段t2，第一控制信号PMW、第三控制信号RD和第四控制信号WR为低电位，第一晶体管T1、第四晶体管T4和第五晶体管T5关闭，第二控制信号EM为高电位，第二晶体管T2开启，第一点g的电位Vg为高电位，第三晶体管T3也开启，发光二极管D在第二控制信号EM和第一点g的电位控制下发光。此时，流经发光二极管D的电流I（D）的公式为：
I（D）=1/2*K（Vg-Vs-Vth）²，
而此时Vg=Vdata，Vs=（Vref-Vth）+（Vdata-Vref）*Cst/（Cst+C1），将两者带入公式，得到的结果为：
I（D）=1/2*K（（Vdata-Vref）*Cst/（Cst+C1）-Vref）²。
其中，K为驱动薄膜晶体管即第三晶体管T3的本征导电因子，可见，流过发光二极管D的电流与第三晶体管T3的阈值电压Vth无关，消除了驱动晶体管的阈值电压Vth漂移对发光二极管D的影响，从而能够使显示面板的显示亮度较均匀，提升显示面板的显示品质。
在发光阶段t2中的某一时刻，参考电压输入模块101在第一控制信号PWM的控制下向第一点g输入参考电压Vref，控制发光模块102停止发光。
本申请实施例提供的像素驱动电路，适用于LED显示面板，LED亮度高，常规的LED驱动方法无法对低灰阶实现高精度区分，即对比度较低，而通过设置参考电压输入模块101，可以用第一控制信号PWM控制参考电压Vref的输入时间，从而可以缩短LED的发光时间，达到更精度的灰阶区分。
如图2所示，第一控制信号PWM为矩形波，连接至第一晶体管T1的栅极，可以使得输入的参考电压Vref成为具有相同占空比的矩形波，即在第一控制信号PWM为高电位时，参考电压Vref也为高电位，在第一控制信号PWM为低电位时，参考电压Vref也为低电位。结合上述实施例中原理，在第一控制信号PWM为高电位时，高电位的参考电压Vref与其他模块相互作用，使得发光二极管D不发光，在第一控制信号PWM为低电位时，低电位的参考电压Vref与其他模块相互作用，使得发光二极管D发光。
因此，在像素驱动电路开始工作时，在阈值电压提取阶段t01，输入的第一控制信号PWM为高电位，参考电压输入模块101和其他模块共同作用，完成对阈值电压Vth的提取。
随后，在阈值电压存储阶段t02、数据写入阶段t1和发光阶段t2，输入低电位的第一控制信号PWM，完成对阈值电压Vth的存储、数据信号Data的写入和发光二极管D的发光。
而在发光阶段t2内的任意时刻，可根据需要随时将第一控制信号PWM由低电位变为高电位，此时输入的参考电压Vref也为高电位，而其他的各模块中各信号电位的高低，与阈值电压提取阶段t01保持一致。此时，发光二极管D停止发光，通过第一控制信号PWM起到了调节发光时间的作用。此外，在发光二极管D发光结束后进行下一帧显示前，还需要进行一次阈值电压的提取、存储和数据信号写入，因此第一控制信号PWM在此阶段又起到了完成下一帧中初始化的作用，即同一时间段内完成调光和初始化两项工作。通过设置参考电压输入模块101，且用第一控制信号PWM进行调节，使得参考电压输入模块101同时起到了调光和初始化的作用。
如图3所示，为采用PWM调光和未采用PWM调光时的对比度比较示意图。其中A为未采用PWM调光时对比度曲线，B为采用本申请实施例的像素驱动电路进行调光后的对比度曲线，横坐标T代表时间，纵坐标Lum代表光强，T1和T2分别代表两种调光方式调节至稳定状态的时刻。
经对比可知，未采用PWM调光时，在稳定状态，对应像素的光强较强，而采用本申请实施例的像素驱动电路进行调光后，在稳定状态，对应像素的光强较弱，即在低灰阶下实现了更小的亮度，达到精度更大的灰阶区分，因此增强了低灰阶下的对比度，提高了显示效果。
如图4所示，为现有技术中像素驱动电路的结构示意图，包括驱动晶体管DT、第一开关晶体管ST1、第二开关晶体管ST2和第三开关晶体管ST3、发光二极管D和存储电容C，驱动晶体管DT的第一电极和连接电源高电位EVDD，第二电极连接发光二极管D的阳极，发光二极管D的阴极连接电源低电位EVSS，第一开关晶体管ST1的栅极和第二开关晶体管ST2的栅极均连接第五控制信号GP，第三开关晶体管ST3栅极连接调光信号PWM。第一开关晶体管ST1的第二电极、驱动晶体管DT的栅极、第三开关晶体管ST3的第一电极和存储电容C的第一极板共同连接于第一节点N1，存储电容C的第二极板、驱动晶体管DT的第二电极、第二开关晶体管ST2的第二电极以及发光二极管D的阳极连接于第二节点N2。
在现有技术中，第三晶体管ST3的第一电极和第二电极分别连接第一节点N1和电源低电位EVSS，第三晶体管ST3的栅极通过接入调光信号PWM进行调光，然而，此种调光方式采用将第一节点N1和电源低电位EVSS直接连接的方式对发光二极管D进行调光，使其停止发光，调光时间只能在发光二极管D整个发光时间段的前后固定调节。
如图5所示，为现有技术和本实施例的调光时间区和发光时间区对比示意图。由上至下第一组代表现有技术中调光时间区10与发光时间区20的关系，第二组代表本实施中调光时间区10与发光时间区20的关系。
在现有技术中采用的PWM调光方式，只能在发光时间区20的前后进行调光，而本实施例中的PWM调光方式，可以在发光时间区20内的任意时刻进行调光，调光时间越靠前，发光二极管D的发光时间越短，调光时间越靠后，发光二极管D的发光时间越长。与现有技术相比，本申请可以，在整个发光时间区内均可以调节，扩大了调光时间的选择范围，且灵活设置调光时间更有利于实现低灰阶下的高对比度。
本申请还提供一种显示面板，包括上述任一实施例所述的像素驱动电路。在本申请中，显示面板为LED显示面板。通过采用本申请实施例提供的像素驱动电路，显示面板的阈值电压差异得到了补偿，低灰阶下的发光时间得到，因此同时实现了提升画面均匀性和高对比度，显示效果得到提高。
根据上述实施例可知：
本申请提供一种像素驱动电路和显示面板，像素驱动电路包括：参考电压输入模块，用于在第一工作状态时，在第一控制信号的控制下向第一点输入参考电压；发光模块，通过第一点与参考电压输入模块连接，用于在第二控制信号和第一点的电位控制下发光；感测模块，通过第二点与发光模块连接，用于在第三控制信号的控制下，感测发光模块的阈值电压；存储电容模块，通过第一点、第二点和第三点与发光模块连接，用于存储发光模块的阈值电压；数据信号输入模块，通过第一点与参考电压输入模块和发光模块连接，用于在第二工作状态时，在第四控制信号的控制下，向第一点输入数据信号；其中，参考电压输入模块还用于在发光模块发光后的第三工作状态时，在第一控制信号的控制下向第一点输入参考电压，控制发光模块停止发光。本申请通过在第一工作状态时获取和存储发光模块的阈值电压，在第二工作状态数据信号写入后可以补偿阈值电压差异，而在第三工作状态时可以通过输入参考电压，控制发光模块停止发光，缩短发光时间，因此，本申请的像素驱动电路可以同时起到提升画面均匀性和实现高对比度的作用，提高了显示效果。
综上所述，虽然本申请已以优选实施例揭露如上，但上述优选实施例并非用以限制本申请，本领域的普通技术人员，在不脱离本申请的精神和范围内，均可作各种更动与润饰，因此本申请的保护范围以权利要求界定的范围为准。

Claims (20)

  1. 一种像素驱动电路，其包括：
    参考电压输入模块，用于在第一工作状态时，在第一控制信号的控制下向第一点输入参考电压；
    发光模块，通过所述第一点与所述参考电压输入模块连接，用于在第二控制信号和所述第一点的电位控制下发光；
    感测模块，通过第二点与所述发光模块连接，用于在第三控制信号的控制下，感测所述发光模块的阈值电压；
    存储电容模块，通过所述第一点、所述第二点和第三点与所述发光模块连接，用于存储所述发光模块的阈值电压；
    数据信号输入模块，通过所述第一点与所述参考电压输入模块和所述发光模块连接，用于在第二工作状态时，在第四控制信号的控制下，向所述第一点输入数据信号；
    其中，所述参考电压输入模块还用于在所述发光模块发光后的第三工作状态时，在所述第一控制信号的控制下向所述第一点输入所述参考电压，控制所述发光模块停止发光。
  2. 如权利要求1所述的像素驱动电路，其中，所述参考电压输入模块包括第一晶体管，所述第一晶体管的栅极与所述第一控制信号连接，所述第一晶体管的第一电极与参考电压输入端连接，所述第一晶体管的第二电极与所述第一点连接。
  3. 如权利要求2所述的像素驱动电路，其中，所述发光模块包括第二晶体管、第三晶体管和发光二极管，所述第二晶体管的栅极与所述第二控制信号连接，所述第二晶体管的第一电极与所述第三点和第一电源信号连接，所述第二晶体管的第二电极与所述第三晶体管的第一电极连接，所述第三晶体管的栅极与所述第一点连接，所述第三晶体管的第二电极与所述第二点和所述发光二极管的阳极连接，所述发光二极管的阴极与第二电源信号连接。
  4. 如权利要求3所述的像素驱动电路，其中，所述感测模块包括第四晶体管，所述第四晶体管的栅极与所述第三控制信号连接，所述第四晶体管的第一电极与初始电压输入端连接，所述第四晶体管的第二电极与所述第二点连接。
  5. 如权利要求4所述的像素驱动电路，其中，所述存储电容模块包括第一存储电容和第二存储电容，所述第一存储电容的第一极板与所述第一点连接，第一存储电容的第二极板和所述第二存储电容的第一极板通过所述第二点连接，所述第二存储电容的第二极板与所述第三点连接。
  6. 如权利要求5所述的像素驱动电路，其中，所述数据信号输入模块包括第五晶体管，所述第五晶体管的栅极与所述第四控制信号连接，所述第五晶体管的第一电极与数据线连接，所述第五晶体管的第二电极与所述第一点连接。
  7. 如权利要求1所述的像素驱动电路，其中，所述参考电压输入模块用于，在第一工作状态和第三工作状态时，在高电位的第一控制信号的控制下向第一点输入参考电压。
  8. 如权利要求1所述的像素驱动电路，其中，所述参考电压输入模块用于，在第一工作状态时输入高电位的参考电压。
  9. 如权利要求1所述的像素驱动电路，其中，所述参考电压输入模块用于，在第三工作状态时输入高电位的参考电压。
  10. 如权利要求1所述的像素驱动电路，其中，所述第一控制信号，所述第二控制信号、所述第三控制信号以及所述第四控制信号均由外部时序器提供。
  11. 一种显示面板，其包括像素驱动电路，所述像素驱动电路包括：
    参考电压输入模块，用于在第一工作状态时，在第一控制信号的控制下向第一点输入参考电压；
    发光模块，通过所述第一点与所述参考电压输入模块连接，用于在第二控制信号和所述第一点的电位控制下发光；
    感测模块，通过第二点与所述发光模块连接，用于在第三控制信号的控制下，感测所述发光模块的阈值电压；
    存储电容模块，通过所述第一点、所述第二点和第三点与所述发光模块连接，用于存储所述发光模块的阈值电压；
    数据信号输入模块，通过所述第一点与所述参考电压输入模块和所述发光模块连接，用于在第二工作状态时，在第四控制信号的控制下，向所述第一点输入数据信号；
    其中，所述参考电压输入模块还用于在所述发光模块发光后的第三工作状态时，在所述第一控制信号的控制下向所述第一点输入所述参考电压，控制所述发光模块停止发光。
  12. 如权利要求11所述的显示面板，其中，所述参考电压输入模块包括第一晶体管，所述第一晶体管的栅极与所述第一控制信号连接，所述第一晶体管的第一电极与参考电压输入端连接，所述第一晶体管的第二电极与所述第一点连接。
  13. 如权利要求12所述的显示面板，其中，所述发光模块包括第二晶体管、第三晶体管和发光二极管，所述第二晶体管的栅极与所述第二控制信号连接，所述第二晶体管的第一电极与所述第三点和第一电源信号连接，所述第二晶体管的第二电极与所述第三晶体管的第一电极连接，所述第三晶体管的栅极与所述第一点连接，所述第三晶体管的第二电极与所述第二点和所述发光二极管的阳极连接，所述发光二极管的阴极与第二电源信号连接。
  14. 如权利要求13所述的显示面板，其中，所述感测模块包括第四晶体管，所述第四晶体管的栅极与所述第三控制信号连接，所述第四晶体管的第一电极与初始电压输入端连接，所述第四晶体管的第二电极与所述第二点连接。
  15. 如权利要求14所述的显示面板，其中，所述存储电容模块包括第一存储电容和第二存储电容，所述第一存储电容的第一极板与所述第一点连接，第一存储电容的第二极板和所述第二存储电容的第一极板通过所述第二点连接，所述第二存储电容的第二极板与所述第三点连接。
  16. 如权利要求15所述的显示面板，其中，所述数据信号输入模块包括第五晶体管，所述第五晶体管的栅极与所述第四控制信号连接，所述第五晶体管的第一电极与数据线连接，所述第五晶体管的第二电极与所述第一点连接。
  17. 如权利要求11所述的显示面板，其中，所述参考电压输入模块用于，在第一工作状态和第三工作状态时，在高电位的第一控制信号的控制下向第一点输入参考电压。
  18. 如权利要求11所述的显示面板，其中，所述参考电压输入模块用于，在第一工作状态时输入高电位的参考电压。
  19. 如权利要求11所述的显示面板，其中，所述参考电压输入模块用于，在第三工作状态时输入高电位的参考电压。
  20. 如权利要求11所述的显示面板，其中，所述第一控制信号，所述第二控制信号、所述第三控制信号以及所述第四控制信号均由外部时序器提供。
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