WO2023168897A1 - 半导体结构及其制备方法 - Google Patents

半导体结构及其制备方法 Download PDF

Info

Publication number
WO2023168897A1
WO2023168897A1 PCT/CN2022/110753 CN2022110753W WO2023168897A1 WO 2023168897 A1 WO2023168897 A1 WO 2023168897A1 CN 2022110753 W CN2022110753 W CN 2022110753W WO 2023168897 A1 WO2023168897 A1 WO 2023168897A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
semiconductor
forming
bit line
magnetic tunnel
Prior art date
Application number
PCT/CN2022/110753
Other languages
English (en)
French (fr)
Inventor
肖德元
曹堪宇
Original Assignee
长鑫存储技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 长鑫存储技术有限公司 filed Critical 长鑫存储技术有限公司
Priority to US17/936,096 priority Critical patent/US20230292530A1/en
Publication of WO2023168897A1 publication Critical patent/WO2023168897A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N50/00—Galvanomagnetic devices
    • H10N50/01—Manufacture or treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5386—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66666—Vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7827—Vertical transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B61/00—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
    • H10B61/20—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices comprising components having three or more electrodes, e.g. transistors
    • H10B61/22—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices comprising components having three or more electrodes, e.g. transistors of the field-effect transistor [FET] type
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N50/00—Galvanomagnetic devices
    • H10N50/10—Magnetoresistive devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N50/00—Galvanomagnetic devices
    • H10N50/80—Constructional details

Definitions

  • the present disclosure relates to the field of semiconductors, and in particular, to a semiconductor structure and a preparation method thereof.
  • the integration density of a two-dimensional (2D) or planar semiconductor structure is determined in part by the area occupied by the individual elements (eg, memory cells) that make up the integrated circuit.
  • the area occupied by individual elements is largely determined by the dimensional parameters (e.g., width, length, spacing, narrowness, adjacent spacing, etc.) of the patterning technology used to define the individual elements and their interconnections. Providing increasingly "fine" patterns requires the development and use of very expensive patterning equipment.
  • GAA FETs gate-all-around field-effect transistors
  • the channel region is surrounded by the gate electrode on all sides, which allows fuller depletion in the channel region and due to the steeper sub-threshold current swing (SS) and smaller Drain-induced barrier lowering (DIBL) produces less short channel effects.
  • SS sub-threshold current swing
  • DIBL Drain-induced barrier lowering
  • the technical problem to be solved by this disclosure is to provide a semiconductor structure and a preparation method thereof to meet the needs of improving the performance and miniaturization of the semiconductor structure.
  • the present disclosure provides a method for manufacturing a semiconductor structure, including the following steps: providing a substrate; forming a base pattern on the substrate, the base pattern including a plurality of parallel-arranged bit lines, between the bit lines An isolation structure is provided; a plurality of semiconductor pillars arranged along the direction of the bit line are formed on the surface of the bit line, and the bit line is electrically connected to the semiconductor pillar; a surrounding gate structure is formed on the surface of the semiconductor pillar, so The surrounding gate structure includes a first insulating layer, a gate structure layer and a second insulating layer sequentially provided on the side of the semiconductor pillar, and the gate structure layer is electrically connected to the semiconductor pillar; in the surrounding gate A first conductor, a magnetic tunnel junction, and a second conductor are sequentially stacked on the surface of the structure, and the first conductor is electrically connected to the semiconductor pillar.
  • the present disclosure also provides a semiconductor structure, which includes: a substrate; a bit line, which is provided on the surface of the substrate, and a plurality of bit lines are arranged in parallel; and a semiconductor pillar, which is provided on the surface of the bit line and along the bit lines. Arranged in the line direction, the semiconductor pillar is electrically connected to the bit line; a surrounding gate structure, the surrounding gate structure includes a first insulating layer, a gate structure layer and a third layer sequentially arranged on the side of the semiconductor pillar. Two insulating layers; a first conductor, a magnetic tunnel junction and a second conductor are arranged on the surface of the surrounding gate structure in sequence, and the first conductor is electrically connected to the semiconductor pillar.
  • the present disclosure greatly improves the existing semiconductor structure by providing a semiconductor structure and a preparation method thereof, which can form a buried bit line in a substrate, and form a vertical transistor and a magnetic tunnel junction region located on the vertical transistor.
  • the performance of the structure meets the needs of miniaturization.
  • Another advantage of the present disclosure is that the preparation method of the semiconductor device of the present disclosure can prepare a vertical junctionless transistor whose source region, drain region and channel region have the same doping type, and no PN junction is formed, thus avoiding the need for doping. Problems such as threshold voltage drift and increased leakage current caused by heterogeneous mutations. At the same time, junctionless transistors can suppress short channel effects and can still work at several nanometer sizes, which can further improve memory integration and performance.
  • FIG. 1 is a schematic diagram of the steps of a method for manufacturing a semiconductor structure provided by a specific embodiment of the present disclosure.
  • 2A-2E are process cross-sectional schematic diagrams of a semiconductor structure preparation method provided by a specific embodiment of the present disclosure.
  • 3A-3B are schematic cross-sectional views of a process for forming a substrate pattern according to an embodiment of the present disclosure.
  • 4A-4B are schematic cross-sectional views of a process for forming semiconductor pillars according to an embodiment of the present disclosure.
  • 5A-5E are schematic cross-sectional views of a process for forming a surrounding gate structure according to an embodiment of the present disclosure.
  • 6A-6B are schematic cross-sectional views of main processes in the process of forming a magnetic tunnel junction according to an embodiment of the present disclosure.
  • FIG. 1 is a schematic diagram of the steps of a method for manufacturing a semiconductor structure provided by a specific embodiment of the present disclosure.
  • the semiconductor structure preparation method includes the following steps: Step S10, providing a substrate 20; Step S11, forming a base pattern 21 on the substrate 20.
  • the base pattern 21 includes a plurality of parallel-arranged Bit lines 211 are provided with isolation structures 212 between the bit lines; step S12, a plurality of semiconductor pillars 22 arranged along the bit line direction are formed on the bit line surface 211, and the bit lines 211 are connected to the bit lines 211.
  • the semiconductor pillars 22 are electrically connected; step S13, a surrounding gate structure 23 is formed on the surface of the semiconductor pillar 22.
  • the surrounding gate structure 23 includes a first insulating layer 231, a gate and Structural layer 232 and second insulating layer 233, the gate structural layer 232 is electrically connected to the semiconductor pillar 22; step S14, forming sequentially stacked first conductors 24 and magnetic tunnel junctions on the surface of the surrounding gate structure 23 25 and a second wire 26, the first wire 24 is electrically connected to the semiconductor pillar 22.
  • FIGS. 2A-2E are process cross-sectional schematic diagrams of a semiconductor structure preparation method provided by a specific embodiment of the present disclosure.
  • a substrate 20 is provided.
  • the substrate 20 includes a first substrate 201 and a second substrate 202 .
  • the conductivity type of the substrate 201 may be N-type or P-type.
  • the substrate 201 is a P-type single crystal silicon substrate and is provided with a logic circuit;
  • the second substrate 202 is an injection laser diode (ILD).
  • ILD injection laser diode
  • a base pattern 21 is formed on the substrate 20 .
  • the base pattern 21 includes a plurality of bit lines 211 arranged in parallel, and an isolation structure 212 is provided between the bit lines.
  • FIG. 3A-FIG. 3B are schematic cross-sectional views of a process for forming the base pattern provided by a specific embodiment of the present disclosure.
  • an isolation layer 210 is formed on the surface of the substrate 20 .
  • the isolation layer may be made of insulating material, such as oxide, nitride, etc.
  • the isolation layer is made of silicon dioxide.
  • the isolation layer 210 is patterned to form an isolation structure 212 .
  • the isolation structure 212 includes a plurality of parallel-arranged strip grooves 213 .
  • the isolation layer 210 may be patterned using a combination of photolithography and etching processes.
  • the isolation structure 212 is electrically isolated from the bit lines.
  • a bit line 211 is formed in the strip groove 213 ; in a specific embodiment of the present disclosure, a first metal silicide layer 214 (not shown) is formed on the surface of the bit line 211 .
  • the metal silicide used may include any metal capable of forming silicide, including but not limited to cobalt, nickel, molybdenum, titanium, tungsten, tantalum, platinum, and combinations of these materials.
  • the metal silicide includes, but is not limited to, cobalt silicide, Tantalum silicide, nickel silicide, titanium silicide, tungsten silicide, etc.
  • the metal silicide may also include, for example, a combination of silicides doped with nitrogen, such as cobalt silicide nitride, tungsten silicide nitride, or a tungsten silicide nitride/tungsten silicide combination.
  • the first metal silicide layer 214 can reduce the contact resistance between metal and silicon and improve the conductivity between the bit line 211 and the semiconductor pillar 22 .
  • an air gap is formed on the side wall of the bit line 221.
  • Forming the bit line in the strip groove includes: forming a sacrificial layer on the side wall of the strip groove; filling the said strip groove with a metal material. Strip groove; remove the sacrificial layer to form an air gap.
  • the air gap can reduce the parasitic capacitance between the bit lines 221 and improve the electrical isolation effect between the bit lines and the isolation structure, which is beneficial to improving the efficiency of the semiconductor device and reducing energy consumption.
  • a plurality of semiconductor pillars 22 arranged along the bit line direction are formed on the surface of the bit line 211.
  • the bit line 211 is electrically connected to the semiconductor pillars 22.
  • FIG. 2C in order to clearly show the structure of the semiconductor device, only the cross-sections of the two semiconductor pillars 22 are schematically shown.
  • This embodiment provides a method of forming the semiconductor pillar 22 .
  • 4A-4B are schematic cross-sectional views of a process for forming semiconductor pillars according to an embodiment of the present disclosure.
  • an oxide semiconductor layer 220 is formed on the surface of the bit line 211 .
  • a protective layer 224 is formed on the surface of the oxide semiconductor layer 220 .
  • This step is an optional step and plays a role in protecting the top of the semiconductor pillar 22 from being etched in subsequent processes.
  • the oxide semiconductor layer 220 and the protective layer 224 are patterned to form a plurality of semiconductor pillars 22 arranged along the bit line direction.
  • the patterned semiconductor pillars 22 are provided on the top surface.
  • the protective layer 224 is also patterned.
  • the semiconductor pillar 22 includes a first source and drain region 221 at the bottom, a channel region 222 in the middle, and a second source and drain region 223 at the top; the first source and drain region 221 and the second source-drain region 223 are formed by doping with a first-type dopant, and the channel region 222 is formed by doping with a second-type dopant; the first source-drain region 221 and the second source-drain region 223 They are respectively parallel to or partially overlapped with the lower surface and the upper surface of the gate structure layer 232 .
  • the semiconductor pillar 22 and the surrounding gate structure 23 together form a vertical transistor.
  • the first source-drain region 221, the channel region 222, and the second source-drain region 223 are only used to distinguish the functions of different regions of the semiconductor pillar 22 in the semiconductor structure, and are not substantial structural differences, that is,
  • the vertical transistor is a vertical junctionless transistor.
  • the first source-drain region 221 , the channel region 222 , and the second source-drain region 223 have the same doping type, and the doping concentrations of the first source-drain region 221 and the second source-drain region 223 are greater than the channel region 222 .
  • semiconductor devices as the level of integration increases, their size further shrinks, resulting in a reduction in the area of the source, drain and channel regions.
  • the source and drain are doped
  • the control difficulty increases, and it becomes increasingly difficult to form a PN junction between the source, drain and channel regions.
  • the preparation method of the disclosed semiconductor structure can prepare vertical junctionless transistors whose source, drain and channel regions have the same doping type and no PN junction is formed, thereby avoiding the threshold voltage caused by doping mutations. Issues such as drift and increased leakage current.
  • the junctionless transistor can suppress the short channel effect and can still work at several nanometer sizes, which can further improve the integration and performance of 4F2 MRAM memory.
  • the vertical junctionless transistor formed in this step is a full-all-around gate field effect vertical junctionless transistor, which allows for more complete depletion in the second region 212, and due to the steeper sub-threshold current swing (SS) and Smaller drain-induced barrier lowering (DIBL) produces less short-channel effects.
  • SS sub-threshold current swing
  • DIBL Smaller drain-induced barrier lowering
  • a surrounding gate structure 23 is formed on the surface of the semiconductor pillar 22.
  • the surrounding gate structure 23 includes a first insulating layer 231, a gate, and a first insulating layer 231 sequentially provided on the side of the semiconductor pillar 22.
  • the gate structural layer 232 is electrically connected to the semiconductor pillar 22.
  • This embodiment also provides a method of forming the surrounding gate structure 23 .
  • 5A-5E are schematic cross-sectional views of a process for forming a surrounding gate structure according to an embodiment of the present disclosure.
  • a first insulating layer 231 is formed on the surface of the bit line 211 and the isolation structure 212 , and the first insulating layer 231 surrounds the bottom of the semiconductor pillar 22 . That is, the first insulating layer 231 surrounds the first source and drain regions 221 of the semiconductor pillar 22 .
  • the material of the first insulating layer 231 includes but is not limited to an oxide layer.
  • a gate dielectric layer 234 is formed, and the gate dielectric layer 234 covers the exposed portion of the semiconductor pillar 22 . That is, the gate dielectric layer 234 covers the channel region 222 and the second source and drain region 223 of the semiconductor pillar 22 .
  • a primary conductive layer 236 is formed on the surface of the first insulating layer 231 and the gate dielectric layer 234 .
  • the material of the primary conductive layer 236 may be polysilicon (poly), TiN, TaN, Al, W, Cu, etc.
  • the primary conductive layer 236 is patterned to form a plurality of gate conductive layers 235 extending along the vertical direction of the bit line.
  • a gate conductive layer 235 is formed on the surface of the first insulating layer 231 and the side surface of the gate dielectric layer 234 .
  • the gate dielectric layer 234 and the gate conductive layer 235 together serve as the gate structure layer 232 . That is, the gate structure layer 232 also extends along the vertical direction of the bit line.
  • a second insulating layer 233 is formed on the surface of the gate conductive layer 235 , and the second insulating layer 233 fills the gaps between the semiconductor pillars 22 .
  • the second insulating layer 233 covers the exposed portion of the gate dielectric layer 234 .
  • the following steps are included: performing metal ion implantation on the semiconductor pillar to form a second metal silicide layer 226 .
  • the second metal silicide layer 226 can reduce the contact resistance between the metal and silicon and improve the conductivity between the semiconductor pillar 22 and the first wire 24 .
  • the second metal silicide layer 226 includes, but is not limited to, cobalt silicide, tantalum silicide, nickel silicide, titanium silicide, tungsten silicide, etc.
  • forming the second metal silicide layer includes the following steps: removing the patterned protective structure 225 on the top surface of the semiconductor pillar 22 , this step is an optional step; Deposit a metal layer; perform high-temperature annealing on the metal layer, and form a second metal silicide layer 226 between the metal layer and the top of the semiconductor pillar. In the high-temperature annealing process, the metal is directly contacted with the silicon layer in the semiconductor pillar and converted into metal silicide.
  • step S14 and FIG. 2E Please continue to refer to step S14 and FIG. 2E to form a sequentially stacked first conductor 24 , a magnetic tunnel junction 25 and a second conductor 26 on the surface of the surrounding gate structure 23 .
  • the first conductor 24 and the semiconductor pillar 22 Electrical connection.
  • FIGS. 6A-6B are schematic cross-sectional views of main processes in the process of forming a magnetic tunnel junction according to an embodiment of the present disclosure.
  • a first conductive line layer 240 is formed on the surrounding gate structure.
  • the first conductive line layer 240 includes a plurality of mutually independent first conductive lines 24 and is disposed adjacent to the first conductive lines 24 . 24, the first conductor 24 is electrically connected to the semiconductor pillar 22.
  • a magnetic tunnel junction layer 250 is formed on the first conductor layer 240 .
  • the magnetic tunnel junction layer 250 includes a plurality of mutually independent magnetic tunnel junctions 25 .
  • the magnetic tunnel junctions 25 are connected to the first conductor layer 240 . Wire electrical 24 connections.
  • a second conductor layer 260 is formed on the magnetic tunnel junction layer 250.
  • the second conductor layer 260 includes a plurality of mutually independent second conductors 26 and is disposed between the adjacent second conductors 26.
  • the second spacer 266 is electrically connected to the magnetic tunnel junction 25 , and the second spacer 266 fills the gap between the magnetic tunnel junctions 25 .
  • This embodiment also enumerates a method of forming the first conductive layer 240.
  • the method includes the following steps: forming a first spacer layer 241 on the surrounding gate structure 23; patterning the first spacer layer 241 to form a plurality of via holes, and the via holes expose the tops of the semiconductor pillars 22; Form a first contact structure 242 in the via hole; form a first conductive layer 243 on the first spacer layer 241 and the first contact structure 242; pattern the first conductive layer 243 to form several
  • the first sub-conductor 244 is electrically connected to the first contact structure 242 and together serves as the first conductor 24; a second spacer layer 245 is formed, and the second spacer layer 245 fills the In the gap between the first sub-conductors 244 , the first spacer layer 241 and the second spacer layer 245 together serve as the first spacer 246 .
  • the first contact structure 242 is electrically connected to the second metal silicide layer 226 on the second source and drain region 223 on the top of the semiconductor pillar 22 .
  • the width of the first contact structure 242 is smaller than the width of the first sub-conductor 244 .
  • the first contact structure 242 serves as a connection pad to electrically connect the first sub-conductor 244 to the second source-drain region 223 on the top of the semiconductor pillar 22 .
  • This embodiment also enumerates a method of forming the magnetic tunnel junction layer 250, which further includes: forming a primary fixed layer 251 on the first wire layer 240; forming a primary non-magnetic insulating layer 252 on the primary fixed layer 251.
  • the magnetic tunnel junction 25 includes a fixed layer 254, a non-magnetic insulating layer 255 and a free layer 256 arranged in sequence, wherein the direction of the magnetic moment of the free layer 256 is variable, and the direction of the magnetic moment of the fixed layer 254 is fixed. Based on the tunnel magnetoresistance effect, the resistance value between the fixed layer 254 and the free layer 256 changes as the magnetization polarity switches in the free layer 256, thereby realizing the read and write operations of the magnetic tunnel junction unit.
  • This embodiment also enumerates a method of forming the second conductor layer 260, further including: forming a third spacer layer 261, the third spacer layer 261 fills between the magnetic tunnel junctions 25 and covers the magnetic tunnel junction layer. 250; Form a via hole that penetrates the third spacer layer 261, and the via hole exposes the magnetic tunnel junction 25; Form a second contact structure 262 in the via hole; In the third spacer layer 261 and A second conductive layer 263 is formed on the second contact structure 262; the second conductive layer 263 is patterned to form a plurality of second sub-conductors 264, and the second contact structure 262 is electrically connected to the second sub-conductors 264.
  • the fourth spacer layer 265 fills the gap between the second sub-conductors 264, the third spacer layer 261 and the fourth The spacer layers 264 collectively serve as the second spacers 266 .
  • the second contact structure 262 is electrically connected to the free layer 256 of the magnetic tunnel junction 25 .
  • the width of the first contact structure 242 is smaller than the width of the second sub-conductor 264 .
  • the second contact structure 262 serves as a connection pad to electrically connect the second sub-conductor 264 to the free layer 256 of the magnetic tunnel junction 25 .
  • the above method can form a semiconductor device composed of a vertical junctionless transistor and a magnetic tunnel junction unit, avoiding problems such as threshold voltage drift and increase in leakage current caused by doping mutations.
  • the junctionless transistor can suppress the short channel effect. It can still work at several nanometer dimensions, which can further improve the integration and performance of memory.
  • the present disclosure also provides a semiconductor structure. See Figure 2E.
  • the semiconductor structure includes: a substrate 20; bit lines 211, which are arranged on the surface of the substrate 20, and a plurality of bit lines 20 are arranged in parallel; semiconductor pillars 22, which are arranged on the surface of the bit lines 211 and along the bit lines Arranged in the direction, the semiconductor pillar 22 is electrically connected to the bit line 211; a surrounding gate structure 23, the surrounding gate structure 23 includes a first insulating layer 231, The gate structure layer 232 and the second insulating layer 233; the first conductor 24, the magnetic tunnel junction 25 and the second conductor 26 are sequentially arranged on the surface of the surrounding gate structure 23.
  • the first conductor 24 and the semiconductor pillar 22 electrical connections.
  • the semiconductor pillar 22 includes a first source and drain region 221 at the bottom, a channel region 222 in the middle, and a second source and drain region 223 at the top; the first source and drain region 221 and the second source and drain region 223 It is formed by doping with a first type dopant, and the channel region 222 is formed by doping with a second type dopant; the first source and drain regions 221 and the second source and drain regions 223 are respectively connected with the gate structure layer.
  • the lower surface and the upper surface of 232 are parallel or partially overlapped.
  • the first source-drain region 221, the channel region 222, and the second source-drain region 223 are only used to distinguish the functions of different regions of the semiconductor pillar 22 in the semiconductor structure, and are not substantial structural differences, that is,
  • the vertical transistor is a vertical junctionless transistor.
  • the disclosed semiconductor structure adopts a vertical junctionless transistor, and the doping types of its source region, drain region and channel region are consistent, and no PN junction is formed, thereby avoiding the threshold voltage drift and increase in leakage current caused by doping mutations. And other issues.
  • the junctionless transistor can suppress the short channel effect and can still work at several nanometer sizes, which can further improve the integration and performance of 4F2 MRAM memory.
  • the gate structure layer 232 includes: a gate dielectric layer 234 disposed on the side of the semiconductor pillar 22; a gate conductive layer 235 disposed between the first insulating layer 231 and the second insulating layer 233 and covering The gate dielectric layer 234 surrounds the side surfaces of the semiconductor pillar 22 , and the gate conductive layer 235 extends along the vertical direction of the bit line 211 .
  • the magnetic tunnel junction 25 includes a fixed layer 254, a non-magnetic insulating layer 255 and a free layer 256 arranged in sequence, wherein the direction of the magnetic moment of the free layer 256 is variable, and the direction of the magnetic moment of the fixed layer 254 is fixed. . Based on the tunnel magnetoresistance effect, the resistance value between the fixed layer 254 and the free layer 256 changes as the magnetization polarity switches in the free layer 256, thereby realizing the read and write operations of the magnetic tunnel junction unit.
  • the surface of the bit line 211 includes a first metal silicide layer (not shown).
  • An air gap (not shown) is formed on the sidewall of the bit line 211 .
  • the top of the semiconductor pillar 22 has a second metal silicide layer 226 .
  • the metal silicide layer can reduce the contact resistance between metal and silicon. That is, the first metal silicide layer 214 can improve the electrical conductivity between the bit line 211 and the semiconductor pillar 22 ; the second metal silicide layer 226 can improve the electrical conductivity between the semiconductor pillar 22 and the first conductive line 24 .
  • the semiconductor structure provided by the embodiments of the present disclosure is composed of a vertical junctionless transistor and a magnetic tunnel junction unit, which avoids problems such as threshold voltage drift and increase in leakage current caused by doping mutations.
  • the junctionless transistor can suppress short channels. The effect can still work at several nanometer dimensions, which can further improve memory integration and performance.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Geometry (AREA)
  • Semiconductor Memories (AREA)
  • Mram Or Spin Memory Techniques (AREA)

Abstract

本公开提供一种半导体结构及其制备方法。本公开提供的半导体结构的制备方法包括如下步骤：提供衬底；于所述衬底上形成基底图案，所述基底图案包括多个平行排布的位线，在所述位线之间设置有隔离结构；在所述位线表面形成多个沿位线方向排布的半导体柱，所述位线与所述半导体柱电连接；于所述半导体柱表面形成环绕式栅极结构，所述环绕式栅极结构包括于所述半导体柱侧面依次设置的第一绝缘层、栅结构层及第二绝缘层，所述栅结构层与所述半导体柱电连接；于所述环绕式栅极结构表面形成依次堆叠的第一导线、磁隧道结以及第二导线，所述第一导线与所述半导体柱电连接。极大的改善了半导体结构的性能，满足小型化的要求。

Description

半导体结构及其制备方法
相关申请引用说明
本申请要求于2022年3月10日递交的中国专利申请号202210235558.2、申请名为“半导体结构及其制备方法”的优先权，其全部内容以引用的形式附录于此。
技术领域
本公开涉及半导体领域，尤其涉及一种半导体结构及其制备方法。
背景技术
对具有高性能的廉价半导体结构的需求推动集成密度，反过来，增加的集成密度对半导体制造工艺提出了更高的要求。
二维(2D)或平面型半导体结构的集成密度部分地由构成组成集成电路的各个元件(例如，存储器单元)占据的面积确定。各个元件占据的面积很大程度上由用于定义各个元件及其互连的图案化技术的尺寸参数(例如，宽度，长度，间距，窄度，相邻间隔等)确定。而提供越来越“精细”的图案需要开发和使用非常昂贵的图案形成设备。
随着半导体工业在追求更高的器件密度、更高的性能和更低的成本的过程中进入纳米技术工艺节点，来自制造和设计问题的挑战引起了诸如全环栅场效应晶体管(GAA FET)的三维设计的发展。
在全环栅场效应晶体管中，沟道区域的所有侧面都由栅电极包围，这允许沟道区域中更充分的耗尽，并且由于较陡的亚阈值电流摆幅(SS)和较小的漏致势垒降低(DIBL)而产生较少的短沟道效应。
随着晶体管尺寸不断缩小至10-15nm以下的技术节点，需要对具有全环栅场效应晶体管的半导体结构进行进一步的改进，以满足需求。
发明内容
本公开所要解决的技术问题是，提供一种半导体结构及其制备方法，以满足提高半导体结构性能和小型化的需求。
本公开提供一种半导体结构的制备方法，包括如下步骤：提供衬底；于所述衬底上形成基底图案，所述基底图案包括多个平行排布的位线，在所述位线之间设置有隔离结构；在所述位线表面形成多个沿位线方向排布的半导体柱，所述位线与所述半导体柱电连接； 于所述半导体柱表面形成环绕式栅极结构，所述环绕式栅极结构包括于所述半导体柱侧面依次设置的第一绝缘层、栅结构层及第二绝缘层，所述栅结构层与所述半导体柱电连接；于所述环绕式栅极结构表面形成依次堆叠的第一导线、磁隧道结以及第二导线，所述第一导线与所述半导体柱电连接。
本公开还提供了一种半导体结构，其中，包括：衬底；位线，设置在所述衬底表面，且多个位线平行排布；半导体柱，设置在所述位线表面且沿位线方向排布，所述半导体柱与所述位线电连接；环绕式栅极结构，所述环绕式栅极结构包括于所述半导体柱侧面依次设置的第一绝缘层、栅结构层及第二绝缘层；第一导线、磁隧道结以及第二导线，依次设置在所述环绕式栅极结构表面，所述第一导线与所述半导体柱电连接。
本公开通过提供一种半导体结构及其制备方法，其能够在衬底内形成埋入式位线，并形成垂直晶体管及位于所述垂直晶体管上的磁隧道结区，大大改善了现有的半导体结构的性能，满足小型化的需求。
本公开的另一优点在于，本公开半导体器件的制备方法能够制备垂直无结晶体管，其源极区、漏极区和沟道区的掺杂类型一致，不再形成PN结，因而避免了掺杂突变所产生的阈值电压漂移和漏电流增加等问题。同时，无结晶体管可以抑制短沟道效应，在几个纳米尺寸下仍然可以工作，可以进一步提高存储器的集成度和性能。
附图说明
图1为本公开一具体实施方式提供的半导体结构制备方法的步骤示意图。
图2A-2E为本公开一具体实施方式提供的半导体结构制备方法的工艺截面示意图。
图3A-3B为本公开一具体实施方式提供的形成基底图案的工艺截面示意图。
图4A-4B为本公开一具体实施方式提供的形成半导体柱的工艺截面示意图。
图5A-5E为本公开一具体实施方式提供的形成环绕式栅极结构的工艺截面示意图。
图6A-6B为本公开一具体实施方式提供的形成磁隧道结的过程中主要的工艺截面示意图。
具体实施方式
下面结合附图对本公开提供的半导体结构及其制备方法的具体实施方式做详细说明。
图1为本公开一具体实施方式提供的半导体结构制备方法的步骤示意图。请参阅图1， 所述半导体结构制备方法包括如下步骤：步骤S10，提供衬底20；步骤S11，于所述衬底20上形成基底图案21，所述基底图案21包括多个平行排布的位线211，在所述位线之间设置有隔离结构212；步骤S12，在所述位线表211面形成多个沿位线方向排布的半导体柱22，所述位线211与所述半导体柱22电连接；步骤S13，于所述半导体柱22表面形成环绕式栅极结构23，所述环绕式栅极结构23包括于所述半导体柱22侧面依次设置的第一绝缘层231、栅结构层232及第二绝缘层233，所述栅结构层232与所述半导体柱22电连接；步骤S14，于所述环绕式栅极结构23表面形成依次堆叠的第一导线24、磁隧道结25以及第二导线26，所述第一导线24与所述半导体柱22电连接。
图2A-2E为本公开一具体实施方式提供的半导体结构制备方法的工艺截面示意图。请参阅步骤S10及图2A，提供衬底20。所述衬底20包括第一衬底201和第二衬底202。所述衬底201的导电类型可为N型或者P型。在本实施例中，所述衬底201为P型单晶硅衬底，并设置有逻辑电路；所述第二衬底202采用注入式激光二极管(ILD)。
请参阅步骤S11及图2B，于所述衬底20上形成基底图案21，所述基底图案21包括多个平行排布的位线211，在所述位线之间设置有隔离结构212。
本实施例列举了一种形成所述基底图案的方法，图3A-图3B为本公开一具体实施方式提供的形成基底图案的工艺截面示意图。
请参阅图3A，在衬底20表面形成隔离层210。所述隔离隔离层可采用绝缘材料，例如氧化物、氮化物等，在本实施例中，所述隔离层采用二氧化硅。
请参阅图3B，图案化所述隔离层210，形成隔离结构212，所述隔离结构212包括多个平行排布的条形凹槽213。在该步骤中，可采用光刻与刻蚀工艺结合的方式图案化所述隔离层210。所述隔离结构212与位线形成电隔离。
请参阅图2B，在所述条形凹槽213内形成位线211；在本公开的一种具体实施方式中，在所述位线211表面形成第一金属硅化物层214(未示出)。所采用的金属硅化物可包括能够形成硅化物的任何金属，包括但不限于钴、镍、钼、钛、钨、钽、铂、以及这些材料的组合，金属硅化物包括但不限于硅化钴、硅化钽、硅化镍、硅化钛、硅化钨等。另外，金属硅化物还可以包括例如掺杂有氮的硅化物的组合，例如氮硅化钴、氮硅化钨或氮硅化钨/硅化钨的组合。所述第一金属硅化物层214能够降低金属与硅之间的接触电阻，提升位线211与半导体柱22之间的导电能力。
在一些实施例中，所述位线221侧壁形成有空气间隙，在所述条形凹槽内形成位线包 括：在所述条形凹槽侧壁形成牺牲层；采用金属材料填充所述条形凹槽；去除所述牺牲层，形成空气间隙。空气间隙能够减少位线221之间的寄生电容，提升位线与隔离结构的电隔离效果，有利于提高半导体器件的效率，降低能耗。
请继续参阅步骤S12及图2C，在所述位线211表面形成多个沿位线方向排布的半导体柱22，所述位线211与所述半导体柱22电连接。在图2C中，为了清楚显示半导体器件的结构，仅示意性地绘示两个半导体柱22的截面。
本实施例提供一种形成所述半导体柱22的方法。图4A-图4B为本公开一具体实施方式提供的形成半导体柱的工艺截面示意图。
请参阅附图4A，在所述位线211表面形成氧化物半导体层220。
请参阅附图4B，在所述氧化物半导体层220表面形成保护层224。该步骤为可选步骤，在后续工艺中起到保护半导体柱22的顶端不被刻蚀的作用。
请参阅附图2C，图案化所述氧化物半导体层220和保护层224，以形成多个沿位线方向排布的半导体柱22，所述半导体柱22的顶面设置有所述图案化的保护结构225。可选地，在本实施例中，所述保护层224也被图案化。
在本公开一具体实施方式中，所述半导体柱22包括位于底部的第一源漏区221、中部的沟道区222、以及顶部的第二源漏区223；所述第一源漏区221和第二源漏区223采用第一型掺杂剂掺杂形成，所述沟道区222采用第二型掺杂剂掺杂形成；所述第一源漏区221和第二源漏区223分别与所述栅结构层232的下表面和上表面平行或部分重叠。所述半导体柱22与环绕式栅极结构23共同构成垂直晶体管。
其中，所述第一源漏区221、沟道区222、以及第二源漏区223仅是为了区分所述半导体柱22的不同区域在半导体结构中的功能，而并非是实质结构区别，即所述垂直晶体管为垂直无结晶体管。第一源漏区221、沟道区222、以及第二源漏区223的掺杂类型一致，且第一源漏区221和第二源漏区223的掺杂浓度大于沟道区222。对于半导体器件而言，随着集成度的增大，其尺寸进一步缩小，使得源极、漏极和沟道区域的面积缩小，在形成传统的PN结晶体管时，对源极和漏极掺杂的控制难度增加，在源极、漏极和沟道区域之间形成PN结变得越来越困难。而本公开半导体结构的制备方法能够制备垂直无结晶体管，其源极区、漏极区和沟道区的掺杂类型一致，不再形成PN结，因而避免了掺杂突变所产生的阈值电压漂移和漏电流增加等问题。同时，无结晶体管可以抑制短沟道效应，在几个纳米尺寸下仍然可以工作，可进一步提高4F2 MRAM存储器的集成度和性能。
进一步，在该步骤中形成的垂直无结晶体管为全环栅场效应垂直无结晶体管，其允许第二区212中更充分的耗尽，并且由于较陡的亚阈值电流摆幅(SS)和较小的漏致势垒降低(DIBL)而产生较少的短沟道效应。
请继续参阅步骤S13及图2D，于所述半导体柱22表面形成环绕式栅极结构23，所述环绕式栅极结构23包括于所述半导体柱22侧面依次设置的第一绝缘层231、栅结构层232及第二绝缘层233，所述栅结构层232与所述半导体柱22电连接。
本实施例还提供一种形成所述环绕式栅极结构23的方法。图5A-5E为本公开一具体实施方式提供的形成环绕式栅极结构的工艺截面示意图。
请参阅图5A，于所述位线211及所述隔离结构212表面形成第一绝缘层231，所述第一绝缘层231包围所述半导体柱22的底部。即所述第一绝缘层231包围所述半导体柱22的所述第一源漏区221。所述第一绝缘层231的材料包括但不限于氧化物层。
请参阅图5B，形成栅介质层234，所述栅介质层234覆盖所述半导体柱22裸露部分。即所述栅介质层234覆盖所述半导体柱22的沟道区222和第二源漏区223。
请参阅图5C，于所述第一绝缘层231表面及所述栅介质层234表面形成初级导电层236。所述初级导电层236的材料可为多晶硅(poly)、TiN，TaN，Al，W，Cu等。
请参阅图5D，图案化所述初级导电层236，形成多个沿位线垂直方向延伸的所述栅导电层235。于所述第一绝缘层231表面及所述栅介质层234侧面形成栅导电层235，所述栅介质层234与所述栅导电层235共同作为所述栅结构层232。即所述栅结构层232也沿位线垂直方向延伸。
请参阅附图5E，于所述栅导电层235表面形成第二绝缘层233，所述第二绝缘层233填充所述半导体柱22之间的空隙。所述第二绝缘层233包覆所述栅介质层234的露出部分。
请参阅图2D，于所述半导体柱22表面形成环绕式栅极结构23之后，包括如下步骤：对所述半导体柱进行金属离子注入，形成第二金属硅化物层226。
所述第二金属硅化物层226能够降低金属与硅之间的接触电阻，提升半导体柱22与第一导线24之间的导电能力。第二金属硅化物层226包括但不限于硅化钴、硅化钽、硅化镍、硅化钛、硅化钨等。
在一实施例中，所述形成第二金属硅化物层包括如下步骤：去除所述半导体柱22的顶面的图案化的保护结构225，该步骤为可选步骤；在所述半导体柱22顶端沉积金属层；对 所述金属层进行高温退火，所述金属层与所述半导体柱顶端形成第二金属硅化物层226。高温退火工艺中使金属与半导体柱中的硅层直接接触转化为金属硅化物。
请继续参阅步骤S14及图2E，于所述环绕式栅极结构23表面形成依次堆叠的第一导线24、磁隧道结25以及第二导线26，所述第一导线24与所述半导体柱22电连接。
图6A-6B为本公开一具体实施方式提供的形成磁隧道结的过程中主要的工艺截面示意图。请参阅图6A，于所述环绕式栅极结构上形成第一导线层240，所述第一导线层240包括若干个彼此独立的所述第一导线24及设置在相邻所述第一导线24之间的第一间隔物246，所述第一导线24与所述半导体柱22电连接。
请参阅图6B，于所述第一导线层240上形成磁隧道结层250，所述磁隧道结层250包括若干个彼此独立的磁隧道结25，所述磁隧道结25与所述第一导线电24连接。
请参阅图2E，于所述磁隧道结层250上形成第二导线层260，所述第二导线层260包括若干个彼此独立的第二导线26及设置在相邻所述第二导线26之间的第二间隔物266，所述第二导线26与所述磁隧道结25电连接，且所述第二间隔物266填充所述磁隧道结25之间的间隙。
本实施例还列举了一种形成第一导线层240的方法。包括如下步骤：于所述环绕式栅极结构23上形成第一间隔层241；图案化所述第一间隔层241，形成若干个过孔，所述过孔暴露所述半导体柱22的顶部；于所述过孔内形成第一接触结构242；于所述第一间隔层241及所述第一接触结构242上形成第一导电层243；图案化所述第一导电层243，形成若干个第一子导线244，所述第一子导线244与所述第一接触结构242电连接，共同作为所述第一导线24；形成第二间隔层245，所述第二间隔层245填充所述第一子导线244之间的间隙，所述第一间隔层241与所述第二间隔层245共同作为所述第一间隔物246。
其中，进一步，在本实施例中，所述第一接触结构242与所述半导体柱22顶部第二源漏区223上的第二金属硅化物层226电连接。所述第一接触结构242的宽度小于所述第一子导线244的宽度。所述第一接触结构242作为连接垫将所述第一子导线244与所述半导体柱22顶部第二源漏区223电连接。
本实施例还列举了一种形成磁隧道结层250的方法，进一步包括：于所述第一导线层240上形成初级固定层251；于所述初级固定层251上形成初级非磁性绝缘层252；于所述初级非磁性绝缘层252形成初级自由层253；图案化所述初级自由层253、初级非磁性绝缘层252及初级固定层251，形成若干个彼此独立的所述磁隧道结25，所述磁隧道结25包括 依次设置的固定层254、非磁性绝缘层255及自由层256，其中，所述自由层256的磁矩方向可变，所述固定层254的磁矩方向固定。基于隧道磁电阻效应，固定层254和自由层256之间的电阻值随着自由层256中的磁化极性切换而变化，从而实现磁隧道结单元的读写操作。
本实施例还列举了一种形成第二导线层260的方法，进一步包括：形成第三间隔层261，所述第三间隔层261填充磁隧道结25之间，且覆盖所述磁隧道结层250；形成贯穿所述第三间隔层261的过孔，所述过孔暴露出所述磁隧道结25；于所述过孔内形成第二接触结构262；于所述第三间隔层261及所述第二接触结构262上形成第二导电层263；图案化所述第二导电层263，形成若干个第二子导线264，所述第二接触结构262与所述第二子导线264电连接，共同作为所述第二导线26；形成第四间隔层265，所述第四间隔层265填充所述第二子导线264之间的间隙，所述第三间隔层261与所述第四间隔层264共同作为所述第二间隔物266。
其中，进一步，在本实施例中，所述第二接触结构262与所述磁隧道结25的自由层256电连接。所述第一接触结构242的宽度小于所述第二子导线264的宽度。所述第二接触结构262作为连接垫将所述第二子导线264与所述磁隧道结25的自由层256电连接。
上述方法能够形成由垂直无结晶体管与磁隧道结单元构成的半导体器件，避免了掺杂突变所产生的阈值电压漂移和漏电流增加等问题，同时，无结晶体管可以抑制短沟道效应，在几个纳米尺寸下仍然可以工作，可以进一步提高存储器的集成度和性能。
本公开还提供一种半导体结构。请参阅图2E。所述半导体结构，包括：衬底20；位线211，设置在所述衬底20表面，且多个位线20平行排布；半导体柱22，设置在所述位线211表面且沿位线方向排布，所述半导体柱22与所述位线211电连接；环绕式栅极结构23，所述环绕式栅极结构23包括于所述半导体柱22侧面依次设置的第一绝缘层231、栅结构层232及第二绝缘层233；第一导线24、磁隧道结25以及第二导线26，依次设置在所述环绕式栅极结构23表面，所述第一导线24与所述半导体柱22电连接。
进一步，所述半导体柱22包括位于底部的第一源漏区221、中部的沟道区222、以及顶部的第二源漏区223；所述第一源漏区221和第二源漏区223采用第一型掺杂剂掺杂形成，所述沟道区222采用第二型掺杂剂掺杂形成；所述第一源漏区221和第二源漏区223分别与所述栅结构层232的下表面和上表面平行或部分重叠。
其中，所述第一源漏区221、沟道区222、以及第二源漏区223仅是为了区分所述半导 体柱22的不同区域在半导体结构中的功能，而并非是实质结构区别，即所述垂直晶体管为垂直无结晶体管。本公开半导体结构采用垂直无结晶体管，其源极区、漏极区和沟道区的掺杂类型一致，不再形成PN结，因而避免了掺杂突变所产生的阈值电压漂移和漏电流增加等问题。同时，无结晶体管可以抑制短沟道效应，在几个纳米尺寸下仍然可以工作，可进一步提高4F2 MRAM存储器的集成度和性能。
进一步，所述栅结构层232包括：栅介质层234，设置在所述半导体柱22的侧面；栅导电层235，设置在所述第一绝缘层231与第二绝缘层233之间，且覆盖所述栅介质层234侧面，并包围所述半导体柱22的侧面，所述栅导电层235沿位线211垂直方向延伸。
进一步，所述磁隧道结25包括依次设置的固定层254、非磁性绝缘层255及自由层256，其中，所述自由层256的磁矩方向可变，所述固定层254的磁矩方向固定。基于隧道磁电阻效应，固定层254和自由层256之间的电阻值随着自由层256中的磁化极性切换而变化，从而实现磁隧道结单元的读写操作。
在本公开的一种具体实施方式中，所述位线211表面包括第一金属硅化物层(未示出)。所述位线211侧壁形成有空气间隙(未示出)。所述半导体柱22的顶端具有第二金属硅化物层226。金属硅化物层能够降低金属与硅之间的接触电阻。即所述第一金属硅化物层214，能够提升位线211与半导体柱22之间的导电能力；所述第二金属硅化物层226能够提升半导体柱22与第一导线24之间的导电能力。
本公开实施例提供的半导体结构，其由垂直无结晶体管与磁隧道结单元构成，避免了掺杂突变所产生的阈值电压漂移和漏电流增加等问题，同时，无结晶体管可以抑制短沟道效应，在几个纳米尺寸下仍然可以工作，可以进一步提高存储器的集成度和性能。
本说明书中的各个具体实施方式均采用相关的方式描述，各个具体实施方式之间相同相似的部分互相参见即可，每个具体实施方式重点说明的都是与其他具体实施方式的不同之处。尤其，对于半导体结构具体实施方式而言，由于其基本相似于半导体结构的制备方法具体实施方式，所以描述的比较简单，相关之处参见半导体结构的制备方法具体实施方式的部分说明即可。
以上所述仅是本公开的优选实施方式，应当指出，对于本技术领域的普通技术人员，在不脱离本公开原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本公开的保护范围。

Claims (20)

  1. 一种半导体结构的制备方法，其中，包括如下步骤：
    提供衬底；
    于所述衬底上形成基底图案，所述基底图案包括多个平行排布的位线，在所述位线之间设置有隔离结构；
    在所述位线表面形成多个沿位线方向排布的半导体柱，所述位线与所述半导体柱电连接；
    于所述半导体柱表面形成环绕式栅极结构，所述环绕式栅极结构包括于所述半导体柱侧面依次设置的第一绝缘层、栅结构层及第二绝缘层，所述栅结构层与所述半导体柱电连接；
    于所述环绕式栅极结构表面形成依次堆叠的第一导线、磁隧道结以及第二导线，所述第一导线与所述半导体柱电连接。
  2. 根据权利要求1所述的半导体结构的制备方法，其中，所述半导体柱包括位于底部的第一源漏区、中部的沟道区、以及顶部的第二源漏区；
    所述第一源漏区和第二源漏区采用第一型掺杂剂掺杂形成，所述沟道区采用第二型掺杂剂掺杂形成；
    所述第一源漏区和第二源漏区分别与所述栅结构层的下表面和上表面平行或部分重叠。
  3. 根据权利要求1所述的半导体结构的制备方法，其中，在所述位线表面形成多个沿位线方向排布的半导体柱，包括：
    在所述位线表面形成氧化物半导体层；
    在所述氧化物半导体层表面形成保护层；
    图案化所述氧化物半导体层和保护层，以形成多个沿位线方向排布的半导体柱，所述半导体柱的顶面设置有所述图案化的保护结构。
  4. 根据权利要求1所述的半导体结构的制备方法，其中，于所述衬底上形成基底图案包括：
    在衬底表面形成隔离层；
    图案化所述隔离层，形成隔离结构，所述隔离结构包括多个平行排布的条形凹槽；
    在所述条形凹槽内形成位线；
    在所述位线表面形成第一金属硅化物层。
  5. 根据权利要求4所述的半导体结构的制备方法，其中，所述位线侧壁形成有空气间隙，在所述条形凹槽内形成位线包括：
    在所述条形凹槽侧壁形成牺牲层；
    采用金属材料填充所述条形凹槽；
    去除所述牺牲层，形成空气间隙。
  6. 根据权利要求1所述的半导体结构的制备方法，其中，于所述半导体柱表面形成环绕式栅极结构包括：
    于所述位线及所述隔离结构表面形成第一绝缘层，所述第一绝缘层包围所述半导体柱的底部；
    形成栅介质层，所述栅介质层覆盖所述半导体柱裸露部分；
    于所述第一绝缘层表面及所述栅介质层侧面形成栅导电层，所述栅介质层与所述栅导电层共同作为所述栅结构层；
    于所述栅导电层表面形成第二绝缘层，所述第二绝缘层填充所述半导体柱之间的空隙。
  7. 根据权利要求6所述的半导体结构的制备方法，其中，于所述第一绝缘层表面及所述栅介质层侧面形成栅导电层包括：
    于所述第一绝缘层表面及所述栅介质层表面形成初级导电层；
    图案化所述初级导电层，形成多个沿位线垂直方向延伸的所述栅导电层。
  8. 根据权利要求6所述的半导体结构的制备方法，其中，于所述半导体柱表面形成环绕式栅极结构之后，包括如下步骤：
    对所述半导体柱进行金属离子注入，形成第二金属硅化物层。
  9. 根据权利要求8所述的半导体结构的制备方法，其中，所述形成第二金属硅化物层包括如下步骤：
    去除所述半导体柱的顶面的图案化的保护结构；
    在所述半导体柱顶端沉积金属层；
    对所述金属层进行高温退火，所述金属层与所述半导体柱顶端形成第二金属硅化物层。
  10. 根据权利要求1所述的半导体结构的制备方法，其中，于所述环绕式栅极结构表面形成磁隧道结包括：
    于所述环绕式栅极结构上形成第一导线层，所述第一导线层包括若干个彼此独立的所述第一导线及设置在相邻所述第一导线之间的第一间隔物，所述第一导线与所述半导体柱电连接；
    于所述第一导线层上形成磁隧道结层，所述磁隧道结层包括若干个彼此独立的磁隧道 结，所述磁隧道结与所述第一导线电连接；
    于所述磁隧道结层上形成第二导线层，所述第二导线层包括若干个彼此独立的第二导线及设置在相邻所述第二导线之间的第二间隔物，所述第二导线与所述磁隧道结电连接，且所述第二间隔物填充所述磁隧道结间的间隙。
  11. 根据权利要求10所述的半导体结构的制备方法，其中，于所述环绕式栅极结构上形成第一导线层包括如下步骤：
    于所述环绕式栅极结构上形成第一间隔层；
    图案化所述第一间隔层，形成若干个过孔，所述过孔暴露所述半导体柱的顶部；
    于所述过孔内形成第一接触结构；
    于所述第一间隔层及所述第一接触结构上形成第一导电层；
    图案化所述第一导电层，形成若干个第一子导线，所述第一子导线与所述第一接触结构电连接，共同作为所述第一导线；
    形成第二间隔层，所述第二间隔层填充所述第一子导线之间的间隙，所述第一间隔层与所述第二间隔层共同作为所述第一间隔物。
  12. 根据权利要求10所述的半导体结构的制备方法，其中，于所述第一导线层上形成磁隧道结层包括：
    于所述第一导线层上形成初级固定层；
    于所述初级固定层上形成初级非磁性绝缘层；
    于所述初级非磁性绝缘层形成初级自由层；
    图案化所述初级自由层、初级非磁性绝缘层及初级固定层，形成若干个彼此独立的所述磁隧道结，所述磁隧道结包括依次设置的固定层、非磁性绝缘层及自由层，其中，所述自由层的磁矩方向可变，所述固定层的磁矩方向固定。
  13. 根据权利要求10所述的半导体结构的制备方法，其中，于所述磁隧道结层上形成第二导线层包括：
    形成第三间隔层，所述第三间隔层填充磁隧道结之间，且覆盖所述磁隧道结层；
    形成贯穿所述第三间隔层的过孔，所述过孔暴露出所述磁隧道结；
    于所述过孔内形成第二接触结构；
    于所述第三间隔层及所述第二接触结构上形成第二导电层；
    图案化所述第二导电层，形成若干个第二子导线，所述第二接触结构与所述第二子导线电连接，共同作为所述第二导线；
    形成第四间隔层，所述第四间隔层填充所述第二子导线之间的间隙，所述第三间隔层与所述第四间隔层共同作为所述第二间隔物。
  14. 一种半导体结构，其中，包括：
    衬底；
    位线，设置在所述衬底表面，且多个位线平行排布；
    半导体柱，设置在所述位线表面且沿位线方向排布，所述半导体柱与所述位线电连接；
    环绕式栅极结构，所述环绕式栅极结构包括于所述半导体柱侧面依次设置的第一绝缘层、栅结构层及第二绝缘层；
    第一导线、磁隧道结以及第二导线，依次设置在所述环绕式栅极结构表面，所述第一导线与所述半导体柱电连接。
  15. 根据权利要求14所述的半导体结构，其中，所述半导体柱包括位于底部的第一源漏区、中部的沟道区、以及顶部的第二源漏区；
    所述第一源漏区和第二源漏区采用第一型掺杂剂掺杂形成，所述沟道区采用第二型掺杂剂掺杂形成；
    所述第一源漏区和第二源漏区分别与所述栅结构层的下表面和上表面平行或部分重叠。
  16. 根据权利要求14所述的半导体结构，其中，所述栅结构层包括：
    栅介质层，设置在所述半导体柱的侧面；
    栅导电层，设置在所述第一绝缘层与第二绝缘层之间，且覆盖所述栅介质层侧面，并包围所述半导体柱的侧面，所述栅导电层沿位线垂直方向延伸。
  17. 根据权利要求14所述的半导体结构，其中，所述位线表面包括第一金属硅化物层。
  18. 根据权利要求14所述的半导体结构，其中，所述位线侧壁形成有空气间隙。
  19. 根据权利要求14所述的半导体结构，其中，所述半导体柱的顶端具有第二金属硅化物层。
  20. 根据权利要求14所述的半导体结构，其中，所述磁隧道结包括依次设置的固定层、非磁性绝缘层及自由层，其中，所述自由层的磁矩方向可变，所述固定层的磁矩方向固定。
PCT/CN2022/110753 2022-03-10 2022-08-08 半导体结构及其制备方法 WO2023168897A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US17/936,096 US20230292530A1 (en) 2022-03-10 2022-09-28 Semiconductor structure and manufacturing method thereof

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202210235558.2A CN114709168A (zh) 2022-03-10 2022-03-10 半导体结构及其制备方法
CN202210235558.2 2022-03-10

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US17/936,096 Continuation US20230292530A1 (en) 2022-03-10 2022-09-28 Semiconductor structure and manufacturing method thereof

Publications (1)

Publication Number Publication Date
WO2023168897A1 true WO2023168897A1 (zh) 2023-09-14

Family

ID=82168085

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2022/110753 WO2023168897A1 (zh) 2022-03-10 2022-08-08 半导体结构及其制备方法

Country Status (2)

Country Link
CN (1) CN114709168A (zh)
WO (1) WO2023168897A1 (zh)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114709168A (zh) * 2022-03-10 2022-07-05 长鑫存储技术有限公司 半导体结构及其制备方法
CN117525110A (zh) * 2022-07-28 2024-02-06 长鑫存储技术有限公司 半导体结构及其制作方法
CN117457737A (zh) * 2022-10-17 2024-01-26 北京超弦存储器研究院 形成掩埋位线的方法、存储器及其制造方法
CN118019323A (zh) * 2022-10-31 2024-05-10 长鑫存储技术有限公司 一种半导体结构及其制作方法
CN118042820A (zh) * 2022-11-01 2024-05-14 长鑫存储技术有限公司 半导体结构及其制造方法
CN117529105B (zh) * 2024-01-08 2024-05-14 长鑫新桥存储技术有限公司 半导体结构及其形成方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1809914A (zh) * 2003-06-24 2006-07-26 飞上公司 三维集成电路结构及其制造方法
CN109461756A (zh) * 2017-09-06 2019-03-12 中国科学院微电子研究所 Mram及其制造方法及包括mram的电子设备
CN111816671A (zh) * 2019-04-10 2020-10-23 长鑫存储技术有限公司 磁性随机存储器及其形成方法
CN114709168A (zh) * 2022-03-10 2022-07-05 长鑫存储技术有限公司 半导体结构及其制备方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1809914A (zh) * 2003-06-24 2006-07-26 飞上公司 三维集成电路结构及其制造方法
CN109461756A (zh) * 2017-09-06 2019-03-12 中国科学院微电子研究所 Mram及其制造方法及包括mram的电子设备
CN111816671A (zh) * 2019-04-10 2020-10-23 长鑫存储技术有限公司 磁性随机存储器及其形成方法
CN114709168A (zh) * 2022-03-10 2022-07-05 长鑫存储技术有限公司 半导体结构及其制备方法

Also Published As

Publication number Publication date
CN114709168A (zh) 2022-07-05

Similar Documents

Publication Publication Date Title
WO2023168897A1 (zh) 半导体结构及其制备方法
US11127783B2 (en) MRAM, method of manufacturing the same, and electronic device including the MRAM
US10304832B1 (en) Integrated circuit structure incorporating stacked field effect transistors and method
TW201715651A (zh) 邏輯半導體裝置
TW201916375A (zh) 半導體元件製造方法以及半導體元件
WO2005036651A1 (ja) 半導体装置及びその製造方法
US11849587B2 (en) Three-dimensional memory device and manufacturing method thereof
CN107017165A (zh) 静态随机存取存储器及其制造方法
US20220336261A1 (en) Method of forming semiconductor device
TWI463655B (zh) 具有合併式源汲極的鰭式場效電晶體結構及形成該結構的方法
US9287499B2 (en) Integrated circuit device
US20210376084A1 (en) Protrusion field-effect transistor and methods of making the same
US20230292530A1 (en) Semiconductor structure and manufacturing method thereof
KR20220080293A (ko) 절연 패턴들을 갖는 반도체 소자 및 그 형성 방법
CN112687627A (zh) 鳍式场效应晶体管及其制造方法
JP7483891B2 (ja) 半導体構造及びその製造方法
TWI790620B (zh) 電晶體、積體半導體元件以及製造突起場效電晶體的方法
KR102533940B1 (ko) 돌출 전계 효과 트랜지스터 및 이를 제조하는 방법
TWI802451B (zh) 半導體結構及其製造方法
CN115483247A (zh) 半导体结构及其制备方法
TW202324511A (zh) 半導體裝置及其形成方法
CN115602727A (zh) 半导体结构及其形成方法
CN114068497A (zh) 半导体结构及其形成方法
CN113506745A (zh) 鳍式场效应晶体管及其制造方法
KR20240019552A (ko) 반도체 장치

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 22930526

Country of ref document: EP

Kind code of ref document: A1