WO2023164793A1 - 显示基板及其制作方法、显示装置 - Google Patents

显示基板及其制作方法、显示装置 Download PDF

Info

Publication number
WO2023164793A1
WO2023164793A1 PCT/CN2022/078569 CN2022078569W WO2023164793A1 WO 2023164793 A1 WO2023164793 A1 WO 2023164793A1 CN 2022078569 W CN2022078569 W CN 2022078569W WO 2023164793 A1 WO2023164793 A1 WO 2023164793A1
Authority
WO
WIPO (PCT)
Prior art keywords
photoresist
display substrate
display
area
signal
Prior art date
Application number
PCT/CN2022/078569
Other languages
English (en)
French (fr)
Inventor
李凯
方业周
李峰
刘弘
王玉张
蔡志光
燕山
刘春景
Original Assignee
京东方科技集团股份有限公司
鄂尔多斯市源盛光电有限责任公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司, 鄂尔多斯市源盛光电有限责任公司 filed Critical 京东方科技集团股份有限公司
Priority to PCT/CN2022/078569 priority Critical patent/WO2023164793A1/zh
Priority to CN202280000368.0A priority patent/CN117016055A/zh
Publication of WO2023164793A1 publication Critical patent/WO2023164793A1/zh

Links

Images

Classifications

    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
    • G03F1/26—Phase shift masks [PSM]; PSM blanks; Preparation thereof
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/20—Exposure; Apparatus therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate

Definitions

  • the present disclosure relates to the field of display technology, in particular to a display substrate, a manufacturing method thereof, and a display device.
  • the full screen is more and more favored by the market; the realization of the full screen mainly lies in the continuous compression of the display frame, but limited by technical capabilities, the existing display screen The frame is still large and cannot achieve a true full screen.
  • the technical problem to be solved in the present disclosure is to provide a display substrate, a manufacturing method thereof, and a display device, which can realize narrow borders of display products.
  • a method for manufacturing a display substrate including:
  • the step of baking the pattern of the photoresist is omitted, and the pattern of the photoresist is used as a mask to etch the metal layer to form signal lines.
  • the method further includes ashing the photoresist, and the bias power used for ashing the photoresist is 3500-6000W.
  • the etching gas used for ashing the photoresist is oxygen, and the gas flow rate is 800-1000 sccm.
  • developing the exposed photoresist layer includes:
  • the developing solution is replenished to the substrate surface on which the photoresist is formed many times.
  • the number of replenishment of the developing solution is 3-5 times.
  • the developing solution is replenished 2-3 times to the surface of the base substrate on which the photoresist is formed before half of the developing process is performed.
  • the display substrate includes a display area and a peripheral area arranged around the display area, the peripheral area includes an arc-shaped corner area near the edge of the display area, and the arc-shaped corner area is provided with a first signal traces, the first signal traces include a first straight line portion, a second straight line portion, and a first arc portion connecting the first straight line portion and the second straight line portion;
  • the mask plate includes a first mask pattern for making the first arc portion, the radius of curvature of the inner boundary of the first mask pattern is 3.5-4.5um, and the outer side of the first mask pattern The radius of curvature of the boundary is 6-8um.
  • Embodiments of the present disclosure also provide a display substrate, which is manufactured by using the above method for manufacturing a display substrate.
  • the display substrate includes a display area and a peripheral area arranged around the display area, the peripheral area includes an arc-shaped corner area near the edge of the display area, and the arc-shaped corner area is provided with a first signal traces, the first signal traces include a first straight line portion, a second straight line portion, and a first arc portion connecting the first straight line portion and the second straight line portion;
  • the curvature radius of the inner boundary of the first arc portion is 3.5-4.5um, and the curvature radius of the outer boundary of the first arc portion is 6-8um.
  • the first straight portion includes a first portion close to the first arc portion and a second portion located on a side of the first portion away from the first arc portion, and the first portion
  • the line width is substantially equal to the line width of the second portion.
  • the display substrate further includes a group of dummy wires located between two adjacent first signal wires, each group of dummy wires includes at least two dummy wires parallel to each other, and the dummy wires the line extends in the same or substantially the same direction as the first straight portion;
  • the minimum distance between the virtual trace closest to the first arc portion and the first arc portion is 4.5-5.5um.
  • the distance between adjacent dummy traces is 2.0-2.5um.
  • each group of dummy wires includes two dummy wires parallel to each other.
  • the peripheral area also includes:
  • the second signal routing near the middle of the display area, the second signal routing includes:
  • the curvature radius of the inner boundary of the second arc portion is 3.5-4.5um, and the curvature radius of the outer boundary of the second arc portion is 6-8um.
  • the peripheral area also includes:
  • the second signal trace includes a second arc portion and a third straight portion connected to the second arc portion;
  • third signal traces parallel to the third straight line portion, the third signal traces are located on a side of the third straight line portion away from the display area;
  • the line width of the third signal trace is approximately equal to the line width of the third straight line portion.
  • An embodiment of the present disclosure also provides a display device, including the above-mentioned display substrate.
  • the step of baking the pattern of the photoresist is omitted, and the slope angle of the edge of the pattern of the photoresist formed like this is smaller, and the pattern of the photoresist is used as a mask to carry out the process on the metal layer.
  • the slope angle of the signal trace obtained after etching is also relatively small, which can optimize the shape of the insulating layer covered on the signal trace, and is beneficial to realize the narrow border of the display product.
  • FIG. 1 is a schematic diagram of making signal wiring in related technologies
  • FIG. 2 is a schematic diagram of making signal wiring according to an embodiment of the present disclosure
  • FIG. 3 and FIG. 4 are schematic diagrams of the developer solution concentration in the developing process of the embodiments of the present disclosure.
  • FIG. 5 is a schematic plan view showing a substrate
  • FIGS. 6-8 are schematic diagrams of masks used in embodiments of the present disclosure.
  • 9-11 are schematic diagrams of display substrates according to embodiments of the present disclosure.
  • Embodiments of the present disclosure provide a display substrate, a manufacturing method thereof, and a display device, which can realize narrow borders of display products.
  • An embodiment of the present disclosure provides a method for manufacturing a display substrate, including:
  • the step of baking the pattern of the photoresist is omitted, and the pattern of the photoresist is used as a mask to etch the metal layer to form signal lines.
  • the above-mentioned metal layer may be a gate metal layer of a display substrate, or may be a source-drain metal layer of a display substrate, and the above-mentioned etching includes dry etching and wet etching.
  • the step of baking the pattern of the photoresist is omitted, the slope angle of the edge of the pattern of the photoresist formed like this is smaller, and the pattern of the photoresist is used as a mask, and the metal layer
  • the slope angle of the signal trace obtained after etching is also relatively small, which can optimize the shape of the insulating layer covered on the signal trace, and is beneficial to realize a narrow border of the display product.
  • a metal layer 12 is formed on the base substrate 11; a photoresist layer is formed on the metal layer 12, the photoresist layer 13 is exposed using a mask, and the exposed photoresist layer is developed to form
  • the pattern of photoresist is then baked to the pattern of photoresist, as shown in Figure 1, the edge of the pattern of photoresist after baking has bigger slope angle, with the pattern of this photoresist as mask Etching the metal layer 12 by the mold will cause the formed signal traces to have a larger slope angle, which will lead to poor morphology of the insulating layer covering the signal traces.
  • the metal layer 12 is a gate metal layer.
  • an interlayer insulating layer covering the pattern of the gate metal layer will be formed, and then the pattern of the source-drain metal layer will be formed on the interlayer insulating layer. If the gate If the slope angle of the pattern of the metal layer is too large, the coverage of the interlayer insulating layer will be poor, and the surface of the interlayer insulating layer will be uneven, which will lead to the residual source and drain metal layer after etching the source and drain metal layer, and the residual source and drain The metal layer will conduct adjacent signal traces (made with source and drain metal layers). If you want to avoid the remaining source and drain metal layers from conducting adjacent signal traces, you need to increase the distance between adjacent signal traces. The design is relatively large, which is not conducive to realizing the narrow border of the display product.
  • the step of baking the pattern of the photoresist is omitted, and the slope angle of the edge of the pattern of the photoresist formed in this way (that is, the difference between the side surface of the pattern edge of the photoresist and the plane where the substrate is located) The included angle between them) is relatively small.
  • the slope angle of the signal traces (made with the gate metal layer) obtained after etching the gate metal layer is also relatively small, which can optimize the signal
  • the shape of the interlayer insulating layer covered on the wiring makes the surface of the interlayer insulating layer relatively flat, avoiding the source and drain metal layer residue on the surface of the interlayer insulating layer, and is conducive to realizing the narrow border of the display product.
  • the slope angle of the signal trace obtained after etching the gate metal layer (that is, the slope angle of the edge of the signal trace
  • the angle between the side surface and the plane where the base substrate is located) average value is 57.8 °
  • the step of baking the pattern of the photoresist is omitted, and the pattern of the photoresist is mask
  • the slope angle of the signal trace obtained after etching the gate metal layer is 36.9-53.7°
  • the average value is 46.2°. It can be seen that the technical solution of this embodiment can greatly reduce the slope angle of the signal trace .
  • the metal layer when etching the metal layer, the metal layer can be wet-etched first, and then the metal layer can be dry-etched. After the metal layer is wet-etched, the formed signal The slope angle of the traces is relatively large. Therefore, dry etching can be used to modify the shape of the signal traces to reduce the slope angle of the signal traces.
  • the critical dimension (Critical Dimension, CD) deviation (Bias) of the signal trace is relatively large, which will make the final critical dimension (Final Inspection Critical Dimension, FICD) value smaller, that is, the line width and line spacing of the signal trace If the sum is too small, the signal line is too thin and the line is broken. Therefore, it is necessary to design a relatively large frame of the display product to improve the FICD, which is not conducive to the narrow frame of the display product. Therefore, it is necessary to optimize CD Bias and improve FICD in order to realize the narrow border of display products.
  • CD Critical Dimension
  • FICD Critical Dimension
  • CD Bias is formed because the ashing speed of the photoresist is too fast, and the metal layer covered by the photoresist is etched due to over-etching.
  • the photoresist is in the form of polymer chains, which form small molecules by plasma bombardment and are ashed in an oxygen atmosphere.
  • the bias power and oxygen in the ashing process can be reduced to reduce the photoresist Ashing speed, reduce overcut, and then reduce CD Bias.
  • the method further includes ashing the photoresist.
  • the bias power used for ashing the photoresist is 3500-6000W.
  • ashing the photoresist The bias power used by the resist is about 8000W.
  • the bias power used for ashing the photoresist is reduced to 3500-6000W, which can reduce the ashing speed of the photoresist, thereby reducing CD Bias, Improve the FICD of signal routing, which is conducive to the realization of narrow borders of display products.
  • the etching gas used for ashing the photoresist is oxygen, and the gas flow rate is 800-1000 sccm.
  • the flow rate of oxygen gas when ashing the photoresist is about 1350 sccm, in this embodiment, the flow rate of oxygen gas when ashing the photoresist is reduced to 800-1000 sccm, which can reduce the flow rate of the photoresist.
  • the ashing speed reduces the CD Bias and improves the FICD of the signal line, which is beneficial to realize the narrow border of the display product.
  • CD Bias can be reduced by about 0.1um, Furthermore, the FICD of the signal routing is improved, which is conducive to realizing the narrow border of the display product.
  • an example is used to ash the photoresist with oxygen, of course, it is not limited to ashing the photoresist with oxygen, and other gases may also be used.
  • the developer spray head can be used to replenish the developer twice to the surface of the substrate on which the photoresist is formed, which can reduce the concentration difference between the exposed area and the non-exposed area, and reduce the CD. difference, improve CD uniformity, and help realize narrow borders of display products.
  • this embodiment is not limited to replenishing the developing solution twice to the surface of the base substrate on which the photoresist is formed during the developing process, and in some embodiments, the number of replenishing developing solution is 3-5 times.
  • the concentration of the developer solution changes greatly in the first half of the development process, it is possible to replenish the developer solution 2-3 times to the surface of the base substrate on which the photoresist is formed before the half of the development process is performed, which can effectively reduce exposure.
  • the developer concentration difference between the exposed area and the non-exposed area reduces the CD difference and improves the CD uniformity, which is beneficial to realize the narrow border of the display product.
  • the display substrate includes a display area and a peripheral area arranged around the display area.
  • a narrow frame of the display product can be realized.
  • the peripheral area includes an arc-shaped corner area W close to an edge portion of the display area, and the arc-shaped corner area is provided with a first signal trace, and the first signal trace includes a first straight a line portion, a second straight line portion, and a first arcuate portion connecting said first straight line portion and said second straight line portion;
  • the mask plate used to make the signal wiring in the peripheral area includes a first mask pattern 01 used to make the first arc portion, and the inner boundary of the first mask pattern 01
  • the radius of curvature is 3.5-4.5um, and the radius of curvature of the outer boundary of the first mask pattern 01 is 6-8um.
  • the radius of curvature of the outer boundary of the first mask pattern 01 is too small, it is easy to cause metal residue between the arc portion of the first signal trace and the adjacent signal trace; if the outer boundary of the first mask pattern 01 is If the radius of curvature is too large, the distance between the arc portion of the first signal trace and adjacent signal traces will be too large, and the signal traces in the peripheral area need to occupy a relatively large area, which is not conducive to realizing a narrow border of the display product.
  • the radius of curvature of the inner boundary of the first mask pattern 01 is designed to be 3.5-4.5um, and the radius of curvature of the outer boundary of the first mask pattern 01 is designed to be 6-8um, which can ensure Metal residues are less likely to appear between the arc portion of the first signal trace and adjacent signal traces, and can prevent the signal traces in the peripheral area from occupying a relatively large area, which is beneficial to realizing a narrow border of the display product.
  • the curvature radius of the inner boundary of the first mask pattern 01 may be 4um, and the curvature radius of the outer boundary of the first mask pattern 01 may be 6um.
  • the first straight line portion includes a first portion close to the first arc portion and a second portion located on a side of the first portion away from the first arc portion, as shown in FIG. 6 , the mask plate includes a second mask pattern 02 for making the first part and a third mask pattern 03 for making the second part.
  • the display substrate further includes a group of dummy wires located between two adjacent first signal wires, each group of dummy wires includes at least two dummy wires parallel to each other, and the extension direction of the dummy wires is the same as
  • the extension directions of the first straight line portions are the same or substantially the same;
  • the mask plate includes a dummy mask pattern 08 for making the dummy wiring and a fourth mask pattern 04 for making the second straight line portion, the dummy mask pattern 08 and the first
  • the extension directions of the two mask patterns 02 are the same or roughly the same;
  • the line widths of the second mask pattern 02 and the third mask pattern 03 are equal, since the distance between the second mask pattern 02 and the virtual mask pattern 08 is relatively short, after exposing and developing the photoresist by using the mask plate, After the pattern of photoresist is used as a mask to etch the metal layer to form signal lines, it is easy to cause the line width of the first part to be smaller than the line width of the second part. Therefore, it is necessary to use the second mask pattern 02 and the third mask Die pattern 03 is designed to compensate the line width of the first part.
  • the line width of the second mask pattern 02 is 0.08-0.12um larger than the line width of the third mask pattern 03, so that the line width of the formed first part and the line width of the second part can be guaranteed Basically equal. If the line width of the second mask pattern is much larger than the line width of the third mask pattern, such as greater than 0.2um or 0.3um, a residual metal layer will be generated between the first part and the dummy wiring; If the line width of the second mask pattern is too small compared with the line width of the third mask pattern, for example, greater than 0.01um, then the compensation effect will not be achieved, and the line width of the first part will still be relatively small, sometimes Risk of disconnection. In a specific example, the line width of the second mask pattern 02 may be 0.1 um larger than the line width of the third mask pattern 03 .
  • the size and position of the dummy mask pattern can be designed, and the dummy mask pattern can be extended to reduce
  • the distance between the virtual mask pattern and the first mask pattern and the fourth mask pattern the minimum distance D between the virtual mask pattern closest to the first mask pattern and the first mask pattern can be is 2.0-2.5um; the minimum distance B or C between the dummy mask pattern and the fourth mask pattern can be 2.0-2.5um.
  • the minimum distance between the virtual mask pattern closest to the first mask pattern and the first mask pattern is 2.5um
  • the distance between the virtual mask pattern and the fourth mask pattern The minimum distance between them is 2.5um, so that after using the mask to make signal traces, the minimum distance between the virtual trace closest to the first arc and the first arc is 4.5-5.5 um, can reduce the distance between the dummy wiring and the first signal wiring, thereby reducing the area of the peripheral area, which is beneficial to realize the narrow border of the display product.
  • each group of virtual wires includes two virtual wires parallel to each other.
  • each group of virtual mask patterns includes two virtual mask patterns parallel to each other.
  • the line width A of the fourth mask pattern 04 can be 3.5um, and the minimum distance B or C between the virtual mask pattern 08 and the fourth mask pattern 04 can be 4.0um , the minimum distance D between the virtual mask pattern 08 and a first mask pattern 01 can be greater than 2.4um, and the minimum distance G between a virtual mask pattern 08 and another first mask pattern 01 can be 2.3um , the minimum distance H between another virtual mask pattern 08 and another first mask pattern 01 can be 2.0um, and the minimum distance I between the third mask pattern 03 and another first mask pattern 01 can be It is 2.2um.
  • the display substrate also includes traces parallel to the first straight line, and the pitch F of the mask pattern used to make this portion of traces may be 1.8-2.0um.
  • the peripheral area also includes:
  • the second signal routing near the middle of the display area, the second signal routing includes:
  • third signal traces parallel to the third straight line portion, the third signal traces are located on a side of the third straight line portion away from the display area;
  • the mask plate includes a fifth mask pattern 05 for making the second arc portion, and the mask plate also includes a sixth mask pattern for making the third straight portion 06 and the seventh mask pattern 07 for making the third signal trace.
  • the radius of curvature of the outer boundary of the fifth mask pattern 05 is too small, it is easy to cause metal residue between the arc portion of the second signal trace and the adjacent signal trace; if the outer boundary of the fifth mask pattern 05 If the radius of curvature is too large, the distance between the arc portion of the second signal trace and the adjacent signal trace is too large, and the signal trace in the peripheral area needs to occupy a relatively large area, which is not conducive to realizing a narrow border of the display product.
  • the radius of curvature of the inner boundary of the fifth mask pattern 05 is designed to be 3.5-4.5um, and the radius of curvature of the outer boundary of the fifth mask pattern 05 is designed to be 6-8um, which can ensure that the second Metal residues are not easy to appear between the arc-shaped part of the signal trace and the adjacent signal trace, and it can prevent the signal trace in the peripheral area from occupying a relatively large area, which is conducive to realizing the narrow border of the display product.
  • the curvature radius of the inner boundary of the fifth mask pattern 05 may be 4um, and the curvature radius of the outer boundary of the fifth mask pattern 05 may be 6um.
  • the line width of the sixth mask pattern 06 is 0.18-0.22um larger than the line width of the seventh mask pattern 07, so as to ensure that the line width of the formed third straight line part is consistent with that of the third signal line.
  • the lines are approximately equal in width. If the line width of the sixth mask pattern 06 is much larger than the line width of the seventh mask pattern 07, such as greater than 0.2um or 0.3um, the linewidth of the third straight line part will be different from that of the third signal.
  • a residual metal layer is generated between the lines; if the line width of the sixth mask pattern 06 is too small than the line width of the seventh mask pattern 07, such as greater than 0.01um, the compensation effect will not be achieved, and the third The line width of the straight part will still be relatively small, and there is a risk of line breakage.
  • the line width of the sixth mask pattern 06 is 0.2 um larger than the line width of the seventh mask pattern 07 .
  • the line width J of the fifth mask pattern 05 may be 3.5um, and the minimum distance K between the fifth mask pattern 05 and the seventh mask pattern 07 may be 2.2um.
  • the display substrate also includes a punch area.
  • the punch area is an area for placing photosensitive devices, and signal traces are arranged around the punch area.
  • the mask plate also includes a mask pattern 09 for making signal traces around the punch area.
  • the minimum distance L and M between the virtual mask pattern 08 and the adjacent mask pattern 09 can be 3.0um
  • the pitch of the virtual routing N can be 2.4-3.3um
  • the pitch P of the mask pattern 09 corresponding to the signal trace can be 2.3-3.3um.
  • the blank area of the outermost signal traces is relatively large, and the line width of the outermost signal traces will be thinner during exposure and development.
  • the line width of the mask pattern 09 on the outermost side of the line makes the line width of this part of the mask pattern 09 increase by 0.18-0.22um compared with other mask patterns, for example, it can be 0.2um.
  • the pattern of the gate metal layer when manufacturing narrow-frame display products, it is necessary to form the pattern of the gate metal layer through two patterning processes, including: forming the pattern of the gate metal layer in the display area through a patterning process using a wet etching + dry etching process.
  • a wet etching + dry etching process Due to the relatively small area of the peripheral area and high precision requirements, another patterning process is required to use a dry etching process with a small etching bias to form the gate metal layer pattern in the peripheral area, which increases the production time of the display substrate and improves the display performance. The production cost of the substrate.
  • the etching bias of the wet etching+dry etching process can be reduced, so that the display area and the peripheral area can be formed through a single patterning process.
  • the pattern of the gate metal layer that is, the gate metal layer pattern of the display area and the peripheral area is formed through a patterning process using a wet etching + dry etching process, which reduces the production time of the display substrate and reduces the production cost of the display substrate.
  • the gate metal layer pattern of the display area and the peripheral area through a patterning process using a wet etching + dry etching process, a layer of photoresist is coated on the gate metal layer, and the photoresist is exposed and developed to form The pattern of the photoresist, using the pattern of the photoresist as a mask, etches the gate metal layer to initially form the pattern of the gate metal layer, but at this time the slope angle of the pattern edge of the formed gate metal layer is relatively large, so Afterwards, the pattern of the gate metal layer is trimmed by dry etching to reduce the slope angle of the pattern edge of the gate metal layer. At the same time, the pattern of the active layer formed on the display substrate can also be doped by dry etching to improve the conductivity of the active layer.
  • Embodiments of the present disclosure also provide a display substrate, which is manufactured by using the above method for manufacturing a display substrate.
  • the step of baking the pattern of the photoresist is omitted in the production process of the display substrate, so that the slope angle of the edge of the pattern of the photoresist formed in this way is small, and the pattern of the photoresist is Mask, the slope angle of the signal traces (made of the gate metal layer) obtained after etching the gate metal layer is also relatively small, so that the morphology of the interlayer insulating layer covered on the signal traces can be optimized, so that the interlayer
  • the surface of the insulating layer is relatively smooth, which avoids source and drain metal layer residues on the surface of the interlayer insulating layer, and is conducive to realizing a narrow frame of the display product.
  • the average slope angle of the signal traces obtained is 57.8°.
  • the step of baking the photoresist pattern is omitted, and the slope angle of the signal trace obtained after etching the gate metal layer using the photoresist pattern as a mask is 36.9-53.7°, with an average value of 46.2°. It can be seen that the technical solution of this embodiment can greatly reduce the slope angle of signal traces.
  • the metal layer when etching the metal layer, the metal layer can be wet-etched first, and then the metal layer can be dry-etched. After the metal layer is wet-etched, the formed signal The slope angle of the traces is relatively large. Therefore, dry etching can be used to modify the shape of the signal traces to reduce the slope angle of the signal traces.
  • the display substrate includes a display area and a peripheral area arranged around the display area, the peripheral area includes an arc-shaped corner area W near the edge of the display area, and the arc
  • the corner area is provided with a first signal trace, and the first signal trace includes a first straight line portion, a second straight line portion and a first arc connecting the first straight line portion and the second straight line portion part;
  • the peripheral area includes an arc-shaped corner area near the edge of the display area, the arc-shaped corner area is provided with a first signal trace, and the first signal trace
  • the line includes a first straight portion, a second straight portion and a first arc portion 21 connecting the first straight portion and the second straight portion;
  • the mask plate used to make the signal wiring in the peripheral area includes a first mask pattern 01 used to make the first arc portion, and the inner boundary of the first mask pattern 01
  • the radius of curvature is 3.5-4.5um, and the radius of curvature of the outer boundary of the first mask pattern 01 is 6-8um.
  • the radius of curvature of the outer boundary of the first mask pattern 01 is too small, it is easy to cause metal residue between the arc portion of the first signal trace and the adjacent signal trace; if the outer boundary of the first mask pattern 01 is If the radius of curvature is too large, the distance between the arc portion of the first signal trace and adjacent signal traces will be too large, and the signal traces in the peripheral area need to occupy a relatively large area, which is not conducive to realizing a narrow border of the display product.
  • the radius of curvature of the inner boundary of the first mask pattern 01 is designed to be 3.5-4.5um, and the radius of curvature of the outer boundary of the first mask pattern 01 is designed to be 6-8um, which can ensure Metal residues are less likely to appear between the arc portion of the first signal trace and adjacent signal traces, and can prevent the signal traces in the peripheral area from occupying a relatively large area, which is beneficial to realizing a narrow border of the display product.
  • the curvature radius of the inner boundary of the first mask pattern 01 may be 4um, and the curvature radius of the outer boundary of the first mask pattern 01 may be 6um.
  • the radius of curvature of the inner boundary of the first arc portion 21 is 3.5-4.5um, and the curvature of the outer boundary of the first arc portion 21 is The radius is 6-8um.
  • the curvature radius of the inner boundary of the first arc portion 21 may be 4um, and the curvature radius of the outer boundary of the first arc portion 21 may be 6um.
  • the first straight portion includes a first portion 22 close to the first arc portion and a portion on the side of the first portion 22 away from the first arc portion 21.
  • the second part 23 as shown in FIG. 6 , the mask plate includes a second mask pattern 02 for making the first part and a third mask pattern 03 for making the second part.
  • the mask plate includes a dummy mask pattern 08 for making the dummy wiring and a fourth mask pattern 04 for making the second straight line portion, the dummy mask pattern 08 and the first
  • the extension directions of the two mask patterns 02 are the same or roughly the same;
  • the line widths of the second mask pattern 02 and the third mask pattern 03 are equal, since the distance between the second mask pattern 02 and the virtual mask pattern 08 is relatively short, after exposing and developing the photoresist by using the mask plate, After the pattern of photoresist is used as a mask to etch the metal layer to form signal lines, it is easy to cause the line width of the first part to be smaller than the line width of the second part. Therefore, it is necessary to use the second mask pattern 02 and the third mask Die pattern 03 is designed to compensate the line width of the first part.
  • the line width of the second mask pattern 02 is 0.08-0.12um larger than the line width of the third mask pattern 03, so that the line width of the formed first part and the line width of the second part can be guaranteed Basically equal. If the line width of the second mask pattern is much larger than the line width of the third mask pattern, such as greater than 0.2um or 0.3um, a residual metal layer will be generated between the first part and the dummy wiring; If the line width of the second mask pattern is too small compared with the line width of the third mask pattern, for example, greater than 0.01um, then the compensation effect will not be achieved, and the line width of the first part will still be relatively small, sometimes Risk of disconnection. In a specific example, the line width of the second mask pattern 02 may be 0.1 um larger than the line width of the third mask pattern 03 .
  • the lines of the first part 22 is approximately equal to the line width of the second portion 23 .
  • the size and position of the dummy mask pattern can be designed, and the dummy mask pattern can be extended to reduce
  • the distance between the virtual mask pattern and the first mask pattern and the fourth mask pattern, the minimum distance D between the virtual mask pattern closest to the first mask pattern and the first mask pattern can be is 2.0-2.5um; the minimum distance B or C between the dummy mask pattern and the fourth mask pattern can be 2.0-2.5um.
  • the minimum distance D1 between the virtual trace 28 closest to the first arc portion 21 and the first arc portion 21 is It is 4.5-5.5um, which can reduce the distance between the dummy trace 28 and the first signal trace, thereby reducing the area of the peripheral area, which is beneficial to realize the narrow border of the display product.
  • each group of virtual wires includes two virtual wires 28 parallel to each other.
  • each group of virtual mask patterns includes two virtual masks parallel to each other. pattern, in order to reduce the area occupied by the virtual mask pattern, the distance between adjacent virtual mask patterns cannot be too large; in addition, in order to avoid residual metal layers between virtual lines, adjacent virtual mask patterns The distance between the graphics cannot be too small.
  • the distance between the adjacent virtual mask graphics can be designed to be 2.0-2.5um, which can reduce the area occupied by the virtual mask graphics and avoid The metal layer remains between the dummy traces.
  • the line width A1 of the second straight line portion 24 may be 3.5um
  • the minimum distance B1 or C1 between the virtual line 28 and the second straight line portion 24 may be 4.0um
  • the virtual line width A1 may be 4.0um.
  • the minimum distance D1 between the line 28 and a first arc portion 21 can be greater than 2.4um
  • the minimum distance G1 between a virtual trace 28 and another first arc portion 21 can be 2.3um
  • the minimum distance H1 between the line 28 and another dummy wire 28 may be 2.0 um
  • the minimum distance I1 between the second part 23 and another dummy wire 28 may be 2.2 um.
  • the display substrate also includes traces parallel to the first straight line. As shown in FIG. 9 , the pitch F1 of this portion of traces can be 1.8-2.0um.
  • the peripheral area further includes:
  • the second signal routing near the middle of the display area, the second signal routing includes:
  • the mask plate includes a fifth mask pattern 05 for making the second arc portion, and the mask plate also includes a sixth mask pattern for making the third straight portion 06 and the seventh mask pattern 07 for making the third signal trace.
  • the radius of curvature of the outer boundary of the fifth mask pattern 05 is too small, it is easy to cause metal residue between the arc portion of the second signal trace and the adjacent signal trace; if the outer boundary of the fifth mask pattern 05 If the radius of curvature is too large, the distance between the arc portion of the second signal trace and the adjacent signal trace is too large, and the signal trace in the peripheral area needs to occupy a relatively large area, which is not conducive to realizing a narrow border of the display product.
  • the radius of curvature of the inner boundary of the fifth mask pattern 05 is designed to be 3.5-4.5um, and the radius of curvature of the outer boundary of the fifth mask pattern 05 is designed to be 6-8um, which can ensure that the second Metal residues are not easy to appear between the arc-shaped part of the signal trace and the adjacent signal trace, and it can prevent the signal trace in the peripheral area from occupying a relatively large area, which is conducive to realizing the narrow border of the display product.
  • the inside of the second arc portion 25 The radius of curvature of the boundary is 3.5-4.5um, and the radius of curvature of the outer boundary of the second arc portion 25 is 6-8um.
  • the curvature radius of the inner boundary of the second arc portion 25 may be 4um, and the curvature radius of the outer boundary of the second arc portion 25 may be 6um.
  • the line width of the sixth mask pattern 06 is 0.18-0.22um larger than the line width of the seventh mask pattern 07, which can ensure that the line width of the formed third straight line portion 26 is consistent with the third signal
  • the line widths of the traces 27 are approximately equal.
  • the line width J1 of the second arc portion 25 may be 3.5um, and the minimum distance K1 between the second arc portion 25 and the third signal trace 27 may be 2.2um.
  • the display substrate also includes a punch area.
  • the punch area is an area for placing photosensitive devices, and signal traces are arranged around the punch area.
  • the mask plate also includes a mask pattern 09 for making signal traces around the punch area.
  • the minimum distances L1 and M1 between the virtual traces 28 and the adjacent signal traces 29 can be 3.0um, and the pitch N1 of the virtual traces It can be 2.4-3.3um, and the pitch P1 of the signal trace 29 can be 2.3-3.3um.
  • An embodiment of the present disclosure also provides a display device, including the above-mentioned display substrate.
  • the display device includes but not limited to: a radio frequency unit, a network module, an audio output unit, an input unit, a sensor, a display unit, a user input unit, an interface unit, a memory, a processor, and a power supply.
  • a radio frequency unit a network module
  • an audio output unit an input unit
  • a sensor a sensor
  • a display unit a user input unit
  • an interface unit a memory
  • a processor and a power supply.
  • the display device includes but is not limited to a monitor, a mobile phone, a tablet computer, a television, a wearable electronic device, a navigation display device, and the like.
  • the display device can be any product or component with a display function such as a TV, a monitor, a digital photo frame, a mobile phone, and a tablet computer, wherein the display device also includes a flexible circuit board, a printed circuit board, and a backplane.
  • each embodiment in this specification is described in a progressive manner, the same and similar parts of each embodiment can be referred to each other, and each embodiment focuses on the differences from other embodiments.
  • the description is relatively simple, and for related parts, please refer to the description of the product embodiment.

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

本公开提供了一种显示基板及其制作方法、显示装置，属于显示技术领域。其中，显示基板的制作方法包括：在衬底基板上形成金属层；在所述金属层上形成光刻胶层；利用掩模板对所述光刻胶层进行曝光；对曝光后的所述光刻胶层进行显影，形成光刻胶的图形；省去对所述光刻胶的图形进行烘烤的步骤，以所述光刻胶的图形为掩模，对所述金属层进行刻蚀，形成信号走线。本公开的技术方案能够实现显示产品的窄边框。

Description

显示基板及其制作方法、显示装置 技术领域
本公开涉及显示技术领域，特别是指一种显示基板及其制作方法、显示装置。
背景技术
随着显示产品的不断创新发展及用户需求的不断更新，全面屏越来越受到市场的青睐；全面屏的实现主要在于显示屏边框的不断压缩，但受限于技术能力，现有显示屏的边框仍然较大，不能实现真正的全面屏。
发明内容
本公开要解决的技术问题是提供一种显示基板及其制作方法、显示装置，能够实现显示产品的窄边框。
为解决上述技术问题，本公开的实施例提供技术方案如下：
一方面，提供一种显示基板的制作方法，包括：
在衬底基板上形成金属层；
在所述金属层上形成光刻胶层；
利用掩模板对所述光刻胶层进行曝光；
对曝光后的所述光刻胶层进行显影，形成光刻胶的图形；
省去对所述光刻胶的图形进行烘烤的步骤，以所述光刻胶的图形为掩模，对所述金属层进行刻蚀，形成信号走线。
一些实施例中，形成信号走线之后，所述方法还包括灰化所述光刻胶，灰化所述光刻胶采用的偏压功率为3500-6000W。
一些实施例中，灰化所述光刻胶采用的刻蚀气体为氧气，气体流量为800-1000sccm。
一些实施例中，对曝光后的所述光刻胶层进行显影包括：
在显影过程中，向形成有光刻胶的衬底基板表面多次补充显影液。
一些实施例中，补充显影液的次数为3-5次。
一些实施例中，在显影过程执行一半之前，向形成有光刻胶的衬底基板表面补充2-3次显影液。
一些实施例中，所述显示基板包括显示区和环绕显示区设置的外围区，所述外围区包括靠近所述显示区的边缘部分的弧形拐角区，所述弧形拐角区设置有第一信号走线，所述第一信号走线包括第一直线部分、第二直线部分和连接所述第一直线部分和所述第二直线部分的第一弧形部分；
所述掩模板包括用以制作所述第一弧形部分的第一掩模图形，所述第一掩模图形的内侧边界的曲率半径为3.5-4.5um，所述第一掩模图形的外侧边界的曲率半径为6-8um。
本公开的实施例还提供了一种显示基板，采用上述的显示基板的制作方法制作得到。
一些实施例中，所述显示基板包括显示区和环绕显示区设置的外围区，所述外围区包括靠近所述显示区的边缘部分的弧形拐角区，所述弧形拐角区设置有第一信号走线，所述第一信号走线包括第一直线部分、第二直线部分和连接所述第一直线部分和所述第二直线部分的第一弧形部分；
所述第一弧形部分的内侧边界的曲率半径为3.5-4.5um，所述第一弧形部分的外侧边界的曲率半径为6-8um。
一些实施例中，所述第一直线部分包括靠近所述第一弧形部分的第一部分和位于所述第一部分远离所述第一弧形部分一侧的第二部分，所述第一部分的线宽与所述第二部分线宽大致相等。
一些实施例中，所述显示基板还包括位于相邻两条第一信号走线之间的一组虚拟走线，每组虚拟走线包括相互平行的至少两条虚拟走线，所述虚拟走线的延伸方向与所述第一直线部分的延伸方向相同或大致相同；
距离所述第一弧形部分最近的虚拟走线与所述第一弧形部分之间的最小距离为4.5-5.5um。
一些实施例中，相邻虚拟走线之间的距离为2.0-2.5um。
一些实施例中，每组虚拟走线包括相互平行的两条虚拟走线。
一些实施例中，所述外围区还包括：
靠近所述显示区的中部的第二信号走线，所述第二信号走线包括：
第二弧形部分和与所述第二弧形部分连接的第三直线部分；
所述第二弧形部分的内侧边界的曲率半径为3.5-4.5um，所述第二弧形部分的外侧边界的曲率半径为6-8um。
一些实施例中，所述外围区还包括：
靠近所述显示区的中部的第二信号走线，所述第二信号走线包括第二弧形部分和与所述第二弧形部分连接的第三直线部分；
与所述第三直线部分平行的多个第三信号走线，所述第三信号走线位于所述第三直线部分远离所述显示区的一侧；
所述第三信号走线的线宽与所述第三直线部分的线宽大致相等。
本公开的实施例还提供了一种显示装置，包括上述的显示基板。
本公开的实施例具有以下有益效果：
上述方案中，省去对光刻胶的图形进行烘烤的步骤，这样形成的光刻胶的图形的边缘的坡度角较小，以这样的光刻胶的图形为掩模，对金属层进行刻蚀后得到的信号走线的坡度角也比较小，这样能够优化信号走线上覆盖的绝缘层的形貌，有利于实现显示产品的窄边框。
附图说明
图1为相关技术制作信号走线的示意图；
图2为本公开实施例制作信号走线的示意图；
图3和图4为本公开实施例显影过程显影液浓度的示意图；
图5为显示基板的平面示意图；
图6-图8为本公开实施例使用的掩模板的示意图；
图9-图11为本公开实施例显示基板的示意图。
附图标记
11 衬底基板
12 金属层
13 光刻胶层
01 第一掩模图形
02 第二掩模图形
03 第三掩模图形
04 第四掩模图形
05 第五掩模图形
06 第六掩模图形
07 第七掩模图形
08 虚拟掩模图形
09 掩模图形
21 第一弧形部分
22 第一部分
23 第二部分
24 第二直线部分
25 第二弧形部分
26 第三直线部分
27 第三信号走线
28 虚拟走线
29 信号走线
具体实施方式
为使本公开的实施例要解决的技术问题、技术方案和优点更加清楚，下面将结合附图及具体实施例进行详细描述。
本公开的实施例提供一种显示基板及其制作方法、显示装置，能够实现显示产品的窄边框。
本公开的实施例提供一种显示基板的制作方法，包括：
在衬底基板上形成金属层；
在所述金属层上形成光刻胶层；
利用掩模板对所述光刻胶层进行曝光；
对曝光后的所述光刻胶层进行显影，形成光刻胶的图形；
省去对所述光刻胶的图形进行烘烤的步骤，以所述光刻胶的图形为掩模，对所述金属层进行刻蚀，形成信号走线。
上述金属层可以是显示基板的栅金属层，也可以是显示基板的源漏金属层，上述刻蚀包括干法刻蚀和湿法刻蚀。
本实施例中，省去对光刻胶的图形进行烘烤的步骤，这样形成的光刻胶的图形的边缘的坡度角较小，以这样的光刻胶的图形为掩模，对金属层进行刻蚀后得到的信号走线的坡度角也比较小，这样能够优化信号走线上覆盖的绝缘层的形貌，有利于实现显示产品的窄边框。
相关技术中，在衬底基板11上形成金属层12；在金属层12上形成光刻胶层，利用掩模板对光刻胶层13进行曝光，对曝光后的光刻胶层进行显影，形成光刻胶的图形，然后对光刻胶的图形进行烘烤，如图1所示，烘烤后的光刻胶的图形的边缘具有较大的坡度角，以该光刻胶的图形为掩模对金属层12进行刻蚀，会使得形成的信号走线也具有较大的坡度角，进而导致覆盖信号走线的绝缘层形貌不良。比如，金属层12为栅金属层，在形成栅金属层的图形后，会形成覆盖栅金属层的图形的层间绝缘层，然后在层间绝缘层上形成源漏金属层的图形，如果栅金属层的图形的坡度角过大，会使得层间绝缘层的覆盖差，层间绝缘层表面不平整，进而导致在刻蚀源漏金属层后会出现源漏金属层残留，残留的源漏金属层会导通相邻的信号走线(采用源漏金属层制作)，如果要避免残留的源漏金属层导通相邻的信号走线，需要将相邻的信号走线之间的间距设计的比较大，不利于实现显示产品的窄边框。
本实施例中，省去对光刻胶的图形进行烘烤的步骤，这样形成的光刻胶的图形的边缘的坡度角(即光刻胶的图形边缘的侧表面与衬底基板所在平面之间夹角)较小，以这样的光刻胶的图形为掩模，对栅金属层进行刻蚀后得到的信号走线(采用栅金属层制作)的坡度角也比较小，这样能够优化信号走线上覆盖的层间绝缘层的形貌，使得层间绝缘层的表面比较平整，避免层间绝缘层表面出现源漏金属层残留，有利于实现显示产品的窄边框。
一具体示例中，对光刻胶的图形进行烘烤后，再利用光刻胶的图形为掩 模，对栅金属层进行刻蚀后得到的信号走线的坡度角(即信号走线边缘的侧表面与衬底基板所在平面之间夹角)平均值为57.8°，在其他工艺参数不变的情况下，省去对光刻胶的图形进行烘烤的步骤，利用光刻胶的图形为掩模，对栅金属层进行刻蚀后得到的信号走线的坡度角为36.9-53.7°，平均值为46.2°，可以看出，本实施例的技术方案能够大大降低信号走线的坡度角。
本实施例中，在对金属层进行刻蚀时，可以先对金属层进行湿法刻蚀，然后再对金属层进行干法刻蚀，在对金属层进行湿法刻蚀后，形成的信号走线的坡度角比较大，因此，后续可以利用干法刻蚀对信号走线的形貌进行修饰，降低信号走线的坡度角。
相关技术中，信号走线的关键尺寸(Critical Dimension，CD)偏差(Bias)比较大，会使得最终关键尺寸(Final Inspection Critical Dimension，FICD)值偏小，即信号走线的线宽和线间距之和偏小，以出现信号走线过细和断线不良，因此，需要将显示产品的边框设计的比较大以提升FICD，不利于显示产品的窄边框。因此，需要优化CD Bias，提升FICD才能实现显示产品的窄边框。
其中，CD Bias是由于光刻胶灰化速度过快，过刻导致光刻胶覆盖的金属层被刻蚀而形成。其中，光刻胶为高分子链状，通过等离子体轰击形成小分子，在氧气氛围内灰化，本实施例中，可以通过降低灰化工艺中的偏压功率和氧气来降低光刻胶的灰化速度，减少过刻，进而降低CD Bias。
一些实施例中，形成信号走线之后，所述方法还包括灰化所述光刻胶，灰化所述光刻胶采用的偏压功率为3500-6000W，相关技术中，灰化所述光刻胶采用的偏压功率为8000W左右，本实施例中，将灰化所述光刻胶采用的偏压功率降低至3500-6000W，可以降低光刻胶的灰化速度，进而降低CD Bias，提升信号走线的FICD，有利于实现显示产品的窄边框。
一些实施例中，灰化所述光刻胶采用的刻蚀气体为氧气，气体流量为800-1000sccm。相关技术中，灰化所述光刻胶时的氧气气体流量为1350sccm左右，本实施例中，将灰化所述光刻胶时的氧气气体流量降低至800-1000sccm，可以降低光刻胶的灰化速度，进而降低CD Bias，提升信号走线的FICD，有利于实现显示产品的窄边框。
经过实验，在将灰化所述光刻胶采用的偏压功率降低至3500-6000W，灰化所述光刻胶时的氧气气体流量降低至800-1000sccm后，可以降低CD Bias0.1um左右，进而提升信号走线的FICD，有利于实现显示产品的窄边框。
本实施例中，以采用氧气灰化光刻胶进行举例，当然，并不局限于采用氧气来灰化光刻胶，还可以采用其他气体。
相关技术中，以光刻胶采用正性光刻胶为例，在利用掩模板对光刻胶进行曝光后，形成曝光区和未曝光区，之后利用显影液对光刻胶进行显影。如图3所示，在显影开始阶段，显示基板各区域的显影液浓度相同，在经过一段时间的显影后，由于曝光区的光刻胶与显影液发生反应，会导致曝光区的显影液的浓度下降，与非曝光区的显影液浓度产生差异，尤其对于窄边框显示产品，信号走线之间的间距比较小，会加重曝光区与非曝光区的显影液浓度差异，进而导致CD差异明显，最终引起显示产品不良。
为了改善显示产品的良率，需要降低曝光区与非曝光区的显影液浓度差异，在显影过程中，向形成有光刻胶的衬底基板表面多次补充显影液。如图4所示，在显影结束之前，可以利用显影液喷头向形成有光刻胶的衬底基板表面补充2次显影液，这样可以降低曝光区与非曝光区的显影液浓度差异，降低CD差异，提升CD均一性，有利于实现显示产品的窄边框。当然，本实施例并不局限于在显影过程中向形成有光刻胶的衬底基板表面补充2次显影液，一些实施例中，补充显影液的次数为3-5次。
另外，由于在显影过程的前半阶段显影液浓度变化比较大，因此，可以在显影过程执行一半之前，向形成有光刻胶的衬底基板表面补充2-3次显影液，这样能够有效降低曝光区与非曝光区的显影液浓度差异，降低CD差异，提升CD均一性，有利于实现显示产品的窄边框。
从降低曝光区与非曝光区的显影液浓度差异的角度出发，在显影过程中，补充显影液的次数越多越好，但这也会带来成本的增加，因此，均衡这两者，可以在显影过程的前半阶段向形成有光刻胶的衬底基板表面补充2-3次显影液，在显影过程的后半阶段向形成有光刻胶的衬底基板表面补充1-2次显影液。这样既可以尽量降低曝光区与非曝光区的显影液浓度差异，也可以控制 显示基板的制作成本。
如图5所示，显示基板包括显示区和环绕显示区设置的外围区，为了降低外围区信号走线的pitch(即信号走线的线宽和线间距之和)，实现显示产品的窄边框，需要对制作外围区信号走线的掩模板进行设计。
一些实施例中，所述外围区包括靠近所述显示区的边缘部分的弧形拐角区W，所述弧形拐角区设置有第一信号走线，所述第一信号走线包括第一直线部分、第二直线部分和连接所述第一直线部分和所述第二直线部分的第一弧形部分；
如图6所示，用以制作外围区信号走线的所述掩模板包括用以制作所述第一弧形部分的第一掩模图形01，所述第一掩模图形01的内侧边界的曲率半径为3.5-4.5um，所述第一掩模图形01的外侧边界的曲率半径为6-8um。
如果第一掩模图形01的外侧边界的曲率半径过小，容易导致第一信号走线的弧形部分与相邻信号走线之间出现金属残留；如果第一掩模图形01的外侧边界的曲率半径过大，容易导致第一信号走线的弧形部分与相邻信号走线之间的间距过大，外围区信号走线需要占据比较大的面积，不利于实现显示产品的窄边框。因此，本实施例中，将第一掩模图形01的内侧边界的曲率半径设计为3.5-4.5um，所述第一掩模图形01的外侧边界的曲率半径设计为6-8um，既可以保证第一信号走线的弧形部分与相邻信号走线之间不易出现金属残留，又可以避免外围区信号走线占据比较大的面积，有利于实现显示产品的窄边框。
一具体示例中，第一掩模图形01的内侧边界的曲率半径可以为4um，所述第一掩模图形01的外侧边界的曲率半径可以为6um。
一些实施例中，所述第一直线部分包括靠近所述第一弧形部分的第一部分和位于所述第一部分远离所述第一弧形部分一侧的第二部分，如图6所示，所述掩模板包括用以制作所述第一部分的第二掩模图形02和用以制作所述第二部分的第三掩模图形03。
所述显示基板还包括位于相邻两条第一信号走线之间的一组虚拟走线，每组虚拟走线包括相互平行的至少两条虚拟走线，所述虚拟走线的延伸方向 与所述第一直线部分的延伸方向相同或大致相同；
如图6所示，所述掩模板包括用以制作所述虚拟走线的虚拟掩模图形08和用以制作所述第二直线部分的第四掩模图形04，虚拟掩模图形08与第二掩模图形02的延伸方向相同或大致相同；
如果第二掩模图形02和第三掩模图形03的线宽相等，由于第二掩模图形02与虚拟掩模图形08的距离比较近，在利用掩模板对光刻胶进行曝光显影后，以光刻胶的图形为掩模对金属层进行刻蚀形成信号走线后，容易导致第一部分的线宽小于第二部分的线宽，因此，需要对第二掩模图形02和第三掩模图形03进行设计，来对第一部分的线宽进行补偿。
一些实施例中，所述第二掩模图形02的线宽比所述第三掩模图形03的线宽大0.08-0.12um，这样可以保证形成的第一部分的线宽与第二部分的线宽基本相等。如果所述第二掩模图形的线宽比所述第三掩模图形的线宽大的过多，比如大于0.2um或0.3um，会使得第一部分与虚拟走线之间产生残留的金属层；如果所述第二掩模图形的线宽比所述第三掩模图形的线宽大的过少，比如大于0.01um，则起不到补偿的效果，第一部分的线宽仍然会比较小，有断线的风险。一具体示例中，第二掩模图形02的线宽可以比第三掩模图形03的线宽大0.1um。
一些实施例中，为了减少虚拟走线与第一信号走线之间的间距，进而缩减外围区的面积，可以对虚拟掩模图形的尺寸和位置进行设计，对虚拟掩模图形进行延伸，降低虚拟掩模图形与第一掩模图形和第四掩模图形之间的距离，距离所述第一掩模图形最近的虚拟掩模图形与所述第一掩模图形之间的最小距离D可以为2.0-2.5um；所述虚拟掩模图形与所述第四掩模图形之间的最小距离B或C可以为2.0-2.5um。
一具体示例中，距离所述第一掩模图形最近的虚拟掩模图形与所述第一掩模图形之间的最小距离为2.5um，所述虚拟掩模图形与所述第四掩模图形之间的最小距离为2.5um，这样在利用掩模板制作信号走线后，距离所述第一弧形部分最近的虚拟走线与所述第一弧形部分之间的最小距离为4.5-5.5um，可以减少虚拟走线与第一信号走线之间的间距，进而缩减外围区 的面积，有利于实现显示产品的窄边框。
一些实施例中，每组虚拟走线包括相互平行的两条虚拟走线，相应地，如图6所示，每组虚拟掩模图形包括相互平行的两个虚拟掩模图形，为了减少虚拟掩模图形所占的面积，相邻所述虚拟掩模图形之间的距离不能过大；另外，为了避免虚拟走线之间残留金属层，相邻所述虚拟掩模图形之间的距离E不能过小，本实施例中，可以将相邻所述虚拟掩模图形之间的距离E设计为2.0-2.5um，既能够减少虚拟掩模图形所占的面积，又能够避免虚拟走线之间残留金属层。
一具体示例中，如图6所示，第四掩模图形04的线宽A可以为3.5um，虚拟掩模图形08与第四掩模图形04之间的最小距离B或C可以为4.0um，虚拟掩模图形08与一第一掩模图形01之间的最小距离D可以大于2.4um，一虚拟掩模图形08与另一第一掩模图形01之间的最小距离G可以为2.3um，另一虚拟掩模图形08与另一第一掩模图形01之间的最小距离H可以为2.0um，第三掩模图形03与另一第一掩模图形01之间的最小距离I可以为2.2um。
显示基板还包括与第一直线部分平行的走线，用于制作这部分走线的掩模图形的pitch F可以为1.8-2.0um。
一些实施例中，所述外围区还包括：
靠近所述显示区的中部的第二信号走线，所述第二信号走线包括：
第二弧形部分和与所述第二弧形部分连接的第三直线部分；
与所述第三直线部分平行的多个第三信号走线，所述第三信号走线位于所述第三直线部分远离所述显示区的一侧；
如图7所示，所述掩模板包括用以制作所述第二弧形部分的第五掩模图形05，所述掩模板还包括用以制作所述第三直线部分的第六掩模图形06和用以制作所述第三信号走线的第七掩模图形07。
如果第五掩模图形05的外侧边界的曲率半径过小，容易导致第二信号走线的弧形部分与相邻信号走线之间出现金属残留；如果第五掩模图形05的外侧边界的曲率半径过大，容易导致第二信号走线的弧形部分与相邻信号走线 之间的间距过大，外围区信号走线需要占据比较大的面积，不利于实现显示产品的窄边框。因此，本实施例中，将第五掩模图形05的内侧边界的曲率半径设计为3.5-4.5um，第五掩模图形05的外侧边界的曲率半径设计为6-8um，既可以保证第二信号走线的弧形部分与相邻信号走线之间不易出现金属残留，又可以避免外围区信号走线占据比较大的面积，有利于实现显示产品的窄边框。
一具体示例中，第五掩模图形05的内侧边界的曲率半径可以为4um，第五掩模图形05的外侧边界的曲率半径可以为6um。
一些实施例中，所述第六掩模图形06的线宽比所述第七掩模图形07的线宽大0.18-0.22um，这样可以保证形成的第三直线部分的线宽与第三信号走线的线宽基本相等。如果所述第六掩模图形06的线宽比所述第七掩模图形07的线宽大的过多，比如大于0.2um或0.3um，会使得第三直线部分的线宽与第三信号走线之间产生残留的金属层；如果第六掩模图形06的线宽比所述第七掩模图形07的线宽大的过少，比如大于0.01um，则起不到补偿的效果，第三直线部分的线宽仍然会比较小，有断线的风险。一具体示例中，第六掩模图形06的线宽比所述第七掩模图形07的线宽大0.2um。
一具体示例中，如图7所示，第五掩模图形05的线宽J可以为3.5um，第五掩模图形05与第七掩模图形07之间的最小距离K可以为2.2um。
显示基板还包括punch区域，punch区域是用以放置感光器件的区域，在punch区域周围布置有信号走线，掩模板还包括用以制作punch区域周围信号走线的掩膜图形09，一具体示例中，如图8所示，为了压缩punch区域的信号走线的pitch，虚拟掩模图形08与相邻的掩模图形09之间的最小距离L和M可以为3.0um，虚拟走线的pitch N可以为2.4-3.3um，信号走线对应的掩模图形09的pitch P可以为2.3-3.3um。最外侧的信号走线处空白区域较大，曝光显影时会使得最外侧的信号走线的线宽偏细，所以需要对最外侧信号走线的线宽进行补偿，可以增加对应最外侧信号走线的最外侧的掩模图形09的线宽，使得该部分掩模图形09的线宽相比其他掩模图形的线宽增加0.18-0.22um，比如可以为0.2um。
相关技术中，在制作窄边框显示产品时，需要通过两次构图工艺形成栅金属层的图形，包括：通过一次构图工艺采用湿刻+干刻的工艺形成显示区的栅金属层图形，另外，由于外围区的面积比较小，精度要求高，需要通过另一次构图工艺采用刻蚀Bias偏小的干刻工艺形成外围区的栅金属层图形，这样就增加了显示基板的制作时间，提高了显示基板的制作成本。本实施例中，通过对掩模板进行设计、在显影过程中补充显影液，能够降低湿刻+干刻的工艺的刻蚀Bias，这样可以通过一次构图工艺形成所述显示区与所述外围区的栅金属层的图形，即通过一次构图工艺采用湿刻+干刻的工艺形成显示区和外围区的栅金属层图形，这样就减少了显示基板的制作时间，降低了显示基板的制作成本。
其中，在通过一次构图工艺采用湿刻+干刻的工艺形成显示区和外围区的栅金属层图形时，在栅金属层上涂覆一层光刻胶，对光刻胶进行曝光显影后形成光刻胶的图形，以光刻胶的图形为掩模，对栅金属层进行刻蚀，初步形成栅金属层的图形，但此时形成的栅金属层的图形边缘的坡度角比较大，因此，后续再通过干法刻蚀来对栅金属层的图形进行修整，降低栅金属层的图形边缘的坡度角。同时，通过干法刻蚀还可以对显示基板上已形成的有源层的图形进行掺杂处理，提高有源层的导电性能。
本公开的实施例还提供了一种显示基板，采用上述的显示基板的制作方法制作得到。
本实施例中，显示基板的制作过程中省去对光刻胶的图形进行烘烤的步骤，这样形成的光刻胶的图形的边缘的坡度角较小，以这样的光刻胶的图形为掩模，对栅金属层进行刻蚀后得到的信号走线(采用栅金属层制作)的坡度角也比较小，这样能够优化信号走线上覆盖的层间绝缘层的形貌，使得层间绝缘层的表面比较平整，避免层间绝缘层表面出现源漏金属层残留，有利于实现显示产品的窄边框。
一具体示例中，对光刻胶的图形进行烘烤后，再利用光刻胶的图形为掩模，对栅金属层进行刻蚀后得到的信号走线的坡度角平均值为57.8°，在其他工艺参数不变的情况下，省去对光刻胶的图形进行烘烤的步骤，利用光刻胶 的图形为掩模，对栅金属层进行刻蚀后得到的信号走线的坡度角为36.9-53.7°，平均值为46.2°，可以看出，本实施例的技术方案能够大大降低信号走线的坡度角。
本实施例中，在对金属层进行刻蚀时，可以先对金属层进行湿法刻蚀，然后再对金属层进行干法刻蚀，在对金属层进行湿法刻蚀后，形成的信号走线的坡度角比较大，因此，后续可以利用干法刻蚀对信号走线的形貌进行修饰，降低信号走线的坡度角。
一些实施例中，如图5所示，所述显示基板包括显示区和环绕显示区设置的外围区，所述外围区包括靠近所述显示区的边缘部分的弧形拐角区W，所述弧形拐角区设置有第一信号走线，所述第一信号走线包括第一直线部分、第二直线部分和连接所述第一直线部分和所述第二直线部分的第一弧形部分；
一些实施例中，如图9所示，所述外围区包括靠近所述显示区的边缘部分的弧形拐角区，所述弧形拐角区设置有第一信号走线，所述第一信号走线包括第一直线部分、第二直线部分和连接所述第一直线部分和所述第二直线部分的第一弧形部分21；
如图6所示，用以制作外围区信号走线的所述掩模板包括用以制作所述第一弧形部分的第一掩模图形01，所述第一掩模图形01的内侧边界的曲率半径为3.5-4.5um，所述第一掩模图形01的外侧边界的曲率半径为6-8um。
如果第一掩模图形01的外侧边界的曲率半径过小，容易导致第一信号走线的弧形部分与相邻信号走线之间出现金属残留；如果第一掩模图形01的外侧边界的曲率半径过大，容易导致第一信号走线的弧形部分与相邻信号走线之间的间距过大，外围区信号走线需要占据比较大的面积，不利于实现显示产品的窄边框。因此，本实施例中，将第一掩模图形01的内侧边界的曲率半径设计为3.5-4.5um，所述第一掩模图形01的外侧边界的曲率半径设计为6-8um，既可以保证第一信号走线的弧形部分与相邻信号走线之间不易出现金属残留，又可以避免外围区信号走线占据比较大的面积，有利于实现显示产品的窄边框。
一具体示例中，第一掩模图形01的内侧边界的曲率半径可以为4um，所述第一掩模图形01的外侧边界的曲率半径可以为6um。采用掩模板制作第一信号走线后，如图9所示，所述第一弧形部分21的内侧边界的曲率半径为3.5-4.5um，所述第一弧形部分21的外侧边界的曲率半径为6-8um。具体地，所述第一弧形部分21的内侧边界的曲率半径可以为4um，所述第一弧形部分21的外侧边界的曲率半径可以为6um。
一些实施例中，如图9所示，所述第一直线部分包括靠近所述第一弧形部分的第一部分22和位于所述第一部分22远离所述第一弧形部分21一侧的第二部分23，如图6所示，所述掩模板包括用以制作所述第一部分的第二掩模图形02和用以制作所述第二部分的第三掩模图形03。
如图6所示，所述掩模板包括用以制作所述虚拟走线的虚拟掩模图形08和用以制作所述第二直线部分的第四掩模图形04，虚拟掩模图形08与第二掩模图形02的延伸方向相同或大致相同；
如果第二掩模图形02和第三掩模图形03的线宽相等，由于第二掩模图形02与虚拟掩模图形08的距离比较近，在利用掩模板对光刻胶进行曝光显影后，以光刻胶的图形为掩模对金属层进行刻蚀形成信号走线后，容易导致第一部分的线宽小于第二部分的线宽，因此，需要对第二掩模图形02和第三掩模图形03进行设计，来对第一部分的线宽进行补偿。
一些实施例中，所述第二掩模图形02的线宽比所述第三掩模图形03的线宽大0.08-0.12um，这样可以保证形成的第一部分的线宽与第二部分的线宽基本相等。如果所述第二掩模图形的线宽比所述第三掩模图形的线宽大的过多，比如大于0.2um或0.3um，会使得第一部分与虚拟走线之间产生残留的金属层；如果所述第二掩模图形的线宽比所述第三掩模图形的线宽大的过少，比如大于0.01um，则起不到补偿的效果，第一部分的线宽仍然会比较小，有断线的风险。一具体示例中，第二掩模图形02的线宽可以比第三掩模图形03的线宽大0.1um。
一具体示例中，在利用掩模板对光刻胶进行曝光显影后，以光刻胶的图形为掩模对金属层进行刻蚀形成信号走线后，制作的显示基板上，第一部分 22的线宽与第二部分23的线宽大致相等。
一些实施例中，为了减少虚拟走线与第一信号走线之间的间距，进而缩减外围区的面积，可以对虚拟掩模图形的尺寸和位置进行设计，对虚拟掩模图形进行延伸，降低虚拟掩模图形与第一掩模图形和第四掩模图形之间的距离，距离所述第一掩模图形最近的虚拟掩模图形与所述第一掩模图形之间的最小距离D可以为2.0-2.5um；所述虚拟掩模图形与所述第四掩模图形之间的最小距离B或C可以为2.0-2.5um。
一具体示例中，利用掩模板制作信号走线后，如图9所示，距离所述第一弧形部分21最近的虚拟走线28与所述第一弧形部分21之间的最小距离D1为4.5-5.5um，可以减少虚拟走线28与第一信号走线之间的间距，进而缩减外围区的面积，有利于实现显示产品的窄边框。
一些实施例中，如图9所示，每组虚拟走线包括相互平行的两条虚拟走线28，相应地，如图6所示，每组虚拟掩模图形包括相互平行的两个虚拟掩模图形，为了减少虚拟掩模图形所占的面积，相邻所述虚拟掩模图形之间的距离不能过大；另外，为了避免虚拟走线之间残留金属层，相邻所述虚拟掩模图形之间的距离不能过小，本实施例中，可以将相邻所述虚拟掩模图形之间的距离设计为2.0-2.5um，既能够减少虚拟掩模图形所占的面积，又能够避免虚拟走线之间残留金属层。
如图9所示，在利用掩模板对光刻胶进行曝光显影后，以光刻胶的图形为掩模对金属层进行刻蚀形成信号走线后，制作的显示基板上，相邻虚拟走线28之间的距离E1为2.0-2.5um。
一具体示例中，如图9所示，第二直线部分24的线宽A1可以为3.5um，虚拟走线28与第二直线部分24之间的最小距离B1或C1可以为4.0um，虚拟走线28与一第一弧形部分21之间的最小距离D1可以大于2.4um，一虚拟走线28与另一第一弧形部分21之间的最小距离G1可以为2.3um，另一虚拟走线28与另一虚拟走线28之间的最小距离H1可以为2.0um，第二部分23与另一虚拟走线28之间的最小距离I1可以为2.2um。
显示基板还包括与第一直线部分平行的走线，如图9所示，这部分走线 的pitch F1可以为1.8-2.0um。
一些实施例中，如图10所示，所述外围区还包括：
靠近所述显示区的中部的第二信号走线，所述第二信号走线包括：
第二弧形部分25和与所述第二弧形部分连接的第三直线部分26；
与所述第三直线部分26平行的多个第三信号走线27，所述第三信号走线27位于所述第三直线26部分远离所述显示区的一侧；
如图7所示，所述掩模板包括用以制作所述第二弧形部分的第五掩模图形05，所述掩模板还包括用以制作所述第三直线部分的第六掩模图形06和用以制作所述第三信号走线的第七掩模图形07。
如果第五掩模图形05的外侧边界的曲率半径过小，容易导致第二信号走线的弧形部分与相邻信号走线之间出现金属残留；如果第五掩模图形05的外侧边界的曲率半径过大，容易导致第二信号走线的弧形部分与相邻信号走线之间的间距过大，外围区信号走线需要占据比较大的面积，不利于实现显示产品的窄边框。因此，本实施例中，将第五掩模图形05的内侧边界的曲率半径设计为3.5-4.5um，第五掩模图形05的外侧边界的曲率半径设计为6-8um，既可以保证第二信号走线的弧形部分与相邻信号走线之间不易出现金属残留，又可以避免外围区信号走线占据比较大的面积，有利于实现显示产品的窄边框。
在利用掩模板对光刻胶进行曝光显影后，以光刻胶的图形为掩模对金属层进行刻蚀形成信号走线后，制作的显示基板上，所述第二弧形部分25的内侧边界的曲率半径为3.5-4.5um，所述第二弧形部分25的外侧边界的曲率半径为6-8um。
一具体示例中，第二弧形部分25的内侧边界的曲率半径可以为4um，第二弧形部分25的外侧边界的曲率半径可以为6um。
一些实施例中，所述第六掩模图形06的线宽比所述第七掩模图形07的线宽大0.18-0.22um，这样可以保证形成的第三直线部分26的线宽与第三信号走线27的线宽大致相等。
一具体示例中，如图10所示，第二弧形部分25的线宽J1可以为3.5um， 第二弧形部分25与第三信号走线27之间的最小距离K1可以为2.2um。
显示基板还包括punch区域，punch区域是用以放置感光器件的区域，在punch区域周围布置有信号走线，掩模板还包括用以制作punch区域周围信号走线的掩膜图形09，一具体示例中，如图11所示，为了压缩punch区域的信号走线的pitch，虚拟走线28与相邻的信号走线29之间的最小距离L1和M1可以为3.0um，虚拟走线的pitch N1可以为2.4-3.3um，信号走线29的pitch P1可以为2.3-3.3um。
本公开的实施例还提供了一种显示装置，包括上述的显示基板。
该显示装置包括但不限于：射频单元、网络模块、音频输出单元、输入单元、传感器、显示单元、用户输入单元、接口单元、存储器、处理器、以及电源等部件。本领域技术人员可以理解，上述显示装置的结构并不构成对显示装置的限定，显示装置可以包括上述更多或更少的部件，或者组合某些部件，或者不同的部件布置。在本公开实施例中，显示装置包括但不限于显示器、手机、平板电脑、电视机、可穿戴电子设备、导航显示设备等。
所述显示装置可以为：电视、显示器、数码相框、手机、平板电脑等任何具有显示功能的产品或部件，其中，所述显示装置还包括柔性电路板、印刷电路板和背板。
需要说明，本说明书中的各个实施例均采用递进的方式描述，各个实施例之间相同相似的部分互相参见即可，每个实施例重点说明的都是与其他实施例的不同之处。尤其，对于实施例而言，由于其基本相似于产品实施例，所以描述得比较简单，相关之处参见产品实施例的部分说明即可。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、 “右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
可以理解，当诸如层、膜、区域或基板之类的元件被称作位于另一元件“上”或“下”时，该元件可以“直接”位于另一元件“上”或“下”，或者可以存在中间元件。
在上述实施方式的描述中，具体特征、结构、材料或者特点可以在任何的一个或多个实施例或示例中以合适的方式结合。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (17)

  1. 一种显示基板的制作方法，其特征在于，包括：
    在衬底基板上形成金属层；
    在所述金属层上形成光刻胶层；
    利用掩模板对所述光刻胶层进行曝光；
    对曝光后的所述光刻胶层进行显影，形成光刻胶的图形；
    省去对所述光刻胶的图形进行烘烤的步骤，以所述光刻胶的图形为掩模，对所述金属层进行刻蚀，形成信号走线。
  2. 根据权利要求1所述的显示基板的制作方法，其特征在于，形成信号走线之后，所述方法还包括灰化所述光刻胶，灰化所述光刻胶采用的偏压功率为3500-6000W。
  3. 根据权利要求1所述的显示基板的制作方法，其特征在于，灰化所述光刻胶采用的刻蚀气体为氧气，气体流量为800-1000sccm。
  4. 根据权利要求1所述的显示基板的制作方法，其特征在于，对曝光后的所述光刻胶层进行显影包括：
    在显影过程中，向形成有光刻胶的衬底基板表面多次补充显影液。
  5. 根据权利要求4所述的显示基板的制作方法，其特征在于，补充显影液的次数为3-5次。
  6. 根据权利要求5所述的显示基板的制作方法，其特征在于，在显影过程执行一半之前，向形成有光刻胶的衬底基板表面补充2-3次显影液。
  7. 根据权利要求1所述的显示基板的制作方法，其特征在于，所述显示基板包括显示区和环绕显示区设置的外围区，所述外围区包括靠近所述显示区的边缘部分的弧形拐角区，所述弧形拐角区设置有第一信号走线，所述第一信号走线包括第一直线部分、第二直线部分和连接所述第一直线部分和所述第二直线部分的第一弧形部分；
    所述掩模板包括用以制作所述第一弧形部分的第一掩模图形，所述第一掩模图形的内侧边界的曲率半径为3.5-4.5um，所述第一掩模图形的外侧边界 的曲率半径为6-8um。
  8. 一种显示基板，其特征在于，采用权利要求1-7中任一项所述的显示基板的制作方法制作得到。
  9. 根据权利要求8所述的显示基板，其特征在于，所述信号走线的坡度角为36.9-53.7°。
  10. 根据权利要求8所述的显示基板，其特征在于，所述显示基板包括显示区和环绕显示区设置的外围区，所述外围区包括靠近所述显示区的边缘部分的弧形拐角区，所述弧形拐角区设置有第一信号走线，所述第一信号走线包括第一直线部分、第二直线部分和连接所述第一直线部分和所述第二直线部分的第一弧形部分；
    所述第一弧形部分的内侧边界的曲率半径为3.5-4.5um，所述第一弧形部分的外侧边界的曲率半径为6-8um。
  11. 根据权利要求10所述的显示基板，其特征在于，所述第一直线部分包括靠近所述第一弧形部分的第一部分和位于所述第一部分远离所述第一弧形部分一侧的第二部分，所述第一部分的线宽与所述第二部分线宽大致相等。
  12. 根据权利要求10所述的显示基板，其特征在于，所述显示基板还包括位于相邻两条第一信号走线之间的一组虚拟走线，每组虚拟走线包括相互平行的至少两条虚拟走线，所述虚拟走线的延伸方向与所述第一直线部分的延伸方向相同或大致相同；
    距离所述第一弧形部分最近的虚拟走线与所述第一弧形部分之间的最小距离为4.5-5.5um。
  13. 根据权利要求12所述的显示基板，其特征在于，相邻虚拟走线之间的距离为2.0-2.5um。
  14. 根据权利要求12所述的显示基板，其特征在于，每组虚拟走线包括相互平行的两条虚拟走线。
  15. 根据权利要求12所述的显示基板，其特征在于，所述外围区还包括：
    靠近所述显示区的中部的第二信号走线，所述第二信号走线包括：
    第二弧形部分和与所述第二弧形部分连接的第三直线部分；
    所述第二弧形部分的内侧边界的曲率半径为3.5-4.5um，所述第二弧形部分的外侧边界的曲率半径为6-8um。
  16. 根据权利要求12所述的显示基板，其特征在于，所述外围区还包括：
    靠近所述显示区的中部的第二信号走线，所述第二信号走线包括第二弧形部分和与所述第二弧形部分连接的第三直线部分；
    与所述第三直线部分平行的多个第三信号走线，所述第三信号走线位于所述第三直线部分远离所述显示区的一侧；
    所述第三信号走线的线宽与所述第三直线部分的线宽大致相等。
  17. 一种显示装置，其特征在于，包括如权利要求8-16中任一项所述的显示基板。
PCT/CN2022/078569 2022-03-01 2022-03-01 显示基板及其制作方法、显示装置 WO2023164793A1 (zh)

Priority Applications (2)

Application Number Priority Date Filing Date Title
PCT/CN2022/078569 WO2023164793A1 (zh) 2022-03-01 2022-03-01 显示基板及其制作方法、显示装置
CN202280000368.0A CN117016055A (zh) 2022-03-01 2022-03-01 显示基板及其制作方法、显示装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2022/078569 WO2023164793A1 (zh) 2022-03-01 2022-03-01 显示基板及其制作方法、显示装置

Publications (1)

Publication Number Publication Date
WO2023164793A1 true WO2023164793A1 (zh) 2023-09-07

Family

ID=87882749

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2022/078569 WO2023164793A1 (zh) 2022-03-01 2022-03-01 显示基板及其制作方法、显示装置

Country Status (2)

Country Link
CN (1) CN117016055A (zh)
WO (1) WO2023164793A1 (zh)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW479277B (en) * 2001-05-11 2002-03-11 Taiwan Semiconductor Mfg Photoresist removing method
CN107367908A (zh) * 2017-08-18 2017-11-21 武汉华星光电半导体显示技术有限公司 曝光光罩以及光阻材料图形化方法
CN110083021A (zh) * 2019-04-08 2019-08-02 深圳市华星光电技术有限公司 一种基板显影方法和基板显影装置
CN112053632A (zh) * 2020-09-16 2020-12-08 京东方科技集团股份有限公司 显示装置及其制作方法
CN113031387A (zh) * 2021-02-26 2021-06-25 合肥维信诺科技有限公司 一种掩膜版及显示面板的制作方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW479277B (en) * 2001-05-11 2002-03-11 Taiwan Semiconductor Mfg Photoresist removing method
CN107367908A (zh) * 2017-08-18 2017-11-21 武汉华星光电半导体显示技术有限公司 曝光光罩以及光阻材料图形化方法
CN110083021A (zh) * 2019-04-08 2019-08-02 深圳市华星光电技术有限公司 一种基板显影方法和基板显影装置
CN112053632A (zh) * 2020-09-16 2020-12-08 京东方科技集团股份有限公司 显示装置及其制作方法
CN113031387A (zh) * 2021-02-26 2021-06-25 合肥维信诺科技有限公司 一种掩膜版及显示面板的制作方法

Also Published As

Publication number Publication date
CN117016055A (zh) 2023-11-07

Similar Documents

Publication Publication Date Title
WO2018176760A1 (zh) 一种柔性显示面板、显示装置及柔性显示面板的制作方法
JP4728292B2 (ja) 薄膜トランジスタ液晶ディスプレイのアレイ基板構造及びその製造方法
US8952384B2 (en) TFT, mask for manufacturing the TFT, array substrate and display device
US20200176604A1 (en) Thin film transistor, method of fabricating the same, array substrate and display device
CN106019751B (zh) 阵列基板及其制造方法、显示装置
US11087985B2 (en) Manufacturing method of TFT array substrate
US9899430B2 (en) GOA unit and method for producing the same, gate driver circuit
US20230180548A1 (en) Chip-on-film structure, display apparatus and method for manufacturing same
WO2018205604A1 (zh) 显示装置、阵列基板及其制造方法
US11145682B2 (en) Array substrate and method for fabricating the same, display panel, display device
US20220077200A1 (en) Display panel, manufacturing method thereof, and display device
WO2022156038A1 (zh) 显示面板以及显示面板的制作方法
TWI571912B (zh) 觸控面板邊緣走線的製作方法、具有該邊緣走線的觸控面板及觸控顯示裝置
TWI374504B (en) System for displaying images and fabricating method thereof
US11094789B2 (en) Thin film transistor and method for manufacturing the same, array substrate, and display device
CN110794630A (zh) 一种阵列基板及其制造方法
WO2023164793A1 (zh) 显示基板及其制作方法、显示装置
TWI423391B (zh) 共通線結構與顯示面板及其製作方法
US9806109B2 (en) Half tone mask plate and method for manufacturing array substrate using the same
US11327401B2 (en) Display substrate, method for preparing the same, and display device
US10942403B2 (en) Display substrate and display apparatus
CN110690231A (zh) 显示背板及其制作方法、显示面板和显示装置
CN107170751B (zh) 阵列基板及其制造方法、显示装置
US10700105B2 (en) Array substrate and method for manufacturing the same, display panel and display device
WO2023141761A1 (zh) 显示基板及其制作方法、显示装置

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 202280000368.0

Country of ref document: CN