W277 五、發明說明（1) 發明領域： 去關於一種半導體製程，特別是有關於-種 去除光阻並降低對介電層損害。 有效 相關技術說明： 一般而言，在半導體製程中，去 除液溶解光阻圖案的濕式光：二 利ΐίίί'圖案使光阻圖案被高能量的離子轟除，或者 剝除的乾式光阻剝除法。 兄而乳礼的％楗中破 々ϋ由光阻去除液之濕式光阻剝除法或者電漿轟擊的# $内連線表面或者接觸窗或溝槽之形化 大^之主要步驟。然而，在雙鑲嵌（dual 製程中’由於習知灰化法是使光阻在充滿氧 ^间溫南壓環境下，例如在200 1以上及i t〇rr以上的 ，件下被氧化掉並隨著抽氣系統將其抽離，因此高溫的氧 刻製程之後所產生的含敦副產。口。，例如训，將容 易與二電層，例如與含Si-CH3的介電材料發生反應，而姓 d到；丨電層造成接觸窗及溝槽的蝕刻輪廓（pr〇file )不 佳並因氧離子作用而破壞介電層的結構使得介電常數增加 而增加時間延遲（RC delay )效應。 為使此習知灰化製程之缺點更為明顯，於第丨A到丨B圖 中係繪示出定義完雙鑲嵌結構之後光阻灰.化之步驟。首W277 V. Description of the Invention (1) Field of the Invention: It is about a semiconductor process, and in particular, it relates to a method of removing photoresist and reducing damage to a dielectric layer. Effective related technical description: Generally speaking, in the semiconductor manufacturing process, the wet type light that dissolves the photoresist pattern is removed by liquid: Erli's pattern causes the photoresist pattern to be bombarded by high-energy ions, or it is stripped dry photoresist. division. Brother and Milky's% 楗 Break 主要 The main steps of forming the inner wiring surface or the contact window or groove by the photoresist stripping method of the photoresist removal solution or the plasma bombardment. However, in the dual damascene (dual process), because the conventional ashing method is used to make the photoresist in an environment full of oxygen and temperature, such as above 200 1 and it 0 rr, the parts are oxidized and follow the It is pumped away by the pumping system, so the by-products produced by the high temperature oxygen etching process. For example, it will easily react with the second electric layer, such as with the Si-CH3 containing dielectric material, The surnames d to 丨 the electrical layer causes poor etching profile (pr0file) of contact windows and trenches and destroys the structure of the dielectric layer due to the action of oxygen ions, which increases the dielectric constant and increases the time delay (RC delay) effect. In order to make the shortcomings of this conventional ashing process more obvious, the steps of photoresist ashing after the definition of the dual damascene structure are shown in Figures 丨 A to 丨 B. First
479277 五、發明說明（2) ' 先’請參照第1 A圖，圖中係繪示出雙鑲嵌結構中進行習知 灰化製程以去除光阻之示意圖。標號丨〇 2所代表的是位在 半導體基底100中的金屬内連線，標號1〇4所代表的是位在 半導體基底1 0 0上的鍅刻終止層而標號1 〇 6、1 〇 7分別代表 的則是介電層及介電質抗反射層（dielectric anti — ref lection coat，DARC )。此步驟係在定義出一溝槽 l〇6a及一接觸窗106b之後，以灰化法去除光阻圖案ι〇8。 山接著，請參照第1B圖，圖中係繪示出去除光阻後之雙 ，嵌結構示意圖。於充滿氧氣的環境中進行灰化 =圖，被灰化除去 '然而，由於反應氣體及含氣的 電示）與溝槽1(^及接觸窗mb内壁的介 二m 接觸窗i〇6b内壁受到敍刻而造成 蝕刻輪廓（profUe)不佳的問題，如圖 ，氧離子的作用將使介電層1〇6 改。同時 吊數增加，造成元件時間延遲的增加。 便；丨電 有鑑於此，本發明提出一種去的、 用氧氣、氮氣及一氧化碳氣體作^ 的方法，其中利 一 30 0到7〇〇 W的偏壓功率。此二似軋體，期間並施加 介電層的損害、防止介電常=阻、降低 蝕刻輪廓。 9加以及具有良好的溝槽 發明概述： 為解決上述之問題，本發明 光阻之方法，其中利用氧氣、氮 、备；提供一種去除 氮乳及一氧化碳氣體作為反479277 V. Description of the invention (2) 'First' Please refer to FIG. 1A, which shows a schematic diagram of a conventional ashing process to remove photoresist in a dual mosaic structure. Reference numeral 丨 〇2 represents the metal interconnects located in the semiconductor substrate 100, reference numeral 104 represents the engraved termination layer located on the semiconductor substrate 100, and reference numerals 〇06, 〇7 They respectively represent a dielectric layer and a dielectric anti-reflective coat (DARC). This step is to remove the photoresist pattern ι08 by ashing after defining a trench 106a and a contact window 106b. Next, please refer to FIG. 1B, which shows a schematic diagram of the embedded structure after removing the photoresist. Ashing in an oxygen-filled environment = Figure, removed by ashing. However, due to the reaction gas and gas-containing electrical indication) and the groove 1 (^ and the inner wall of the contact window mb, the inner wall of the contact window i〇6b). The problem of poor etch profile (profUe) due to engraving, as shown in the figure, the effect of oxygen ions will change the dielectric layer 106. At the same time, the increase in the number of suspensions will increase the time delay of the device. Therefore, the present invention proposes a method using oxygen, nitrogen, and carbon monoxide gas, in which a bias power of 300 to 700 W is used. These two are similar to a rolled body, and the dielectric layer is damaged during the process. , Prevent dielectric constant = resistance, reduce the etching profile. 9 plus and have a good trench. Summary of the invention: In order to solve the above problems, the photoresist method of the present invention, which uses oxygen, nitrogen, and preparation; Carbon monoxide gas
479277 五、發明說明（3) 應氣體可防止灰化處理期間對低介電材料的疒金。 本發明之另一目的在於提供一種去 中在灰化處理進行期間，施加一偏壓功率， f ’其 阻並獲得良好的蝕刻輪廓。 有效去除光 根據上述之目的’本發明提供—種去除光阻之方法， 匕括下列步驟：（a)提供一半導體基底’依 形成有-絕緣層、-介電質抗反射層（Darg)及一光^且序 層j (b )圖案化光阻層並蝕刻絕緣層以定義出至少一 槽，（c )灰化去除蝕刻後所剩餘的光阻圖案丨其中 j C )係利用氧氣及氮氣之混合氣體作為反應氣體 並施加一300到700 W的偏壓功率。其反應溫度及壓力分別 為60C以下及1〇〇 mtorr以下。再者，卜、十，从 尸 ^ ^ r 丹肴，上述的反應氣體中 更加入一氧化碳氣體以有效降低對介電材料的損害。 、根據上述之目的，本發明提供另一種去除光^之方法 ，適用於一雙鑲嵌製程，包括下列步驟：提供一半 導體基底，此基底表面具有一内連線；（b)在基底上依 序形成-終止層、-介電層、—介電質抗反㈣（darc) 及一第一光阻層；（〇圖案化第一光阻層並蝕刻介電層 ，以定義出一接觸窗而露出終止層；（d)灰化去除蝕刻 後所剩餘的第一光阻圖案；（e)在接觸窗内部及介電層 表面形成一第二光阻層·， （ f )圖案化第二光阻層並蝕刻 介電層，以定義出一溝槽；（g )灰化去除蝕刻後所剩餘 的第二光阻圖案；（h )蝕刻終止層以露出内連線；其中 該步驟（d )及（g )係利用氧氣及氮氣之混合氣體作為反479277 V. Description of the invention (3) The application of gas can prevent the deposit of low dielectric materials during the ashing process. Another object of the present invention is to provide a method for removing a bias power during the ashing process, f 'which resists and obtains a good etching profile. Effectively remove light. According to the above-mentioned object, the present invention provides a method for removing photoresist, which includes the following steps: (a) Providing a semiconductor substrate according to the formation of-an insulating layer, a dielectric anti-reflection layer (Darg), and The photoresist layer j (b) is used to pattern the photoresist layer and etch the insulating layer to define at least one groove. (C) Ashing removes the remaining photoresist pattern after the etching. Among them, j C) uses oxygen and nitrogen. The mixed gas is used as a reaction gas and a bias power of 300 to 700 W is applied. The reaction temperature and pressure are 60C or lower and 100 mtorr or lower, respectively. In addition, Bu, X. From the corpse ^ ^ r Dan cuisine, the above reaction gas is further added with carbon monoxide gas to effectively reduce the damage to the dielectric material. According to the above purpose, the present invention provides another method for removing light, which is suitable for a dual damascene process, including the following steps: providing a semiconductor substrate having an interconnect on the surface of the substrate; (b) sequentially on the substrate Forming a termination layer, a dielectric layer, a dielectric anti-darc (darc) and a first photoresist layer; (o patterning the first photoresist layer and etching the dielectric layer to define a contact window and The termination layer is exposed; (d) ashing removes the first photoresist pattern remaining after etching; (e) forming a second photoresist layer inside the contact window and the surface of the dielectric layer; (f) patterning the second photoresist Resist and etch the dielectric layer to define a trench; (g) ashing to remove the second photoresist pattern remaining after the etching; (h) etching the stop layer to expose the interconnects; wherein step (d) And (g) is the use of a mixed gas of oxygen and nitrogen as a reaction
H1 0503-6141TW ； TSMC2000-0817 ； spin.ptd 第6頁 479277 五、發明說明（4) 應氣體’期間並施加一 3〇〇到7〇〇 w的偏壓功率。再者，上 述的反應氣體中更加入一氧化碳氣體以有效降低對介電材 料的損害。 圖式之簡單說明： 為讓本發明之上述目的、特徵和優點能更明顯易懂， 下文特舉一較佳實施例，並配合所附圖式，作詳細說明如 下： 第1 A圖係繪示出雙鑲嵌結構中進行習知灰化製程以去 除光阻之示意圖。 第1B圖係繪示出去除光阻後之雙鑲嵌結構示意圖。 第2 A到2E圖繪示出雙鑲嵌製程中根據本發明實施例以 去除光阻之剖面圖。 [符號說明] 10、100〜半導體基底； 12、102〜内連線； 14、104〜終止層； 16、106〜介電層； 16b、106a〜溝槽； 16a、106b〜接觸窗； 18〜第一光阻層； 18a〜第一光阻圖案； 20〜第二光阻層； 20a〜第二光阻圖案； 107、17〜介電質抗反射層；1〇8〜光阻圖案。 較佳實施例之詳細說明： 以下配合第2A到2E圖說明本發明實施例之去除光阻的 方法，其繪示出雙鑲嵌製程中利用本發明以去除光阻之剖 面圖。H1 0503-6141TW; TSMC2000-0817; spin.ptd page 6 479277 5. Description of the invention (4) During the application of gas', a bias power of 300 to 700 w is applied. Furthermore, carbon monoxide gas is further added to the above-mentioned reaction gas to effectively reduce the damage to the dielectric material. Brief description of the drawings: In order to make the above-mentioned objects, features and advantages of the present invention more comprehensible, a preferred embodiment is given below and described in detail with the accompanying drawings as follows: FIG. 1A is a drawing A schematic diagram of a conventional ashing process to remove photoresist in a dual damascene structure is shown. FIG. 1B is a schematic diagram showing the dual mosaic structure after removing the photoresist. Figures 2A to 2E are cross-sectional views showing photoresist removal in a dual damascene process according to an embodiment of the present invention. [Symbol description] 10, 100 ~ semiconductor substrate; 12, 102 ~ interconnect; 14, 104 ~ termination layer; 16, 106 ~ dielectric layer; 16b, 106a ~ trench; 16a, 106b ~ contact window; 18 ~ First photoresist layer; 18a ~ first photoresist pattern; 20 ~ second photoresist layer; 20a ~ second photoresist pattern; 107, 17 ~ dielectric anti-reflection layer; 108 ~ photoresist pattern. Detailed description of the preferred embodiment: The method of removing photoresist according to the embodiment of the present invention will be described below with reference to FIGS. 2A to 2E. It illustrates a cross-sectional view of using the present invention to remove photoresist in a dual damascene process.
°5〇3-6l41TWF ； TSMC2000-0817 ； spin.ptd 第 7 頁 五、發明說明（5) 首先，請參昭^[ 9 Α κι , 一厶届ΗΠ、± ^…第2A圖’提供一半導體基底1 〇，其具有 ㈣上依序:成’例如：或紹，並在此半導體基 ^-ch3的一低介電材料且介電常數（"為2 間。 接下來明參照第2B圖，藉由一微影製程以圖案化第 :光阻•層18，並接著以一乾式蝕刻製程定義出一接觸窗 a以路出終止層i 4的表面。再者，根據本發明之去除光 阻的方法來對第—光阻層圖案1 8 a進行灰化處理以去除蝕 刻後所剩餘的第一光阻層圖案18a。其中，使用氧氣（〇2 )及鼠氣（N2)作為反應氣體以進行灰化，如第2β圖所示 立此處灰化處理的工作溫度在6 0 °C以下，以避免高溫環 兄下發生不必要的反應。再者，控制氧氣的流量在1 〇 〇到 400 seem的範圍，且氮氣的流量在到2〇〇 3(^讯的範圍並 使=作壓力維持在100 mtorr以下。相較於習知技術中， 氧氣流量為30 0 0 SCCnr以上、氮氣流量為2〇〇 sccm以上工 作，，在1 t〇rr以上，可有效地減少氣體的浪費及降低因 大量氧離子作用對介電層16造成Si-CH3結構減少而使介電 常數增加的不良影響。上述Si—CHS結構的減少係因為氧離 子置換甲基（CH3 )使整個介電材料之多孔性結構變得較 為緻密而使介電常數增加。另外，在灰化處理期間，施加 一偏壓功率，可使反應氣體中的離子受到磁場作用而能更 均勻地與光阻作用。相較於沒有施加偏壓功率的習知灰化° 5〇3-6l41TWF; TSMC2000-0817; spin.ptd Page 7 V. Description of the Invention (5) First, please refer to [9 Α κι, as shown in Figure 2A ', and provide a semiconductor The substrate 10 has a sequence on the substrate: for example, or a low dielectric material with a dielectric constant (" of 2) in the semiconductor substrate ^ -ch3. Next, refer to FIG. 2B. The first photoresist layer 18 is patterned by a lithography process, and then a contact window a is defined by a dry etching process to access the surface of the termination layer i 4. Furthermore, the light is removed according to the present invention. Ashing the first photoresist layer pattern 18a to remove the first photoresist layer pattern 18a remaining after the etching. Among them, oxygen (〇2) and rat gas (N2) are used as reaction gases. In order to perform ashing, as shown in FIG. 2β, the working temperature of the ashing treatment is below 60 ° C, so as to avoid unnecessary reactions at high temperature. Also, the oxygen flow rate is controlled to 1 〇〇 To the range of 400 seem, and the flow rate of nitrogen to the range of 2003 and the pressure maintained at 100 mtorr Compared with the conventional technology, working with an oxygen flow rate of 30,000 SCCnr or more and a nitrogen flow rate of 200 sccm or more can effectively reduce the waste of gas and reduce the action due to a large amount of oxygen ions above 1 t〇rr. The adverse effect of the decrease in the Si-CH3 structure and the increase in the dielectric constant on the dielectric layer 16. The decrease in the Si-CHS structure is due to the replacement of the methyl group (CH3) by oxygen ions to make the porous structure of the entire dielectric material relatively Dense and increase the dielectric constant. In addition, during the ashing process, the application of a bias power can make the ions in the reaction gas subject to a magnetic field to more uniformly interact with the photoresist. Compared with no bias power Habitual ashing
479277 五、發明說明（6) ί it的：：效$去除光阻而不留下殘留物且能夠減少終止 ；! π則ϊ 1而，本發明者發現，當所施加的偏壓功率 ί 阻殘留。相對地，若施加的偏壓功率太 電層16的表面會受到損害而產生微溝槽“ =Ch)或尖峰（spike)及介電常數的增加，對後續製 ::3二不2影響。因此’本發明實施例之較佳的偏壓功^ 疋在3 0 0到7 〇 〇 W的範圍。 午 接下來，請參照第2C圖，在介電層16的表面及接觸窗 aH塗佈H阻層20。接著，請參照第2D圖，同 『製程以圖案化第二光阻層20 =在接-觸窗16a上方定義出一溝槽16b，其寬度大= ”直徑’如第2c圖所示。同樣地，接著科用與去除 匕光阻圖㈣a相同的方法來對第二光阻圖細a進行-化處理以去除蝕刻後所剩餘的第二光阻圖案2〇&。 如先前所述，灰化處理時係使用氧氣（A )及氮 (N2 )作為反應氣體。然而，此處會再加入一氧化 )氣體（未繪示），其原因是在乾式蝕刻製程中，反應5 體所產生的含氟副產品會滯留於接觸窗16a及溝槽Bb ^ = 壁。當進行灰化處理時，會繼續蝕刻接觸窗16a及溝栌 的内壁而造成蝕刻輪廓（pr0f i i e )不佳的情形。因上 加入一氧化碳（CO)氣體來與含a的蝕刻副產品反庳’ 少氣滯留時間（retention time )以達到良好蝕刻^ ' (profile)的目的。最後，請參照第2£圖，藉由蝕 程去除位於接觸窗16a底部的終止層14以露出金屬内連線 479277 根據 少對介電 ，無需在 更可維持 欲製程為 用於I虫刻 雖然 限定本發 神和範圍 當視後附 本發明 層的損 灰化處 良好的 例，然 絕緣層 本發明 明，任 内，當 之申請 飾，因此本發明之保護範園 疋者為準。479277 V. Description of the invention (6) ί it: The effect of removing the photoresist without leaving a residue and reducing the termination; π is ϊ 1 and the inventor found that when the applied bias power ί resistance Residual. In contrast, if the bias voltage applied to the surface of the electrical layer 16 is damaged, micro-channels “= Ch” or spikes and an increase in the dielectric constant will have an impact on the subsequent system: 3: 3. Therefore, 'the preferred bias work of the embodiment of the present invention is in the range of 300 to 7000 W. Next, please refer to FIG. 2C, and apply a coating on the surface of the dielectric layer 16 and the contact window aH. H-resistance layer 20. Next, please refer to FIG. 2D, the same as the process of "patterning the second photoresistive layer 20 = a trench 16b is defined above the contact-contact window 16a, and its width is large =" diameter "as in 2c As shown. Similarly, the second photoresist pattern a is subjected to the same method as that used to remove the photoresist pattern ㈣a to remove the second photoresist pattern 20 & remaining after the etching. As described earlier, the ashing process uses oxygen (A) and nitrogen (N2) as reaction gases. However, another oxygen gas (not shown) is added here because the fluorine-containing by-products produced by the reaction body 5 are retained in the contact window 16a and the groove Bb in the dry etching process. When the ashing process is performed, the contact window 16a and the inner walls of the trenches will continue to be etched, resulting in a poor etching profile (pr0f i i e). Therefore, carbon monoxide (CO) gas is added to counteract the etching by-product containing a to reduce the gas retention time (retention time) to achieve the purpose of good etching ^ (profile). Finally, please refer to Fig. 2. The termination layer 14 located at the bottom of the contact window 16a is removed by an etching process to expose the metal interconnects 479277. According to the low dielectric pair, there is no need to maintain the desired process for I insect etching. The definition of the scope and scope of the invention should be regarded as a good example of the damaged ashing layer attached to the layer of the present invention. However, the insulation layer of the present invention is clear.
12而完成一雙鑲嵌結構。 〜玄除光阻的 害並保持低介 理後再加入去 蝕刻輪廓。另 而本發明並不 後去除光阻的 已以較佳實施 何熟習此項技 可作更動與潤 專利範圍所界 方法，可在灰 電常數，且可 除光阻殘留物 外，本發明實 受限於此，亦 步驟。 例接露如上， 藝者，在不脫 有效去除光阻 的清洗步驟， 施例係以雙鑲 即本發明 < 通 然其並非用以 離本發明之精12 and complete a double mosaic structure. ~ Remove the damage of photoresist and keep it low before adding to etch the contour. In addition, the present invention does not remove the photoresist. The familiar practice of this technique can be modified and implemented in a better way. It can be used to modify and limit the range of the patent. Limited to this, also steps. The example is as described above. In the cleaning step of effectively removing the photoresist without removing the photoresist, the example is a double setting, which is the invention < Of course, it is not used to separate the essence of the invention.