WO2023141761A1 - 显示基板及其制作方法、显示装置 - Google Patents

显示基板及其制作方法、显示装置 Download PDF

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Publication number
WO2023141761A1
WO2023141761A1 PCT/CN2022/073778 CN2022073778W WO2023141761A1 WO 2023141761 A1 WO2023141761 A1 WO 2023141761A1 CN 2022073778 W CN2022073778 W CN 2022073778W WO 2023141761 A1 WO2023141761 A1 WO 2023141761A1
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WIPO (PCT)
Prior art keywords
base substrate
signal line
connection line
groove
line
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PCT/CN2022/073778
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English (en)
French (fr)
Inventor
贾宜訸
王骁
丁向前
陈维涛
郭晖
刘海鹏
王勋
刘建涛
刘静
宋勇志
庞妍
Original Assignee
京东方科技集团股份有限公司
北京京东方显示技术有限公司
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Application filed by 京东方科技集团股份有限公司, 北京京东方显示技术有限公司 filed Critical 京东方科技集团股份有限公司
Priority to CN202280000059.3A priority Critical patent/CN117043673A/zh
Priority to US18/016,876 priority patent/US20240153968A1/en
Priority to PCT/CN2022/073778 priority patent/WO2023141761A1/zh
Publication of WO2023141761A1 publication Critical patent/WO2023141761A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H01L27/1244—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits for preventing breakage, peeling or short circuiting
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods

Definitions

  • the present disclosure relates to the field of display technology, in particular to a display substrate, a manufacturing method thereof, and a display device.
  • the technical problem to be solved in the present disclosure is to provide a display substrate, a manufacturing method thereof, and a display device, which can avoid abnormal images.
  • a display substrate including a base substrate, the base substrate includes a display area and a peripheral area surrounding the display area, wherein the display substrate includes:
  • a first insulating layer located on a side of the first signal line away from the base substrate
  • the first signal line and the second signal line are connected by a connecting wire, and the connecting wire is located on a side of the first insulating layer away from the base substrate, and the first insulating layer is far away from the substrate.
  • a groove is formed on one side of the base substrate, the depth of the groove is greater than a preset threshold, and the orthographic projection of the connecting trace on the base substrate is the same as that of the groove on the substrate. orthographic overlay on the substrate;
  • connection routing includes:
  • a first connection line includes a first part and a second part, wherein the first part covers the bottom and side walls of the groove, and the second part covers the first insulating layer and is located outside the groove area.
  • the display substrate further includes:
  • a second insulating layer located on a side of the first connection line away from the base substrate
  • connection routing also includes:
  • Two connection lines are used to connect the first connection line with the first signal line and the second signal line, and the orthographic projection of the second connection line on the base substrate is the same as that of the groove on the The orthographic projections on the base substrate do not overlap, and the depth of the via hole is smaller than the groove depth of the groove.
  • the first orthographic projection of the first portion on the base substrate is located within the orthographic projection of the groove on the base substrate, and the second portion is on the base substrate
  • the second orthographic projection of the groove is located outside the orthographic projection of the groove on the base substrate, and the area ratio of the first orthographic projection to the second orthographic projection is 6:1 ⁇ 1:1.
  • the extending direction of the first connection line is parallel to the extending direction of the first signal line.
  • the distance between adjacent first connecting lines is 10-15um.
  • the second connection line includes a hollow area, and the extension direction of the hollow area is parallel to the extension direction of the second connection line.
  • the second connection line includes a third part and a fourth part
  • the third orthographic projection of the third part on the base substrate is located at the position of the first connection line on the base substrate.
  • the fourth orthographic projection of the fourth part on the base substrate is located outside the orthographic projection of the first connecting line on the base substrate, and the third orthographic projection and the The area ratio of the fourth orthographic projection is 1:20-1:25.
  • the second connection line includes a fifth part and a sixth part
  • the fifth orthographic projection of the fifth part on the base substrate is located at the position of the via hole on the base substrate.
  • the sixth orthographic projection of the sixth portion on the base substrate is located outside the orthographic projection of the via hole on the base substrate, and the fifth orthographic projection is different from the sixth orthographic projection
  • the projected area ratio is 1:20-1:25.
  • the second connecting line includes a seventh part and an eighth part, the seventh part connects the first connecting line and the first signal line, and the eighth part connects the first The connection line and the second signal line, the extension direction of the seventh part is parallel to the first signal line, the eighth part is L-shaped, and the eighth part includes The first subsection and the second subsection parallel to the second signal line.
  • the via hole is a rectangular via hole with a side length of 6-8um.
  • the preset threshold is 2um.
  • the connecting wires are made of transparent conductive materials.
  • the second connection line is of the same layer and material as the pixel electrode of the display substrate; and/or,
  • the first connection line is of the same layer and material as the common electrode of the display substrate.
  • the first signal line is a clock signal line of the gate drive unit
  • the second signal line is a signal line in a fan-shaped area.
  • An embodiment of the present disclosure also provides a display device, including the above-mentioned display substrate.
  • Embodiments of the present disclosure also provide a method for manufacturing a display substrate, the display substrate comprising a base substrate, the base substrate comprising a display area and a peripheral area surrounding the display area, the method comprising:
  • connection trace connecting the first signal line and the second signal line
  • the connection trace is located on a side of the first insulating layer away from the base substrate, and the first insulating layer is far away from the
  • a groove is formed on one side of the base substrate, the groove depth of the groove is greater than a preset threshold, and the orthographic projection of the connecting trace on the base substrate is the same as that of the groove on the base substrate. Orthographic overlap on ;
  • Forming the connection routing includes:
  • a first conductive layer is formed on the side of the first insulating layer away from the base substrate, a photoresist pattern is formed on the first conductive layer, and the photoresist pattern is overexposed, so as to The pattern of the photoresist is a mask, and the first conductive layer is etched to form a first connection line, the first connection line includes a first part and a second part, wherein the first part covers the groove The bottom and the sidewall, the second part covers the area of the first insulating layer outside the groove.
  • the method also includes:
  • a second insulating layer is formed on the side of the first connecting line away from the base substrate, and the second insulating layer is patterned to form a via hole exposing the first connecting line, and the via hole is having a depth less than the groove depth of the groove;
  • Forming the connection routing also includes:
  • a second connection line is formed on a side of the second insulating layer away from the base substrate, and the second connection line is connected to the first connection line through a via hole penetrating through the second insulating layer.
  • the second connection line is used to connect the first connection line with the first signal line and the second signal line, and the orthographic projection of the second connection line on the base substrate is the same as that of the groove.
  • the orthographic projections on the base substrate do not overlap, and the depth of the via hole is smaller than the groove depth of the groove.
  • the first signal line and the second signal line are connected through the first connection line, and the first connection line does not include a hollow area.
  • the first connection line is formed, it is possible to The photoresist is exposed to form the first connection line, so as to prevent the conductive film layer from remaining in the groove, and then prevent the residual conductive film layer from short-circuiting different signal lines together, avoiding abnormal pictures, and ensuring good display products. Rate.
  • 1 is a schematic plan view showing a substrate
  • FIG. 2 and FIG. 3 are schematic diagrams of related art display substrates
  • FIG. 4 is a schematic plan view of a second transparent conductive layer
  • 5-13 are schematic diagrams of manufacturing a display substrate according to an embodiment of the present disclosure.
  • the organic film layer After the organic film layer is introduced between the display module and the touch module, the clock signal lines around the area 02 of the gate drive circuit (GOA) will be short-circuited. Because the organic film layer is water-absorbent, in order to prevent external water vapor from intruding into the display product, as shown in Figure 1, the organic film layer will be dug in the packaging area to form a groove 04, and the encapsulant will be coated in the groove 04.
  • the X direction is parallel to one side edge of the display substrate
  • the Y direction is parallel to the other side edge of the display substrate
  • the Z direction is perpendicular to the display substrate
  • the X direction is perpendicular to the Y direction
  • the X direction is parallel to the display substrate.
  • the Z direction is perpendicular
  • the Y direction is perpendicular to the Z direction.
  • the clock signal line 07 on the periphery of the GOA area 02 is connected to the signal line 09 in the display area 01 through the line made of the second transparent conductive layer 05
  • Figure 3 is Figure 2 is a schematic cross-sectional view along the AA direction.
  • the second transparent conductive layer 05 is formed on the organic film layer 12 formed with the groove 04, and a photoresist is coated on the second transparent conductive layer 05, and the photoresist is exposed and developed to form a photoresist.
  • the pattern of the resist using the pattern of the photoresist as a mask to pattern the second transparent conductive layer 05 to form a trace, the trace is connected to the clock signal line 07 through the via hole 08, and connected to the signal trace 09 through the via hole 10 connect. Since the film thickness of the organic film layer 12 is relatively large and the groove 04 is relatively deep, the photoresist at the bottom of the groove 04 cannot be fully exposed, as shown in FIG. 2 , resulting in the second transparent conductive layer 11 remaining at the bottom of the groove 04. The remaining second transparent conductive layer 11 will short-circuit different signal lines together, resulting in an abnormal picture.
  • Embodiments of the present disclosure provide a display substrate, a manufacturing method thereof, and a display device, which can avoid abnormal images.
  • An embodiment of the present disclosure provides a display substrate, including a base substrate, the base substrate includes a display area and a peripheral area surrounding the display area, and the display substrate includes:
  • a first insulating layer located on a side of the first signal line away from the base substrate
  • the first signal line and the second signal line are connected by a connecting wire, and the connecting wire is located on a side of the first insulating layer away from the base substrate, and the first insulating layer is far away from the substrate.
  • a groove is formed on one side of the base substrate, the depth of the groove is greater than a preset threshold, and the orthographic projection of the connecting trace on the base substrate is the same as that of the groove on the substrate. orthographic overlay on the substrate;
  • connection routing includes:
  • a first connection line includes a first part and a second part, wherein the first part covers the bottom and side walls of the groove, and the second part covers the first insulating layer and is located outside the groove area.
  • the first signal line and the second signal line are connected through the first connection line, and the first connection line does not include a hollow area.
  • the first connection line it is possible to The photoresist is exposed to form the first connection line, so as to prevent the conductive film layer from remaining in the groove, and then prevent the residual conductive film layer from short-circuiting different signal lines together, avoiding abnormal pictures, and ensuring the quality of the display product yield.
  • the first insulating layer may be an organic film layer located between the display module and the touch module.
  • the thickness of the organic film layer is generally relatively large, such as Greater than 2.5um, the depth of the groove is relatively large, generally greater than 2um.
  • the first conductive layer is formed on the side of the first insulating layer away from the base substrate, and the pattern of photoresist is formed on the first conductive layer, in order to avoid the first conductive layer remaining at the bottom of the groove , the photoresist pattern used to form the first connection line on the first conductive layer is overexposed to ensure that the photoresist at the bottom of the groove can be completely exposed, and then the first conductive layer is etched to form the first connection line , can avoid the first conductive layer remaining at the bottom of the groove.
  • the display substrate further includes:
  • a second insulating layer located on a side of the first connection line away from the base substrate
  • connection routing also includes:
  • Two connection lines are used to connect the first connection line with the first signal line and the second signal line, and the orthographic projection of the second connection line on the base substrate is the same as that of the groove on the The orthographic projections on the base substrate do not overlap, and the depth of the via hole is smaller than the groove depth of the groove.
  • the first signal line, the second signal line and the first connection line are located in different film layers, and the first signal line, the second signal line and the first connection line are connected through the second connection line, wherein the first connection line
  • the second insulating layer can be an inorganic insulating layer, the thickness of the second insulating layer is relatively small, smaller than the thickness of the first insulating layer, and the depth of the via hole used to connect the first connecting line and the second connecting line is smaller than the depth of the groove, forming The second conductive layer of the second connection line is less likely to remain in the via hole.
  • the connecting wires can be made of transparent conductive materials, such as ITO, IZO and the like.
  • the first connection line and the second connection line can be arranged on the same layer and the same material as the original film layer of the display substrate.
  • the second connection line is the same as the pixel electrode of the display substrate.
  • the layer is the same material, so that the second connection line and the pixel electrode of the display substrate can be formed by one patterning process; the first connection line and the common electrode of the display substrate are the same layer and the same material, so that the first connection line can be formed by one patterning process
  • the connecting wire and the common electrode of the display substrate are the same layer and the same material, so that the first connection line can be formed by one patterning process
  • the first signal line and the second signal line may be any signal lines on the display substrate that need to be connected.
  • the first signal line may be a clock signal line of the gate drive unit;
  • the second signal line may be a signal line in a fan-shaped area.
  • the clock signal The line 07 is connected to the signal trace 09 through a connecting trace, and the connecting trace includes a first connecting wire 15 and a second connecting wire 17, wherein the first connecting wire 15 is connected to the second connecting wire 17 through the via hole 161 and the via hole 162.
  • the extension direction of the first connection line 15 may be parallel to the extension direction of the signal trace 09;
  • the second connection line 17 includes a seventh part 171 and an eighth part 172, and the seventh part 171 is connected to the first connection line 15 and the signal trace 09, the seventh part 171 is connected to the signal trace 09 through the via hole 163, and connected to the first connection line 15 through the via hole 161;
  • the eighth part 172 is connected to the first connection line 15 and the clock Signal line 07, the eighth part 172 is connected to the first connection line 15 through the via hole 162, and connected to the signal line 07 through the via hole 164;
  • the extension direction of the seventh part 171 is parallel to the signal line 09, and the first
  • the eighth part 172 is L-shaped, and the eighth part 172 includes a first subsection parallel to the clock signal line 07 and a second subsection parallel to the signal line 09; in some embodiments, the eighth part 172 It can be linear, and the extension direction is parallel to the clock signal line 07 .
  • the peripheral area of the display substrate is provided with a plurality of clock signal lines 07 arranged in parallel and spaced apart from each other.
  • the line widths of adjacent clock signal lines 07 may be the same or different from each other.
  • the distance between adjacent clock signal lines 07 Can be the same or different.
  • the vias can be oval vias, circular vias or rectangular vias, and the vias are oval vias, that is, the vias are parallel to the direction of the substrate.
  • the cross section (section on the XY plane) of the via is elliptical, and the via hole is circular.
  • the via hole means that the cross section of the via hole in the direction parallel to the substrate substrate (the cross section on the XY plane) is a rectangular via hole.
  • the via hole can be a rectangular via hole, and the side length of the rectangle can be 6-8um .
  • the cross-section of the groove 04 in the direction perpendicular to the substrate can be an inverted trapezoid
  • the length of the upper side of the inverted trapezoid can be 63um
  • the length of the lower side can be 60um.
  • the groove depth may be 2.5um.
  • the first transparent conductive layer of the display substrate can be used to form the first connection line 15
  • the first connection line 15 covers the sidewall and the bottom of the groove and exceeds the range of the groove.
  • the first connection line 15 includes a first portion 151 and a second portion 152, and the first orthographic projection of the first portion 151 on the base substrate is located in the groove.
  • a second orthographic projection of the second portion 152 on the base substrate is outside the orthographic projection of the recess on the base substrate, the first The area ratio of the first orthographic projection to the second orthographic projection may be 6:1-1:1.
  • a second insulating layer 13 is formed on the side of the first connection line 15 away from the base substrate, the second insulating layer 13 may be a passivation layer, and the thickness may be less than 1um; on the side of the second insulating layer 13 away from the base substrate A second connection line 17 is formed, and the second connection line 17 can be made by using the second transparent conductive layer of the display substrate.
  • the second connection line 17 formed by the second transparent conductive layer includes a slit-shaped hollow area 18 , and the extension direction of the hollow area 18 is parallel to the extension direction of the second connection line 17 .
  • the second transparent conductive layer is directly used to form the second connection line 17 to connect the clock signal line 07 and the signal line 09, in order to avoid the second transparent conductive layer remaining in the groove, when forming the second connection line, it is necessary to The photoresist used to form the second connection line on the second transparent conductive layer is exposed to form the second connection line, but as shown in Figure 4, the second connection line 17 formed by the second transparent conductive layer 05 includes a slit-shaped If the hollow area 18 is overexposed, the second connection line 17 will be too thin, resulting in poor disconnection.
  • the first connection line 15 is a complete conductive pattern, which does not include a hollow area, so that when the first connection line is formed, the photoresist used to form the first connection line on the first transparent conductive layer can be overexposed and formed. the first connecting wire without breaking the first connecting wire.
  • the distance between adjacent first connecting lines is 10-15um.
  • the line width of the first connecting line 15 can be equal to the line width of the second connecting line 17, or slightly larger than the line width of the second connecting line 17, or slightly smaller than the line width of the second connecting line 17. Width of connection line 17.
  • the line width of the second connection line 17 may be equal to the line width of the clock signal line 07 , or slightly larger than the line width of the clock signal line 07 , or slightly smaller than the line width of the clock signal line 07 .
  • the line width of the second connection line 17 can be equal to the line width of the signal line 09, or slightly larger than the line width of the signal line 09, or slightly smaller than the line width of the signal line 09.
  • the second connection line 17 includes a third portion 173 and a fourth portion 174
  • the third orthographic projection of the third portion 173 on the base substrate is located at the In the orthographic projection of the first connection line 15 on the base substrate
  • the fourth orthographic projection of the fourth portion 174 on the base substrate is located on the base substrate of the first connection line 15
  • the area ratio between the third orthographic projection and the fourth orthographic projection is 1:20-1:25.
  • the second connection line 17 includes a fifth portion 175 and a sixth portion 176
  • the fifth orthographic projection of the fifth portion 175 on the base substrate is located at the via hole 161 and 162 are within the orthographic projections on the base substrate
  • the sixth orthographic projection of the sixth portion 176 on the base substrate is outside the orthographic projections of the via holes 161 and 162 on the base substrate.
  • the area ratio of the fifth orthographic projection to the sixth orthographic projection is 1:20-1:25.
  • An embodiment of the present disclosure also provides a display device, including the above-mentioned display substrate.
  • the display device includes but not limited to: a radio frequency unit, a network module, an audio output unit, an input unit, a sensor, a display unit, a user input unit, an interface unit, a memory, a processor, and a power supply.
  • a radio frequency unit a network module
  • an audio output unit an input unit
  • a sensor a sensor
  • a display unit a user input unit
  • an interface unit a memory
  • a processor and a power supply.
  • the display device includes but is not limited to a monitor, a mobile phone, a tablet computer, a television, a wearable electronic device, a navigation display device, and the like.
  • the display device can be any product or component with a display function such as a TV, a monitor, a digital photo frame, a mobile phone, and a tablet computer, wherein the display device also includes a flexible circuit board, a printed circuit board, and a backplane.
  • Embodiments of the present disclosure also provide a method for manufacturing a display substrate, including:
  • the display substrate includes a base substrate, the base substrate includes a display area and a peripheral area surrounding the display area, and the method includes:
  • connection trace connecting the first signal line and the second signal line
  • the connection trace is located on a side of the first insulating layer away from the base substrate, and the first insulating layer is far away from the
  • a groove is formed on one side of the base substrate, the groove depth of the groove is greater than a preset threshold, and the orthographic projection of the connecting trace on the base substrate is the same as that of the groove on the base substrate. Orthographic overlap on ;
  • Forming the connection routing includes:
  • a first conductive layer is formed on the side of the first insulating layer away from the base substrate, a photoresist pattern is formed on the first conductive layer, and the photoresist pattern is overexposed, so as to The pattern of the photoresist is a mask, and the first conductive layer is etched to form a first connection line, the first connection line includes a first part and a second part, wherein the first part covers the groove The bottom and the sidewall, the second part covers the area of the first insulating layer outside the groove.
  • the first signal line and the second signal line are connected through the first connection line, and the first connection line does not include a hollow area.
  • the first connection line it is possible to The photoresist is exposed to form the first connection line, so as to prevent the conductive film layer from remaining in the groove, and then prevent the residual conductive film layer from short-circuiting different signal lines together, avoiding abnormal pictures, and ensuring the display of products. yield.
  • the first insulating layer may be an organic film layer located between the display module and the touch module.
  • the thickness of the organic film layer is generally relatively large, such as Greater than 2.5um, the depth of the groove is relatively large, generally greater than 2um.
  • the first conductive layer is formed on the side of the first insulating layer away from the base substrate, and the pattern of photoresist is formed on the first conductive layer, in order to avoid the first conductive layer remaining at the bottom of the groove , the photoresist pattern used to form the first connection line on the first conductive layer is overexposed to ensure that the photoresist at the bottom of the groove can be completely exposed, and then the first conductive layer is etched to form the first connection line , can avoid the first conductive layer remaining at the bottom of the groove.
  • the method also includes:
  • a second insulating layer is formed on the side of the first connecting line away from the base substrate, and the second insulating layer is patterned to form a via hole exposing the first connecting line, and the via hole is having a depth less than the groove depth of the groove;
  • Forming the connection routing also includes:
  • a second connection line is formed on a side of the second insulating layer away from the base substrate, and the second connection line is connected to the first connection line through a via hole penetrating through the second insulating layer.
  • the second connection line is used to connect the first connection line with the first signal line and the second signal line, and the orthographic projection of the second connection line on the base substrate is the same as that of the groove.
  • the orthographic projections on the base substrate do not overlap, and the depth of the via hole is smaller than the groove depth of the groove.
  • the first signal line, the second signal line and the first connection line are located in different film layers, and the first signal line, the second signal line and the first connection line are connected through the second connection line, wherein the first connection line
  • the second insulating layer can be an inorganic insulating layer, the thickness of the second insulating layer is relatively small, smaller than the thickness of the first insulating layer, and the depth of the via hole used to connect the first connecting line and the second connecting line is smaller than the depth of the groove, forming The second conductive layer of the second connection line is less likely to remain in the via hole.
  • the connecting wires can be made of transparent conductive materials, such as ITO, IZO and the like.
  • the first connection line and the second connection line can be arranged on the same layer and the same material as the original film layer of the display substrate.
  • the second connection line is the same as the pixel electrode of the display substrate.
  • the layer is the same material, so that the second connection line and the pixel electrode of the display substrate can be formed by one patterning process; the first connection line and the common electrode of the display substrate are the same layer and the same material, so that the first connection line can be formed by one patterning process
  • the connecting wire and the common electrode of the display substrate are the same layer and the same material, so that the first connection line can be formed by one patterning process
  • the first signal line and the second signal line may be any signal lines on the display substrate that need to be connected.
  • the first signal line may be a clock signal line of the gate drive unit;
  • the second signal line may be a signal line in a fan-shaped area.
  • the manufacturing method of this embodiment includes the following steps:
  • Step 1 As shown in FIG. 5, an organic film layer 12 is formed on the display substrate on which the clock signal line 07 and the signal line 09 are formed, and the organic film layer 12 is dug to form a groove 04.
  • FIG. A schematic cross-sectional view in the BB direction, wherein the organic film layer 12 is located on the gate insulating layer 14;
  • Step 2 as shown in Figure 7 and Figure 8, forming the first connection line 15;
  • the first transparent conductive layer can be formed on the display substrate after step 1.
  • the first transparent conductive layer can be ITO, IZO or other transparent metal oxides, and a layer of photolithography is coated on the first transparent conductive layer.
  • the unreserved area of glue corresponds to the area outside the above-mentioned pattern; carry out developing treatment, the photoresist in the unreserved area of photoresist is completely removed, and the thickness of the photoresist in the photoresist reserved area remains unchanged; use the photoresist as a mask
  • the film etches the first transparent conductive layer to form the first connection line 15 .
  • the exposure amount is increased to prevent the first transparent conductive layer from remaining at the bottom of the groove through over
  • FIG. 8 is a schematic cross-sectional view of FIG. 7 along the BB direction, wherein, as shown in FIG. 13 , the part where the first connection line 15 overlaps the sidewall of the groove may be smooth.
  • Step 3 as shown in FIG. 9 and FIG. 10 , forming a second insulating layer 13;
  • the passivation layer is used as the second insulating layer 13, and the passivation layer can be selected from oxide, nitride or oxynitride compound.
  • the material of the passivation layer can be SiNx, SiOx or Si(ON)x, and the passivation layer can also be Al 2 O 3 is used.
  • the passivation layer can be a single-layer structure, or a two-layer structure composed of silicon nitride and silicon oxide.
  • the reaction gas corresponding to silicon oxide can be SiH 4 , N 2 O; the corresponding gas of nitride or oxynitride compound can be SiH 4 , NH 3 , N 2 or SiH 2 Cl 2 , NH 3 , N 2 .
  • a pattern of the passivation layer including via holes is formed through one patterning process, and the first connection lines 15 are exposed through the via holes.
  • FIG. 10 is a schematic cross-sectional view along the BB direction of FIG. 9 .
  • Step 4 as shown in FIG. 11 and FIG. 12 , forming a second connection line 17 .
  • the thickness deposited on the display substrate after step 3 by sputtering or thermal evaporation is about
  • the second transparent conductive layer, the second transparent conductive layer can be ITO, IZO or other transparent metal oxides, coat a layer of photoresist on the second transparent conductive layer, and use a mask to expose the photoresist , making the photoresist form a photoresist unreserved area and a photoresist reserved area, wherein the photoresist reserved area corresponds to the area where the pattern of the second connection line 17 is located, and the photoresist unreserved area corresponds to the area other than the above-mentioned pattern area; carry out developing treatment, the photoresist in the photoresist unreserved area is completely removed, and the photoresist thickness in the photoresist reserved area remains unchanged; the transparent area of the photoresist unreserved area is completely etched away by an etching process The conductive layer film is stripped off the remaining photoresist
  • the first connection line 15 and the second connection line 17 are used to form a connection line to connect the signal line 09 and the clock signal line 07. Since the first connection line 15 is a complete conductive pattern, it does not include a hollow area. , when forming the first connection line, the photoresist used to form the first connection line on the first transparent conductive layer can be overexposed to form the first connection line, so as to avoid the first transparent conductive layer remaining in the groove, Causes a short circuit in the signal line.
  • the peripheral area of the display substrate is provided with a plurality of clock signal lines 07 arranged in parallel and spaced apart from each other.
  • the line widths of adjacent clock signal lines 07 may be the same or different from each other.
  • the distance between adjacent clock signal lines 07 Can be the same or different.
  • the vias can be oval vias, circular vias or rectangular vias, and the vias are oval vias, that is, the vias are parallel to the direction of the substrate.
  • the cross section (section on the XY plane) of the via is elliptical, and the via hole is circular.
  • the via hole means that the cross section of the via hole in the direction parallel to the substrate substrate (the cross section on the XY plane) is a rectangular via hole.
  • the via hole can be a rectangular via hole, and the side length of the rectangle can be 6-8um .
  • each embodiment in this specification is described in a progressive manner, the same and similar parts of each embodiment can be referred to each other, and each embodiment focuses on the differences from other embodiments.
  • the description is relatively simple, and for related parts, please refer to the description of the product embodiment.

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Abstract

一种显示基板及其制作方法、显示装置，能够避免出现画面异常，属于显示技术领域。其中，显示基板包括：位于衬底基板的周边区域的第一信号线（07）和第二信号线（09）；第一绝缘层，位于第一信号线（07）远离衬底基板一侧；第一信号线（07）和第二信号线（09）之间通过连接走线连接，连接走线位于第一绝缘层远离衬底基板的一侧，第一绝缘层远离衬底基板的一侧形成有凹槽（04），凹槽（04）的槽深大于预设阈值，连接走线在衬底基板上的正投影与凹槽（04）在衬底基板上的正投影交叠；连接走线包括：第一连接线（15），第一连接线（15）包括第一部分（151）和第二部分（152），其中第一部分（151）覆盖凹槽（04）的底部和侧壁，第二部分（152）覆盖第一绝缘层位于凹槽（04）之外区域。

Description

显示基板及其制作方法、显示装置 技术领域
本公开涉及显示技术领域，特别是指一种显示基板及其制作方法、显示装置。
背景技术
在触控桌面显示产品中，由于在显示模组上增加了触控模组，导致触控走线与显示模组的信号线之间产生寄生电容，会导致污渍类不良现象加重，因此需要在显示模组与触控模组之间引入有机膜层来减少触控走线与信号线之间的寄生电容。
发明内容
本公开要解决的技术问题是提供一种显示基板及其制作方法、显示装置，能够避免出现画面异常。
为解决上述技术问题，本公开的实施例提供技术方案如下：
一方面，提供一种显示基板，包括衬底基板，所述衬底基板包括显示区域和环绕所述显示区域的周边区域，其特征在于，所述显示基板包括：
位于所述衬底基板的所述周边区域的第一信号线和第二信号线；
第一绝缘层，位于所述第一信号线远离所述衬底基板一侧；
所述第一信号线和所述第二信号线之间通过连接走线连接，所述连接走线位于所述第一绝缘层远离所述衬底基板的一侧，所述第一绝缘层远离所述衬底基板的一侧形成有凹槽，所述凹槽的槽深大于预设阈值，所述连接走线在所述衬底基板上的正投影与所述凹槽在所述衬底基板上的正投影交叠；
所述连接走线包括：
第一连接线，所述第一连接线包括第一部分和第二部分，其中第一部分覆盖所述凹槽的底部和侧壁，第二部分覆盖所述第一绝缘层位于所述凹槽之外区域。
一些实施例中，所述显示基板还包括：
位于所述第一连接线远离所述衬底基板一侧的第二绝缘层；
所述连接走线还包括：
位于所述第二绝缘层远离所述衬底基板一侧的第二连接线，所述第二连接线通过贯穿所述第二绝缘层的过孔与所述第一连接线连接，所述第二连接线用以连接所述第一连接线与所述第一信号线和所述第二信号线，所述第二连接线在所述衬底基板上的正投影与所述凹槽在所述衬底基板上的正投影不交叠，所述过孔的深度小于所述凹槽的槽深。
一些实施例中，所述第一部分在所述衬底基板上的第一正投影位于所述凹槽在所述衬底基板上的正投影内，所述第二部分在所述衬底基板上的第二正投影位于所述凹槽在所述衬底基板上的正投影外，所述第一正投影与所述第二正投影的面积比为6：1～1：1。
一些实施例中，所述第一连接线的延伸方向与所述第一信号线的延伸方向平行。
一些实施例中，相邻所述第一连接线之间的距离为10-15um。
一些实施例中，所述第二连接线包括有镂空区域，所述镂空区域的延伸方向与所述第二连接线的延伸方向平行。
一些实施例中，所述第二连接线包括第三部分和第四部分，所述第三部分在所述衬底基板上的第三正投影位于所述第一连接线在所述衬底基板上的正投影内，所述第四部分在所述衬底基板上的第四正投影位于所述第一连接线在所述衬底基板上的正投影外，所述第三正投影与所述第四正投影的面积比为1:20-1:25。
一些实施例中，所述第二连接线包括第五部分和第六部分，所述第五部分在所述衬底基板上的第五正投影位于所述过孔在所述衬底基板上的正投影内，所述第六部分在所述衬底基板上的第六正投影位于所述过孔在所述衬底基板上的正投影外，所述第五正投影与所述第六正投影的面积比为1:20-1:25。
一些实施例中，所述第二连接线包括第七部分和第八部分，所述第七部分连接所述第一连接线和所述第一信号线，所述第八部分连接所述第一连接 线和所述第二信号线，所述第七部分的延伸方向与所述第一信号线平行，所述第八部分为L型，所述第八部分包括与所述第一信号线平行的第一子部分和与所述第二信号线平行的第二子部分。
一些实施例中，所述过孔为矩形过孔，边长为6-8um。
一些实施例中，所述预设阈值为2um。
一些实施例中，所述连接走线采用透明导电材料。
一些实施例中，所述第二连接线与所述显示基板的像素电极同层同材料；和/或，
所述第一连接线与所述显示基板的公共电极同层同材料。
一些实施例中，
所述第一信号线为栅极驱动单元的时钟信号线；
所述第二信号线为扇形区域的信号走线。
本公开的实施例还提供了一种显示装置，包括如上所述的显示基板。
本公开的实施例还提供了一种显示基板的制作方法，所述显示基板包括衬底基板，所述衬底基板包括显示区域和环绕所述显示区域的周边区域，所述方法包括：
在所述衬底基板的所述周边区域形成第一信号线和第二信号线；
在所述第一信号线远离所述衬底基板的一侧形成第一绝缘层；
形成连接所述第一信号线和所述第二信号线的连接走线，所述连接走线位于所述第一绝缘层远离所述衬底基板的一侧，所述第一绝缘层远离所述衬底基板的一侧形成有凹槽，所述凹槽的槽深大于预设阈值，所述连接走线在所述衬底基板上的正投影与所述凹槽在所述衬底基板上的正投影交叠；
形成所述连接走线包括：
在所述第一绝缘层远离所述衬底基板的一侧形成第一导电层，在所述第一导电层上形成光刻胶的图形，对所述光刻胶的图形进行过曝光，以所述光刻胶的图形为掩膜，对所述第一导电层进行刻蚀，形成第一连接线，所述第一连接线包括第一部分和第二部分，其中第一部分覆盖所述凹槽的底部和侧壁，第二部分覆盖所述第一绝缘层位于所述凹槽之外区域。
一些实施例中，所述方法还包括：
在所述第一连接线远离所述衬底基板的一侧形成第二绝缘层，对所述第二绝缘层进行构图，形成暴露出所述第一连接线的过孔，所述过孔的深度小于所述凹槽的槽深；
形成所述连接走线还包括：
在所述第二绝缘层远离所述衬底基板的一侧形成第二连接线，所述第二连接线通过贯穿所述第二绝缘层的过孔与所述第一连接线连接，所述第二连接线用以连接所述第一连接线与所述第一信号线和所述第二信号线，所述第二连接线在所述衬底基板上的正投影与所述凹槽在所述衬底基板上的正投影不交叠，所述过孔的深度小于所述凹槽的槽深。
本公开的实施例具有以下有益效果：
上述方案中，第一信号线和第二信号线通过第一连接线连接，第一连接线未包括镂空区域，在形成第一连接线时，可以对形成第一连接线的导电膜层上的光刻胶进行过曝光来形成第一连接线，避免导电膜层在凹槽内残留，进而避免残留的导电膜层将不同的信号线短接在一起，避免出现画面异常，保证显示产品的良率。
附图说明
图1为显示基板的平面示意图；
图2和图3为相关技术显示基板的示意图；
图4为第二透明导电层的平面示意图；
图5-图13为本公开实施例制作显示基板的示意图。
附图标记
01 显示区域
02 GOA区域
03 电源电压线
04 凹槽
05 第二透明导电层
07 时钟信号线
08、10 过孔
09 信号走线
11 残留的第二透明导电层
12 有机膜层
13 第二绝缘层
14 栅绝缘层
15 第一连接线
151 第一部分
152 第二部分
161-164 过孔
17 第二连接线
171 第七部分
172 第八部分
173 第三部分
174 第四部分
175 第五部分
176 第六部分
18 镂空区域
具体实施方式
为使本公开的实施例要解决的技术问题、技术方案和优点更加清楚，下面将结合附图及具体实施例进行详细描述。
在显示模组与触控模组之间引入有机膜层后，栅极驱动电路(GOA)区域02外围的时钟信号线会发生短路不良。因为有机膜层具有吸水性，为了防止外部水汽侵入显示产品内部，如图1所示，会在封装区域将有机膜层进行挖槽形成凹槽04，在凹槽04内涂覆封装胶后即可起到隔绝水汽的作用，其中，X方向与显示基板的一侧边缘平行，Y方向与显示基板的另一侧边缘平行，Z方向垂直于显示基板，X方向与Y方向垂直，X方向与Z方向垂直， Y方向与Z方向垂直。相关技术中，如图2和图3所示，GOA区域02外围的时钟信号线07与显示区域01的信号走线09通过第二透明导电层05制作的走线进行连接，其中，图3为图2在AA方向上的截面示意图。在制作走线时，在形成有凹槽04的有机膜层12上形成第二透明导电层05，在第二透明导电层05上涂覆光刻胶，对光刻胶进行曝光显影后形成光刻胶的图形，以光刻胶的图形为掩膜对第二透明导电层05进行构图后形成走线，走线通过过孔08与时钟信号线07连接，通过过孔10与信号走线09连接。由于有机膜层12的膜厚比较大，凹槽04比较深，凹槽04底部的光刻胶不能被完全曝光，如图2所示，导致凹槽04底部有第二透明导电层11残留，残留的第二透明导电层11会将不同的信号线短接在一起，导致画面异常。
本公开的实施例提供一种显示基板及其制作方法、显示装置，能够避免出现画面异常。
本公开的实施例提供一种显示基板，包括衬底基板，所述衬底基板包括显示区域和环绕所述显示区域的周边区域，所述显示基板包括：
位于所述衬底基板的所述周边区域的第一信号线和第二信号线；
第一绝缘层，位于所述第一信号线远离所述衬底基板一侧；
所述第一信号线和所述第二信号线之间通过连接走线连接，所述连接走线位于所述第一绝缘层远离所述衬底基板的一侧，所述第一绝缘层远离所述衬底基板的一侧形成有凹槽，所述凹槽的槽深大于预设阈值，所述连接走线在所述衬底基板上的正投影与所述凹槽在所述衬底基板上的正投影交叠；
所述连接走线包括：
第一连接线，所述第一连接线包括第一部分和第二部分，其中第一部分覆盖所述凹槽的底部和侧壁，第二部分覆盖所述第一绝缘层位于所述凹槽之外区域。
本实施例中，第一信号线和第二信号线通过第一连接线连接，第一连接线未包括镂空区域，在形成第一连接线时，可以对形成第一连接线的导电膜层上的光刻胶进行过曝光来形成第一连接线，避免导电膜层在凹槽内残留，进而避免残留的导电膜层将不同的信号线短接在一起，避免出现画面异常， 保证显示产品的良率。
其中，第一绝缘层可以为位于显示模组和触控模组之间的有机膜层，为了减少触控走线与信号线之间的寄生电容，有机膜层的厚度一般都比较大，比如大于2.5um，凹槽的深度比较大，一般大于2um。在制作第一连接线时，在第一绝缘层远离衬底基板的一侧形成第一导电层，在第一导电层上形成光刻胶的图形，为了避免第一导电层在凹槽底部残留，对第一导电层上用以形成第一连接线的光刻胶图形进行过曝光，保证凹槽底部的光刻胶能够被完全曝光，进而对第一导电层进行刻蚀形成第一连接线，可以避免第一导电层在凹槽底部残留。
一些实施例中，所述显示基板还包括：
位于所述第一连接线远离所述衬底基板一侧的第二绝缘层；
所述连接走线还包括：
位于所述第二绝缘层远离所述衬底基板一侧的第二连接线，所述第二连接线通过贯穿所述第二绝缘层的过孔与所述第一连接线连接，所述第二连接线用以连接所述第一连接线与所述第一信号线和所述第二信号线，所述第二连接线在所述衬底基板上的正投影与所述凹槽在所述衬底基板上的正投影不交叠，所述过孔的深度小于所述凹槽的槽深。
本实施例中，第一信号线、第二信号线与第一连接线位于不同的膜层，通过第二连接线将第一信号线、第二信号线与第一连接线连接，其中，第二绝缘层可以为无机绝缘层，第二绝缘层的厚度比较小，小于第一绝缘层的厚度，用以连接第一连接线和第二连接线的过孔的深度小于凹槽的深度，形成第二连接线的第二导电层不易残留在过孔中。
为了避免对显示基板的透过率造成影响，连接走线可以采用透明导电材料，比如ITO、IZO等。为了避免增加显示基板的构图工艺的次数，第一连接线和第二连接线可以与显示基板的原有膜层同层同材料设置，比如，第二连接线与所述显示基板的像素电极同层同材料，这样，可以通过一次构图工艺形成第二连接线和显示基板的像素电极；第一连接线与所述显示基板的公共电极同层同材料，这样，可以通过一次构图工艺形成第一连接线和显示基 板的公共电极。
本实施例中，第一信号线和第二信号线可以为显示基板上任意的需要连接的信号线，一些实施例中，所述第一信号线可以为栅极驱动单元的时钟信号线；所述第二信号线可以为扇形区域的信号走线。
一具体示例中，在图1的虚线框所示位置，如图11和图12(图12为图11在BB方向上的Z方向截面示意图，即在YZ平面上的截面)所示，时钟信号线07与信号走线09通过连接走线连接，连接走线包括第一连接线15和第二连接线17，其中，第一连接线15通过过孔161和过孔162与第二连接线17连接，第一连接线15的延伸方向可以与信号走线09的延伸方向平行；第二连接线17包括第七部分171和第八部分172，所述第七部分171连接所述第一连接线15和信号走线09，第七部分171通过过孔163与信号走线09连接，通过过孔161与第一连接线15连接；所述第八部分172连接所述第一连接线15和时钟信号线07，第八部分172通过过孔162与第一连接线15连接，通过过孔164与信号走线07连接；所述第七部分171的延伸方向与信号走线09平行，所述第八部分172为L型，所述第八部分172包括与时钟信号线07平行的第一子部分和与信号走线09平行的第二子部分；在一些实施例中，所述第八部分172可以为直线型，且延伸方向与时钟信号线07平行。
本实施例中，显示基板的周边区域设置有多条平行设置且彼此间隔的时钟信号线07，相邻时钟信号线07的线宽可相同或彼此不同，相邻时钟信号线07之间的间距可以相同也可以不同。
其中，过孔(包括过孔161、162、163和164)可以为椭圆形过孔、圆形过孔或矩形过孔，过孔为椭圆形过孔即过孔在平行于衬底基板方向上的截面(在XY平面上的截面)为椭圆形，过孔为圆形过孔即过孔在平行于衬底基板方向上的截面(在XY平面上的截面)为圆形，过孔为矩形过孔即过孔在平行于衬底基板方向上的截面(在XY平面上的截面)为矩形过孔，一些实施例中，过孔可以为矩形过孔，矩形的边长可以为6-8um。
如图12所示，凹槽04在垂直于衬底基板方向上的截面(在YZ平面上的截面)可以为倒梯形，倒梯形的上边长可以为63um，下边长可以为60um， 凹槽的槽深可以为2.5um。本实施例中，可以利用显示基板的第一透明导电层形成第一连接线15，第一连接线15覆盖凹槽的侧壁和底部，且超出凹槽的范围。
一些实施例中，如图12所示，所述第一连接线15包括第一部分151和第二部分152，所述第一部分151在所述衬底基板上的第一正投影位于所述凹槽在所述衬底基板上的正投影内，所述第二部分152在所述衬底基板上的第二正投影位于所述凹槽在所述衬底基板上的正投影外，所述第一正投影与所述第二正投影的面积比可以为6：1-1：1。
在第一连接线15远离衬底基板的一侧形成有第二绝缘层13，第二绝缘层13可以为钝化层，厚度可以小于1um；在第二绝缘层13远离衬底基板的一侧形成有第二连接线17，第二连接线17可以采用显示基板的第二透明导电层制作。如图4所示，第二透明导电层形成第二连接线17包括狭缝状的镂空区域18，所述镂空区域18的延伸方向与所述第二连接线17的延伸方向平行。
如果直接采用第二透明导电层形成第二连接线17来连接时钟信号线07和信号走线09，为了避免第二透明导电层在凹槽内残留，在形成第二连接线时，需要对第二透明导电层上用以形成第二连接线的光刻胶进行过曝光来形成第二连接线，但如图4所示，第二透明导电层05形成的第二连接线17包括狭缝状的镂空区域18，过曝光会造成第二连接线17过细而造成断路不良。而第一连接线15为完整的导电图案，其中不包括镂空区域，这样在形成第一连接线时，可以对第一透明导电层上用以形成第一连接线的光刻胶进行过曝光形成第一连接线，而不会使得第一连接线断裂。
为了避免相邻的第一连接线之间产生串扰，相邻所述第一连接线之间的距离为10-15um。
本实施例中，如图11所示，第一连接线15的线宽可以与第二连接线17的线宽相等，或者，略大于第二连接线17的线宽，或者，略小于第二连接线17的线宽。第二连接线17的线宽可以与时钟信号线07的线宽相等，或者，略大于时钟信号线07的线宽，或者，略小于时钟信号线07的线宽。第二连 接线17的线宽可以与信号走线09的线宽相等，或者，略大于信号走线09的线宽，或者，略小于信号走线09的线宽。
一些实施例中，如图12所示，所述第二连接线17包括第三部分173和第四部分174，所述第三部分173在所述衬底基板上的第三正投影位于所述第一连接线15在所述衬底基板上的正投影内，所述第四部分174在所述衬底基板上的第四正投影位于所述第一连接线15在所述衬底基板上的正投影外，所述第三正投影与所述第四正投影的面积比为1:20-1:25。
一些实施例中，如图12所示，所述第二连接线17包括第五部分175和第六部分176，所述第五部分175在所述衬底基板上的第五正投影位于过孔161和162在所述衬底基板上的正投影内，所述第六部分176在所述衬底基板上的第六正投影位于过孔161和162在所述衬底基板上的正投影外，所述第五正投影与所述第六正投影的面积比为1:20-1:25。
本公开的实施例还提供了一种显示装置，包括如上所述的显示基板。
该显示装置包括但不限于：射频单元、网络模块、音频输出单元、输入单元、传感器、显示单元、用户输入单元、接口单元、存储器、处理器、以及电源等部件。本领域技术人员可以理解，上述显示装置的结构并不构成对显示装置的限定，显示装置可以包括上述更多或更少的部件，或者组合某些部件，或者不同的部件布置。在本公开实施例中，显示装置包括但不限于显示器、手机、平板电脑、电视机、可穿戴电子设备、导航显示设备等。
所述显示装置可以为：电视、显示器、数码相框、手机、平板电脑等任何具有显示功能的产品或部件，其中，所述显示装置还包括柔性电路板、印刷电路板和背板。
本公开的实施例还提供了一种显示基板的制作方法，包括：
所述显示基板包括衬底基板，所述衬底基板包括显示区域和环绕所述显示区域的周边区域，所述方法包括：
在所述衬底基板的所述周边区域形成第一信号线和第二信号线；
在所述第一信号线远离所述衬底基板的一侧形成第一绝缘层；
形成连接所述第一信号线和所述第二信号线的连接走线，所述连接走线 位于所述第一绝缘层远离所述衬底基板的一侧，所述第一绝缘层远离所述衬底基板的一侧形成有凹槽，所述凹槽的槽深大于预设阈值，所述连接走线在所述衬底基板上的正投影与所述凹槽在所述衬底基板上的正投影交叠；
形成所述连接走线包括：
在所述第一绝缘层远离所述衬底基板的一侧形成第一导电层，在所述第一导电层上形成光刻胶的图形，对所述光刻胶的图形进行过曝光，以所述光刻胶的图形为掩膜，对所述第一导电层进行刻蚀，形成第一连接线，所述第一连接线包括第一部分和第二部分，其中第一部分覆盖所述凹槽的底部和侧壁，第二部分覆盖所述第一绝缘层位于所述凹槽之外区域。
本实施例中，第一信号线和第二信号线通过第一连接线连接，第一连接线未包括镂空区域，在形成第一连接线时，可以对形成第一连接线的导电膜层上的光刻胶进行过曝光来形成第一连接线，避免导电膜层在凹槽内残留，进而避免残留的导电膜层将不同的信号线短接在一起，避免出现画面异常，保证显示产品的良率。
其中，第一绝缘层可以为位于显示模组和触控模组之间的有机膜层，为了减少触控走线与信号线之间的寄生电容，有机膜层的厚度一般都比较大，比如大于2.5um，凹槽的深度比较大，一般大于2um。在制作第一连接线时，在第一绝缘层远离衬底基板的一侧形成第一导电层，在第一导电层上形成光刻胶的图形，为了避免第一导电层在凹槽底部残留，对第一导电层上用以形成第一连接线的光刻胶图形进行过曝光，保证凹槽底部的光刻胶能够被完全曝光，进而对第一导电层进行刻蚀形成第一连接线，可以避免第一导电层在凹槽底部残留。
一些实施例中，所述方法还包括：
在所述第一连接线远离所述衬底基板的一侧形成第二绝缘层，对所述第二绝缘层进行构图，形成暴露出所述第一连接线的过孔，所述过孔的深度小于所述凹槽的槽深；
形成所述连接走线还包括：
在所述第二绝缘层远离所述衬底基板的一侧形成第二连接线，所述第二 连接线通过贯穿所述第二绝缘层的过孔与所述第一连接线连接，所述第二连接线用以连接所述第一连接线与所述第一信号线和所述第二信号线，所述第二连接线在所述衬底基板上的正投影与所述凹槽在所述衬底基板上的正投影不交叠，所述过孔的深度小于所述凹槽的槽深。
本实施例中，第一信号线、第二信号线与第一连接线位于不同的膜层，通过第二连接线将第一信号线、第二信号线与第一连接线连接，其中，第二绝缘层可以为无机绝缘层，第二绝缘层的厚度比较小，小于第一绝缘层的厚度，用以连接第一连接线和第二连接线的过孔的深度小于凹槽的深度，形成第二连接线的第二导电层不易残留在过孔中。
为了避免对显示基板的透过率造成影响，连接走线可以采用透明导电材料，比如ITO、IZO等。为了避免增加显示基板的构图工艺的次数，第一连接线和第二连接线可以与显示基板的原有膜层同层同材料设置，比如，第二连接线与所述显示基板的像素电极同层同材料，这样，可以通过一次构图工艺形成第二连接线和显示基板的像素电极；第一连接线与所述显示基板的公共电极同层同材料，这样，可以通过一次构图工艺形成第一连接线和显示基板的公共电极。
本实施例中，第一信号线和第二信号线可以为显示基板上任意的需要连接的信号线，一些实施例中，所述第一信号线可以为栅极驱动单元的时钟信号线；所述第二信号线可以为扇形区域的信号走线。
一具体示例中，如图5-图12所示，本实施例的制作方法包括以下步骤：
步骤1、如图5所示，在形成时钟信号线07和信号走线09的显示基板上形成有机膜层12，对有机膜层12进行挖槽，形成凹槽04，图6为图5在BB方向上的截面示意图，其中，有机膜层12位于栅绝缘层14上；
步骤2、如图7和图8所示，形成第一连接线15；
具体地，可以在完成步骤1的显示基板上形成第一透明导电层，第一透明导电层可以是ITO、IZO或者其他的透明金属氧化物，在第一透明导电层上涂覆一层光刻胶，采用掩膜板对光刻胶进行曝光，使光刻胶形成光刻胶未保留区域和光刻胶保留区域，其中，光刻胶保留区域对应于第一连接线15所 在区域，光刻胶未保留区域对应于上述图形以外的区域；进行显影处理，光刻胶未保留区域的光刻胶被完全去除，光刻胶保留区域的光刻胶厚度保持不变；以光刻胶为掩膜对第一透明导电层进行刻蚀，形成第一连接线15。在对光刻胶进行曝光时，增大曝光量，通过过曝光避免有第一透明导电层残留在凹槽底部。
图8为图7在BB方向上的截面示意图，其中，如图13所示，第一连接线15搭接在凹槽侧壁上的部分可以为平滑的。
步骤3、如图9和图10所示，形成第二绝缘层13；
具体地，可以在完成步骤2的显示基板上采用磁控溅射、热蒸发、PECVD或其它成膜方法沉积厚度为
Figure PCTCN2022073778-appb-000001
的钝化层作为第二绝缘层13，钝化层可以选用氧化物、氮化物或者氧氮化合物，具体地，钝化层材料可以是SiNx，SiOx或Si(ON)x，钝化层还可以使用Al 2O 3。钝化层可以是单层结构，也可以是采用氮化硅和氧化硅构成的两层结构。其中，硅的氧化物对应的反应气体可以为SiH 4，N 2O；氮化物或者氧氮化合物对应气体可以是SiH 4，NH 3，N 2或SiH 2Cl 2，NH 3，N 2。通过一次构图工艺形成包括有过孔的钝化层的图形，过孔暴露出第一连接线15。
其中，图10为图9在BB方向上的截面示意图。
步骤4、如图11和图12所示，形成第二连接线17。
具体地，在完成步骤3的显示基板上通过溅射或热蒸发的方法沉积厚度约为
Figure PCTCN2022073778-appb-000002
的第二透明导电层，第二透明导电层可以是ITO、IZO或者其他的透明金属氧化物，在第二透明导电层上涂覆一层光刻胶，采用掩膜板对光刻胶进行曝光，使光刻胶形成光刻胶未保留区域和光刻胶保留区域，其中，光刻胶保留区域对应于第二连接线17的图形所在区域，光刻胶未保留区域对应于上述图形以外的区域；进行显影处理，光刻胶未保留区域的光刻胶被完全去除，光刻胶保留区域的光刻胶厚度保持不变；通过刻蚀工艺完全刻蚀掉光刻胶未保留区域的透明导电层薄膜，剥离剩余的光刻胶，形成第二连接线17，第二连接线17通过过孔161和162与第一连接线15连接。
本实施例中，通过第一连接线15和第二连接线17组成连接走线，连接 信号走线09和时钟信号线07，由于第一连接线15为完整的导电图案，其中不包括镂空区域，这样在形成第一连接线时，可以对第一透明导电层上用以形成第一连接线的光刻胶进行过曝光形成第一连接线，避免第一透明导电层残留在凹槽中，导致信号线短路不良。
本实施例中，显示基板的周边区域设置有多条平行设置且彼此间隔的时钟信号线07，相邻时钟信号线07的线宽可相同或彼此不同，相邻时钟信号线07之间的间距可以相同也可以不同。
其中，过孔(包括过孔161、162、163和164)可以为椭圆形过孔、圆形过孔或矩形过孔，过孔为椭圆形过孔即过孔在平行于衬底基板方向上的截面(在XY平面上的截面)为椭圆形，过孔为圆形过孔即过孔在平行于衬底基板方向上的截面(在XY平面上的截面)为圆形，过孔为矩形过孔即过孔在平行于衬底基板方向上的截面(在XY平面上的截面)为矩形过孔，一些实施例中，过孔可以为矩形过孔，矩形的边长可以为6-8um。
需要说明，本说明书中的各个实施例均采用递进的方式描述，各个实施例之间相同相似的部分互相参见即可，每个实施例重点说明的都是与其他实施例的不同之处。尤其，对于实施例而言，由于其基本相似于产品实施例，所以描述得比较简单，相关之处参见产品实施例的部分说明即可。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
可以理解，当诸如层、膜、区域或基板之类的元件被称作位于另一元件“上”或“下”时，该元件可以“直接”位于另一元件“上”或“下”，或者可以存在 中间元件。
在上述实施方式的描述中，具体特征、结构、材料或者特点可以在任何的一个或多个实施例或示例中以合适的方式结合。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (17)

  1. 一种显示基板，包括衬底基板，所述衬底基板包括显示区域和环绕所述显示区域的周边区域，其特征在于，所述显示基板包括：
    位于所述衬底基板的所述周边区域的第一信号线和第二信号线；
    第一绝缘层，位于所述第一信号线远离所述衬底基板一侧；
    所述第一信号线和所述第二信号线之间通过连接走线连接，所述连接走线位于所述第一绝缘层远离所述衬底基板的一侧，所述第一绝缘层远离所述衬底基板的一侧形成有凹槽，所述凹槽的槽深大于预设阈值，所述连接走线在所述衬底基板上的正投影与所述凹槽在所述衬底基板上的正投影交叠；
    所述连接走线包括：
    第一连接线，所述第一连接线包括第一部分和第二部分，其中第一部分覆盖所述凹槽的底部和侧壁，第二部分覆盖所述第一绝缘层位于所述凹槽之外区域。
  2. 根据权利要求1所述的显示基板，其特征在于，还包括：
    位于所述第一连接线远离所述衬底基板一侧的第二绝缘层；
    所述连接走线还包括：
    位于所述第二绝缘层远离所述衬底基板一侧的第二连接线，所述第二连接线通过贯穿所述第二绝缘层的过孔与所述第一连接线连接，所述第二连接线用以连接所述第一连接线与所述第一信号线和所述第二信号线，所述第二连接线在所述衬底基板上的正投影与所述凹槽在所述衬底基板上的正投影不交叠，所述过孔的深度小于所述凹槽的槽深。
  3. 根据权利要求2所述的显示基板，其特征在于，所述第一部分在所述衬底基板上的第一正投影位于所述凹槽在所述衬底基板上的正投影内，所述第二部分在所述衬底基板上的第二正投影位于所述凹槽在所述衬底基板上的正投影外，所述第一正投影与所述第二正投影的面积比为6：1-1：1。
  4. 根据权利要求2所述的显示基板，其特征在于，所述第一连接线的延伸方向与所述第一信号线的延伸方向平行。
  5. 根据权利要求2所述的显示基板，其特征在于，相邻所述第一连接线之间的距离为10-15um。
  6. 根据权利要求2所述的显示基板，其特征在于，所述第二连接线包括有镂空区域，所述镂空区域的延伸方向与所述第二连接线的延伸方向平行。
  7. 根据权利要求6所述的显示基板，其特征在于，所述第二连接线包括第三部分和第四部分，所述第三部分在所述衬底基板上的第三正投影位于所述第一连接线在所述衬底基板上的正投影内，所述第四部分在所述衬底基板上的第四正投影位于所述第一连接线在所述衬底基板上的正投影外，所述第三正投影与所述第四正投影的面积比为1:20-1:25。
  8. 根据权利要求6所述的显示基板，其特征在于，所述第二连接线包括第五部分和第六部分，所述第五部分在所述衬底基板上的第五正投影位于所述过孔在所述衬底基板上的正投影内，所述第六部分在所述衬底基板上的第六正投影位于所述过孔在所述衬底基板上的正投影外，所述第五正投影与所述第六正投影的面积比为1:20-1:25。
  9. 根据权利要求6所述的显示基板，其特征在于，所述第二连接线包括第七部分和第八部分，所述第七部分连接所述第一连接线和所述第一信号线，所述第八部分连接所述第一连接线和所述第二信号线，所述第七部分的延伸方向与所述第一信号线平行，所述第八部分为L型，所述第八部分包括与所述第一信号线平行的第一子部分和与所述第二信号线平行的第二子部分。
  10. 根据权利要求2所述的显示基板，其特征在于，所述过孔为矩形过孔，边长为6-8um。
  11. 根据权利要求1所述的显示基板，其特征在于，所述预设阈值为2um。
  12. 根据权利要求1所述的显示基板，其特征在于，所述连接走线采用透明导电材料。
  13. 根据权利要求2所述的显示基板，其特征在于，
    所述第二连接线与所述显示基板的像素电极同层同材料；和/或，
    所述第一连接线与所述显示基板的公共电极同层同材料。
  14. 根据权利要求1所述的显示基板，其特征在于，
    所述第一信号线为栅极驱动单元的时钟信号线；
    所述第二信号线为扇形区域的信号走线。
  15. 一种显示装置，其特征在于，包括如权利要求1-14中任一项所述的显示基板。
  16. 一种显示基板的制作方法，其特征在于，所述显示基板包括衬底基板，所述衬底基板包括显示区域和环绕所述显示区域的周边区域，所述方法包括：
    在所述衬底基板的所述周边区域形成第一信号线和第二信号线；
    在所述第一信号线远离所述衬底基板的一侧形成第一绝缘层；
    形成连接所述第一信号线和所述第二信号线的连接走线，所述连接走线位于所述第一绝缘层远离所述衬底基板的一侧，所述第一绝缘层远离所述衬底基板的一侧形成有凹槽，所述凹槽的槽深大于预设阈值，所述连接走线在所述衬底基板上的正投影与所述凹槽在所述衬底基板上的正投影交叠；
    形成所述连接走线包括：
    在所述第一绝缘层远离所述衬底基板的一侧形成第一导电层，在所述第一导电层上形成光刻胶的图形，对所述光刻胶的图形进行过曝光，以所述光刻胶的图形为掩膜，对所述第一导电层进行刻蚀，形成第一连接线，所述第一连接线包括第一部分和第二部分，其中第一部分覆盖所述凹槽的底部和侧壁，第二部分覆盖所述第一绝缘层位于所述凹槽之外区域。
  17. 根据权利要求16所述的显示基板的制作方法，其特征在于，所述方法还包括：
    在所述第一连接线远离所述衬底基板的一侧形成第二绝缘层，对所述第二绝缘层进行构图，形成暴露出所述第一连接线的过孔，所述过孔的深度小于所述凹槽的槽深；
    形成所述连接走线还包括：
    在所述第二绝缘层远离所述衬底基板的一侧形成第二连接线，所述第二连接线通过贯穿所述第二绝缘层的过孔与所述第一连接线连接，所述第二连接线用以连接所述第一连接线与所述第一信号线和所述第二信号线，所述第 二连接线在所述衬底基板上的正投影与所述凹槽在所述衬底基板上的正投影不交叠，所述过孔的深度小于所述凹槽的槽深。
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