WO2023159513A1 - 显示基板及其制备方法、显示装置 - Google Patents

显示基板及其制备方法、显示装置 Download PDF

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Publication number
WO2023159513A1
WO2023159513A1 PCT/CN2022/078076 CN2022078076W WO2023159513A1 WO 2023159513 A1 WO2023159513 A1 WO 2023159513A1 CN 2022078076 W CN2022078076 W CN 2022078076W WO 2023159513 A1 WO2023159513 A1 WO 2023159513A1
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Prior art keywords
layer
substrate
structure layer
circuit structure
binding
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PCT/CN2022/078076
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English (en)
French (fr)
Inventor
浦超
杨盛际
卢鹏程
黄冠达
陈小川
Original Assignee
京东方科技集团股份有限公司
云南创视界光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 云南创视界光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to PCT/CN2022/078076 priority Critical patent/WO2023159513A1/zh
Priority to CN202280000380.1A priority patent/CN117063629A/zh
Publication of WO2023159513A1 publication Critical patent/WO2023159513A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods

Definitions

  • Micro Organic Light-Emitting Diode is a micro-display developed in recent years, and silicon-based OLED is one of them. Silicon-based OLED can not only realize the active addressing of pixels, but also realize the preparation of pixel driving circuit, timing control (TCON) circuit and over-current protection (OCP) circuit on the silicon-based substrate, which is beneficial to reduce the system volume, Achieve lightweight. Silicon-based OLED is prepared by mature Complementary Metal Oxide Semiconductor (CMOS) integrated circuit technology. It has the advantages of small size, high resolution (Pixels Per Inch, PPI for short), and high refresh rate. It is widely used in In the field of near-eye display such as virtual reality (Virtual Reality, referred to as VR), augmented reality (Augmented Reality, referred to as AR).
  • VR virtual reality
  • AR Augmented Reality
  • a circuit structure layer is formed on the substrate; a pixel drive circuit is arranged in the circuit structure layer of the display area, the pixel drive circuit includes a plurality of transistors, the circuit structure layer of the binding area includes a binding electrode, and On the composite insulating layer on the side of the binding electrode away from the substrate, the composite insulating layer is provided with a groove exposing the surface of the binding electrode away from the substrate;
  • a light-emitting structure layer is formed on the circuit structure layer of the display area; the light-emitting structure layer includes a light-emitting device connected to the pixel driving circuit.
  • FIG. 2 is a schematic diagram of the A-A sectional structure of the display substrate in FIG. 1 in some technologies
  • FIG. 3 is a schematic diagram of the A-A cross-sectional structure of the display substrate of FIG. 1 in some exemplary embodiments;
  • Fig. 6b is a schematic structural view after forming the first conductive pillars in the method for preparing the display substrate in some exemplary embodiments;
  • Fig. 6e is a schematic structural view after forming a fifth insulating layer in the method for manufacturing a display substrate in some exemplary embodiments;
  • Fig. 7a is a schematic structural view after forming a circuit structure layer in the method for preparing a display substrate in other exemplary embodiments;
  • Fig. 7b is a schematic diagram of the structure after the filling layer is formed in the manufacturing method of the display substrate in some other exemplary embodiments.
  • FIG. 1 is a schematic plan view of a display substrate in some exemplary embodiments.
  • the display substrate includes a display area 100 and a non-display area 200 located around the display area 100.
  • the non-display area 200 includes a display area 100- Binding region 300 on the side.
  • the display area 100 is provided with a plurality of sub-pixels regularly arranged for image display, each sub-pixel includes a pixel driving circuit and a light-emitting device connected to the pixel driving circuit, and the non-display area 200 is provided with a control circuit for controlling the light emission of the sub-pixels,
  • the bonding area 300 is provided with pads 310 for bonding connection with an external circuit board.
  • the display area 100 is rectangular, and in other implementation manners, the display area 100 may be circular or other shapes, which are not limited.
  • FIG. 3 is a schematic diagram of the A-A cross-sectional structure of the display substrate of FIG. 1 in some exemplary embodiments.
  • the structural layer 30 includes a light-emitting device 301 connected to the pixel driving circuit; a pad 310 is provided in the circuit structural layer 20 of the bonding area 300, and the pad 310 is configured to be bonded and connected to an external circuit board, The surface of the pad 310 is flush with the surface of the circuit structure layer 20 around
  • the surface of the pad 310 is arranged flush with the surface of the circuit structure layer 20 around the pad 310 away from the substrate 10, so that no pit is formed at the position of the pad 310, so that in the preparation
  • the first electrode of the light-emitting device 301 of the display substrate during the development process, there will be no photoresist residue at the position of the pad 310, so that the photoresist residue in the pit of the pad 310 can be avoided. Display the twill mura problem generated by the substrate when displaying the picture, and improve the product yield.
  • the circuit structure layer 20 of the display area 100 is provided with a pixel driving circuit and some signal lines, such as scanning signal lines, data signal lines, and power lines. (VDD), etc.
  • the pixel driving circuit includes a plurality of transistors (T) 210 and storage capacitors (C), and the pixel driving circuit can be fabricated using CMOS (Complementary Metal Oxide Semiconductor) integrated circuit technology.
  • CMOS Complementary Metal Oxide Semiconductor
  • the pixel driving circuit may be a circuit structure such as 3T1C, 5T1C or 7T1C, which is not limited in this disclosure.
  • the light emitting structure layer 30 may include a first electrode layer, a pixel defining layer 32 , a light emitting functional layer 33 and a second electrode layer 34 .
  • the first electrode layer includes a plurality of first electrodes 31 arranged on the circuit structure layer 20, each first electrode 31 is connected to one of the pixel driving circuits, and the pixel defining layer 32 is arranged on the plurality of electrodes.
  • the encapsulation structure layer may include a plurality of stacked inorganic material layers, for example, may include a first inorganic material layer and a second inorganic material layer stacked in sequence along a direction away from the substrate.
  • Materials for the first inorganic material layer and the second inorganic material layer may include any one or more of silicon nitride, silicon oxide, and silicon oxynitride.
  • the encapsulation structure layer may further include an organic material layer disposed between the first inorganic material layer and the second inorganic material layer.
  • the circuit structure layer 20 of the binding region 300 includes a binding electrode 311 , and a A composite insulating layer, the composite insulating layer is provided with a groove exposing the surface of the binding electrode 311 away from the substrate 10, a filling layer 314 is arranged in the groove, and the surface of the filling layer 314 and the surface of the composite insulating layer around the groove that is away from the substrate 10; the pad 310 includes the binding electrode 311 and the filling layer 314, and the surface of the pad 310 is the surface of the filling layer 314 .
  • the circuit structure layer of the display area includes a plurality of conductive layers arranged in sequence along the direction away from the substrate; the pad includes a binding electrode and a distance away from the binding electrode At least one connection layer on one side of the substrate, between one connection layer close to the binding electrode and the binding electrode, and between two adjacent connection layers are connected through conductive columns; The binding electrode and any one of the connection layers are arranged on the same layer as the film layers in the plurality of conductive layers.
  • FIG. 4 is a schematic diagram of the A-A sectional structure of the display substrate in FIG. 1 in other exemplary embodiments.
  • FIG. 4 shows three sub-pixels (respectively P1, P2 and P3), each sub-pixel includes a pixel driving circuit and a light-emitting device 301 connected to the pixel driving circuit, the pixel driving circuit includes a plurality of transistors 210 and storage capacitors, one transistor 210 is shown in each sub-pixel in FIG. 4 .
  • the number of insulating layers in the bonding area 300 is the same as the number of insulating layers in the display area 100 , both being five layers.
  • the thickness of the fifth insulating layer 25 of the bonding area 300 is smaller than the thickness of the fifth insulating layer 25 of the display area 100 .
  • the circuit structure layer 20 of the display area 100 is provided with four conductive layers, and the connection layer of the bonding pad 310 on the side away from the substrate 10 of the bonding electrode 311 includes a first connection layer 3121 and the second connection layer 3122 are two film layers.
  • the circuit structure layer of the display area may be provided with three, five or more than five conductive layers, and the number of conductive layers may be determined according to the structure of the pixel driving circuit and the wiring method of the signal lines. It is provided that the number of film layers of the connection layer in the pad can be one, three or more than three. The present disclosure does not limit the number of film layers of the conductive layer of the circuit structure layer in the display area and the number of film layers of the connection layer in the pad.
  • FIG. 5 is a schematic diagram of the A-A cross-sectional structure of the display substrate shown in FIG. 1 in some other exemplary embodiments.
  • FIG. 5 shows three sub-pixels, each sub-pixel includes A driving circuit and a light emitting device 301 connected to the pixel driving circuit, the pixel driving circuit includes a plurality of transistors 210 and storage capacitors, one transistor 210 is shown in each sub-pixel in FIG. 5 .
  • the circuit structure layer 20 of the display area 100 may include a first insulating layer 21, a first conductive layer 201, a second insulating layer 22, and a second conductive layer 202 arranged in sequence along a direction away from the substrate 10.
  • the first conducting layer 201 may comprise The gate electrode 2011 of the transistor 210 of each sub-pixel, the second conductive layer 202 can include the source electrode 2021 and the drain electrode 2022 of the transistor 210 of each sub-pixel, and some signal lines (such as scanning signal lines), the third conductive layer 203 can Including data signal lines and the like, the fourth conductive layer 204 may include a power supply line (VDD) and the like, and the fifth conductive layer 205 may include connection electrodes connected to other conductive layers and the like.
  • VDD power supply line
  • the pillars 313 are connected, and the material of the conductive pillars 313 may include tungsten.
  • the number of layers of the insulating layer in the display area 100 is six layers
  • the number of layers of the insulating layer in the bonding area 300 is four layers
  • the number of layers of the insulating layer in the bonding area 300 is smaller than that of the insulating layer in the display area 100 number.
  • the thickness of the fourth insulating layer 24 of the bonding area 300 is smaller than the thickness of the fourth insulating layer 24 of the display area 100 .
  • the circuit structure layer 20 of the display area 100 is provided with five conductive layers, and the number of film layers of the connection layer on the side of the bonding electrode 311 away from the substrate 10 of the pad 310 is for one.
  • the circuit structure layer of the display area can be provided with three, four or more than five conductive layers, and the number of conductive layers can be determined according to the structure of the pixel driving circuit and the wiring method of the signal lines. It is provided that the number of film layers of the connection layer in the pad can be two, three or more than three. The present disclosure does not limit the number of film layers of the conductive layer of the circuit structure layer in the display area and the number of film layers of the connection layer in the pad.
  • the plurality of conductive layers include a first conductive layer 201 and a second conductive layer 202 arranged in sequence along a direction away from the substrate 10, and arranged in At least one conductive layer on the side of the second conductive layer 202 away from the substrate 10;
  • the first conductive layer 201 may include the gate electrode 2011 of the transistor 210, and the second conductive layer 202 may include the The source electrode 2021 and the drain electrode 2022 of the transistor 210;
  • the binding electrode 311 and the second conductive layer 202 can be arranged in the same layer.
  • the binding electrode 311 can be arranged on the same layer as other conductive layers.
  • the number of insulating layers of the circuit structure layer of the bonding area may be less than or equal to the number of insulating layers of the circuit structure layer of the display area.
  • the number of insulating layers of the circuit structure layer 20 in the bonding area 300 is the same as the number of insulating layers of the circuit structure layer 20 in the display area 100 , both of which are five layers. In the example of FIG.
  • the number of layers of the insulating layer of the circuit structure layer 20 of the display area 100 is six layers
  • the number of layers of the insulating layer of the circuit structure layer 20 of the bonding area 300 is four layers
  • the circuit of the bonding area 300 The number of insulating layers of the structural layer 20 is less than the number of insulating layers of the circuit structural layer 20 of the display area 100 .
  • the number of layers of the conductive layer of the circuit structure layer of the display area can be other layers.
  • a circuit structure layer is formed on the substrate; a pixel drive circuit is provided in the circuit structure layer of the display area, and the pixel drive circuit includes a plurality of transistors, and a pad is provided in the circuit structure layer of the binding area, so The pad is configured to be bonded to an external circuit board, and the surface of the pad is flush with the surface of the circuit structure layer around the pad that is away from the substrate.
  • the circuit structure layer of the display area includes a plurality of conductive layers arranged in sequence along the direction away from the substrate; the pad includes a binding electrode and a distance away from the binding electrode At least one connection layer on one side of the substrate, between one connection layer close to the binding electrode and the binding electrode, and between two adjacent connection layers are connected through conductive columns; The binding electrode and any one of the connection layers are arranged on the same layer as the film layers in the plurality of conductive layers.
  • the preparation process of the display substrate of the present disclosure is exemplarily described below.
  • the "patterning process” mentioned in this disclosure includes coating photoresist, mask exposure, developing, etching and stripping photoresist. Any one or more of sputtering, evaporation and chemical vapor deposition can be used for deposition, any one or more of spray coating and spin coating can be used for coating, and any of dry etching and wet etching can be used for etching. one or more.
  • “Film” refers to a layer of film produced by depositing or coating a certain material on a substrate. If the "thin film” does not require a patterning process during the entire manufacturing process, the “thin film” can also be called a "layer".
  • the "thin film” requires a patterning process throughout the production process, it is called a "film” before the patterning process, and it is called a “layer” after the patterning process.
  • the "layer” after the patterning process includes at least one "pattern”.
  • a and B are arranged in the same layer” in this disclosure means that A and B are formed simultaneously through the same patterning process.
  • the orthographic projection of A includes the orthographic projection of B” in this disclosure means that the orthographic projection of B falls within the range of the orthographic projection of A, or the orthographic projection of A covers the orthographic projection of B.
  • the display substrate illustrated in FIG. 4 is a silicon-based OLED display substrate as an example.
  • the preparation process may include the following steps:
  • the pixel driving circuit may include a plurality of transistors and a storage capacitor, and the plurality of transistors may include at least one P-type transistor and at least one N-type transistor.
  • Forming the silicon-based substrate may include: providing a silicon-based substrate, such as a single-crystal silicon substrate; forming a plurality of N-type well regions and a plurality of P-type well regions on the single-crystal silicon substrate, and the N-type well regions may be As the active layer of the P-type transistor in the pixel driving circuit, the P-type well region can be used as the active layer of the N-type transistor in the pixel driving circuit.
  • forming the pattern of the first insulating layer 21 and the first conductive layer 201 may include: sequentially depositing a first insulating film and a polysilicon film on the silicon-based substrate 10, and first patterning the polysilicon film through a patterning process chemical treatment to form the first insulating layer 21 covering the silicon-based substrate 10 and the polysilicon layer pattern disposed on the first insulating layer 21; using the polysilicon layer pattern as a shielding layer, carry out two regions of the N-type well region P-type doping to form the first region and the second region of the active layer of the P-type transistor, N-type doping is performed on the two regions of the P-type well region to form the active layer of the N-type transistor
  • the first area and the second area; the polysilicon layer pattern can be heavily doped, so that the polysilicon layer with higher resistance becomes the first conductive layer 201 with lower resistance, and the first conductive layer
  • the second insulating layer 22 is provided with a plurality of via holes, and the plurality of via holes may include a first via hole and a second via hole, and the first insulating layer 21 and the second insulating layer 22 in the first via hole and the second via hole being etched away, the first via hole exposes the first region of the active layer, and the second via hole exposes the second region of the active layer.
  • a second conductive film is deposited on the second insulating layer 22 , and the second conductive film is patterned by a patterning process to form a pattern of the second conductive layer 202 on the second insulating layer 22 .
  • the via holes in the display area 100 can be configured to connect the subsequently formed third conductive layer 203 with the second The conductive layer 202 is connected, and the third via hole 231 of the bonding region 300 exposes a part of the surface of the bonding electrode 311 . As shown in Figure 6a.
  • the via hole provided in the third insulating layer 23 is filled with a metal conductive material (such as a tungsten metal material, and a via hole filled with tungsten metal can be called a tungsten hole); filling in the third insulating layer
  • the metal conductive material in the via hole 23 can be called a conductive column, and the metal conductive material located in the third via hole 231 is a first conductive column 3131, and the first conductive column 3131 is configured to connect the subsequently formed first connection layer 3121 with the
  • the bonding electrodes 311 are connected, and the conductive pillars of the third insulating layer 23 located in the plurality of via holes in the display area 100 can be configured to connect the subsequently formed third conductive layer 203 with the second conductive layer 202 .
  • Figure 6b As shown in Figure 6b.
  • the third conductive layer 203 and the fourth insulating layer 24 are formed.
  • forming the third conductive layer 203 and the fourth insulating layer 24 may include: depositing a third conductive film on the silicon-based substrate 10 formed with the aforementioned pattern, and patterning the third conductive film through a patterning process. chemical treatment to form a pattern of the third conductive layer 203 on the third insulating layer 23 .
  • the pattern of the third conductive layer 203 may include a power line etc. located in the display area 100 , and a first connection layer 3121 located in the binding area 300 , the first connection layer 3121 is connected to the binding electrode 311 through the first conductive pillar 3131 .
  • a fourth insulating film is deposited on the previously patterned silicon-based substrate 10, and the fourth insulating film is patterned through a patterning process to form a fourth insulating layer 24 covering the pattern of the third conductive layer 203.
  • the fourth insulating layer 24 is provided with a plurality of via holes located in the display area 100 and a fourth via hole 241 located in the binding area 300.
  • the via holes in the display area 100 can be configured to connect the subsequently formed fourth conductive layer 204 with the third
  • the conductive layer 203 is connected, and the fourth via hole 241 of the bonding region 300 exposes a part of the surface of the first connection layer 3121 . As shown in Figure 6c.
  • the via hole provided in the fourth insulating layer 24 is filled with a metal conductive material (such as a tungsten metal material, and a via hole filled with tungsten metal can be called a tungsten hole);
  • the metal conductive material in the via hole 24 can be called a conductive column, and the metal conductive material located in the fourth via hole 241 is the second conductive column 3132, and the second conductive column 3132 is configured to connect the subsequently formed second connection layer 3122 with the
  • the first connection layer 3121 is connected, and the conductive columns of the fourth insulating layer 24 located in the plurality of via holes in the display area 100 can be configured to connect the subsequently formed fourth conductive layer 204 with the third conductive layer 203 .
  • Figure 6d As shown in Figure 6d.
  • Forming the fourth conductive layer 204 and the fifth insulating layer 25 may include: depositing a fourth conductive film on the silicon-based substrate 10 formed with the aforementioned pattern, patterning the fourth conductive film through a patterning process, and performing a patterning process on the fourth conductive film.
  • a pattern of the fourth conductive layer 204 is formed on the insulating layer 24 .
  • the pattern of the fourth conductive layer 204 may include some signal lines located in the display area 100 and connection electrodes connected to other conductive layers, and the second connection layer 3122 located in the binding area 300; the second connection layer 3122 passes through the second conductive column 3132 Connect with the first connection layer 3121.
  • a fifth insulating layer 25 is formed on the aforementioned patterned silicon-based substrate 10 .
  • forming the fifth insulating layer 25 may include: depositing a fifth insulating film on the silicon-based substrate 10 formed with the aforementioned pattern, and patterning the fifth insulating film through a patterning process to form a covering fourth conductive layer. 204 pattern of the fifth insulating layer 25 .
  • patterning the fifth insulating film may include: thinning the surface of the fifth insulating film in the bonding region 300 away from the substrate 10 , and forming a plurality of via holes to form the fifth insulating layer 25 .
  • the surface of the fifth insulating layer 25 of the binding area 300 facing away from the substrate 10 is flush with the surface of the second connection layer 3122, and the multiple via holes provided on the fifth insulating layer 25 of the display area 100 can be configured to connect the subsequently formed
  • the first electrode 31 of the light emitting device 301 is connected to the fourth conductive layer 204 .
  • forming the fifth insulating layer 25 may include: depositing a first sub-insulation film on the silicon-based substrate 10 with the aforementioned pattern formed, the surface of the first sub-insulation film is flush with the surface of the second connection layer 3122 setting; subsequently, depositing a second sub-insulation film in the display area 100; patterning the second sub-insulation film and the first sub-insulation film in the display area 100 through a patterning process to form the fifth insulation layer 25.
  • the fifth insulating layer 25 of the display area 100 includes a stacked first sub-insulation layer and a second sub-insulation layer, and covers the fourth conductive layer 204 of the display area 100, and the fifth insulating layer 25 of the display area 100 is provided with A plurality of via holes, the plurality of via holes may be configured to connect the first electrode 31 of the subsequently formed light emitting device 301 with the fourth conductive layer 204 .
  • the fifth insulating layer 25 of the bonding region 300 includes the first sub-insulating layer and does not include the second sub-insulating layer, and the surface of the fifth insulating layer 25 of the bonding region 300 facing away from the substrate 10 is connected to the surface of the second connection layer 3122 flush. As shown in Figure 6e.
  • the binding electrode 311, the first conductive column 3131, the first connection layer 3121, the second conductive column 3132 and the second connection layer 3122 form the pad 310, and the surface of the second connection layer 3122 is the pad 310
  • the surface of the pad 310 is flush with the surface of the circuit structure layer 20 around the pad 310 that is away from the substrate 10 .
  • the pixel-defining layer 32 is provided with a plurality of pixel openings, each The pixel opening exposes a surface of a corresponding first electrode 31 away from the substrate 10 .
  • the light-emitting functional layer 33 and the second electrode layer 34 are sequentially formed on the silicon-based substrate 10 with the aforementioned pattern formed.
  • Each of the first electrode 31 , the light-emitting functional layer 33 and the second electrode layer 34 is sequentially stacked to form a light-emitting device 301 . As shown in Figure 4.
  • An embodiment of the present disclosure also provides another method for preparing a display substrate, where the display substrate includes a display area and a binding area located on one side of the display area; the preparation method includes:
  • a circuit structure layer is formed on the substrate; a pixel drive circuit is arranged in the circuit structure layer of the display area, the pixel drive circuit includes a plurality of transistors, the circuit structure layer of the binding area includes a binding electrode, and On the composite insulating layer on the side of the binding electrode away from the substrate, the composite insulating layer is provided with a groove exposing the surface of the binding electrode away from the substrate;
  • a filling layer is formed in the groove, and the surface of the filling layer is flush with the surface of the composite insulating layer around the groove that is away from the substrate; the binding electrode and the filling layer form a solder a pad, and the pad is configured to be bonded and connected to an external circuit board;
  • a light-emitting structure layer is formed on the circuit structure layer of the display area; the light-emitting structure layer includes a light-emitting device connected to the pixel driving circuit.
  • the circuit structure layer of the display area includes a plurality of conductive layers arranged in sequence along the direction away from the substrate, and the binding electrode is arranged on the same layer as one of the plurality of conductive layers , the filling layer is not disposed on the same layer as the film layers in the plurality of conductive layers.
  • the display substrate illustrated in FIG. 3 is a silicon-based OLED display substrate as an example.
  • the preparation process may include the following steps :
  • the circuit structure layer 20 is formed on the substrate 10 .
  • forming the circuit structure layer 20 on the substrate 10 may include: forming a silicon-based substrate 10 , and sequentially forming a plurality of conductive layers on the silicon-based substrate 10 .
  • the circuit structure layer 20 of the display area 100 includes a pixel drive circuit, and signal lines such as scanning signal lines, data signal lines, and power lines, and the pixel drive circuit includes a plurality of transistors 210; the binding area
  • the circuit structure layer 20 of 300 includes a binding electrode 311, and a composite insulating layer disposed on the side of the binding electrode 311 away from the substrate, and the composite insulating layer is provided with a layer exposing the binding electrode 311.
  • the groove 320 is remote from the surface of the substrate.
  • the binding electrode 311 is arranged on the same layer as one of the plurality of conductive layers. As shown in Figure 7a.
  • a filling layer 314 is formed in the groove 320 , the surface of the filling layer 314 is flush with the surface of the composite insulating layer around the groove 320 away from the substrate 10 .
  • the filling layer 314 is disposed on the surface of the bonding electrode 311, the bonding electrode 311 and the filling layer 314 form a pad 310, and the pad 310 is configured to be bonded to an external circuit board.
  • the material of the filling layer 314 may be metal conductive material, such as aluminum. As shown in Figure 7b.
  • the light-emitting structure layer 30 includes a light-emitting device 301 connected to the pixel driving circuit, and the light-emitting device 301 includes a first electrode 31, a light-emitting functional layer 33 and a second electrode layer 34 stacked in sequence along the direction away from the substrate 10 . As shown in Figure 3.
  • the surface of the pad 310 is flush with the surface of the circuit structure layer 20 around the pad 310 that is away from the substrate 10 , In this way, no pit is formed at the location of the pad 310, so that during the preparation of the first electrode 31 of the light-emitting device 301, during the development process, there will be no photoresist residues at the location of the pad 310, thereby avoiding Due to the photoresist residues in the pits of the pads 310 , the problem of oblique lines mura generated on the display substrate when displaying pictures is caused, thereby improving the product yield.
  • An embodiment of the present disclosure further provides a display device, comprising the display substrate described in any one of the foregoing embodiments.
  • the display device can be a near-eye display device, such as VR glasses, a helmet display, etc.; or, the display device can be any product or component with a display function such as a mobile phone, a tablet computer, a TV, a monitor, a notebook computer, a digital photo frame, a navigator, etc. .
  • a transistor refers to an element including at least three terminals of a gate electrode, a drain electrode, and a source electrode.
  • a transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode .
  • a channel region refers to a region through which current mainly flows.
  • parallel refers to a state where the angle formed by two straight lines is -10° or more and 10° or less, and thus includes a state where the angle is -5° or more and 5° or less.
  • perpendicular refers to a state where the angle formed by two straight lines is 80° to 100°, and thus includes an angle of 85° to 95°.
  • connection means a fixed connection, or a detachable connection, or Connected integrally;
  • mounted means “connected”, and “fixedly connected” may be directly connected, indirectly connected through an intermediary, or internally connected between two components.

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Abstract

一种显示基板，显示基板包括显示区(100)和位于显示区(100)一侧的绑定区(300)；显示基板包括衬底(10)和设于衬底(10)上的电路结构层(20)；显示区(100)的电路结构层(20)内设有像素驱动电路，像素驱动电路包括多个晶体管(210)，显示区(100)还包括依次叠设于电路结构层(20)的远离衬底(10)一侧的发光结构层(30)和封装结构层(40)，发光结构层(30)包括与像素驱动电路连接的发光器件(301)；绑定区(300)的电路结构层(20)内设有焊盘(310)，焊盘(310)配置为与外部的电路板绑定连接，焊盘(310)的表面与焊盘(310)周围的电路结构层(20)的背离衬底(10)的表面平齐设置。

Description

显示基板及其制备方法、显示装置 技术领域
本公开实施例涉及但不限于显示技术领域，具体涉及一种显示基板及其制备方法、显示装置。
背景技术
微型有机发光二极管(Micro Organic Light-Emitting Diode，简称Micro-OLED)是近年来发展起来的微型显示器，硅基OLED是其中一种。硅基OLED不仅可以实现像素的有源寻址，并且可以实现在硅基衬底上制备像素驱动电路、时序控制(TCON)电路和过电流保护(OCP)电路等，有利于减小系统体积，实现轻量化。硅基OLED采用成熟的互补金属氧化物半导体(Complementary Metal Oxide Semiconductor，简称CMOS)集成电路工艺制备，具有体积小、高分辨率(Pixels Per Inch，简称PPI)、高刷新率等优点，广泛应用在虚拟现实(Virtual Reality，简称VR)、增强现实(Augmented Reality，简称AR)等近眼显示领域中。
发明内容
以下是对本文详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
本公开实施例提供一种显示基板，所述显示基板包括显示区和位于所述显示区一侧的绑定区；所述显示基板包括衬底和设于所述衬底上的电路结构层；所述显示区的电路结构层内设有像素驱动电路，所述像素驱动电路包括多个晶体管，所述显示区还包括依次叠设于电路结构层的远离所述衬底一侧的发光结构层和封装结构层，所述发光结构层包括与所述像素驱动电路连接的发光器件；所述绑定区的电路结构层内设有焊盘，所述焊盘配置为与外部的电路板绑定连接，所述焊盘的表面与所述焊盘周围的电路结构层的背离所述衬底的表面平齐设置。
本公开实施例还提供一种显示装置，包括所述的显示基板。
本公开实施例还提供一种显示基板的制备方法，所述显示基板包括显示区和位于所述显示区一侧的绑定区；所述制备方法包括：
在衬底上形成电路结构层；所述显示区的电路结构层内设有像素驱动电路，所述像素驱动电路包括多个晶体管，所述绑定区的电路结构层包括绑定电极，以及设于所述绑定电极的远离所述衬底一侧的复合绝缘层，所述复合绝缘层设有暴露出所述绑定电极的远离所述衬底的表面的凹槽；
在所述凹槽内形成填充层，所述填充层的表面与所述凹槽周围的复合绝缘层的背离所述衬底的表面平齐设置；所述绑定电极和所述填充层组成焊盘，所述焊盘配置为与外部的电路板绑定连接；
在所述显示区的电路结构层上形成发光结构层；所述发光结构层包括与所述像素驱动电路连接的发光器件。
本公开实施例还提供另一种显示基板的制备方法，所述显示基板包括显示区和位于所述显示区一侧的绑定区；所述制备方法包括：
在衬底上形成电路结构层；所述显示区的电路结构层内设有像素驱动电路，所述像素驱动电路包括多个晶体管，所述绑定区的电路结构层内设有焊盘，所述焊盘配置为与外部的电路板绑定连接，所述焊盘的表面与所述焊盘周围的电路结构层的背离所述衬底的表面平齐设置。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图说明
附图用来提供对本公开技术方案的进一步理解，并且构成说明书的一部分，与本公开的实施例一起用于解释本公开的技术方案，并不构成对本公开技术方案的限制。附图中部件的形状和大小不反映真实比例，目的只是示意说明本公开内容。
图1为一些示例性实施例的显示基板的平面结构示意图；
图2为一些技术中图1的显示基板的A-A剖面结构示意图；
图3为在一些示例性实施例中图1的显示基板的A-A剖面结构示意图；
图4为在另一些示例性实施例中图1的显示基板的A-A剖面结构示意图；
图5为在又一些示例性实施例中图1的显示基板的A-A剖面结构示意图；
图6a为在一些示例性实施例的显示基板的制备方法中形成第三绝缘层后的结构示意图；
图6b为在一些示例性实施例的显示基板的制备方法中形成第一导电柱后的结构示意图；
图6c为在一些示例性实施例的显示基板的制备方法中形成第四绝缘层后的结构示意图；
图6d为在一些示例性实施例的显示基板的制备方法中形成第二导电柱后的结构示意图；
图6e为在一些示例性实施例的显示基板的制备方法中形成第五绝缘层后的结构示意图；
图7a为在另一些示例性实施例的显示基板的制备方法中形成电路结构层后的结构示意图；
图7b为在另一些示例性实施例的显示基板的制备方法中形成填充层后的结构示意图。
具体实施方式
本领域的普通技术人员应当理解，可以对本公开实施例的技术方案进行修改或者等同替换，而不脱离本公开实施例技术方案的精神和范围，均应涵盖在本公开的权利要求范围当中。
如图1所示，图1为一些示例性实施例的显示基板的平面结构示意图，显示基板包括显示区100和位于显示区100周边的非显示区200，非显示区200包括位于显示区100一侧的绑定区300。显示区100设置有规则排布的多个子像素，以进行图像显示，每个子像素包括像素驱动电路和与像素驱动电路连接的发光器件，非显示区200设置有用于控制子像素发光的控制电路，绑定区300设置有用于与外部电路板绑定连接的焊盘310。图1的示例中，显示区100为矩形，在其他实施方式中，显示区100可以为圆形或者其他形状，对此不做限定。
如图2所示，图2为一些技术中图1的显示基板的A-A剖面结构示意图，示例性地，显示基板可以为硅基OLED显示基板，在垂直于显示基板的平面内，显示基板的显示区100和绑定区300均包括硅基衬底10和设于硅基衬底10上的电路结构层20；显示区100的电路结构层20内设有多个像素驱动电路，每个像素驱动电路包括多个晶体管210和存储电容，显示区100还包括依次叠设于电路结构层20的远离硅基衬底10一侧的发光结构层30和封装结构层40，发光结构层30包括多个发光器件301，每个发光器件301与对应的一个像素驱动电路连接，所述发光器件301可以包括沿远离硅基衬底10方向依次叠设的第一电极31、发光功能层33和第二电极层34。绑定区300的电路结构层20内设有焊盘310，焊盘310表面低于焊盘310周围的电路结构层20的背离硅基衬底10的表面设置，即焊盘310所在位置呈凹坑状，这样，在制备显示基板的第一电极31过程(包括成膜、涂胶、曝光、显影和刻蚀等工序)中，其中在显影过程中，焊盘310所在位置的凹坑内会有光阻残留物，光阻残留物在硅基衬底(可称为晶片，wafer)10旋转时会甩到硅基衬底10上制备的膜层表面上，光阻残留物通常不导电，如果光阻残留物甩到金属与金属搭接位置则会影响搭接位置的导电性能，最终会影响一些子像素的发光亮度，进而会导致显示基板在显示画面时产生斜纹mura(亮度不均)问题，造成产品良率降低。
如图3所示，图3为在一些示例性实施例中图1的显示基板的A-A剖面结构示意图，图3的示例中示意了三个子像素，所述显示基板包括显示区100和位于所述显示区100一侧的绑定区300；所述显示基板包括衬底10和设于所述衬底10上的电路结构层20；所述显示区100的电路结构层20内设有像素驱动电路，所述像素驱动电路包括多个晶体管210，所述显示区100还包括依次叠设于电路结构层20的远离所述衬底10一侧的发光结构层30和封装结构层40，所述发光结构层30包括与所述像素驱动电路连接的发光器件301；所述绑定区300的电路结构层20内设有焊盘310，所述焊盘310配置为与外部的电路板绑定连接，所述焊盘310的表面与所述焊盘310周围的电路结构层20的背离所述衬底10的表面平齐设置。
本公开实施例的显示基板，将焊盘310的表面与焊盘310周围的电路结 构层20的背离衬底10的表面平齐设置，如此，焊盘310所在位置没有形成凹坑，这样在制备显示基板的发光器件301的第一电极过程中，其中在显影过程中，不会在焊盘310所在位置有光阻残留物存在，从而可以避免由于焊盘310凹坑内的光阻残留物导致的显示基板在显示画面时产生的斜纹mura问题，提高产品良率。
本文中，所述焊盘的表面与所述焊盘周围的电路结构层的背离所述衬底的表面平齐设置，其中的“平齐”是指焊盘的表面与焊盘周围的电路结构层的背离衬底的表面的高度差允许在一定误差范围内，该误差范围可以是，以所述衬底的表面为基准面，焊盘的表面高度与焊盘周围的电路结构层的背离衬底的表面高度的比值范围为95％至110％。
在一些示例性实施例中，如图3所示，所述显示基板可以是硅基OLED显示基板，所述显示基板的衬底10为硅基衬底。在其他实施方式中，所述显示基板可以是其他类型的显示基板，所述显示基板的衬底10可以为玻璃衬底或柔性衬底等。
在一些示例性实施例中，如图3所示，所述显示区100的电路结构层20内设有像素驱动电路，还设有一些信号线，比如，扫描信号线、数据信号线、电源线(VDD)等。所述像素驱动电路包括多个晶体管(T)210和存储电容(C)，所述像素驱动电路可以采用CMOS(互补金属氧化物半导体)集成电路工艺制备。所述像素驱动电路可以是3T1C、5T1C或7T1C等电路结构，本公开对此不做限定。
在一些示例性实施例中，如图3所示，所述发光结构层30可以包括第一电极层、像素界定层32、发光功能层33和第二电极层34。所述第一电极层包括设置在所述电路结构层20上的多个第一电极31，每个第一电极31与一个所述像素驱动电路连接，所述像素界定层32设于所述多个第一电极31的远离所述衬底10一侧并设有多个像素开口，每个像素开口将对应的一个第一电极31的远离所述衬底10的表面暴露出，所述发光功能层33和所述第二电极层34依次叠设于所述多个第一电极31和所述像素界定层32的远离所述衬底10一侧，每个所述第一电极31、所述发光功能层33和所述第二电极层34依次叠设并形成一个发光器件301。示例性地，所述发光器件301可以是 OLED器件，每个发光器件301可以为串联式发光器件，并可以设置为发射白光。
在一些示例性实施例中，所述封装结构层可以包括叠设的多个无机材料层，比如可以包括沿远离所述衬底方向依次叠设的第一无机材料层和第二无机材料层。第一无机材料层和第二无机材料层的材料可以包括氮化硅、氧化硅和氮氧化硅中的任一种或多种。在其他实施方式中，所述封装结构层还可以包括设于第一无机材料层和第二无机材料层之间的有机材料层。
在一些示例性实施例中，所述显示基板还可以包括设于所述封装结构层的远离所述衬底一侧的彩色滤光层。所述彩色滤光层包括多个可以透射设定颜色光的滤光单元，比如，包括透射红光的红色滤光单元、透射绿光的绿色滤光单元和透射蓝光的蓝色滤光单元。每个发光器件发射的白光透过对应的一个滤光单元后出射相应颜色的光。
在一些示例性实施例中，如图3所示，所述绑定区300的电路结构层20包括绑定电极311，以及设于所述绑定电极311的远离所述衬底10一侧的复合绝缘层，所述复合绝缘层设有暴露出所述绑定电极311的远离所述衬底10的表面的凹槽，所述凹槽内设有填充层314，所述填充层314的表面与所述凹槽周围的复合绝缘层的背离所述衬底10的表面平齐设置；所述焊盘310包括所述绑定电极311和所述填充层314，所述焊盘310的表面为所述填充层314的表面。
在一些示例性实施例中，如图3所示，所述显示区100的电路结构层20包括沿远离所述衬底10方向依次设置的多个导电层；所述绑定电极311与所述多个导电层中的一个同层设置，所述填充层314不与所述多个导电层中的膜层同层设置。本实施例中，可以在形成显示区100的电路结构层20，以及绑定区300的绑定电极311和位于绑定电极311的远离衬底10一侧的复合绝缘层后，且在制备所述第一电极31之前，向复合绝缘层的所述凹槽内填充导电材料并将所述凹槽填平，所述凹槽内填充的导电材料即为填充层314。
在本文描述中，“A和B同层设置”是指，A和B通过同一次图案化工艺同时形成。
在一些示例性实施例中，所述显示区的电路结构层包括沿远离所述衬底 方向依次设置的多个导电层；所述焊盘包括绑定电极和设于所述绑定电极的远离所述衬底一侧的至少一个连接层，靠近所述绑定电极的一个所述连接层与所述绑定电极之间，以及相邻两个所述连接层之间均通过导电柱连接；所述绑定电极和任一个所述连接层均与所述多个导电层中的膜层同层设置。
本实施例的一个示例中，如图4所示，图4为在另一些示例性实施例中图1的显示基板的A-A剖面结构示意图，图4示意了三个子像素(分别为P1、P2和P3)，每个子像素包括像素驱动电路和与所述像素驱动电路连接的发光器件301，所述像素驱动电路包括多个晶体管210和存储电容，图4的每个子像素中示意了一个晶体管210。示例性地，所述显示区100的电路结构层20可以包括沿远离所述衬底10方向依次设置的第一绝缘层21、第一导电层201、第二绝缘层22、第二导电层202、第三绝缘层23、第三导电层203、第四绝缘层24、第四导电层204和第五绝缘层25；第一导电层201可以包括每个子像素的晶体管210的栅电极2011，以及一些信号线(比如扫描信号线)，第二导电层202可以包括每个子像素的晶体管210的源电极2021和漏电极2022，以及数据信号线等，第三导电层203可以包括电源线(VDD)等，第四导电层204可以包括一些其他信号线，以及与其他导电层连接的连接电极等。示例性地，所述焊盘310包括可以绑定电极311和设于所述绑定电极311的远离所述衬底10一侧的第一连接层3121和第二连接层3122，所述第一连接层3121与所述绑定电极311之间通过第一导电柱3131连接，第一连接层3121和第二连接层3122之间通过第二导电柱3132连接；所述第二连接层3122的表面为所述焊盘310的表面并与所述焊盘310周围的电路结构层20的背离所述衬底10的表面平齐设置。所述绑定电极311可以与所述第二导电层202同层设置，所述第一连接层3121可以与所述第三导电层203同层设置，所述第二连接层3122可以与所述第四导电层204同层设置。示例性地，所述绑定区300的电路结构层20可以包括依次叠设于衬底10上的第一绝缘层21和第二绝缘层22、设于第二绝缘层22上的绑定电极311、覆盖绑定电极311的第三绝缘层23、设于第三绝缘层23上的第一连接层3121、覆盖第一连接层3121的第四绝缘层24，以及设于第四绝缘层24上的第二连接层3122和第五绝缘层25；其中，第二连接层3122的表面与第五绝缘层25的背离所述衬底10的表面平齐设置，所述第三绝缘层23设有第三过孔，所 述第一连接层3121与所述绑定电极311之间通过设于所述第三过孔内的第一导电柱3131连接，所述第四绝缘层24设有第四过孔，第一连接层3121和第二连接层3122之间通过设于所述第四过孔内的第二导电柱3132连接，第一导电柱3131和第二导电柱3132的材料可以均包括钨。本示例中，绑定区300的绝缘层的层数和显示区100的绝缘层的层数相同，均为五层。绑定区300的第五绝缘层25的厚度小于显示区100的第五绝缘层25的厚度。
图4的示例中，所述显示区100的电路结构层20设有四个导电层，所述焊盘310的设于绑定电极311的远离衬底10一侧的连接层包括第一连接层3121和第二连接层3122两个膜层。在其他实施方式中，所述显示区的电路结构层可以设有三个、五个或五个以上的导电层，导电层的膜层个数可以根据像素驱动电路的结构以及信号线的布线方式进行设置，所述焊盘中所述连接层的膜层个数可以是一个、三个或三个以上。本公开对所述显示区的电路结构层的导电层的膜层个数，以及所述焊盘中所述连接层的膜层个数不做限定。
本实施例的另一个示例中，如图5所示，图5为在又一些示例性实施例中图1的显示基板的A-A剖面结构示意图，图5示意了三个子像素，每个子像素包括像素驱动电路和与所述像素驱动电路连接的发光器件301，所述像素驱动电路包括多个晶体管210和存储电容，图5的每个子像素中示意了一个晶体管210。示例性地，所述显示区100的电路结构层20可以包括沿远离所述衬底10方向依次设置的第一绝缘层21、第一导电层201、第二绝缘层22、第二导电层202、第三绝缘层23、第三导电层203、第四绝缘层24、第四导电层204、第五绝缘层25、第五导电层205和第六绝缘层26；第一导电层201可以包括每个子像素的晶体管210的栅电极2011，第二导电层202可以包括每个子像素的晶体管210的源电极2021和漏电极2022，以及一些信号线(比如扫描信号线)，第三导电层203可以包括数据信号线等，第四导电层204可以包括电源线(VDD)等，第五导电层205可以包括与其他导电层连接的连接电极等。示例性地，所述焊盘310可以包括绑定电极311和设于所述绑定电极311的远离所述衬底10一侧的连接层312，所述连接层312与所述绑定电极311之间通过导电柱313连接；所述连接层312的表面为所 述焊盘310的表面并与所述焊盘310周围的电路结构层20的背离所述衬底10的表面平齐设置。所述绑定电极311可以与所述第二导电层202同层设置，所述连接层312可以与所述第三导电层203同层设置。示例性地，所述绑定区300的电路结构层20可以包括依次叠设于衬底10上的第一绝缘层21和第二绝缘层22、设于第二绝缘层22上的绑定电极311、覆盖绑定电极311的第三绝缘层23，以及设于第三绝缘层23上的连接层312和第四绝缘层24；其中，连接层312的表面与第四绝缘层24的背离所述衬底10的表面平齐设置，所述第三绝缘层23设有第三过孔，所述连接层312与所述绑定电极311之间通过设于所述第三过孔内的导电柱313连接，导电柱313的材料可以包括钨。本示例中，显示区100的绝缘层的层数为六层，绑定区300的绝缘层的层数为四层，绑定区300的绝缘层的层数小于显示区100的绝缘层的层数。绑定区300的第四绝缘层24的厚度小于显示区100的第四绝缘层24的厚度。
图5的示例中，所述显示区100的电路结构层20设有五个导电层，所述焊盘310的设于绑定电极311的远离衬底10一侧的连接层的膜层个数为一个。在其他实施方式中，所述显示区的电路结构层可以设有三个、四个或五个以上的导电层，导电层的膜层个数可以根据像素驱动电路的结构以及信号线的布线方式进行设置，所述焊盘中所述连接层的膜层个数可以是二个、三个或三个以上。本公开对所述显示区的电路结构层的导电层的膜层个数，以及所述焊盘中所述连接层的膜层个数不做限定。
本实施例的一个示例中，如图4、图5所示，所述多个导电层包括沿远离所述衬底10方向依次设置的第一导电层201和第二导电层202，以及设置在所述第二导电层202的远离所述衬底10一侧的至少一个导电层；所述第一导电层201可以包括所述晶体管210的栅电极2011，所述第二导电层202可以包括所述晶体管210的源电极2021和漏电极2022；所述绑定电极311可以与所述第二导电层202同层设置。在其他实施方式中，可以根据所述显示区100的电路结构层20内像素驱动电路的结构以及信号线的布线方式，将所述绑定电极311与其他导电层同层设置。
在一些示例性实施例中，所述绑定区的电路结构层的绝缘层的层数可以小于或等于所述显示区的电路结构层的绝缘层的层数。示例性地，在图4的 示例中，绑定区300的电路结构层20的绝缘层的层数和显示区100的电路结构层20的绝缘层的层数相同，均为五层。在图5的示例中，显示区100的电路结构层20的绝缘层的层数为六层，绑定区300的电路结构层20的绝缘层的层数为四层，绑定区300的电路结构层20的绝缘层的层数小于显示区100的电路结构层20的绝缘层的层数。在其他实施方式中，根据像素驱动电路的结构以及信号线的布线方式的不同，显示区的电路结构层的导电层的层数可以是其他层数，相应地，显示区的电路结构层的绝缘层的层数可以是其他层数；绑定区的电路结构层的绝缘层的层数可以根据所述焊盘的结构以及所述焊盘中所述连接层的膜层个数进行设置。本公开对显示区的电路结构层的导电层的层数和绝缘层的层数不做限定，对绑定区的电路结构层的绝缘层的层数不做限定。
本公开实施例还提供一种显示基板的制备方法，所述显示基板包括显示区和位于所述显示区一侧的绑定区；所述制备方法包括：
在衬底上形成电路结构层；所述显示区的电路结构层内设有像素驱动电路，所述像素驱动电路包括多个晶体管，所述绑定区的电路结构层内设有焊盘，所述焊盘配置为与外部的电路板绑定连接，所述焊盘的表面与所述焊盘周围的电路结构层的背离所述衬底的表面平齐设置。
在一些示例性实施例中，所述显示区的电路结构层包括沿远离所述衬底方向依次设置的多个导电层；所述焊盘包括绑定电极和设于所述绑定电极的远离所述衬底一侧的至少一个连接层，靠近所述绑定电极的一个所述连接层与所述绑定电极之间，以及相邻两个所述连接层之间均通过导电柱连接；所述绑定电极和任一个所述连接层均与所述多个导电层中的膜层同层设置。
下面对本公开显示基板的制备过程进行示例性说明。本公开所说的“图案化工艺”包括涂覆光刻胶、掩模曝光、显影、刻蚀和剥离光刻胶处理。沉积可以采用溅射、蒸镀和化学气相沉积中的任意一种或多种，涂覆可以采用喷涂和旋涂中的任意一种或多种，刻蚀可以采用干刻和湿刻中的任意一种或多种。“薄膜”是指将某一种材料在基底上利用沉积或涂覆工艺制作出的一层薄膜。若在整个制作过程中该“薄膜”无需图案化工艺，则该“薄膜”还可以称为“层”。若在整个制作过程中该“薄膜”需图案化工艺，则在图案化工艺前称为“薄膜”， 图案化工艺后称为“层”。经过图案化工艺后的“层”中包含至少一个“图案”。本公开中所说的“A和B同层设置”是指，A和B通过同一次图案化工艺同时形成。本公开中所说的“A的正投影包含B的正投影”是指，B的正投影落入A的正投影范围内，或者A的正投影覆盖B的正投影。
以图4示例的显示基板的结构为例，说明本公开实施例的显示基板的制备过程，图4示例的显示基板为硅基OLED显示基板为例，所述制备过程可以包括如下步骤：
(1)形成硅基衬底。在示例性实施方式中，硅基OLED显示基板中，所述像素驱动电路可以包括多个晶体管和存储电容，多个晶体管可以包括至少一个P型晶体管和至少一个N型晶体管。形成硅基衬底可以包括：提供硅基衬底，比如单晶硅衬底；在单晶硅衬底上形成多个N型阱区和多个P型阱区，所述N型阱区可以作为像素驱动电路中的P型晶体管的有源层，所述P型阱区可以作为像素驱动电路中的N型晶体管的有源层。
(2)形成第一绝缘层21和第一导电层201图案。在示例性实施方式中，形成第一绝缘层21和第一导电层201图案可以包括：在硅基衬底10上依次沉积第一绝缘薄膜和多晶硅薄膜，先通过图案化工艺对多晶硅薄膜进行图案化处理，形成覆盖硅基衬底10的第一绝缘层21以及设置在第一绝缘层21上的多晶硅层图案；以多晶硅层图案为遮挡层，对所述N型阱区的两个区域进行P型掺杂，以形成P型晶体管的有源层的第一区和第二区，对所述P型阱区的两个区域进行N型掺杂，以形成N型晶体管的有源层的第一区和第二区；可以对所述多晶硅层图案进行重掺杂，使电阻较高的多晶硅层变成电阻较低的第一导电层201，第一导电层201可以包括P型晶体管和N型晶体管的栅电极2011，以及扫描信号线；栅电极2011与晶体管210的有源层相重叠的区域作为有源层的沟道区。如图6a所示。
(3)形成第二绝缘层22和第二导电层202图案。在示例性实施方式中，形成第二绝缘层22和第二导电层202图案可以包括：在形成前述图案的硅基衬底10上沉积第二绝缘薄膜，通过图案化工艺对第二绝缘薄膜进行图案化处理，形成覆盖第一导电层201图案的第二绝缘层22。第二绝缘层22设置有多个过孔，多个过孔可以包括第一过孔和第二过孔，第一过孔和第二过孔内 的第一绝缘层21和第二绝缘层22被刻蚀掉，第一过孔将有源层的第一区暴露出，第二过孔将有源层的第二区暴露出。然后，在第二绝缘层22上沉积第二导电薄膜，通过图案化工艺对第二导电薄膜进行图案化处理，在第二绝缘层22上形成第二导电层202图案。第二导电层202图案包括位于显示区100的源电极2021、漏电极2022和数据信号线，以及位于绑定区300的绑定电极311；源电极2021通过第二绝缘层22的第一过孔与有源层的第一区连接，漏电极2022通过第二绝缘层22的第二过孔与有源层的第二区连接。如图6a所示。
(4)形成第三绝缘层23。在示例性实施方式中，形成第三绝缘层23可以包括：在形成前述图案的硅基衬底10上沉积第三绝缘薄膜，通过图案化工艺对第三绝缘薄膜进行图案化处理，形成覆盖第二导电层202图案的第三绝缘层23。第三绝缘层23设置有位于显示区100的多个过孔和位于绑定区300的第三过孔231，显示区100的过孔可以配置为将后续形成的第三导电层203与第二导电层202连接，绑定区300的第三过孔231将所述绑定电极311的表面的一部分暴露出。如图6a所示。
(5)形成第一导电柱3131。在示例性实施方式中，向第三绝缘层23设置的过孔内填充金属导电材料(比如可以是钨金属材料，由钨金属填充的过孔可称为钨孔)；填充在第三绝缘层23的过孔内的金属导电材料可以称为导电柱，位于第三过孔231内的金属导电材料为第一导电柱3131，第一导电柱3131配置为将后续形成的第一连接层3121与绑定电极311连接，第三绝缘层23的位于显示区100的多个过孔内的导电柱可以配置为将后续形成的第三导电层203与第二导电层202连接。如图6b所示。
(6)形成第三导电层203和第四绝缘层24。在示例性实施方式中，形成第三导电层203和第四绝缘层24可以包括：在形成前述图案的硅基衬底10上沉积第三导电薄膜，通过图案化工艺对第三导电薄膜进行图案化处理，在第三绝缘层23上形成第三导电层203图案。第三导电层203图案可以包括位于显示区100的电源线等，以及位于绑定区300的第一连接层3121，第一连接层3121通过第一导电柱3131与绑定电极311连接。随后，在形成前述图案的硅基衬底10上沉积第四绝缘薄膜，通过图案化工艺对第四绝缘薄膜进 行图案化处理，形成覆盖第三导电层203图案的第四绝缘层24。第四绝缘层24设置有位于显示区100的多个过孔和位于绑定区300的第四过孔241，显示区100的过孔可以配置为将后续形成的第四导电层204与第三导电层203连接，绑定区300的第四过孔241将所述第一连接层3121的表面的一部分暴露出。如图6c所示。
(7)形成第二导电柱3132。在示例性实施方式中，向第四绝缘层24设置的过孔内填充金属导电材料(比如可以是钨金属材料，由钨金属填充的过孔可称为钨孔)；填充在第四绝缘层24的过孔内的金属导电材料可以称为导电柱，位于第四过孔241内的金属导电材料为第二导电柱3132，第二导电柱3132配置为将后续形成的第二连接层3122与第一连接层3121连接，第四绝缘层24的位于显示区100的多个过孔内的导电柱可以配置为将后续形成的第四导电层204与第三导电层203连接。如图6d所示。
(8)形成第四导电层204和第五绝缘层25。在示例性实施方式中，形成第四导电层204可以包括：在形成前述图案的硅基衬底10上沉积第四导电薄膜，通过图案化工艺对第四导电薄膜进行图案化处理，在第四绝缘层24上形成第四导电层204图案。第四导电层204图案可以包括位于显示区100的一些信号线和与其他导电层连接的连接电极，以及位于绑定区300的第二连接层3122；第二连接层3122通过第二导电柱3132与第一连接层3121连接。
随后，在形成前述图案的硅基衬底10上形成第五绝缘层25。一些示例中，形成第五绝缘层25可以包括：在形成前述图案的硅基衬底10上沉积第五绝缘薄膜，通过图案化工艺对第五绝缘薄膜进行图案化处理，形成覆盖第四导电层204图案的第五绝缘层25。其中，对第五绝缘薄膜进行图案化处理可以包括：对绑定区300的第五绝缘薄膜的背离衬底10的表面进行减薄处理，以及在显示区100的第五绝缘薄膜上形成多个过孔，从而形成第五绝缘层25。绑定区300的第五绝缘层25的背离衬底10的表面与第二连接层3122的表面平齐，显示区100的第五绝缘层25设置的多个过孔可以配置为将后续形成的发光器件301的第一电极31与第四导电层204连接。在另一些示例中，形成第五绝缘层25可以包括：在形成前述图案的硅基衬底10上沉积第一子绝缘 薄膜，第一子绝缘薄膜的表面与第二连接层3122的表面平齐设置；随后，在显示区100沉积第二子绝缘薄膜；通过图案化工艺对显示区100的第二子绝缘薄膜和第一子绝缘薄膜进行图案化处理，形成第五绝缘层25。其中，显示区100的第五绝缘层25包括叠设的第一子绝缘层和第二子绝缘层，并覆盖显示区100的第四导电层204，显示区100的第五绝缘层25设置有多个过孔，多个过孔可以配置为将后续形成的发光器件301的第一电极31与第四导电层204连接。绑定区300的第五绝缘层25包括第一子绝缘层且不包括第二子绝缘层，绑定区300的第五绝缘层25的背离衬底10的表面与第二连接层3122的表面平齐。如图6e所示。
至此，完成电路结构层20的制备。所述绑定电极311、第一导电柱3131、第一连接层3121、第二导电柱3132和第二连接层3122组成所述焊盘310，第二连接层3122的表面为所述焊盘310的表面，所述焊盘310的表面与所述焊盘310周围的电路结构层20的背离衬底10的表面平齐设置。
(9)形成发光结构层30。在示例性实施方式中，形成发光结构层30可以包括：在形成前述图案的硅基衬底10上沉积第一电极薄膜，通过图案化工艺对第一电极薄膜进行图案化处理，形成第一电极层，第一电极层包括位于显示区100的多个第一电极31，每个第一电极31通过第五绝缘层25上的过孔与第四导电层204连接，实现与像素驱动电路的连接。之后，在形成前述图案的硅基衬底10上形成像素界定薄膜，通过图案化工艺对像素界定薄膜进行图案化处理，形成像素界定层32，像素界定层32设有多个像素开口，每个像素开口将对应的一个第一电极31的远离所述衬底10的表面暴露出。之后，在形成前述图案的硅基衬底10上依次形成发光功能层33和第二电极层34。每个所述第一电极31、所述发光功能层33和所述第二电极层34依次叠设并形成一个发光器件301。如图4所示。
(10)形成封装结构层40。在示例性实施方式中，形成封装结构层40可以包括：在形成前述图案的硅基衬底10上依次沉积第一无机材料薄膜和第二无机材料薄膜，通过图案化工艺对第一无机材料薄膜和第二无机材料薄膜进行图案化处理，形成包括第一无机材料层和第二无机材料层的封装结构层40，封装结构层40将显示区100覆盖并将绑定区300暴露出。
本公开实施例还提供另一种显示基板的制备方法，所述显示基板包括显示区和位于所述显示区一侧的绑定区；所述制备方法包括：
在衬底上形成电路结构层；所述显示区的电路结构层内设有像素驱动电路，所述像素驱动电路包括多个晶体管，所述绑定区的电路结构层包括绑定电极，以及设于所述绑定电极的远离所述衬底一侧的复合绝缘层，所述复合绝缘层设有暴露出所述绑定电极的远离所述衬底的表面的凹槽；
在所述凹槽内形成填充层，所述填充层的表面与所述凹槽周围的复合绝缘层的背离所述衬底的表面平齐设置；所述绑定电极和所述填充层组成焊盘，所述焊盘配置为与外部的电路板绑定连接；
在所述显示区的电路结构层上形成发光结构层；所述发光结构层包括与所述像素驱动电路连接的发光器件。
在一些示例性实施例中，所述显示区的电路结构层包括沿远离所述衬底方向依次设置的多个导电层，所述绑定电极与所述多个导电层中的一个同层设置，所述填充层不与所述多个导电层中的膜层同层设置。
以图3示例的显示基板的结构为例，说明本公开实施例的另一种显示基板的制备过程，图3示例的显示基板为硅基OLED显示基板为例，所述制备过程可以包括如下步骤：
(1)在衬底10上形成电路结构层20。在示例性实施方式中，在衬底10上形成电路结构层20可以包括：形成硅基衬底10，并依次在硅基衬底10上形成多个导电层。
制备完电路结构层20后，显示区100的电路结构层20包括像素驱动电路，以及扫描信号线、数据信号线、电源线等信号线，所述像素驱动电路包括多个晶体管210；绑定区300的电路结构层20包括绑定电极311，以及设于所述绑定电极311的远离所述衬底一侧的复合绝缘层，所述复合绝缘层设有暴露出所述绑定电极311的远离所述衬底的表面的凹槽320。其中，所述绑定电极311与所述多个导电层中的一个同层设置。如图7a所示。
(2)在所述凹槽320内形成填充层314，所述填充层314的表面与所述凹槽320周围的复合绝缘层的背离所述衬底10的表面平齐设置。所述填充层 314设置在所述绑定电极311的表面上，所述绑定电极311和所述填充层314组成焊盘310，所述焊盘310配置为与外部的电路板绑定连接。其中，所述填充层314的材料可以为金属导电材料，比如铝。如图7b所示。
(3)在所述显示区100的电路结构层20上依次形成发光结构层30和封装结构层40。所述发光结构层30包括与所述像素驱动电路连接的发光器件301，所述发光器件301包括沿远离衬底10方向依次叠设的第一电极31、发光功能层33和第二电极层34。如图3所示。
本公开实施例的显示基板的制备方法，在制备发光器件301的第一电极31之前，将焊盘310的表面与焊盘310周围的电路结构层20的背离衬底10的表面平齐设置，如此，焊盘310所在位置没有形成凹坑，这样在制备发光器件301的第一电极31过程中，其中在显影过程中，不会在焊盘310所在位置有光阻残留物存在，从而可以避免由于焊盘310凹坑内的光阻残留物导致的显示基板在显示画面时产生的斜纹mura问题，提高产品良率。
本公开实施例还提供一种显示装置，包括前文任一实施例所述的显示基板。显示装置可以为近眼显示装置，比如VR眼镜、头盔显示器等；或者，显示装置可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
在附图中，有时为了明确起见，夸大表示了构成要素的大小、层的厚度或区域。因此，本公开的实施方式并不一定限定于该尺寸，附图中每个部件的形状和大小不反映真实比例。此外，附图示意性地示出了一些例子，本公开的实施方式不局限于附图所示的形状或数值。
在本说明书中，晶体管是指至少包括栅电极、漏电极以及源电极这三个端子的元件。晶体管在漏电极(漏电极端子、漏区域或漏电极)与源电极(源电极端子、源区域或源电极)之间具有沟道区域，并且电流能够流过漏电极、沟道区域以及源电极。在本说明书中，沟道区域是指电流主要流过的区域。
在本说明书中，为了区分晶体管除控制极之外的两极，直接描述了其中一极为第一极，另一极为第二极，其中，第一极可以为漏电极、第二极可以为源电极，或者第一极可以为源电极、第二极可以为漏电极。在使用极性相 反的晶体管的情况或电路工作中的电流方向变化的情况等下，“源电极”及“漏电极”的功能有时互相调换。因此，在本说明书中，“源电极”和“漏电极”可以互相调换。
在本文描述中，“平行”是指两条直线形成的角度为-10°以上且10°以下的状态，因此，包括该角度为-5°以上且5°以下的状态。另外，“垂直”是指两条直线形成的角度为80°以上且100°以下的状态，因此，包括85°以上且95°以下的角度的状态。
在本说明书中，为了方便起见，使用“中部”、“上”、“下”、“前”、“后”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示方位或位置关系的词句以参照附图说明构成要素的位置关系，仅是为了便于描述本说明书和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。构成要素的位置关系根据描述各构成要素的方向适当地改变。因此，不局限于在说明书中说明的词句，根据情况可以适当地更换。
在本文描述中，除非另有明确的规定和限定，术语“连接”、“固定连接”、“安装”、“装配”应做广义理解，例如，可以是固定连接，或是可拆卸连接，或一体地连接；术语“安装”、“连接”、“固定连接”可以是直接相连，或通过中间媒介间接相连，或是两个元件内部的连通。对于本领域的普通技术人员而言，可以根据情况理解上述术语在本公开实施例中的含义。

Claims (12)

  1. 一种显示基板，所述显示基板包括显示区和位于所述显示区一侧的绑定区；所述显示基板包括衬底和设于所述衬底上的电路结构层；所述显示区的电路结构层内设有像素驱动电路，所述像素驱动电路包括多个晶体管，所述显示区还包括依次叠设于电路结构层的远离所述衬底一侧的发光结构层和封装结构层，所述发光结构层包括与所述像素驱动电路连接的发光器件；所述绑定区的电路结构层内设有焊盘，所述焊盘配置为与外部的电路板绑定连接，所述焊盘的表面与所述焊盘周围的电路结构层的背离所述衬底的表面平齐设置。
  2. 如权利要求1所述的显示基板，其中，所述显示区的电路结构层包括沿远离所述衬底方向依次设置的多个导电层；
    所述焊盘包括绑定电极和设于所述绑定电极的远离所述衬底一侧的至少一个连接层，靠近所述绑定电极的一个所述连接层与所述绑定电极之间，以及相邻两个所述连接层之间均通过导电柱连接；
    所述绑定电极和任一个所述连接层均与所述多个导电层中的膜层同层设置。
  3. 如权利要求1所述的显示基板，其中，所述绑定区的电路结构层包括绑定电极，以及设于所述绑定电极的远离所述衬底一侧的复合绝缘层，所述复合绝缘层设有暴露出所述绑定电极的远离所述衬底的表面的凹槽，所述凹槽内设有填充层，所述填充层的表面与所述凹槽周围的复合绝缘层的背离所述衬底的表面平齐设置；所述焊盘包括所述绑定电极和所述填充层，所述焊盘的表面为所述填充层的表面。
  4. 如权利要求3所述的显示基板，其中，所述显示区的电路结构层包括沿远离所述衬底方向依次设置的多个导电层；
    所述绑定电极与所述多个导电层中的一个同层设置，所述填充层不与所述多个导电层中的膜层同层设置。
  5. 如权利要求2或4所述的显示基板，其中，所述多个导电层包括沿远离所述衬底方向依次设置的第一导电层和第二导电层，以及设置在所述第二 导电层的远离所述衬底一侧的至少一个导电层；
    所述第一导电层包括所述晶体管的栅电极，所述第二导电层包括所述晶体管的源电极和漏电极；所述绑定电极与所述第二导电层同层设置。
  6. 如权利要求2或3所述的显示基板，其中，所述绑定区的电路结构层的绝缘层的层数小于或等于所述显示区的电路结构层的绝缘层的层数。
  7. 如权利要求2所述的显示基板，其中，所述导电柱的材料包括钨。
  8. 一种显示装置，包括权利要求1至7任一项所述的显示基板。
  9. 一种显示基板的制备方法，所述显示基板包括显示区和位于所述显示区一侧的绑定区；所述制备方法包括：
    在衬底上形成电路结构层；所述显示区的电路结构层内设有像素驱动电路，所述像素驱动电路包括多个晶体管，所述绑定区的电路结构层包括绑定电极，以及设于所述绑定电极的远离所述衬底一侧的复合绝缘层，所述复合绝缘层设有暴露出所述绑定电极的远离所述衬底的表面的凹槽；
    在所述凹槽内形成填充层，所述填充层的表面与所述凹槽周围的复合绝缘层的背离所述衬底的表面平齐设置；所述绑定电极和所述填充层组成焊盘，所述焊盘配置为与外部的电路板绑定连接；
    在所述显示区的电路结构层上形成发光结构层；所述发光结构层包括与所述像素驱动电路连接的发光器件。
  10. 如权利要求9所述的显示基板的制备方法，其中，所述显示区的电路结构层包括沿远离所述衬底方向依次设置的多个导电层，所述绑定电极与所述多个导电层中的一个同层设置，所述填充层不与所述多个导电层中的膜层同层设置。
  11. 一种显示基板的制备方法，所述显示基板包括显示区和位于所述显示区一侧的绑定区；所述制备方法包括：
    在衬底上形成电路结构层；所述显示区的电路结构层内设有像素驱动电路，所述像素驱动电路包括多个晶体管，所述绑定区的电路结构层内设有焊盘，所述焊盘配置为与外部的电路板绑定连接，所述焊盘的表面与所述焊盘周围的电路结构层的背离所述衬底的表面平齐设置。
  12. 如权利要求11所述的显示基板的制备方法，其中，所述显示区的电路结构层包括沿远离所述衬底方向依次设置的多个导电层；
    所述焊盘包括绑定电极和设于所述绑定电极的远离所述衬底一侧的至少一个连接层，靠近所述绑定电极的一个所述连接层与所述绑定电极之间，以及相邻两个所述连接层之间均通过导电柱连接；
    所述绑定电极和任一个所述连接层均与所述多个导电层中的膜层同层设置。
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JP2010244850A (ja) * 2009-04-06 2010-10-28 Toshiba Mobile Display Co Ltd 有機ｅｌ表示装置
CN110491904A (zh) * 2018-05-14 2019-11-22 三星显示有限公司 显示设备
CN110931540A (zh) * 2019-12-20 2020-03-27 京东方科技集团股份有限公司 镜面显示面板及其制作方法、镜面显示装置
CN110931523A (zh) * 2018-09-18 2020-03-27 三星显示有限公司 显示装置
CN111880344A (zh) * 2020-07-30 2020-11-03 厦门天马微电子有限公司 一种显示面板及其制备方法、显示装置
CN212135113U (zh) * 2020-05-15 2020-12-11 京东方科技集团股份有限公司 阵列基板、液晶显示面板及显示装置

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010244850A (ja) * 2009-04-06 2010-10-28 Toshiba Mobile Display Co Ltd 有機ｅｌ表示装置
CN110491904A (zh) * 2018-05-14 2019-11-22 三星显示有限公司 显示设备
CN110931523A (zh) * 2018-09-18 2020-03-27 三星显示有限公司 显示装置
CN110931540A (zh) * 2019-12-20 2020-03-27 京东方科技集团股份有限公司 镜面显示面板及其制作方法、镜面显示装置
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