WO2020192585A1 - 阵列基板及其制备方法、显示面板和显示装置和像素驱动电路 - Google Patents

阵列基板及其制备方法、显示面板和显示装置和像素驱动电路 Download PDF

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Publication number
WO2020192585A1
WO2020192585A1 PCT/CN2020/080429 CN2020080429W WO2020192585A1 WO 2020192585 A1 WO2020192585 A1 WO 2020192585A1 CN 2020080429 W CN2020080429 W CN 2020080429W WO 2020192585 A1 WO2020192585 A1 WO 2020192585A1
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Prior art keywords
base substrate
wiring
orthographic projection
layer
effective light
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PCT/CN2020/080429
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English (en)
French (fr)
Inventor
李孟
杜森
承天一
张跳梅
黄耀
刘庭良
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US17/040,587 priority Critical patent/US11563073B2/en
Publication of WO2020192585A1 publication Critical patent/WO2020192585A1/zh
Priority to US18/083,969 priority patent/US11903281B2/en
Priority to US18/502,168 priority patent/US20240074263A1/en

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/124—Insulating layers formed between TFT elements and OLED elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3258—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the voltage across the light-emitting element
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0251—Precharge or discharge of pixel before applying new pixel voltage
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K2102/00—Constructional details relating to the organic devices covered by this subclass
    • H10K2102/301—Details of OLEDs
    • H10K2102/351—Thickness

Definitions

  • the present disclosure relates to the field of display technology, and in particular to an array substrate and a preparation method thereof, a display panel, a display device and a pixel driving circuit.
  • OLED Organic Light Emitting Diode
  • AMOLED Active Matrix Organic Light Emitting Diode
  • TFTLCD Thin Film Transistor Liquid Crystal Display
  • Some embodiments of the present disclosure provide an array substrate, including: a base substrate; and a wiring layer and an effective light emitting layer that are sequentially stacked and formed on the base substrate, wherein the wiring layer includes a first wiring and The second wiring, the orthographic projection of the first wiring on the base substrate and the orthographic projection of the effective light-emitting layer on the base substrate have a first overlapping area, and the second wiring is in the The orthographic projection on the base substrate and the orthographic projection of the effective light-emitting layer on the base substrate have a second overlapping area, and the first overlapping area and the second overlapping area are respectively located in the effective light-emitting area.
  • the layers are on both sides of the center line of the orthographic projection on the base substrate.
  • the distance between the surface of the first trace facing away from the base substrate and the base substrate is equal to the distance between the surface of the second trace facing away from the base substrate and the The distance between the base substrate.
  • the orthographic projection of the effective light-emitting layer on the base substrate is an axisymmetric pattern
  • the center line of the orthographic projection of the effective light-emitting layer on the base substrate is the axis of the axisymmetric pattern. Symmetry axis.
  • the first overlapping area and the second overlapping area are symmetrically arranged with respect to the center line of the orthographic projection of the effective light-emitting layer on the base substrate.
  • the first overlapping area and the second overlapping area are both parallel to the center line of the orthographic projection of the effective light-emitting layer on the base substrate.
  • the wiring layer further includes a signal line, wherein the center line of the orthographic projection of the signal line on the base substrate is collinear with the center line of the orthographic projection of the effective light-emitting layer on the base substrate.
  • the first trace, the second trace, and the signal line are arranged with the same material and the same layer, and the thickness of the first trace, the second trace, and the signal line are the same.
  • the first trace is a power high-voltage trace
  • the signal line is a data signal line
  • the array substrate further includes: a flat layer disposed between the wiring layer and the effective light-emitting layer, wherein the flat layer includes a first part and a second part, and the first part is on the substrate.
  • the orthographic projection on the substrate coincides with the first overlapping area
  • the orthographic projection of the second part on the base substrate coincides with the second overlapping area
  • the first part faces away from the base substrate.
  • the distance between the surface and the base substrate is equal to the distance between the surface of the second portion facing away from the base substrate and the base substrate.
  • the array substrate further includes: a first electrode disposed between the flat layer and the effective light-emitting layer, wherein the first electrode includes a third part and a fourth part, and the third The orthographic projection of a part on the base substrate coincides with the first overlap area, the orthographic projection of the fourth part on the base substrate coincides with the second overlap area, and the third part faces away from the The distance between the surface of the base substrate and the base substrate is equal to the distance between the surface of the fourth part facing away from the base substrate and the base substrate, and the third part and the fourth part The thickness is the same.
  • the effective light-emitting layer includes a fifth part and a sixth part, the orthographic projection of the fifth part on the base substrate coincides with the first overlap area, and the sixth part is on the base substrate.
  • the orthographic projection coincides with the second overlapping area, and the distance between the surface of the fifth part facing away from the base substrate and the base substrate is equal to the distance between the sixth part facing away from the base substrate. The distance between the surface and the base substrate, and the fifth part and the sixth part have the same thickness.
  • the fifth part and the sixth part are respectively located at two opposite edge regions of the effective light-emitting layer.
  • the second trace is connected to an initialization voltage signal.
  • the array substrate further includes: an interlayer dielectric layer disposed between the base substrate and the wiring layer; the first wiring and the second wiring form The surface of the interlayer dielectric layer facing away from the base substrate.
  • Some embodiments of the present disclosure provide a display panel including the array substrate as described in the foregoing embodiments.
  • Some embodiments of the present disclosure provide a display device including the display panel as described in the foregoing embodiments.
  • Some embodiments of the present disclosure provide a method for preparing an array substrate, including: providing a base substrate; forming a wiring layer on the base substrate, the wiring layer including a first wiring and a second wiring; An effective light-emitting layer is formed on a base substrate with a wiring layer, wherein the orthographic projection of the first wiring on the base substrate and the orthographic projection of the effective light-emitting layer on the base substrate have a first An overlap area, the orthographic projection of the second trace on the base substrate and the orthographic projection of the effective light-emitting layer on the base substrate have a second overlap area, the first overlap area and The second overlapping regions are respectively located on both sides of the center line of the orthographic projection of the effective light-emitting layer on the base substrate.
  • the preparation method before forming the effective light-emitting layer, further includes: forming a flat layer on the base substrate with the wiring layer, wherein the flat layer includes a first part and a second part, and the first part is on the liner.
  • the orthographic projection on the base substrate coincides with the first overlapping area
  • the orthographic projection of the second part on the base substrate coincides with the second overlapping area
  • the first part faces away from the base substrate
  • the distance between the surface of and the base substrate is equal to the distance between the surface of the second part facing away from the base substrate and the base substrate.
  • the preparation method before the effective light-emitting layer is formed, the preparation method further includes: forming a first electrode on the base substrate on which the flat layer is formed, wherein the first electrode includes a third part and a fourth part, and the third The orthographic projection of a part on the base substrate coincides with the first overlap area, the orthographic projection of the fourth part on the base substrate coincides with the second overlap area, and the third part faces away from the The distance between the surface of the base substrate and the base substrate is equal to the distance between the surface of the fourth part facing away from the base substrate and the base substrate, and the third part and the fourth part The thickness is the same.
  • Some embodiments of the present disclosure provide a pixel driving circuit applied to the array substrate described in the foregoing embodiments, including:
  • the source of the first thin film transistor is connected to the initialization signal, the gate is electrically connected to the reset signal, and the drain is electrically connected to the first node;
  • the gate of the second thin film transistor is connected to the scan signal, the source is electrically connected to the second node, and the drain is electrically connected to the first node;
  • the source of the third thin film transistor is electrically connected to the second node, the gate is electrically connected to the first node, and the drain is electrically connected to the third node;
  • the gate of the fourth thin film transistor is connected to the scan signal, the source is electrically connected to the data signal, and the drain is electrically connected to the third node;
  • the source of the fifth thin film transistor is connected to the first power voltage, the gate is connected to a light-emitting control signal, and the drain is electrically connected to the third node;
  • the source of the sixth thin film transistor is electrically connected to the second node, the gate is connected to a light emission control signal, and the drain is electrically connected to the fourth node;
  • a gate of the seventh thin film transistor is connected to a scan signal, a source is electrically connected to the access initialization signal, and a drain is electrically connected to the fourth node;
  • the first electrode of the organic light emitting diode is connected to the fourth node, and the second electrode is connected to a second power supply voltage;
  • Both ends of the capacitor are electrically connected to the first node and the first power supply voltage
  • the second wiring is suspended, or is connected to an initialization signal, or is electrically connected to the first node.
  • FIG. 1 is a schematic top view of a pixel area in an OLED array substrate in the related art
  • FIG. 2 is a cross-sectional view of the pixel area in the OLED array substrate in FIG. 1;
  • FIG. 3 is a schematic top view of a pixel area in an OLED array substrate according to some embodiments of the present disclosure
  • FIG. 4 is a cross-sectional view of a pixel area in the OLED array substrate in FIG. 3;
  • FIG. 5 is a flowchart of a manufacturing method of an OLED array substrate according to some embodiments of the present disclosure
  • FIG. 6 is a schematic diagram of a pixel driving circuit corresponding to a pixel area in an OLED array substrate according to an embodiment of the present disclosure.
  • first, second, etc. may be used herein to describe different elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another.
  • the first element may be named as the second element, and similarly, the second element may be named as the first element.
  • the term "and/or" as used herein includes any and all combinations of one or more of the related listed items.
  • the expression “thickness” refers to the layer or component in the direction perpendicular to the upper surface of the substrate (in the use state, the upper surface of the substrate is the surface facing the user) size.
  • the expression “located on the same layer” generally means that the first component and the second component can use the same material and can be formed by the same patterning process.
  • Traditional display technology uses a single display mode.
  • the brightness, contrast, color gamut and visual role of the liquid crystal display device The color difference of different viewing angles
  • the visual role deviation requirements are higher, and the visual role of the ordinary display panel is required. Partially improve.
  • the OLED display screen mainly realizes image display by driving the electroluminescent device to emit light by current.
  • the brightness and contrast of the display screen will also change, resulting in color shift. Therefore, how to improve the color shift of the OLED display area and improve the display effect of the display panel is a problem to be solved urgently.
  • the array substrate is an OLED array substrate for explanation.
  • the OLED array substrate includes a plurality of pixel areas arranged in an array, each pixel area is provided with an OLED device, and each OLED device includes a second array which is arranged away from the substrate in turn.
  • the first electrode is, for example, an anode
  • the effective light-emitting layer is, for example, a red organic effective light-emitting layer, a green organic effective light-emitting layer or a blue organic effective light-emitting layer
  • the second electrode is, for example, a cathode.
  • the array substrate in the present disclosure may also be other electroluminescent array substrates, such as a PLED array substrate.
  • 1 and 2 are respectively a top view and a cross-sectional view of a pixel area in an OLED array substrate in the related art, and FIG. 1 mainly shows the wiring layer and the effective light-emitting layer.
  • the effective light-emitting layer refers to the light-emitting functional layer of a single pixel.
  • the light-emitting functional layer includes a hole injection layer, a hole transport layer, a light emitting layer, an electron injection layer, and an electron transport layer.
  • the hole injection layer of the light-emitting function layer of all pixels is an integral structure. In addition to being arranged in each pixel area, it is also arranged between adjacent pixels, and basically covers the base substrate of the OLED array substrate as a whole.
  • the hole transport layer of the functional layer is also an integrated structure, which basically covers the base substrate of the OLED array substrate; the electron transport layer of the light-emitting function layer of all pixels is also an integrated structure, which basically covers the base substrate of the OLED array substrate.
  • the electron injection layer of the light-emitting function layer of all pixels is also an integral structure, which basically covers the base substrate of the OLED array substrate as a whole.
  • the light-emitting layers of the light-emitting function layers of each pixel are spaced apart from each other, and are respectively located in each pixel area, such as an opening in the pixel defining layer.
  • the light-emitting function layer of a single pixel located in the single pixel area is called an effective light-emitting layer to distinguish it from the light-emitting function layer that basically covers the base substrate in an OLED display panel.
  • the wiring layer 20, the flat layer 30, and the effective light-emitting layer 40 are sequentially arranged on the flat base substrate 10.
  • the wiring layer 20 is provided on the base substrate 10
  • the flat layer 30 is provided on the side of the wiring layer 20 away from the base substrate 10, and covers the wiring layer 20, and the effective light-emitting layer 40 is provided on the flat layer 30 The side away from the base substrate 10.
  • the wiring layer includes a first wiring 21 and a signal line 22, and the effective light-emitting layer 40 includes the left end located in the area A shown in FIGS. 1 and 2 and the first wiring 21 in FIGS. 1 and 2 The right end in the area B shown.
  • the signal line 2 is located below the central part of the effective light-emitting layer 40, and there is no trace under the right end of the effective light-emitting layer 40. This arrangement will cause the setting to go wrong.
  • the surface of the flat layer 30 on the line layer 20 on the side away from the base substrate 10 is inclined. As shown in FIG.
  • the surface of the flat layer 30 on the side away from the base substrate 10 corresponding to the left end of the effective light-emitting layer 40 is The distance between the base substrate 10 is greater than the distance between the surface of the flat layer 30 on the side away from the base substrate 10 and the base substrate 10 at the right end of the effective light-emitting layer 40, so that the left side of the effective light-emitting layer 40
  • the heights of the side end and the right end are not uniform, that is, the left end of the effective light emitting layer 40 is higher and the right end is lower.
  • the left end and the right end of the effective light emitting layer 40 are not level, and the distance between the left end of the effective light emitting layer 40 and the base substrate 10 is greater than the right end of the effective light emitting layer 40 The distance from the base substrate 10.
  • the effective light-emitting layer of the pixel area is tilted, causing the brightness to decay too slowly on one side, which leads to redness on one side, and finally causes the color difference between the two sides when the pixel area emits light.
  • the brightness of the display screen Contrast, etc. will change, causing color shift.
  • the array substrate includes: a base substrate; and a wiring layer and an effective light-emitting layer that are sequentially stacked and formed on the base substrate, wherein the wiring layer includes a first wiring and a second wiring,
  • the orthographic projection of the first trace on the base substrate and the orthographic projection of the effective light-emitting layer on the base substrate have a first overlapping area
  • the second trace is on the base substrate
  • the orthographic projection of the effective light-emitting layer and the orthographic projection of the effective light-emitting layer on the base substrate have a second overlapping area, and the first overlapping area and the second overlapping area are respectively located in the effective light-emitting layer on the substrate.
  • FIG. 3 and 4 are a top view and a cross-sectional view of a pixel area in an OLED array substrate provided by an embodiment of the present disclosure. Among them, FIG. 3 mainly shows a wiring layer and an effective light-emitting layer.
  • the OLED array substrate includes: a base substrate 10, and a wiring layer sequentially stacked and formed on the base substrate 10 20 and the effective light-emitting layer 40.
  • the wiring layer 20 includes a first wiring 21 and a second wiring 23.
  • the base substrate 10 is, for example, a flat flexible substrate.
  • the orthographic projection of the first wire 21 on the base substrate 10 and the orthographic projection of the effective light-emitting layer 40 on the base substrate 10 have a first overlapping area, and the orthographic projection of the second wire 23 on the base substrate 10
  • the orthographic projection of the effective light-emitting layer 40 on the base substrate 10 has a second overlap area, the first overlap area and the second overlap area are separated from each other, and the first overlap area and the second overlap area are respectively located
  • the effective light-emitting layer 40 is on both sides of the center line of the orthographic projection on the base substrate 10.
  • the distance between the surface of the first trace 21 facing away from the base substrate 10 and the base substrate 10 is equal to the surface of the second trace 23 facing away from the base substrate 10
  • the distance from the base substrate 10, that is, the surface of the first wiring 21 facing away from the base substrate 10 and the surface of the second wiring 23 facing away from the base substrate 10 are flush (at the same height) ).
  • the wiring layer 20 further includes a signal line 22, such as a data signal line, and the signal line 22 is configured to provide a data signal to the OLED in the pixel area.
  • the first wiring 21 and the second wiring 23 are respectively arranged on both sides of the signal line 22.
  • the signal line 22 is provided with the same material and the same layer as the first wiring 21 and the second wiring 23, and the thickness of the first wiring 21, the second wiring 23 and the signal line 22 are the same. At this time, the surface of the first wiring 21 facing away from the base substrate 10, the surface of the second wiring 23 facing away from the base substrate 10, and the surface of the signal line 22 facing away from the base substrate 10 are flat. Qi.
  • the orthographic projection of the signal line 22 on the base substrate 10 and the orthographic projection of the effective light-emitting layer 40 on the base substrate 10 have a third overlapping area, and the signal line 22 is in the The center line of the orthographic projection on the base substrate 10 is collinear with the center line of the orthographic projection of the effective light-emitting layer 40 on the base substrate 10, that is, the center line of the third overlapping area and the effective light-emitting layer 40 are in the The center lines of the orthographic projection of 10 on the base substrate coincide.
  • both the first overlapping area and the second overlapping area are parallel to the center line of the orthographic projection of the effective light-emitting layer 40 on the base substrate 10.
  • the orthographic projection of the effective light-emitting layer 40 on the base substrate 10 is an axisymmetric pattern, such as a hexagon, and the effective light-emitting layer 40 is on the base substrate 10.
  • the center line of the projection is the axis of symmetry of the axisymmetric figure, and the first overlap area and the second overlap area are symmetrically arranged with respect to the center line of the orthographic projection of the effective light-emitting layer 40 on the base substrate 10.
  • the OLED array substrate further includes a flat layer 30, wherein the flat layer 30 is disposed between the wiring layer 20 and the effective light-emitting layer 40.
  • the flat layer includes a first portion 31 and a second portion 32, the first portion 31 is located in the area A, and the second portion 32 is located in the area B.
  • the orthographic projection of the first portion 31 on the base substrate 10 coincides with the first overlap area
  • the orthographic projection of the second portion 32 on the base substrate 10 coincides with the second overlap area
  • the first portion 31 The distance between the surface facing away from the base substrate 10 and the base substrate 10 is equal to the distance between the surface of the second portion 32 facing away from the base substrate 10 and the base substrate 10, In other words, the surface of the first portion 31 facing away from the base substrate 10 and the surface of the second portion 32 facing away from the base substrate 10 are flush.
  • the OLED array substrate further includes a first electrode 50, for example, an anode, which is disposed between the flat layer 30 and the effective light-emitting layer 40.
  • the first electrode 50 includes a third part 51 and a fourth part 52.
  • the third portion 51 is located in the area A, such as but limited to the left end of the first electrode 50
  • the fourth portion 52 is located in the area B, such as but limited to the right end of the first electrode 50.
  • the orthographic projection of the third portion 51 on the base substrate 10 coincides with the first overlap area
  • the orthographic projection of the fourth portion 52 on the base substrate 10 coincides with the second overlap area.
  • the distance between the surface of the third part 51 facing away from the base substrate 10 and the base substrate 10 is equal to the distance between the surface of the fourth part 52 facing away from the base substrate 10 and the base substrate 10 That is, the surface of the third part 51 facing away from the base substrate 10 is flush with the surface of the fourth part 52 facing away from the base substrate 10. And the third part 51 and the fourth part 52 have the same thickness.
  • the effective light-emitting layer 40 includes a fifth portion 41 and a sixth portion 42.
  • the fifth portion 41 is located in the area A, such as but limited to the left end of the effective light-emitting layer 40
  • the sixth portion 42 is located in the area B, such as but limited to the right end of the effective light-emitting layer 40.
  • the orthographic projection of the fifth portion 41 on the base substrate 10 coincides with the first overlap area
  • the orthographic projection of the sixth portion 42 on the base substrate 10 coincides with the second overlap area
  • the The distance between the surface of the fifth part 41 facing away from the base substrate 10 and the base substrate 10 is equal to the distance between the surface of the sixth part 42 facing away from the base substrate 10 and the base substrate 10 That is, the surface of the fifth part 41 facing away from the base substrate 10 is flush with the surface of the sixth part 42 facing away from the base substrate 10.
  • the fifth part 41 and the sixth part 42 have the same thickness.
  • the second wiring 23 is added, so that the layers in the A area, such as the flat layer, the first electrode, the effective light-emitting layer, etc., are The corresponding film layers are even, so that when the pixel area emits light, the brightness is attenuated uniformly on both sides, thereby achieving the purpose of improving color shift.
  • the surface of the flat layer 30 away from the base substrate 10 is substantially parallel to the base substrate 10, for example, in a horizontal state.
  • the first electrode 50 and the surface of the effective light-emitting layer 40 that are formed later on the side away from the base substrate 10 are substantially parallel to the base substrate 10, so as to avoid the color difference between the two sides when the pixel region emits light.
  • the first wiring 21 is, for example, a power supply high voltage (VDD) wiring for transmitting the VDD signal.
  • VDD power supply high voltage
  • the second wiring 23 may be connected to an initialization voltage (Vinit) signal. In this way, the second wiring 23 can be connected to a stable voltage signal without affecting the normal operation of the thin film transistor that provides signals to the OLED in the pixel area.
  • Vinit initialization voltage
  • the OLED array substrate further includes an Inter-Layer Dielectric (ILD) 60 between the base substrate 10 and the wiring layer 20, and the first wiring 21 and the second wiring 23 are formed in The interlayer dielectric layer 60 faces away from the surface of the flexible backplane.
  • ILD Inter-Layer Dielectric
  • the array substrate provided by the above-mentioned embodiments of the present disclosure includes a base substrate; and a wiring layer and an effective light-emitting layer formed on the base substrate in sequence, wherein the wiring layer includes a first wiring and a second wiring.
  • the orthographic projection of the first trace on the base substrate and the orthographic projection of the effective light-emitting layer on the base substrate have a first overlapping area
  • the second trace is on the substrate
  • the orthographic projection on the substrate and the orthographic projection of the effective light-emitting layer on the base substrate have a second overlapping area, and the first overlapping area and the second overlapping area are respectively located where the effective light-emitting layer is located. Both sides of the center line of the orthographic projection on the base substrate.
  • the tilt of the flat layer and the effective light-emitting layer is reduced or even eliminated.
  • the pixel area emits light, the brightness is attenuated uniformly on both sides, achieving the purpose of improving the color shift.
  • FIG. 5 is a flow chart of the method for manufacturing the OLED array substrate provided in the foregoing embodiment of the disclosure. The exemplary method is described as follows in conjunction with the accompanying drawings:
  • Step S1 Provide a base substrate
  • the base substrate is, for example, a flat flexible substrate.
  • Step S2 forming a wiring layer on the surface of the base substrate, the wiring layer including a first wiring and a second wiring;
  • the metal layer obtains a first trace, such as a power supply high-voltage trace, and a second trace.
  • Step S3 forming a flat layer on the base substrate on which the wiring layer is formed;
  • a coating process is used to form a flat layer on the entire upper surface of the base substrate on which the wiring layer is formed. Because the second wiring is added, the flat layer disposed on the side of the wiring layer away from the base substrate is far away from the substrate. The surface of one side of the substrate is substantially parallel to the base substrate.
  • Step S4 forming a first electrode on the base substrate on which the flat layer is formed;
  • the first electrode such as the anode
  • a patterning process such as deposition, coating photoresist, exposure, development, etching, and stripping processes.
  • the anode is provided on the flat surface of the side of the flat layer away from the base substrate, whereby the surface of the side of the flat layer away from the base substrate is substantially parallel to the base substrate.
  • Step S5 forming an effective light-emitting layer on the base substrate on which the first electrode is formed.
  • the effective light-emitting layer is formed by the evaporation process, and the effective light-emitting layer is arranged on the flat surface of the flat layer away from the base substrate. Therefore, the brightness of the pixel area is attenuated uniformly on both sides when the pixel area emits light to achieve the purpose of improving color shift.
  • embodiments of the present disclosure also provide a display panel, including the array substrate in any of the above-mentioned embodiments, and the array substrate can be prepared according to the above-mentioned manufacturing method of the array substrate.
  • Other indispensable components of the display panel are understood by those of ordinary skill in the art, and will not be repeated here.
  • embodiments of the present disclosure also provide a display device including the above-mentioned display panel, and the display device may include the display substrate in the foregoing embodiment.
  • the display device can be any product or component with a display function and a camera function such as a TV, a monitor, a digital photo frame, a mobile phone, a smart watch, a tablet computer, etc.
  • FIG. 6 is a schematic diagram of a pixel driving circuit in a pixel area of an OLED array substrate according to an embodiment of the present disclosure, wherein the pixel driving circuit includes:
  • the source of the first thin film transistor T1 is connected to the initialization signal Vinit, the gate is electrically connected to the reset signal Reset, and the drain is electrically connected to the first node A;
  • the gate of the second thin film transistor T2 is connected to the scanning signal Gate, the source is electrically connected to the second node B, and the drain is electrically connected to the first node A;
  • the source of the third thin film transistor T3 is electrically connected to the second node B, the gate is electrically connected to the first node A, and the drain is electrically connected to the third node C;
  • the gate of the fourth thin film transistor T4 is connected to the scan signal Gate, the source is electrically connected to the data signal Data, and the drain is electrically connected to the third node C;
  • the source of the fifth thin film transistor T5 is connected to the first power supply voltage, such as the power high voltage VDD, the gate is connected to the light emission control signal EM, and the drain is electrically connected to the third node C;
  • the source of the sixth thin film transistor T6 is electrically connected to the second node B, the gate is connected to the emission control signal EM, and the drain is electrically connected to the fourth node D;
  • the source of the seventh thin film transistor T7 is electrically connected to the initialization signal Vinit, and the drain is electrically connected to the fourth node D;
  • the anode of the organic light emitting diode D1 is connected to the fourth node, and the cathode is connected to a second power supply voltage, such as a power supply low voltage VSS;
  • Both ends of the capacitor C1 are electrically connected to the first node and the first power supply voltage, such as the power high voltage VDD.
  • the second wiring 23 is connected to the initialization signal, that is, the Vinit signal, that is, the second wiring 23 can be connected to the source of the first thin film transistor T1 and the seventh thin film transistor T7.
  • the source is electrically connected.
  • the second wiring 23 may also be electrically connected to the first node A.
  • the second wiring 23 may be suspended, that is, the second wiring 23 is a dummy electrode.

Abstract

一种阵列基板及其制备方法、显示面板、显示装置和像素驱动电路。阵列基板包括：衬底基板（10）；以及依次层叠形成在衬底基板上的走线层（20）和有效发光层（40），其中，走线层包括第一走线（21）和第二走线（23），第一走线在衬底基板上的正投影与有效发光层在衬底基板上的正投影具有第一交叠区域，第二走线在衬底基板上的正投影与有效发光层在衬底基板上的正投影具有第二交叠区域，第一交叠区域和第二交叠区域分别位于有效发光层在衬底基板上的正投影的中线的两侧。

Description

阵列基板及其制备方法、显示面板和显示装置和像素驱动电路 技术领域
本公开涉及显示技术领域，尤其涉及一种阵列基板及其制备方法、显示面板、和显示装置和像素驱动电路。
背景技术
近年来，随着显示技术的进步，有机发光二极管(Organic Light Emitting Diode，OLED)显示器是当今平板显示器研究领域的热点之一，越来越多的有源矩阵有机发光二极管(Active Matrix Organic Light Emitting Diode，AMOLED)显示面板进入市场，相对于传统的薄膜晶体管液晶显示面板(Thin Film Transistor Liquid Crystal Display，TFTLCD)，AMOLED具有更快的反应速度，更高的对比度以及更广大的视角。且随着显示技术的发展，越来越多的电子设备中开始使用轻薄且抗冲击特性表现良好的可弯折柔性OLED显示屏。
公开内容
本公开一些实施例提供一种阵列基板，包括：衬底基板；以及依次层叠形成在所述衬底基板上的走线层和有效发光层，其中，所述走线层包括第一走线和第二走线，所述第一走线在所述衬底基板上的正投影与所述有效发光层在衬底基板上的正投影具有第一交叠区域，所述第二走线在所述衬底基板上的正投影与所述有效发光层在衬底基板上的正投影具有第二交叠区域，所述第一交叠区域和所述第二交叠区域分别位于所述有效发光层在所述衬底基板上的正投影的中线的两侧。
在一些实施例中，所述第一走线背向所述衬底基板的表面与所述衬底基板之间的距离等于所述第二走线背向所述衬底基板的表面与所述衬底基板之间的距离。
在一些实施例中，所述有效发光层在所述衬底基板上的正投影为轴对称图形，所述有效发光层在所述衬底基板上的正投影的中线为所述轴对称图形的对称轴。
在一些实施例中，所述第一交叠区域和所述第二交叠区域相对于所述有效发光层在所述衬底基板上的正投影的中线对称设置。
在一些实施例中，所述第一交叠区域和所述第二交叠区域均平行于所述有效发光层在所述衬底基板上的正投影的中线。
在一些实施例中，走线层还包括信号线，其中信号线在所述衬底基板上的正投影的中线与所述有效发光层在所述衬底基板上的正投影的中线共线。
在一些实施例中，所述第一走线，第二走线以及信号线采用相同材料同层设置，所述第一走线，第二走线以及信号线的厚度相同。
在一些实施例中，所述第一走线为电源高电压走线，所述信号线为数据信号线。
在一些实施例中，所述的阵列基板还包括：平坦层，设置在所述走线层和所述有效发光层之间，其中，平坦层包括第一部分和第二部分，第一部分在衬底基板上的正投影与所述第一交叠区域重合，所述第二部分在衬底基板上的正投影与所述第二交叠区域重合，所述第一部分背向所述衬底基板的表面与所述衬底基板之间的距离等于所述第二部分背向所述衬底基板的表面与所述衬底基板之间的距离。
在一些实施例中，所述的阵列基板，还包括：第一电极，设置在所述平坦层和所述有效发光层之间，其中，第一电极包括第三部分和第四部分，第三部分在衬底基板上的正投影与所述第一交叠区域重合，所述第四部分在衬底基板上的正投影与所述第二交叠区域重合，所述第三部分背向所述衬底基板的表面与所述衬底基板之间的距离等于所述第四部分背向所述衬底基板的表面与所述衬底基板之间的距离，且第三部分与第四部分厚度相同。
在一些实施例中，有效发光层包括第五部分和第六部分，第五部分在衬底基板上的正投影与所述第一交叠区域重合，所述第六部分在衬底基板上的正投影与所述第二交叠区域重合，所述第五部分背向所述衬底基板的表面与所述衬底基板之间的距离等于所述第六部分背向所述衬底基板的表面与所述衬底基板之间的距离，且第五部分与第六部分厚度相同。
在一些实施例中，所述第五部分和所述第六部分分别位于所述有效发光层相对的两边缘区域。
在一些实施例中，所述第二走线接入初始化电压信号。
在一些实施例中，所述的阵列基板，还包括：层间介质层，设置在所述衬底基板和所述走线层之间；所述第一走线和所述第二走线形成在所述层间介质层背 向所述衬底基板的表面。
本公开一些实施例提供一种显示面板，包括如前述实施例所述的阵列基板。
本公开一些实施例提供一种显示装置，包括如前述实施例所述的显示面板。
本公开一些实施例提供一种阵列基板的制备方法，包括：提供一衬底基板；在所述衬底基板上形成走线层，所述走线层包括第一走线和第二走线；在形成有走线层的衬底基板上形成有效发光层，其中，所述第一走线在所述衬底基板上的正投影与所述有效发光层在衬底基板上的正投影具有第一交叠区域，所述第二走线在所述衬底基板上的正投影与所述有效发光层在衬底基板上的正投影具有第二交叠区域，所述第一交叠区域和所述第二交叠区域分别位于所述有效发光层在所述衬底基板上的正投影的中线的两侧。
在一些实施例中，在形成有效发光层之前，所述制备方法还包括：形成有走线层的衬底基板上形成平坦层，其中，平坦层包括第一部分和第二部分，第一部分在衬底基板上的正投影与所述第一交叠区域重合，所述第二部分在衬底基板上的正投影与所述第二交叠区域重合，所述第一部分背向所述衬底基板的表面与所述衬底基板之间的距离等于所述第二部分背向所述衬底基板的表面与所述衬底基板之间的距离。
在一些实施例中，在形成有效发光层之前，所述制备方法还包括：形成有平坦层的衬底基板上形成第一电极，其中，第一电极包括第三部分和第四部分，第三部分在衬底基板上的正投影与所述第一交叠区域重合，所述第四部分在衬底基板上的正投影与所述第二交叠区域重合，所述第三部分背向所述衬底基板的表面与所述衬底基板之间的距离等于所述第四部分背向所述衬底基板的表面与所述衬底基板之间的距离，且第三部分与第四部分厚度相同。
本公开一些实施例提供一种应用于前述实施例所述的阵列基板的像素驱动电路，包括：
第一薄膜晶体管、第二薄膜晶体管、第三薄膜晶体管、第四薄膜晶体管、第五薄膜晶体管、第六薄膜晶体管和第七薄膜晶体管、电容、有机发光二极管，其中：
所述第一薄膜晶体管的源极接入初始化信号，栅极电性连接复位信号，漏极电性连接第一节点；
所述第二薄膜晶体管的栅极连接扫描信号，源极电性连接第二节点，漏极电 性连接所述第一节点；
所述第三薄膜晶体管的源极电性连接所述第二节点，栅极电性连接所述第一节点，漏极电性连接第三节点；
所述第四薄膜晶体管的栅极连接扫描信号，源极电性连接数据信号，漏极电性连接所述第三节点；
所述第五薄膜晶体管的源极接入第一电源电压，栅极接入发光控制信号，漏极电性连接所述第三节点；
所述第六薄膜晶体管的源极电性连接所述第二节点，栅极接入发光控制信号，漏极电性连接第四节点；
所述第七薄膜晶体管的栅极连接扫描信号，源极电性连接电性连接所述接入初始化信号，漏极电性连接所述第四节点；
所述有机发光二极管的第一电极连接所述第四节点，第二电极接入第二电源电压；
所述电容的两端分别电性连接第一节点和第一电源电压；
所述第二走线悬置、或者接入初始化信号，或者与第一节点电连接。
附图说明
通过阅读参照以下附图所作的对非限制性实施例所作的详细描述，本公开的其它特征、目的和优点将会变得更明显：
图1为相关技术中的OLED阵列基板中一个像素区域的俯视示意图；
图2为图1中OLED阵列基板中的像素区域的剖面图；
图3根据本公开一些实施例提供的一种OLED阵列基板中的一个像素区域的俯视示意图；
图4为图3中OLED阵列基板中的像素区域的剖面图；
图5为根据本公开一些实施例提供的一种OLED阵列基板的制备方法的流程图；
图6为根据本公开实施例提供的对应OLED阵列基板中的一个像素区域的像素驱动电路的示意图。
具体实施方式
下面结合附图和实施例对本公开作进一步的详细说明。可以理解的是，此处 所描述的具体实施例仅仅用于解释相关发明，而非对该发明的限定。另外还需要说明的是，为了便于描述，附图中仅示出了与发明相关的部分。
需要说明的是，在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互组合。
另外，在下面的详细描述中，为便于解释，阐述了许多具体的细节以提供对本披露实施例的全面理解。然而明显地，一个或多个实施例在没有这些具体细节的情况下也可以被实施。
应该理解的是，尽管在这里可使用术语第一、第二等来描述不同的元件，但是这些元件不应受这些术语的限制。这些术语仅是用来将一个元件与另一个元件区分开来。例如，在不脱离示例实施例的范围的情况下，第一元件可以被命名为第二元件，类似地，第二元件可以被命名为第一元件。如在这里使用的术语“和/或”包括一个或多个相关所列的项目的任意组合和所有组合。
应该理解的是，当元件或层被称作“形成在”另一元件或层“上”时，该元件或层可以直接地或间接地形成在另一元件或层上。也就是，例如，可以存在中间元件或中间层。相反，当元件或层被称作“直接形成在”另一元件或层“上”时，不存在中间元件或中间层。应当以类似的方式来解释其它用于描述元件或层之间的关系的词语(例如，“在...之间”与“直接在…之间”、“相邻的”与“直接相邻的”等)。
本文中使用的术语仅是为了描述特定实施例的目的，而不意图限制实施例。如本文中所使用的，除非上下文另外明确指出，否则单数形式也意图包括复数形式。还将理解的是，当在此使用术语“包含”和/或“包括”时，说明存在所述特征、整体、步骤、操作、元件和/或组件，但不排除存在或附加一个或多个其它特征、整体、步骤、操作、元件、组件和/或它们的组合。
在本文中，如无特别说明，表述“厚度”指的是层或部件在垂直于衬底的上表面(在使用状态下，衬底的上表面为面对使用者的表面)的方向上的尺寸。
在本文中，如无特别说明，表述“位于同一层”一般表示的是：第一部件和第二部件可以使用相同的材料并且可以通过同一构图工艺形成。
传统的显示技术都是采用单一的显示方式，在观看时，例如，当用户的观看方向从屏幕左侧改变为屏幕右侧方向时，液晶显示装置的亮度、对比度、色域和视角色偏(不同视角的颜色差异)等会发生变化，造成视觉效果降低，特别对一 些高端显示或者特殊显示场所，例如医疗、平面设计等领域，对视角色偏要求较高，需要对普通显示面板的视角色偏进行改善。
OLED显示屏主要通过电流驱动电致发光器件发光而实现图像显示。当用户的观看角度变化时，显示屏的亮度、对比度等也会发生变化，出现色偏现象。因此，如何改善OLED显示区的色偏问题，提高显示面板的显示效果，是目前亟待解决的问题。
本公开中，阵列基板以OLED阵列基板为了进行解释说明，OLED阵列基板包括多个阵列排布的像素区域，每个像素区域设置有一个OLED器件，每个OLED器件包括依次远离衬底设置的第一电极、有效发光层以及第二电极，第一电极例如为阳极，有效发光层例如为红色有机有效发光层、绿色有机有效发光层或蓝色有机有效发光层，第二电极例如为阴极。本领域技术人员可以理解的是，本公开中的阵列基板还可以是其他电致发光阵列基板，例如为PLED阵列基板。图1和图2分别为相关技术中OLED阵列基板中的一个像素区域俯视图和剖面图，其中，图1中主要示出了走线层和有效发光层。
在本公开中，有效发光层是指单个像素的发光功能层，通常发光功能层包括空穴注入层、空穴传输层、发光层、电子注入层和电子传输层，在整个OLED阵列基板上，所有像素的发光功能层的空穴注入层为一体结构，除了设置在各像素区域内还设置在相邻像素之间，基本上整体覆盖OLED阵列基板的衬底基板，类似的，所有像素的发光功能层的空穴传输层亦为一体结构，基本上整体覆盖OLED阵列基板的衬底基板；所有像素的发光功能层的电子传输层亦为一体结构，基本上整体覆盖OLED阵列基板的衬底基板；所有像素的发光功能层的电子注入层亦为一体结构，基本上整体覆盖OLED阵列基板的衬底基板。而各像素的发光功能层的发光层相互间隔，分别位于各像素区域内，例如像素界定层中的开口内。本公开中，将位于单个像素区域内的单个像素的发光功能层称作有效发光层，以与OLED显示面板中基本上整体覆盖衬底基板的发光功能层相区别。
参照图1和图2，在以GGRB排列方式设置的像素结构中，以红色像素区域为例，走线层20、平坦层30以及有效发光层40依次设置在平坦的衬底基板10上，具体地，走线层20设置在衬底基板10上，平坦层30设置在走线层20远离衬底基板10的一侧，并且覆盖所述走线层20，有效发光层40设置在平坦层30远离衬底基板10的一侧。
走线层包括第一走线21和信号线22，有效发光层40包括位于图1和图2中所示的区域A中的左侧端部和位于第一走线21图1和图2中所示的B区域中的右侧端部。位于有效发光层40的左侧端部下方，信号线2位于有效发光层40的中心部分的下方，而有效发光层40的右侧端部下方不存在任何走线，该种设置会引起设置走线层20上的平坦层30的远离衬底基板10一侧的表面倾斜，如图2所示，对应有效发光层40左侧端部的平坦层30的远离衬底基板10一侧的表面与衬底基板10之间的距离大于对应有效发光层40右侧端部的平坦层30的远离衬底基板10一侧的表面与衬底基板10之间的距离，从而使得有效发光层40的左侧端部和右侧端部的高度不一致，即有效发光层40的左侧端部较高，右侧端部较低。也就是说，有效发光层40的左侧端部和右侧端部并不平齐，有效发光层40的左侧端部与衬底基板10之间的距离大于有效发光层40的右侧端部与衬底基板10之间的距离。从而使得像素区域的有效发光层倾斜，引起亮度在一侧衰减过慢，从而导致一侧发红，最终导致像素区域发光时两侧配色差异，当用户的观看角度变化时，显示屏的亮度、对比度等会发生变化，出现色偏现象。
鉴于上述缺陷，本公开实施例提供了一种阵列基板，能够改善色偏现象。具体地，阵列基板，包括：衬底基板；以及依次层叠形成在所述衬底基板上的走线层和有效发光层，其中，所述走线层包括第一走线和第二走线，所述第一走线在所述衬底基板上的正投影与所述有效发光层在衬底基板上的正投影具有第一交叠区域，所述第二走线在所述衬底基板上的正投影与所述有效发光层在衬底基板上的正投影具有第二交叠区域，所述第一交叠区域和所述第二交叠区域分别位于所述有效发光层在所述衬底基板上的正投影的中线的两侧。通过设置第二走线，可以减轻甚至消除平坦层以及有效发光层倾斜，减轻或避免像素区域发光时像素区域两侧出现色差。下面将参考附图并结合实施例来详细说明本公开。
图3和图4，为本公开实施例提供的一种OLED阵列基板中的一个像素区域俯视图和剖面图，其中，图3中主要示出了走线层和有效发光层。
参照图3和图4，在以GGRB排列方式设置的像素结构中，以红色像素区域为例，该OLED阵列基板包括：衬底基板10，以及依次层叠形成在衬底基板10上的走线层20和有效发光层40，走线层20包括第一走线21和第二走线23。衬底基板10例如为平坦的柔性基板。第一走线21在衬底基板10上的正投影与有效发光层40在在衬底基板10上的正投影具有第一交叠区域，第二走线23在衬 底基板10上的正投影与有效发光层40在在衬底基板10上的正投影具有第二交叠区域，第一交叠区域与第二交叠区域彼此分离，且第一交叠区域和第二交叠区域分别位于有效发光层40在所述衬底基板10上的正投影的中线的两侧。
在一些实施例中，第一走线21背向所述衬底基板10的表面与所述衬底基板10之间的距离等于所述第二走线23背向所述衬底基板10的表面与所述衬底基板10之间的距离，即第一走线21背向所述衬底基板10的表面与第二走线23背向所述衬底基板10的表面平齐(处于相同高度)。
继续参照图3和图4，走线层20还包括信号线22，例如为数据信号线，信号线22配置为向像素区域中的OLED提供数据信号。第一走线21和第二走线23分别设置在信号线22两侧。在一些实施例中，信号线22与第一走线21和第二走线23采用相同材料同层设置，且第一走线21，第二走线23以及信号线22的厚度相同。此时，第一走线21背向所述衬底基板10的表面与第二走线23背向所述衬底基板10的表面以及信号线22背向所述衬底基板10的表面均平齐。
在一些实施例中，信号线22在所述衬底基板10上的正投影与所述有效发光层40在所述衬底基板上10的正投影具有第三交叠区域，信号线22在所述衬底基板10上的正投影的中线与所述有效发光层40在所述衬底基板上10的正投影的中线共线，即第三交叠区域的中线与有效发光层40在所述衬底基板上10的正投影的中线重合。
在一些实施例中，第一交叠区域与第二交叠区域均平行于有效发光层40在所述衬底基板上10的正投影的中线。
在一些实施例中，所述有效发光层40在所述衬底基板10上的正投影为轴对称图形，例如为六边形，所述有效发光层40在所述衬底基板10上的正投影的中线为所述轴对称图形的对称轴，第一交叠区域与第二交叠区域相对于所述有效发光层40在所述衬底基板10上的正投影的中线对称设置。
在一些实施例中，如图3和4所示，OLED阵列基板还包括平坦层30，其中，平坦层30设置在走线层20和有效发光层40之间。如图3和图4所示，平坦层包括第一部分31和第二部分32，第一部分31位于区域A中，第二部分32位于区域B中。第一部分31在衬底基板10上的正投影与第一交叠区域重合，所述第二部分32在衬底基板10上的正投影与所述第二交叠区域重合，所述第一部分31背向所述衬底基板10的表面与所述衬底基板10之间的距离等于所述第二部分32 背向所述衬底基板10的表面与所述衬底基板10之间的距离，也就是说，第一部分31背向所述衬底基板10的表面与第二部分32背向所述衬底基板10的表面平齐。
在一些实施例中，如图3和4所示，OLED阵列基板还包括第一电极50，例如为阳极，设置在平坦层30和有效发光层40之间。第一电极50包括第三部分51和第四部分52。第三部分51位于区域A中，例如但限于第一电极50的左侧端部，第四部分52位于区域B中，例如但限于第一电极50的右侧端部。第三部分51在衬底基板上10的正投影与所述第一交叠区域重合，所述第四部分52在衬底基板10上的正投影与所述第二交叠区域重合，所述第三部分51背向所述衬底基板10的表面与所述衬底基板10之间的距离等于所述第四部分52背向所述衬底基板10的表面与所述衬底基板10之间的距离，就是说，第三部分51背向所述衬底基板10的表面与第四部分52背向所述衬底基板10的表面平齐。并且第三部分51与第四部分52厚度相同。
在一些实施例中，如图3和4所示，有效发光层40包括第五部分41和第六部分42。第五部分41位于区域A中，例如但限于有效发光层40的左侧端部，第六部分42位于区域B中，例如但限于有效发光层40的右侧端部。第五部分41在衬底基板上10的正投影与所述第一交叠区域重合，所述第六部分42在衬底基板10上的正投影与所述第二交叠区域重合，所述第五部分41背向所述衬底基板10的表面与所述衬底基板10之间的距离等于所述第六部分42背向所述衬底基板10的表面与所述衬底基板10之间的距离，就是说，第五部分41背向所述衬底基板10的表面与第六部分42背向所述衬底基板10的表面平齐。且第五部分41与第六部分42厚度相同。
相较于相关技术，本公开的上述该些实施例中，增加了第二走线23，使A区域中的各膜层，例如平坦层，第一电极，有效发光层等与B区域中的对应的膜层均平齐，由此像素区域发光时，亮度在两侧衰减一致，从而达到改善色偏的目的。具体地，平坦层30远离衬底基板10一侧的表面基本上与衬底基板10平行，例如处于水平状态。使得后续形成的第一电极50以及有效发光层40远离衬底基板10一侧的表面基本上与衬底基板10平行，避免像素区域发光时两侧配色差异而导致色差。
在一些实施例中，第一走线21例如为电源高电压(VDD)走线，用于传输 VDD信号。
在一些实施例中，第二走线23可以接入初始化电压(Vinit)信号。由此第二走线23可以接入稳定的电压信号，不会影响像素区域为OLED提供信号的薄膜晶体管的正常工作。
在一些实施例中，OLED阵列基板还包括衬底基板10和走线层20之间的层间介质层(Inter-Layer Dielectric，ILD)60，第一走线21和第二走线23形成在层间介质层60背向柔性背板的表面。
本公开上述实施例提供的阵列基板包括衬底基板；以及依次层叠形成在所述衬底基板上的走线层和有效发光层，其中，所述走线层包括第一走线和第二走线，所述第一走线在所述衬底基板上的正投影与所述有效发光层在衬底基板上的正投影具有第一交叠区域，所述第二走线在所述衬底基板上的正投影与所述有效发光层在衬底基板上的正投影具有第二交叠区域，所述第一交叠区域和所述第二交叠区域分别位于所述有效发光层在所述衬底基板上的正投影的中线的两侧。与相关技术相比，通过增设第二走线，从而减轻甚至消除平坦层以及有效发光层倾斜，像素区域发光时亮度在两侧衰减一致，达到改善色偏的目的。
图5为本公开前述实施例中提供的OLED阵列基板的制备方法的流程图。下面结合附图对该示例性的方法描述如下：
步骤S1：提供一衬底基板；
衬底基板例如为平坦的柔性基板。
步骤S2，在衬底基板的表面形成走线层，走线层包括第一走线和第二走线；
具体的，首先在衬底基板的表面沉积金属层，然后在金属层背向衬底基板的表面涂覆光刻胶，通过预先设置的掩膜版对光刻胶进行曝光和显影，再刻蚀金属层，获得第一走线，例如为电源高压走线，以及第二走线。
步骤S3：在形成有走线层的衬底基板上形成平坦层；
具体地，采用涂覆工艺在形成有走线层的衬底基板的整个上表面形成平坦层，由于增设了第二走线，设置在走线层远离衬底基板一侧的平坦层远离衬底基板的一侧的表面基本上平行于衬底基板。
步骤S4：在形成有平坦层的衬底基板上形成第一电极；
具体地，通过构图工艺，例如沉积、涂覆光刻胶，曝光，显影、刻蚀、剥离工艺等形成第一电极，例如为阳极。阳极设置在平坦层远离衬底基板的一侧的平 坦的表面上，由此，平坦层远离衬底基板的一侧的表面基本上平行于衬底基板。
步骤S5，在形成有第一电极的衬底基板上形成有效发光层。
采用蒸镀工艺形成有效发光层，有效发光层设置在平坦层远离衬底基板的一侧的平坦的表面上，由此，像素区域发光时亮度在两侧衰减一致，达到改善色偏的目的。
基于同一发明构思，本公开实施例还提供了一种显示面板，包括上述任一实施例中阵列基板，该阵列基板可以按照上述阵列基板的制备方法制备。对于该显示面板的其它必不可少的组成部分均为本领域的普通技术人员应该理解具有的，在此不予赘述。
基于同一发明构思，本公开实施例还提供了一种显示装置，包括上述显示面板，显示装置可以包括前述实施例中的显示基板。显示装置可以为：电视、显示器、数码相框、手机、智能手表、平板电脑等任何具有显示功能及摄像功能的产品或部件。
对于该显示面板的其它必不可少的组成部分均为本领域的普通技术人员应该理解具有的，在此不予赘述。
图6为根据本公开实施例提供的OLED阵列基板中的一个像素区域的像素驱动电路的示意图，其中，该像素驱动电路包括：
第一薄膜晶体管T1、第二薄膜晶体管T2、第三薄膜晶体管T3、第四薄膜晶体管T4、第五薄膜晶体管T5、第六薄膜晶体管T6和第七薄膜晶体管T7、电容C1、有机发光二极管D1(即OLED器件)，其中：
所述第一薄膜晶体管T1的源极接入初始化信号Vinit，栅极电性连接复位信号Reset，漏极电性连接第一节点A；
所述第二薄膜晶体管T2的栅极连接扫描信号Gate，源极电性连接第二节点B，漏极电性连接所述第一节点A；
所述第三薄膜晶体管T3的源极电性连接所述第二节点B，栅极电性连接所述第一节点A，漏极电性连接第三节点C；
所述第四薄膜晶体管T4的栅极连接扫描信号Gate，源极电性连接数据信号Data，漏极电性连接所述第三节点C；
所述第五薄膜晶体管T5的源极接入第一电源电压，例如电源高电压VDD，栅极接入发光控制信号EM，漏极电性连接所述第三节点C；
所述第六薄膜晶体管T6的源极电性连接所述第二节点B，栅极接入发光控制信号EM，漏极电性连接第四节点D；
所述第七薄膜晶体管T7的源极电性连接电性接入初始化信号Vinit，漏极电性连接所述第四节点D；
所述有机发光二极管D1的阳极连接所述第四节点，阴极接入第二电源电压，例如电源低电压VSS；
所述电容C1的两端分别电性连接第一节点和第一电源电压，例如电源高电压VDD。
在一些实施例中，如图6所示，所述第二走线23接入初始化信号，即Vinit信号，即第二走线23可以与第一薄膜晶体管T1的源极以及第七薄膜晶体管T7的源极电连接。
在一些实施例中，第二走线23还可以与第一节点A电连接。
在一些实施例中，第二走线23可以悬置，即第二走线23为Dummy电极。
以上描述仅为本公开的较佳实施例以及对所运用技术原理的说明。本领域技术人员应当理解，本公开中所涉及的发明范围，并不限于上述技术特征的特定组合而成的技术方案，同时也应涵盖在不脱离所述发明构思的情况下，由上述技术特征或其等同特征进行任意组合而形成的其它技术方案。例如上述特征与本公开中公开的(但不限于)具有类似功能的技术特征进行互相替换而形成的技术方案。＝

Claims (20)

  1. 一种阵列基板，包括：
    衬底基板；以及
    依次层叠形成在所述衬底基板上的走线层和有效发光层，
    其中，所述走线层包括第一走线和第二走线，所述第一走线在所述衬底基板上的正投影与所述有效发光层在衬底基板上的正投影具有第一交叠区域，所述第二走线在所述衬底基板上的正投影与所述有效发光层在衬底基板上的正投影具有第二交叠区域，所述第一交叠区域和所述第二交叠区域分别位于所述有效发光层在所述衬底基板上的正投影的中线的两侧。
  2. 根据权利要求1所述的阵列基板，其中，所述第一走线背向所述衬底基板的表面与所述衬底基板之间的距离等于所述第二走线背向所述衬底基板的表面与所述衬底基板之间的距离。
  3. 根据权利要求1所述的阵列基板，其中，所述有效发光层在所述衬底基板上的正投影为轴对称图形，所述有效发光层在所述衬底基板上的正投影的中线为所述轴对称图形的对称轴。
  4. 根据权利要求3所述的阵列基板，其中，所述第一交叠区域和所述第二交叠区域相对于所述有效发光层在所述衬底基板上的正投影的中线对称设置。
  5. 根据权利要求4所述的阵列基板，其中，所述第一交叠区域和所述第二交叠区域均平行于所述有效发光层在所述衬底基板上的正投影的中线。
  6. 根据权利要求1-5中任一项所述阵列基板，其中，走线层还包括信号线，其中信号线在所述衬底基板上的正投影的中线与所述有效发光层在所述衬底基板上的正投影的中线共线。
  7. 根据权利要求6所述阵列基板，其中，所述第一走线，第二走线以及信号线采用相同材料同层设置，所述第一走线，第二走线以及信号线的厚度相同。
  8. 根据权利要求7所述阵列基板，其中，所述第一走线为电源高电压走线，所述信号线为数据信号线。
  9. 根据权利要求1-5中任一项所述的阵列基板，还包括：
    平坦层，设置在所述走线层和所述有效发光层之间，
    其中，平坦层包括第一部分和第二部分，第一部分在衬底基板上的正投影与所述第一交叠区域重合，所述第二部分在衬底基板上的正投影与所述第二交叠区域重合，所述第一部分背向所述衬底基板的表面与所述衬底基板之间的距离等于所述第二部分背向所述衬底基板的表面与所述衬底基板之间的距离。
  10. 根据权利要求9所述的阵列基板，还包括：
    第一电极，设置在所述平坦层和所述有效发光层之间，
    其中，第一电极包括第三部分和第四部分，第三部分在衬底基板上的正投影与所述第一交叠区域重合，所述第四部分在衬底基板上的正投影与所述第二交叠区域重合，所述第三部分背向所述衬底基板的表面与所述衬底基板之间的距离等于所述第四部分背向所述衬底基板的表面与所述衬底基板之间的距离，且第三部分与第四部分厚度相同。
  11. 根据权利要求10所述的阵列基板，其中，有效发光层包括第五部分和第六部分，第五部分在衬底基板上的正投影与所述第一交叠区域重合，所述第六部分在衬底基板上的正投影与所述第二交叠区域重合，所述第五部分背向所述衬底基板的表面与所述衬底基板之间的距离等于所述第六部分背向所述衬底基板的表面与所述衬底基板之间的距离，且第五部分与第六部分厚度相同。
  12. 根据权利要求11所述的阵列基板，其中，所述第五部分和所述第六部分分别位于所述有效发光层相对的两边缘区域。
  13. 根据权利要求1-5中任一项所述阵列基板，其中，所述第二走线接入初始化电压信号。
  14. 根据权利要求1-5中任一项所述的阵列基板，还包括：
    层间介质层，设置在所述衬底基板和所述走线层之间；
    所述第一走线和所述第二走线形成在所述层间介质层背向所述衬底基板的表面。
  15. 一种显示面板，包括如权利要求1至14中任一项所述的阵列基板。
  16. 一种显示装置，包括如权利要求15所述的显示面板。
  17. 一种阵列基板的制备方法，包括：
    提供一衬底基板；
    在所述衬底基板上形成走线层，所述走线层包括第一走线和第二走线；
    在形成有走线层的衬底基板上形成有效发光层，
    其中，所述第一走线在所述衬底基板上的正投影与所述有效发光层在衬底基板上的正投影具有第一交叠区域，所述第二走线在所述衬底基板上的正投影与所述有效发光层在衬底基板上的正投影具有第二交叠区域，所述第一交叠区域和所述第二交叠区域分别位于所述有效发光层在所述衬底基板上的正投影的中线的两侧。
  18. 根据权利要求17所述的制备方法，其中，在形成有效发光层之前，所述制备方法还包括：
    形成有走线层的衬底基板上形成平坦层，
    其中，平坦层包括第一部分和第二部分，第一部分在衬底基板上的正投影与所述第一交叠区域重合，所述第二部分在衬底基板上的正投影与所述第二交叠区域重合，所述第一部分背向所述衬底基板的表面与所述衬底基板之间的距离等于所述第二部分背向所述衬底基板的表面与所述衬底基板之间的距离。
  19. 根据权利要求18所述的制备方法，其中，在形成有效发光层之前，所述制备方法还包括：
    形成有平坦层的衬底基板上形成第一电极，
    其中，第一电极包括第三部分和第四部分，第三部分在衬底基板上的正投影与所述第一交叠区域重合，所述第四部分在衬底基板上的正投影与所述第二交叠区域重合，所述第三部分背向所述衬底基板的表面与所述衬底基板之间的距离等于所述第四部分背向所述衬底基板的表面与所述衬底基板之间的距离，且第三部分与第四部分厚度相同。
  20. 一种应用于权利要求1至14任一项所述的阵列基板的像素驱动电路，包括：
    第一薄膜晶体管、第二薄膜晶体管、第三薄膜晶体管、第四薄膜晶体管、第五薄膜晶体管、第六薄膜晶体管和第七薄膜晶体管、电容、有机发光二极管，其中：
    所述第一薄膜晶体管的源极接入初始化信号，栅极电性连接复位信号，漏极电性连接第一节点；
    所述第二薄膜晶体管的栅极连接扫描信号，源极电性连接第二节点，漏极电性连接所述第一节点；
    所述第三薄膜晶体管的源极电性连接所述第二节点，栅极电性连接所述第一 节点，漏极电性连接第三节点；
    所述第四薄膜晶体管的栅极连接扫描信号，源极电性连接数据信号，漏极电性连接所述第三节点；
    所述第五薄膜晶体管的源极接入第一电源电压，栅极接入发光控制信号，漏极电性连接所述第三节点；
    所述第六薄膜晶体管的源极电性连接所述第二节点，栅极接入发光控制信号，漏极电性连接第四节点；
    所述第七薄膜晶体管的栅极连接扫描信号，源极电性连接电性连接所述接入初始化信号，漏极电性连接所述第四节点；
    所述有机发光二极管的第一电极连接所述第四节点，第二电极接入第二电源电压；
    所述电容的两端分别电性连接第一节点和第一电源电压；
    所述第二走线悬置、或者接入初始化信号，或者与第一节点电连接。
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