Classifications

• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03K—PULSE TECHNIQUE
  • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
  • H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F30/00—Computer-aided design [CAD]
  • G06F30/30—Circuit design
  • G06F30/34—Circuit design for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F30/00—Computer-aided design [CAD]
  • G06F30/30—Circuit design
  • G06F30/34—Circuit design for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
  • G06F30/343—Logical level

Definitions

• the present application relates to the field of electronic information technology, in particular to a reconfigurable logic gate circuit and a control method for the circuit.
• the commonly used hardware circuit is a silicon-based circuit. Since the P-type or N-type field effect transistor used in this circuit has a single electrical characteristic, after the circuit is successfully prepared, it cannot be easily changed. Therefore, when silicon-based circuits are used to perform different logic operations, it is necessary to construct a complex circuit structure by consuming a large amount of transistor resources, which leads to problems such as low utilization of hardware resources in hardware circuits and high cost.
• the present application provides a reconfigurable logic gate circuit and a control method of the circuit to solve the above-mentioned problems existing in the prior art.
• the present application provides a reconfigurable logic gate circuit.
• the reconfigurable logic gate circuit includes: a field effect transistor and a pull-down resistor, wherein the field effect transistor includes: a source, a gate, a drain, a substrate , the source is connected to a power supply, the drain is connected to one end of the pull-down resistor, and the other end of the pull-down resistor is grounded;
• the field effect transistor is configured to switch between a first logic state and a second logic state according to the frequency of the first pulse applied to the gate, and when in the first logic state, according to the applied
• the magnitude of the DC voltage on the gate controls the field effect transistor to be in a connected state or a blocked state to control the current output by the drain, and when it is in the second logic state, according to the current applied to the
• the magnitude of the direct current voltage of the gate and the second pulse applied to the gate to control the field effect transistor to be in a connected state or a blocked state to control the current output by the drain, the first pulse, for controlling the field effect transistor in the first logic state and the Switching between the second logic states, the second pulse is used to control the correlation between the DC voltage and the current output by the drain;
• the pull-down resistor is used to block the connection between the drain and the ground when the field effect transistor is in the connected state, so that the voltage of the drain is close to the power supply voltage, and the voltage of the drain is stabilized to a high voltage. level, when the field effect transistor is in the blocking state, the drain is grounded, and the voltage of the drain is stabilized to a low level.
• controlling the field effect transistor to be in a connected state or a blocked state according to the magnitude of the DC voltage applied to the gate and the second pulse applied to the gate specifically includes:
• the field effect transistor is in a blocking state, and when applied to the gate When the DC voltage of the polarity is low level, the field effect transistor is in a connected state;
• the second pulse applied to the gate is higher than the negative voltage intensity threshold, when the DC voltage applied to the gate is low, the field effect transistor is in a connected state, and when the DC voltage applied to the gate When the DC voltage is at a high level, the field effect transistor is in a connected state.
• controlling the field effect transistor to be in a connected state or a blocked state according to the magnitude of the DC voltage applied to the gate and the second pulse applied to the gate specifically includes:
• the field effect transistor is controlled to be in a connected state or to be in a blocking state. off state.
• the DC voltage applied to the gate and the second pulse are serially input.
• the reconfigurable logic gate circuit further includes: a lower-level circuit unit, the lower-level circuit unit is composed of other field effect transistors and other pull-down resistors, the gates of the other field effect transistors are connected to the field effect transistor The drains of the other field effect transistors are connected to one end of the other pull-down resistors, and the other ends of the other pull-down resistors are grounded;
• the lower circuit unit is configured to control the other field effect transistors to be connected according to the voltage of the drain of the field effect transistor and the third pulse and the fourth pulse applied to the gates of the other field effect transistors. state or blocking state to control the drain output current of said other field effect transistors, said third pulse is used to control said other field effect transistors in said first logic state and said second logic state The fourth pulse is used to control the relationship between the DC voltage applied to the gate of the other field effect transistor and the current output by the drain of the other field effect transistor.
• the present application provides a method for controlling a circuit, the method is applied to a reconfigurable logic gate circuit, and the reconfigurable logic gate circuit includes: a field effect transistor and a pull-down resistor, wherein the field effect transistor includes: a source electrode, gate, drain, substrate, the source is connected to a power supply, the drain is connected to one end of the pull-down resistor, and the other end of the pull-down resistor is grounded, the method includes:
• the type of the logic operation instruction is the first type
• the field effect transistor is in the first logic state
• the effect of the pull-down resistor by adjusting the magnitude of the DC voltage applied to the gate, the field effect transistor is controlled to be in a connected state or a blocked state, and the current output by the drain is controlled to perform a logic operation according to the logic operation instruction ;
• the type of the logic operation instruction is the second type
• the field effect transistor is in the second logic state
• the first pulse is used to control the field effect transistor to switch between the first logic state and the second logic state
• the second pulse is used to control the DC voltage and the drain output The relationship between the currents.
• controlling the field effect transistor to be in a connected state or a blocked state by adjusting the magnitude of the DC voltage applied to the gate and the second pulse applied to the gate specifically includes:
• the DC voltage applied to the gate is adjusted to a high level, so that the field effect transistor is in a blocking state, adjusting the DC voltage applied to the gate to a low level, so that the field effect transistor is in a connected state;
• the DC voltage applied to the gate is adjusted to a low level, so that the field effect transistor is in a connected state, and the The DC voltage applied to the gate is adjusted to a high level, so that the field effect transistor is in a connected state.
• controlling the field effect transistor to be in a connected state or a blocked state by adjusting the magnitude of the DC voltage applied to the gate and the second pulse applied to the gate specifically includes:
• a bias voltage is applied to the substrate of the field effect transistor, so that under the action of the bias voltage, by adjusting the magnitude of the DC voltage applied to the gate and the second voltage applied to the gate pulse to control the field effect transistor to be in a connected state or a blocked state.
• the reconfigurable logic gate circuit further includes: a lower-level circuit unit, the lower-level circuit unit is composed of other field effect transistors and other pull-down resistors, the gates of the other field effect transistors are connected to the field effect transistor The drains of the other field effect transistors are connected to one end of the other pull-down resistors, the other end of the other pull-down resistors is grounded, and the method also includes:
• the voltage of the drain of the field effect transistor is controlled, and by controlling
• the third pulse and the fourth pulse applied to the gates of the other field effect transistors control the other field effect transistors to be in the connected state or the blocked state, and control the output of the drains of the other field effect transistors current, to perform logical operation according to the logical operation instruction;
• the third pulse is used to control the other field effect transistors to switch between the first logic state and the second logic state
• the fourth pulse is used to control the switching of the other field effect transistors The correlation between the DC voltage of the gate and the current output by the drains of the other field effect transistors.
• the present application provides an electronic device, including a memory, a processor, and a computer program stored on the memory and operable on the processor.
• the electronic device realizes the above-mentioned reconfigurable logic gate circuit or the control method of the above-mentioned circuit.
• a logic operation instruction is received, and if the type of the logic operation instruction is the first type, the field effect transistor is placed in the first logic state by changing the frequency of the first pulse applied to the gate , and under the action of the pull-down resistor, by adjusting the magnitude of the DC voltage applied to the gate, the field effect transistor is controlled to be in the connected state or blocked state, and the current output by the drain is controlled to perform logic operations according to the logic operation instructions.
• the type of logic operation instruction is the second type
• the field effect transistor is in the second logic state
• the pull-down resistor by adjusting the pulse applied to the gate
• the magnitude of the DC voltage of the electrode and the second pulse applied to the gate control the field effect transistor to be in a connected state or a blocked state, and control the current output by the drain to perform logic operations according to logic operation instructions.
• the logic state of the reconfigurable logic circuit can be changed between the first logic state and the second logic state by changing the frequency of the first pulse, the direction of the second pulse, and the magnitude of the DC voltage and other electrical operations. Switch between them, so that one logic circuit can be used as two different logic circuits, thereby improving the utilization rate of hardware resources and reducing the cost of hardware devices.
• FIG. 1 is a schematic diagram of a reconfigurable logic gate circuit provided by the present application
• Fig. 2 is the structural representation of the field effect transistor that the present application provides
• Fig. 3 is the schematic diagram of two kinds of transfer characteristics of the field effect transistor provided by the present application.
• Fig. 4 is the schematic diagram of the truth table that uses field effect transistor to carry out non-logic operation that the present application provides;
• FIG. 5 is a schematic diagram of a truth table using a field-effect transistor to perform an AND logic operation provided by the present application
• FIG. 6 is a schematic flow chart of a circuit control method provided by the present application.
• FIG. 7 is a schematic diagram of an electronic device corresponding to FIG. 1 provided in the present application.
• a reconfigurable logic gate circuit which includes: a field effect transistor and a pull-down resistor, wherein
• the field effect transistor includes: a source, a gate, a drain, and a substrate.
• the source of the field effect transistor is connected to a power supply
• the drain of the field effect transistor is connected to one end of a pull-down resistor
• the other end of the pull-down resistor is grounded.
• FIG. 1 is a schematic diagram of a reconfigurable logic gate circuit provided by the present application.
• the field effect transistor can be adjusted according to the frequency of the first pulse applied to the gate. switching between the first logic state and the second logic state. And when it is in the first logic state, the field effect transistor is controlled to be in the connected state or the blocked state according to the magnitude of the DC voltage applied to the gate. And when in the second logic state, the field effect transistor is controlled to be in the connected state or the blocked state according to the magnitude of the direct current voltage applied to the gate and the second pulse applied to the gate.
• the gate of the above-mentioned field effect transistor is composed of one metal layer and two gate dielectric layers of different materials, as shown in FIG. 2 .
• FIG. 2 is a schematic structural diagram of a field effect transistor provided by the present application.
• the field effect transistor includes: a substrate 1 , a first gate dielectric layer 2 , a second gate dielectric layer 3 , movable ions 4 , a metal layer 5 , a source 6 and a drain 7 .
• the metal layer 5 can be made of nitride metal
• the first gate dielectric layer 2 can be made of hafnium oxide HfO 2 , zirconium oxide ZrO 2 , aluminum oxide Al 2 O 3 , lanthanum oxide La 2 O 3 , yttrium oxide Y 2 O 3 , titanium oxide TiO 2 , silicon oxide SiO 2 , germanium oxide GeO 2 and other materials
• the second gate dielectric layer 3 may be made of tantalum oxide Ta 2 O 5 , titanium oxide TiO 2 and other materials.
• mobile ions 4 such as: positively charged oxygen vacancies, and negatively charged oxygen ions
• these mobile ions 4 can migrate under the action of an electric field and Dipoles are formed, thereby forming long-range polarization (Long range polarization), which can undergo polarization reversal when the electric field is reversed (that is, the positively charged end of the dipole and the negatively charged end Inversion, so that the originally positively charged end is converted to a negatively charged end).
• the concentration of carriers in the substrate 1 of the field effect transistor changes, so that the field effect transistor exhibits two transfer characteristics (that is, at the drain 7 and When the voltage across the source 6 is a variable, the functional relationship between the current of the drain 7 and the DC voltage applied to the gate), as shown in FIG. 3 .
• FIG. 3 is a schematic diagram of two kinds of transfer characteristics of the field effect transistor provided by the present application.
• the field effect transistor can be controlled to switch between the two transfer characteristics by controlling the second pulse applied to the gate, and by controlling the magnitude of the DC voltage applied to the gate of the field effect transistor, the field effect transistor can be controlled to be in the open state. state or blocked state.
• the direction of the electric field can be controlled by controlling the second pulse to be higher than the positive voltage intensity threshold and higher than the negative voltage intensity threshold. and intensity, so that the dipoles can undergo polarization reversal, so that two polarization states can be presented respectively, and then the transfer characteristics of the field effect transistor can be switched between the two transfer characteristics in Figure 2.
• the transfer characteristic of the field effect transistor is shown as the white curve in Figure 3 when the value is , and the transfer characteristic of the field effect transistor is shown as the black curve in Figure 3 when the second pulse is higher than the forward voltage strength threshold.
• the mobile ions in the second gate dielectric layer can be captured by the interface between the metal layer and the second gate dielectric layer under the action of the first pulse applied to the gate, so that the ions in the second gate dielectric layer Does not contain mobile ions, so that the field effect transistor no longer has the above two transfer characteristics.
• field effect transistors can be enabled to exhibit two different logic states. Therefore, the logic state of the field effect transistor can be switched by controlling the frequency of the first pulse applied to the gate of the field effect transistor to exceed the preset frequency or lower than the preset frequency.
• the field effect transistor can be controlled between two logic states by controlling the frequency of the first pulse applied to the gate of the field effect transistor, the direction and voltage intensity of the second pulse, and the magnitude of the DC voltage. switch, and control the connection state and blocking state of the field effect transistor.
• the DC voltage applied to the grid and the second pulse applied to the grid may be serially input.
• the field effect transistor is in the first logic state, that is, the non-logic gate state, and the field effect transistor at this time can be Used to perform non-logical operations.
• the magnitude of the DC voltage applied to the gate is the input of the logic operation
• the drain voltage of the field effect transistor is the output.
• FIG. 4 is a schematic diagram of a truth table for non-logic operations using field effect transistors provided in the present application.
• the field effect transistor at this time is in the second logic state, that is, the NAND logic gate state, and the field effect transistor at this time Can be used to perform AND and NOT logic operations.
• the field effect transistor when used for NAND logic operation, there are two input value, the first input value is the magnitude of the DC voltage applied on the gate, the second input value is the direction and voltage intensity of the second pulse applied on the gate, when the second pulse is higher than the negative voltage intensity threshold , the field effect transistor at this time is in a low threshold voltage state, and the field effect transistor at this time has the first transfer characteristic (that is, the white curve in Figure 3), so it is considered that the input value at this time is 0, when the second pulse is high At the threshold of the forward voltage intensity, the field effect transistor at this time is in a high threshold voltage state, and the field effect transistor at this time has the second transfer characteristic (that is, the black curve in Figure 3), and it is considered that the input value at this time is 1, specifically as shown in Figure 5.
• the first input value is the magnitude of the DC voltage applied on the gate
• the second input value when the second pulse is higher than the negative voltage intensity threshold , the field effect transistor at this time is in a low threshold voltage state, and the field effect transistor at this
• FIG. 5 is a schematic diagram of a truth table using field effect transistors for NAND logic operations provided by the present application.
• the corresponding input value is 0, and the field effect transistor is in the connected state at this time, so that the drain current of the field effect transistor is greater than 10 -6 A/um, then The corresponding drain voltage is high level, that is, the output value is 1.
• the polarization state of the field effect transistor at this time is a high threshold voltage state, and the corresponding input value is 1. It can be seen from the black curve in Figure 3 that when the DC voltage applied to the gate is 0.5V, the corresponding input value is also 1, and at this time the field effect transistor is in the blocking state, so that the field effect transistor If the drain current is less than 10 -9 A/um, the corresponding drain voltage is low level, that is, the output value is 0.
• the corresponding input value is 0, and the field effect transistor is in the connected state at this time, so that the drain current of the field effect transistor at this time is 10 -6 A/ um, the corresponding drain voltage is high level, that is, the output value is 1.
• NAND logic operations can be performed through the field effect transistor.
• a bias voltage can be applied to the substrate of the field effect transistor, such as: when the bias voltage of the substrate of the field effect transistor is set to -0.5V, so that The two transfer curves in 3 are shifted towards the positive gate voltage by 0.5V as a whole, so as to adjust the threshold value of the DC voltage applied to the gate under the action of the bias voltage, so that the DC voltage applied to the gate can be adjusted
• the magnitude of the voltage and the second pulse applied to the gate control the field effect transistor to be in a connected state or a blocked state.
• the pull-down resistor in the reconfigurable logic gate circuit is used to block the connection between the drain and the ground when the field effect transistor is in the connected state, so that the voltage of the drain is close to the power supply voltage, and the drain voltage is stabilized to a high level , when the field effect transistor is in a blocking state, the drain is grounded, and the drain voltage is stabilized to a low level.
• the aforementioned field effect transistor may refer to a P-channel movable ion ferroelectric field effect transistor.
• the aforementioned field effect transistor may also refer to an N-channel movable ion ferroelectric field effect transistor.
• the field effect transistor here is an N-channel movable ion-type ferroelectric field-effect transistor
• the above-mentioned reconfigurable logic circuit can be composed of an N-channel movable ion-type ferroelectric field-effect transistor and a pull-up resistor.
• the control method of the reconfigurable logic circuit composed of the movable ion ferroelectric field effect transistor and the pull-up resistor is the same as the control method of the reconfigurable logic circuit composed of the movable ion ferroelectric field effect transistor of the P channel and the pull-down resistor. The application will not be described in detail here.
• the above-mentioned reconfigurable logic gate circuit can have one input in the first logic state and can perform AND logic operation, and the above-mentioned reconfigurable logic gate circuit can have two inputs in the second logic state. Input, can carry out AND logic operation.
• the above-mentioned field effect transistor and pull-down resistor can also be used as upper-level circuit units, and then can be reconfigurable
• the method of adding lower-level circuit units composed of other field effect transistors and other pull-down resistors in the logic gate circuit enables the reconfigurable logic gate circuit to handle multi-bit logic operations, where the upper-level circuit unit and the lower-level single-way unit form a level joint structure.
• the voltage of the drain of the field effect transistor by changing the frequency of the first pulse applied to the gate of the field effect transistor, the magnitude of the second pulse, and the DC voltage, and by controlling the voltage applied to the other field effect transistor.
• the frequency of the third pulse of the gate, the fourth pulse above the positive voltage strength threshold and above the negative voltage strength threshold controls other field effect transistors to be in a connected state or a blocked state, and controls the drains of other field effect transistors
• the output current is used to perform logic operations according to logic operation instructions.
• the third pulse is used to control other FETs
• the body transistor switches between the first logic state and the second logic state
• the fourth pulse is used to control the relationship between the DC voltage applied to the gates of other field effect transistors and the current output by the drains of other field effect transistors.
• the input of the reconfigurable logic gate circuit can be increased to three or more by forming a cascaded structure of multiple circuit units, so that the reconfigurable logic gate circuit can be more complex. logic operations.
• Fig. 6 is a schematic flowchart of a method for controlling a circuit provided in the present application, including the following steps.
• S604 If the type of the logic operation instruction is the second type, by changing the frequency of the first pulse applied to the field effect transistor, the field effect transistor is in the second logic state, and the Under the action of the pull-down resistor, by adjusting the magnitude of the DC voltage applied to the gate and the second pulse applied to the gate, the field effect transistor is controlled to be in a connected state or a blocked state, and the drain is controlled.
• the current output by the poles is used to perform logic operations according to the logic operation instructions.
• the controller of the hardware device can execute the corresponding logical operation according to the received logical operation instruction. Specifically, if the type of the received logical operation instruction is the first type, by changing the The frequency of the first pulse of the gate makes the field effect transistor in the first logic state, and by adjusting the magnitude of the DC voltage applied to the gate, the field effect transistor is controlled to be in the connected state or blocked state, and the drain output is controlled The current to perform logic operations according to logic operation instructions.
• the type of the logic operation instruction received is the second type
• the field effect transistor is in the second logic state
• the magnitude of the DC voltage applied to the gate and the second pulse applied to the gate control the field effect transistor to be in a connected state or a blocked state, and control the output current of the drain to perform logic operations according to logic operation instructions.
• the execution subject used to realize the control method of the circuit may refer to a device equipped with reconfigurable logic gates
• the controller of the hardware device of the circuit may also refer to a terminal device such as a notebook computer or a desktop computer.
• the following uses the terminal device as an example to describe the method for controlling the circuit provided by this application.
• the terminal device When the terminal device adjusts the second pulse applied to the gate to be higher than the forward voltage threshold value, it can adjust the DC voltage applied to the gate to a high level, so that the field effect transistor is in a blocking state, and will be applied to the The DC voltage of the gate is at a low level, so that the field effect transistor is in a connected state;
• the terminal device can also adjust the DC voltage applied to the gate to a low level when the second pulse applied to the gate is adjusted to be higher than the negative voltage intensity threshold, so that the field effect transistor is in a connected state, and the voltage applied to the gate The DC voltage of the gate is adjusted to a high level, so that the field effect transistor is in a connected state.
• the terminal device can apply a bias voltage on the substrate of the field effect transistor, so that under the action of the bias voltage, by adjusting the magnitude of the DC voltage applied to the gate and the second pulse applied to the gate, the field effect transistor is controlled to be in connected state or blocked state.
• the above-mentioned reconfigurable logic gate circuit may include different circuit units (that is, circuit units composed of field effect transistors and pull-down resistors) to form a cascaded structure, so as to realize complex logic operations.
• the terminal device can also control the voltage of the drain of the field effect transistor by changing the frequency of the first pulse, the second pulse, and the magnitude of the DC voltage applied to the gate of the field effect transistor, and by controlling the voltage applied to the gate of the field effect transistor.
• the frequency of the third pulse and the frequency of the fourth pulse of the gate of the effect transistor control other field effect transistors to be in a connected state or a blocked state, and control the current output by the drains of other field effect transistors to perform operations according to logic operation instructions logic operation.
• the terminal device can make the logic of the reconfigurable logic circuit by adjusting the frequency of the first pulse applied to the gate of the field effect transistor, the direction of the second pulse, and adjusting the magnitude of the DC voltage.
• the state is switched between the first logic state and the second logic state, so that one logic circuit can be used as two different logic circuits, thereby improving the utilization rate of hardware resources and reducing the cost of hardware equipment.
• the present application also provides a schematic structural diagram of an electronic device shown in FIG. 7 corresponding to FIG. 1 .
• the electronic device includes a processor, an internal bus, a network interface, a memory, and a non-volatile memory, and of course may also include hardware required by other services.
• the processor reads the corresponding computer program from the non-volatile memory into the memory and then runs it, so as to realize the control method of the circuit shown in FIG. 6 above.
• this application does not exclude other implementations, such as logic devices or a combination of software and hardware, etc. That is to say, the execution subject of the following processing flow is not limited to each logic unit, and may also be hardware or logic devices.
• the improvement of a technology can be clearly distinguished as an improvement in hardware (for example, improvements in circuit structures such as diodes, transistors, and switches) or improvements in software (improvement in method flow).
• improvements in circuit structures such as diodes, transistors, and switches
• improvements in software improvement in method flow
• the improvement of many current method flows can be regarded as the direct improvement of the hardware circuit structure.
• Designers almost always get the corresponding hardware circuit structure by programming the improved method flow into the hardware circuit. Therefore, it cannot be said that the improvement of a method flow cannot be realized by hardware physical modules.
• a programmable logic device Programmable Logic Device, PLD
• PLD Programmable Logic Device
• FPGA Field Programmable Gate Array
• HDL Hardware Description Language
• ABEL Advanced Boolean Expression Language
• AHDL Altera Hardware Description Language
• HDCal JHDL
• Lava Lava
• Lola MyHDL
• PALASM RHDL
• VHDL Very-High-Speed Integrated Circuit Hardware Description Language
• Verilog Verilog
• the controller may be implemented in any suitable way, for example the controller may take the form of a microprocessor or processor and a computer readable medium storing computer readable program code (such as software or firmware) executable by the (micro)processor , logic gates, switches, Application Specific Integrated Circuit (ASIC), programmable logic controllers, and embedded microcontrollers, examples of controllers include but are not limited to the following microcontrollers: ARC 625D, Atmel AT91SAM, Microchip PIC18F26K20 and Silicone Labs C8051F320, the memory controller can also be implemented as part of the memory's control logic.
• ASIC Application Specific Integrated Circuit
• controller in addition to realizing the controller in a purely computer-readable program code mode, it is entirely possible to make the controller use logic gates, switches, application-specific integrated circuits, programmable logic controllers, and embedded The same function can be realized in the form of a microcontroller or the like. Therefore, such a controller can be regarded as a hardware component, and the devices included in it for realizing various functions can also be regarded as structures within the hardware component. or even, can Means for implementing various functions are considered to be either software modules implementing methods or structures within hardware components.
• a typical implementing device is a computer.
• the computer may be, for example, a personal computer, a laptop computer, a cellular phone, a camera phone, a smart phone, a personal digital assistant, a media player, a navigation device, an email device, a game console, a tablet computer, a wearable device, or Combinations of any of these devices.
• the embodiments of the present application may be provided as methods, systems, or computer program products. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) having computer-usable program code embodied therein.
• computer-usable storage media including but not limited to disk storage, CD-ROM, optical storage, etc.
• These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing apparatus to operate in a specific manner, such that the instructions stored in the computer-readable memory produce an article of manufacture comprising instruction means, the instructions
• the device realizes the function specified in one or more procedures of the flowchart and/or one or more blocks of the block diagram.
• a computing device includes one or more processors (CPUs), input/output interfaces, network interfaces, and memory.
• processors CPUs
• input/output interfaces network interfaces
• memory volatile and non-volatile memory
• Memory may include non-permanent storage in computer readable media, in the form of random access memory (RAM) and/or nonvolatile memory such as read-only memory (ROM) or flash RAM. Memory is an example of computer readable media.
• RAM random access memory
• ROM read-only memory
• flash RAM flash random access memory
• Computer-readable media including both permanent and non-permanent, removable and non-removable media, can be implemented by any method or technology for storage of information.
• Information may be computer readable instructions, data structures, modules of a program, or other data.
• Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read only memory (ROM), Electrically Erasable Programmable Read-Only Memory (EEPROM), Flash memory or other memory technology, Compact Disc Read-Only Memory (CD-ROM), Digital Versatile Disc (DVD) or other optical storage, Magnetic tape cartridge, tape magnetic disk storage or other magnetic storage device or any other non-transmission medium that can be used to store information that can be accessed by a computing device.
• computer-readable media excludes transitory computer-readable media, such as modulated data signals and carrier waves.
• the embodiments of the present application may be provided as methods, systems or computer program products. Accordingly, the present application can take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) having computer-usable program code embodied therein.
• a computer-usable storage media including but not limited to disk storage, CD-ROM, optical storage, etc.
• program modules include routines, programs, objects, components, data structures, etc. that perform particular tasks or implement particular abstract data types.
• the application may also be practiced in distributed computing environments where tasks are performed by remote processing devices that are linked through a communications network.
• program modules may be located in both local and remote computer storage media including storage devices.
• each embodiment in the present application is described in a progressive manner, the same and similar parts of each embodiment can be referred to each other, and each embodiment focuses on the differences from other embodiments.
• the description is relatively simple, and for relevant parts, refer to part of the description of the method embodiment.

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• 2022
  • 2022-11-03 CN CN202211366929.7A patent/CN115425965B/zh active Active
• 2023
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