WO2023155473A1 - 钝化接触电池及其制备工艺 - Google Patents

钝化接触电池及其制备工艺 Download PDF

Info

Publication number
WO2023155473A1
WO2023155473A1 PCT/CN2022/127747 CN2022127747W WO2023155473A1 WO 2023155473 A1 WO2023155473 A1 WO 2023155473A1 CN 2022127747 W CN2022127747 W CN 2022127747W WO 2023155473 A1 WO2023155473 A1 WO 2023155473A1
Authority
WO
WIPO (PCT)
Prior art keywords
silicon carbide
carbide layer
phosphorus
preparation process
layer
Prior art date
Application number
PCT/CN2022/127747
Other languages
English (en)
French (fr)
Inventor
陈浩
徐文州
孟夏杰
姚骞
王秀鹏
邢国强
Original Assignee
通威太阳能(眉山)有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 通威太阳能(眉山)有限公司 filed Critical 通威太阳能(眉山)有限公司
Priority to EP22926777.8A priority Critical patent/EP4345920A1/en
Priority to AU2022441542A priority patent/AU2022441542A1/en
Publication of WO2023155473A1 publication Critical patent/WO2023155473A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H01L31/1804—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof comprising only elements of Group IV of the Periodic Table
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0216—Coatings
    • H01L31/02161—Coatings for devices characterised by at least one potential jump barrier or surface barrier
    • H01L31/02167—Coatings for devices characterised by at least one potential jump barrier or surface barrier for solar cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers
    • H01L31/068—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN homojunction type, e.g. bulk silicon PN homojunction solar cells or thin film polycrystalline silicon PN homojunction solar cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H01L31/186—Particular post-treatment for the devices, e.g. annealing, impurity gettering, short-circuit elimination, recrystallisation
    • H01L31/1864—Annealing
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/547—Monocrystalline silicon PV cells
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Definitions

  • the present application relates to the field of solar cells, in particular to a passivated contact cell and a preparation process thereof.
  • doped oxide layer passivated contact cells can significantly improve the photoelectric conversion efficiency of solar cells, and currently occupy a certain market share and have extremely high industrialization value.
  • the key part of doped oxide layer passivation contact cell technology is to first grow a tunnel oxide layer SiOx with a thickness of about 1.4nm on the back of the cell, and then deposit phosphorus-doped n+-poly-Si (heavily doped polysilicon ) film, after high temperature annealing, can effectively reduce the rear recombination current density.
  • LPCVD low-pressure chemical vapor deposition
  • ion implantation or phosphorus diffusion to dope the film to form phosphorus-doped polysilicon
  • tube PECVD Pasma Enhanced Chemical Vapor Deposition
  • the heavily doped polysilicon on the back has weak resistance to silver paste corrosion during the screen printing process, and is easily pierced by metals to increase metal recombination, resulting in a decrease in photoelectric conversion efficiency.
  • This application provides a passivated contact battery and its preparation process, which can significantly improve the serious problem of film explosion of the back field passivation structure obtained by PECVD deposition; it can also improve the corrosion resistance of the silver paste on the back, thereby reducing the metal piercing phenomenon, Reduce metal cladding.
  • Some embodiments of the present application provide a process for preparing a passivated contact cell, and the preparation of the back field passivation structure may include:
  • an intrinsic silicon carbide layer and a phosphorus-doped silicon carbide layer are sequentially grown on the surface of the tunnel oxide layer, instead of the traditional polysilicon structure.
  • the problem of film explosion can be significantly improved, which is conducive to enhancing the passivation performance of the battery, and is conducive to improving Voc (open circuit voltage) and battery efficiency.
  • SiC x has higher hardness than Poly-Si, it can improve the corrosion resistance of silver paste on the back during the sintering process after screen printing, thereby reducing metal piercing and metal recombination, which is also conducive to making Voc and improved battery efficiency.
  • SiC x Compared with Poly-Si, SiC x has a more stable CH bond, which makes the hydrogen content in SiC x higher, and also increases the interface H content, which is beneficial to improve the passivation performance of the battery.
  • the optical bandgap of SiC is wider than that of polysilicon, which can reduce infrared parasitic absorption, help to increase current density, and effectively improve battery efficiency and double-sided rate.
  • the intrinsic silicon carbide layer is spaced between the tunnel oxide layer and the phosphorus-doped silicon carbide layer. As a buffer structure, it can also prevent phosphorus from entering the bulk silicon through the tunnel oxide layer when forming the phosphorus-doped silicon carbide layer, and can Effectively avoid the impact on the open circuit voltage of the battery.
  • the thickness of the intrinsic silicon carbide layer may be 5-80 nm
  • the thickness of the intrinsic silicon carbide layer may be 5-50 nm;
  • the thickness of the intrinsic silicon carbide layer may be 20-30 nm.
  • the intrinsic silicon carbide layer has an appropriate thickness, which can better play the role of passivation and buffering, and is beneficial to better realize the improvement of Voc, Isc and battery efficiency.
  • the thickness of the phosphorus-doped silicon carbide layer may be 20-200 nm;
  • the phosphorus-doped silicon carbide layer may have a thickness of 100-150 nm.
  • the phosphorus-doped silicon carbide layer has an appropriate thickness, which can better play the role of passivation and anti-slurry corrosion and penetration, and is conducive to better realizing the improvement of Voc, Isc and battery efficiency.
  • the total thickness of the intrinsic silicon carbide layer and the phosphorus-doped silicon carbide layer is ⁇ 200 nm.
  • the total thickness of the intrinsic silicon carbide layer and the phosphorus-doped silicon carbide layer is controlled within a certain standard, while effectively improving Voc, Isc, and battery efficiency, and better taking into account the overall performance of the battery.
  • the intrinsic silicon carbide layer in the step of growing the intrinsic silicon carbide layer, may be deposited by plasma enhanced chemical vapor deposition;
  • the phosphorus-doped silicon carbide layer may be deposited by plasma enhanced chemical vapor deposition.
  • the plasma-enhanced chemical vapor deposition method is adopted, so that the surrounding plating is less, which is beneficial to the control of the appearance and yield of the battery.
  • CH 4 , SiH 4 and H 2 are introduced for reactive deposition; wherein, the volume ratio of CH 4 and SiH 4 is 1:(1 ⁇ 10 ).
  • CH 4 and SiH 4 have an appropriate volume ratio, which is beneficial for the intrinsic silicon carbide layer to better play the role of passivation and buffering.
  • CH 4 , SiH 4 , PH 3 and H 2 are introduced for reactive deposition; wherein, the volume ratio of CH 4 and SiH 4 is 1: (1 ⁇ 10).
  • CH 4 and SiH 4 have an appropriate volume ratio, which is beneficial for the phosphorus-doped silicon carbide layer to better play the role of passivation, reducing infrared absorption and preventing slurry corrosion and penetration.
  • the annealing temperature may be 600-1000° C., and the annealing time may be 10-60 minutes;
  • the annealing temperature may be 900-940°C.
  • the annealing treatment is carried out with appropriate annealing conditions to ensure better crystallization and effective phosphorus doping of the back field passivation structure, which is conducive to better realizing the improvement of Voc, Isc and battery efficiency.
  • the step of growing the phosphorus-doped silicon carbide layer and before the annealing step may further include: growing a SiO x mask layer on the surface of the phosphorus-doped silicon carbide layer.
  • PECVD may be used to feed SiH 4 and N 2 O to deposit the SiO x mask layer,
  • the thickness of the SiO x mask layer is 10-50 nm.
  • the annealing treatment may be performed using a tube annealing furnace, and the annealing gas atmosphere is nitrogen (N 2 ) or oxygen (O 2 ).
  • the preparation process may also include RCA cleaning, in which, chain hydrofluoric acid (HF) is first used to remove oxidation from the surrounding plating to the front side in each step of preparation of the back field passivation structure. layer and the oxide layer formed during the annealing process, and then transferred to the alkali tank to remove the front silicon carbide coating.
  • RCA cleaning in which, chain hydrofluoric acid (HF) is first used to remove oxidation from the surrounding plating to the front side in each step of preparation of the back field passivation structure. layer and the oxide layer formed during the annealing process, and then transferred to the alkali tank to remove the front silicon carbide coating.
  • HF chain hydrofluoric acid
  • the preparation process may also include deposition of an aluminum oxide film and a silicon nitride film on the front side, wherein the aluminum oxide (AlO x ) film deposited by plasma-enhanced atomic layer deposition or PECVD is used For passivation, PECVD is used to deposit silicon nitride (SiN x ) films for anti-reflection.
  • AlO x aluminum oxide
  • PECVD plasma-enhanced atomic layer deposition
  • SiN x silicon nitride
  • the preparation process may also include depositing a silicon nitride film on the back side, wherein a SiN x film is deposited by PECVD for hydrogen passivation of the back film.
  • PEALD or PECVD may be used to form a tunnel oxide layer with a thickness of 0.5-2 nm.
  • the SiO x mask layer is used to protect the back field passivation structure, which can effectively prevent the back field passivation structure from being damaged in subsequent dewinding, plating, cleaning and other processes.
  • a passivation contact cell which may include: a silicon wafer, and a tunnel oxide layer, an intrinsic silicon carbide layer, and a phosphorus-doped silicon carbide layer sequentially stacked on the back of the silicon wafer.
  • the passivated contact cell can be manufactured through the preparation process provided in some embodiments of the present application.
  • FIG. 1 is a schematic structural diagram of a passivated contact battery provided in an embodiment of the present application.
  • Icon 100-passivation contact cell; 110-front anti-reflection layer; 120-front passivation layer; 130-front P-type doped layer; 140-silicon wafer; 150-tunneling oxide layer; 160-intrinsic silicon carbide layer; 170—phosphorous doped silicon carbide layer; 180—backside passivation layer.
  • the range of “value a to value b" includes the values “a” and “b” at both ends, and the “measurement unit” in “value a to value b+measurement unit” A "unit of measure” representing both "value a" and “value b”.
  • the heavily doped polysilicon has weak resistance to silver paste corrosion during the screen printing process, and is easily pierced by metals to increase metal recombination, resulting in a decrease in photoelectric conversion efficiency.
  • SiC x has higher hardness than poly-Si, which can improve the corrosion resistance of silver paste on the back side during the sintering process of annealing treatment, thereby reducing metal piercing and metal recombination.
  • some embodiments of the present application provide a process for preparing a passivated contact cell, and the preparation of the rear field passivation structure may include:
  • an intrinsic silicon carbide layer and a phosphorus-doped silicon carbide layer are sequentially grown on the surface of the tunnel oxide layer, instead of the traditional polysilicon structure.
  • the preparation process of the passivated contact cell provided by the application has at least the following effects:
  • SiC x has higher hardness, which can improve the corrosion resistance of silver paste on the back during the sintering process of annealing treatment, thereby reducing metal piercing and metal compounding, which is also conducive to making Voc and Battery efficiency is improved.
  • SiC x has a more stable CH bond, which makes the hydrogen content in SiC x higher, and also increases the interface H content, which is beneficial to improve the passivation performance of the battery.
  • optical band gap of SiC is wider than that of polysilicon, which can reduce infrared parasitic absorption, help to increase current density, and effectively improve battery efficiency and double-sided rate.
  • the inventors have found that while using SiCx instead of poly-Si, the intrinsic silicon carbide layer is separated between the tunnel oxide layer and the phosphorus-doped silicon carbide layer In between, using the intrinsic silicon carbide layer as a buffer structure can also prevent phosphorus from entering the bulk silicon through the tunnel oxide layer when forming the phosphorus-doped silicon carbide layer, and can effectively avoid affecting the open circuit voltage of the battery.
  • the above mainly shows the preparation process of the rear field passivation structure.
  • texturing, p-n junction fabrication, dewinding plating, and mask formation can also be performed according to needs or in a conventional manner.
  • the preparation process of passivated contact cells may include:
  • Texturing Exemplarily, an N-type silicon wafer is prepared, 1% alkali solution is used for texturing, and hydrogen peroxide and alkali are used to clean the silicon wafer.
  • Boron expansion Exemplarily, enter a boron diffusion furnace, use BCl 3 to diffuse at 900-1050° C. to form a pn junction.
  • Alkali cast Exemplarily, a chain-type HF machine is used to remove boron-extended BSG (borosilicate glass) on the back, and then transferred to a slot-type alkali polishing machine by a robot to remove the back and edge p-n junctions.
  • BSG borosilicate glass
  • a tunnel oxide layer is grown on the backside of the silicon wafer.
  • An intrinsic silicon carbide layer is grown on the surface of the tunnel oxide layer.
  • a phosphorus-doped silicon carbide layer is grown on the surface of the intrinsic silicon carbide layer.
  • Annealing treatment exemplary, a tubular annealing furnace is used, and the annealing gas atmosphere is nitrogen (N 2 ) or oxygen (O 2 ).
  • the chain hydrofluoric acid (HF) is first used to remove the oxide layer plated to the front side and the oxide layer formed during the annealing process in each step of the preparation of the rear field passivation structure, and then transferred to an alkali bath to remove the front side Silicon carbide wrap around coating.
  • HF chain hydrofluoric acid
  • Aluminum oxide film and silicon nitride film deposition on the front side Exemplarily, an aluminum oxide (AlO x ) film deposited by PEALD (Plasma Enhanced Atomic Layer Deposition) or PECVD is used for passivation, and a silicon nitride (SiN x ) film is deposited by PECVD for antireflection.
  • PEALD Pullasma Enhanced Atomic Layer Deposition
  • SiN x silicon nitride
  • a SiN x thin film is deposited by PECVD for hydrogen passivation of the back film.
  • the front and back pastes are screen printed.
  • PEALD or PECVD is used to generate a tunnel oxide layer with a thickness of 0.5-2 nm.
  • PECVD is used to deposit an intrinsic silicon carbide layer.
  • the plasma-enhanced chemical vapor deposition method is used to reduce the surrounding plating, which is beneficial to the control of the appearance and yield of the battery.
  • CH 4 , SiH 4 and H 2 for reactive deposition; wherein, the volume ratio of CH 4 and SiH 4 is 1: (1-10), for example but not limited to 1:1, 1:2, 1:3, 1:4, 1:5, 1:6, 1:7, 1:8, 1:9 and 1:10 or any two range of values between.
  • CH 4 and SiH 4 have an appropriate volume ratio, which is beneficial for the intrinsic silicon carbide layer to better play the role of passivation and buffer.
  • the thickness of the intrinsic silicon carbide layer is 5-80 nm; optionally, the thickness of the intrinsic silicon carbide layer is 5-50 nm; optionally, the thickness of the intrinsic silicon carbide layer is 20-30 nm.
  • the thickness of the intrinsic silicon carbide layer is, for example but not limited to, any one of 5nm, 10nm, 20nm, 25nm, 30nm, 40nm, 50nm and 80nm or a range between any two. Since the intrinsic silicon carbide layer has an appropriate thickness, it can better play the roles of passivation, infrared absorption reduction and buffering, which is beneficial to better realize the improvement of Voc, Isc and battery efficiency.
  • a phosphorous-doped silicon carbide layer is deposited using PECVD.
  • the plasma-enhanced chemical vapor deposition method is used to reduce the surrounding plating, which is beneficial to the control of the appearance and yield of the battery.
  • CH 4 , SiH 4 , PH 3 and H 2 are introduced into the reaction deposition; wherein, the volume ratio of CH 4 and SiH 4 is 1: (1-10), For example but not limited to any one of 1:1, 1:2, 1:3, 1:4, 1:5, 1:6, 1:7, 1:8, 1:9 and 1:10 or Any range value in between.
  • CH 4 and SiH 4 have an appropriate volume ratio, which is beneficial for the phosphorus-doped silicon carbide layer to play a better role in passivation and anti-slurry corrosion penetration.
  • the phosphorus-doped silicon carbide layer has a thickness of 20-200 nm; optionally, the phosphorus-doped silicon carbide layer has a thickness of 100-150 nm.
  • the thickness of the phosphorus-doped silicon carbide layer is, for example but not limited to, any one of 20nm, 50nm, 80nm, 100nm, 120nm, 150nm and 200nm or a range between any two. Since the phosphorus-doped silicon carbide layer has an appropriate thickness, it can better play the role of passivation and anti-slurry corrosion penetration, which is conducive to better realizing the improvement of Voc, Isc and battery efficiency.
  • the total thickness of the intrinsic silicon carbide layer and the phosphorus-doped silicon carbide layer ⁇ thickness ⁇ total.
  • the total thickness of the intrinsic silicon carbide layer and the phosphorus-doped silicon carbide layer is controlled within a certain standard, which can effectively improve the Voc and battery efficiency while taking into account the overall performance of the battery.
  • the method further includes: growing a SiO x mask layer on the surface of the phosphorus-doped silicon carbide layer.
  • PECVD is used to feed SiH 4 and N 2 O to deposit a SiO x mask layer.
  • the thickness of the SiO x mask layer is 10-50 nm, such as but not limited to 10 nm, 20 nm, 30 nm, 40 nm or 50nm.
  • the SiO x mask layer is used to protect the back field passivation structure, which can effectively prevent the back field passivation structure from being damaged in subsequent dewinding, plating, cleaning and other processes.
  • the multiple films Layers can be deposited in the same tube at one time without breaking the vacuum.
  • PVD plasma enhanced physical vapor deposition
  • CVD chemical vapor deposition
  • MOCVD metal organic compound Chemical vapor deposition
  • the annealing temperature is 600 to 1000 steps, optionally, the annealing temperature is 900 to 9400 degrees, the annealing temperature is for example but not limited to 600°C, 700°C, 800°C, 900°C, 910°C, 920°C , any one of 930°C, 940°C, 950°C and 1000°C or the range between any two.
  • the annealing time is 10-60 min, and the annealing time is, for example but not limited to, any one of 10 min, 20 min, 30 min, 40 min, 50 min and 60 min or a range between any two.
  • the annealing treatment is carried out by adopting appropriate annealing conditions to ensure better crystallization and effective phosphorus doping of the back field passivation structure, so that the phosphorus in the phosphorus-doped silicon carbide layer can better form a common layer with silicon carbide.
  • the valence bond can better provide electrons to form a passivation structure, which is beneficial to better realize the improvement of Voc and battery efficiency.
  • FIG. 1 other embodiments of the present application provide a passivated contact cell 100 , which can be manufactured through the preparation process provided in some embodiments of the present application.
  • the passivation contact cell 100 may include a silicon wafer 140 , and a tunnel oxide layer 150 , an intrinsic silicon carbide layer 160 and a phosphorus-doped silicon carbide layer 170 are sequentially stacked on the backside of the silicon wafer 140 .
  • the above mainly shows the structure corresponding to the rear field passivation structure, and in the passivated contact cell, other anti-reflection layers, passivation layers, electrodes, etc. can also be configured according to functional requirements and cell design.
  • the passivated contact cell 100 may include a front antireflection layer 110 , a front passivation layer 120 , a front P-type doped layer 130 , and an N-type silicon wafer 140 arranged in sequence. , a tunnel oxide layer 150 , an intrinsic silicon carbide layer 160 , a phosphorus-doped silicon carbide layer 170 and a rear passivation layer 180 .
  • the front anti-reflection layer 110 may be a SiN x anti-reflection layer
  • the front passivation layer 120 may be an AlO x passivation layer
  • the back passivation layer 180 may be a SiN x passivation layer.
  • a preparation process for a passivated contact cell may include:
  • Alkali polishing Use a chain-type HF machine to remove the BSG with boron expansion on the back, and then transfer it to a trough-type alkali polishing machine by a robot to remove the p-n junctions on the back and edges.
  • Phosphorus-doped silicon carbide layer grown on the surface of the intrinsic silicon carbide layer using PECVD, feed CH 4 , SiH 4 , PH 3 and H 2 for reaction deposition; wherein, the volume ratio of CH 4 and SiH 4 is 1 : 10, the thickness of the phosphorus-doped silicon carbide layer is 100nm.
  • Annealing treatment a tubular annealing furnace is used, the annealing gas atmosphere is nitrogen, the annealing temperature is 900° C., and the annealing time is 20 minutes.
  • RCA cleaning first go through chain hydrofluoric acid (HF) to remove the oxide layer plated to the front side in steps S4 ⁇ S7 and the oxide layer formed during the annealing process in step S8, and then transfer to alkali tank to remove silicon carbide on the front side Coating around.
  • HF hydrofluoric acid
  • S12 making electrodes.
  • the front and back pastes are screen printed.
  • a preparation process of a passivated contact cell which differs from Example 1 only in that:
  • step S5 the volume ratio of CH 4 and SiH 4 is 1:5.
  • a preparation process of a passivated contact cell which differs from Example 1 only in that:
  • step S5 the thickness of the intrinsic silicon carbide layer is 5 nm.
  • a preparation process of a passivated contact cell which differs from Example 1 only in that:
  • step S5 the thickness of the intrinsic silicon carbide layer is 80 nm.
  • a preparation process of a passivated contact cell which differs from Example 1 only in that:
  • step S6 the phosphorus-doped silicon carbide layer has a thickness of 20 nm.
  • a preparation process of a passivated contact cell which differs from Example 1 only in that:
  • step S6 the phosphorus-doped silicon carbide layer has a thickness of 200 nm.
  • a preparation process of a passivated contact cell which differs from Example 1 only in that:
  • step S8 the annealing temperature is 940°C.
  • a preparation process for a passivated contact cell which is a conventional polysilicon process, differs from Example 1 in that it deposits an n+-poly-Si film instead of depositing an intrinsic silicon carbide layer and a phosphorus-doped silicon carbide layer. specifically:
  • Steps S4-S7 are replaced by: use LPCVD equipment to grow the tunnel oxide layer and intrinsic polysilicon, feed oxygen to grow the tunnel oxide layer with a film thickness of 1nm; shut off oxygen, feed silane, and grow 130nm intrinsic polysilicon.
  • Step S8 is replaced by: changing to adopting a tube-type diffusion furnace, passing in phosphine, and performing phosphorus doping.
  • the Voc is increased by 2.3mV
  • the Isc is increased by 60mA
  • the photoelectric conversion efficiency of the cell is increased by 0.15%
  • the overall electrical performance of the cell is greatly improved.
  • the Voc is increased by 2.9mV
  • the Isc is increased by 50mA
  • the photoelectric conversion efficiency of the cell is increased by 0.11%
  • the overall electrical performance of the cell is greatly improved.
  • the thickness of the intrinsic silicon carbide layer is small, and compared with the traditional polysilicon process, the Isc is increased by 60 mA, and the photoelectric conversion efficiency of the cell is equivalent.
  • the thickness of the intrinsic silicon carbide layer is relatively large. Compared with the traditional polysilicon process, the Isc is increased by 50mA, the Voc is increased by 0.9mV, and the photoelectric conversion efficiency of the cell is equivalent.
  • the thickness of the phosphorus-doped silicon carbide layer is small. Compared with the traditional polysilicon process, the Isc is increased by 120mA, and the photoelectric conversion efficiency of the cell is equivalent.
  • the thickness of the phosphorus-doped silicon carbide layer is relatively large. Compared with the traditional polysilicon process, Voc is increased by 3.9mV, FF is increased by 0.17%, and the photoelectric conversion efficiency of the cell is equivalent.
  • Voc is increased by 1.5mV
  • Isc is increased by 60mA
  • FF is increased by 0.11%
  • the photoelectric conversion efficiency of the cell is increased by 0.16%
  • the overall electrical performance of the cell is relatively high. improvement.
  • the application provides a passivated contact cell and a preparation process thereof, belonging to the field of solar cells.
  • the preparation process of the passivated contact cell, the preparation of the back field passivation structure includes: growing a tunnel oxide layer on the back of the silicon wafer; growing an intrinsic silicon carbide layer on the surface of the tunnel oxide layer; growing an intrinsic silicon carbide layer on the surface of the intrinsic silicon carbide layer growing a phosphorus-doped silicon carbide layer; and annealing to cause phosphorus in the phosphorus-doped silicon carbide layer to form covalent bonds with the silicon carbide.
  • the passivated contact cell can be manufactured through the above-mentioned preparation process, which includes a silicon wafer, and a tunnel oxide layer, an intrinsic silicon carbide layer and a phosphorus-doped silicon carbide layer sequentially stacked on the back of the silicon wafer.
  • the preparation process and the battery can effectively alleviate the serious problem of film bursting of the back field passivation structure obtained by PECVD deposition; it can also improve the anti-corrosion ability of the silver paste on the back side, thereby reducing the phenomenon of metal piercing and metal recombination. .
  • the passivated contact cell of the present application and its fabrication process are reproducible and can be used in various industrial applications.
  • the passivated contact cell and its preparation process of the present application can be used in the field of solar cells.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Life Sciences & Earth Sciences (AREA)
  • Manufacturing & Machinery (AREA)
  • Sustainable Development (AREA)
  • Sustainable Energy (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Formation Of Insulating Films (AREA)
  • Photovoltaic Devices (AREA)

Abstract

一种钝化接触电池及其制备工艺，属于太阳能电池领域。钝化接触电池的制备工艺，其背面场钝化结构的制备包括：在硅片的背面生长隧穿氧化层；在隧穿氧化层的表面生长本征碳化硅层；在本征碳化硅层表面生长磷掺杂碳化硅层；以及退火处理，以使磷掺杂碳化硅层中的磷与碳化硅形成共价键。钝化接触电池能够通过上述制备工艺制得，其包括硅片，以及在所述硅片的背面依次层叠的隧穿氧化层、本征碳化硅层和磷掺杂碳化硅层。该制备工艺和电池能有效缓解PECVD沉积得到的背面场钝化结构爆膜严重的问题；还能提高背面耐银浆腐蚀能力，从而减少金属刺穿现象，降低金属复合。

Description

钝化接触电池及其制备工艺
相关申请的交叉引用
本申请要求于2022年02月16日提交中国国家知识产权局的申请号为202210141493.5、名称为“钝化接触电池及其制备工艺”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及太阳能电池领域，具体而言，涉及一种钝化接触电池及其制备工艺。
背景技术
相较于其他传统的太阳能电池，掺杂氧化层钝化接触电池可以明显提高太阳能电池的光电转换效率，在目前已经占有一定的市场份额，具有极高的产业化价值。
目前，掺杂氧化层钝化接触电池技术关键部分是，首先在电池背面生长一层厚度约1.4nm的隧穿氧化层SiO x，然后沉积磷掺杂的n+-poly-Si(重掺杂多晶硅)薄膜，经过高温退火后，能够有效地降低背面复合电流密度。
掺杂氧化层钝化接触电池在大规模量产的过程中，主要的技术路线主要有如下两种：
一种是采用低压化学气相沉积法(LPCVD)沉积隧穿氧化层和非晶硅薄膜，然后采用离子注入或磷扩散的方式对薄膜进行掺杂形成磷掺杂的多晶硅；另外一种是基于管式PECVD(等离子体增强化学气相沉积法)沉积技术，由于其绕镀更少，有利于外观和良率的控制，具有更高的量产优势。
但是，一方面，在PECVD沉积poly-Si过程以及后续的高温退火过程中，存在严重的爆膜问题，导致电池光电转换效率降低。
另一方面，背面的重掺杂多晶硅在丝网印刷过程中的耐银浆腐蚀能力较弱，容易被金属刺穿从而增加金属复合，导致光电转换效率降低。
发明内容
本申请提供了一种钝化接触电池及其制备工艺，能明显改善PECVD沉积得到的背面场钝化结构爆膜严重的问题；还能提高背面耐银浆腐蚀能力，从而减少金属刺穿现象，降低金属复合。
本申请的实施例是这样实现的：
本申请的一些实施例提供了一种钝化接触电池的制备工艺，其背面场钝化结构的制备 可以包括：
在硅片的背面生长隧穿氧化层；
在隧穿氧化层的表面生长本征碳化硅层；
在本征碳化硅层表面生长磷掺杂碳化硅层；以及
退火处理，以使磷掺杂碳化硅层中的磷与碳化硅形成共价键。
上述技术方案中，在背面场结构中，在隧穿氧化层的表面依次生长本征碳化硅层和磷掺杂碳化硅层，代替传统的多晶硅结构。在PECVD沉积工艺中，能明显改善爆膜的问题，有利于增强电池的钝化性能，并有利于使得Voc(开路电压)和电池效率得到提升。由于SiC x相较于Poly-Si具有更高的硬度，在丝网印刷后的烧结过程中能提高背面耐银浆腐蚀能力，从而减少金属刺穿现象，降低金属复合，同样地有利于使得Voc和电池效率得到提升。
其中，SiC x相较于Poly-Si而言，C-H键更加稳定，使SiC x中的氢含量更高，也增加了界面H含量，有利于提升电池的钝化性能。SiC的光学带隙比多晶硅更宽，能降低红外寄生吸收，有利于提升电流密度，还能有效提升电池效率和双面率。
本征碳化硅层间隔在隧穿氧化层和磷掺杂碳化硅层之间，作为缓冲结构，还能阻挡形成磷掺杂碳化硅层时的磷穿过隧穿氧化层进入体硅中，能有效避免对电池的开路电压等造成影响。
在一些可选的实施方案中，本征碳化硅层的厚度可以为5～80nm；
可选地，本征碳化硅层的厚度可以为5～50nm；
可选地，本征碳化硅层的厚度可以为20～30nm。
上述技术方案中，本征碳化硅层具有合适的厚度，能较好地发挥钝化和缓冲的作用，有利于更好地实现Voc、Isc和电池效率的提升。
在一些可选的实施方案中，磷掺杂碳化硅层的厚度可以为20～200nm；
可选地，磷掺杂碳化硅层的厚度可以为100～150nm。
上述技术方案中，磷掺杂碳化硅层具有合适的厚度，能较好地发挥钝化和防浆料腐蚀刺穿的作用，有利于更好地实现Voc、Isc和电池效率的提升。
在一些可选的实施方案中，本征碳化硅层和磷掺杂碳化硅层的总厚度≤200nm。
上述技术方案中，本征碳化硅层和磷掺杂碳化硅层的总厚度控制在一定的标准内，在有效提升Voc、Isc和电池效率的同时，较好地兼顾电池的整体性能。
在一些可选的实施方案中，生长本征碳化硅层的步骤中，可以采用等离子体增强化学气相沉积法沉积本征碳化硅层；
和/或，生长磷掺杂碳化硅层的步骤中，可以采用等离子体增强化学气相沉积法沉积磷掺杂碳化硅层。
上述技术方案中，采用等离子体增强化学气相沉积法，使得绕镀较少，有利于电池外观和良率的控制。
在一些可选的实施方案中，生长本征碳化硅层的步骤中，通入CH 4、SiH 4和H 2进行反应沉积；其中，CH 4和SiH 4的体积比为1：(1～10)。
上述技术方案中，CH 4和SiH 4具有合适的体积比，有利于本征碳化硅层较好地发挥钝化和缓冲的作用。
在一些可选的实施方案中，生长磷掺杂碳化硅层的步骤中，通入CH 4、SiH 4、PH 3和H 2进行反应沉积；其中，CH 4和SiH 4的体积比为1：(1～10)。
上述技术方案中，CH 4和SiH 4具有合适的体积比，有利于磷掺杂碳化硅层较好地发挥钝化、减少红外吸收和防浆料腐蚀刺穿的作用。
在一些可选的实施方案中，退火处理步骤中，退火温度可以为600～1000℃，退火时间可以为10～60min；
可选地，退火温度可以为900～940℃。
上述技术方案中，采用合适的退火条件进行退火处理，保证较好地对背面场钝化结构进行晶化和有效掺磷，有利于更好地实现Voc、Isc和电池效率的提升。
在一些可选的实施方案中，在生长磷掺杂碳化硅层的步骤之后，且在退火处理步骤之前，还可以包括：在磷掺杂碳化硅层的表面生长SiO x掩膜层。
在一些可选的实施方案中，在磷掺杂碳化硅层的表面生长SiO x掩膜层的步骤中，可以采用PECVD方式，通入SiH 4和N 2O，以沉积SiO x掩膜层，所述SiO x掩膜层的厚度为10～50nm。
在一些可选的实施方案中，可以采用管式退火炉进行所述退火处理，退火气体氛围为氮气(N 2)或氧气(O 2)。
在一些可选的实施方案中，所述制备工艺还可以包括RCA清洗，其中，先经过链式氢氟酸(HF)，去除背面场钝化结构的制备的各步骤中绕镀到正面的氧化层以及退火过程中生成的氧化层，随后转入碱槽去除正面碳化硅绕镀层。
在一些可选的实施方案中，所述制备工艺还可以包括正面氧化铝膜和氮化硅膜沉积，其中，采用等离子体增强原子层沉积方式或PECVD方式沉积的氧化铝(AlO x)薄膜用于钝化，采用PECVD沉积氮化硅(SiN x)薄膜用于减反射。
在一些可选的实施方案中，所述制备工艺还可以包括沉积背面氮化硅膜，其中，采用PECVD沉积SiN x薄膜，用于背膜氢钝化。
在一些可选的实施方案中，在生长隧穿氧化层的步骤中，可以采用PEALD或PECVD方式，生成一层厚度为0.5～2nm的隧穿氧化层。
上述技术方案中，SiO x掩膜层用于保护背面场钝化结构，能够有效避免背面场钝化结 构在后续的去绕镀清洗等工艺中被破坏。
本申请的另一些实施例提供了一种钝化接触电池，可以包括：硅片，以及在硅片的背面依次层叠的隧穿氧化层、本征碳化硅层和磷掺杂碳化硅层。
上述技术方案中，该钝化接触电池能够通过本申请的一些实施方式提供的制备工艺制得。
附图说明
为了更清楚地说明本申请实施例的技术方案，下面将对实施例中所需要使用的附图作简单地介绍，应当理解，以下附图仅示出了本申请的某些实施例，因此不应被看作是对范围的限定，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他相关的附图。
图1为本申请实施例提供的一种钝化接触电池的结构示意图。
图标：100-钝化接触电池；110-正面减反射层；120-正面钝化层；130-正面P型掺杂层；140-硅片；150-隧穿氧化层；160-本征碳化硅层；170-磷掺杂碳化硅层；180-背面钝化层。
具体实施方式
为使本申请实施例的目的、技术方案和优点更加清楚，下面将对本申请实施例中的技术方案进行清楚、完整地描述。实施例中未注明具体条件者，按照常规条件或制造商建议的条件进行。所用试剂或仪器未注明生产厂商者，均为可以通过市售购买获得的常规产品。
需要说明的是，本申请中的“和/或”，如“特征1和/或特征2”，均是指可以单独地为“特征1”、单独地为“特征2”、“特征1”加“特征2”，该三种情况。
另外，在本申请的描述中，除非另有说明，“数值a～数值b”的范围包括两端值“a”和“b”，“数值a～数值b+计量单位”中的“计量单位”代表“数值a”和“数值b”二者的“计量单位”。
下面对本申请实施例的钝化接触电池的制备工艺及钝化接触电池进行具体说明。
发明人研究发现，目前，在生产常规的多晶硅形式的掺杂氧化层钝化接触电池时，在PECVD沉积poly-Si的过程中以及后续的高温退火过程中，poly-Si中的氢会被释放出来，并导致poly-Si膜层被破坏，从而产生爆膜现象，而poly-Si爆膜会严重影响电池的钝化性能，并导致电池光电转换效率降低。而且，重掺杂多晶硅在丝网印刷过程中的耐银浆腐蚀能力较弱，容易被金属刺穿从而增加金属复合，导致光电转换效率降低。
进一步研究发现，相比起PECVD沉积poly-Si，SiC x中的H很难逃逸，在PECVD沉积工艺中，能有效缓解爆膜的问题。而且，SiC x相较于poly-Si具有更高的硬度，在退火处理的烧结过程中能提高背面耐银浆腐蚀能力，从而减少金属刺穿现象，降低金属复合。
基于上述研究发现，本申请的一些实施方式提供了一种钝化接触电池的制备工艺，其背面场钝化结构的制备可以包括：
在硅片的背面生长隧穿氧化层；
在隧穿氧化层的表面生长本征碳化硅层；
在本征碳化硅层表面生长磷掺杂碳化硅层；以及
退火处理，以使磷掺杂碳化硅层中的磷与碳化硅形成共价键。
本申请提供的钝化接触电池的制备工艺，在背面场结构中，在隧穿氧化层的表面依次生长本征碳化硅层和磷掺杂碳化硅层，代替传统的多晶硅结构。本申请提供的钝化接触电池的制备工艺至少具有以下效果：
1、相比起PECVD沉积poly-Si，SiC x中的H很难逃逸，在PECVD沉积工艺下，在PECVD沉积工艺中，能明显改善爆膜的问题，有利于增强电池的钝化性能，并有利于使得Voc和电池效率得到提升。
2、SiC x相较于poly-Si具有更高的硬度，在退火处理的烧结过程中能提高背面耐银浆腐蚀能力，从而减少金属刺穿现象，降低金属复合，同样地有利于使得Voc和电池效率得到提升。
3、SiC x相较于poly-Si而言，C-H键更加稳定，使SiC x中的氢含量更高，也增加了界面H含量，有利于提升电池的钝化性能。
4、SiC的光学带隙比多晶硅更宽，能降低红外寄生吸收，有利于提升电流密度，还能有效提升电池效率和双面率。
此外，在本申请提供的钝化接触电池的制备工艺中，发明人研究发现，在采用SiC x替代poly-Si的同时，本征碳化硅层间隔在隧穿氧化层和磷掺杂碳化硅层之间，以本征碳化硅层作为缓冲结构，还能阻挡形成磷掺杂碳化硅层时的磷穿过隧穿氧化层进入体硅中，能有效避免对电池的开路电压等造成影响。
需要说明的是，以上主要示出了背面场钝化结构的制备过程，在钝化接触电池的制备工艺中，还可以根据需要或者常规方式进行制绒、p-n结制作、去绕镀、形成掩膜、制作电极等其他步骤。
在一些示例性的实施例中，钝化接触电池的制备工艺可以包括：
制绒。示例性地，准备N型硅片，采用1％的碱液进行制绒，采用双氧水和碱对硅片进行清洗。
硼扩。示例性地，进入硼扩散炉，利用BCl 3在900～1050℃扩散形成p-n结。
碱抛。示例性地，采用链式HF机去除背面硼扩绕度的BSG(硼硅玻璃)，再通过机械手转入槽式碱抛机，去除背面和边缘p-n结。
在硅片的背面生长隧穿氧化层。
在隧穿氧化层的表面生长本征碳化硅层。
在本征碳化硅层表面生长磷掺杂碳化硅层。
退火处理。示例性地，采用管式退火炉，退火气体氛围为氮气(N 2)或氧气(O 2)。
RCA清洗。示例性地，先经过链式氢氟酸(HF)，去除背面场钝化结构的制备的各步骤中绕镀到正面的氧化层以及退火过程中生成的氧化层，随后转入碱槽去除正面碳化硅绕镀层。
正面氧化铝膜和氮化硅膜沉积。示例性地，采用PEALD(等离子体增强原子层沉积方式)或PECVD方式沉积的氧化铝(AlO x)薄膜用于钝化，采用PECVD沉积氮化硅(SiN x)薄膜用于减反射。
沉积背面氮化硅膜。示例性地，采用PECVD沉积SiN x薄膜，用于背膜氢钝化。
制作电极。示例性地，丝网印刷正背面浆料。
电注入、测试效率和分选。
关于制备背面场钝化结构的各个步骤，以下将对一些示例性的实施方式进行说明。
关于生长隧穿氧化层的步骤：
作为示例，采用PEALD或PECVD方式，生成一层厚度为0.5～2nm的隧穿氧化层。
关于生长本征碳化硅层的步骤：
作为示例，采用PECVD沉积本征碳化硅层。采用等离子体增强化学气相沉积法，使得绕镀较少，有利于电池外观和良率的控制。
作为示例，生长本征碳化硅层的步骤中，通入CH 4、SiH 4和H 2进行反应沉积；其中，CH 4和SiH 4的体积比为1：(1～10)，例如但不限于为1：1、1：2、1：3、1：4、1：5、1：6、1：7、1：8、1：9和1：10中的任意一者或任意两者之间的范围值。该设计中，CH 4和SiH 4具有合适的体积比，有利于本征碳化硅层较好地发挥钝化和缓冲的作用。
作为示例，本征碳化硅层的厚度为5～80nm；可选地，本征碳化硅层的厚度为5～50nm；可选地，本征碳化硅层的厚度为20～30nm。
该本征碳化硅层的厚度例如但不限于为5nm、10nm、20nm、25nm、30nm、40nm、50nm和80nm中的任意一者或任意两者之间的范围值。由于本征碳化硅层具有合适的厚度，能较好地发挥钝化、减少红外吸收和缓冲的作用，有利于更好地实现Voc、Isc和电池效率的提升。
关于生长磷掺杂碳化硅层的步骤：
作为示例，采用PECVD沉积磷掺杂碳化硅层。采用等离子体增强化学气相沉积法，使得绕镀较少，有利于电池外观和良率的控制。
作为示例，生长磷掺杂碳化硅层的步骤中，通入CH 4、SiH 4、PH 3和H 2进行反应沉积；其中，CH 4和SiH 4的体积比为1：(1～10)，例如但不限于为1：1、1：2、1：3、1：4、1：5、1：6、1：7、1：8、1：9和1：10中的任意一者或任意两者之间的范围值。该设计中，CH 4和SiH 4具有合适的体积比，有利于磷掺杂碳化硅层较好地发挥钝化和防浆料腐蚀刺穿的作用。
作为示例，磷掺杂碳化硅层的厚度为20～200nm；可选地，磷掺杂碳化硅层的厚度为100～150nm。
该磷掺杂碳化硅层的厚度例如但不限于为20nm、50nm、80nm、100nm、120nm、150nm和200nm中的任意一者或任意两者之间的范围值。由于磷掺杂碳化硅层具有合适的厚度，能较好地发挥钝化和防浆料腐蚀刺穿的作用，有利于更好地实现Voc、Isc和电池效率的提升。
进一步地选地，本征碳化硅层和磷掺杂碳化硅层的总厚度≤厚度≤的总。本征碳化硅层和磷掺杂碳化硅层的总厚度控制在一定的标准内，在有效提升Voc和电池效率的同时，较好地兼顾电池的整体性能。
在一些可选的实施方案中，在生长磷掺杂碳化硅层的步骤之后，且在退火处理步骤之前，还包括：在磷掺杂碳化硅层的表面生长SiO x掩膜层。
作为示例，采用PECVD方式，通入SiH 4和N 2O，以沉积SiO x掩膜层，该SiO x掩膜层的厚度为10～50nm，例如但不限于为10nm、20nm、30nm、40nm或者50nm。
上述实施方案中，SiO x掩膜层用于保护背面场钝化结构，能够有效避免背面场钝化结构在后续的去绕镀清洗等工艺中被破坏。
关于上述各个步骤，在一些示例性的实施方式下，隧穿氧化层、本征碳化硅层、磷掺杂碳化硅层以及SiO x掩膜层均采用PECVD设备实现薄膜沉积时，该多个膜层可在同一管不破真空的情况下一次性完成薄膜沉积。当然，需要说明的是，在本申请中，关于该各个膜层的生成方式不限，例如但不限于还可以是等离子增强物理气相沉积(PVD)、化学气相沉积(CVD)技术、金属有机化合物化学气相沉积(MOCVD)等。
关于退火处理的步骤：退火温度为600～1000骤，可选地，退火温度为900～9400，该退火温度例如但不限于为600℃、700℃、800℃、900℃、910℃、920℃、930℃、940℃、950℃和1000℃中的任意一者或任意两者之间的范围值。
退火时间为10～60min，该退火时间例如但不限于为10min、20min、30min、40min、50min和60min中的任意一者或任意两者之间的范围值。
上述实施方式下，采用合适的退火条件进行退火处理，保证较好地对背面场钝化结构进行晶化和有效掺磷，使得磷掺杂碳化硅层中的磷较好地与碳化硅形成共价键，能够较好 地提供电子形成钝化结构，从而有利于更好地实现Voc和电池效率的提升。
参照图1，本申请的另一些实施方式提供了一种钝化接触电池100，其能够通过本申请的一些实施方式提供的制备工艺制得。
钝化接触电池100可以包括硅片140、以及在硅片140的背面依次层叠的隧穿氧化层150、本征碳化硅层160和磷掺杂碳化硅层170。
需要说明的是，以上主要示出了与背面场钝化结构对应的结构，在钝化接触电池中，还可以根据功能需要以及电池设计等配置其他的减反层、钝化层、电极等。
继续参照图1，在一些示例性的实施例中，钝化接触电池100可以包括依次设置的正面减反射层110、正面钝化层120、正面P型掺杂层130、N型的硅片140、隧穿氧化层150、本征碳化硅层160、磷掺杂碳化硅层170以及背面钝化层180。
其中，可选地，正面减反射层110可以为SiN x减反射层，正面钝化层120可以为AlO x钝化层，背面钝化层180可以为SiN x钝化层。
以下结合实施例对本申请的特征和性能作进一步的详细描述。
实施例1
一种钝化接触电池的制备工艺，可以包括：
S1、制绒：准备N型硅片，采用1％的碱液进行制绒，采用双氧水和碱对硅片进行清洗。
S2、硼扩：进入硼扩散炉，利用BCl 3在1000℃扩散形成p-n结。
S3、碱抛：采用链式HF机去除背面硼扩绕度的BSG，再通过机械手转入槽式碱抛机，去除背面和边缘p-n结。
S4、在硅片的背面生长隧穿氧化层：采用PECVD的方式，通入O 2，生长出厚度为1nm的隧穿氧化层SiO x。
S5、在隧穿氧化层的表面生长本征碳化硅层：采用PECVD的方式，通入CH 4、SiH 4和H 2进行反应沉积；其中，CH 4和SiH 4的体积比为1：10，本征碳化硅层的厚度为30nm。
S6、本征碳化硅层表面生长磷掺杂碳化硅层：采用PECVD的方式，通入CH 4、SiH 4、PH 3和H 2进行反应沉积；其中，CH 4和SiH 4的体积比为1：10，磷掺杂碳化硅层的厚度为100nm。
S7、在磷掺杂碳化硅层的表面生长SiO x掩膜层：采用PECVD的方式，通入SiH 4和N 2O，沉积SiO x掩膜层，厚度为20nm。
S8、退火处理：采用管式退火炉，退火气体氛围为氮气，退火温度为900℃，退火时间为20min。
S9、RCA清洗：先经过链式氢氟酸(HF)，去除S4～S7步骤中绕镀到正面的氧化层以及S8步骤中退火过程中生成的氧化层，随后转入碱槽去除正面碳化硅绕镀层。
S10、正面氧化铝膜和氮化硅膜沉积：采用PEALD:方式沉积的氧化铝薄膜用于钝化，采用PECVD沉积氮化硅薄膜用于减反射。
S11、沉积背面氮化硅膜：采用PECVD沉积SiN x薄膜，用于背膜氢钝化。
S12、制作电极。示例性地，丝网印刷正背面浆料。
S13、电注入、测试效率和分选。
实施例2
一种钝化接触电池的制备工艺，其与实施例1的不同之处仅在于：
S5步骤中，CH 4和SiH 4的体积比为1：5。
实施例3
一种钝化接触电池的制备工艺，其与实施例1的不同之处仅在于：
S5步骤中，本征碳化硅层的厚度为5nm。
实施例4
一种钝化接触电池的制备工艺，其与实施例1的不同之处仅在于：
S5步骤中，本征碳化硅层的厚度为80nm。
实施例5
一种钝化接触电池的制备工艺，其与实施例1的不同之处仅在于：
S6步骤中，磷掺杂碳化硅层的厚度为20nm。
实施例6
一种钝化接触电池的制备工艺，其与实施例1的不同之处仅在于：
S6步骤中，磷掺杂碳化硅层的厚度为200nm。
实施例7
一种钝化接触电池的制备工艺，其与实施例1的不同之处仅在于：
S8步骤中，退火温度为940℃。
各实施例中一些实验条件的汇总如表1所示。
表1.实施例中实验条件汇总
Figure PCTCN2022127747-appb-000001
Figure PCTCN2022127747-appb-000002
对比例1
一种钝化接触电池的制备工艺，其为常规多晶硅工艺，其与实施例1的不同之处在于：其沉积n+-poly-Si薄膜代替沉积本征碳化硅层和磷掺杂碳化硅层。具体地：
将S4～S7步骤替换为：采用LPCVD设备生长隧穿氧化层和本征多晶硅，通入氧气，生长隧穿氧化层，膜厚为1nm；关闭氧气，通入硅烷，生长130nm本征多晶硅。
将S8步骤替换为：变更为采用管式扩散炉，通入磷烷，进行磷掺杂。
试验例
将各实施例和对比例制得的钝化接触电池的电性能进行检测，检测结果如表2所示。
表2.钝化接触电池的电性能
Figure PCTCN2022127747-appb-000003
根据表1可知，实施例1～实施例7提供的钝化接触电池，有较好的整体电性能。其中：
实施例1提供的钝化接触电池，相较于传统的多晶硅工艺，Voc提升2.3mV，Isc提升60mA，电池的光电转换效率提升0.15％，电池的整体电性能有较高的提升。
实施例2提供的钝化接触电池，相较于传统的多晶硅工艺，Voc提升2.9mV，Isc提升 50mA，电池的光电转换效率提升0.11％，电池的整体电性能有较高的提升。
实施例3提供的钝化接触电池，本征碳化硅层的厚度较小，相较于传统的多晶硅工艺，Isc提升60mA，电池的光电转换效率相当。
实施例4提供的钝化接触电池，本征碳化硅层的厚度较大，相较于传统的多晶硅工艺，Isc提升50mA，Voc提升0.9mV，电池的光电转换效率相当。
实施例5提供的钝化接触电池，磷掺杂碳化硅层的厚度较小，相较于传统的多晶硅工艺，Isc提升120mA，电池的光电转换效率相当。
实施例6提供的钝化接触电池，磷掺杂碳化硅层的厚度较大，相较于传统的多晶硅工艺，Voc提升3.9mV，FF提高0.17％，电池的光电转换效率相当。
实施例7提供的钝化接触电池，相较于传统的多晶硅工艺，Voc提升1.5mV，Isc提升60mA，FF提升了0.11％，电池的光电转换效率提升0.16％，电池的整体电性能有较高的提升。
以上所描述的实施例是本申请一部分实施例，而不是全部的实施例。本申请的实施例的详细描述并非旨在限制要求保护的本申请的范围，而是仅仅表示本申请的选定实施例。基于本申请中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
工业实用性
本申请提供了一种钝化接触电池及其制备工艺，属于太阳能电池领域。钝化接触电池的制备工艺，其背面场钝化结构的制备包括：在硅片的背面生长隧穿氧化层；在隧穿氧化层的表面生长本征碳化硅层；在本征碳化硅层表面生长磷掺杂碳化硅层；以及退火处理，以使磷掺杂碳化硅层中的磷与碳化硅形成共价键。钝化接触电池能够通过上述制备工艺制得，其包括硅片，以及在所述硅片的背面依次层叠的隧穿氧化层、本征碳化硅层和磷掺杂碳化硅层。该制备工艺和电池能有效缓解PECVD沉积得到的背面场钝化结构爆膜严重的问题；还能提高背面耐银浆腐蚀能力，从而减少金属刺穿现象，降低金属复合。。
此外，可以理解的是，本申请的钝化接触电池及其制备工艺是可以重现的，并且可以用在多种工业应用中。例如，本申请的钝化接触电池及其制备工艺可以用于太阳能电池领域。

Claims (16)

  1. 一种钝化接触电池的制备工艺，其背面场钝化结构的制备包括：
    在硅片的背面生长隧穿氧化层；
    在所述隧穿氧化层的表面生长本征碳化硅层；
    在所述本征碳化硅层表面生长磷掺杂碳化硅层；以及
    退火处理，以使所述磷掺杂碳化硅层中的磷与碳化硅形成共价键。
  2. 根据权利要求1所述的制备工艺，其中，所述本征碳化硅层的厚度为5～80nm；
    可选地，所述本征碳化硅层的厚度为5～50nm；
    可选地，所述本征碳化硅层的厚度为20～30nm。
  3. 根据权利要求1或2所述的制备工艺，其中，所述磷掺杂碳化硅层的厚度为20～200nm；
    可选地，所述磷掺杂碳化硅层的厚度为100～150nm。
  4. 根据权利要求1至3中任一项所述的制备工艺，其中，所述本征碳化硅层和所述磷掺杂碳化硅层的总厚度≤200nm。
  5. 根据权利要求1至4中任一项所述的制备工艺，其中，生长所述本征碳化硅层的步骤中，采用等离子体增强化学气相沉积法沉积所述本征碳化硅层；
    和/或，生长所述磷掺杂碳化硅层的步骤中，采用等离子体增强化学气相沉积法沉积所述磷掺杂碳化硅层。
  6. 根据权利要求1、2或5所述的制备工艺，其中，生长所述本征碳化硅层的步骤中，通入CH 4、SiH 4和H 2进行反应沉积；其中，CH 4和SiH 4的体积比为1：(1～10)。
  7. 根据权利要求1、3或5所述的制备工艺，其中，生长所述磷掺杂碳化硅层的步骤中，通入CH 4、SiH 4、PH 3和H 2进行反应沉积；其中，CH 4和SiH 4的体积比为1：(1～10)。
  8. 根据权利要求1至7中任一项所述的制备工艺，其中，所述退火处理步骤中，退火温度为600～1000℃，退火时间为10～60min；
    可选地，退火温度为900～940℃。
  9. 根据权利要求1至8中任一项所述的制备工艺，其中，在生长所述磷掺杂碳化硅层的步骤之后，且在所述退火处理步骤之前，还包括：在所述磷掺杂碳化硅层的表面生长SiO x掩膜层。
  10. 根据权利要求9所述的制备工艺，其中，在磷掺杂碳化硅层的表面生长SiO x掩膜层的步骤中，采用PECVD方式，通入SiH 4和N 2O，以沉积SiO x掩膜层，所述SiO x掩膜层的厚度为10～50nm。
  11. 根据权利要求1至10中任一项所述的制备工艺，其中，采用管式退火炉进行所述 退火处理，退火气体氛围为氮气(N 2)或氧气(O 2)。
  12. 根据权利要求1至11中任一项所述的制备工艺，其中，所述制备工艺还包括RCA清洗，其中，先经过链式氢氟酸(HF)，去除背面场钝化结构的制备的各步骤中绕镀到正面的氧化层以及退火过程中生成的氧化层，随后转入碱槽去除正面碳化硅绕镀层。
  13. 根据权利要求1至12中任一项所述的制备工艺，其中，所述制备工艺还包括正面氧化铝膜和氮化硅膜沉积，其中，采用等离子体增强原子层沉积方式或PECVD方式沉积的氧化铝(AlO x)薄膜用于钝化，采用PECVD沉积氮化硅(SiN x)薄膜用于减反射。
  14. 根据权利要求1至13中任一项所述的制备工艺，其中，所述制备工艺还包括沉积背面氮化硅膜，其中，采用PECVD沉积SiN x薄膜，用于背膜氢钝化。
  15. 根据权利要求1至14中任一项所述的制备工艺，其中，在生长隧穿氧化层的步骤中，采用PEALD或PECVD方式，生成一层厚度为0.5～2nm的隧穿氧化层。
  16. 一种钝化接触电池，其中，包括：硅片，以及在所述硅片的背面依次层叠的隧穿氧化层、本征碳化硅层和磷掺杂碳化硅层。
PCT/CN2022/127747 2022-02-16 2022-10-26 钝化接触电池及其制备工艺 WO2023155473A1 (zh)

Priority Applications (2)

Application Number Priority Date Filing Date Title
EP22926777.8A EP4345920A1 (en) 2022-02-16 2022-10-26 Passivated contact battery and preparation process therefor
AU2022441542A AU2022441542A1 (en) 2022-02-16 2022-10-26 Passivated contact battery and preparation process therefor

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202210141493.5 2022-02-16
CN202210141493.5A CN114520276B (zh) 2022-02-16 2022-02-16 钝化接触电池及其制备工艺

Publications (1)

Publication Number Publication Date
WO2023155473A1 true WO2023155473A1 (zh) 2023-08-24

Family

ID=81599927

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2022/127747 WO2023155473A1 (zh) 2022-02-16 2022-10-26 钝化接触电池及其制备工艺

Country Status (4)

Country Link
EP (1) EP4345920A1 (zh)
CN (1) CN114520276B (zh)
AU (1) AU2022441542A1 (zh)
WO (1) WO2023155473A1 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117174783A (zh) * 2023-10-16 2023-12-05 江苏微导纳米科技股份有限公司 一种TOPCon太阳能电池及其制备方法

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114520276B (zh) * 2022-02-16 2023-10-10 通威太阳能(眉山)有限公司 钝化接触电池及其制备工艺
CN117248199A (zh) * 2023-11-17 2023-12-19 常州亿晶光电科技有限公司 一种防止爆膜的pecvd沉积非晶硅的方法

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111106183A (zh) * 2019-12-26 2020-05-05 湖南红太阳光电科技有限公司 利用管式pecvd制备背面全钝化接触太阳电池的方法及背面全钝化接触太阳电池
CN112542519A (zh) * 2019-09-23 2021-03-23 苏州阿特斯阳光电力科技有限公司 太阳能电池及其制备方法
CN215118914U (zh) * 2021-06-04 2021-12-10 浙江爱旭太阳能科技有限公司 一种太阳能电池及其钝化接触结构、电池组件及光伏系统
CN215220733U (zh) * 2021-06-04 2021-12-17 浙江爱旭太阳能科技有限公司 一种太阳能电池及其正面膜层结构、电池组件及光伏系统
CN113948609A (zh) * 2021-09-22 2022-01-18 江苏微导纳米科技股份有限公司 钝化接触太阳能电池制备方法及钝化接触太阳能电池
CN114420786A (zh) * 2021-12-22 2022-04-29 西安隆基乐叶光伏科技有限公司 钝化接触电池的制备方法及钝化接触电池
CN114520276A (zh) * 2022-02-16 2022-05-20 通威太阳能(眉山)有限公司 钝化接触电池及其制备工艺
CN114864751A (zh) * 2022-05-19 2022-08-05 通威太阳能(眉山)有限公司 太阳电池及其制备方法

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109786476B (zh) * 2018-12-27 2021-05-28 中国科学院宁波材料技术与工程研究所 一种钝化接触结构及其在硅太阳电池中应用
CN111834492A (zh) * 2020-07-22 2020-10-27 常州时创能源股份有限公司 TOPCon电池的制备方法
CN113437179A (zh) * 2021-06-04 2021-09-24 浙江爱旭太阳能科技有限公司 一种太阳能电池及其制备方法

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112542519A (zh) * 2019-09-23 2021-03-23 苏州阿特斯阳光电力科技有限公司 太阳能电池及其制备方法
CN111106183A (zh) * 2019-12-26 2020-05-05 湖南红太阳光电科技有限公司 利用管式pecvd制备背面全钝化接触太阳电池的方法及背面全钝化接触太阳电池
CN215118914U (zh) * 2021-06-04 2021-12-10 浙江爱旭太阳能科技有限公司 一种太阳能电池及其钝化接触结构、电池组件及光伏系统
CN215220733U (zh) * 2021-06-04 2021-12-17 浙江爱旭太阳能科技有限公司 一种太阳能电池及其正面膜层结构、电池组件及光伏系统
CN113948609A (zh) * 2021-09-22 2022-01-18 江苏微导纳米科技股份有限公司 钝化接触太阳能电池制备方法及钝化接触太阳能电池
CN114420786A (zh) * 2021-12-22 2022-04-29 西安隆基乐叶光伏科技有限公司 钝化接触电池的制备方法及钝化接触电池
CN114520276A (zh) * 2022-02-16 2022-05-20 通威太阳能(眉山)有限公司 钝化接触电池及其制备工艺
CN114864751A (zh) * 2022-05-19 2022-08-05 通威太阳能(眉山)有限公司 太阳电池及其制备方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117174783A (zh) * 2023-10-16 2023-12-05 江苏微导纳米科技股份有限公司 一种TOPCon太阳能电池及其制备方法

Also Published As

Publication number Publication date
AU2022441542A1 (en) 2024-01-18
CN114520276B (zh) 2023-10-10
CN114520276A (zh) 2022-05-20
EP4345920A1 (en) 2024-04-03

Similar Documents

Publication Publication Date Title
WO2023155473A1 (zh) 钝化接触电池及其制备工艺
EP4027395A1 (en) Efficient back passivation crystalline silicon solar cell and manufacturing method therefor
CN114864751B (zh) 太阳电池及其制备方法
WO2024066884A1 (zh) 太阳电池及其制备方法
WO2024087838A1 (zh) 一种太阳电池及其制备方法
WO2020199494A1 (zh) 太阳能电池及其制备方法
WO2023092977A1 (zh) 制备隧穿氧化层和非晶硅薄膜的方法及TOPCon电池
WO2023036121A1 (zh) 一种电池背钝化结构及其制作方法、太阳能电池
CN115692545A (zh) 一种提升PECVD路线N型TOPCon电池多晶硅活性磷掺杂浓度的方法
CN114335236A (zh) 钝化接触电池及其制备方法和钝化接触结构及其制备装置
WO2023216652A1 (zh) 一种双面太阳能电池及其制备方法
CN104701390A (zh) 太阳能电池背面钝化方法
CN115692533A (zh) 一种TOPCon电池及其制备方法
WO2022242067A1 (zh) 一种perc电池背钝化结构、perc电池及制备方法
CN114597267A (zh) 一种TOPCon电池及其制备方法
CN111969070B (zh) 一种太阳电池及其制备方法
CN114583016A (zh) 一种TOPCon电池及其制备方法
CN112186067A (zh) 一种掺杂氮硅化物薄膜钝化接触结构的制备方法及其应用
CN117352589B (zh) 一种改善TOPCon电池背面钝化接触结构的方法
TWI701845B (zh) 太陽能電池結構以及太陽能電池氧化層的製造方法
CN114765234B (zh) 一种p型晶硅双面电池退火增强背钝化方法
CN114203832B (zh) 具有钝化接触层并叠加复合钝化层的铸造单晶硅钝化结构
CN116913984B (zh) 电介质层及制备方法、太阳电池、光伏组件
WO2023115787A1 (zh) 一种太阳能电池的窗口层、太阳能电池及其制备方法
WO2022205523A1 (zh) 一种双面太阳能电池及其制备方法

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 22926777

Country of ref document: EP

Kind code of ref document: A1

WWE Wipo information: entry into national phase

Ref document number: 2022441542

Country of ref document: AU

Ref document number: AU2022441542

Country of ref document: AU

WWE Wipo information: entry into national phase

Ref document number: 2022926777

Country of ref document: EP

Ref document number: 22926777.8

Country of ref document: EP

ENP Entry into the national phase

Ref document number: 2022441542

Country of ref document: AU

Date of ref document: 20221026

Kind code of ref document: A

ENP Entry into the national phase

Ref document number: 2022926777

Country of ref document: EP

Effective date: 20231228