WO2022242067A1 - 一种perc电池背钝化结构、perc电池及制备方法 - Google Patents

一种perc电池背钝化结构、perc电池及制备方法 Download PDF

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WO2022242067A1
WO2022242067A1 PCT/CN2021/130303 CN2021130303W WO2022242067A1 WO 2022242067 A1 WO2022242067 A1 WO 2022242067A1 CN 2021130303 W CN2021130303 W CN 2021130303W WO 2022242067 A1 WO2022242067 A1 WO 2022242067A1
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oxide layer
silicon oxide
silicon
perc battery
layer
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PCT/CN2021/130303
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English (en)
French (fr)
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方超炎
何悦
郭帅
任海亮
任勇
陈德爽
徐君
金志洪
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横店集团东磁股份有限公司
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Priority claimed from CN202110538791.3A external-priority patent/CN113257927A/zh
Priority claimed from CN202121059479.8U external-priority patent/CN215911433U/zh
Application filed by 横店集团东磁股份有限公司 filed Critical 横店集团东磁股份有限公司
Priority to EP21940511.5A priority Critical patent/EP4307394A1/en
Publication of WO2022242067A1 publication Critical patent/WO2022242067A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0216—Coatings
    • H01L31/02161—Coatings for devices characterised by at least one potential jump barrier or surface barrier
    • H01L31/02167—Coatings for devices characterised by at least one potential jump barrier or surface barrier for solar cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers
    • H01L31/068—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN homojunction type, e.g. bulk silicon PN homojunction solar cells or thin film polycrystalline silicon PN homojunction solar cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H01L31/186—Particular post-treatment for the devices, e.g. annealing, impurity gettering, short-circuit elimination, recrystallisation
    • H01L31/1868—Passivation
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Definitions

  • the invention belongs to the technical field of photovoltaic cells, and relates to a back passivation structure of a PERC cell, a PERC cell and a preparation method.
  • PERC battery that is, passivated emitter and back battery technology, originated in the 1980s.
  • the general process flow of PERC cells has the following steps: texturing ⁇ diffusion ⁇ SE laser ⁇ oxidation ⁇ etching (removing PSG) ⁇ annealing ⁇ back film ⁇ positive film ⁇ laser slotting ⁇ screen printing ⁇ sintering ⁇ light injection or electrical injection ⁇ Test sorting.
  • the coating process is an extremely important part of the PERC battery production line process. During the production process of the battery sheet, an anti-reflection film needs to be coated on the front side to reduce the reflection of light and enhance the absorption of light.
  • a passivation film is coated on the back side.
  • the passivation film is used to passivate the dangling bonds on the silicon surface to reduce the recombination rate of the surface so as to play the role of surface passivation or bulk passivation.
  • its high refractive index can enhance the reflectivity of the back and further improve the efficiency of the cell. It can be said that the quality of the passivation film directly affects the performance of the solar cell.
  • Silicon dioxide is a good passivation material.
  • the industrialized SiO 2 film growth method is mainly the thermal oxidation method.
  • the silicon wafer is placed in a high-temperature quartz furnace tube, and the SiO 2 film is grown on the surface of the silicon wafer under the action of oxidizing substances.
  • thermal oxidation can be divided into dry oxygen oxidation, water vapor oxidation and wet oxygen oxidation.
  • the oxide layer can effectively reduce the interface state defect density.
  • the Si-SiO 2 interface plays a leading role in the chemical passivation effect of saturated dangling bonds. There is a certain fixed positive charge on the Si-SiO 2 interface, and the charge density is on the order of 1010cm -2 .
  • the positive charge carried by the passivation film of SiO x basically does not affect the field passivation effect of AlO x , but a defect growth of thermal oxidation growth The speed is relatively slow, and the thickness cannot grow too thick.
  • CN105470349A discloses a PERC solar cell and its preparation method, wherein the PERC solar cell includes a silicon wafer, a silicon dioxide layer and a silver layer located on the upper surface of the silicon wafer, a front silicon nitride passivation layer located on the upper surface of the silicon dioxide layer, The aluminum oxide passivation layer located on the lower surface of the silicon wafer, the back silicon nitride passivation layer located on the lower surface of the aluminum oxide passivation layer, and several openings are spaced apart on the back silicon nitride passivation layer, in the openings It is filled with an aluminum layer that forms an aluminum-silicon alloy with the silicon wafer after the aluminum oxide passivation layer is etched away.
  • holes are opened on the back silicon nitride passivation layer by means of laser opening, and the depth of the holes is controlled to penetrate the back silicon nitride passivation layer without piercing the aluminum oxide passivation layer, and then print aluminum paste and pass through sintering process, the aluminum paste corrodes the aluminum oxide passivation layer and forms an aluminum-silicon alloy with the silicon wafer.
  • CN209515679U discloses a PERC cell structure, comprising: substrate, front silicon dioxide layer, anti-reflection layer, front silicon nitride layer, back passivation layer, and protective structure; The front side of the substrate, the anti-reflection layer is arranged on the side of the front silicon dioxide layer opposite to the substrate, and the front silicon nitride layer is arranged on the front side of the anti-reflection layer and the front side The side opposite the silicon dioxide layer.
  • CN110854240A discloses a PERC battery and its preparation method.
  • the preparation method includes texturing, diffusion, etching, back polishing, annealing, back coating and front coating.
  • the back coating step includes: passing ozone gas into the equipment equipped with the annealed silicon chip for oxidation treatment, so that the back side of the silicon chip forms a back silicon dioxide layer. Then, in the same equipment, continue to feed ozone as an oxygen source, and add an aluminum source to deposit a back aluminum oxide layer on the back silicon dioxide layer. A backside silicon nitride layer is deposited on the backside aluminum oxide layer.
  • PECVD plasma-enhanced chemical vapor deposition
  • the purpose of the present invention is to provide a PERC cell back passivation structure, PERC cell and its preparation method.
  • the present invention uses crystalline silicon oxide to replace traditional amorphous silicon oxide, and the crystalline silicon oxide The atomic distribution has long-range order. Therefore, compared with the amorphous silicon oxide layer, the crystalline silicon oxide layer is denser, the passivation effect is better, and the interface state defect density can be as low as 10 10 cm -2 eV -1 , which improves the overall performance of PERC batteries.
  • the present invention provides a rear passivation structure of a PERC battery, and the rear passivation structure of a PERC battery includes a crystalline silicon oxide layer disposed on the back of a silicon substrate.
  • the silicon oxide layer in the rear passivation structure of the PERC battery mostly uses amorphous silicon oxide, but the silicon-hydrogen bonding of amorphous silicon oxide is weak, and the passivation effect is poor.
  • the present invention uses crystalline silicon oxide to replace the traditional Amorphous silicon oxide, although the atomic distribution in amorphous silicon oxide also has a certain order, but it is only a short-range order, while the atomic distribution in crystalline silicon oxide has a long-range order. Therefore, compared with Compared with the amorphous silicon oxide layer, the crystalline silicon oxide layer has a higher density and better passivation effect, and the interface state defect density can be as low as 10 10 cm -2 eV -1 , which improves the overall performance of PERC cells.
  • back passivation structure claimed in the present invention is a part of the structure of the PERC battery. It can be understood that within the scope of protection defined here, there are no specific requirements and special requirements for other structures in the PERC battery. Definition, in other words, on the basis of the rear passivation structure defined in the present invention, those skilled in the art can make conventional replacements or creative improvements to other structures based on the prior art.
  • the present invention provides a complete structure of a PERC battery, including a silicon substrate, the front of the silicon substrate is sequentially stacked with an emitter, a front silicon oxide layer and a front silicon nitride layer (the front silicon nitride layer can be replaced by silicon oxynitride layer or silicon carbide layer), and at the same time, a front electrode is inserted vertically on the front.
  • the back of the silicon substrate is stacked with a crystalline silicon oxide layer, an aluminum oxide layer, and a silicon nitride layer on the back (the silicon nitride layer on the back can be replaced by a silicon nitride oxide layer or a silicon carbide layer), and the back is also vertically inserted into the back electrode.
  • the improved PERC battery also falls within the scope of protection and disclosure of the present invention.
  • the thickness of the crystalline silicon oxide layer is 1 to 20 nm, such as 1 nm, 2 nm, 3 nm, 4 nm, 5 nm, 6 nm, 7 nm, 8 nm, 9 nm, 10 nm, 11 nm, 12nm, 13nm, 14nm, 15nm, 16nm, 17nm, 18nm, 19nm or 20nm, but not limited to the listed values, other unlisted values within this range are also applicable.
  • the surface of the crystalline silicon oxide layer is sequentially provided with an aluminum oxide layer and a silicon nitride layer on the back.
  • the thickness of the aluminum oxide layer is 5-10nm, such as 5nm, 5.5nm, 6nm, 6.5nm, 7nm, 7.5nm, 8nm, 8.5nm, 9nm, 9.5nm or 10nm, but not limited to the listed Numerical values, other unlisted numerical values within this numerical range are also applicable.
  • the thickness of the silicon nitride layer on the back side is 10-200nm, such as 10nm, 20nm, 30nm, 40nm, 50nm, 60nm, 70nm, 80nm, 90nm, 100nm, 110nm, 120nm, 130nm, 140nm, 150nm, 160nm, 170nm, 180nm, 190nm or 200nm, but not limited to the listed values, other unlisted values within this range are also applicable.
  • the present invention provides a method for preparing the PERC battery back passivation structure described in the first aspect, the preparation method comprising:
  • An amorphous silicon oxide film is deposited on the back of the silicon substrate, and after annealing, the amorphous silicon oxide film is transformed into a crystalline silicon oxide layer.
  • an amorphous silicon oxide film is first deposited on the back of the silicon substrate, but the structure of the amorphous silicon oxide film is relatively loose, and the deposited silicon oxide is all amorphous, with weak silicon-hydrogen bonding and poor passivation effect.
  • the amorphous silicon oxide gradually transforms into hydrogen-rich crystalline silicon oxide, which greatly enhances the passivation effect, and finally obtains a thicker crystalline silicon oxide layer with better passivation effect, and interface state defects
  • the density can be as low as 10 10 cm -2 eV -1 , which improves the overall performance of the solar cell.
  • the deposition process of the amorphous silicon oxide film specifically includes:
  • the present invention combines PECVD and thermal oxidation to prepare the rear passivation structure of single-crystal PERC cells.
  • PECVD silane and laughing gas are used to deposit and form a silicon oxide layer with the assistance of plasma.
  • the growth rate of the silicon oxide layer deposited by the PECVD method is faster, and the deposited silicon oxide layer is also thicker, but correspondingly, the structure of the silicon oxide layer is relatively loose, and the deposited silicon oxide is all amorphous, and the silicon-hydrogen bond is combined.
  • the passivation effect is inferior to the silicon oxide layer formed by thermal oxidation.
  • the present invention gradually transforms amorphous silicon oxide into crystalline silicon oxide through thermal oxidation, which greatly enhances the passivation effect, and finally obtains a thicker crystalline silicon oxide layer with better passivation effect , the interface state defect density can be as low as 10 10 cm -2 eV -1 , which improves the overall performance of the solar cell.
  • the flow rate of the laughing gas is 4000-6000 sccm, for example, it can be 4000 sccm, 4200 sccm, 4400 sccm, 4600 sccm, 4800 sccm, 5000 sccm, 5200 sccm, 5400 sccm, 5600 sccm, 5800 sccm or 6000 sccm, but not Not limited to the listed values, other unlisted values within the range of values are also applicable.
  • the feed flow rate of the silane is 500-800sccm, such as 500sccm, 520sccm, 540sccm, 560sccm, 580sccm, 600sccm, 620sccm, 640sccm, 660sccm, 680sccm, 700sccm, 720sccm, 740sccm, 760sccm, 780sccm or 800sccm, but not only Limited to the listed numerical values, other unlisted numerical values within this numerical range are also applicable.
  • the pressure in the film-forming chamber is maintained at 1400-1600Pa, for example, it can be 1400Pa, 1420Pa, 1440Pa, 1460Pa, 1480Pa, 1500Pa, 1520Pa, 1540Pa, 1560Pa, 1580Pa or 1600Pa, but it is not limited to the listed values. Other unrecited values within the range also apply.
  • the radio frequency power of the plasma is 6000-10000W, for example, it can be 6000W, 6500W, 7000W, 7500W, 8000W, 8500W, 9000W, 9500W or 10000W, but it is not limited to the listed values. Numerical values also apply.
  • the deposition time is 10-300s, for example, 10s, 50s, 100s, 150s, 200s, 250s or 300s, but it is not limited to the listed values, other unlisted values within this range are also applicable.
  • the annealing process is carried out in a hydrogen-rich atmosphere.
  • the hydrogen-rich atmosphere is a mixed gas containing hydrogen, and the hydrogen accounts for 40-80% of the total volume of the mixed gas, for example, it can be 40%, 45%, 50%, 55%, 60%, 65%, 70% , 75% or 80%, but not limited to the listed values, other unlisted values within this range are also applicable.
  • the present invention since there will be more dangling bonds of silicon atoms (that is, valence bonds that are not combined with oxygen atoms) at the interface of Si and SiO2 , the existence of dangling bonds will affect the interface state defect density, thereby reducing the silicon dioxide density.
  • the mixed gas also includes nitrogen and/or inert gas.
  • the annealing temperature is 850-1300°C, such as 850°C, 900°C, 950°C, 1000°C, 1050°C, 1100°C, 1150°C, 1200°C, 1250°C Or 1300°C, but not limited to the listed values, other unlisted values within this range are also applicable.
  • the present invention specifically limits the annealing temperature to 850-1300°C.
  • the annealing temperature is lower than 850°C, the temperature cannot reach the crystallization temperature of SiO2 .
  • the annealing temperature is higher than 1300°C, the energy consumption becomes larger, which is The degree of thermal damage to the silicon wafer is also increased.
  • the annealing time is 1-20 min, for example, 1 min, 2 min, 3 min, 4 min, 5 min, 6 min, 7 min, 8 min, 9 min, 10 min, 11 min, 12 min, 13 min, 14 min, 15 min, 16 min, 17 min, 18 min, 19 min Or 20min, but not limited to the listed values, other unlisted values within this range are also applicable.
  • the preparation method further includes: sequentially depositing an aluminum oxide layer and a back silicon nitride layer on the surface of the crystalline silicon oxide layer.
  • a PERC cell comprising the PERC cell back passivation structure described in the first aspect
  • the PERC cell includes a silicon substrate
  • the PERC cell includes a silicon substrate
  • the front sides of the silicon substrate are sequentially stacked
  • the back passivation structure described in the first aspect is provided on the back side of the silicon substrate.
  • the PERC battery also includes a front electrode and a back electrode, the front electrode is vertically inserted into the silicon matrix from the front of the PERC battery, and the back electrode is vertically inserted into the silicon matrix from the back of the PERC battery.
  • the present invention specifically limits the preparation methods of the crystalline silicon oxide layer to PECVD and thermal oxidation methods, but does not make specific requirements or restrictions on the preparation methods of other layer structures in PERC cells.
  • the present invention provides the following preparation method for reference by those skilled in the art, but not as a limitation to the protection scope of the present invention:
  • Texture processing is carried out on the surface of the monocrystalline silicon substrate to form a textured surface, and the monocrystalline silicon substrate is cleaned after texturing;
  • Phosphorus is diffused on the cleaned silicon substrate to generate phosphosilicate glass on the surface, and laser doping is used to form a local re-doped region on the front of the silicon substrate to obtain a selective emitter;
  • the silicon substrate is annealed in a hydrogen-rich atmosphere, the hydrogen-rich atmosphere is a mixed gas of nitrogen and/or an inert gas, and after the annealing is completed, the amorphous silicon oxide film is transformed into a crystalline silicon oxide layer;
  • ALD is used to deposit an aluminum oxide layer on the surface of crystalline silicon oxide
  • the beneficial effects of the present invention include:
  • the silicon oxide layer in the rear passivation structure of the PERC battery mostly uses amorphous silicon oxide, but the silicon-hydrogen bonding of amorphous silicon oxide is weak, and the passivation effect is poor.
  • the present invention uses crystalline silicon oxide to replace the traditional Amorphous silicon oxide, although the atomic distribution in amorphous silicon oxide also has a certain order, but it is only a short-range order, while the atomic distribution in crystalline silicon oxide has a long-range order. Therefore, compared with Compared with the amorphous silicon oxide layer, the crystalline silicon oxide layer has a higher density and better passivation effect, and the interface state defect density can be as low as 10 10 cm -2 eV -1 , which improves the overall performance of PERC cells.
  • the object of the present invention is also to provide a PERC battery back passivation structure and PERC battery comprising it, the present invention provides a PERC battery back passivation structure of sandwich structure, the main passivation structure is made of the first crystalline silicon oxide layer, a gallium oxide layer and a second crystalline silicon oxide layer are sequentially stacked and formed, and the three layers complement each other, reduce the recombination rate of the back surface, increase the passivation effect of the back surface and improve the passivation effect.
  • the present invention provides a rear passivation structure for PERC cells, the rear passivation structure for PERC cells includes a first crystalline silicon oxide layer, a gallium oxide layer, a second A crystalline silicon oxide layer and at least two backside silicon nitride layers.
  • the present invention provides a PERC battery back passivation structure with a sandwich structure.
  • the main passivation structure is formed by stacking a first crystalline silicon oxide layer, a gallium oxide layer and a second crystalline silicon oxide layer in sequence, and the three layers are complementary. Reduce the recombination rate of the back surface, increase the passivation effect of the back surface and improve the passivation effect.
  • the first crystalline silicon oxide layer is deposited on the surface of the silicon substrate to saturate the dangling bonds on the silicon surface, thereby reducing the interface state density and providing an excellent interface chemical passivation effect
  • the gallium oxide layer is sandwiched between the first crystalline oxide
  • a high concentration of fixed negative charges is formed between the first crystalline oxide
  • the negative charges can play a field passivation effect on the surface of the silicon substrate, reduce the number carrier recombination in one step, effectively reduce the surface state density, and improve Its chemical passivation effect.
  • the traditional silicon oxide layer mostly uses amorphous silicon oxide, but the silicon-hydrogen bonding of amorphous silicon oxide is weak, and the passivation effect is poor.
  • the present invention replaces traditional amorphous silicon oxide with crystalline silicon oxide , although the atomic distribution in amorphous silicon oxide also has a certain order, it is only a short-range order, while the atomic distribution in crystalline silicon oxide has a long-range order. Therefore, compared with amorphous silicon oxide
  • the silicon layer and the crystalline silicon oxide layer have a higher density, better passivation effect, and the interface state defect density can be as low as 10 10 cm -2 eV -1 , which improves the overall performance of the PERC battery.
  • the crystalline silicon oxide defined in the present invention is a concept relative to amorphous silicon oxide, and silicon oxide can be divided into crystalline and amorphous states.
  • crystal quartz
  • the thermally grown oxide film on the silicon wafer is amorphous silicon oxide.
  • the atomic distribution in crystalline silicon oxide has a long-range order, and the atomic distribution in amorphous silicon oxide also has a certain order, but it is only a short-range order. Orderliness.
  • the back passivation structure claimed in the present invention is a part of the structure of the PERC battery. It can be understood that within the scope of protection defined here, there are no specific requirements and special restrictions on other structures in the PERC battery. In other words , on the basis of the rear passivation structure defined in the present invention, those skilled in the art can make conventional replacements or creative improvements to other structures based on the prior art.
  • a connecting block is provided at the contact surface between the silicon substrate and the first crystalline silicon oxide layer, and the connecting block and the first crystalline silicon oxide layer have an integral structure, and the The connecting block is embedded inside the silicon substrate.
  • connection blocks are arranged at the contact surface between the silicon substrate and the first crystalline silicon oxide layer, and the contact area between the silicon substrate and the first crystalline silicon oxide layer is increased by adding connection blocks, so that the silicon substrate and the first crystalline silicon oxide layer
  • the first crystalline silicon oxide layer is more stable, which ensures the normal use of the battery and the service life of the battery.
  • a first fixing block is provided at the contact surface between the first crystalline silicon oxide layer and the gallium oxide layer, and the first fixing block and the gallium oxide layer have an integral structure, The first fixed block is embedded in the first crystalline silicon oxide layer.
  • first fixing blocks are arranged at the contact surface between the first crystalline silicon oxide layer and the gallium oxide layer, and the contact between the first crystalline silicon oxide layer and the gallium oxide layer is increased by adding the first fixing blocks. area, making the first crystalline silicon oxide layer and the gallium oxide layer more stable, ensuring the normal use of the battery and the service life of the battery.
  • a second fixing block is provided at the contact surface between the gallium oxide layer and the second crystalline silicon oxide layer, and the second fixing block and the gallium oxide layer have an integral structure, The second fixed block is embedded in the second crystalline silicon oxide layer.
  • both the first fixing block and the second fixing block are trapezoidal in cross-section.
  • the thickness of the first crystalline silicon oxide layer is 1-10 nm, such as 1 nm, 2 nm, 3 nm, 4 nm, 5 nm, 6 nm, 7 nm, 8 nm, 9 nm or 10 nm, However, it is not limited to the listed values, and other unlisted values within the range of values are also applicable.
  • the thickness of the gallium oxide layer is 5-10 nm, such as 5 nm, 5.5 nm, 6 nm, 6.5 nm, 7 nm, 7.5 nm, 8 nm, 8.5 nm, 9 nm, 9.5 nm Or 10nm, but not limited to the listed values, other unlisted values within this range are also applicable.
  • the thickness of the second crystalline silicon oxide layer is 1-10 nm, such as 1 nm, 2 nm, 3 nm, 4 nm, 5 nm, 6 nm, 7 nm, 8 nm, 9 nm or 10 nm, However, it is not limited to the listed values, and other unlisted values within the range of values are also applicable.
  • the total thickness of all back silicon nitride layers is 40-80nm, such as 40nm, 45nm, 50nm, 55nm, 60nm, 65nm, 70nm, 75nm or 80nm, but not limited to the Numerical values listed, other unlisted numerical values within the numerical range are also applicable.
  • the thickness of the silicon nitride layer on the back of each layer gradually decreases from the inside to the outside.
  • the present invention provides a PERC battery comprising the back passivation structure of the PERC battery described in the fourth aspect
  • the PERC battery includes a silicon substrate, and the front of the silicon substrate is sequentially stacked with an emitter, a front A silicon oxide layer and a front silicon nitride layer, the rear side of the silicon substrate is provided with the rear passivation structure of the PERC cell described in the fourth aspect.
  • the PERC battery also includes a front electrode and a back electrode, the front electrode is vertically inserted into the silicon matrix from the front of the PERC battery, and the back electrode is vertically inserted into the silicon matrix from the back of the PERC battery.
  • the present invention provides the following preparation method for reference by those skilled in the art, but not as a limitation to the protection scope of the present invention:
  • Texture processing is carried out on the surface of the monocrystalline silicon substrate to form a textured surface, and the monocrystalline silicon substrate is cleaned after texturing;
  • Phosphorus is diffused on the cleaned silicon substrate to generate phosphosilicate glass on the surface, and laser doping is used to form a local re-doped region on the front of the silicon substrate to obtain a selective emitter;
  • the silicon substrate is annealed in a hydrogen-rich atmosphere, the hydrogen-rich atmosphere is a mixed gas of nitrogen and/or an inert gas, and after the annealing is completed, the amorphous silicon oxide film is transformed into a first crystalline silicon oxide layer;
  • step (8) Repeat step (5) and step (6) to form a second crystalline silicon oxide layer on the surface of the gallium oxide layer;
  • the beneficial effects of the present invention include:
  • the present invention provides a PERC battery back passivation structure with a sandwich structure.
  • the main passivation structure is formed by stacking a first crystalline silicon oxide layer, a gallium oxide layer and a second crystalline silicon oxide layer in sequence.
  • the three layers The film is complementary, reduces the recombination rate of the back surface, increases the passivation effect of the back surface and improves the passivation effect.
  • the first crystalline silicon oxide layer is deposited on the surface of the silicon substrate to saturate the dangling bonds on the silicon surface, thereby reducing the interface state density and providing an excellent interface chemical passivation effect
  • the gallium oxide layer is sandwiched between the first crystalline oxide
  • a high concentration of fixed negative charges is formed between the silicon layer and the second crystalline silicon oxide layer.
  • the negative charges can play a field passivation effect on the surface of the silicon substrate, reduce the number carrier recombination in one step, effectively reduce the surface state density, and improve Its chemical passivation effect.
  • the traditional silicon oxide layer mostly uses amorphous silicon oxide, but the silicon-hydrogen bond of amorphous silicon oxide is weak, and the passivation effect is poor.
  • the present invention uses crystalline silicon oxide to replace the traditional amorphous silicon oxide Silicon, although the atomic distribution in amorphous silicon oxide also has a certain order, it is only a short-range order, while the atomic distribution in crystalline silicon oxide has a long-range order. Therefore, compared with amorphous
  • the silicon oxide layer and the crystalline silicon oxide layer have a higher density, better passivation effect, and the interface state defect density can be as low as 10 10 cm -2 eV -1 , which improves the overall performance of the PERC battery.
  • Fig. 1 is a schematic structural diagram of a PERC battery provided by a specific embodiment of the present invention.
  • 1-front electrode 2-front silicon nitride layer; 3-front silicon oxide layer; 4-emitter; 5-silicon substrate; 6-crystalline silicon oxide layer; 7-aluminum oxide layer; 8-back nitrogen Silicon oxide layer; 9-back electrode.
  • Fig. 2 is a schematic structural diagram of a PERC battery provided in another specific embodiment of the present invention.
  • This embodiment provides a preparation method of a PERC battery, and the preparation method includes the following steps:
  • the front silicon oxide layer 3 is deposited on the surface of the selective emitter 4 by a thermal oxidation method, wherein the oxygen flow rate is 1000 sccm, the deposition pressure is 100 Pa, the thermal oxidation temperature is 600° C., and the deposition time is 10 min;
  • silicon base body 5 is put into the film-forming chamber, feeds laughing gas and silane in the film-forming chamber, the feeding flow of laughing gas is 4000sccm, and the feeding flow of silane is 500sccm;
  • the pressure in the film-forming chamber maintains At 1400Pa, the plasma-enhanced chemical vapor deposition method is used to deposit an amorphous silicon oxide film on the back of the silicon substrate 5, the radio frequency power of the plasma is 6000W, and the deposition time is 10s;
  • the silicon substrate 5 is annealed in a hydrogen-rich atmosphere
  • the hydrogen-rich atmosphere is a mixed gas of hydrogen and nitrogen
  • hydrogen accounts for 40% of the total volume of the mixed gas
  • the annealing temperature is 850 ° C
  • the annealing time is 1 min
  • the amorphous silicon oxide film is transformed into a crystalline silicon oxide layer 6;
  • Aluminum oxide layer 7 is deposited on the surface of crystalline silicon oxide by ALD.
  • the deposition process parameters of aluminum oxide layer 7 are: radio frequency power 450W, deposition temperature 350°C, deposition pressure 10Pa, TMA flow rate 300sccm, oxygen flow rate 400sccm, nitrogen gas Flow rate 350sccm, deposition time 8s;
  • PECVD is used to deposit silicon nitride layer 8 on the surface of aluminum oxide layer 7.
  • the deposition process parameters of silicon nitride are: deposition radio frequency power 9000W, deposition temperature 450°C, deposition pressure 300Pa, ammonia flow rate 6250sccm, silane flow rate 680sccm, deposition time 800s;
  • the deposition process parameters of silicon nitride are: deposition radio frequency power 9000W, deposition temperature 450°C, deposition pressure 300Pa, ammonia gas flow rate 6250sccm, silane Flow rate 680sccm, deposition time 800s;
  • the finally prepared PERC battery is shown in Figure 1, including a silicon substrate 5, the front of the silicon substrate 5 is sequentially stacked with an emitter 4, a front silicon oxide layer 3 and a front silicon nitride layer 2, and the thickness of the front silicon oxide layer 3 is The thickness of the front silicon nitride layer 2 is 15 nm, and the front electrode 1 is also provided on the front.
  • the back side of the silicon substrate 5 is stacked with a crystalline silicon oxide layer 6, an aluminum oxide layer 7 and a silicon nitride layer 8 on the back side in sequence.
  • the thickness of the crystalline silicon oxide layer 6 is 5 nm
  • the thickness of the aluminum oxide layer 7 is 5 nm
  • the silicon oxide layer 8 has a thickness of 15 nm
  • a back electrode 9 is provided on the back.
  • This embodiment provides a preparation method of a PERC battery, and the preparation method includes the following steps:
  • a mixed solution of KOH, water and isopropanol is used at 75°C to carry out texturing treatment on the surface of the monocrystalline silicon substrate 5 to form a textured surface.
  • the volume ratio of KOH, water and isopropanol is 10:280: 2.5; cleaning the monocrystalline silicon substrate 5 after texturing;
  • the front silicon oxide layer 3 is deposited on the surface of the selective emitter 4 by a thermal oxidation method, wherein the oxygen flow rate is 1200 sccm, the deposition pressure is 140 Pa, the thermal oxidation temperature is 620° C., and the deposition time is 15 min;
  • silicon substrate 5 is put into the film-forming chamber, feeds laughing gas and silane into the film-forming chamber, the feeding flow rate of laughing gas is 4500 sccm, and the feeding flow rate of silane is 560 sccm; the pressure in the film-forming chamber is maintained At 1450Pa, the plasma-enhanced chemical vapor deposition method is used to deposit an amorphous silicon oxide film on the back of the silicon substrate 5, the radio frequency power of the plasma is 6800W, and the deposition time is 50s;
  • the silicon substrate 5 is annealed in a hydrogen-rich atmosphere
  • the hydrogen-rich atmosphere is a mixed gas of nitrogen and argon
  • hydrogen accounts for 50% of the total volume of the mixed gas
  • the annealing temperature is 950 ° C
  • the annealing time is 3 minutes
  • the amorphous silicon oxide film is transformed into a crystalline silicon oxide layer 6;
  • ALD is used to deposit aluminum oxide layer 7 on the surface of crystalline silicon oxide.
  • the deposition process parameters of aluminum oxide layer 7 are: radio frequency power 450W, deposition temperature 370°C, deposition pressure 10.4Pa, TMA flow rate 320sccm, oxygen flow rate 420sccm, Nitrogen flow rate 360sccm, deposition time 8.5s;
  • PECVD is used to deposit silicon nitride layer 8 on the surface of aluminum oxide layer 7.
  • the deposition process parameters of silicon nitride are: deposition radio frequency power 9000W, deposition temperature 456°C, deposition pressure 250Pa, ammonia gas flow rate 6250sccm, silane flow rate 680sccm, deposition time 830s;
  • a silicon nitride layer is deposited on the surface of the front silicon oxide layer 3 by PECVD.
  • the deposition process parameters of silicon nitride are: deposition radio frequency power 9000W, deposition temperature 456°C, deposition pressure 250Pa, ammonia flow rate 6250sccm, silane flow rate 680sccm , deposition time 830s;
  • the finally prepared PERC cell includes a silicon substrate 5, the front of the silicon substrate 5 is sequentially stacked with an emitter 4, a front silicon oxide layer 3 and a front silicon nitride layer 2, the thickness of the front silicon oxide layer 3 is 3nm, and the front surface is nitrided.
  • the thickness of the silicon layer 2 is 50 nm, and a front electrode 1 is also provided on the front.
  • the back side of the silicon substrate 5 is sequentially stacked with a crystalline silicon oxide layer 6, an aluminum oxide layer 7 and a silicon nitride layer 8 on the back side.
  • the thickness of the crystalline silicon oxide layer 6 is 10 nm, and the thickness of the aluminum oxide layer 7 is 8 nm.
  • the thickness of the silicon layer is 50nm, and a back electrode 9 is provided on the back.
  • This embodiment provides a preparation method of a PERC battery, and the preparation method includes the following steps:
  • silicon base body 5 is put into the film-forming chamber, feeds laughing gas and silane in the film-forming chamber, the feeding flow of laughing gas is 5000sccm, and the feeding flow of silane is 620sccm;
  • the pressure in the film-forming chamber maintains At 1500Pa, the plasma-enhanced chemical vapor deposition method is used to deposit an amorphous silicon oxide film on the back of the silicon substrate 5, the radio frequency power of the plasma is 7600W, and the deposition time is 100s;
  • the silicon substrate 5 is annealed in a hydrogen-rich atmosphere
  • the hydrogen-rich atmosphere is a mixed gas of nitrogen and helium
  • hydrogen accounts for 60% of the total volume of the mixed gas
  • the annealing temperature is 1050° C.
  • the annealing time is 5 minutes
  • the amorphous silicon oxide film is transformed into a crystalline silicon oxide layer 6;
  • ALD is used to deposit aluminum oxide layer 7 on the surface of crystalline silicon oxide.
  • the deposition process parameters of aluminum oxide layer 7 are: radio frequency power 450W, deposition temperature 400°C, deposition pressure 10.8Pa, TMA flow rate 340sccm, oxygen flow rate 440sccm, Nitrogen flow rate 370sccm, deposition time 9s;
  • PECVD is used to deposit silicon nitride layer 8 on the surface of aluminum oxide layer 7.
  • the deposition process parameters of silicon nitride are: deposition radio frequency power 9000W, deposition temperature 462°C, deposition pressure 280Pa, ammonia gas flow rate 6250sccm, silane flow rate 680sccm, deposition time 860s;
  • PECVD is used to deposit a silicon nitride layer on the surface of the front silicon oxide layer 3.
  • the deposition process parameters of silicon nitride are: deposition radio frequency power 9000W, deposition temperature 462°C, deposition pressure 280Pa, ammonia gas flow 6250sccm, silane flow 680sccm , deposition time 860s;
  • the finally prepared PERC battery includes a silicon substrate 5, the front of the silicon substrate 5 is sequentially stacked with an emitter 4, a front silicon oxide layer 3 and a front silicon nitride layer 2, the thickness of the front silicon oxide layer 3 is 2nm, and the front surface is nitrided.
  • the thickness of the silicon layer 2 is 80nm, and a front electrode 1 is provided on the front.
  • the back side of the silicon substrate 5 is sequentially stacked with a crystalline silicon oxide layer 6, an aluminum oxide layer 7 and a silicon nitride layer 8 on the back side.
  • the thickness of the crystalline silicon oxide layer 6 is 15 nm
  • the thickness of the aluminum oxide layer 7 is 8 nm.
  • the thickness of the silicon layer is 80nm, and a back electrode 9 is provided on the back.
  • This embodiment provides a preparation method of a PERC battery, and the preparation method includes the following steps:
  • a mixed solution of KOH, water and isopropanol is used at 82°C to carry out texturing treatment on the surface of the monocrystalline silicon substrate 5 to form a textured surface.
  • the volume ratio of KOH, water and isopropanol is 11:330: 2.5; cleaning the monocrystalline silicon substrate 5 after texturing;
  • the front silicon oxide layer 3 is deposited on the surface of the selective emitter 4 by a thermal oxidation method, wherein the oxygen flow rate is 1600 sccm, the deposition pressure is 220 Pa, the thermal oxidation temperature is 660° C., and the deposition time is 22 minutes;
  • silicon matrix 5 is put into the film-forming chamber, feed laughing gas and silane in the film-forming chamber, the feeding flow of laughing gas is 5300sccm, and the feeding flow of silane is 680sccm;
  • the pressure in the film-forming chamber maintains At 1530Pa, the plasma-enhanced chemical vapor deposition method is used to deposit an amorphous silicon oxide film on the back of the silicon substrate 5, the radio frequency power of the plasma is 8400W, and the deposition time is 150s;
  • the silicon substrate 5 is annealed in a hydrogen-rich atmosphere
  • the hydrogen-rich atmosphere is a mixed gas of nitrogen and nitrogen
  • hydrogen accounts for 65% of the total volume of the mixed gas
  • the annealing temperature is 1150 ° C
  • the annealing time is 10 minutes
  • the amorphous silicon oxide film is transformed into a crystalline silicon oxide layer 6;
  • ALD is used to deposit aluminum oxide layer 7 on the surface of crystalline silicon oxide.
  • the deposition process parameters of aluminum oxide layer 7 are: radio frequency power 450W, deposition temperature 420°C, deposition pressure 11.2Pa, TMA flow rate 360sccm, oxygen flow rate 460sccm, Nitrogen flow rate 380sccm, deposition time 9.3s;
  • PECVD is used to deposit silicon nitride layer 8 on the surface of aluminum oxide layer 7.
  • the deposition process parameters of silicon nitride are: deposition radio frequency power 9000W, deposition temperature 468°C, deposition pressure 250Pa, ammonia flow rate 6250sccm, silane flow rate 680sccm, deposition time 890s;
  • the deposition process parameters of silicon nitride are: deposition radio frequency power 9000W, deposition temperature 468°C, deposition pressure 250Pa, ammonia flow rate 6250sccm, silane flow rate 680sccm , deposition time 890s;
  • the finally prepared PERC battery includes a silicon substrate 5, the front of the silicon substrate 5 is sequentially stacked with an emitter 4, a front silicon oxide layer 3 and a front silicon nitride layer 2, the thickness of the front silicon oxide layer 3 is 4nm, and the front surface is nitrided.
  • the silicon layer 2 has a thickness of 100 nm, and a front electrode 1 is also provided on the front.
  • the back side of the silicon substrate 5 is sequentially stacked with a crystalline silicon oxide layer 6, an aluminum oxide layer 7 and a silicon nitride layer 8 on the back side.
  • the thickness of the crystalline silicon oxide layer 6 is 16 nm
  • the thickness of the aluminum oxide layer 7 is 8 nm.
  • the silicon oxide layer 8 has a thickness of 100 nm, and a back electrode 9 is also provided on the back.
  • This embodiment provides a preparation method of a PERC battery, and the preparation method includes the following steps:
  • the front silicon oxide layer 3 is deposited on the surface of the selective emitter 4 by a thermal oxidation method, wherein the oxygen flow rate is 1800 sccm, the deposition pressure is 260 Pa, the thermal oxidation temperature is 680° C., and the deposition time is 26 minutes;
  • silicon substrate 5 is put into the film-forming chamber, feed laughing gas and silane in the film-forming chamber, the feeding flow of laughing gas is 5600sccm, and the feeding flow of silane is 720sccm;
  • the pressure in the film-forming chamber maintains At 1560Pa, the plasma-enhanced chemical vapor deposition method is used to deposit an amorphous silicon oxide film on the back of the silicon substrate 5, the radio frequency power of the plasma is 9200W, and the deposition time is 200s;
  • the silicon substrate 5 is annealed in a hydrogen-rich atmosphere
  • the hydrogen-rich atmosphere is a mixed gas of nitrogen and argon
  • hydrogen accounts for 70% of the total volume of the mixed gas
  • the annealing temperature is 1250 ° C
  • the annealing time is 15 minutes
  • the amorphous silicon oxide film is transformed into a crystalline silicon oxide layer 6;
  • Aluminum oxide layer 7 is deposited on the surface of crystalline silicon oxide by ALD.
  • the deposition process parameters of aluminum oxide layer 7 are: radio frequency power 450W, deposition temperature 440°C, deposition pressure 11.6Pa, TMA flow rate 380sccm, oxygen flow rate 480sccm, Nitrogen flow rate 390sccm, deposition time 9.6s;
  • PECVD is used to deposit silicon nitride layer 8 on the surface of aluminum oxide layer 7.
  • the deposition process parameters of silicon nitride are: deposition radio frequency power 9000W, deposition temperature 475°C, deposition pressure 300Pa, ammonia flow rate 6250sccm, silane flow rate 680sccm, deposition time 920s;
  • silicon nitride layer Use PECVD to deposit a silicon nitride layer on the surface of the front silicon oxide layer 3.
  • the deposition process parameters of silicon nitride are: deposition radio frequency power 9000W, deposition temperature 475°C, deposition pressure 300Pa, ammonia flow rate 6250sccm, silane flow rate 680sccm , the deposition time is 920s;
  • the finally prepared PERC cell includes a silicon substrate 5, the front of the silicon substrate 5 is sequentially stacked with an emitter 4, a front silicon oxide layer 3 and a front silicon nitride layer 2, the thickness of the front silicon oxide layer 3 is 3nm, and the front surface is nitrided.
  • the silicon layer 2 has a thickness of 150 nm, and a front electrode 1 is also provided on the front.
  • the back side of the silicon substrate 5 is sequentially stacked with a crystalline silicon oxide layer 6, an aluminum oxide layer 7 and a silicon nitride layer 8 on the back side.
  • the thickness of the crystalline silicon oxide layer 6 is 18 nm
  • the thickness of the aluminum oxide layer 7 is 10 nm.
  • the silicon oxide layer 8 has a thickness of 18nm, and a back electrode 9 is also provided on the back.
  • This embodiment provides a preparation method of a PERC battery, and the preparation method includes the following steps:
  • a mixed solution of KOH, water and isopropanol is used at 90°C to carry out texturing treatment on the surface of the monocrystalline silicon substrate 5 to form a textured surface.
  • the volume ratio of KOH, water and isopropanol is 12:360: 3. Cleaning the monocrystalline silicon substrate 5 after texturing;
  • the front silicon oxide layer 3 is deposited on the surface of the selective emitter 4 by a thermal oxidation method, wherein the oxygen flow rate is 2000 sccm, the deposition pressure is 300 Pa, the thermal oxidation temperature is 700° C., and the deposition time is 30 min;
  • silicon substrate 5 is put into the film-forming chamber, feeds laughing gas and silane into the film-forming chamber, the feeding flow rate of laughing gas is 6000 sccm, and the feeding flow rate of silane is 800 sccm; the pressure in the film-forming chamber is maintained At 1600Pa, the plasma-enhanced chemical vapor deposition method is used to deposit an amorphous silicon oxide film on the back of the silicon substrate 5, the radio frequency power of the plasma is 10000W, and the deposition time is 300s;
  • the silicon substrate 5 is annealed in a hydrogen-rich atmosphere
  • the hydrogen-rich atmosphere is a mixed gas of nitrogen and helium
  • hydrogen accounts for 80% of the total volume of the mixed gas
  • the annealing temperature is 1300 ° C
  • the annealing time is 20 minutes
  • the amorphous silicon oxide film is transformed into a crystalline silicon oxide layer 6;
  • ALD is used to deposit aluminum oxide layer 7 on the surface of crystalline silicon oxide.
  • the deposition process parameters of aluminum oxide layer 7 are: radio frequency power 450W, deposition temperature 450°C, deposition pressure 12Pa, TMA flow rate 400sccm, oxygen flow rate 500sccm, nitrogen gas Flow rate 400sccm, deposition time 10s;
  • PECVD is used to deposit silicon nitride layer 8 on the surface of aluminum oxide layer 7.
  • the deposition process parameters of silicon nitride are: deposition radio frequency power 9000W, deposition temperature 480°C, deposition pressure 200Pa, ammonia flow rate 6250sccm, silane flow rate 680sccm, deposition time 950s;
  • a silicon nitride layer is deposited on the surface of the front silicon oxide layer 3 by PECVD.
  • the deposition process parameters of silicon nitride are: deposition radio frequency power 9000W, deposition temperature 480°C, deposition pressure 200Pa, ammonia flow rate 6250 sccm, silane flow rate 680 sccm , the deposition time is 950s;
  • the finally prepared PERC battery includes a silicon substrate 5, the front of the silicon substrate 5 is sequentially stacked with an emitter 4, a front silicon oxide layer 3 and a front silicon nitride layer 2, the thickness of the front silicon oxide layer 3 is 5nm, and the front surface is nitrided.
  • the thickness of the silicon layer 2 is 200nm, and a front electrode 1 is provided on the front.
  • the back side of the silicon substrate 5 is sequentially stacked with a crystalline silicon oxide layer 6, an aluminum oxide layer 7 and a silicon nitride layer 8 on the back side.
  • the thickness of the crystalline silicon oxide layer 6 is 20 nm, and the thickness of the aluminum oxide layer 7 is 10 nm.
  • the silicon oxide layer 8 has a thickness of 200 nm, and a back electrode 9 is provided on the back.
  • This example provides a method for preparing a PERC battery.
  • the difference from Example 3 is that the annealing temperature in step (6) is adjusted to 800° C., and other process parameters and operating steps are exactly the same as Example 3.
  • This example provides a method for preparing a PERC battery.
  • the difference from Example 3 is that the annealing temperature in step (6) is adjusted to 1400° C., and other process parameters and operating steps are exactly the same as Example 3.
  • This embodiment provides a preparation method of a PERC battery, and the preparation method includes the following steps:
  • the front silicon oxide layer 3 is deposited on the surface of the selective emitter 4 by a thermal oxidation method, wherein the oxygen flow rate is 1400 sccm, the deposition pressure is 180 Pa, the thermal oxidation temperature is 640° C., and the deposition time is 20 min;
  • a crystalline silicon oxide layer 6 is deposited on the back of the silicon substrate 5 by a thermal oxidation method, wherein the oxygen flow rate is 1400 sccm, the deposition pressure is 180 Pa, the thermal oxidation temperature is 640° C., and the deposition time is 20 minutes;
  • ALD is used to deposit aluminum oxide layer 7 on the surface of crystalline silicon oxide.
  • the deposition process parameters of aluminum oxide layer 7 are: radio frequency power 450W, deposition temperature 400°C, deposition pressure 10.8Pa, TMA flow rate 340sccm, oxygen flow rate 440sccm, Nitrogen flow rate 370sccm, deposition time 9s;
  • PECVD is used to deposit silicon nitride layer 8 on the surface of aluminum oxide layer 7.
  • the deposition process parameters of silicon nitride are: deposition radio frequency power 9000W, deposition temperature 462°C, deposition pressure 280Pa, ammonia gas flow rate 6250sccm, silane flow rate 680sccm, deposition time 860s;
  • PECVD is used to deposit a silicon nitride layer on the surface of the front silicon oxide layer 3.
  • the deposition process parameters of silicon nitride are: deposition radio frequency power 9000W, deposition temperature 462°C, deposition pressure 280Pa, ammonia flow rate 6250sccm, silane flow rate 680sccm , deposition time 860s;
  • the finally prepared PERC cell includes a silicon substrate 5, the front of the silicon substrate 5 is sequentially stacked with an emitter 4, a front silicon oxide layer 3 and a front silicon nitride layer 2, the thickness of the front silicon oxide layer 3 is 2nm, and the front surface is nitrided.
  • the thickness of the silicon layer 2 is 80nm, and a front electrode 1 is also provided on the front.
  • the back side of the silicon substrate 5 is sequentially stacked with a back silicon oxide layer, an aluminum oxide layer 7 and a back silicon nitride layer 8, the thickness of the back silicon oxide layer is 2nm, the thickness of the aluminum oxide layer 7 is 8nm, and the thickness of the silicon nitride layer The thickness is 80nm, and a back electrode 9 is also provided on the back.
  • This embodiment provides a preparation method of a PERC battery, and the preparation method includes the following steps:
  • the front silicon oxide layer 3 is deposited on the surface of the selective emitter 4 by a thermal oxidation method, wherein the oxygen flow rate is 1400 sccm, the deposition pressure is 180 Pa, the thermal oxidation temperature is 640° C., and the deposition time is 20 min;
  • silicon base body 5 is put into the film-forming chamber, feeds laughing gas and silane in the film-forming chamber, the feeding flow of laughing gas is 5000sccm, and the feeding flow of silane is 620sccm;
  • the pressure in the film-forming chamber maintains At 1500Pa, the plasma-enhanced chemical vapor deposition method is used to deposit an amorphous silicon oxide layer on the back of the silicon substrate 5, the radio frequency power of the plasma is 7600W, and the deposition time is 100s;
  • ALD is used to deposit aluminum oxide layer 7 on the surface of amorphous silicon oxide layer.
  • the deposition process parameters of aluminum oxide layer 7 are: radio frequency power 450W, deposition temperature 400°C, deposition pressure 10.8Pa, TMA flow rate 340sccm, oxygen flow rate 440sccm, nitrogen flow rate 370sccm, deposition time 9s;
  • PECVD is used to deposit silicon nitride layer 8 on the surface of aluminum oxide layer 7.
  • the deposition process parameters of silicon nitride are: deposition radio frequency power 9000W, deposition temperature 462°C, deposition pressure 280Pa, ammonia gas flow rate 6250sccm, silane flow rate 680sccm, deposition time 860s;
  • the deposition process parameters of silicon nitride are: deposition radio frequency power 9000W, deposition temperature 462°C, deposition pressure 280Pa, ammonia gas flow 6250sccm, silane flow 680sccm , deposition time 860s;
  • the finally prepared PERC battery includes a silicon substrate 5, the front of the silicon substrate 5 is sequentially stacked with an emitter 4, a front silicon oxide layer 3 and a front silicon nitride layer 2, the thickness of the front silicon oxide layer 3 is 15nm, and the front surface is nitrided.
  • the thickness of the silicon layer 2 is 80nm, and a front electrode 1 is also provided on the front.
  • the back side of the silicon substrate 5 is sequentially stacked with a crystalline silicon oxide layer 6, an aluminum oxide layer 7 and a silicon nitride layer 8 on the back side.
  • the thickness of the crystalline silicon oxide layer 6 is 15 nm
  • the thickness of the aluminum oxide layer 7 is 8 nm.
  • the thickness of the silicon layer is 80nm, and a back electrode 9 is provided on the back.
  • Example 1 0.696 11.195 81.28 23.10
  • Example 2 0.695 11.196 81.09 23.05
  • Example 3 0.696 11.196 81.10 23.05
  • Example 4 0.696 11.197 81.12 23.06
  • Example 5 0.697 11.198 81.14 23.10
  • Example 6 0.697 11.196 81.18 23.08
  • Example 7 0.697 11.198 81.05 23.02
  • Example 8 0.696 11.197 81.03 23.01 Comparative example 1 0.695 11.197 80.69 22.90 Comparative example 2 0.692 11.196 80.53 22.76
  • the interface state defect density of embodiment 3 is slightly lower than comparative example 1, illustrates that the passivation effect of embodiment 3 is better than comparative example 1, and this is because comparative example 1 has only adopted thermal oxidation method to prepare silicon oxide, and implements Example 3 is the combination of PECVD and thermal oxidation to prepare silicon oxide. Although both of them are crystalline silicon oxide, the thickness of the silicon oxide layer prepared in Comparative Example 1 is much smaller than that in Example 3 (Comparative Example 1 The thickness of the crystalline silicon oxide layer 6 is 2 nm, and the thickness of the crystalline silicon oxide layer 6 in Example 3 is 15 nm), so the passivation effect of Comparative Example 1 is inferior to that of Example 3.
  • Example 3 The interface state defect density of Example 3 is much lower than that of Comparative Example 2, indicating that the passivation effect of Example 3 is far superior to that of Comparative Example 2. This is due to the joint preparation of Example 3 by PECVD and thermal oxidation. Crystalline silicon oxide, while the comparative example 2 only adopts PECVD to prepare amorphous silicon oxide, and the passivation effect of crystalline silicon oxide is better than that of amorphous silicon oxide.
  • the present invention adopts PECVD and thermal oxidation method to jointly prepare silicon oxide, the thickness defect of thermal oxidation method is remedied by PECVD, and the amorphous state defect of PECVD is remedied by thermal oxidation method. Thick crystalline silicon oxide layer 6 .
  • the present invention provides a rear passivation structure for PERC cells, as shown in FIG. A silicon oxide layer 16 , a gallium oxide layer 17 , a second crystalline silicon oxide layer 18 and at least two backside silicon nitride layers 19 .
  • the thickness of the first crystalline silicon oxide layer 16 is 1-10 nm
  • the thickness of the gallium oxide layer 17 is 5-10 nm
  • the thickness of the second crystalline silicon oxide layer 18 is 1-10 nm
  • the total of the silicon nitride layer 19 on the back is The thickness is 40-80 nm, and the thickness of the silicon nitride layer 19 on the back of each layer gradually decreases from the inside to the outside.
  • a connection block 111 is provided at the contact surface between the silicon substrate 15 and the first crystalline silicon oxide layer 16 , the connection block 111 is integrated with the first crystalline silicon oxide layer 16 , and the connection block 111 is embedded in the silicon substrate 15 .
  • a first fixed block 112 is provided at the contact surface between the first crystalline silicon oxide layer 16 and the gallium oxide layer 17.
  • the first fixed block 112 and the gallium oxide layer 17 have an integrated structure, and the first fixed block 112 is embedded in the first crystalline oxide layer. inside the silicon layer 16 .
  • a second fixed block 113 is provided at the contact surface between the gallium oxide layer 17 and the second crystalline silicon oxide layer 18.
  • the second fixed block 113 is integrated with the gallium oxide layer 17.
  • the second fixed block 113 is embedded in the second crystalline silicon oxide layer 18. inside the silicon layer 18 .
  • the present invention provides a PERC cell.
  • the PERC cell includes a silicon substrate 15, and the front side of the silicon substrate 15 is sequentially stacked with an emitter 14, a front silicon oxide layer 13 and the front silicon nitride layer 12, and the back side of the silicon substrate 15 is provided with the rear passivation structure of the PERC battery as provided in the above-mentioned specific embodiment.
  • the PERC battery also includes a front electrode 11 and a back electrode 110, the front electrode 11 is vertically inserted into the silicon substrate 15 from the front of the PERC battery, and the back electrode 110 is vertically inserted into the silicon substrate 15 from the back of the PERC battery.
  • This embodiment provides a PERC battery.
  • the PERC battery is based on the PERC battery provided in a specific embodiment, wherein the thickness of the first crystalline silicon oxide layer 16 is 1 nm, and the thickness of the gallium oxide layer 17 is 5 nm.
  • the thickness of the silicon dioxide layer is 1nm
  • the back silicon nitride layer 19 has two layers, which are respectively recorded as the first back silicon nitride layer and the second back silicon nitride layer, and the thickness of the first back silicon nitride layer is 15nm.
  • the thickness of the second back silicon nitride layer is 25nm.
  • This embodiment provides a PERC battery.
  • the PERC battery is based on the PERC battery provided in a specific embodiment, wherein the thickness of the first crystalline silicon oxide layer 16 is 3 nm, and the thickness of the gallium oxide layer 17 is 6 nm.
  • the thickness of the dicrystalline silicon oxide layer 18 is 3nm, and the back silicon nitride layer 19 has two layers, which are respectively recorded as the first back silicon nitride layer and the second back silicon nitride layer, and the thickness of the first back silicon nitride layer
  • the thickness of the second backside silicon nitride layer is 30nm.
  • This embodiment provides a PERC battery.
  • the PERC battery is based on the PERC battery provided in a specific embodiment, wherein the thickness of the first crystalline silicon oxide layer 16 is 5 nm, and the thickness of the gallium oxide layer 17 is 7 nm.
  • the thickness of the dicrystalline silicon oxide layer 18 is 5nm
  • the back silicon nitride layer 19 has three layers, which are respectively denoted as the first back silicon nitride layer, the second back silicon nitride layer and the third back silicon nitride layer.
  • the thickness of the first back silicon nitride layer is 10nm
  • the thickness of the second back silicon nitride layer is 20nm
  • the thickness of the third back silicon nitride layer is 30nm.
  • This embodiment provides a PERC battery.
  • the PERC battery is based on the PERC battery provided in a specific embodiment, wherein the thickness of the first crystalline silicon oxide layer 16 is 7 nm, and the thickness of the gallium oxide layer 17 is 8 nm.
  • the thickness of the dicrystalline silicon oxide layer 18 is 7nm
  • the back silicon nitride layer 19 consists of two layers, respectively denoted as the first back silicon nitride layer, the second back silicon nitride layer and the third back silicon nitride layer, and the second back silicon nitride layer.
  • the thickness of the first back silicon nitride layer is 15nm
  • the thickness of the second back silicon nitride layer is 25nm
  • the thickness of the third back silicon nitride layer is 30nm.
  • This embodiment provides a PERC battery.
  • the PERC battery is based on the PERC battery provided in a specific embodiment, wherein the thickness of the first crystalline silicon oxide layer 16 is 9 nm, and the thickness of the gallium oxide layer 17 is 9 nm.
  • the thickness of the dicrystalline silicon oxide layer 18 is 9nm, and the back silicon nitride layer 19 has four layers in total, which are respectively denoted as the first back silicon nitride layer, the second back silicon nitride layer, the third back silicon nitride layer and the second back silicon nitride layer.
  • the thickness of the first back silicon nitride layer is 5nm
  • the thickness of the second back silicon nitride layer is 10nm
  • the thickness of the third back silicon nitride layer is 20nm
  • the fourth back silicon nitride layer The thickness is 30nm.
  • This embodiment provides a PERC battery.
  • the PERC battery is based on the PERC battery provided in a specific embodiment, wherein the thickness of the first crystalline silicon oxide layer 16 is 10 nm, and the thickness of the gallium oxide layer 17 is 10 nm.
  • the thickness of the dicrystalline silicon oxide layer 18 is 10nm, and the back silicon nitride layer 19 has four layers in total, which are respectively recorded as the first back silicon nitride layer, the second back silicon nitride layer, the third back silicon nitride layer and the second back silicon nitride layer.
  • the thickness of the first back silicon nitride layer is 10nm
  • the thickness of the second back silicon nitride layer is 15nm
  • the thickness of the third back silicon nitride layer is 25nm
  • the fourth back silicon nitride layer The thickness is 30nm.
  • This embodiment provides a preparation method of the PERC battery described in Embodiment 3 ' , the preparation method comprising the following steps:
  • silicon matrix 15 is put into the film-forming chamber, feed laughing gas and silane in the film-forming chamber, the feeding flow rate of laughing gas is 5000 sccm, and the feeding flow rate of silane is 620 sccm;
  • the pressure in the film-forming chamber is maintained At 1500Pa, the plasma-enhanced chemical vapor deposition method is used to deposit an amorphous silicon oxide film on the back of the silicon substrate 15, the radio frequency power of the plasma is 7600W, and the deposition time is 100s;
  • the silicon substrate 15 is annealed in a hydrogen-rich atmosphere
  • the hydrogen-rich atmosphere is a mixed gas of nitrogen and helium
  • hydrogen accounts for 60% of the total volume of the mixed gas
  • the annealing temperature is 1050° C.
  • the annealing time is 5 minutes
  • the amorphous silicon oxide film is transformed into a first crystalline silicon oxide layer 16 with a thickness of 5 nm;
  • ALD is used to deposit a gallium oxide layer 17 with a thickness of 7 nm on the surface of the first crystalline silicon oxide layer 16;
  • step (8) repeating step (5) and step (6), depositing and forming the second crystalline silicon oxide layer 18 with a thickness of 5 nm on the gallium oxide layer 17 surface;

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Abstract

本发明提供了一种PERC电池背钝化结构、PERC电池及制备方法，所述的PERC电池背钝化结构包括设置于硅基体背面的晶态氧化硅层。本发明还提供了一种PERC电池背钝化结构及包括其的PERC电池，所述的PERC电池背钝化结构包括由硅基体的背面依次层叠设置的第一晶态氧化硅层、氧化镓层、第二晶态氧化硅层以及至少两层背面氮化硅层。

Description

一种PERC电池背钝化结构、PERC电池及制备方法 技术领域
本发明属于光伏电池技术领域，涉及一种PERC电池背钝化结构、PERC电池及制备方法。
背景技术
PERC电池即钝化发射极和背面电池技术，起源于上世纪80年代，通过在常规电池的背面叠加钝化层，可以提高转化效率。PERC电池一般的工艺流程有以下步骤：制绒→扩散→SE激光→氧化→刻蚀(去PSG)→退火→背膜→正膜→激光开槽→丝网印刷→烧结→光注入或电注入→测试分拣。其中镀膜工艺是PERC电池产线工艺中及其重要的一环。电池片在生产过程中，需要在正面镀一层减反膜，降低光的反射，增强光的吸收。在背面镀一层钝化膜，一般钝化膜是通过钝化硅表面的悬挂键来降低表面的复合速率从而起到表面钝化或者体钝化的作用。同时其高折射率可以增强背面的反射率进一步提升电池效率，可以说钝化膜的好坏直接影响到太阳能电池的性能。
二氧化硅是一种很好的钝化材料，产业化的SiO 2薄膜生长方式主要是热氧化法，将硅片放入高温的石英炉管内，硅片表面在氧化物质作用下生长SiO 2膜，根据氧化气氛的不同，又可以多采用热氧化分为干氧氧化、水汽氧化和湿氧氧化。该氧化层能够有效降低界面态缺陷密度。Si-SiO 2界面起主导作用的是饱和悬挂键的化学钝化效果，在Si-SiO 2界面带有一定的固定正电荷，电荷密度量级在1010cm -2，其电荷量同退火处理条件相关，相较于AlO x的固定负电荷(1012cm -2)可以忽略不计，即SiO x钝化膜所带的正电荷基本不会影响AlO x的场钝化效应，不过热氧化生长的一个缺陷生长速度比较慢，且厚度长不了太厚。
CN105470349A公开一种PERC太阳能电池及其制备方法，其中PERC太阳能电池包括硅片、位于硅片上表面的二氧化硅层和银层、位于二氧化硅层上表面的正面氮化硅钝化层、位于硅片下表面的氧化铝钝化层、位于氧化铝钝化层下表面的背面氮化硅钝化层，在背面氮化硅钝化层上间隔开设有若干个开孔，在开孔中填充有腐蚀掉氧化铝钝化层后与硅片形成铝硅合金的铝层。本发明在背面氮化硅钝化层上通过激光开孔方式开孔，孔的深度控制在打穿背面氮化硅钝化层而不打穿氧化铝钝化层，然后印刷铝浆，通过烧结工艺，铝浆腐蚀掉氧化铝钝化层后与硅片形成铝硅合金。
CN209515679U公开了一种PERC电池结构，包括：衬底、正面二氧化硅层、 抗反射层、正面氮化硅层、背面钝化层，以及保护结构；所述正面二氧化硅层设于所述衬底的正面，所述抗反射层设于所述正面二氧化硅层的与所述衬底相背的一侧，所述正面氮化硅层设于所述抗反射层的与所述正面二氧化硅层相背的一侧。
CN110854240A公开了一种PERC电池及其制备方法，制备方法包括制绒、扩散、刻蚀、背面抛光、退火、背面镀膜及正面镀膜。背面镀膜步骤包括：向装有退火后的硅片的设备中通入臭氧气体进行氧化处理，使硅片的背面形成背面二氧化硅层。然后在同一设备中继续通入臭氧作为氧源，并加入铝源，在背面二氧化硅层上沉积背面氧化铝层。在背面氧化铝层上沉积背面氮化硅层。
目前，常用的二氧化硅层的沉积方法为等离子体增强化学气相沉积法(PECVD)，利用硅烷和笑气沉积氧化硅，PECVD生长速度较快，可沉积的氧化硅薄膜也较厚，但其结构较疏松，钝化效果较差。
发明内容
针对现有技术存在的不足，本发明的目的在于提供一种PERC电池背钝化结构、PERC电池及制备方法，本发明采用晶态氧化硅替换传统的非晶态氧化硅，晶态氧化硅中的原子分布具有长程有序性，因此，相比于非晶态氧化硅层，晶态氧化硅层的致密程度更高，钝化效果更好，界面态缺陷密度可以低至10 10cm -2eV -1，提升了PERC电池的综合性能。
为达此目的，本发明采用以下技术方案：
第一方面，本发明提供了一种PERC电池背钝化结构，所述的PERC电池背钝化结构包括设置于硅基体背面的晶态氧化硅层。
PERC电池的背钝化结构中的氧化硅层多采用非晶态氧化硅，但非晶态氧化硅的硅氢键结合较弱，钝化效果较差，本发明采用晶态氧化硅替换传统的非晶态氧化硅，虽然非晶态氧化硅中的原子分布也具有一定的有序性，但只是短程有序性，而晶态氧化硅中的原子分布具有长程有序性，因此，相比于非晶态氧化硅层，晶态氧化硅层的致密程度更高，钝化效果更好，界面态缺陷密度可以低至10 10cm -2eV -1，提升了PERC电池的综合性能。
需要说明的是，本发明要求保护的背钝化结构是PERC电池中的部分结构，可以理解的是，在此限定的保护范围之内，对PERC电池中的其他结构并未进行具体要求和特殊限定，换言之，在本发明限定的背钝化结构的基础上，本领域技术人员可以基于现有技术对其他结构进行常规替换或创造性改进。
示例性地，本发明提供了一种PERC电池的完整结构，包括硅基体，硅基 体的正面依次层叠设置有发射极、正面氧化硅层和正面氮化硅层(正面氮化硅层可以替换为氮氧化硅层或碳化硅层)，同时，正面还垂直插入了正面电极。硅基体的背面依次层叠设置有晶态氧化硅层、氧化铝层和背面氮化硅层(背面氮化硅层可以替换为氮氧化硅层或碳化硅层)，同时，背面还垂直插入了背面电极。本领域技术人员可以对除晶态氧化硅层之外的其余各层进行创造性改进，或改进材料，或增加其他功能层，或剔除其中某层，当然，无论进行何种改进方式，只要采用了本发明提供的背钝化结构，那么改进后的PERC电池同样落入本发明的保护范围和公开范围之内。
作为本发明一种优选的技术方案，所述的晶态氧化硅层的厚度为1～20nm，例如可以是1nm、2nm、3nm、4nm、5nm、6nm、7nm、8nm、9nm、10nm、11nm、12nm、13nm、14nm、15nm、16nm、17nm、18nm、19nm或20nm，但并不仅限于所列举的数值，该数值范围内其他未列举的数值同样适用。
作为本发明一种优选的技术方案，所述晶态氧化硅层的表面依次层叠设置有氧化铝层和背面氮化硅层。
所述的氧化铝层的厚度为5～10nm，例如可以是5nm、5.5nm、6nm、6.5nm、7nm、7.5nm、8nm、8.5nm、9nm、9.5nm或10nm，但并不仅限于所列举的数值，该数值范围内其他未列举的数值同样适用。
所述的背面氮化硅层的厚度为10～200nm，例如可以是10nm、20nm、30nm、40nm、50nm、60nm、70nm、80nm、90nm、100nm、110nm、120nm、130nm、140nm、150nm、160nm、170nm、180nm、190nm或200nm，但并不仅限于所列举的数值，该数值范围内其他未列举的数值同样适用。
第二方面，本发明提供了一种第一方面所述的PERC电池背钝化结构的制备方法，所述的制备方法包括：
硅基体背面沉积形成非晶态氧化硅薄膜，经退火处理后，非晶态氧化硅薄膜转变为晶态氧化硅层。
本发明首先在硅基体背面沉积形成非晶态氧化硅薄膜，但非晶态氧化硅薄膜的结构较疏松，沉积的氧化硅均是非晶态，硅氢键结合较弱，钝化效果较差。随后经过退火处理后，使得非晶态的氧化硅逐渐转变成富氢的晶态氧化硅，大大增强了钝化效果，最终得到较厚且钝化效果较好的晶态氧化硅层，界面态缺陷密度可以低至10 10cm -2eV -1，提升了太阳能电池的综合性能。
作为本发明一种优选的技术方案，所述的非晶态氧化硅薄膜的沉积过程具体包括：
将硅基体放入成膜腔室内，向成膜腔室内通入笑气和硅烷，维持成膜腔室内的压力，采用等离子体增强化学气相沉积法在硅基体背面沉积形成非晶态氧化硅薄膜。
本发明将PECVD和热氧化法加以结合制备得到了单晶PERC电池的背钝化结构，首先，通过PECVD的方式，利用硅烷和笑气在等离子体的辅助下沉积形成氧化硅层，相较于热氧化，采用PECVD法沉积氧化硅层的生长速度较快，可沉积的氧化硅层也较厚，但相应地，氧化硅层结构较疏松，沉积的氧化硅均是非晶态，硅氢键结合较弱，钝化效果劣于热氧化法形成的氧化硅层。在次基础上，本发明通过热氧化法，使得非晶态的氧化硅逐渐转变成晶态氧化硅，大大增强了钝化效果，最终得到较厚且钝化效果较好的晶态氧化硅层，界面态缺陷密度可以低至10 10cm -2eV -1，提升了太阳能电池的综合性能。
作为本发明一种优选的技术方案，所述笑气的通入流量为4000～6000sccm，例如可以是4000sccm、4200sccm、4400sccm、4600sccm、4800sccm、5000sccm、5200sccm、5400sccm、5600sccm、5800sccm或6000sccm，但并不仅限于所列举的数值，该数值范围内其他未列举的数值同样适用。
所述硅烷的通入流量为500～800sccm，例如可以是500sccm、520sccm、540sccm、560sccm、580sccm、600sccm、620sccm、640sccm、660sccm、680sccm、700sccm、720sccm、740sccm、760sccm、780sccm或800sccm，但并不仅限于所列举的数值，该数值范围内其他未列举的数值同样适用。
所述成膜腔室内的压力维持在1400～1600Pa，例如可以是1400Pa、1420Pa、1440Pa、1460Pa、1480Pa、1500Pa、1520Pa、1540Pa、1560Pa、1580Pa或1600Pa，但并不仅限于所列举的数值，该数值范围内其他未列举的数值同样适用。
所述等离子体的射频功率为6000～10000W，例如可以是6000W、6500W、7000W、7500W、8000W、8500W、9000W、9500W或10000W，但并不仅限于所列举的数值，该数值范围内其他未列举的数值同样适用。
所述的沉积时间为10～300s，例如可以是10s、50s、100s、150s、200s、250s或300s，但并不仅限于所列举的数值，该数值范围内其他未列举的数值同样适用。
作为本发明一种优选的技术方案，所述的退火过程在富氢气氛下进行。
所述的富氢气氛为包括氢气的混合气体，所述氢气占混合气体总体积的40～80％，例如可以是40％、45％、50％、55％、60％、65％、70％、75％或80％，但并不仅限于所列举的数值，该数值范围内其他未列举的数值同样适用。
在本发明中，由于Si和SiO 2的界面处会存在较多硅原子的悬挂键(即未与氧原子结合的价键)，悬挂键的存在会影响界面态缺陷密度，从而降低二氧化硅层的钝化效果。因此，本发明在富氢气氛下进行退火处理，使得氢原子进入到界面中并与悬挂键形成Si-H键，以减小界面处存在的悬挂键，减小Si/SiO 2界面态密度，提高二氧化硅层的钝化效果。
所述的混合气体中还包括氮气和/或惰性气体。
作为本发明一种优选的技术方案，所述的退火温度为850～1300℃，例如可以是850℃、900℃、950℃、1000℃、1050℃、1100℃、1150℃、1200℃、1250℃或1300℃，但并不仅限于所列举的数值，该数值范围内其他未列举的数值同样适用。
本发明特别限定了退火温度为850～1300℃，当退火温度低于850℃时，导致温度达不到SiO 2的晶化温度，当退火温度高于1300℃时，导致能耗变大，对硅片的热损伤程度也加大。
所述的退火时间为1～20min，例如可以是1min、2min、3min、4min、5min、6min、7min、8min、9min、10min、11min、12min、13min、14min、15min、16min、17min、18min、19min或20min，但并不仅限于所列举的数值，该数值范围内其他未列举的数值同样适用。
作为本发明一种优选的技术方案，所述的制备方法还包括：在晶态氧化硅层表面依次沉积形成氧化铝层和背面氮化硅层。
第三方面，一种包括第一方面所述的PERC电池背钝化结构的PERC电池，所述的PERC电池包括硅基体，所述的PERC电池包括硅基体，所述硅基体的正面依次层叠设置有发射极、正面氧化硅层和正面氮化硅层，所述硅基体的背面设置有第一方面所述的背钝化结构。
所述的PERC电池还包括正面电极和背面电极，所述的正面电极由PERC电池的正面垂直插入至硅基体内，所述的背面电极由PERC电池的背面垂直插入至硅基体内。
需要说明的是，本发明特别限定了晶态氧化硅层的制备方法为PECVD和热氧化法，但对于PERC电池中其他层结构的制备方法并未作出具体要求和特殊限定。示例性地，本发明提供了如下制备方法供本领域技术人员参考，但不作为对本发明保护范围的限定：
(1)对单晶硅基体的表面进行制绒处理，形成绒面，制绒后对单晶硅基体进行清洗；
(2)对清洗好的硅基体进行磷扩散，表面生成磷硅玻璃，采用激光掺杂在硅基体正面形成局部重掺区，得到选择性发射极；
(3)通过HF水溶液刻蚀去除硅基体其余表面的磷硅玻璃；
(4)采用热氧化法在选择性发射极表面沉积形成正面氧化硅层；
(5)将硅基体放入成膜腔室内，向成膜腔室内通入笑气和硅烷，采用等离子体增强化学气相沉积法在硅基体背面沉积形成非晶态氧化硅薄膜；
(6)随后在富氢气氛下对硅基体进行退火处理，富氢气氛为氮气和/或惰性气体的混合气体，退火完成后，非晶态氧化硅薄膜转变为晶态氧化硅层；
(7)采用ALD在晶态氧化硅表面沉积形成氧化铝层；
(8)采用PECVD在氧化铝层表面沉积形成背面氮化硅层；
(9)采用PECVD在正面氧化硅层表面沉积形成正面氮化硅层；
(10)通过丝网印刷和烧结在硅片的正面和背面分别形成正面电极和背面电极。
与现有技术相比，本发明的有益效果包括：
PERC电池的背钝化结构中的氧化硅层多采用非晶态氧化硅，但非晶态氧化硅的硅氢键结合较弱，钝化效果较差，本发明采用晶态氧化硅替换传统的非晶态氧化硅，虽然非晶态氧化硅中的原子分布也具有一定的有序性，但只是短程有序性，而晶态氧化硅中的原子分布具有长程有序性，因此，相比于非晶态氧化硅层，晶态氧化硅层的致密程度更高，钝化效果更好，界面态缺陷密度可以低至10 10cm -2eV -1，提升了PERC电池的综合性能。
本发明的目的还在于提供一种PERC电池背钝化结构及包括其的PERC电池，本发明提供了一种三明治结构的PERC电池背钝化结构，主要的钝化结构由第一晶态氧化硅层、氧化镓层和第二晶态氧化硅层依次层叠形成，三层膜互补，降低背表面复合速率，增加背表面钝化效果和提高钝化效果。
为达此目的，本发明采用以下技术方案：
第四方面，本发明提供了一种PERC电池背钝化结构，所述的PERC电池背钝化结构包括由硅基体的背面依次层叠设置的第一晶态氧化硅层、氧化镓层、第二晶态氧化硅层以及至少两层背面氮化硅层。
本发明提供了一种三明治结构的PERC电池背钝化结构，主要的钝化结构由第一晶态氧化硅层、氧化镓层和第二晶态氧化硅层依次层叠形成，三层膜互补，降低背表面复合速率，增加背表面钝化效果和提高钝化效果。具体而言：第一晶态氧化硅层沉积在硅基体表面用于饱和硅表面的悬挂键，从而降低界面 态密度，提供优良的界面化学钝化效应，氧化镓层夹在第一晶态氧化硅层和第二晶态氧化硅层之间，从而形成高浓度的固定负电荷，负电荷对硅基体表面能起到场钝化作用，一步减少数载流子复合，有效降低表面态密度，提升其化学钝化效果。
此外，传统的氧化硅层多采用非晶态氧化硅，但非晶态氧化硅的硅氢键结合较弱，钝化效果较差，本发明采用晶态氧化硅替换传统的非晶态氧化硅，虽然非晶态氧化硅中的原子分布也具有一定的有序性，但只是短程有序性，而晶态氧化硅中的原子分布具有长程有序性，因此，相比于非晶态氧化硅层，晶态氧化硅层的致密程度更高，钝化效果更好，界面态缺陷密度可以低至10 10cm -2eV -1，提升了PERC电池的综合性能。
需要说明的是，本发明限定的晶态氧化硅是与非晶态氧化硅相对的概念，氧化硅有晶态和非晶态之分，例如水晶(石英)就是一种晶态氧化硅，而硅片上热生长的氧化膜则为非晶态氧化硅，晶态氧化硅中的原子分布具有长程有序性，非晶态氧化硅中的原子分布也具有一定的有序性，但只是短程有序性。
另外，本发明要求保护的背钝化结构是PERC电池中的部分结构，可以理解的是，在此限定的保护范围之内，对PERC电池中的其他结构并未进行具体要求和特殊限定，换言之，在本发明限定的背钝化结构的基础上，本领域技术人员可以基于现有技术对其他结构进行常规替换或创造性改进。
作为本发明一种优选的技术方案，所述的硅基体与第一晶态氧化硅层的接触面处设置有连接块，所述连接块与第一晶态氧化硅层为一体结构，所述的连接块嵌入硅基体内部。
在本发明中，硅基体与第一晶态氧化硅层的接触面处设置有若干个连接块，通过增设连接块来增加硅基体与第一晶态氧化硅层的接触面积，使硅基体与第一晶态氧化硅层更加稳定，保证电池正常使用，也保证电池的使用寿命。
作为本发明一种优选的技术方案，所述的第一晶态氧化硅层与氧化镓层的接触面处设置有第一固定块，所述的第一固定块与氧化镓层为一体结构，所述的第一固定块嵌入第一晶态氧化硅层内部。
在本发明中，第一晶态氧化硅层与氧化镓层的接触面处设置有若干个第一固定块，通过增设第一固定块来增加第一晶态氧化硅层与氧化镓层的接触面积，使第一晶态氧化硅层与氧化镓层更加稳定，保证电池正常使用，也保证电池的使用寿命。
作为本发明一种优选的技术方案，所述的氧化镓层与第二晶态氧化硅层的 接触面处设置有第二固定块，所述的第二固定块与氧化镓层为一体结构，所述的第二固定块嵌入第二晶态氧化硅层内部。
在本发明中，氧化镓层与第二晶态氧化硅层的接触面处设置有若干个第二固定块，通过增设第二固定块来增加氧化镓层与第二晶态氧化硅层的接触面积，使氧化镓层与第二晶态氧化硅层更加稳定，保证电池正常使用，也保证电池的使用寿命。可选地，第一固定块和第二固定块均为梯形截面。
作为本发明一种优选的技术方案，所述的第一晶态氧化硅层的厚度为1～10nm，例如可以是1nm、2nm、3nm、4nm、5nm、6nm、7nm、8nm、9nm或10nm，但并不仅限于所列举的数值，该数值范围内其他未列举的数值同样适用。
作为本发明一种优选的技术方案，所述的氧化镓层的厚度为5～10nm，例如可以是5nm、5.5nm、6nm、6.5nm、7nm、7.5nm、8nm、8.5nm、9nm、9.5nm或10nm，但并不仅限于所列举的数值，该数值范围内其他未列举的数值同样适用。
作为本发明一种优选的技术方案，所述的第二晶态氧化硅层的厚度为1～10nm，例如可以是1nm、2nm、3nm、4nm、5nm、6nm、7nm、8nm、9nm或10nm，但并不仅限于所列举的数值，该数值范围内其他未列举的数值同样适用。
作为本发明一种优选的技术方案，全部背面氮化硅层的总厚度为40～80nm，例如可以是40nm、45nm、50nm、55nm、60nm、65nm、70nm、75nm或80nm，但并不仅限于所列举的数值，该数值范围内其他未列举的数值同样适用。
作为本发明一种优选的技术方案，各层背面氮化硅层的厚度由内至外呈梯度递减。
第五方面，本发明提供了一种包括第四方面所述的PERC电池背钝化结构的PERC电池，所述的PERC电池包括硅基体，所述硅基体的正面依次层叠设置有发射极、正面氧化硅层和正面氮化硅层，所述硅基体的背面设置有第四方面所述的PERC电池背钝化结构。
所述的PERC电池还包括正面电极和背面电极，所述的正面电极由PERC电池的正面垂直插入至硅基体内，所述的背面电极由PERC电池的背面垂直插入至硅基体内。
示例性地，本发明提供了如下制备方法供本领域技术人员参考，但不作为对本发明保护范围的限定：
(1)对单晶硅基体的表面进行制绒处理，形成绒面，制绒后对单晶硅基体进行清洗；
(2)对清洗好的硅基体进行磷扩散，表面生成磷硅玻璃，采用激光掺杂在硅基体正面形成局部重掺区，得到选择性发射极；
(3)通过HF水溶液刻蚀去除硅基体其余表面的磷硅玻璃；
(4)采用热氧化法在选择性发射极表面沉积形成正面氧化硅层；
(5)将硅基体放入成膜腔室内，向成膜腔室内通入笑气和硅烷，采用等离子体增强化学气相沉积法在硅基体背面沉积形成非晶态氧化硅薄膜；
(6)随后在富氢气氛下对硅基体进行退火处理，富氢气氛为氮气和/或惰性气体的混合气体，退火完成后，非晶态氧化硅薄膜转变为第一晶态氧化硅层；
(7)采用ALD在第一晶态氧化硅层表面沉积形成氧化镓层；
(8)重复步骤(5)和步骤(6)，在氧化镓层表面沉积形成第二晶态氧化硅层；
(9)采用PECVD在第二晶态氧化硅层表面沉积形成至少两层背面氮化硅层；
(10)采用PECVD在正面氧化硅层表面沉积形成正面氮化硅层；
(11)通过丝网印刷和烧结在硅片的正面和背面分别形成正面电极和背面电极。
与现有技术相比，本发明的有益效果包括：
(1)本发明提供了一种三明治结构的PERC电池背钝化结构，主要的钝化结构由第一晶态氧化硅层、氧化镓层和第二晶态氧化硅层依次层叠形成，三层膜互补，降低背表面复合速率，增加背表面钝化效果和提高钝化效果。具体而言：第一晶态氧化硅层沉积在硅基体表面用于饱和硅表面的悬挂键，从而降低界面态密度，提供优良的界面化学钝化效应，氧化镓层夹在第一晶态氧化硅层和第二晶态氧化硅层之间，从而形成高浓度的固定负电荷，负电荷对硅基体表面能起到场钝化作用，一步减少数载流子复合，有效降低表面态密度，提升其化学钝化效果。
(2)传统的氧化硅层多采用非晶态氧化硅，但非晶态氧化硅的硅氢键结合较弱，钝化效果较差，本发明采用晶态氧化硅替换传统的非晶态氧化硅，虽然非晶态氧化硅中的原子分布也具有一定的有序性，但只是短程有序性，而晶态氧化硅中的原子分布具有长程有序性，因此，相比于非晶态氧化硅层，晶态氧化硅层的致密程度更高，钝化效果更好，界面态缺陷密度可以低至10 10cm -2eV -1，提升了PERC电池的综合性能。
附图说明
图1为本发明一个具体实施方式提供的PERC电池的结构示意图。
其中，1-正面电极；2-正面氮化硅层；3-正面氧化硅层；4-发射极；5-硅基体；6-晶态氧化硅层；7-氧化铝层；8-背面氮化硅层；9-背面电极。
图2为本发明另一个具体实施方式提供的PERC电池的结构示意图。
其中，11-正面电极；12-正面氮化硅层；13-正面氧化硅层；14-发射极；15-硅基体；16-第一晶态氧化硅层；17-氧化镓层；18-第二晶态氧化硅层；19-背面氮化硅层；110-背面电极；111-连接块；112-第一固定块；113-第二固定块。
具体实施方式
下面结合附图并通过具体实施方式来进一步说明本发明的技术方案。
实施例1
本实施例提供了一种PERC电池的制备方法，所述的制备方法包括如下步骤：
(1)采用NaOH、水和乙醇的混合溶液在70℃下对单晶硅基体5的表面进行制绒处理，形成绒面，NaOH、水和乙醇的体积比为8:240:3；制绒后对单晶硅基体5进行清洗；
(2)对清洗好的硅基体5进行磷扩散，表面生成磷硅玻璃，采用激光掺杂在硅基体5正面形成局部重掺区，得到选择性发射极4；
(3)通过HF水溶液刻蚀去除硅基体5其余表面的磷硅玻璃，HF水溶液中的水和HF的体积比为35:3；
(4)采用热氧化法在选择性发射极4表面沉积形成正面氧化硅层3，其中，氧气流量为1000sccm，沉积压力为100Pa，热氧化温度为600℃，沉积时间为10min；
(5)将硅基体5放入成膜腔室内，向成膜腔室内通入笑气和硅烷，笑气的通入流量为4000sccm，硅烷的通入流量为500sccm；成膜腔室内的压力维持在1400Pa，采用等离子体增强化学气相沉积法在硅基体5背面沉积形成非晶态氧化硅薄膜，等离子体的射频功率为6000W，沉积时间为10s；
(6)随后在富氢气氛下对硅基体5进行退火处理，富氢气氛为氢气和氮气的混合气体，氢气占混合气体总体积的40％，退火温度为850℃，退火时间为1min，退火完成后，非晶态氧化硅薄膜转变为晶态氧化硅层6；
(7)采用ALD在晶态氧化硅表面沉积形成氧化铝层7，氧化铝层7的沉积 工艺参数为：射频功率450W，沉积温度350℃，沉积压力10Pa，TMA流量300sccm，氧气流量400sccm，氮气流量350sccm，沉积时间8s；
(8)采用PECVD在氧化铝层7表面沉积形成背面氮化硅层8，氮化硅的沉积工艺参数为：沉积射频功率9000W，沉积温度450℃，沉积压力300Pa，氨气流量6250sccm，硅烷流量680sccm，沉积时间800s；
(9)采用PECVD在正面氧化硅层3表面沉积形成正面氮化硅层2，氮化硅的沉积工艺参数为：沉积射频功率9000W，沉积温度450℃，沉积压力300Pa，氨气流量6250sccm，硅烷流量680sccm，沉积时间800s；
(10)通过丝网印刷和烧结在硅片的正面和背面分别形成正面电极1和背面电极9。
最终制备得到的PERC电池如图1所示，包括硅基体5，硅基体5的正面依次层叠设置有发射极4、正面氧化硅层3和正面氮化硅层2，正面氧化硅层3的厚度为1nm，正面氮化硅层2的厚度为15nm，正面还设置有正面电极1。硅基体5的背面依次层叠设置有晶态氧化硅层6、氧化铝层7和背面氮化硅层8，晶态氧化硅层6的厚度为5nm，氧化铝层7的厚度为5nm，背面氮化硅层8的厚度为15nm，背面还设置有背面电极9。
实施例2
本实施例提供了一种PERC电池的制备方法，所述的制备方法包括如下步骤：
(1)采用KOH、水和异丙醇的混合溶液在75℃下对单晶硅基体5的表面进行制绒处理，形成绒面，KOH、水和异丙醇的体积比为10:280:2.5；制绒后对单晶硅基体5进行清洗；
(2)对清洗好的硅基体5进行磷扩散，表面生成磷硅玻璃，采用激光掺杂在硅基体5正面形成局部重掺区，得到选择性发射极4；
(3)通过HF水溶液刻蚀去除硅基体5其余表面的磷硅玻璃，HF水溶液中的水和HF的体积比为37:3；
(4)采用热氧化法在选择性发射极4表面沉积形成正面氧化硅层3，其中，氧气流量为1200sccm，沉积压力为140Pa，热氧化温度为620℃，沉积时间为15min；
(5)将硅基体5放入成膜腔室内，向成膜腔室内通入笑气和硅烷，笑气的通入流量为4500sccm，硅烷的通入流量为560sccm；成膜腔室内的压力维持在1450Pa，采用等离子体增强化学气相沉积法在硅基体5背面沉积形成非晶态氧 化硅薄膜，等离子体的射频功率为6800W，沉积时间为50s；
(6)随后在富氢气氛下对硅基体5进行退火处理，富氢气氛为氮气和氩气的混合气体，氢气占混合气体总体积的50％，退火温度为950℃，退火时间为3min，退火完成后，非晶态氧化硅薄膜转变为晶态氧化硅层6；
(7)采用ALD在晶态氧化硅表面沉积形成氧化铝层7，氧化铝层7的沉积工艺参数为：射频功率450W，沉积温度370℃，沉积压力10.4Pa，TMA流量320sccm，氧气流量420sccm，氮气流量360sccm，沉积时间8.5s；
(8)采用PECVD在氧化铝层7表面沉积形成背面氮化硅层8，氮化硅的沉积工艺参数为：沉积射频功率9000W，沉积温度456℃，沉积压力250Pa，氨气流量6250sccm，硅烷流量680sccm，沉积时间830s；
(9)采用PECVD在正面氧化硅层3表面沉积形成氮化硅层，氮化硅的沉积工艺参数为：沉积射频功率9000W，沉积温度456℃，沉积压力250Pa，氨气流量6250sccm，硅烷流量680sccm，沉积时间830s；
(10)通过丝网印刷和烧结在硅片的正面和背面分别形成正面电极1和背面电极9。
最终制备得到的PERC电池包括硅基体5，硅基体5的正面依次层叠设置有发射极4、正面氧化硅层3和正面氮化硅层2，正面氧化硅层3的厚度为3nm，正面氮化硅层2的厚度为50nm，正面还设置有正面电极1。硅基体5的背面依次层叠设置有晶态氧化硅层6、氧化铝层7和背面氮化硅层8，晶态氧化硅层6的厚度为10nm，氧化铝层7的厚度为8nm，氮化硅层的厚度为50nm，背面还设置有背面电极9。
实施例3
本实施例提供了一种PERC电池的制备方法，所述的制备方法包括如下步骤：
(1)采用NaOH、水和乙醇的混合溶液在80℃下对单晶硅基体5的表面进行制绒处理，形成绒面，NaOH、水和乙醇的体积比为10:330:2.2；制绒后对单晶硅基体5进行清洗；
(2)对清洗好的硅基体5进行磷扩散，表面生成磷硅玻璃，采用激光掺杂在硅基体5正面形成局部重掺区，得到选择性发射极4；
(3)通过HF水溶液刻蚀去除硅基体5其余表面的磷硅玻璃，HF水溶液中的水和HF的体积比为40:3；
(4)采用热氧化法在选择性发射极4表面沉积形成正面氧化硅层3，其中， 氧气流量为1400sccm，沉积压力为180Pa，热氧化温度为640℃，沉积时间为20min；
(5)将硅基体5放入成膜腔室内，向成膜腔室内通入笑气和硅烷，笑气的通入流量为5000sccm，硅烷的通入流量为620sccm；成膜腔室内的压力维持在1500Pa，采用等离子体增强化学气相沉积法在硅基体5背面沉积形成非晶态氧化硅薄膜，等离子体的射频功率为7600W，沉积时间为100s；
(6)随后在富氢气氛下对硅基体5进行退火处理，富氢气氛为氮气和氦气的混合气体，氢气占混合气体总体积的60％，退火温度为1050℃，退火时间为5min，退火完成后，非晶态氧化硅薄膜转变为晶态氧化硅层6；
(7)采用ALD在晶态氧化硅表面沉积形成氧化铝层7，氧化铝层7的沉积工艺参数为：射频功率450W，沉积温度400℃，沉积压力10.8Pa，TMA流量340sccm，氧气流量440sccm，氮气流量370sccm，沉积时间9s；
(8)采用PECVD在氧化铝层7表面沉积形成背面氮化硅层8，氮化硅的沉积工艺参数为：沉积射频功率9000W，沉积温度462℃，沉积压力280Pa，氨气流量6250sccm，硅烷流量680sccm，沉积时间860s；
(9)采用PECVD在正面氧化硅层3表面沉积形成氮化硅层，氮化硅的沉积工艺参数为：沉积射频功率9000W，沉积温度462℃，沉积压力280Pa，氨气流量6250sccm，硅烷流量680sccm，沉积时间860s；
(10)通过丝网印刷和烧结在硅片的正面和背面分别形成正面电极1和背面电极9。
最终制备得到的PERC电池包括硅基体5，硅基体5的正面依次层叠设置有发射极4、正面氧化硅层3和正面氮化硅层2，正面氧化硅层3的厚度为2nm，正面氮化硅层2的厚度为80nm，正面还设置有正面电极1。硅基体5的背面依次层叠设置有晶态氧化硅层6、氧化铝层7和背面氮化硅层8，晶态氧化硅层6的厚度为15nm，氧化铝层7的厚度为8nm，氮化硅层的厚度为80nm，背面还设置有背面电极9。
实施例4
本实施例提供了一种PERC电池的制备方法，所述的制备方法包括如下步骤：
(1)采用KOH、水和异丙醇的混合溶液在82℃下对单晶硅基体5的表面进行制绒处理，形成绒面，KOH、水和异丙醇的体积比为11:330:2.5；制绒后对单晶硅基体5进行清洗；
(2)对清洗好的硅基体5进行磷扩散，表面生成磷硅玻璃，采用激光掺杂在硅基体5正面形成局部重掺区，得到选择性发射极4；
(3)通过HF水溶液刻蚀去除硅基体5其余表面的磷硅玻璃，HF水溶液中的水和HF的体积比为42:3；
(4)采用热氧化法在选择性发射极4表面沉积形成正面氧化硅层3，其中，氧气流量为1600sccm，沉积压力为220Pa，热氧化温度为660℃，沉积时间为22min；
(5)将硅基体5放入成膜腔室内，向成膜腔室内通入笑气和硅烷，笑气的通入流量为5300sccm，硅烷的通入流量为680sccm；成膜腔室内的压力维持在1530Pa，采用等离子体增强化学气相沉积法在硅基体5背面沉积形成非晶态氧化硅薄膜，等离子体的射频功率8400W，沉积时间为150s；
(6)随后在富氢气氛下对硅基体5进行退火处理，富氢气氛为氮气和氮气的混合气体，氢气占混合气体总体积的65％，退火温度为1150℃，退火时间为10min，退火完成后，非晶态氧化硅薄膜转变为晶态氧化硅层6；
(7)采用ALD在晶态氧化硅表面沉积形成氧化铝层7，氧化铝层7的沉积工艺参数为：射频功率450W，沉积温度420℃，沉积压力11.2Pa，TMA流量360sccm，氧气流量460sccm，氮气流量380sccm，沉积时间9.3s；
(8)采用PECVD在氧化铝层7表面沉积形成背面氮化硅层8，氮化硅的沉积工艺参数为：沉积射频功率9000W，沉积温度468℃，沉积压力250Pa，氨气流量6250sccm，硅烷流量680sccm，沉积时间890s；
(9)采用PECVD在正面氧化硅层3表面沉积形成氮化硅层，氮化硅的沉积工艺参数为：沉积射频功率9000W，沉积温度468℃，沉积压力250Pa，氨气流量6250sccm，硅烷流量680sccm，沉积时间890s；
(10)通过丝网印刷和烧结在硅片的正面和背面分别形成正面电极1和背面电极9。
最终制备得到的PERC电池包括硅基体5，硅基体5的正面依次层叠设置有发射极4、正面氧化硅层3和正面氮化硅层2，正面氧化硅层3的厚度为4nm，正面氮化硅层2的厚度为100nm，正面还设置有正面电极1。硅基体5的背面依次层叠设置有晶态氧化硅层6、氧化铝层7和背面氮化硅层8，晶态氧化硅层6的厚度为16nm，氧化铝层7的厚度为8nm，背面氮化硅层8的厚度为100nm，背面还设置有背面电极9。
实施例5
本实施例提供了一种PERC电池的制备方法，所述的制备方法包括如下步骤：
(1)采用NaOH、水和乙醇的混合溶液在88℃下对单晶硅基体5的表面进行制绒处理，形成绒面，NaOH、水和乙醇的体积比为11.5:350:2.5；制绒后对单晶硅基体5进行清洗；
(2)对清洗好的硅基体5进行磷扩散，表面生成磷硅玻璃，采用激光掺杂在硅基体5正面形成局部重掺区，得到选择性发射极4；
(3)通过HF水溶液刻蚀去除硅基体5其余表面的磷硅玻璃，HF水溶液中的水和HF的体积比为43:3；
(4)采用热氧化法在选择性发射极4表面沉积形成正面氧化硅层3，其中，氧气流量为1800sccm，沉积压力为260Pa，热氧化温度为680℃，沉积时间为26min；
(5)将硅基体5放入成膜腔室内，向成膜腔室内通入笑气和硅烷，笑气的通入流量为5600sccm，硅烷的通入流量为720sccm；成膜腔室内的压力维持在1560Pa，采用等离子体增强化学气相沉积法在硅基体5背面沉积形成非晶态氧化硅薄膜，等离子体的射频功率为9200W，沉积时间为200s；
(6)随后在富氢气氛下对硅基体5进行退火处理，富氢气氛为氮气和氩气的混合气体，氢气占混合气体总体积的70％，退火温度为1250℃，退火时间为15min，退火完成后，非晶态氧化硅薄膜转变为晶态氧化硅层6；
(7)采用ALD在晶态氧化硅表面沉积形成氧化铝层7，氧化铝层7的沉积工艺参数为：射频功率450W，沉积温度440℃，沉积压力11.6Pa，TMA流量380sccm，氧气流量480sccm，氮气流量390sccm，沉积时间9.6s；
(8)采用PECVD在氧化铝层7表面沉积形成背面氮化硅层8，氮化硅的沉积工艺参数为：沉积射频功率9000W，沉积温度475℃，沉积压力300Pa，氨气流量6250sccm，硅烷流量680sccm，沉积时间920s；
(9)采用PECVD在正面氧化硅层3表面沉积形成氮化硅层，氮化硅的沉积工艺参数为：沉积射频功率9000W，沉积温度475℃，沉积压力300Pa，氨气流量6250sccm，硅烷流量680sccm，沉积时间920s；
(10)通过丝网印刷和烧结在硅片的正面和背面分别形成正面电极1和背面电极9。
最终制备得到的PERC电池包括硅基体5，硅基体5的正面依次层叠设置有发射极4、正面氧化硅层3和正面氮化硅层2，正面氧化硅层3的厚度为3nm， 正面氮化硅层2的厚度为150nm，正面还设置有正面电极1。硅基体5的背面依次层叠设置有晶态氧化硅层6、氧化铝层7和背面氮化硅层8，晶态氧化硅层6的厚度为18nm，氧化铝层7的厚度为10nm，背面氮化硅层8的厚度为18nm，背面还设置有背面电极9。
实施例6
本实施例提供了一种PERC电池的制备方法，所述的制备方法包括如下步骤：
(1)采用KOH、水和异丙醇的混合溶液在90℃下对单晶硅基体5的表面进行制绒处理，形成绒面，KOH、水和异丙醇的体积比为12:360:3；制绒后对单晶硅基体5进行清洗；
(2)对清洗好的硅基体5进行磷扩散，表面生成磷硅玻璃，采用激光掺杂在硅基体5正面形成局部重掺区，得到选择性发射极4；
(3)通过HF水溶液刻蚀去除硅基体5其余表面的磷硅玻璃，HF水溶液中的水和HF的体积比为45:3；
(4)采用热氧化法在选择性发射极4表面沉积形成正面氧化硅层3，其中，氧气流量为2000sccm，沉积压力为300Pa，热氧化温度为700℃，沉积时间为30min；
(5)将硅基体5放入成膜腔室内，向成膜腔室内通入笑气和硅烷，笑气的通入流量为6000sccm，硅烷的通入流量为800sccm；成膜腔室内的压力维持在1600Pa，采用等离子体增强化学气相沉积法在硅基体5背面沉积形成非晶态氧化硅薄膜，等离子体的射频功率为10000W，沉积时间为300s；
(6)随后在富氢气氛下对硅基体5进行退火处理，富氢气氛为氮气和氦气的混合气体，氢气占混合气体总体积的80％，退火温度为1300℃，退火时间为20min，退火完成后，非晶态氧化硅薄膜转变为晶态氧化硅层6；
(7)采用ALD在晶态氧化硅表面沉积形成氧化铝层7，氧化铝层7的沉积工艺参数为：射频功率450W，沉积温度450℃，沉积压力12Pa，TMA流量400sccm，氧气流量500sccm，氮气流量400sccm，沉积时间10s；
(8)采用PECVD在氧化铝层7表面沉积形成背面氮化硅层8，氮化硅的沉积工艺参数为：沉积射频功率9000W，沉积温度480℃，沉积压力200Pa，氨气流量6250sccm，硅烷流量680sccm，沉积时间950s；
(9)采用PECVD在正面氧化硅层3表面沉积形成氮化硅层，氮化硅的沉积工艺参数为：沉积射频功率9000W，沉积温度480℃，沉积压力200Pa，氨气 流量6250sccm，硅烷流量680sccm，沉积时间950s；
(10)通过丝网印刷和烧结在硅片的正面和背面分别形成正面电极1和背面电极9。
最终制备得到的PERC电池包括硅基体5，硅基体5的正面依次层叠设置有发射极4、正面氧化硅层3和正面氮化硅层2，正面氧化硅层3的厚度为5nm，正面氮化硅层2的厚度为200nm，正面还设置有正面电极1。硅基体5的背面依次层叠设置有晶态氧化硅层6、氧化铝层7和背面氮化硅层8，晶态氧化硅层6的厚度为20nm，氧化铝层7的厚度为10nm，背面氮化硅层8的厚度为200nm，背面还设置有背面电极9。
实施例7
本实施例提供了一种PERC电池的制备方法，与实施例3的区别在于，步骤(6)中的退火温度调整为800℃，其他工艺参数及操作步骤与实施例3完全相同。
实施例8
本实施例提供了一种PERC电池的制备方法，与实施例3的区别在于，步骤(6)中的退火温度调整为1400℃，其他工艺参数及操作步骤与实施例3完全相同。
对比例1
本实施例提供了一种PERC电池的制备方法，所述的制备方法包括如下步骤：
(1)采用NaOH、水和乙醇的混合溶液在80℃下对单晶硅基体5的表面进行制绒处理，形成绒面，NaOH、水和乙醇的体积比为10:330:2.2；制绒后对单晶硅基体5进行清洗；
(2)对清洗好的硅基体5进行磷扩散，表面生成磷硅玻璃，采用激光掺杂在硅基体5正面形成局部重掺区，得到选择性发射极4；
(3)通过HF水溶液刻蚀去除硅基体5其余表面的磷硅玻璃，HF水溶液中的水和HF的体积比为40:3；
(4)采用热氧化法在选择性发射极4表面沉积形成正面氧化硅层3，其中，氧气流量为1400sccm，沉积压力为180Pa，热氧化温度为640℃，沉积时间为20min；
(5)采用热氧化法在硅基体5背面沉积形成晶态氧化硅层6，其中，氧气流量为1400sccm，沉积压力为180Pa，热氧化温度为640℃，沉积时间为20min；
(6)采用ALD在晶态氧化硅表面沉积形成氧化铝层7，氧化铝层7的沉积工艺参数为：射频功率450W，沉积温度400℃，沉积压力10.8Pa，TMA流量340sccm，氧气流量440sccm，氮气流量370sccm，沉积时间9s；
(7)采用PECVD在氧化铝层7表面沉积形成背面氮化硅层8，氮化硅的沉积工艺参数为：沉积射频功率9000W，沉积温度462℃，沉积压力280Pa，氨气流量6250sccm，硅烷流量680sccm，沉积时间860s；
(8)采用PECVD在正面氧化硅层3表面沉积形成氮化硅层，氮化硅的沉积工艺参数为：沉积射频功率9000W，沉积温度462℃，沉积压力280Pa，氨气流量6250sccm，硅烷流量680sccm，沉积时间860s；
(9)通过丝网印刷和烧结在硅片的正面和背面分别形成正面电极1和背面电极9。
最终制备得到的PERC电池包括硅基体5，硅基体5的正面依次层叠设置有发射极4、正面氧化硅层3和正面氮化硅层2，正面氧化硅层3的厚度为2nm，正面氮化硅层2的厚度为80nm，正面还设置有正面电极1。硅基体5的背面依次层叠设置有背面氧化硅层、氧化铝层7和背面氮化硅层8，背面氧化硅层的厚度为2nm，氧化铝层7的厚度为8nm，氮化硅层的厚度为80nm，背面还设置有背面电极9。
对比例2
本实施例提供了一种PERC电池的制备方法，所述的制备方法包括如下步骤：
(1)采用NaOH、水和乙醇的混合溶液在80℃下对单晶硅基体5的表面进行制绒处理，形成绒面，NaOH、水和乙醇的体积比为10:330:2.2；制绒后对单晶硅基体5进行清洗；
(2)对清洗好的硅基体5进行磷扩散，表面生成磷硅玻璃，采用激光掺杂在硅基体5正面形成局部重掺区，得到选择性发射极4；
(3)通过HF水溶液刻蚀去除硅基体5其余表面的磷硅玻璃，HF水溶液中的水和HF的体积比为40:3；
(4)采用热氧化法在选择性发射极4表面沉积形成正面氧化硅层3，其中，氧气流量为1400sccm，沉积压力为180Pa，热氧化温度为640℃，沉积时间为20min；
(5)将硅基体5放入成膜腔室内，向成膜腔室内通入笑气和硅烷，笑气的通入流量为5000sccm，硅烷的通入流量为620sccm；成膜腔室内的压力维持在 1500Pa，采用等离子体增强化学气相沉积法在硅基体5背面沉积形成非晶态氧化硅层，等离子体的射频功率为7600W，沉积时间为100s；
(7)采用ALD在非晶态氧化硅层表面沉积形成氧化铝层7，氧化铝层7的沉积工艺参数为：射频功率450W，沉积温度400℃，沉积压力10.8Pa，TMA流量340sccm，氧气流量440sccm，氮气流量370sccm，沉积时间9s；
(8)采用PECVD在氧化铝层7表面沉积形成背面氮化硅层8，氮化硅的沉积工艺参数为：沉积射频功率9000W，沉积温度462℃，沉积压力280Pa，氨气流量6250sccm，硅烷流量680sccm，沉积时间860s；
(9)采用PECVD在正面氧化硅层3表面沉积形成氮化硅层，氮化硅的沉积工艺参数为：沉积射频功率9000W，沉积温度462℃，沉积压力280Pa，氨气流量6250sccm，硅烷流量680sccm，沉积时间860s；
(10)通过丝网印刷和烧结在硅片的正面和背面分别形成正面电极1和背面电极9。
最终制备得到的PERC电池包括硅基体5，硅基体5的正面依次层叠设置有发射极4、正面氧化硅层3和正面氮化硅层2，正面氧化硅层3的厚度为15nm，正面氮化硅层2的厚度为80nm，正面还设置有正面电极1。硅基体5的背面依次层叠设置有晶态氧化硅层6、氧化铝层7和背面氮化硅层8，晶态氧化硅层6的厚度为15nm，氧化铝层7的厚度为8nm，氮化硅层的厚度为80nm，背面还设置有背面电极9。
分别测量实施例1～8和对比例1～2提供的PERC电池的开路电压(Uoc)、短路电流(Isc)、填充因子(FF)、光电转化率(Eta)和界面态缺陷密度(Dit)，其结果如表1所示。需要说明的是，硅基体与钝化层界面处的缺陷密度是衡量钝化效果的关键因素，缺陷密度越低，表明钝化效果越优秀。
表1
  界面态缺陷密度Dit(10 10cm -2eV -1)
实施例1 1.0
实施例2 1.2
实施例3 1.2
实施例4 1.1
实施例5 1.0
实施例6 1.0
实施例7 1.3
实施例8 1.4
对比例1 1.5
对比例2 5.0
表2
序号 Uoc(V) Isc(A) FF(％) Eta(％)
实施例1 0.696 11.195 81.28 23.10
实施例2 0.695 11.196 81.09 23.05
实施例3 0.696 11.196 81.10 23.05
实施例4 0.696 11.197 81.12 23.06
实施例5 0.697 11.198 81.14 23.10
实施例6 0.697 11.196 81.18 23.08
实施例7 0.697 11.198 81.05 23.02
实施例8 0.696 11.197 81.03 23.01
对比例1 0.695 11.197 80.69 22.90
对比例2 0.692 11.196 80.53 22.76
根据实施例3、实施例7、实施例8和对比例1和对比例2并结合表1数据 可以看出如下两点：
(1)实施例3的界面态缺陷密度略低于对比例1，说明实施例3的钝化效果优于对比例1，这是由于对比例1仅采用了热氧化法制备氧化硅，而实施例3则是采用了PECVD和热氧化法联合制备氧化硅，虽然二者制备得到的都是晶态氧化硅，但对比例1制备得到的氧化硅层的厚度远小于实施例3(对比例1中晶态氧化硅层6的厚度为2nm，实施例3中晶态氧化硅层6的厚度为15nm)，因此导致对比例1的钝化效果劣于实施例3。
(2)实施例3的的界面态缺陷密度远低于对比例2，说明实施例3的钝化效果远超对比例2，这是由于实施例3采用PECVD和热氧化法联合制备得到的是晶态氧化硅，而对比例2仅采用PECVD制备得到的是非晶态氧化硅，晶态氧化硅的钝化效果优于非晶态氧化硅。
(3)实施例7和实施例8的数据略小于实施例3，这是由于退火温度过高或过低均影响了制备得到的晶态氧化硅层6的钝化效果。
由此也可以看出，本发明采用PECVD和热氧化法联合制备氧化硅，通过PECVD弥补了热氧化法的厚度缺陷，热氧化法弥补了PECVD的非晶态缺陷，二者结合最终得到了较厚的晶态氧化硅层6。
由表2可以看出，钝化效果的提升也提高了PERC电池的综合性能。
在一个具体实施方式中，本发明提供了一种PERC电池背钝化结构，所述的PERC电池背钝化结构如图2所示，包括由硅基体15的背面依次层叠设置的第一晶态氧化硅层16、氧化镓层17、第二晶态氧化硅层18以及至少两层背面氮化硅层19。第一晶态氧化硅层16的厚度为1～10nm，氧化镓层17的厚度为5～10nm，第二晶态氧化硅层18的厚度为1～10nm，全部背面氮化硅层19的总厚度为40～80nm，各层背面氮化硅层19的厚度由内至外呈梯度递减。
硅基体15与第一晶态氧化硅层16的接触面处设置有连接块111，连接块111与第一晶态氧化硅层16为一体结构，连接块111嵌入硅基体15内部。第一晶态氧化硅层16与氧化镓层17的接触面处设置有第一固定块112，第一固定块112与氧化镓层17为一体结构，第一固定块112嵌入第一晶态氧化硅层16内部。氧化镓层17与第二晶态氧化硅层18的接触面处设置有第二固定块113，第二固定块113与氧化镓层17为一体结构，第二固定块113嵌入第二晶态氧化硅层18内部。
在另一个具体实施方式中，本发明提供了一种PERC电池，所述的PERC电池如图2所示，包括硅基体15，硅基体15的正面依次层叠设置有发射极14、 正面氧化硅层13和正面氮化硅层12，硅基体15的背面设置有如上述具体实施方式提供的PERC电池背钝化结构。
PERC电池还包括正面电极11和背面电极110，所述的正面电极11由PERC电池的正面垂直插入至硅基体15内，所述的背面电极110由PERC电池的背面垂直插入至硅基体15内。
实施例1’
本实施例提供了一种PERC电池，所述的PERC电池基于一个具体实施方式提供的PERC电池，其中，第一晶态氧化硅层16的厚度为1nm，氧化镓层17的厚度为5nm，第二氧化硅层的厚度为1nm，背面氮化硅层19共两层，分别记为第一背面氮化硅层和第二背面氮化硅层，第一背面氮化硅层的厚度为15nm，第二背面氮化硅层的厚度为25nm。
实施例2’
本实施例提供了一种PERC电池，所述的PERC电池基于一个具体实施方式提供的PERC电池，其中，第一晶态氧化硅层16的厚度为3nm，氧化镓层17的厚度为6nm，第二晶态氧化硅层18的厚度为3nm，背面氮化硅层19共两层，分别记为第一背面氮化硅层和第二背面氮化硅层，第一背面氮化硅层的厚度为20nm，第二背面氮化硅层的厚度为30nm。
实施例3’
本实施例提供了一种PERC电池，所述的PERC电池基于一个具体实施方式提供的PERC电池，其中，第一晶态氧化硅层16的厚度为5nm，氧化镓层17的厚度为7nm，第二晶态氧化硅层18的厚度为5nm，背面氮化硅层19共三层，分别记为第一背面氮化硅层、第二背面氮化硅层和第三背面氮化硅层，第一背面氮化硅层的厚度为10nm，第二背面氮化硅层的厚度为20nm，第三背面氮化硅层的厚度为30nm。
实施例4’
本实施例提供了一种PERC电池，所述的PERC电池基于一个具体实施方式提供的PERC电池，其中，第一晶态氧化硅层16的厚度为7nm，氧化镓层17的厚度为8nm，第二晶态氧化硅层18的厚度为7nm，背面氮化硅层19共两层，分别记为第一背面氮化硅层、第二背面氮化硅层和第三背面氮化硅层，第一背面氮化硅层的厚度为15nm，第二背面氮化硅层的厚度为25nm，第三背面氮化硅层的厚度为30nm。
实施例5’
本实施例提供了一种PERC电池，所述的PERC电池基于一个具体实施方式提供的PERC电池，其中，第一晶态氧化硅层16的厚度为9nm，氧化镓层17的厚度为9nm，第二晶态氧化硅层18的厚度为9nm，背面氮化硅层19共四层，分别记为第一背面氮化硅层、第二背面氮化硅层、第三背面氮化硅层和第四背面氮化硅层，第一背面氮化硅层的厚度为5nm，第二背面氮化硅层的厚度为10nm，第三背面氮化硅层的厚度为20nm，第四背面氮化硅层的厚度30nm。
实施例6’
本实施例提供了一种PERC电池，所述的PERC电池基于一个具体实施方式提供的PERC电池，其中，第一晶态氧化硅层16的厚度为10nm，氧化镓层17的厚度为10nm，第二晶态氧化硅层18的厚度为10nm，背面氮化硅层19共四层，分别记为第一背面氮化硅层、第二背面氮化硅层、第三背面氮化硅层和第四背面氮化硅层，第一背面氮化硅层的厚度为10nm，第二背面氮化硅层的厚度为15nm，第三背面氮化硅层的厚度为25nm，第四背面氮化硅层的厚度为30nm。
实施例7’
本实施例提供了一种实施例3 ’所述的PERC电池的制备方法，所述的制备方法包括如下步骤：
(1)采用NaOH、水和乙醇的混合溶液在80℃下对单晶硅基体15的表面进行制绒处理，形成绒面，NaOH、水和乙醇的体积比为10:330:2.2；制绒后对单晶硅基体15进行清洗；
(2)对清洗好的硅基体15进行磷扩散，表面生成磷硅玻璃，采用激光掺杂在硅基体15正面形成局部重掺区，得到选择性发射极14；
(3)通过HF水溶液刻蚀去除硅基体15其余表面的磷硅玻璃，HF水溶液中的水和HF的体积比为40:3；
(4)采用热氧化法在选择性发射极14表面沉积形成正面氧化硅层13；
(5)将硅基体15放入成膜腔室内，向成膜腔室内通入笑气和硅烷，笑气的通入流量为5000sccm，硅烷的通入流量为620sccm；成膜腔室内的压力维持在1500Pa，采用等离子体增强化学气相沉积法在硅基体15背面沉积形成非晶态氧化硅薄膜，等离子体的射频功率为7600W，沉积时间为100s；
(6)随后在富氢气氛下对硅基体15进行退火处理，富氢气氛为氮气和氦气的混合气体，氢气占混合气体总体积的60％，退火温度为1050℃，退火时间为5min，退火完成后，非晶态氧化硅薄膜转变为厚度为5nm的第一晶态氧化硅 层16；
(7)采用ALD在第一晶态氧化硅层16表面沉积形成厚度为7nm的氧化镓层17；
(8)重复步骤(5)和步骤(6)，在氧化镓层17表面沉积形成厚度为5nm的第二晶态氧化硅层18；
(9)采用PECVD在第二晶态氧化硅层18表面依次沉积形成第一背面氮化硅层、第二背面氮化硅层和第三背面氮化硅层；
(10)采用PECVD在正面氧化硅层13表面沉积形成正面氮化硅层12；
(11)通过丝网印刷和烧结在硅片的正面和背面分别形成正面电极11和背面电极110。
申请人声明，以上所述仅为本发明的具体实施方式，但本发明的保护范围并不局限于此，所属技术领域的技术人员应该明了，任何属于本技术领域的技术人员在本发明揭露的技术范围内，可轻易想到的变化或替换，均落在本发明的保护范围和公开范围之内。
申请人声明，以上所述仅为本发明的具体实施方式，但本发明的保护范围并不局限于此。

Claims (20)

  1. 一种PERC电池背钝化结构，其特征在于，所述的PERC电池背钝化结构包括设置于硅基体背面的晶态氧化硅层。
  2. 根据权利要求1所述的PERC电池背钝化结构，其特征在于，所述的晶态氧化硅层的厚度为1～20nm。
  3. 根据权利要求1所述的PERC电池背钝化结构，其特征在于，所述晶态氧化硅层的表面依次层叠设置有氧化铝层和背面氮化硅层；
    所述的氧化铝层的厚度为5～10nm；
    所述的背面氮化硅层的厚度为10～200nm。
  4. 一种权利要求1-3任一项所述的PERC电池背钝化结构的制备方法，其特征在于，所述的制备方法包括：
    硅基体背面沉积形成非晶态氧化硅薄膜，经退火处理后，非晶态氧化硅薄膜转变为晶态氧化硅层。
  5. 根据权利要求4所述的制备方法，其特征在于，所述的非晶态氧化硅薄膜的沉积过程具体包括：
    将硅基体放入成膜腔室内，向成膜腔室内通入笑气和硅烷，维持成膜腔室内的压力，采用等离子体增强化学气相沉积法在硅基体背面沉积形成非晶态氧化硅薄膜。
  6. 根据权利要求5所述的制备方法，其特征在于，所述笑气的通入流量为4000～6000sccm；
    所述硅烷的通入流量为500～800sccm；
    所述成膜腔室内的压力维持在1400～1600Pa；
    所述等离子体的射频功率为6000～10000W；
    所述的沉积时间为10～300s。
  7. 根据权利要求4所述的制备方法，其特征在于，所述的退火过程在富氢气氛下进行；
    所述的富氢气氛为包括氢气的混合气体，所述氢气占混合气体总体积的40～80％；
    所述的混合气体中还包括氮气和/或惰性气体。
  8. 根据权利要求7所述的制备方法，其特征在于，所述的退火温度为850～1300℃；
    所述的退火时间为1～20min。
  9. 根据权利要求4所述的制备方法，其特征在于，所述的制备方法还包括： 在晶态氧化硅层表面依次沉积形成氧化铝层和背面氮化硅层。
  10. 一种包括权利要求1-3任一项所述的PERC电池背钝化结构的PERC电池，其特征在于，所述的PERC电池包括硅基体，所述硅基体的正面依次层叠设置有发射极、正面氧化硅层和正面氮化硅层，所述硅基体的背面设置有权利要求1-3任一项所述的PERC电池背钝化结构；
    所述的PERC电池还包括正面电极和背面电极，所述的正面电极由PERC电池的正面垂直插入至硅基体内，所述的背面电极由PERC电池的背面垂直插入至硅基体内。
  11. 一种PERC电池背钝化结构，其特征在于，所述的PERC电池背钝化结构包括由硅基体的背面依次层叠设置的第一晶态氧化硅层、氧化镓层、第二晶态氧化硅层以及至少两层背面氮化硅层。
  12. 根据权利要求11所述的PERC电池背钝化结构，其特征在于，所述的硅基体与第一晶态氧化硅层的接触面处设置有连接块，所述连接块与第一晶态氧化硅层为一体结构，所述的连接块嵌入硅基体内部。
  13. 根据权利要求11所述的PERC电池背钝化结构，其特征在于，所述的第一晶态氧化硅层与氧化镓层的接触面处设置有第一固定块，所述的第一固定块与氧化镓层为一体结构，所述的第一固定块嵌入第一晶态氧化硅层内部。
  14. 根据权利要求11所述的PERC电池背钝化结构，其特征在于，所述的氧化镓层与第二晶态氧化硅层的接触面处设置有第二固定块，所述的第二固定块与氧化镓层为一体结构，所述的第二固定块嵌入第二晶态氧化硅层内部。
  15. 根据权利要求11所述的PERC电池背钝化结构，其特征在于，所述的第一晶态氧化硅层的厚度为1～10nm。
  16. 根据权利要求11所述的PERC电池背钝化结构，其特征在于，所述的氧化镓层的厚度为5～10nm。
  17. 根据权利要求11所述的PERC电池背钝化结构，其特征在于，所述的第二晶态氧化硅层的厚度为1～10nm。
  18. 根据权利要求11所述的PERC电池背钝化结构，其特征在于，全部背面氮化硅层的总厚度为40～80nm。
  19. 根据权利要求1所述的PERC电池背钝化结构，其特征在于，各层背面氮化硅层的厚度由内至外呈梯度递减。
  20. 一种包括权利要求11-19任一项所述的PERC电池背钝化结构的PERC电池，其特征在于，所述的PERC电池包括硅基体，所述硅基体的正面依次层 叠设置有发射极、正面氧化硅层和正面氮化硅层，所述硅基体的背面设置有权利要求11-19任一项所述的PERC电池背钝化结构；
    所述的PERC电池还包括正面电极和背面电极，所述的正面电极由PERC电池的正面垂直插入至硅基体内，所述的背面电极由PERC电池的背面垂直插入至硅基体内。
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